1 /*
2 ** ###################################################################
3 **     Processors:          MIMX8ML8CVNKZ_dsp
4 **                          MIMX8ML8DVNLZ_dsp
5 **
6 **     Compiler:            XCC Compiler
7 **     Reference manual:    IMX8MPRM, Rev.D, 12/2020
8 **     Version:             rev. 5.0, 2021-03-01
9 **     Build:               b230302
10 **
11 **     Abstract:
12 **         Peripheral Access Layer for MIMX8ML8_dsp
13 **
14 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
15 **     Copyright 2016-2023 NXP
16 **     All rights reserved.
17 **
18 **     SPDX-License-Identifier: BSD-3-Clause
19 **
20 **     http:                 www.nxp.com
21 **     mail:                 support@nxp.com
22 **
23 **     Revisions:
24 **     - rev. 1.0 (2019-10-11)
25 **         Initial version.
26 **     - rev. 2.0 (2020-02-21)
27 **         Rev.B Header.
28 **     - rev. 3.0 (2020-06-22)
29 **         Rev.C Header.
30 **     - rev. 4.0 (2020-11-16)
31 **         Rev.D Header.
32 **     - rev. 5.0 (2021-03-01)
33 **         Rev.D Header Final.
34 **
35 ** ###################################################################
36 */
37 
38 /*!
39  * @file MIMX8ML8_dsp.h
40  * @version 5.0
41  * @date 2021-03-01
42  * @brief Peripheral Access Layer for MIMX8ML8_dsp
43  *
44  * Peripheral Access Layer for MIMX8ML8_dsp
45  */
46 
47 #ifndef _MIMX8ML8_DSP_H_
48 #define _MIMX8ML8_DSP_H_                         /**< Symbol preventing repeated inclusion */
49 
50 /** Memory map major version (memory maps with equal major version number are
51  * compatible) */
52 #define MCU_MEM_MAP_VERSION 0x0500U
53 /** Memory map minor version */
54 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
55 
56 /* ----------------------------------------------------------------------------
57    --
58    ---------------------------------------------------------------------------- */
59 
60 /* IO definitions (access restrictions to peripheral registers) */
61 /**
62     \defgroup CMSIS_glob_defs CMSIS Global Defines
63     <strong>IO Type Qualifiers</strong> are used
64     \li to specify the access to peripheral variables.
65     \li for automatic generation of peripheral register debug information.
66 */
67 #define     __I     volatile const       /*!< Defines 'read only' permissions */
68 #define     __O     volatile             /*!< Defines 'write only' permissions */
69 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
70 
71 /* following defines should be used for structure members */
72 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
73 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
74 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
75 
76 #define __STATIC_INLINE static inline
77 
78 #define __BKPT(value) do {} while(0)
79 #define __NOP() do {} while(0)
80 
81 #include "system_MIMX8ML8_dsp.h"     /* Device specific configuration file */
82 
83 
84 
85 /* ----------------------------------------------------------------------------
86    -- Interrupt vector numbers
87    ---------------------------------------------------------------------------- */
88 
89 /*!
90  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
91  * @{
92  */
93 
94 /** Interrupt Number Definitions */
95 #define NUMBER_OF_INT_VECTORS 182                /**< Number of interrupts in the Vector table */
96 
97 typedef enum IRQn {
98   /* Auxiliary constants */
99   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
100 
101   /* Core interrupts */
102 
103   /* Device specific interrupts */
104   RtosTimer0_IRQn              = 2,                /**< Internal RTOS Timer0 Interrupt. */
105   RtosTimer1_IRQn              = 3,                /**< Internal RTOS Timer1 Interrupt. */
106   MU2_MU3_IRQn                 = 7,                /**< From MU2 and MU3(the two MU instances for communication with the Audio DSP). */
107   Software0_IRQn               = 8,                /**< Software0 triggered Interrupt. */
108   Software1_IRQn               = 9,                /**< Software1 triggered Interrupt. */
109   WriteError_IRQn              = 10,               /**< Write Error Interrupt. */
110   IRQSTEER_0_IRQn              = 19,               /**< External IRQSTEER interrupt 0. */
111   IRQSTEER_1_IRQn              = 20,               /**< External IRQSTEER interrupt 1. */
112   IRQSTEER_2_IRQn              = 21,               /**< External IRQSTEER interrupt 2. */
113   IRQSTEER_3_IRQn              = 22,               /**< External IRQSTEER interrupt 3. */
114   IRQSTEER_4_IRQn              = 23,               /**< External IRQSTEER interrupt 4. */
115   IRQSTEER_5_IRQn              = 24,               /**< External IRQSTEER interrupt 5. */
116   IRQSTEER_6_IRQn              = 25,               /**< External IRQSTEER interrupt 6. */
117   IRQSTEER_7_IRQn              = 26,               /**< External IRQSTEER interrupt 7. */
118   IRQSTEER_8_IRQn              = 27,               /**< External IRQSTEER interrupt 8. */
119   Profiling_IRQn               = 31,               /**< Profiling Interrupt. */
120   DAP_IRQn                     = 33,               /**< DAP Interrupt(IRQSTEER Source 1) */
121   SDMA1_IRQn                   = 34,               /**< AND of all 48 SDMA1 interrupts (events) from all the channels(IRQSTEER Source 2) */
122   GPU3D_IRQn                   = 35,               /**< GPU3D Interrupt(IRQSTEER Source 3) */
123   SNVS_IRQn                    = 36,               /**< ON-OFF button press shorter than 5 seconds (pulse event)(IRQSTEER Source 4) */
124   LCDIF1_IRQn                  = 37,               /**< LCDIF1 Interrupt(IRQSTEER Source 5) */
125   LCDIF2_IRQn                  = 38,               /**< LCDIF2 Interrupt(IRQSTEER Source 6) */
126   VPU_G1_IRQn                  = 39,               /**< VPU G1 Decoder Interrupt(IRQSTEER Source 7) */
127   VPU_G2_IRQn                  = 40,               /**< VPU G2 Decoder Interrupt(IRQSTEER Source 8) */
128   QOS_IRQn                     = 41,               /**< QOS interrupt(IRQSTEER Source 9) */
129   WDOG3_IRQn                   = 42,               /**< Watchdog Timer reset(IRQSTEER Source 10) */
130   HS_CP1_IRQn                  = 43,               /**< HS Interrupt Request(IRQSTEER Source 11) */
131   APBHDMA_IRQn                 = 44,               /**< GPMI operation channel 0-3 description complete interrupt(IRQSTEER Source 12) */
132   ML_IRQn                      = 45,               /**< Machine Learning Processor Interrupt(IRQSTEER Source 13) */
133   BCH_IRQn                     = 46,               /**< BCH operation complete interrupt(IRQSTEER Source 14) */
134   GPMI_IRQn                    = 47,               /**< GPMI operation TIMEOUT ERROR interrupt(IRQSTEER Source 15) */
135   ISI_IRQn                     = 48,               /**< ISI Interrupt(IRQSTEER Source 16) */
136   MIPI_CSI1_IRQn               = 49,               /**< MIPI CSI Interrupt(IRQSTEER Source 17) */
137   MIPI_DSI_IRQn                = 50,               /**< MIPI DSI Interrupt(IRQSTEER Source 18) */
138   SNVS_Consolidated_IRQn       = 51,               /**< SRTC Consolidated Interrupt. Non TZ.(IRQSTEER Source 19) */
139   SNVS_Security_IRQn           = 52,               /**< SRTC Security Interrupt. TZ.(IRQSTEER Source 20) */
140   CSU_IRQn                     = 53,               /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.(IRQSTEER Source 21) */
141   USDHC1_IRQn                  = 54,               /**< uSDHC1 Enhanced SDHC Interrupt Request(IRQSTEER Source 22) */
142   USDHC2_IRQn                  = 55,               /**< uSDHC2 Enhanced SDHC Interrupt Request(IRQSTEER Source 23) */
143   USDHC3_IRQn                  = 56,               /**< uSDHC3 Enhanced SDHC Interrupt Request(IRQSTEER Source 24) */
144   GPU2D_IRQn                   = 57,               /**< GPU2D Interrupt(IRQSTEER Source 25) */
145   UART1_IRQn                   = 58,               /**< UART-1 ORed interrupt(IRQSTEER Source 26) */
146   UART2_IRQn                   = 59,               /**< UART-2 ORed interrupt(IRQSTEER Source 27) */
147   UART3_IRQn                   = 60,               /**< UART-3 ORed interrupt(IRQSTEER Source 28) */
148   UART4_IRQn                   = 61,               /**< UART-4 ORed interrupt(IRQSTEER Source 29) */
149   VPU_IRQn                     = 62,               /**< VPU Encoder Interrupt(IRQSTEER Source 30) */
150   ECSPI1_IRQn                  = 63,               /**< ECSPI1 interrupt request line to the core.(IRQSTEER Source 31) */
151   ECSPI2_IRQn                  = 64,               /**< ECSPI2 interrupt request line to the core.(IRQSTEER Source 32) */
152   ECSPI3_IRQn                  = 65,               /**< ECSPI3 interrupt request line to the core.(IRQSTEER Source 33) */
153   SDMA3_IRQn                   = 66,               /**< AND of all 48 SDMA3 interrupts (events) from all the channels(IRQSTEER Source 34) */
154   I2C1_IRQn                    = 67,               /**< I2C-1 Interrupt(IRQSTEER Source 35) */
155   I2C2_IRQn                    = 68,               /**< I2C-2 Interrupt(IRQSTEER Source 36) */
156   I2C3_IRQn                    = 69,               /**< I2C-3 Interrupt(IRQSTEER Source 37) */
157   I2C4_IRQn                    = 70,               /**< I2C-4 Interrupt(IRQSTEER Source 38) */
158   RDC_IRQn                     = 71,               /**< RDC interrupt(IRQSTEER Source 39) */
159   USB1_IRQn                    = 72,               /**< USB1 Interrupt(IRQSTEER Source 40) */
160   USB2_IRQn                    = 73,               /**< USB2 Interrupt(IRQSTEER Source 41) */
161   ISI_CH1_IRQn                 = 74,               /**< ISI Camera Channel 1 Interrupt(IRQSTEER Source 42) */
162   HDMI_TX_IRQn                 = 75,               /**< HDMI TX Subsystem Interrupt(IRQSTEER Source 43) */
163   PDM_HWVAD_EVENT_IRQn         = 76,               /**< Digital Microphone interface voice activity detector event interrupt(IRQSTEER Source 44) */
164   PDM_HWVAD_ERROR_IRQn         = 77,               /**< Digital Microphone interface voice activity detector error interrupt(IRQSTEER Source 45) */
165   GPT6_IRQn                    = 78,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines(IRQSTEER Source 46) */
166   SCTR_IRQ0_IRQn               = 79,               /**< System Counter Interrupt 0(IRQSTEER Source 47) */
167   SCTR_IRQ1_IRQn               = 80,               /**< System Counter Interrupt 1(IRQSTEER Source 48) */
168   ANAMIX_IRQn                  = 81,               /**< TempSensor (Temperature alarm and criticl alarm).(IRQSTEER Source 49) */
169   I2S3_IRQn                    = 82,               /**< SAI3 Receive / Transmit Interrupt(IRQSTEER Source 50) */
170   GPT5_IRQn                    = 83,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines(IRQSTEER Source 51) */
171   GPT4_IRQn                    = 84,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines(IRQSTEER Source 52) */
172   GPT3_IRQn                    = 85,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines(IRQSTEER Source 53) */
173   GPT2_IRQn                    = 86,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines(IRQSTEER Source 54) */
174   GPT1_IRQn                    = 87,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines(IRQSTEER Source 55) */
175   GPIO1_INT7_IRQn              = 88,               /**< Active HIGH Interrupt from INT7 from GPIO(IRQSTEER Source 56) */
176   GPIO1_INT6_IRQn              = 89,               /**< Active HIGH Interrupt from INT6 from GPIO(IRQSTEER Source 57) */
177   GPIO1_INT5_IRQn              = 90,               /**< Active HIGH Interrupt from INT5 from GPIO(IRQSTEER Source 58) */
178   GPIO1_INT4_IRQn              = 91,               /**< Active HIGH Interrupt from INT4 from GPIO(IRQSTEER Source 59) */
179   GPIO1_INT3_IRQn              = 92,               /**< Active HIGH Interrupt from INT3 from GPIO(IRQSTEER Source 60) */
180   GPIO1_INT2_IRQn              = 93,               /**< Active HIGH Interrupt from INT2 from GPIO(IRQSTEER Source 61) */
181   GPIO1_INT1_IRQn              = 94,               /**< Active HIGH Interrupt from INT1 from GPIO(IRQSTEER Source 62) */
182   GPIO1_INT0_IRQn              = 95,               /**< Active HIGH Interrupt from INT0 from GPIO(IRQSTEER Source 63) */
183   GPIO1_Combined_0_15_IRQn     = 96,               /**< Combined interrupt indication for GPIO1 signal 0 throughout 15(IRQSTEER Source 64) */
184   GPIO1_Combined_16_31_IRQn    = 97,               /**< Combined interrupt indication for GPIO1 signal 16 throughout 31(IRQSTEER Source 65) */
185   GPIO2_Combined_0_15_IRQn     = 98,               /**< Combined interrupt indication for GPIO2 signal 0 throughout 15(IRQSTEER Source 66) */
186   GPIO2_Combined_16_31_IRQn    = 99,               /**< Combined interrupt indication for GPIO2 signal 16 throughout 31(IRQSTEER Source 67) */
187   GPIO3_Combined_0_15_IRQn     = 100,              /**< Combined interrupt indication for GPIO3 signal 0 throughout 15(IRQSTEER Source 68) */
188   GPIO3_Combined_16_31_IRQn    = 101,              /**< Combined interrupt indication for GPIO3 signal 16 throughout 31(IRQSTEER Source 69) */
189   GPIO4_Combined_0_15_IRQn     = 102,              /**< Combined interrupt indication for GPIO4 signal 0 throughout 15(IRQSTEER Source 70) */
190   GPIO4_Combined_16_31_IRQn    = 103,              /**< Combined interrupt indication for GPIO4 signal 16 throughout 31(IRQSTEER Source 71) */
191   GPIO5_Combined_0_15_IRQn     = 104,              /**< Combined interrupt indication for GPIO5 signal 0 throughout 15(IRQSTEER Source 72) */
192   GPIO5_Combined_16_31_IRQn    = 105,              /**< Combined interrupt indication for GPIO5 signal 16 throughout 31(IRQSTEER Source 73) */
193   ISP1_IRQn                    = 106,              /**< ISP 1 ISP Interrupts(IRQSTEER Source 74) */
194   ISP2_IRQn                    = 107,              /**< ISP 2 ISP Interrupts(IRQSTEER Source 75) */
195   I2C5_IRQn                    = 108,              /**< I2C-5 Interrupt(IRQSTEER Source 76) */
196   I2C6_IRQn                    = 109,              /**< I2C-6 Interrupt(IRQSTEER Source 77) */
197   WDOG1_IRQn                   = 110,              /**< Watchdog Timer reset(IRQSTEER Source 78) */
198   WDOG2_IRQn                   = 111,              /**< Watchdog Timer reset(IRQSTEER Source 79) */
199   MIPI_CSI2_IRQn               = 112,              /**< MIPI CSI 2 Interrupt(IRQSTEER Source 80) */
200   PWM1_IRQn                    = 113,              /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.(IRQSTEER Source 81) */
201   PWM2_IRQn                    = 114,              /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.(IRQSTEER Source 82) */
202   PWM3_IRQn                    = 115,              /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.(IRQSTEER Source 83) */
203   PWM4_IRQn                    = 116,              /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.(IRQSTEER Source 84) */
204   CCM_IRQ1_IRQn                = 117,              /**< CCM Interrupt Request 1(IRQSTEER Source 85) */
205   CCM_IRQ2_IRQn                = 118,              /**< CCM Interrupt Request 2(IRQSTEER Source 86) */
206   GPC_IRQn                     = 119,              /**< GPC Interrupt Request 1(IRQSTEER Source 87) */
207   MU1_A53_IRQn                 = 120,              /**< Interrupt to A53 (A53,M7 MU)(IRQSTEER Source 88) */
208   SRC_IRQn                     = 121,              /**< SRC interrupt request(IRQSTEER Source 89) */
209   I2S56_IRQn                   = 122,              /**< SAI5/6 Receive / Transmit Interrupt(IRQSTEER Source 90) */
210   RTIC_IRQn                    = 123,              /**< RTIC Interrupt(IRQSTEER Source 91) */
211   CPU_PerformanceUnit_IRQn     = 124,              /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n](IRQSTEER Source 92) */
212   CPU_CTI_Trigger_IRQn         = 125,              /**< CTI trigger outputs (internal: nCTIIRQ[n](IRQSTEER Source 93) */
213   SRC_Combined_IRQn            = 126,              /**< Combined CPU wdog interrupts (4x) out of SRC.(IRQSTEER Source 94) */
214   I2S1_IRQn                    = 127,              /**< SAI1 Receive / Transmit Interrupt(IRQSTEER Source 95) */
215   I2S2_IRQn                    = 128,              /**< SAI2 Receive / Transmit Interrupt(IRQSTEER Source 96) */
216   MU1_M7_IRQn                  = 129,              /**< Interrupt to M7 (A53, M7 MU)(IRQSTEER Source 97) */
217   DDR_PerformanceMonitor_IRQn  = 130,              /**< ddr Interrupt for performance monitor(IRQSTEER Source 98) */
218   DDR_IRQn                     = 131,              /**< ddr Interrupt(IRQSTEER Source 99) */
219   DEWARP_IRQn                  = 132,              /**< Dewarp Interrupt(IRQSTEER Source 100) */
220   CPU_Error_AXI_IRQn           = 133,              /**< CPU Error indicator for AXI transaction with a write response error condition(IRQSTEER Source 101) */
221   CPU_Error_L2RAM_IRQn         = 134,              /**< CPU Error indicator for L2 RAM double-bit ECC error(IRQSTEER Source 102) */
222   SDMA2_IRQn                   = 135,              /**< AND of all 48 SDMA2 interrupts (events) from all the channels(IRQSTEER Source 103) */
223   SJC_IRQn                     = 136,              /**< Interrupt triggered by SJC register(IRQSTEER Source 104) */
224   CAAM_IRQ0_IRQn               = 137,              /**< CAAM interrupt queue for JQ(IRQSTEER Source 105) */
225   CAAM_IRQ1_IRQn               = 138,              /**< CAAM interrupt queue for JQ(IRQSTEER Source 106) */
226   FlexSPI_IRQn                 = 139,              /**< FlexSPI Interrupt(IRQSTEER Source 107) */
227   TZASC_IRQn                   = 140,              /**< TZASC (PL380) interrupt(IRQSTEER Source 108) */
228   PDM_EVENT_IRQn               = 141,              /**< Digital Microphone interface interrupt(IRQSTEER Source 109) */
229   PDM_ERROR_IRQn               = 142,              /**< Digital Microphone interface error interrupt(IRQSTEER Source 110) */
230   I2S7_IRQn                    = 143,              /**< SAI7 Receive / Transmit Interrupt(IRQSTEER Source 111) */
231   PERFMON1_IRQn                = 144,              /**< General Interrupt(IRQSTEER Source 112) */
232   PERFMON2_IRQn                = 145,              /**< General Interrupt(IRQSTEER Source 113) */
233   CAAM_IRQ2_IRQn               = 146,              /**< CAAM interrupt queue for JQ(IRQSTEER Source 114) */
234   CAAM_ERROR_IRQn              = 147,              /**< Recoverable error interrupt(IRQSTEER Source 115) */
235   HS_CP0_IRQn                  = 148,              /**< HS Interrupt Request(IRQSTEER Source 116) */
236   CM7_CTI_IRQn                 = 149,              /**< CTI trigger outputs from CM7 platform(IRQSTEER Source 117) */
237   ENET1_MAC0_Rx_Tx_Done1_IRQn  = 150,              /**< MAC 0 Receive / Trasmit Frame / Buffer Done(IRQSTEER Source 118) */
238   ENET1_MAC0_Rx_Tx_Done2_IRQn  = 151,              /**< MAC 0 Receive / Trasmit Frame / Buffer Done(IRQSTEER Source 119) */
239   ENET1_IRQn                   = 152,              /**< MAC 0 IRQ(IRQSTEER Source 120) */
240   ENET1_1588_Timer_IRQn        = 153,              /**< MAC 0 1588 Timer Interrupt-synchronous(IRQSTEER Source 121) */
241   ASRC_IRQn                    = 154,              /**< ASRC Interrupt(IRQSTEER Source 122) */
242   PCIE_CTRL1_0_IRQn            = 155,              /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 0(IRQSTEER Source 123) */
243   PCIE_CTRL1_1_IRQn            = 156,              /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 1(IRQSTEER Source 124) */
244   PCIE_CTRL1_2_IRQn            = 157,              /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 2(IRQSTEER Source 125) */
245   PCIE_CTRL1_3_IRQn            = 158,              /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 3(IRQSTEER Source 126) */
246   PCIE_EDMA_IRQn               = 159,              /**< Channels [63:32] interrupts requests(IRQSTEER Source 127) */
247   AUDIO_XCVR0_IRQn             = 160,              /**< eARC Interrupt 0(IRQSTEER Source 128) */
248   AUDIO_XCVR1_IRQn             = 161,              /**< eARC Interrupt 1(IRQSTEER Source 129) */
249   AUD2HTX_IRQn                 = 162,              /**< Audio to HDMI TX Audio Link Master Interrupt(IRQSTEER Source 130) */
250   EDMA1_ERR_IRQn               = 163,              /**< Audio Subsystem eDMA Error Interrupt(IRQSTEER Source 131) */
251   EDMA1_0_15_IRQn              = 164,              /**< Audio Subsystem eDMA Channel Interrupts, Logical OR of channels [15:0](IRQSTEER Source 132) */
252   EDMA1_16_31_IRQn             = 165,              /**< Audio Subsystem eDMA Channel Interrupts, Logical OR of channels [31:16](IRQSTEER Source 133) */
253   ENET_QOS_PMT_IRQn            = 166,              /**< ENET QOS TSN Interrupt from PMT(IRQSTEER Source 134) */
254   ENET_QOS_IRQn                = 167,              /**< ENET QOS TSN LPI RX exit/Host System/RX/TX Channels[4:0] Interrupt(IRQSTEER Source 135) */
255   MU2_A53_IRQn                 = 168,              /**< Interrupt to A53 (A53, Audio Processor MU)(IRQSTEER Source 136) */
256   MU2_AUDIO_IRQn               = 169,              /**< Interrupt to Audio Processor (A53, Audio Processor MU)(IRQSTEER Source 137) */
257   MU3_M7_IRQn                  = 170,              /**< Interrupt to M7 (M7, Audio Processor MU)(IRQSTEER Source 138) */
258   MU3_AUDIO_IRQn               = 171,              /**< Interrupt to Audio Processor (M7, Audio Processor MU)(IRQSTEER Source 139) */
259   PCIE_CTRL1_IRQn              = 172,              /**< RC/EP message transaction Interrupt(IRQSTEER Source 140) */
260   PCIE_CTRL1_ERR_IRQn          = 173,              /**< RC/EP PME Message and Error Interrupt(IRQSTEER Source 141) */
261   CAN_FD1_IRQn                 = 174,              /**< CAN-FD1 Interrupt from bus off/line error/RX warning/TX warning/wakeup/match in PN/timeout in PN/busoff done/FD error(IRQSTEER Source 142) */
262   CAN_FD1_ERROR_IRQn           = 175,              /**< CAN-FD1 Interrupt from correctable error/non correctable error int host/ non correctable error int internal(IRQSTEER Source 143) */
263   CAN_FD2_IRQn                 = 176,              /**< CAN-FD2 Interrupt from bus off/line error/RX warning/TX warning/wakeup/match in PN/timeout in PN/busoff done/FD error(IRQSTEER Source 144) */
264   CAN_FD2_ERROR_IRQn           = 177,              /**< CAN-FD2 Interrupt from correctable error/non correctable error int host/ non correctable error int internal(IRQSTEER Source 145) */
265   AUDIO_XCVR_IRQn              = 178,              /**< eARC PHY - SPDIF wakeup interrupt(IRQSTEER Source 146) */
266   DDR_ERR_IRQn                 = 179,              /**< DRAM Controller Error Interrupt(IRQSTEER Source 147) */
267   USB1_WAKEUP_IRQn             = 180,              /**< USB-1 Wake-up Interrupt(IRQSTEER Source 148) */
268   USB2_WAKEUP_IRQn             = 181               /**< USB-2 Wake-up Interrupt(IRQSTEER Source 149) */
269 } IRQn_Type;
270 
271 /*!
272  * @}
273  */ /* end of group Interrupt_vector_numbers */
274 
275 
276 /* ----------------------------------------------------------------------------
277    -- Mapping Information
278    ---------------------------------------------------------------------------- */
279 
280 /*!
281  * @addtogroup Mapping_Information Mapping Information
282  * @{
283  */
284 
285 /** Mapping Information */
286 /*!
287  * @addtogroup iomuxc_pads
288  * @{ */
289 
290 /*******************************************************************************
291  * Definitions
292 *******************************************************************************/
293 
294 /*!
295  * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
296  *
297  * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
298  */
299 typedef enum _iomuxc_sw_mux_ctl_pad
300 {
301     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U,        /**< IOMUXC SW_MUX_CTL_PAD index */
302     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U,        /**< IOMUXC SW_MUX_CTL_PAD index */
303     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U,        /**< IOMUXC SW_MUX_CTL_PAD index */
304     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U,        /**< IOMUXC SW_MUX_CTL_PAD index */
305     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U,        /**< IOMUXC SW_MUX_CTL_PAD index */
306     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U,        /**< IOMUXC SW_MUX_CTL_PAD index */
307     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U,        /**< IOMUXC SW_MUX_CTL_PAD index */
308     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U,        /**< IOMUXC SW_MUX_CTL_PAD index */
309     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U,        /**< IOMUXC SW_MUX_CTL_PAD index */
310     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U,        /**< IOMUXC SW_MUX_CTL_PAD index */
311     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U,       /**< IOMUXC SW_MUX_CTL_PAD index */
312     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U,       /**< IOMUXC SW_MUX_CTL_PAD index */
313     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U,       /**< IOMUXC SW_MUX_CTL_PAD index */
314     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U,       /**< IOMUXC SW_MUX_CTL_PAD index */
315     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U,       /**< IOMUXC SW_MUX_CTL_PAD index */
316     kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U,       /**< IOMUXC SW_MUX_CTL_PAD index */
317     kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U,         /**< IOMUXC SW_MUX_CTL_PAD index */
318     kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U,        /**< IOMUXC SW_MUX_CTL_PAD index */
319     kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U,         /**< IOMUXC SW_MUX_CTL_PAD index */
320     kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U,         /**< IOMUXC SW_MUX_CTL_PAD index */
321     kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U,         /**< IOMUXC SW_MUX_CTL_PAD index */
322     kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U,         /**< IOMUXC SW_MUX_CTL_PAD index */
323     kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U,      /**< IOMUXC SW_MUX_CTL_PAD index */
324     kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U,         /**< IOMUXC SW_MUX_CTL_PAD index */
325     kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U,      /**< IOMUXC SW_MUX_CTL_PAD index */
326     kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U,         /**< IOMUXC SW_MUX_CTL_PAD index */
327     kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U,         /**< IOMUXC SW_MUX_CTL_PAD index */
328     kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U,         /**< IOMUXC SW_MUX_CTL_PAD index */
329     kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U,         /**< IOMUXC SW_MUX_CTL_PAD index */
330     kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U,         /**< IOMUXC SW_MUX_CTL_PAD index */
331     kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK  = 30U,         /**< IOMUXC SW_MUX_CTL_PAD index */
332     kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD  = 31U,         /**< IOMUXC SW_MUX_CTL_PAD index */
333     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U,        /**< IOMUXC SW_MUX_CTL_PAD index */
334     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U,        /**< IOMUXC SW_MUX_CTL_PAD index */
335     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U,        /**< IOMUXC SW_MUX_CTL_PAD index */
336     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U,        /**< IOMUXC SW_MUX_CTL_PAD index */
337     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U,        /**< IOMUXC SW_MUX_CTL_PAD index */
338     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U,        /**< IOMUXC SW_MUX_CTL_PAD index */
339     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U,        /**< IOMUXC SW_MUX_CTL_PAD index */
340     kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U,        /**< IOMUXC SW_MUX_CTL_PAD index */
341     kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U,      /**< IOMUXC SW_MUX_CTL_PAD index */
342     kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U,       /**< IOMUXC SW_MUX_CTL_PAD index */
343     kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U,         /**< IOMUXC SW_MUX_CTL_PAD index */
344     kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK  = 43U,         /**< IOMUXC SW_MUX_CTL_PAD index */
345     kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD  = 44U,         /**< IOMUXC SW_MUX_CTL_PAD index */
346     kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U,        /**< IOMUXC SW_MUX_CTL_PAD index */
347     kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U,        /**< IOMUXC SW_MUX_CTL_PAD index */
348     kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U,        /**< IOMUXC SW_MUX_CTL_PAD index */
349     kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U,        /**< IOMUXC SW_MUX_CTL_PAD index */
350     kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U,      /**< IOMUXC SW_MUX_CTL_PAD index */
351     kIOMUXC_SW_MUX_CTL_PAD_SD2_WP   = 50U,         /**< IOMUXC SW_MUX_CTL_PAD index */
352     kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U,         /**< IOMUXC SW_MUX_CTL_PAD index */
353     kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U,       /**< IOMUXC SW_MUX_CTL_PAD index */
354     kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U,       /**< IOMUXC SW_MUX_CTL_PAD index */
355     kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U,       /**< IOMUXC SW_MUX_CTL_PAD index */
356     kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U,       /**< IOMUXC SW_MUX_CTL_PAD index */
357     kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U,         /**< IOMUXC SW_MUX_CTL_PAD index */
358     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U,      /**< IOMUXC SW_MUX_CTL_PAD index */
359     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U,      /**< IOMUXC SW_MUX_CTL_PAD index */
360     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U,      /**< IOMUXC SW_MUX_CTL_PAD index */
361     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U,      /**< IOMUXC SW_MUX_CTL_PAD index */
362     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U,      /**< IOMUXC SW_MUX_CTL_PAD index */
363     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U,      /**< IOMUXC SW_MUX_CTL_PAD index */
364     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U,      /**< IOMUXC SW_MUX_CTL_PAD index */
365     kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U,      /**< IOMUXC SW_MUX_CTL_PAD index */
366     kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U,         /**< IOMUXC SW_MUX_CTL_PAD index */
367     kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U,        /**< IOMUXC SW_MUX_CTL_PAD index */
368     kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U,     /**< IOMUXC SW_MUX_CTL_PAD index */
369     kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U,        /**< IOMUXC SW_MUX_CTL_PAD index */
370     kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U,        /**< IOMUXC SW_MUX_CTL_PAD index */
371     kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U,        /**< IOMUXC SW_MUX_CTL_PAD index */
372     kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U,         /**< IOMUXC SW_MUX_CTL_PAD index */
373     kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U,        /**< IOMUXC SW_MUX_CTL_PAD index */
374     kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U,        /**< IOMUXC SW_MUX_CTL_PAD index */
375     kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U,        /**< IOMUXC SW_MUX_CTL_PAD index */
376     kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U,        /**< IOMUXC SW_MUX_CTL_PAD index */
377     kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U,        /**< IOMUXC SW_MUX_CTL_PAD index */
378     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U,        /**< IOMUXC SW_MUX_CTL_PAD index */
379     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U,         /**< IOMUXC SW_MUX_CTL_PAD index */
380     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U,        /**< IOMUXC SW_MUX_CTL_PAD index */
381     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U,        /**< IOMUXC SW_MUX_CTL_PAD index */
382     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U,        /**< IOMUXC SW_MUX_CTL_PAD index */
383     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U,        /**< IOMUXC SW_MUX_CTL_PAD index */
384     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U,        /**< IOMUXC SW_MUX_CTL_PAD index */
385     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U,        /**< IOMUXC SW_MUX_CTL_PAD index */
386     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U,        /**< IOMUXC SW_MUX_CTL_PAD index */
387     kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U,        /**< IOMUXC SW_MUX_CTL_PAD index */
388     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U,        /**< IOMUXC SW_MUX_CTL_PAD index */
389     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U,         /**< IOMUXC SW_MUX_CTL_PAD index */
390     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U,        /**< IOMUXC SW_MUX_CTL_PAD index */
391     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U,        /**< IOMUXC SW_MUX_CTL_PAD index */
392     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U,        /**< IOMUXC SW_MUX_CTL_PAD index */
393     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U,        /**< IOMUXC SW_MUX_CTL_PAD index */
394     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U,        /**< IOMUXC SW_MUX_CTL_PAD index */
395     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U,        /**< IOMUXC SW_MUX_CTL_PAD index */
396     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U,        /**< IOMUXC SW_MUX_CTL_PAD index */
397     kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U,        /**< IOMUXC SW_MUX_CTL_PAD index */
398     kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U,        /**< IOMUXC SW_MUX_CTL_PAD index */
399     kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U,        /**< IOMUXC SW_MUX_CTL_PAD index */
400     kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U,         /**< IOMUXC SW_MUX_CTL_PAD index */
401     kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U,       /**< IOMUXC SW_MUX_CTL_PAD index */
402     kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U,       /**< IOMUXC SW_MUX_CTL_PAD index */
403     kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U,        /**< IOMUXC SW_MUX_CTL_PAD index */
404     kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U,       /**< IOMUXC SW_MUX_CTL_PAD index */
405     kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U,       /**< IOMUXC SW_MUX_CTL_PAD index */
406     kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U,       /**< IOMUXC SW_MUX_CTL_PAD index */
407     kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U,        /**< IOMUXC SW_MUX_CTL_PAD index */
408     kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U,        /**< IOMUXC SW_MUX_CTL_PAD index */
409     kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U,       /**< IOMUXC SW_MUX_CTL_PAD index */
410     kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U,        /**< IOMUXC SW_MUX_CTL_PAD index */
411     kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U,        /**< IOMUXC SW_MUX_CTL_PAD index */
412     kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U,       /**< IOMUXC SW_MUX_CTL_PAD index */
413     kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U,        /**< IOMUXC SW_MUX_CTL_PAD index */
414     kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U,        /**< IOMUXC SW_MUX_CTL_PAD index */
415     kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
416     kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U,     /**< IOMUXC SW_MUX_CTL_PAD index */
417     kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U,     /**< IOMUXC SW_MUX_CTL_PAD index */
418     kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U,     /**< IOMUXC SW_MUX_CTL_PAD index */
419     kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U,      /**< IOMUXC SW_MUX_CTL_PAD index */
420     kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U,     /**< IOMUXC SW_MUX_CTL_PAD index */
421     kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U,     /**< IOMUXC SW_MUX_CTL_PAD index */
422     kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U,     /**< IOMUXC SW_MUX_CTL_PAD index */
423     kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U,      /**< IOMUXC SW_MUX_CTL_PAD index */
424     kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U,        /**< IOMUXC SW_MUX_CTL_PAD index */
425     kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U,        /**< IOMUXC SW_MUX_CTL_PAD index */
426     kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U,        /**< IOMUXC SW_MUX_CTL_PAD index */
427     kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U,        /**< IOMUXC SW_MUX_CTL_PAD index */
428     kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U,        /**< IOMUXC SW_MUX_CTL_PAD index */
429     kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U,        /**< IOMUXC SW_MUX_CTL_PAD index */
430     kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U,        /**< IOMUXC SW_MUX_CTL_PAD index */
431     kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U,        /**< IOMUXC SW_MUX_CTL_PAD index */
432     kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U,       /**< IOMUXC SW_MUX_CTL_PAD index */
433     kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U,       /**< IOMUXC SW_MUX_CTL_PAD index */
434     kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U,       /**< IOMUXC SW_MUX_CTL_PAD index */
435     kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U,       /**< IOMUXC SW_MUX_CTL_PAD index */
436     kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U,       /**< IOMUXC SW_MUX_CTL_PAD index */
437     kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U,       /**< IOMUXC SW_MUX_CTL_PAD index */
438     kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U,       /**< IOMUXC SW_MUX_CTL_PAD index */
439     kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U,       /**< IOMUXC SW_MUX_CTL_PAD index */
440     kIOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SCL = 139U,    /**< IOMUXC SW_MUX_CTL_PAD index */
441     kIOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SDA = 140U,    /**< IOMUXC SW_MUX_CTL_PAD index */
442     kIOMUXC_SW_MUX_CTL_PAD_HDMI_CEC = 141U,        /**< IOMUXC SW_MUX_CTL_PAD index */
443     kIOMUXC_SW_MUX_CTL_PAD_HDMI_HPD = 142U,        /**< IOMUXC SW_MUX_CTL_PAD index */
444 } iomuxc_sw_mux_ctl_pad_t;
445 
446 /*!
447  * @addtogroup iomuxc_pads
448  * @{ */
449 
450 /*******************************************************************************
451  * Definitions
452 *******************************************************************************/
453 
454 /*!
455  * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
456  *
457  * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
458  */
459 typedef enum _iomuxc_sw_pad_ctl_pad
460 {
461     kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 0U,        /**< IOMUXC SW_PAD_CTL_PAD index */
462     kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 1U,        /**< IOMUXC SW_PAD_CTL_PAD index */
463     kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 = 2U,        /**< IOMUXC SW_PAD_CTL_PAD index */
464     kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 = 3U,        /**< IOMUXC SW_PAD_CTL_PAD index */
465     kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 4U,          /**< IOMUXC SW_PAD_CTL_PAD index */
466     kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U,          /**< IOMUXC SW_PAD_CTL_PAD index */
467     kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U,          /**< IOMUXC SW_PAD_CTL_PAD index */
468     kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U,          /**< IOMUXC SW_PAD_CTL_PAD index */
469     kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U,          /**< IOMUXC SW_PAD_CTL_PAD index */
470     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 9U,        /**< IOMUXC SW_PAD_CTL_PAD index */
471     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 10U,       /**< IOMUXC SW_PAD_CTL_PAD index */
472     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 11U,       /**< IOMUXC SW_PAD_CTL_PAD index */
473     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 12U,       /**< IOMUXC SW_PAD_CTL_PAD index */
474     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 13U,       /**< IOMUXC SW_PAD_CTL_PAD index */
475     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 14U,       /**< IOMUXC SW_PAD_CTL_PAD index */
476     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 15U,       /**< IOMUXC SW_PAD_CTL_PAD index */
477     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 16U,       /**< IOMUXC SW_PAD_CTL_PAD index */
478     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 17U,       /**< IOMUXC SW_PAD_CTL_PAD index */
479     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 18U,       /**< IOMUXC SW_PAD_CTL_PAD index */
480     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 19U,       /**< IOMUXC SW_PAD_CTL_PAD index */
481     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 20U,       /**< IOMUXC SW_PAD_CTL_PAD index */
482     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 21U,       /**< IOMUXC SW_PAD_CTL_PAD index */
483     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 22U,       /**< IOMUXC SW_PAD_CTL_PAD index */
484     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 23U,       /**< IOMUXC SW_PAD_CTL_PAD index */
485     kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 24U,       /**< IOMUXC SW_PAD_CTL_PAD index */
486     kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 25U,         /**< IOMUXC SW_PAD_CTL_PAD index */
487     kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 26U,        /**< IOMUXC SW_PAD_CTL_PAD index */
488     kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 27U,         /**< IOMUXC SW_PAD_CTL_PAD index */
489     kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 28U,         /**< IOMUXC SW_PAD_CTL_PAD index */
490     kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 29U,         /**< IOMUXC SW_PAD_CTL_PAD index */
491     kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 30U,         /**< IOMUXC SW_PAD_CTL_PAD index */
492     kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 31U,      /**< IOMUXC SW_PAD_CTL_PAD index */
493     kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 32U,         /**< IOMUXC SW_PAD_CTL_PAD index */
494     kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 33U,      /**< IOMUXC SW_PAD_CTL_PAD index */
495     kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 34U,         /**< IOMUXC SW_PAD_CTL_PAD index */
496     kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 35U,         /**< IOMUXC SW_PAD_CTL_PAD index */
497     kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 36U,         /**< IOMUXC SW_PAD_CTL_PAD index */
498     kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 37U,         /**< IOMUXC SW_PAD_CTL_PAD index */
499     kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 38U,         /**< IOMUXC SW_PAD_CTL_PAD index */
500     kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK  = 39U,         /**< IOMUXC SW_PAD_CTL_PAD index */
501     kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD  = 40U,         /**< IOMUXC SW_PAD_CTL_PAD index */
502     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 41U,        /**< IOMUXC SW_PAD_CTL_PAD index */
503     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 42U,        /**< IOMUXC SW_PAD_CTL_PAD index */
504     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 43U,        /**< IOMUXC SW_PAD_CTL_PAD index */
505     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 44U,        /**< IOMUXC SW_PAD_CTL_PAD index */
506     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 45U,        /**< IOMUXC SW_PAD_CTL_PAD index */
507     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 46U,        /**< IOMUXC SW_PAD_CTL_PAD index */
508     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 47U,        /**< IOMUXC SW_PAD_CTL_PAD index */
509     kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 48U,        /**< IOMUXC SW_PAD_CTL_PAD index */
510     kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 49U,      /**< IOMUXC SW_PAD_CTL_PAD index */
511     kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 50U,       /**< IOMUXC SW_PAD_CTL_PAD index */
512     kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 51U,         /**< IOMUXC SW_PAD_CTL_PAD index */
513     kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK  = 52U,         /**< IOMUXC SW_PAD_CTL_PAD index */
514     kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD  = 53U,         /**< IOMUXC SW_PAD_CTL_PAD index */
515     kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 54U,        /**< IOMUXC SW_PAD_CTL_PAD index */
516     kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 55U,        /**< IOMUXC SW_PAD_CTL_PAD index */
517     kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 56U,        /**< IOMUXC SW_PAD_CTL_PAD index */
518     kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 57U,        /**< IOMUXC SW_PAD_CTL_PAD index */
519     kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 58U,      /**< IOMUXC SW_PAD_CTL_PAD index */
520     kIOMUXC_SW_PAD_CTL_PAD_SD2_WP   = 59U,         /**< IOMUXC SW_PAD_CTL_PAD index */
521     kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 60U,         /**< IOMUXC SW_PAD_CTL_PAD index */
522     kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 61U,       /**< IOMUXC SW_PAD_CTL_PAD index */
523     kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 62U,       /**< IOMUXC SW_PAD_CTL_PAD index */
524     kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 63U,       /**< IOMUXC SW_PAD_CTL_PAD index */
525     kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 64U,       /**< IOMUXC SW_PAD_CTL_PAD index */
526     kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 65U,         /**< IOMUXC SW_PAD_CTL_PAD index */
527     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 66U,      /**< IOMUXC SW_PAD_CTL_PAD index */
528     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 67U,      /**< IOMUXC SW_PAD_CTL_PAD index */
529     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 68U,      /**< IOMUXC SW_PAD_CTL_PAD index */
530     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 69U,      /**< IOMUXC SW_PAD_CTL_PAD index */
531     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 70U,      /**< IOMUXC SW_PAD_CTL_PAD index */
532     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 71U,      /**< IOMUXC SW_PAD_CTL_PAD index */
533     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 72U,      /**< IOMUXC SW_PAD_CTL_PAD index */
534     kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 73U,      /**< IOMUXC SW_PAD_CTL_PAD index */
535     kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 74U,         /**< IOMUXC SW_PAD_CTL_PAD index */
536     kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 75U,        /**< IOMUXC SW_PAD_CTL_PAD index */
537     kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 76U,     /**< IOMUXC SW_PAD_CTL_PAD index */
538     kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 77U,        /**< IOMUXC SW_PAD_CTL_PAD index */
539     kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 78U,        /**< IOMUXC SW_PAD_CTL_PAD index */
540     kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 79U,        /**< IOMUXC SW_PAD_CTL_PAD index */
541     kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 80U,         /**< IOMUXC SW_PAD_CTL_PAD index */
542     kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 81U,        /**< IOMUXC SW_PAD_CTL_PAD index */
543     kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 82U,        /**< IOMUXC SW_PAD_CTL_PAD index */
544     kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 83U,        /**< IOMUXC SW_PAD_CTL_PAD index */
545     kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 84U,        /**< IOMUXC SW_PAD_CTL_PAD index */
546     kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 85U,        /**< IOMUXC SW_PAD_CTL_PAD index */
547     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 86U,        /**< IOMUXC SW_PAD_CTL_PAD index */
548     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 87U,         /**< IOMUXC SW_PAD_CTL_PAD index */
549     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 88U,        /**< IOMUXC SW_PAD_CTL_PAD index */
550     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 89U,        /**< IOMUXC SW_PAD_CTL_PAD index */
551     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 90U,        /**< IOMUXC SW_PAD_CTL_PAD index */
552     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 91U,        /**< IOMUXC SW_PAD_CTL_PAD index */
553     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 92U,        /**< IOMUXC SW_PAD_CTL_PAD index */
554     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 93U,        /**< IOMUXC SW_PAD_CTL_PAD index */
555     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 94U,        /**< IOMUXC SW_PAD_CTL_PAD index */
556     kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 95U,        /**< IOMUXC SW_PAD_CTL_PAD index */
557     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 96U,        /**< IOMUXC SW_PAD_CTL_PAD index */
558     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 97U,         /**< IOMUXC SW_PAD_CTL_PAD index */
559     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 98U,        /**< IOMUXC SW_PAD_CTL_PAD index */
560     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 99U,        /**< IOMUXC SW_PAD_CTL_PAD index */
561     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 100U,       /**< IOMUXC SW_PAD_CTL_PAD index */
562     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 101U,       /**< IOMUXC SW_PAD_CTL_PAD index */
563     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 102U,       /**< IOMUXC SW_PAD_CTL_PAD index */
564     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 103U,       /**< IOMUXC SW_PAD_CTL_PAD index */
565     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 104U,       /**< IOMUXC SW_PAD_CTL_PAD index */
566     kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 105U,       /**< IOMUXC SW_PAD_CTL_PAD index */
567     kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 106U,       /**< IOMUXC SW_PAD_CTL_PAD index */
568     kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 107U,       /**< IOMUXC SW_PAD_CTL_PAD index */
569     kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 108U,        /**< IOMUXC SW_PAD_CTL_PAD index */
570     kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 109U,       /**< IOMUXC SW_PAD_CTL_PAD index */
571     kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 110U,       /**< IOMUXC SW_PAD_CTL_PAD index */
572     kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 111U,        /**< IOMUXC SW_PAD_CTL_PAD index */
573     kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 112U,       /**< IOMUXC SW_PAD_CTL_PAD index */
574     kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 113U,       /**< IOMUXC SW_PAD_CTL_PAD index */
575     kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 114U,       /**< IOMUXC SW_PAD_CTL_PAD index */
576     kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 115U,        /**< IOMUXC SW_PAD_CTL_PAD index */
577     kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 116U,        /**< IOMUXC SW_PAD_CTL_PAD index */
578     kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 117U,       /**< IOMUXC SW_PAD_CTL_PAD index */
579     kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 118U,        /**< IOMUXC SW_PAD_CTL_PAD index */
580     kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 119U,        /**< IOMUXC SW_PAD_CTL_PAD index */
581     kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 120U,       /**< IOMUXC SW_PAD_CTL_PAD index */
582     kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 121U,        /**< IOMUXC SW_PAD_CTL_PAD index */
583     kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 122U,        /**< IOMUXC SW_PAD_CTL_PAD index */
584     kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 123U,   /**< IOMUXC SW_PAD_CTL_PAD index */
585     kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 124U,     /**< IOMUXC SW_PAD_CTL_PAD index */
586     kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 125U,     /**< IOMUXC SW_PAD_CTL_PAD index */
587     kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 126U,     /**< IOMUXC SW_PAD_CTL_PAD index */
588     kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 127U,      /**< IOMUXC SW_PAD_CTL_PAD index */
589     kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 128U,     /**< IOMUXC SW_PAD_CTL_PAD index */
590     kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 129U,     /**< IOMUXC SW_PAD_CTL_PAD index */
591     kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 130U,     /**< IOMUXC SW_PAD_CTL_PAD index */
592     kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 131U,      /**< IOMUXC SW_PAD_CTL_PAD index */
593     kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 132U,        /**< IOMUXC SW_PAD_CTL_PAD index */
594     kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 133U,        /**< IOMUXC SW_PAD_CTL_PAD index */
595     kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 134U,        /**< IOMUXC SW_PAD_CTL_PAD index */
596     kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 135U,        /**< IOMUXC SW_PAD_CTL_PAD index */
597     kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 136U,        /**< IOMUXC SW_PAD_CTL_PAD index */
598     kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 137U,        /**< IOMUXC SW_PAD_CTL_PAD index */
599     kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 138U,        /**< IOMUXC SW_PAD_CTL_PAD index */
600     kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 139U,        /**< IOMUXC SW_PAD_CTL_PAD index */
601     kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 140U,       /**< IOMUXC SW_PAD_CTL_PAD index */
602     kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 141U,       /**< IOMUXC SW_PAD_CTL_PAD index */
603     kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 142U,       /**< IOMUXC SW_PAD_CTL_PAD index */
604     kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 143U,       /**< IOMUXC SW_PAD_CTL_PAD index */
605     kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 144U,       /**< IOMUXC SW_PAD_CTL_PAD index */
606     kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 145U,       /**< IOMUXC SW_PAD_CTL_PAD index */
607     kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 146U,       /**< IOMUXC SW_PAD_CTL_PAD index */
608     kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 147U,       /**< IOMUXC SW_PAD_CTL_PAD index */
609     kIOMUXC_SW_PAD_CTL_PAD_HDMI_DDC_SCL = 148U,    /**< IOMUXC SW_PAD_CTL_PAD index */
610     kIOMUXC_SW_PAD_CTL_PAD_HDMI_DDC_SDA = 149U,    /**< IOMUXC SW_PAD_CTL_PAD index */
611     kIOMUXC_SW_PAD_CTL_PAD_HDMI_CEC = 150U,        /**< IOMUXC SW_PAD_CTL_PAD index */
612     kIOMUXC_SW_PAD_CTL_PAD_HDMI_HPD = 151U,        /**< IOMUXC SW_PAD_CTL_PAD index */
613     kIOMUXC_SW_PAD_CTL_PAD_CLKIN1   = 152U,        /**< IOMUXC SW_PAD_CTL_PAD index */
614     kIOMUXC_SW_PAD_CTL_PAD_CLKIN2   = 153U,        /**< IOMUXC SW_PAD_CTL_PAD index */
615     kIOMUXC_SW_PAD_CTL_PAD_CLKOUT1  = 154U,        /**< IOMUXC SW_PAD_CTL_PAD index */
616     kIOMUXC_SW_PAD_CTL_PAD_CLKOUT2  = 155U,        /**< IOMUXC SW_PAD_CTL_PAD index */
617 } iomuxc_sw_pad_ctl_pad_t;
618 
619 /* @} */
620 
621 /*!
622  * @brief Enumeration for the IOMUXC select input
623  *
624  * Defines the enumeration for the IOMUXC select input collections.
625  */
626 typedef enum _iomuxc_select_input
627 {
628     kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 0U, /**< IOMUXC select input index */
629     kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 1U, /**< IOMUXC select input index */
630     kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 2U, /**< IOMUXC select input index */
631     kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 3U, /**< IOMUXC select input index */
632     kIOMUXC_AUDIOMIX_SAI1_RXSYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */
633     kIOMUXC_AUDIOMIX_SAI1_TXBCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
634     kIOMUXC_AUDIOMIX_SAI1_TXSYNC_SELECT_INPUT = 6U, /**< IOMUXC select input index */
635     kIOMUXC_AUDIOMIX_SAI2_RXDATA_SELECT_INPUT_1 = 7U, /**< IOMUXC select input index */
636     kIOMUXC_AUDIOMIX_SAI3_MCLK_SELECT_INPUT = 8U,  /**< IOMUXC select input index */
637     kIOMUXC_AUDIOMIX_SAI3_RXDATA_SELECT_INPUT_0 = 9U, /**< IOMUXC select input index */
638     kIOMUXC_AUDIOMIX_SAI3_TXBCLK_SELECT_INPUT = 10U, /**< IOMUXC select input index */
639     kIOMUXC_AUDIOMIX_SAI3_TXSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
640     kIOMUXC_AUDIOMIX_SAI5_MCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
641     kIOMUXC_AUDIOMIX_SAI5_RXBCLK_SELECT_INPUT = 13U, /**< IOMUXC select input index */
642     kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_0 = 14U, /**< IOMUXC select input index */
643     kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_1 = 15U, /**< IOMUXC select input index */
644     kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_2 = 16U, /**< IOMUXC select input index */
645     kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_3 = 17U, /**< IOMUXC select input index */
646     kIOMUXC_AUDIOMIX_SAI5_RXSYNC_SELECT_INPUT = 18U, /**< IOMUXC select input index */
647     kIOMUXC_AUDIOMIX_SAI5_TXBCLK_SELECT_INPUT = 19U, /**< IOMUXC select input index */
648     kIOMUXC_AUDIOMIX_SAI5_TXSYNC_SELECT_INPUT = 20U, /**< IOMUXC select input index */
649     kIOMUXC_AUDIOMIX_SAI6_MCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
650     kIOMUXC_AUDIOMIX_SAI6_RXBCLK_SELECT_INPUT = 22U, /**< IOMUXC select input index */
651     kIOMUXC_AUDIOMIX_SAI6_RXDATA_SELECT_INPUT_0 = 23U, /**< IOMUXC select input index */
652     kIOMUXC_AUDIOMIX_SAI6_RXSYNC_SELECT_INPUT = 24U, /**< IOMUXC select input index */
653     kIOMUXC_AUDIOMIX_SAI6_TXBCLK_SELECT_INPUT = 25U, /**< IOMUXC select input index */
654     kIOMUXC_AUDIOMIX_SAI6_TXSYNC_SELECT_INPUT = 26U, /**< IOMUXC select input index */
655     kIOMUXC_AUDIOMIX_SAI7_MCLK_SELECT_INPUT = 27U, /**< IOMUXC select input index */
656     kIOMUXC_AUDIOMIX_SAI7_RXBCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */
657     kIOMUXC_AUDIOMIX_SAI7_RXDATA_SELECT_INPUT_0 = 29U, /**< IOMUXC select input index */
658     kIOMUXC_AUDIOMIX_SAI7_RXSYNC_SELECT_INPUT = 30U, /**< IOMUXC select input index */
659     kIOMUXC_AUDIOMIX_SAI7_TXBCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */
660     kIOMUXC_AUDIOMIX_SAI7_TXSYNC_SELECT_INPUT = 32U, /**< IOMUXC select input index */
661     kIOMUXC_AUDIOMIX_EARC_PHY_SPDIF_IN_SELECT_INPUT = 33U, /**< IOMUXC select input index */
662     kIOMUXC_AUDIOMIX_SPDIF_EXTCLK_SELECT_INPUT = 34U, /**< IOMUXC select input index */
663     kIOMUXC_CAN1_CANRX_SELECT_INPUT = 35U,         /**< IOMUXC select input index */
664     kIOMUXC_CAN2_CANRX_SELECT_INPUT = 36U,         /**< IOMUXC select input index */
665     kIOMUXC_CCM_GPC_PMIC_VFUNCTIONAL_READY_SELECT_INPUT = 37U, /**< IOMUXC select input index */
666     kIOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT = 38U, /**< IOMUXC select input index */
667     kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 39U,        /**< IOMUXC select input index */
668     kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 40U,        /**< IOMUXC select input index */
669     kIOMUXC_ECSPI1_SS_B_SELECT_INPUT_0 = 41U,      /**< IOMUXC select input index */
670     kIOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT = 42U, /**< IOMUXC select input index */
671     kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 43U,        /**< IOMUXC select input index */
672     kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 44U,        /**< IOMUXC select input index */
673     kIOMUXC_ECSPI2_SS_B_SELECT_INPUT_0 = 45U,      /**< IOMUXC select input index */
674     kIOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 46U, /**< IOMUXC select input index */
675     kIOMUXC_ENET1_MDIO_SELECT_INPUT = 47U,         /**< IOMUXC select input index */
676     kIOMUXC_ENET1_RXDATA_0_SELECT_INPUT = 48U,     /**< IOMUXC select input index */
677     kIOMUXC_ENET1_RXDATA_1_SELECT_INPUT = 49U,     /**< IOMUXC select input index */
678     kIOMUXC_ENET1_RXEN_SELECT_INPUT = 50U,         /**< IOMUXC select input index */
679     kIOMUXC_ENET1_RXERR_SELECT_INPUT = 51U,        /**< IOMUXC select input index */
680     kIOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT = 52U, /**< IOMUXC select input index */
681     kIOMUXC_GPT1_CAPIN1_SELECT_INPUT = 53U,        /**< IOMUXC select input index */
682     kIOMUXC_GPT1_CAPIN2_SELECT_INPUT = 54U,        /**< IOMUXC select input index */
683     kIOMUXC_GPT1_CLKIN_SELECT_INPUT = 55U,         /**< IOMUXC select input index */
684     kIOMUXC_PCIE_CLKREQ_B_SELECT_INPUT = 56U,      /**< IOMUXC select input index */
685     kIOMUXC_I2C1_SCL_IN_SELECT_INPUT = 57U,        /**< IOMUXC select input index */
686     kIOMUXC_I2C1_SDA_IN_SELECT_INPUT = 58U,        /**< IOMUXC select input index */
687     kIOMUXC_I2C2_SCL_IN_SELECT_INPUT = 59U,        /**< IOMUXC select input index */
688     kIOMUXC_I2C2_SDA_IN_SELECT_INPUT = 60U,        /**< IOMUXC select input index */
689     kIOMUXC_I2C3_SCL_IN_SELECT_INPUT = 61U,        /**< IOMUXC select input index */
690     kIOMUXC_I2C3_SDA_IN_SELECT_INPUT = 62U,        /**< IOMUXC select input index */
691     kIOMUXC_I2C4_SCL_IN_SELECT_INPUT = 63U,        /**< IOMUXC select input index */
692     kIOMUXC_I2C4_SDA_IN_SELECT_INPUT = 64U,        /**< IOMUXC select input index */
693     kIOMUXC_I2C5_SCL_IN_SELECT_INPUT = 65U,        /**< IOMUXC select input index */
694     kIOMUXC_I2C5_SDA_IN_SELECT_INPUT = 66U,        /**< IOMUXC select input index */
695     kIOMUXC_I2C6_SCL_IN_SELECT_INPUT = 67U,        /**< IOMUXC select input index */
696     kIOMUXC_I2C6_SDA_IN_SELECT_INPUT = 68U,        /**< IOMUXC select input index */
697     kIOMUXC_ISP_FL_TRIG_0_SELECT_INPUT = 69U,      /**< IOMUXC select input index */
698     kIOMUXC_ISP_FL_TRIG_1_SELECT_INPUT = 70U,      /**< IOMUXC select input index */
699     kIOMUXC_ISP_SHUTTER_TRIG_0_SELECT_INPUT = 71U, /**< IOMUXC select input index */
700     kIOMUXC_ISP_SHUTTER_TRIG_1_SELECT_INPUT = 72U, /**< IOMUXC select input index */
701     kIOMUXC_UART1_UART_RTS_B_SELECT_INPUT = 73U,   /**< IOMUXC select input index */
702     kIOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT = 74U, /**< IOMUXC select input index */
703     kIOMUXC_UART2_UART_RTS_B_SELECT_INPUT = 75U,   /**< IOMUXC select input index */
704     kIOMUXC_UART2_UART_RXD_MUX_SELECT_INPUT = 76U, /**< IOMUXC select input index */
705     kIOMUXC_UART3_UART_RTS_B_SELECT_INPUT = 77U,   /**< IOMUXC select input index */
706     kIOMUXC_UART3_UART_RXD_MUX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
707     kIOMUXC_UART4_UART_RTS_B_SELECT_INPUT = 79U,   /**< IOMUXC select input index */
708     kIOMUXC_UART4_UART_RXD_MUX_SELECT_INPUT = 80U, /**< IOMUXC select input index */
709     kIOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT = 81U, /**< IOMUXC select input index */
710     kIOMUXC_USDHC3_CARD_DET_SELECT_INPUT = 82U,    /**< IOMUXC select input index */
711     kIOMUXC_USDHC3_CMD_IN_SELECT_INPUT = 83U,      /**< IOMUXC select input index */
712     kIOMUXC_USDHC3_DAT0_IN_SELECT_INPUT = 84U,     /**< IOMUXC select input index */
713     kIOMUXC_USDHC3_DAT1_IN_SELECT_INPUT = 85U,     /**< IOMUXC select input index */
714     kIOMUXC_USDHC3_DAT2_IN_SELECT_INPUT = 86U,     /**< IOMUXC select input index */
715     kIOMUXC_USDHC3_DAT3_IN_SELECT_INPUT = 87U,     /**< IOMUXC select input index */
716     kIOMUXC_USDHC3_DAT4_IN_SELECT_INPUT = 88U,     /**< IOMUXC select input index */
717     kIOMUXC_USDHC3_DAT5_IN_SELECT_INPUT = 89U,     /**< IOMUXC select input index */
718     kIOMUXC_USDHC3_DAT6_IN_SELECT_INPUT = 90U,     /**< IOMUXC select input index */
719     kIOMUXC_USDHC3_DAT7_IN_SELECT_INPUT = 91U,     /**< IOMUXC select input index */
720     kIOMUXC_USDHC3_STROBE_SELECT_INPUT = 92U,      /**< IOMUXC select input index */
721     kIOMUXC_USDHC3_WP_ON_SELECT_INPUT = 93U,       /**< IOMUXC select input index */
722 } iomuxc_select_input_t;
723 
724 /*!
725  * @addtogroup rdc_mapping
726  * @{
727  */
728 
729 /*******************************************************************************
730  * Definitions
731  ******************************************************************************/
732 
733 /*!
734  * @brief Structure for the RDC mapping
735  *
736  * Defines the structure for the RDC resource collections.
737  */
738 
739 typedef enum _rdc_master
740 {
741     kRDC_Master_A53                 = 0U,          /**< ARM Cortex-A53 RDC Master */
742     kRDC_Master_M7                  = 1U,          /**< ARM Cortex-M7 RDC Master */
743     kRDC_PCIE_CTRL1                 = 2U,          /**< Reserved */
744     kRDC_Master_SDMA3_PERIPH        = 3U,          /**< SDMA3 PERIPHERAL RDC Master */
745     kRDC_Master_SDMA3_BURST         = 4U,          /**< SDMA3 BURST RDC Master */
746     kRDC_Master_LCDIF1              = 5U,          /**< LCDIF1 RDC Master */
747     kRDC_Master_ISI                 = 6U,          /**< ISI PORT RDC Master */
748     kRDC_Master_NPU                 = 7U,          /**< NPU RDC Master */
749     kRDC_Master_Coresight           = 8U,          /**< CORESIGHT RDC Master */
750     kRDC_Master_DAP                 = 9U,          /**< DAP RDC Master */
751     kRDC_Master_CAAM                = 10U,         /**< CAAM RDC Master */
752     kRDC_Master_SDMA1_PERIPH        = 11U,         /**< SDMA1 PERIPHERAL RDC Master */
753     kRDC_Master_SDMA1_BURST         = 12U,         /**< SDMA1 BURST RDC Master */
754     kRDC_Master_APBHDMA             = 13U,         /**< APBH DMA RDC Master */
755     kRDC_Master_RAWNAND             = 14U,         /**< RAW NAND RDC Master */
756     kRDC_Master_USDHC1              = 15U,         /**< USDHC1 RDC Master */
757     kRDC_Master_USDHC2              = 16U,         /**< USDHC2 RDC Master */
758     kRDC_Master_USDHC3              = 17U,         /**< USDHC3 RDC Master */
759     kRDC_Master_AUDIO_PROCESSOR     = 18U,         /**< AUDIO PROCESSOR RDC Master */
760     kRDC_Master_USB1                = 19U,         /**< USB1 RDC Master */
761     kRDC_Master_USB2                = 20U,         /**< USB2 RDC Master */
762     kRDC_Master_TESTPORT            = 21U,         /**< TESTPORT RDC Master */
763     kRDC_Master_ENET1TX             = 22U,         /**< ENET1 TX RDC Master */
764     kRDC_Master_ENET1RX             = 23U,         /**< ENET1 RX RDC Master */
765     kRDC_Master_SDMA2_PERIPH        = 24U,         /**< SDMA2 PERIPH RDC Master */
766     kRDC_Master_SDMA2_BURST         = 24U,         /**< SDMA2 BURST RDC Master */
767     kRDC_Master_SDMA2_SPBA2         = 24U,         /**< SDMA2 to SPBA2 RDC Master */
768     kRDC_Master_SDMA3_SPBA2         = 25U,         /**< SDMA3 to SPBA2 RDC Master */
769     kRDC_Master_SDMA1_SPBA1         = 26U,         /**< SDMA1 to SPBA1 RDC Master */
770     kRDC_Master_LCDIF2              = 27U,         /**< LCDIF2 RDC Master */
771     kRDC_Master_HDMI_TX             = 28U,         /**< HDMI_TX RDC Master */
772     kRDC_Master_ENET2               = 29U,         /**< ENET2 RDC Master */
773     kRDC_Master_GPU3D               = 30U,         /**< GPU3D RDC Master */
774     kRDC_Master_GPU2D               = 31U,         /**< GPU2D RDC Master */
775     kRDC_Master_VPU_G1              = 32U,         /**< VPU_G1 RDC Master */
776     kRDC_Master_VPU_G2              = 33U,         /**< VPU_G2 RDC Master */
777     kRDC_Master_VPU_VC8000E         = 34U,         /**< VPU_VC8000E RDC Master */
778     kRDC_Master_AUDIO_EDMA          = 35U,         /**< AUDIO_EDMA RDC Master */
779     kRDC_Master_ISP1                = 36U,         /**< ISP1 RDC Master */
780     kRDC_Master_ISP2                = 37U,         /**< ISP2 RDC Master */
781     kRDC_Master_DEWARP              = 38U,         /**< DEWARP RDC Master */
782     kRDC_Master_GIC500              = 39U,         /**< GIC500 RDC Master */
783 } rdc_master_t;
784 
785 typedef enum _rdc_mem
786 {
787     kRDC_Mem_MRC0_0                 = 0U,          /**< DEBUG(DAP). Region resolution 4KB. */
788     kRDC_Mem_MRC0_1                 = 1U,
789     kRDC_Mem_MRC0_2                 = 2U,
790     kRDC_Mem_MRC0_3                 = 3U,
791     kRDC_Mem_MRC1_0                 = 4U,          /**< QSPI. Region resolution 4KB. */
792     kRDC_Mem_MRC1_1                 = 5U,
793     kRDC_Mem_MRC1_2                 = 6U,
794     kRDC_Mem_MRC1_3                 = 7U,
795     kRDC_Mem_MRC1_4                 = 8U,
796     kRDC_Mem_MRC1_5                 = 9U,
797     kRDC_Mem_MRC1_6                 = 10U,
798     kRDC_Mem_MRC1_7                 = 11U,
799     kRDC_Mem_MRC2_0                 = 12U,         /**< OCRAM. Region resolution 128B. */
800     kRDC_Mem_MRC2_1                 = 13U,
801     kRDC_Mem_MRC2_2                 = 14U,
802     kRDC_Mem_MRC2_3                 = 15U,
803     kRDC_Mem_MRC2_4                 = 16U,
804     kRDC_Mem_MRC3_0                 = 17U,         /**< OCRAM_S. Region resolution 128B. */
805     kRDC_Mem_MRC3_1                 = 18U,
806     kRDC_Mem_MRC3_2                 = 19U,
807     kRDC_Mem_MRC3_3                 = 20U,
808     kRDC_Mem_MRC3_4                 = 21U,
809     kRDC_Mem_MRC4_0                 = 22U,         /**< TCM. Region resolution 128B. */
810     kRDC_Mem_MRC4_1                 = 23U,
811     kRDC_Mem_MRC4_2                 = 24U,
812     kRDC_Mem_MRC4_3                 = 25U,
813     kRDC_Mem_MRC4_4                 = 26U,
814     kRDC_Mem_MRC5_0                 = 27U,         /**< GIC. Region resolution 4KB. */
815     kRDC_Mem_MRC5_1                 = 28U,
816     kRDC_Mem_MRC5_2                 = 29U,
817     kRDC_Mem_MRC5_3                 = 30U,
818     kRDC_Mem_MRC6_0                 = 31U,         /**< GPU. Region resolution 4KB. */
819     kRDC_Mem_MRC6_1                 = 32U,
820     kRDC_Mem_MRC6_2                 = 33U,
821     kRDC_Mem_MRC6_3                 = 34U,
822     kRDC_Mem_MRC6_4                 = 35U,
823     kRDC_Mem_MRC6_5                 = 36U,
824     kRDC_Mem_MRC6_6                 = 37U,
825     kRDC_Mem_MRC6_7                 = 38U,
826     kRDC_Mem_MRC7_0                 = 39U,         /**< DRAM. Region resolution 4KB. */
827     kRDC_Mem_MRC7_1                 = 40U,
828     kRDC_Mem_MRC7_2                 = 41U,
829     kRDC_Mem_MRC7_3                 = 42U,
830     kRDC_Mem_MRC7_4                 = 43U,
831     kRDC_Mem_MRC7_5                 = 44U,
832     kRDC_Mem_MRC7_6                 = 45U,
833     kRDC_Mem_MRC7_7                 = 46U,
834     kRDC_Mem_MRC8_0                 = 47U,         /**< DDRC(REG). Region resolution 4KB. */
835     kRDC_Mem_MRC8_1                 = 48U,
836     kRDC_Mem_MRC8_2                 = 49U,
837     kRDC_Mem_MRC8_3                 = 50U,
838     kRDC_Mem_MRC8_4                 = 51U,
839     kRDC_Mem_MRC9_0                 = 52U,         /**< PCIe1, USB1/2. Region resolution 4KB. */
840     kRDC_Mem_MRC9_1                 = 53U,
841     kRDC_Mem_MRC9_2                 = 54U,
842     kRDC_Mem_MRC9_3                 = 55U,
843     kRDC_Mem_MRC9_4                 = 56U,
844     kRDC_Mem_MRC9_5                 = 57U,
845     kRDC_Mem_MRC9_6                 = 58U,
846     kRDC_Mem_MRC9_7                 = 59U,
847     kRDC_Mem_MRC10_0                = 60U,         /**< VPU. Region resolution 4KB. */
848     kRDC_Mem_MRC10_1                = 61U,
849     kRDC_Mem_MRC10_2                = 62U,
850     kRDC_Mem_MRC10_3                = 63U,
851     kRDC_Mem_MRC11_0                = 64U,         /**< NPU. Region resolution 4KB. */
852     kRDC_Mem_MRC11_1                = 65U,
853     kRDC_Mem_MRC11_2                = 66U,
854     kRDC_Mem_MRC11_3                = 67U,
855     kRDC_Mem_MRC12_0                = 68U,         /**< AUDIO PROCESSOR. Region resolution 4KB. */
856     kRDC_Mem_MRC12_1                = 69U,
857     kRDC_Mem_MRC12_2                = 70U,
858     kRDC_Mem_MRC12_3                = 71U,
859     kRDC_Mem_MRC13_0                = 72U,         /**< OCRAM_A. Region resolution 128B. */
860     kRDC_Mem_MRC13_1                = 73U,
861     kRDC_Mem_MRC13_2                = 74U,
862     kRDC_Mem_MRC13_3                = 75U,
863     kRDC_Mem_MRC13_4                = 76U,
864 } rdc_mem_t;
865 
866 typedef enum _rdc_periph
867 {
868     kRDC_Periph_GPIO1               = 0U,          /**< GPIO1 RDC Peripheral */
869     kRDC_Periph_GPIO2               = 1U,          /**< GPIO2 RDC Peripheral */
870     kRDC_Periph_GPIO3               = 2U,          /**< GPIO3 RDC Peripheral */
871     kRDC_Periph_GPIO4               = 3U,          /**< GPIO4 RDC Peripheral */
872     kRDC_Periph_GPIO5               = 4U,          /**< GPIO5 RDC Peripheral */
873     kRDC_Periph_MU2_A               = 5U,          /**< MU_2_A (A53, Audio Processor) RDC Peripheral */
874     kRDC_Periph_ANA_TSENSOR         = 6U,          /**< ANA_TSENSOR RDC Peripheral */
875     kRDC_Periph_ANA_OSC             = 7U,          /**< ANA_OSC RDC Peripheral */
876     kRDC_Periph_WDOG1               = 8U,          /**< WDOG1 RDC Peripheral */
877     kRDC_Periph_WDOG2               = 9U,          /**< WDOG2 RDC Peripheral */
878     kRDC_Periph_WDOG3               = 10U,         /**< WDOG3 RDC Peripheral */
879     kRDC_Periph_OCRAM_MECC          = 11U,         /**< OCRAM MECC RDC Peripheral */
880     kRDC_Periph_OCRAM_S_MECC        = 12U,         /**< OCRAM_S MECC RDC Peripheral */
881     kRDC_Periph_GPT1                = 13U,         /**< GPT1 RDC Peripheral */
882     kRDC_Periph_GPT2                = 14U,         /**< GPT2 RDC Peripheral */
883     kRDC_Periph_GPT3                = 15U,         /**< GPT3 RDC Peripheral */
884     kRDC_Periph_MU2_B               = 16U,         /**< MU_2_B (A53, Audio Processor) RDC Peripheral */
885     kRDC_Periph_ROMCP               = 17U,         /**< ROMCP RDC Peripheral */
886     kRDC_Periph_MU3_A               = 18U,         /**< MU_3_A (M7, Audio Processor) RDC Peripheral */
887     kRDC_Periph_IOMUXC              = 19U,         /**< IOMUXC RDC Peripheral */
888     kRDC_Periph_IOMUXC_GPR          = 20U,         /**< IOMUXC_GPR RDC Peripheral */
889     kRDC_Periph_OCOTP_CTRL          = 21U,         /**< OCOTP_CTRL RDC Peripheral */
890     kRDC_Periph_ANA_PLL             = 22U,         /**< ANA_PLL RDC Peripheral */
891     kRDC_Periph_SNVS_HP             = 23U,         /**< SNVS_HP GPR RDC Peripheral */
892     kRDC_Periph_CCM                 = 24U,         /**< CCM RDC Peripheral */
893     kRDC_Periph_SRC                 = 25U,         /**< SRC RDC Peripheral */
894     kRDC_Periph_GPC                 = 26U,         /**< GPC RDC Peripheral */
895     kRDC_Periph_SEMAPHORE1          = 27U,         /**< SEMAPHORE1 RDC Peripheral */
896     kRDC_Periph_SEMAPHORE2          = 28U,         /**< SEMAPHORE2 RDC Peripheral */
897     kRDC_Periph_RDC                 = 29U,         /**< RDC RDC Peripheral */
898     kRDC_Periph_CSU                 = 30U,         /**< CSU RDC Peripheral */
899     kRDC_Periph_MU3_B               = 31U,         /**< MU_3_B (M7, Audio Processor) RDC Peripheral */
900     kRDC_Periph_ISI                 = 32U,         /**< ISI RDC Peripheral */
901     kRDC_Periph_ISP0                = 33U,         /**< ISP0 RDC Peripheral */
902     kRDC_Periph_ISP1                = 34U,         /**< ISP1 RDC Peripheral */
903     kRDC_Periph_IPS_DEWARP          = 35U,         /**< IPS DEWARP RDC Peripheral */
904     kRDC_Periph_MIPI_CSI0           = 36U,         /**< MIPI CSI0 RDC Peripheral */
905     kRDC_Periph_HSIOMIX_BLK_CTL     = 37U,         /**< HSIOMIX BLK CTL RDC Peripheral */
906     kRDC_Periph_PWM1                = 38U,         /**< PWM1 RDC Peripheral */
907     kRDC_Periph_PWM2                = 39U,         /**< PWM2 RDC Peripheral */
908     kRDC_Periph_PWM3                = 40U,         /**< PWM3 RDC Peripheral */
909     kRDC_Periph_PWM4                = 41U,         /**< PWM4 RDC Peripheral */
910     kRDC_Periph_SYS_COUNTER_RD      = 42U,         /**< System counter read RDC Peripheral */
911     kRDC_Periph_SYS_COUNTER_CMP     = 43U,         /**< System counter compare RDC Peripheral */
912     kRDC_Periph_SYS_COUNTER_CTRL    = 44U,         /**< System counter control RDC Peripheral */
913     kRDC_Periph_I2C5                = 45U,         /**< I2C1 RDC Peripheral */
914     kRDC_Periph_GPT6                = 46U,         /**< GPT6 RDC Peripheral */
915     kRDC_Periph_GPT5                = 47U,         /**< GPT5 RDC Peripheral */
916     kRDC_Periph_GPT4                = 48U,         /**< GPT4 RDC Peripheral */
917     kRDC_Periph_MIPI_CSI1           = 49U,         /**< MIPI CSI1 RDC Peripheral */
918     kRDC_Periph_MIPI_DSI0           = 50U,         /**< MIPI DSI0 RDC Peripheral */
919     kRDC_Periph_MEDIAMIX_BLK_CTL    = 51U,         /**< MEDIAMIX BLK CTL RDC Peripheral */
920     kRDC_Periph_LCDIF1              = 52U,         /**< LCDIF1 RDC Peripheral */
921     kRDC_Periph_EDMA                = 53U,         /**< EDMA RDC Peripheral */
922     kRDC_Periph_EDMA_0_15           = 54U,         /**< EDMA Channels [0:15] RDC Peripheral */
923     kRDC_Periph_EDMA_16_31          = 55U,         /**< EDMA Channels [1:31] RDC Peripheral */
924     kRDC_Periph_TZASC               = 56U,         /**< TZASC RDC Peripheral */
925     kRDC_Periph_I2C6                = 57U,         /**< I2C6 RDC Peripheral */
926     kRDC_Periph_CAAM                = 58U,         /**< CAAM RDC Peripheral */
927     kRDC_Periph_LCDIF2              = 59U,         /**< LCDIF2 RDC Peripheral */
928     kRDC_Periph_PERFMON1            = 60U,         /**< PERFMON1 RDC Peripheral */
929     kRDC_Periph_PERFMON2            = 61U,         /**< PERFMON2 RDC Peripheral */
930     kRDC_Periph_PLATFORM_CTRL       = 62U,         /**< PLATFORM_CTRL RDC Peripheral */
931     kRDC_Periph_QOSC                = 63U,         /**< QOSC RDC Peripheral */
932     kRDC_Periph_LVDS0               = 64U,         /**< LVDS0 RDC Peripheral */
933     kRDC_Periph_LVDS1               = 65U,         /**< LVDS1 RDC Peripheral */
934     kRDC_Periph_I2C1                = 66U,         /**< I2C1 RDC Peripheral */
935     kRDC_Periph_I2C2                = 67U,         /**< I2C2 RDC Peripheral */
936     kRDC_Periph_I2C3                = 68U,         /**< I2C3 RDC Peripheral */
937     kRDC_Periph_I2C4                = 69U,         /**< I2C4 RDC Peripheral */
938     kRDC_Periph_UART4               = 70U,         /**< UART4 RDC Peripheral */
939     kRDC_Periph_HDMI_TX             = 71U,         /**< HDMI TX RDC Peripheral */
940     kRDC_Periph_IRQ_STEER           = 72U,         /**< IRQ STEER (Audio Processor) RDC Peripheral */
941     kRDC_Periph_SDMA2               = 73U,         /**< SDMA2 RDC Peripheral */
942     kRDC_Periph_MU1_A               = 74U,         /**< MU1_A RDC Peripheral */
943     kRDC_Periph_MU1_B               = 75U,         /**< MU1_B RDC Peripheral */
944     kRDC_Periph_SEMAPHORE_HS        = 76U,         /**< SEMAPHORE_HS RDC Peripheral */
945     kRDC_Periph_SAI1                = 78U,         /**< SAI1 RDC Peripheral */
946     kRDC_Periph_SAI2                = 79U,         /**< SAI2 RDC Peripheral */
947     kRDC_Periph_SAI3                = 80U,         /**< SAI3 RDC Peripheral */
948     kRDC_Periph_CAN_FD1             = 81U,         /**< CAN_FD1 RDC Peripheral */
949     kRDC_Periph_SAI5                = 82U,         /**< SAI5 RDC Peripheral */
950     kRDC_Periph_SAI6                = 83U,         /**< SAI6 RDC Peripheral */
951     kRDC_Periph_USDHC1              = 84U,         /**< USDHC1 RDC Peripheral */
952     kRDC_Periph_USDHC2              = 85U,         /**< USDHC2 RDC Peripheral */
953     kRDC_Periph_USDHC3              = 86U,         /**< USDHC3 RDC Peripheral */
954     kRDC_Periph_PCIE_PHY1           = 87U,         /**< PCIE PHY1 RDC Peripheral */
955     kRDC_Periph_HDMI_TX_AUDLNK_MSTR = 88U,         /**< HDMI TX AUDLNK MSTR RDC Peripheral */
956     kRDC_Periph_CAN_FD2             = 89U,         /**< CAN_FD2 RDC Peripheral */
957     kRDC_Periph_SPBA2               = 90U,         /**< SPBA2 RDC Peripheral */
958     kRDC_Periph_QSPI                = 91U,         /**< QSPI RDC Peripheral */
959     kRDC_Periph_AUDIO_BLK_CTRL      = 92U,         /**< AUDIO BLK CTRL RDC Peripheral */
960     kRDC_Periph_SDMA1               = 93U,         /**< SDMA1 RDC Peripheral */
961     kRDC_Periph_ENET1               = 94U,         /**< ENET1 RDC Peripheral */
962     kRDC_Periph_ENET2_TSN           = 95U,         /**< ENET2 TSN RDC Peripheral */
963     kRDC_Periph_SPDIF1              = 97U,         /**< SPDIF1 RDC Peripheral */
964     kRDC_Periph_ECSPI1              = 98U,         /**< ECSPI1 RDC Peripheral */
965     kRDC_Periph_ECSPI2              = 99U,         /**< ECSPI2 RDC Peripheral */
966     kRDC_Periph_ECSPI3              = 100U,        /**< ECSPI3 RDC Peripheral */
967     kRDC_Periph_SAI7                = 101U,        /**< SAI7 RDC Peripheral */
968     kRDC_Periph_UART1               = 102U,        /**< UART1 RDC Peripheral */
969     kRDC_Periph_UART3               = 104U,        /**< UART3 RDC Peripheral */
970     kRDC_Periph_UART2               = 105U,        /**< UART2 RDC Peripheral */
971     kRDC_Periph_PDM                 = 106U,        /**< PDM (MICFIL) RDC Peripheral */
972     kRDC_Periph_AUDIO_XCVR_RX       = 107U,        /**< AUDIO XCVR RX RDC (eARC)Peripheral */
973     kRDC_Periph_SDMA3               = 109U,        /**< SDMA3 RDC Peripheral */
974     kRDC_Periph_SPBA1               = 111U,        /**< SPBA1 RDC Peripheral */
975 } rdc_periph_t;
976 
977 /* @} */
978 
979 
980 /*!
981  * @}
982  */ /* end of group Mapping_Information */
983 
984 
985 /* ----------------------------------------------------------------------------
986    -- Device Peripheral Access Layer
987    ---------------------------------------------------------------------------- */
988 
989 /*!
990  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
991  * @{
992  */
993 
994 /* ----------------------------------------------------------------------------
995    -- AIPSTZ Peripheral Access Layer
996    ---------------------------------------------------------------------------- */
997 
998 /*!
999  * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
1000  * @{
1001  */
1002 
1003 /** AIPSTZ - Register Layout Typedef */
1004 typedef struct {
1005   __IO uint32_t MPR;                               /**< Master Priviledge Registers, offset: 0x0 */
1006        uint8_t RESERVED_0[60];
1007   __IO uint32_t OPACR;                             /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
1008   __IO uint32_t OPACR1;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
1009   __IO uint32_t OPACR2;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
1010   __IO uint32_t OPACR3;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
1011   __IO uint32_t OPACR4;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
1012 } AIPSTZ_Type;
1013 
1014 /* ----------------------------------------------------------------------------
1015    -- AIPSTZ Register Masks
1016    ---------------------------------------------------------------------------- */
1017 
1018 /*!
1019  * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
1020  * @{
1021  */
1022 
1023 /*! @name MPR - Master Priviledge Registers */
1024 /*! @{ */
1025 
1026 #define AIPSTZ_MPR_MPROT5_MASK                   (0xF00U)
1027 #define AIPSTZ_MPR_MPROT5_SHIFT                  (8U)
1028 /*! MPROT5
1029  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1030  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1031  *  0bxx0x..This master is not trusted for write accesses.
1032  *  0bxx1x..This master is trusted for write accesses.
1033  *  0bx0xx..This master is not trusted for read accesses.
1034  *  0bx1xx..This master is trusted for read accesses.
1035  *  0b1xxx..Write accesses from this master are allowed to be buffered
1036  */
1037 #define AIPSTZ_MPR_MPROT5(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
1038 
1039 #define AIPSTZ_MPR_MPROT3_MASK                   (0xF0000U)
1040 #define AIPSTZ_MPR_MPROT3_SHIFT                  (16U)
1041 /*! MPROT3
1042  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1043  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1044  *  0bxx0x..This master is not trusted for write accesses.
1045  *  0bxx1x..This master is trusted for write accesses.
1046  *  0bx0xx..This master is not trusted for read accesses.
1047  *  0bx1xx..This master is trusted for read accesses.
1048  *  0b1xxx..Write accesses from this master are allowed to be buffered
1049  */
1050 #define AIPSTZ_MPR_MPROT3(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
1051 
1052 #define AIPSTZ_MPR_MPROT2_MASK                   (0xF00000U)
1053 #define AIPSTZ_MPR_MPROT2_SHIFT                  (20U)
1054 /*! MPROT2
1055  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1056  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1057  *  0bxx0x..This master is not trusted for write accesses.
1058  *  0bxx1x..This master is trusted for write accesses.
1059  *  0bx0xx..This master is not trusted for read accesses.
1060  *  0bx1xx..This master is trusted for read accesses.
1061  *  0b1xxx..Write accesses from this master are allowed to be buffered
1062  */
1063 #define AIPSTZ_MPR_MPROT2(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
1064 
1065 #define AIPSTZ_MPR_MPROT1_MASK                   (0xF000000U)
1066 #define AIPSTZ_MPR_MPROT1_SHIFT                  (24U)
1067 /*! MPROT1
1068  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1069  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1070  *  0bxx0x..This master is not trusted for write accesses.
1071  *  0bxx1x..This master is trusted for write accesses.
1072  *  0bx0xx..This master is not trusted for read accesses.
1073  *  0bx1xx..This master is trusted for read accesses.
1074  *  0b1xxx..Write accesses from this master are allowed to be buffered
1075  */
1076 #define AIPSTZ_MPR_MPROT1(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
1077 
1078 #define AIPSTZ_MPR_MPROT0_MASK                   (0xF0000000U)
1079 #define AIPSTZ_MPR_MPROT0_SHIFT                  (28U)
1080 /*! MPROT0
1081  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1082  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1083  *  0bxx0x..This master is not trusted for write accesses.
1084  *  0bxx1x..This master is trusted for write accesses.
1085  *  0bx0xx..This master is not trusted for read accesses.
1086  *  0bx1xx..This master is trusted for read accesses.
1087  *  0b1xxx..Write accesses from this master are allowed to be buffered
1088  */
1089 #define AIPSTZ_MPR_MPROT0(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
1090 /*! @} */
1091 
1092 /*! @name OPACR - Off-Platform Peripheral Access Control Registers */
1093 /*! @{ */
1094 
1095 #define AIPSTZ_OPACR_OPAC7_MASK                  (0xFU)
1096 #define AIPSTZ_OPACR_OPAC7_SHIFT                 (0U)
1097 /*! OPAC7
1098  *  0bxxx0..Accesses from an untrusted master are allowed.
1099  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1100  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1101  *  0bxx0x..This peripheral allows write accesses.
1102  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1103  *          error response and no peripheral access is initiated on the IPS bus.
1104  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1105  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1106  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1107  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1108  *          on the IPS bus.
1109  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1110  */
1111 #define AIPSTZ_OPACR_OPAC7(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
1112 
1113 #define AIPSTZ_OPACR_OPAC6_MASK                  (0xF0U)
1114 #define AIPSTZ_OPACR_OPAC6_SHIFT                 (4U)
1115 /*! OPAC6
1116  *  0bxxx0..Accesses from an untrusted master are allowed.
1117  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1118  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1119  *  0bxx0x..This peripheral allows write accesses.
1120  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1121  *          error response and no peripheral access is initiated on the IPS bus.
1122  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1123  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1124  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1125  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1126  *          on the IPS bus.
1127  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1128  */
1129 #define AIPSTZ_OPACR_OPAC6(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
1130 
1131 #define AIPSTZ_OPACR_OPAC5_MASK                  (0xF00U)
1132 #define AIPSTZ_OPACR_OPAC5_SHIFT                 (8U)
1133 /*! OPAC5
1134  *  0bxxx0..Accesses from an untrusted master are allowed.
1135  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1136  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1137  *  0bxx0x..This peripheral allows write accesses.
1138  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1139  *          error response and no peripheral access is initiated on the IPS bus.
1140  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1141  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1142  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1143  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1144  *          on the IPS bus.
1145  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1146  */
1147 #define AIPSTZ_OPACR_OPAC5(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
1148 
1149 #define AIPSTZ_OPACR_OPAC4_MASK                  (0xF000U)
1150 #define AIPSTZ_OPACR_OPAC4_SHIFT                 (12U)
1151 /*! OPAC4
1152  *  0bxxx0..Accesses from an untrusted master are allowed.
1153  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1154  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1155  *  0bxx0x..This peripheral allows write accesses.
1156  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1157  *          error response and no peripheral access is initiated on the IPS bus.
1158  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1159  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1160  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1161  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1162  *          on the IPS bus.
1163  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1164  */
1165 #define AIPSTZ_OPACR_OPAC4(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
1166 
1167 #define AIPSTZ_OPACR_OPAC3_MASK                  (0xF0000U)
1168 #define AIPSTZ_OPACR_OPAC3_SHIFT                 (16U)
1169 /*! OPAC3
1170  *  0bxxx0..Accesses from an untrusted master are allowed.
1171  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1172  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1173  *  0bxx0x..This peripheral allows write accesses.
1174  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1175  *          error response and no peripheral access is initiated on the IPS bus.
1176  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1177  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1178  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1179  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1180  *          on the IPS bus.
1181  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1182  */
1183 #define AIPSTZ_OPACR_OPAC3(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
1184 
1185 #define AIPSTZ_OPACR_OPAC2_MASK                  (0xF00000U)
1186 #define AIPSTZ_OPACR_OPAC2_SHIFT                 (20U)
1187 /*! OPAC2
1188  *  0bxxx0..Accesses from an untrusted master are allowed.
1189  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1190  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1191  *  0bxx0x..This peripheral allows write accesses.
1192  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1193  *          error response and no peripheral access is initiated on the IPS bus.
1194  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1195  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1196  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1197  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1198  *          on the IPS bus.
1199  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1200  */
1201 #define AIPSTZ_OPACR_OPAC2(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
1202 
1203 #define AIPSTZ_OPACR_OPAC1_MASK                  (0xF000000U)
1204 #define AIPSTZ_OPACR_OPAC1_SHIFT                 (24U)
1205 /*! OPAC1
1206  *  0bxxx0..Accesses from an untrusted master are allowed.
1207  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1208  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1209  *  0bxx0x..This peripheral allows write accesses.
1210  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1211  *          error response and no peripheral access is initiated on the IPS bus.
1212  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1213  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1214  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1215  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1216  *          on the IPS bus.
1217  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1218  */
1219 #define AIPSTZ_OPACR_OPAC1(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
1220 
1221 #define AIPSTZ_OPACR_OPAC0_MASK                  (0xF0000000U)
1222 #define AIPSTZ_OPACR_OPAC0_SHIFT                 (28U)
1223 /*! OPAC0
1224  *  0bxxx0..Accesses from an untrusted master are allowed.
1225  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1226  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1227  *  0bxx0x..This peripheral allows write accesses.
1228  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1229  *          error response and no peripheral access is initiated on the IPS bus.
1230  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1231  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1232  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1233  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1234  *          on the IPS bus.
1235  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1236  */
1237 #define AIPSTZ_OPACR_OPAC0(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
1238 /*! @} */
1239 
1240 /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
1241 /*! @{ */
1242 
1243 #define AIPSTZ_OPACR1_OPAC15_MASK                (0xFU)
1244 #define AIPSTZ_OPACR1_OPAC15_SHIFT               (0U)
1245 /*! OPAC15
1246  *  0bxxx0..Accesses from an untrusted master are allowed.
1247  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1248  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1249  *  0bxx0x..This peripheral allows write accesses.
1250  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1251  *          error response and no peripheral access is initiated on the IPS bus.
1252  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1253  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1254  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1255  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1256  *          on the IPS bus.
1257  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1258  */
1259 #define AIPSTZ_OPACR1_OPAC15(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
1260 
1261 #define AIPSTZ_OPACR1_OPAC14_MASK                (0xF0U)
1262 #define AIPSTZ_OPACR1_OPAC14_SHIFT               (4U)
1263 /*! OPAC14
1264  *  0bxxx0..Accesses from an untrusted master are allowed.
1265  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1266  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1267  *  0bxx0x..This peripheral allows write accesses.
1268  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1269  *          error response and no peripheral access is initiated on the IPS bus.
1270  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1271  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1272  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1273  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1274  *          on the IPS bus.
1275  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1276  */
1277 #define AIPSTZ_OPACR1_OPAC14(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
1278 
1279 #define AIPSTZ_OPACR1_OPAC13_MASK                (0xF00U)
1280 #define AIPSTZ_OPACR1_OPAC13_SHIFT               (8U)
1281 /*! OPAC13
1282  *  0bxxx0..Accesses from an untrusted master are allowed.
1283  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1284  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1285  *  0bxx0x..This peripheral allows write accesses.
1286  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1287  *          error response and no peripheral access is initiated on the IPS bus.
1288  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1289  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1290  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1291  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1292  *          on the IPS bus.
1293  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1294  */
1295 #define AIPSTZ_OPACR1_OPAC13(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
1296 
1297 #define AIPSTZ_OPACR1_OPAC12_MASK                (0xF000U)
1298 #define AIPSTZ_OPACR1_OPAC12_SHIFT               (12U)
1299 /*! OPAC12
1300  *  0bxxx0..Accesses from an untrusted master are allowed.
1301  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1302  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1303  *  0bxx0x..This peripheral allows write accesses.
1304  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1305  *          error response and no peripheral access is initiated on the IPS bus.
1306  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1307  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1308  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1309  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1310  *          on the IPS bus.
1311  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1312  */
1313 #define AIPSTZ_OPACR1_OPAC12(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
1314 
1315 #define AIPSTZ_OPACR1_OPAC11_MASK                (0xF0000U)
1316 #define AIPSTZ_OPACR1_OPAC11_SHIFT               (16U)
1317 /*! OPAC11
1318  *  0bxxx0..Accesses from an untrusted master are allowed.
1319  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1320  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1321  *  0bxx0x..This peripheral allows write accesses.
1322  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1323  *          error response and no peripheral access is initiated on the IPS bus.
1324  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1325  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1326  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1327  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1328  *          on the IPS bus.
1329  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1330  */
1331 #define AIPSTZ_OPACR1_OPAC11(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
1332 
1333 #define AIPSTZ_OPACR1_OPAC10_MASK                (0xF00000U)
1334 #define AIPSTZ_OPACR1_OPAC10_SHIFT               (20U)
1335 /*! OPAC10
1336  *  0bxxx0..Accesses from an untrusted master are allowed.
1337  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1338  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1339  *  0bxx0x..This peripheral allows write accesses.
1340  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1341  *          error response and no peripheral access is initiated on the IPS bus.
1342  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1343  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1344  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1345  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1346  *          on the IPS bus.
1347  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1348  */
1349 #define AIPSTZ_OPACR1_OPAC10(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
1350 
1351 #define AIPSTZ_OPACR1_OPAC9_MASK                 (0xF000000U)
1352 #define AIPSTZ_OPACR1_OPAC9_SHIFT                (24U)
1353 /*! OPAC9
1354  *  0bxxx0..Accesses from an untrusted master are allowed.
1355  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1356  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1357  *  0bxx0x..This peripheral allows write accesses.
1358  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1359  *          error response and no peripheral access is initiated on the IPS bus.
1360  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1361  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1362  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1363  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1364  *          on the IPS bus.
1365  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1366  */
1367 #define AIPSTZ_OPACR1_OPAC9(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
1368 
1369 #define AIPSTZ_OPACR1_OPAC8_MASK                 (0xF0000000U)
1370 #define AIPSTZ_OPACR1_OPAC8_SHIFT                (28U)
1371 /*! OPAC8
1372  *  0bxxx0..Accesses from an untrusted master are allowed.
1373  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1374  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1375  *  0bxx0x..This peripheral allows write accesses.
1376  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1377  *          error response and no peripheral access is initiated on the IPS bus.
1378  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1379  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1380  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1381  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1382  *          on the IPS bus.
1383  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1384  */
1385 #define AIPSTZ_OPACR1_OPAC8(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
1386 /*! @} */
1387 
1388 /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
1389 /*! @{ */
1390 
1391 #define AIPSTZ_OPACR2_OPAC23_MASK                (0xFU)
1392 #define AIPSTZ_OPACR2_OPAC23_SHIFT               (0U)
1393 /*! OPAC23
1394  *  0bxxx0..Accesses from an untrusted master are allowed.
1395  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1396  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1397  *  0bxx0x..This peripheral allows write accesses.
1398  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1399  *          error response and no peripheral access is initiated on the IPS bus.
1400  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1401  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1402  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1403  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1404  *          on the IPS bus.
1405  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1406  */
1407 #define AIPSTZ_OPACR2_OPAC23(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
1408 
1409 #define AIPSTZ_OPACR2_OPAC22_MASK                (0xF0U)
1410 #define AIPSTZ_OPACR2_OPAC22_SHIFT               (4U)
1411 /*! OPAC22
1412  *  0bxxx0..Accesses from an untrusted master are allowed.
1413  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1414  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1415  *  0bxx0x..This peripheral allows write accesses.
1416  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1417  *          error response and no peripheral access is initiated on the IPS bus.
1418  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1419  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1420  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1421  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1422  *          on the IPS bus.
1423  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1424  */
1425 #define AIPSTZ_OPACR2_OPAC22(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
1426 
1427 #define AIPSTZ_OPACR2_OPAC21_MASK                (0xF00U)
1428 #define AIPSTZ_OPACR2_OPAC21_SHIFT               (8U)
1429 /*! OPAC21
1430  *  0bxxx0..Accesses from an untrusted master are allowed.
1431  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1432  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1433  *  0bxx0x..This peripheral allows write accesses.
1434  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1435  *          error response and no peripheral access is initiated on the IPS bus.
1436  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1437  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1438  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1439  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1440  *          on the IPS bus.
1441  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1442  */
1443 #define AIPSTZ_OPACR2_OPAC21(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
1444 
1445 #define AIPSTZ_OPACR2_OPAC20_MASK                (0xF000U)
1446 #define AIPSTZ_OPACR2_OPAC20_SHIFT               (12U)
1447 /*! OPAC20
1448  *  0bxxx0..Accesses from an untrusted master are allowed.
1449  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1450  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1451  *  0bxx0x..This peripheral allows write accesses.
1452  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1453  *          error response and no peripheral access is initiated on the IPS bus.
1454  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1455  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1456  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1457  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1458  *          on the IPS bus.
1459  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1460  */
1461 #define AIPSTZ_OPACR2_OPAC20(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
1462 
1463 #define AIPSTZ_OPACR2_OPAC19_MASK                (0xF0000U)
1464 #define AIPSTZ_OPACR2_OPAC19_SHIFT               (16U)
1465 /*! OPAC19
1466  *  0bxxx0..Accesses from an untrusted master are allowed.
1467  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1468  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1469  *  0bxx0x..This peripheral allows write accesses.
1470  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1471  *          error response and no peripheral access is initiated on the IPS bus.
1472  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1473  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1474  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1475  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1476  *          on the IPS bus.
1477  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1478  */
1479 #define AIPSTZ_OPACR2_OPAC19(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
1480 
1481 #define AIPSTZ_OPACR2_OPAC18_MASK                (0xF00000U)
1482 #define AIPSTZ_OPACR2_OPAC18_SHIFT               (20U)
1483 /*! OPAC18
1484  *  0bxxx0..Accesses from an untrusted master are allowed.
1485  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1486  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1487  *  0bxx0x..This peripheral allows write accesses.
1488  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1489  *          error response and no peripheral access is initiated on the IPS bus.
1490  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1491  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1492  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1493  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1494  *          on the IPS bus.
1495  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1496  */
1497 #define AIPSTZ_OPACR2_OPAC18(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
1498 
1499 #define AIPSTZ_OPACR2_OPAC17_MASK                (0xF000000U)
1500 #define AIPSTZ_OPACR2_OPAC17_SHIFT               (24U)
1501 /*! OPAC17
1502  *  0bxxx0..Accesses from an untrusted master are allowed.
1503  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1504  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1505  *  0bxx0x..This peripheral allows write accesses.
1506  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1507  *          error response and no peripheral access is initiated on the IPS bus.
1508  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1509  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1510  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1511  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1512  *          on the IPS bus.
1513  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1514  */
1515 #define AIPSTZ_OPACR2_OPAC17(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
1516 
1517 #define AIPSTZ_OPACR2_OPAC16_MASK                (0xF0000000U)
1518 #define AIPSTZ_OPACR2_OPAC16_SHIFT               (28U)
1519 /*! OPAC16
1520  *  0bxxx0..Accesses from an untrusted master are allowed.
1521  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1522  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1523  *  0bxx0x..This peripheral allows write accesses.
1524  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1525  *          error response and no peripheral access is initiated on the IPS bus.
1526  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1527  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1528  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1529  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1530  *          on the IPS bus.
1531  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1532  */
1533 #define AIPSTZ_OPACR2_OPAC16(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
1534 /*! @} */
1535 
1536 /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
1537 /*! @{ */
1538 
1539 #define AIPSTZ_OPACR3_OPAC31_MASK                (0xFU)
1540 #define AIPSTZ_OPACR3_OPAC31_SHIFT               (0U)
1541 /*! OPAC31
1542  *  0bxxx0..Accesses from an untrusted master are allowed.
1543  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1544  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1545  *  0bxx0x..This peripheral allows write accesses.
1546  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1547  *          error response and no peripheral access is initiated on the IPS bus.
1548  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1549  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1550  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1551  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1552  *          on the IPS bus.
1553  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1554  */
1555 #define AIPSTZ_OPACR3_OPAC31(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1556 
1557 #define AIPSTZ_OPACR3_OPAC30_MASK                (0xF0U)
1558 #define AIPSTZ_OPACR3_OPAC30_SHIFT               (4U)
1559 /*! OPAC30
1560  *  0bxxx0..Accesses from an untrusted master are allowed.
1561  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1562  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1563  *  0bxx0x..This peripheral allows write accesses.
1564  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1565  *          error response and no peripheral access is initiated on the IPS bus.
1566  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1567  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1568  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1569  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1570  *          on the IPS bus.
1571  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1572  */
1573 #define AIPSTZ_OPACR3_OPAC30(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1574 
1575 #define AIPSTZ_OPACR3_OPAC29_MASK                (0xF00U)
1576 #define AIPSTZ_OPACR3_OPAC29_SHIFT               (8U)
1577 /*! OPAC29
1578  *  0bxxx0..Accesses from an untrusted master are allowed.
1579  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1580  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1581  *  0bxx0x..This peripheral allows write accesses.
1582  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1583  *          error response and no peripheral access is initiated on the IPS bus.
1584  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1585  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1586  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1587  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1588  *          on the IPS bus.
1589  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1590  */
1591 #define AIPSTZ_OPACR3_OPAC29(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1592 
1593 #define AIPSTZ_OPACR3_OPAC28_MASK                (0xF000U)
1594 #define AIPSTZ_OPACR3_OPAC28_SHIFT               (12U)
1595 /*! OPAC28
1596  *  0bxxx0..Accesses from an untrusted master are allowed.
1597  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1598  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1599  *  0bxx0x..This peripheral allows write accesses.
1600  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1601  *          error response and no peripheral access is initiated on the IPS bus.
1602  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1603  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1604  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1605  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1606  *          on the IPS bus.
1607  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1608  */
1609 #define AIPSTZ_OPACR3_OPAC28(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1610 
1611 #define AIPSTZ_OPACR3_OPAC27_MASK                (0xF0000U)
1612 #define AIPSTZ_OPACR3_OPAC27_SHIFT               (16U)
1613 /*! OPAC27
1614  *  0bxxx0..Accesses from an untrusted master are allowed.
1615  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1616  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1617  *  0bxx0x..This peripheral allows write accesses.
1618  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1619  *          error response and no peripheral access is initiated on the IPS bus.
1620  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1621  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1622  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1623  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1624  *          on the IPS bus.
1625  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1626  */
1627 #define AIPSTZ_OPACR3_OPAC27(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1628 
1629 #define AIPSTZ_OPACR3_OPAC26_MASK                (0xF00000U)
1630 #define AIPSTZ_OPACR3_OPAC26_SHIFT               (20U)
1631 /*! OPAC26
1632  *  0bxxx0..Accesses from an untrusted master are allowed.
1633  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1634  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1635  *  0bxx0x..This peripheral allows write accesses.
1636  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1637  *          error response and no peripheral access is initiated on the IPS bus.
1638  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1639  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1640  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1641  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1642  *          on the IPS bus.
1643  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1644  */
1645 #define AIPSTZ_OPACR3_OPAC26(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
1646 
1647 #define AIPSTZ_OPACR3_OPAC25_MASK                (0xF000000U)
1648 #define AIPSTZ_OPACR3_OPAC25_SHIFT               (24U)
1649 /*! OPAC25
1650  *  0bxxx0..Accesses from an untrusted master are allowed.
1651  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1652  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1653  *  0bxx0x..This peripheral allows write accesses.
1654  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1655  *          error response and no peripheral access is initiated on the IPS bus.
1656  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1657  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1658  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1659  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1660  *          on the IPS bus.
1661  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1662  */
1663 #define AIPSTZ_OPACR3_OPAC25(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
1664 
1665 #define AIPSTZ_OPACR3_OPAC24_MASK                (0xF0000000U)
1666 #define AIPSTZ_OPACR3_OPAC24_SHIFT               (28U)
1667 /*! OPAC24
1668  *  0bxxx0..Accesses from an untrusted master are allowed.
1669  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1670  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1671  *  0bxx0x..This peripheral allows write accesses.
1672  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1673  *          error response and no peripheral access is initiated on the IPS bus.
1674  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1675  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1676  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1677  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1678  *          on the IPS bus.
1679  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1680  */
1681 #define AIPSTZ_OPACR3_OPAC24(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
1682 /*! @} */
1683 
1684 /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
1685 /*! @{ */
1686 
1687 #define AIPSTZ_OPACR4_OPAC33_MASK                (0xF000000U)
1688 #define AIPSTZ_OPACR4_OPAC33_SHIFT               (24U)
1689 /*! OPAC33
1690  *  0bxxx0..Accesses from an untrusted master are allowed.
1691  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1692  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1693  *  0bxx0x..This peripheral allows write accesses.
1694  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1695  *          error response and no peripheral access is initiated on the IPS bus.
1696  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1697  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1698  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1699  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1700  *          on the IPS bus.
1701  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1702  */
1703 #define AIPSTZ_OPACR4_OPAC33(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
1704 
1705 #define AIPSTZ_OPACR4_OPAC32_MASK                (0xF0000000U)
1706 #define AIPSTZ_OPACR4_OPAC32_SHIFT               (28U)
1707 /*! OPAC32
1708  *  0bxxx0..Accesses from an untrusted master are allowed.
1709  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1710  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1711  *  0bxx0x..This peripheral allows write accesses.
1712  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1713  *          error response and no peripheral access is initiated on the IPS bus.
1714  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1715  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1716  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1717  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
1718  *          on the IPS bus.
1719  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1720  */
1721 #define AIPSTZ_OPACR4_OPAC32(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
1722 /*! @} */
1723 
1724 
1725 /*!
1726  * @}
1727  */ /* end of group AIPSTZ_Register_Masks */
1728 
1729 
1730 /* AIPSTZ - Peripheral instance base addresses */
1731 /** Peripheral AIPSTZ1 base address */
1732 #define AIPSTZ1_BASE                             (0x301F0000u)
1733 /** Peripheral AIPSTZ1 base pointer */
1734 #define AIPSTZ1                                  ((AIPSTZ_Type *)AIPSTZ1_BASE)
1735 /** Peripheral AIPSTZ2 base address */
1736 #define AIPSTZ2_BASE                             (0x305F0000u)
1737 /** Peripheral AIPSTZ2 base pointer */
1738 #define AIPSTZ2                                  ((AIPSTZ_Type *)AIPSTZ2_BASE)
1739 /** Peripheral AIPSTZ3 base address */
1740 #define AIPSTZ3_BASE                             (0x309F0000u)
1741 /** Peripheral AIPSTZ3 base pointer */
1742 #define AIPSTZ3                                  ((AIPSTZ_Type *)AIPSTZ3_BASE)
1743 /** Peripheral AIPSTZ4 base address */
1744 #define AIPSTZ4_BASE                             (0x32DF0000u)
1745 /** Peripheral AIPSTZ4 base pointer */
1746 #define AIPSTZ4                                  ((AIPSTZ_Type *)AIPSTZ4_BASE)
1747 /** Peripheral AIPSTZ5 base address */
1748 #define AIPSTZ5_BASE                             (0x30DF0000u)
1749 /** Peripheral AIPSTZ5 base pointer */
1750 #define AIPSTZ5                                  ((AIPSTZ_Type *)AIPSTZ5_BASE)
1751 /** Array initializer of AIPSTZ peripheral base addresses */
1752 #define AIPSTZ_BASE_ADDRS                        { AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE, AIPSTZ5_BASE }
1753 /** Array initializer of AIPSTZ peripheral base pointers */
1754 #define AIPSTZ_BASE_PTRS                         { AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, AIPSTZ5 }
1755 
1756 /*!
1757  * @}
1758  */ /* end of group AIPSTZ_Peripheral_Access_Layer */
1759 
1760 
1761 /* ----------------------------------------------------------------------------
1762    -- APBH Peripheral Access Layer
1763    ---------------------------------------------------------------------------- */
1764 
1765 /*!
1766  * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1767  * @{
1768  */
1769 
1770 /** APBH - Register Layout Typedef */
1771 typedef struct {
1772   __IO uint32_t CTRL0;                             /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1773   __IO uint32_t CTRL0_SET;                         /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1774   __IO uint32_t CTRL0_CLR;                         /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1775   __IO uint32_t CTRL0_TOG;                         /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1776   __IO uint32_t CTRL1;                             /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1777   __IO uint32_t CTRL1_SET;                         /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1778   __IO uint32_t CTRL1_CLR;                         /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1779   __IO uint32_t CTRL1_TOG;                         /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1780   __IO uint32_t CTRL2;                             /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1781   __IO uint32_t CTRL2_SET;                         /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1782   __IO uint32_t CTRL2_CLR;                         /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1783   __IO uint32_t CTRL2_TOG;                         /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1784   __IO uint32_t CHANNEL_CTRL;                      /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1785   __IO uint32_t CHANNEL_CTRL_SET;                  /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1786   __IO uint32_t CHANNEL_CTRL_CLR;                  /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1787   __IO uint32_t CHANNEL_CTRL_TOG;                  /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1788   __I  uint32_t DEVSEL;                            /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1789        uint8_t RESERVED_0[12];
1790   __IO uint32_t DMA_BURST_SIZE;                    /**< AHB to APBH DMA burst size, offset: 0x50 */
1791        uint8_t RESERVED_1[12];
1792   __IO uint32_t DEBUGr;                            /**< AHB to APBH DMA Debug Register, offset: 0x60, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
1793        uint8_t RESERVED_2[156];
1794   struct {                                         /* offset: 0x100, array step: 0x70 */
1795     __I  uint32_t CH_CURCMDAR;                       /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1796          uint8_t RESERVED_0[12];
1797     __IO uint32_t CH_NXTCMDAR;                       /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1798          uint8_t RESERVED_1[12];
1799     __I  uint32_t CH_CMD;                            /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1800          uint8_t RESERVED_2[12];
1801     __I  uint32_t CH_BAR;                            /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1802          uint8_t RESERVED_3[12];
1803     __IO uint32_t CH_SEMA;                           /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1804          uint8_t RESERVED_4[12];
1805     __I  uint32_t CH_DEBUG1;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1806          uint8_t RESERVED_5[12];
1807     __I  uint32_t CH_DEBUG2;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1808          uint8_t RESERVED_6[12];
1809   } CH_CFGn[16];
1810   __I  uint32_t VERSION;                           /**< APBH Bridge Version Register, offset: 0x800 */
1811 } APBH_Type;
1812 
1813 /* ----------------------------------------------------------------------------
1814    -- APBH Register Masks
1815    ---------------------------------------------------------------------------- */
1816 
1817 /*!
1818  * @addtogroup APBH_Register_Masks APBH Register Masks
1819  * @{
1820  */
1821 
1822 /*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1823 /*! @{ */
1824 
1825 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK          (0xFFFFU)
1826 #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT         (0U)
1827 /*! CLKGATE_CHANNEL
1828  *  0b0000000000000001..NAND0
1829  *  0b0000000000000010..NAND1
1830  *  0b0000000000000100..NAND2
1831  *  0b0000000000001000..NAND3
1832  *  0b0000000000010000..NAND4
1833  *  0b0000000000100000..NAND5
1834  *  0b0000000001000000..NAND6
1835  *  0b0000000010000000..NAND7
1836  *  0b0000000100000000..SSP
1837  */
1838 #define APBH_CTRL0_CLKGATE_CHANNEL(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1839 
1840 #define APBH_CTRL0_RSVD0_MASK                    (0xFFF0000U)
1841 #define APBH_CTRL0_RSVD0_SHIFT                   (16U)
1842 #define APBH_CTRL0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
1843 
1844 #define APBH_CTRL0_APB_BURST_EN_MASK             (0x10000000U)
1845 #define APBH_CTRL0_APB_BURST_EN_SHIFT            (28U)
1846 #define APBH_CTRL0_APB_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1847 
1848 #define APBH_CTRL0_AHB_BURST8_EN_MASK            (0x20000000U)
1849 #define APBH_CTRL0_AHB_BURST8_EN_SHIFT           (29U)
1850 #define APBH_CTRL0_AHB_BURST8_EN(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1851 
1852 #define APBH_CTRL0_CLKGATE_MASK                  (0x40000000U)
1853 #define APBH_CTRL0_CLKGATE_SHIFT                 (30U)
1854 #define APBH_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1855 
1856 #define APBH_CTRL0_SFTRST_MASK                   (0x80000000U)
1857 #define APBH_CTRL0_SFTRST_SHIFT                  (31U)
1858 #define APBH_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1859 /*! @} */
1860 
1861 /*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
1862 /*! @{ */
1863 
1864 #define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK      (0xFFFFU)
1865 #define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT     (0U)
1866 /*! CLKGATE_CHANNEL
1867  *  0b0000000000000001..NAND0
1868  *  0b0000000000000010..NAND1
1869  *  0b0000000000000100..NAND2
1870  *  0b0000000000001000..NAND3
1871  *  0b0000000000010000..NAND4
1872  *  0b0000000000100000..NAND5
1873  *  0b0000000001000000..NAND6
1874  *  0b0000000010000000..NAND7
1875  *  0b0000000100000000..SSP
1876  */
1877 #define APBH_CTRL0_SET_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
1878 
1879 #define APBH_CTRL0_SET_RSVD0_MASK                (0xFFF0000U)
1880 #define APBH_CTRL0_SET_RSVD0_SHIFT               (16U)
1881 #define APBH_CTRL0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
1882 
1883 #define APBH_CTRL0_SET_APB_BURST_EN_MASK         (0x10000000U)
1884 #define APBH_CTRL0_SET_APB_BURST_EN_SHIFT        (28U)
1885 #define APBH_CTRL0_SET_APB_BURST_EN(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
1886 
1887 #define APBH_CTRL0_SET_AHB_BURST8_EN_MASK        (0x20000000U)
1888 #define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT       (29U)
1889 #define APBH_CTRL0_SET_AHB_BURST8_EN(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
1890 
1891 #define APBH_CTRL0_SET_CLKGATE_MASK              (0x40000000U)
1892 #define APBH_CTRL0_SET_CLKGATE_SHIFT             (30U)
1893 #define APBH_CTRL0_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
1894 
1895 #define APBH_CTRL0_SET_SFTRST_MASK               (0x80000000U)
1896 #define APBH_CTRL0_SET_SFTRST_SHIFT              (31U)
1897 #define APBH_CTRL0_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
1898 /*! @} */
1899 
1900 /*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
1901 /*! @{ */
1902 
1903 #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK      (0xFFFFU)
1904 #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT     (0U)
1905 /*! CLKGATE_CHANNEL
1906  *  0b0000000000000001..NAND0
1907  *  0b0000000000000010..NAND1
1908  *  0b0000000000000100..NAND2
1909  *  0b0000000000001000..NAND3
1910  *  0b0000000000010000..NAND4
1911  *  0b0000000000100000..NAND5
1912  *  0b0000000001000000..NAND6
1913  *  0b0000000010000000..NAND7
1914  *  0b0000000100000000..SSP
1915  */
1916 #define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
1917 
1918 #define APBH_CTRL0_CLR_RSVD0_MASK                (0xFFF0000U)
1919 #define APBH_CTRL0_CLR_RSVD0_SHIFT               (16U)
1920 #define APBH_CTRL0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
1921 
1922 #define APBH_CTRL0_CLR_APB_BURST_EN_MASK         (0x10000000U)
1923 #define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT        (28U)
1924 #define APBH_CTRL0_CLR_APB_BURST_EN(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
1925 
1926 #define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK        (0x20000000U)
1927 #define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT       (29U)
1928 #define APBH_CTRL0_CLR_AHB_BURST8_EN(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
1929 
1930 #define APBH_CTRL0_CLR_CLKGATE_MASK              (0x40000000U)
1931 #define APBH_CTRL0_CLR_CLKGATE_SHIFT             (30U)
1932 #define APBH_CTRL0_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
1933 
1934 #define APBH_CTRL0_CLR_SFTRST_MASK               (0x80000000U)
1935 #define APBH_CTRL0_CLR_SFTRST_SHIFT              (31U)
1936 #define APBH_CTRL0_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
1937 /*! @} */
1938 
1939 /*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
1940 /*! @{ */
1941 
1942 #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK      (0xFFFFU)
1943 #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT     (0U)
1944 /*! CLKGATE_CHANNEL
1945  *  0b0000000000000001..NAND0
1946  *  0b0000000000000010..NAND1
1947  *  0b0000000000000100..NAND2
1948  *  0b0000000000001000..NAND3
1949  *  0b0000000000010000..NAND4
1950  *  0b0000000000100000..NAND5
1951  *  0b0000000001000000..NAND6
1952  *  0b0000000010000000..NAND7
1953  *  0b0000000100000000..SSP
1954  */
1955 #define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
1956 
1957 #define APBH_CTRL0_TOG_RSVD0_MASK                (0xFFF0000U)
1958 #define APBH_CTRL0_TOG_RSVD0_SHIFT               (16U)
1959 #define APBH_CTRL0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
1960 
1961 #define APBH_CTRL0_TOG_APB_BURST_EN_MASK         (0x10000000U)
1962 #define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT        (28U)
1963 #define APBH_CTRL0_TOG_APB_BURST_EN(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
1964 
1965 #define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK        (0x20000000U)
1966 #define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT       (29U)
1967 #define APBH_CTRL0_TOG_AHB_BURST8_EN(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
1968 
1969 #define APBH_CTRL0_TOG_CLKGATE_MASK              (0x40000000U)
1970 #define APBH_CTRL0_TOG_CLKGATE_SHIFT             (30U)
1971 #define APBH_CTRL0_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
1972 
1973 #define APBH_CTRL0_TOG_SFTRST_MASK               (0x80000000U)
1974 #define APBH_CTRL0_TOG_SFTRST_SHIFT              (31U)
1975 #define APBH_CTRL0_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
1976 /*! @} */
1977 
1978 /*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1979 /*! @{ */
1980 
1981 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK         (0x1U)
1982 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT        (0U)
1983 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1984 
1985 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK         (0x2U)
1986 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT        (1U)
1987 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1988 
1989 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK         (0x4U)
1990 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT        (2U)
1991 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1992 
1993 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK         (0x8U)
1994 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT        (3U)
1995 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1996 
1997 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK         (0x10U)
1998 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT        (4U)
1999 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
2000 
2001 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK         (0x20U)
2002 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT        (5U)
2003 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
2004 
2005 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK         (0x40U)
2006 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT        (6U)
2007 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
2008 
2009 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK         (0x80U)
2010 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT        (7U)
2011 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
2012 
2013 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK         (0x100U)
2014 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT        (8U)
2015 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
2016 
2017 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK         (0x200U)
2018 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT        (9U)
2019 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
2020 
2021 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK        (0x400U)
2022 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT       (10U)
2023 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
2024 
2025 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK        (0x800U)
2026 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT       (11U)
2027 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
2028 
2029 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK        (0x1000U)
2030 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT       (12U)
2031 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
2032 
2033 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK        (0x2000U)
2034 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT       (13U)
2035 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
2036 
2037 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK        (0x4000U)
2038 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT       (14U)
2039 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
2040 
2041 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK        (0x8000U)
2042 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT       (15U)
2043 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
2044 
2045 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK      (0x10000U)
2046 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT     (16U)
2047 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
2048 
2049 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK      (0x20000U)
2050 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT     (17U)
2051 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
2052 
2053 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK      (0x40000U)
2054 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT     (18U)
2055 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
2056 
2057 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK      (0x80000U)
2058 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT     (19U)
2059 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
2060 
2061 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK      (0x100000U)
2062 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT     (20U)
2063 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
2064 
2065 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK      (0x200000U)
2066 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT     (21U)
2067 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
2068 
2069 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK      (0x400000U)
2070 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT     (22U)
2071 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
2072 
2073 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK      (0x800000U)
2074 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT     (23U)
2075 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
2076 
2077 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK      (0x1000000U)
2078 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT     (24U)
2079 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
2080 
2081 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK      (0x2000000U)
2082 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT     (25U)
2083 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
2084 
2085 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK     (0x4000000U)
2086 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT    (26U)
2087 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
2088 
2089 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK     (0x8000000U)
2090 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT    (27U)
2091 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
2092 
2093 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK     (0x10000000U)
2094 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT    (28U)
2095 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
2096 
2097 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK     (0x20000000U)
2098 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT    (29U)
2099 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
2100 
2101 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK     (0x40000000U)
2102 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT    (30U)
2103 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
2104 
2105 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK     (0x80000000U)
2106 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT    (31U)
2107 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
2108 /*! @} */
2109 
2110 /*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
2111 /*! @{ */
2112 
2113 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK     (0x1U)
2114 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT    (0U)
2115 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
2116 
2117 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK     (0x2U)
2118 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT    (1U)
2119 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
2120 
2121 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK     (0x4U)
2122 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT    (2U)
2123 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
2124 
2125 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK     (0x8U)
2126 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT    (3U)
2127 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
2128 
2129 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK     (0x10U)
2130 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT    (4U)
2131 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
2132 
2133 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK     (0x20U)
2134 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT    (5U)
2135 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
2136 
2137 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK     (0x40U)
2138 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT    (6U)
2139 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
2140 
2141 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK     (0x80U)
2142 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT    (7U)
2143 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
2144 
2145 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK     (0x100U)
2146 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT    (8U)
2147 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
2148 
2149 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK     (0x200U)
2150 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT    (9U)
2151 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
2152 
2153 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK    (0x400U)
2154 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT   (10U)
2155 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
2156 
2157 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK    (0x800U)
2158 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT   (11U)
2159 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
2160 
2161 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK    (0x1000U)
2162 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT   (12U)
2163 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
2164 
2165 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK    (0x2000U)
2166 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT   (13U)
2167 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
2168 
2169 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK    (0x4000U)
2170 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT   (14U)
2171 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
2172 
2173 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK    (0x8000U)
2174 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT   (15U)
2175 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
2176 
2177 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK  (0x10000U)
2178 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2179 #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
2180 
2181 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK  (0x20000U)
2182 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2183 #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
2184 
2185 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK  (0x40000U)
2186 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2187 #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
2188 
2189 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK  (0x80000U)
2190 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2191 #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
2192 
2193 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK  (0x100000U)
2194 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2195 #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
2196 
2197 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK  (0x200000U)
2198 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2199 #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
2200 
2201 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK  (0x400000U)
2202 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2203 #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
2204 
2205 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK  (0x800000U)
2206 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2207 #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
2208 
2209 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK  (0x1000000U)
2210 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2211 #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
2212 
2213 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK  (0x2000000U)
2214 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2215 #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
2216 
2217 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2218 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2219 #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
2220 
2221 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2222 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2223 #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
2224 
2225 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2226 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2227 #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
2228 
2229 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2230 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2231 #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
2232 
2233 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2234 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2235 #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
2236 
2237 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2238 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2239 #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
2240 /*! @} */
2241 
2242 /*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
2243 /*! @{ */
2244 
2245 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK     (0x1U)
2246 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT    (0U)
2247 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
2248 
2249 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK     (0x2U)
2250 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT    (1U)
2251 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
2252 
2253 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK     (0x4U)
2254 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT    (2U)
2255 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
2256 
2257 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK     (0x8U)
2258 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT    (3U)
2259 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
2260 
2261 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK     (0x10U)
2262 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT    (4U)
2263 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
2264 
2265 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK     (0x20U)
2266 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT    (5U)
2267 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
2268 
2269 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK     (0x40U)
2270 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT    (6U)
2271 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
2272 
2273 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK     (0x80U)
2274 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT    (7U)
2275 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
2276 
2277 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK     (0x100U)
2278 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT    (8U)
2279 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
2280 
2281 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK     (0x200U)
2282 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT    (9U)
2283 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
2284 
2285 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK    (0x400U)
2286 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT   (10U)
2287 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
2288 
2289 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK    (0x800U)
2290 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT   (11U)
2291 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
2292 
2293 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK    (0x1000U)
2294 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT   (12U)
2295 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
2296 
2297 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK    (0x2000U)
2298 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT   (13U)
2299 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
2300 
2301 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK    (0x4000U)
2302 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT   (14U)
2303 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
2304 
2305 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK    (0x8000U)
2306 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT   (15U)
2307 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
2308 
2309 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK  (0x10000U)
2310 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2311 #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
2312 
2313 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK  (0x20000U)
2314 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2315 #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
2316 
2317 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK  (0x40000U)
2318 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2319 #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
2320 
2321 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK  (0x80000U)
2322 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2323 #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
2324 
2325 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK  (0x100000U)
2326 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2327 #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
2328 
2329 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK  (0x200000U)
2330 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2331 #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
2332 
2333 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK  (0x400000U)
2334 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2335 #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
2336 
2337 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK  (0x800000U)
2338 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2339 #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
2340 
2341 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK  (0x1000000U)
2342 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2343 #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
2344 
2345 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK  (0x2000000U)
2346 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2347 #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
2348 
2349 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2350 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2351 #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
2352 
2353 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2354 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2355 #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
2356 
2357 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2358 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2359 #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
2360 
2361 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2362 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2363 #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
2364 
2365 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2366 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2367 #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
2368 
2369 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2370 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2371 #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
2372 /*! @} */
2373 
2374 /*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
2375 /*! @{ */
2376 
2377 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK     (0x1U)
2378 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT    (0U)
2379 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
2380 
2381 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK     (0x2U)
2382 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT    (1U)
2383 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
2384 
2385 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK     (0x4U)
2386 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT    (2U)
2387 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
2388 
2389 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK     (0x8U)
2390 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT    (3U)
2391 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
2392 
2393 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK     (0x10U)
2394 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT    (4U)
2395 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
2396 
2397 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK     (0x20U)
2398 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT    (5U)
2399 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
2400 
2401 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK     (0x40U)
2402 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT    (6U)
2403 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
2404 
2405 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK     (0x80U)
2406 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT    (7U)
2407 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
2408 
2409 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK     (0x100U)
2410 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT    (8U)
2411 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
2412 
2413 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK     (0x200U)
2414 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT    (9U)
2415 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
2416 
2417 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK    (0x400U)
2418 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT   (10U)
2419 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
2420 
2421 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK    (0x800U)
2422 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT   (11U)
2423 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
2424 
2425 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK    (0x1000U)
2426 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT   (12U)
2427 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
2428 
2429 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK    (0x2000U)
2430 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT   (13U)
2431 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
2432 
2433 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK    (0x4000U)
2434 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT   (14U)
2435 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
2436 
2437 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK    (0x8000U)
2438 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT   (15U)
2439 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
2440 
2441 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK  (0x10000U)
2442 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2443 #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
2444 
2445 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK  (0x20000U)
2446 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2447 #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
2448 
2449 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK  (0x40000U)
2450 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2451 #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
2452 
2453 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK  (0x80000U)
2454 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2455 #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
2456 
2457 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK  (0x100000U)
2458 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2459 #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
2460 
2461 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK  (0x200000U)
2462 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2463 #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
2464 
2465 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK  (0x400000U)
2466 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2467 #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
2468 
2469 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK  (0x800000U)
2470 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2471 #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
2472 
2473 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK  (0x1000000U)
2474 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2475 #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
2476 
2477 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK  (0x2000000U)
2478 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2479 #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
2480 
2481 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2482 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2483 #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
2484 
2485 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2486 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2487 #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
2488 
2489 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2490 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2491 #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
2492 
2493 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2494 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2495 #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
2496 
2497 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2498 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2499 #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
2500 
2501 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2502 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2503 #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
2504 /*! @} */
2505 
2506 /*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
2507 /*! @{ */
2508 
2509 #define APBH_CTRL2_CH0_ERROR_IRQ_MASK            (0x1U)
2510 #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT           (0U)
2511 #define APBH_CTRL2_CH0_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
2512 
2513 #define APBH_CTRL2_CH1_ERROR_IRQ_MASK            (0x2U)
2514 #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT           (1U)
2515 #define APBH_CTRL2_CH1_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
2516 
2517 #define APBH_CTRL2_CH2_ERROR_IRQ_MASK            (0x4U)
2518 #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT           (2U)
2519 #define APBH_CTRL2_CH2_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
2520 
2521 #define APBH_CTRL2_CH3_ERROR_IRQ_MASK            (0x8U)
2522 #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT           (3U)
2523 #define APBH_CTRL2_CH3_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
2524 
2525 #define APBH_CTRL2_CH4_ERROR_IRQ_MASK            (0x10U)
2526 #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT           (4U)
2527 #define APBH_CTRL2_CH4_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
2528 
2529 #define APBH_CTRL2_CH5_ERROR_IRQ_MASK            (0x20U)
2530 #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT           (5U)
2531 #define APBH_CTRL2_CH5_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
2532 
2533 #define APBH_CTRL2_CH6_ERROR_IRQ_MASK            (0x40U)
2534 #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT           (6U)
2535 #define APBH_CTRL2_CH6_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
2536 
2537 #define APBH_CTRL2_CH7_ERROR_IRQ_MASK            (0x80U)
2538 #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT           (7U)
2539 #define APBH_CTRL2_CH7_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
2540 
2541 #define APBH_CTRL2_CH8_ERROR_IRQ_MASK            (0x100U)
2542 #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT           (8U)
2543 #define APBH_CTRL2_CH8_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
2544 
2545 #define APBH_CTRL2_CH9_ERROR_IRQ_MASK            (0x200U)
2546 #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT           (9U)
2547 #define APBH_CTRL2_CH9_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
2548 
2549 #define APBH_CTRL2_CH10_ERROR_IRQ_MASK           (0x400U)
2550 #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT          (10U)
2551 #define APBH_CTRL2_CH10_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
2552 
2553 #define APBH_CTRL2_CH11_ERROR_IRQ_MASK           (0x800U)
2554 #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT          (11U)
2555 #define APBH_CTRL2_CH11_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
2556 
2557 #define APBH_CTRL2_CH12_ERROR_IRQ_MASK           (0x1000U)
2558 #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT          (12U)
2559 #define APBH_CTRL2_CH12_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
2560 
2561 #define APBH_CTRL2_CH13_ERROR_IRQ_MASK           (0x2000U)
2562 #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT          (13U)
2563 #define APBH_CTRL2_CH13_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
2564 
2565 #define APBH_CTRL2_CH14_ERROR_IRQ_MASK           (0x4000U)
2566 #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT          (14U)
2567 #define APBH_CTRL2_CH14_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
2568 
2569 #define APBH_CTRL2_CH15_ERROR_IRQ_MASK           (0x8000U)
2570 #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT          (15U)
2571 #define APBH_CTRL2_CH15_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
2572 
2573 #define APBH_CTRL2_CH0_ERROR_STATUS_MASK         (0x10000U)
2574 #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT        (16U)
2575 /*! CH0_ERROR_STATUS
2576  *  0b0..An early termination from the device causes error IRQ.
2577  *  0b1..An AHB bus error causes error IRQ.
2578  */
2579 #define APBH_CTRL2_CH0_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
2580 
2581 #define APBH_CTRL2_CH1_ERROR_STATUS_MASK         (0x20000U)
2582 #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT        (17U)
2583 /*! CH1_ERROR_STATUS
2584  *  0b0..An early termination from the device causes error IRQ.
2585  *  0b1..An AHB bus error causes error IRQ.
2586  */
2587 #define APBH_CTRL2_CH1_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
2588 
2589 #define APBH_CTRL2_CH2_ERROR_STATUS_MASK         (0x40000U)
2590 #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT        (18U)
2591 /*! CH2_ERROR_STATUS
2592  *  0b0..An early termination from the device causes error IRQ.
2593  *  0b1..An AHB bus error causes error IRQ.
2594  */
2595 #define APBH_CTRL2_CH2_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
2596 
2597 #define APBH_CTRL2_CH3_ERROR_STATUS_MASK         (0x80000U)
2598 #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT        (19U)
2599 /*! CH3_ERROR_STATUS
2600  *  0b0..An early termination from the device causes error IRQ.
2601  *  0b1..An AHB bus error causes error IRQ.
2602  */
2603 #define APBH_CTRL2_CH3_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
2604 
2605 #define APBH_CTRL2_CH4_ERROR_STATUS_MASK         (0x100000U)
2606 #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT        (20U)
2607 /*! CH4_ERROR_STATUS
2608  *  0b0..An early termination from the device causes error IRQ.
2609  *  0b1..An AHB bus error causes error IRQ.
2610  */
2611 #define APBH_CTRL2_CH4_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
2612 
2613 #define APBH_CTRL2_CH5_ERROR_STATUS_MASK         (0x200000U)
2614 #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT        (21U)
2615 /*! CH5_ERROR_STATUS
2616  *  0b0..An early termination from the device causes error IRQ.
2617  *  0b1..An AHB bus error causes error IRQ.
2618  */
2619 #define APBH_CTRL2_CH5_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
2620 
2621 #define APBH_CTRL2_CH6_ERROR_STATUS_MASK         (0x400000U)
2622 #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT        (22U)
2623 /*! CH6_ERROR_STATUS
2624  *  0b0..An early termination from the device causes error IRQ.
2625  *  0b1..An AHB bus error causes error IRQ.
2626  */
2627 #define APBH_CTRL2_CH6_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
2628 
2629 #define APBH_CTRL2_CH7_ERROR_STATUS_MASK         (0x800000U)
2630 #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT        (23U)
2631 /*! CH7_ERROR_STATUS
2632  *  0b0..An early termination from the device causes error IRQ.
2633  *  0b1..An AHB bus error causes error IRQ.
2634  */
2635 #define APBH_CTRL2_CH7_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
2636 
2637 #define APBH_CTRL2_CH8_ERROR_STATUS_MASK         (0x1000000U)
2638 #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT        (24U)
2639 /*! CH8_ERROR_STATUS
2640  *  0b0..An early termination from the device causes error IRQ.
2641  *  0b1..An AHB bus error causes error IRQ.
2642  */
2643 #define APBH_CTRL2_CH8_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
2644 
2645 #define APBH_CTRL2_CH9_ERROR_STATUS_MASK         (0x2000000U)
2646 #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT        (25U)
2647 /*! CH9_ERROR_STATUS
2648  *  0b0..An early termination from the device causes error IRQ.
2649  *  0b1..An AHB bus error causes error IRQ.
2650  */
2651 #define APBH_CTRL2_CH9_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
2652 
2653 #define APBH_CTRL2_CH10_ERROR_STATUS_MASK        (0x4000000U)
2654 #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT       (26U)
2655 /*! CH10_ERROR_STATUS
2656  *  0b0..An early termination from the device causes error IRQ.
2657  *  0b1..An AHB bus error causes error IRQ.
2658  */
2659 #define APBH_CTRL2_CH10_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
2660 
2661 #define APBH_CTRL2_CH11_ERROR_STATUS_MASK        (0x8000000U)
2662 #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT       (27U)
2663 /*! CH11_ERROR_STATUS
2664  *  0b0..An early termination from the device causes error IRQ.
2665  *  0b1..An AHB bus error causes error IRQ.
2666  */
2667 #define APBH_CTRL2_CH11_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
2668 
2669 #define APBH_CTRL2_CH12_ERROR_STATUS_MASK        (0x10000000U)
2670 #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT       (28U)
2671 /*! CH12_ERROR_STATUS
2672  *  0b0..An early termination from the device causes error IRQ.
2673  *  0b1..An AHB bus error causes error IRQ.
2674  */
2675 #define APBH_CTRL2_CH12_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
2676 
2677 #define APBH_CTRL2_CH13_ERROR_STATUS_MASK        (0x20000000U)
2678 #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT       (29U)
2679 /*! CH13_ERROR_STATUS
2680  *  0b0..An early termination from the device causes error IRQ.
2681  *  0b1..An AHB bus error causes error IRQ.
2682  */
2683 #define APBH_CTRL2_CH13_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
2684 
2685 #define APBH_CTRL2_CH14_ERROR_STATUS_MASK        (0x40000000U)
2686 #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT       (30U)
2687 /*! CH14_ERROR_STATUS
2688  *  0b0..An early termination from the device causes error IRQ.
2689  *  0b1..An AHB bus error causes error IRQ.
2690  */
2691 #define APBH_CTRL2_CH14_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
2692 
2693 #define APBH_CTRL2_CH15_ERROR_STATUS_MASK        (0x80000000U)
2694 #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT       (31U)
2695 /*! CH15_ERROR_STATUS
2696  *  0b0..An early termination from the device causes error IRQ.
2697  *  0b1..An AHB bus error causes error IRQ.
2698  */
2699 #define APBH_CTRL2_CH15_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
2700 /*! @} */
2701 
2702 /*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
2703 /*! @{ */
2704 
2705 #define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK        (0x1U)
2706 #define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT       (0U)
2707 #define APBH_CTRL2_SET_CH0_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
2708 
2709 #define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK        (0x2U)
2710 #define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT       (1U)
2711 #define APBH_CTRL2_SET_CH1_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
2712 
2713 #define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK        (0x4U)
2714 #define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT       (2U)
2715 #define APBH_CTRL2_SET_CH2_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
2716 
2717 #define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK        (0x8U)
2718 #define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT       (3U)
2719 #define APBH_CTRL2_SET_CH3_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
2720 
2721 #define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK        (0x10U)
2722 #define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT       (4U)
2723 #define APBH_CTRL2_SET_CH4_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
2724 
2725 #define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK        (0x20U)
2726 #define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT       (5U)
2727 #define APBH_CTRL2_SET_CH5_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
2728 
2729 #define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK        (0x40U)
2730 #define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT       (6U)
2731 #define APBH_CTRL2_SET_CH6_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
2732 
2733 #define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK        (0x80U)
2734 #define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT       (7U)
2735 #define APBH_CTRL2_SET_CH7_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
2736 
2737 #define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK        (0x100U)
2738 #define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT       (8U)
2739 #define APBH_CTRL2_SET_CH8_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
2740 
2741 #define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK        (0x200U)
2742 #define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT       (9U)
2743 #define APBH_CTRL2_SET_CH9_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
2744 
2745 #define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK       (0x400U)
2746 #define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT      (10U)
2747 #define APBH_CTRL2_SET_CH10_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
2748 
2749 #define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK       (0x800U)
2750 #define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT      (11U)
2751 #define APBH_CTRL2_SET_CH11_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
2752 
2753 #define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK       (0x1000U)
2754 #define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT      (12U)
2755 #define APBH_CTRL2_SET_CH12_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
2756 
2757 #define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK       (0x2000U)
2758 #define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT      (13U)
2759 #define APBH_CTRL2_SET_CH13_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
2760 
2761 #define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK       (0x4000U)
2762 #define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT      (14U)
2763 #define APBH_CTRL2_SET_CH14_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
2764 
2765 #define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK       (0x8000U)
2766 #define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT      (15U)
2767 #define APBH_CTRL2_SET_CH15_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
2768 
2769 #define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK     (0x10000U)
2770 #define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT    (16U)
2771 /*! CH0_ERROR_STATUS
2772  *  0b0..An early termination from the device causes error IRQ.
2773  *  0b1..An AHB bus error causes error IRQ.
2774  */
2775 #define APBH_CTRL2_SET_CH0_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
2776 
2777 #define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK     (0x20000U)
2778 #define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT    (17U)
2779 /*! CH1_ERROR_STATUS
2780  *  0b0..An early termination from the device causes error IRQ.
2781  *  0b1..An AHB bus error causes error IRQ.
2782  */
2783 #define APBH_CTRL2_SET_CH1_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
2784 
2785 #define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK     (0x40000U)
2786 #define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT    (18U)
2787 /*! CH2_ERROR_STATUS
2788  *  0b0..An early termination from the device causes error IRQ.
2789  *  0b1..An AHB bus error causes error IRQ.
2790  */
2791 #define APBH_CTRL2_SET_CH2_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
2792 
2793 #define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK     (0x80000U)
2794 #define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT    (19U)
2795 /*! CH3_ERROR_STATUS
2796  *  0b0..An early termination from the device causes error IRQ.
2797  *  0b1..An AHB bus error causes error IRQ.
2798  */
2799 #define APBH_CTRL2_SET_CH3_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
2800 
2801 #define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK     (0x100000U)
2802 #define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT    (20U)
2803 /*! CH4_ERROR_STATUS
2804  *  0b0..An early termination from the device causes error IRQ.
2805  *  0b1..An AHB bus error causes error IRQ.
2806  */
2807 #define APBH_CTRL2_SET_CH4_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
2808 
2809 #define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK     (0x200000U)
2810 #define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT    (21U)
2811 /*! CH5_ERROR_STATUS
2812  *  0b0..An early termination from the device causes error IRQ.
2813  *  0b1..An AHB bus error causes error IRQ.
2814  */
2815 #define APBH_CTRL2_SET_CH5_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
2816 
2817 #define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK     (0x400000U)
2818 #define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT    (22U)
2819 /*! CH6_ERROR_STATUS
2820  *  0b0..An early termination from the device causes error IRQ.
2821  *  0b1..An AHB bus error causes error IRQ.
2822  */
2823 #define APBH_CTRL2_SET_CH6_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
2824 
2825 #define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK     (0x800000U)
2826 #define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT    (23U)
2827 /*! CH7_ERROR_STATUS
2828  *  0b0..An early termination from the device causes error IRQ.
2829  *  0b1..An AHB bus error causes error IRQ.
2830  */
2831 #define APBH_CTRL2_SET_CH7_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
2832 
2833 #define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK     (0x1000000U)
2834 #define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT    (24U)
2835 /*! CH8_ERROR_STATUS
2836  *  0b0..An early termination from the device causes error IRQ.
2837  *  0b1..An AHB bus error causes error IRQ.
2838  */
2839 #define APBH_CTRL2_SET_CH8_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
2840 
2841 #define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK     (0x2000000U)
2842 #define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT    (25U)
2843 /*! CH9_ERROR_STATUS
2844  *  0b0..An early termination from the device causes error IRQ.
2845  *  0b1..An AHB bus error causes error IRQ.
2846  */
2847 #define APBH_CTRL2_SET_CH9_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
2848 
2849 #define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK    (0x4000000U)
2850 #define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT   (26U)
2851 /*! CH10_ERROR_STATUS
2852  *  0b0..An early termination from the device causes error IRQ.
2853  *  0b1..An AHB bus error causes error IRQ.
2854  */
2855 #define APBH_CTRL2_SET_CH10_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
2856 
2857 #define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK    (0x8000000U)
2858 #define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT   (27U)
2859 /*! CH11_ERROR_STATUS
2860  *  0b0..An early termination from the device causes error IRQ.
2861  *  0b1..An AHB bus error causes error IRQ.
2862  */
2863 #define APBH_CTRL2_SET_CH11_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
2864 
2865 #define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK    (0x10000000U)
2866 #define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT   (28U)
2867 /*! CH12_ERROR_STATUS
2868  *  0b0..An early termination from the device causes error IRQ.
2869  *  0b1..An AHB bus error causes error IRQ.
2870  */
2871 #define APBH_CTRL2_SET_CH12_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
2872 
2873 #define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK    (0x20000000U)
2874 #define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT   (29U)
2875 /*! CH13_ERROR_STATUS
2876  *  0b0..An early termination from the device causes error IRQ.
2877  *  0b1..An AHB bus error causes error IRQ.
2878  */
2879 #define APBH_CTRL2_SET_CH13_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
2880 
2881 #define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK    (0x40000000U)
2882 #define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT   (30U)
2883 /*! CH14_ERROR_STATUS
2884  *  0b0..An early termination from the device causes error IRQ.
2885  *  0b1..An AHB bus error causes error IRQ.
2886  */
2887 #define APBH_CTRL2_SET_CH14_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
2888 
2889 #define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK    (0x80000000U)
2890 #define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT   (31U)
2891 /*! CH15_ERROR_STATUS
2892  *  0b0..An early termination from the device causes error IRQ.
2893  *  0b1..An AHB bus error causes error IRQ.
2894  */
2895 #define APBH_CTRL2_SET_CH15_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
2896 /*! @} */
2897 
2898 /*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
2899 /*! @{ */
2900 
2901 #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK        (0x1U)
2902 #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT       (0U)
2903 #define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
2904 
2905 #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK        (0x2U)
2906 #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT       (1U)
2907 #define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
2908 
2909 #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK        (0x4U)
2910 #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT       (2U)
2911 #define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
2912 
2913 #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK        (0x8U)
2914 #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT       (3U)
2915 #define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
2916 
2917 #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK        (0x10U)
2918 #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT       (4U)
2919 #define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
2920 
2921 #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK        (0x20U)
2922 #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT       (5U)
2923 #define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
2924 
2925 #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK        (0x40U)
2926 #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT       (6U)
2927 #define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
2928 
2929 #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK        (0x80U)
2930 #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT       (7U)
2931 #define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
2932 
2933 #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK        (0x100U)
2934 #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT       (8U)
2935 #define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
2936 
2937 #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK        (0x200U)
2938 #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT       (9U)
2939 #define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
2940 
2941 #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK       (0x400U)
2942 #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT      (10U)
2943 #define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
2944 
2945 #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK       (0x800U)
2946 #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT      (11U)
2947 #define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
2948 
2949 #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK       (0x1000U)
2950 #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT      (12U)
2951 #define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
2952 
2953 #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK       (0x2000U)
2954 #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT      (13U)
2955 #define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
2956 
2957 #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK       (0x4000U)
2958 #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT      (14U)
2959 #define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
2960 
2961 #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK       (0x8000U)
2962 #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT      (15U)
2963 #define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
2964 
2965 #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK     (0x10000U)
2966 #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT    (16U)
2967 /*! CH0_ERROR_STATUS
2968  *  0b0..An early termination from the device causes error IRQ.
2969  *  0b1..An AHB bus error causes error IRQ.
2970  */
2971 #define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
2972 
2973 #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK     (0x20000U)
2974 #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT    (17U)
2975 /*! CH1_ERROR_STATUS
2976  *  0b0..An early termination from the device causes error IRQ.
2977  *  0b1..An AHB bus error causes error IRQ.
2978  */
2979 #define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
2980 
2981 #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK     (0x40000U)
2982 #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT    (18U)
2983 /*! CH2_ERROR_STATUS
2984  *  0b0..An early termination from the device causes error IRQ.
2985  *  0b1..An AHB bus error causes error IRQ.
2986  */
2987 #define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
2988 
2989 #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK     (0x80000U)
2990 #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT    (19U)
2991 /*! CH3_ERROR_STATUS
2992  *  0b0..An early termination from the device causes error IRQ.
2993  *  0b1..An AHB bus error causes error IRQ.
2994  */
2995 #define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
2996 
2997 #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK     (0x100000U)
2998 #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT    (20U)
2999 /*! CH4_ERROR_STATUS
3000  *  0b0..An early termination from the device causes error IRQ.
3001  *  0b1..An AHB bus error causes error IRQ.
3002  */
3003 #define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
3004 
3005 #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK     (0x200000U)
3006 #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT    (21U)
3007 /*! CH5_ERROR_STATUS
3008  *  0b0..An early termination from the device causes error IRQ.
3009  *  0b1..An AHB bus error causes error IRQ.
3010  */
3011 #define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
3012 
3013 #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK     (0x400000U)
3014 #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT    (22U)
3015 /*! CH6_ERROR_STATUS
3016  *  0b0..An early termination from the device causes error IRQ.
3017  *  0b1..An AHB bus error causes error IRQ.
3018  */
3019 #define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
3020 
3021 #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK     (0x800000U)
3022 #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT    (23U)
3023 /*! CH7_ERROR_STATUS
3024  *  0b0..An early termination from the device causes error IRQ.
3025  *  0b1..An AHB bus error causes error IRQ.
3026  */
3027 #define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
3028 
3029 #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK     (0x1000000U)
3030 #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT    (24U)
3031 /*! CH8_ERROR_STATUS
3032  *  0b0..An early termination from the device causes error IRQ.
3033  *  0b1..An AHB bus error causes error IRQ.
3034  */
3035 #define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
3036 
3037 #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK     (0x2000000U)
3038 #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT    (25U)
3039 /*! CH9_ERROR_STATUS
3040  *  0b0..An early termination from the device causes error IRQ.
3041  *  0b1..An AHB bus error causes error IRQ.
3042  */
3043 #define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
3044 
3045 #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK    (0x4000000U)
3046 #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT   (26U)
3047 /*! CH10_ERROR_STATUS
3048  *  0b0..An early termination from the device causes error IRQ.
3049  *  0b1..An AHB bus error causes error IRQ.
3050  */
3051 #define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
3052 
3053 #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK    (0x8000000U)
3054 #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT   (27U)
3055 /*! CH11_ERROR_STATUS
3056  *  0b0..An early termination from the device causes error IRQ.
3057  *  0b1..An AHB bus error causes error IRQ.
3058  */
3059 #define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
3060 
3061 #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK    (0x10000000U)
3062 #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT   (28U)
3063 /*! CH12_ERROR_STATUS
3064  *  0b0..An early termination from the device causes error IRQ.
3065  *  0b1..An AHB bus error causes error IRQ.
3066  */
3067 #define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
3068 
3069 #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK    (0x20000000U)
3070 #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT   (29U)
3071 /*! CH13_ERROR_STATUS
3072  *  0b0..An early termination from the device causes error IRQ.
3073  *  0b1..An AHB bus error causes error IRQ.
3074  */
3075 #define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
3076 
3077 #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK    (0x40000000U)
3078 #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT   (30U)
3079 /*! CH14_ERROR_STATUS
3080  *  0b0..An early termination from the device causes error IRQ.
3081  *  0b1..An AHB bus error causes error IRQ.
3082  */
3083 #define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
3084 
3085 #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK    (0x80000000U)
3086 #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT   (31U)
3087 /*! CH15_ERROR_STATUS
3088  *  0b0..An early termination from the device causes error IRQ.
3089  *  0b1..An AHB bus error causes error IRQ.
3090  */
3091 #define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
3092 /*! @} */
3093 
3094 /*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
3095 /*! @{ */
3096 
3097 #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK        (0x1U)
3098 #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT       (0U)
3099 #define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
3100 
3101 #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK        (0x2U)
3102 #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT       (1U)
3103 #define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
3104 
3105 #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK        (0x4U)
3106 #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT       (2U)
3107 #define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
3108 
3109 #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK        (0x8U)
3110 #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT       (3U)
3111 #define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
3112 
3113 #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK        (0x10U)
3114 #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT       (4U)
3115 #define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
3116 
3117 #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK        (0x20U)
3118 #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT       (5U)
3119 #define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
3120 
3121 #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK        (0x40U)
3122 #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT       (6U)
3123 #define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
3124 
3125 #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK        (0x80U)
3126 #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT       (7U)
3127 #define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
3128 
3129 #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK        (0x100U)
3130 #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT       (8U)
3131 #define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
3132 
3133 #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK        (0x200U)
3134 #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT       (9U)
3135 #define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
3136 
3137 #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK       (0x400U)
3138 #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT      (10U)
3139 #define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
3140 
3141 #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK       (0x800U)
3142 #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT      (11U)
3143 #define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
3144 
3145 #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK       (0x1000U)
3146 #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT      (12U)
3147 #define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
3148 
3149 #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK       (0x2000U)
3150 #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT      (13U)
3151 #define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
3152 
3153 #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK       (0x4000U)
3154 #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT      (14U)
3155 #define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
3156 
3157 #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK       (0x8000U)
3158 #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT      (15U)
3159 #define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
3160 
3161 #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK     (0x10000U)
3162 #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT    (16U)
3163 /*! CH0_ERROR_STATUS
3164  *  0b0..An early termination from the device causes error IRQ.
3165  *  0b1..An AHB bus error causes error IRQ.
3166  */
3167 #define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
3168 
3169 #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK     (0x20000U)
3170 #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT    (17U)
3171 /*! CH1_ERROR_STATUS
3172  *  0b0..An early termination from the device causes error IRQ.
3173  *  0b1..An AHB bus error causes error IRQ.
3174  */
3175 #define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
3176 
3177 #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK     (0x40000U)
3178 #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT    (18U)
3179 /*! CH2_ERROR_STATUS
3180  *  0b0..An early termination from the device causes error IRQ.
3181  *  0b1..An AHB bus error causes error IRQ.
3182  */
3183 #define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
3184 
3185 #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK     (0x80000U)
3186 #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT    (19U)
3187 /*! CH3_ERROR_STATUS
3188  *  0b0..An early termination from the device causes error IRQ.
3189  *  0b1..An AHB bus error causes error IRQ.
3190  */
3191 #define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
3192 
3193 #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK     (0x100000U)
3194 #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT    (20U)
3195 /*! CH4_ERROR_STATUS
3196  *  0b0..An early termination from the device causes error IRQ.
3197  *  0b1..An AHB bus error causes error IRQ.
3198  */
3199 #define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
3200 
3201 #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK     (0x200000U)
3202 #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT    (21U)
3203 /*! CH5_ERROR_STATUS
3204  *  0b0..An early termination from the device causes error IRQ.
3205  *  0b1..An AHB bus error causes error IRQ.
3206  */
3207 #define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
3208 
3209 #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK     (0x400000U)
3210 #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT    (22U)
3211 /*! CH6_ERROR_STATUS
3212  *  0b0..An early termination from the device causes error IRQ.
3213  *  0b1..An AHB bus error causes error IRQ.
3214  */
3215 #define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
3216 
3217 #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK     (0x800000U)
3218 #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT    (23U)
3219 /*! CH7_ERROR_STATUS
3220  *  0b0..An early termination from the device causes error IRQ.
3221  *  0b1..An AHB bus error causes error IRQ.
3222  */
3223 #define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
3224 
3225 #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK     (0x1000000U)
3226 #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT    (24U)
3227 /*! CH8_ERROR_STATUS
3228  *  0b0..An early termination from the device causes error IRQ.
3229  *  0b1..An AHB bus error causes error IRQ.
3230  */
3231 #define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
3232 
3233 #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK     (0x2000000U)
3234 #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT    (25U)
3235 /*! CH9_ERROR_STATUS
3236  *  0b0..An early termination from the device causes error IRQ.
3237  *  0b1..An AHB bus error causes error IRQ.
3238  */
3239 #define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
3240 
3241 #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK    (0x4000000U)
3242 #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT   (26U)
3243 /*! CH10_ERROR_STATUS
3244  *  0b0..An early termination from the device causes error IRQ.
3245  *  0b1..An AHB bus error causes error IRQ.
3246  */
3247 #define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
3248 
3249 #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK    (0x8000000U)
3250 #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT   (27U)
3251 /*! CH11_ERROR_STATUS
3252  *  0b0..An early termination from the device causes error IRQ.
3253  *  0b1..An AHB bus error causes error IRQ.
3254  */
3255 #define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
3256 
3257 #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK    (0x10000000U)
3258 #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT   (28U)
3259 /*! CH12_ERROR_STATUS
3260  *  0b0..An early termination from the device causes error IRQ.
3261  *  0b1..An AHB bus error causes error IRQ.
3262  */
3263 #define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
3264 
3265 #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK    (0x20000000U)
3266 #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT   (29U)
3267 /*! CH13_ERROR_STATUS
3268  *  0b0..An early termination from the device causes error IRQ.
3269  *  0b1..An AHB bus error causes error IRQ.
3270  */
3271 #define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
3272 
3273 #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK    (0x40000000U)
3274 #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT   (30U)
3275 /*! CH14_ERROR_STATUS
3276  *  0b0..An early termination from the device causes error IRQ.
3277  *  0b1..An AHB bus error causes error IRQ.
3278  */
3279 #define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
3280 
3281 #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK    (0x80000000U)
3282 #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT   (31U)
3283 /*! CH15_ERROR_STATUS
3284  *  0b0..An early termination from the device causes error IRQ.
3285  *  0b1..An AHB bus error causes error IRQ.
3286  */
3287 #define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
3288 /*! @} */
3289 
3290 /*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
3291 /*! @{ */
3292 
3293 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK    (0xFFFFU)
3294 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT   (0U)
3295 /*! FREEZE_CHANNEL
3296  *  0b0000000000000001..NAND0
3297  *  0b0000000000000010..NAND1
3298  *  0b0000000000000100..NAND2
3299  *  0b0000000000001000..NAND3
3300  *  0b0000000000010000..NAND4
3301  *  0b0000000000100000..NAND5
3302  *  0b0000000001000000..NAND6
3303  *  0b0000000010000000..NAND7
3304  *  0b0000000100000000..SSP
3305  */
3306 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
3307 
3308 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK     (0xFFFF0000U)
3309 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT    (16U)
3310 /*! RESET_CHANNEL
3311  *  0b0000000000000001..NAND0
3312  *  0b0000000000000010..NAND1
3313  *  0b0000000000000100..NAND2
3314  *  0b0000000000001000..NAND3
3315  *  0b0000000000010000..NAND4
3316  *  0b0000000000100000..NAND5
3317  *  0b0000000001000000..NAND6
3318  *  0b0000000010000000..NAND7
3319  *  0b0000000100000000..SSP
3320  */
3321 #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
3322 /*! @} */
3323 
3324 /*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
3325 /*! @{ */
3326 
3327 #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
3328 #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
3329 /*! FREEZE_CHANNEL
3330  *  0b0000000000000001..NAND0
3331  *  0b0000000000000010..NAND1
3332  *  0b0000000000000100..NAND2
3333  *  0b0000000000001000..NAND3
3334  *  0b0000000000010000..NAND4
3335  *  0b0000000000100000..NAND5
3336  *  0b0000000001000000..NAND6
3337  *  0b0000000010000000..NAND7
3338  *  0b0000000100000000..SSP
3339  */
3340 #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
3341 
3342 #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
3343 #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
3344 /*! RESET_CHANNEL
3345  *  0b0000000000000001..NAND0
3346  *  0b0000000000000010..NAND1
3347  *  0b0000000000000100..NAND2
3348  *  0b0000000000001000..NAND3
3349  *  0b0000000000010000..NAND4
3350  *  0b0000000000100000..NAND5
3351  *  0b0000000001000000..NAND6
3352  *  0b0000000010000000..NAND7
3353  *  0b0000000100000000..SSP
3354  */
3355 #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
3356 /*! @} */
3357 
3358 /*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
3359 /*! @{ */
3360 
3361 #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
3362 #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
3363 /*! FREEZE_CHANNEL
3364  *  0b0000000000000001..NAND0
3365  *  0b0000000000000010..NAND1
3366  *  0b0000000000000100..NAND2
3367  *  0b0000000000001000..NAND3
3368  *  0b0000000000010000..NAND4
3369  *  0b0000000000100000..NAND5
3370  *  0b0000000001000000..NAND6
3371  *  0b0000000010000000..NAND7
3372  *  0b0000000100000000..SSP
3373  */
3374 #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
3375 
3376 #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
3377 #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
3378 /*! RESET_CHANNEL
3379  *  0b0000000000000001..NAND0
3380  *  0b0000000000000010..NAND1
3381  *  0b0000000000000100..NAND2
3382  *  0b0000000000001000..NAND3
3383  *  0b0000000000010000..NAND4
3384  *  0b0000000000100000..NAND5
3385  *  0b0000000001000000..NAND6
3386  *  0b0000000010000000..NAND7
3387  *  0b0000000100000000..SSP
3388  */
3389 #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
3390 /*! @} */
3391 
3392 /*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
3393 /*! @{ */
3394 
3395 #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
3396 #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
3397 /*! FREEZE_CHANNEL
3398  *  0b0000000000000001..NAND0
3399  *  0b0000000000000010..NAND1
3400  *  0b0000000000000100..NAND2
3401  *  0b0000000000001000..NAND3
3402  *  0b0000000000010000..NAND4
3403  *  0b0000000000100000..NAND5
3404  *  0b0000000001000000..NAND6
3405  *  0b0000000010000000..NAND7
3406  *  0b0000000100000000..SSP
3407  */
3408 #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
3409 
3410 #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
3411 #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
3412 /*! RESET_CHANNEL
3413  *  0b0000000000000001..NAND0
3414  *  0b0000000000000010..NAND1
3415  *  0b0000000000000100..NAND2
3416  *  0b0000000000001000..NAND3
3417  *  0b0000000000010000..NAND4
3418  *  0b0000000000100000..NAND5
3419  *  0b0000000001000000..NAND6
3420  *  0b0000000010000000..NAND7
3421  *  0b0000000100000000..SSP
3422  */
3423 #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
3424 /*! @} */
3425 
3426 /*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
3427 /*! @{ */
3428 
3429 #define APBH_DEVSEL_CH0_MASK                     (0x3U)
3430 #define APBH_DEVSEL_CH0_SHIFT                    (0U)
3431 #define APBH_DEVSEL_CH0(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
3432 
3433 #define APBH_DEVSEL_CH1_MASK                     (0xCU)
3434 #define APBH_DEVSEL_CH1_SHIFT                    (2U)
3435 #define APBH_DEVSEL_CH1(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
3436 
3437 #define APBH_DEVSEL_CH2_MASK                     (0x30U)
3438 #define APBH_DEVSEL_CH2_SHIFT                    (4U)
3439 #define APBH_DEVSEL_CH2(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
3440 
3441 #define APBH_DEVSEL_CH3_MASK                     (0xC0U)
3442 #define APBH_DEVSEL_CH3_SHIFT                    (6U)
3443 #define APBH_DEVSEL_CH3(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
3444 
3445 #define APBH_DEVSEL_CH4_MASK                     (0x300U)
3446 #define APBH_DEVSEL_CH4_SHIFT                    (8U)
3447 #define APBH_DEVSEL_CH4(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
3448 
3449 #define APBH_DEVSEL_CH5_MASK                     (0xC00U)
3450 #define APBH_DEVSEL_CH5_SHIFT                    (10U)
3451 #define APBH_DEVSEL_CH5(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
3452 
3453 #define APBH_DEVSEL_CH6_MASK                     (0x3000U)
3454 #define APBH_DEVSEL_CH6_SHIFT                    (12U)
3455 #define APBH_DEVSEL_CH6(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
3456 
3457 #define APBH_DEVSEL_CH7_MASK                     (0xC000U)
3458 #define APBH_DEVSEL_CH7_SHIFT                    (14U)
3459 #define APBH_DEVSEL_CH7(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
3460 
3461 #define APBH_DEVSEL_CH8_MASK                     (0x30000U)
3462 #define APBH_DEVSEL_CH8_SHIFT                    (16U)
3463 #define APBH_DEVSEL_CH8(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
3464 
3465 #define APBH_DEVSEL_CH9_MASK                     (0xC0000U)
3466 #define APBH_DEVSEL_CH9_SHIFT                    (18U)
3467 #define APBH_DEVSEL_CH9(x)                       (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
3468 
3469 #define APBH_DEVSEL_CH10_MASK                    (0x300000U)
3470 #define APBH_DEVSEL_CH10_SHIFT                   (20U)
3471 #define APBH_DEVSEL_CH10(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
3472 
3473 #define APBH_DEVSEL_CH11_MASK                    (0xC00000U)
3474 #define APBH_DEVSEL_CH11_SHIFT                   (22U)
3475 #define APBH_DEVSEL_CH11(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
3476 
3477 #define APBH_DEVSEL_CH12_MASK                    (0x3000000U)
3478 #define APBH_DEVSEL_CH12_SHIFT                   (24U)
3479 #define APBH_DEVSEL_CH12(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
3480 
3481 #define APBH_DEVSEL_CH13_MASK                    (0xC000000U)
3482 #define APBH_DEVSEL_CH13_SHIFT                   (26U)
3483 #define APBH_DEVSEL_CH13(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
3484 
3485 #define APBH_DEVSEL_CH14_MASK                    (0x30000000U)
3486 #define APBH_DEVSEL_CH14_SHIFT                   (28U)
3487 #define APBH_DEVSEL_CH14(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
3488 
3489 #define APBH_DEVSEL_CH15_MASK                    (0xC0000000U)
3490 #define APBH_DEVSEL_CH15_SHIFT                   (30U)
3491 #define APBH_DEVSEL_CH15(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
3492 /*! @} */
3493 
3494 /*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
3495 /*! @{ */
3496 
3497 #define APBH_DMA_BURST_SIZE_CH0_MASK             (0x3U)
3498 #define APBH_DMA_BURST_SIZE_CH0_SHIFT            (0U)
3499 #define APBH_DMA_BURST_SIZE_CH0(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
3500 
3501 #define APBH_DMA_BURST_SIZE_CH1_MASK             (0xCU)
3502 #define APBH_DMA_BURST_SIZE_CH1_SHIFT            (2U)
3503 #define APBH_DMA_BURST_SIZE_CH1(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
3504 
3505 #define APBH_DMA_BURST_SIZE_CH2_MASK             (0x30U)
3506 #define APBH_DMA_BURST_SIZE_CH2_SHIFT            (4U)
3507 #define APBH_DMA_BURST_SIZE_CH2(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
3508 
3509 #define APBH_DMA_BURST_SIZE_CH3_MASK             (0xC0U)
3510 #define APBH_DMA_BURST_SIZE_CH3_SHIFT            (6U)
3511 #define APBH_DMA_BURST_SIZE_CH3(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
3512 
3513 #define APBH_DMA_BURST_SIZE_CH4_MASK             (0x300U)
3514 #define APBH_DMA_BURST_SIZE_CH4_SHIFT            (8U)
3515 #define APBH_DMA_BURST_SIZE_CH4(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
3516 
3517 #define APBH_DMA_BURST_SIZE_CH5_MASK             (0xC00U)
3518 #define APBH_DMA_BURST_SIZE_CH5_SHIFT            (10U)
3519 #define APBH_DMA_BURST_SIZE_CH5(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
3520 
3521 #define APBH_DMA_BURST_SIZE_CH6_MASK             (0x3000U)
3522 #define APBH_DMA_BURST_SIZE_CH6_SHIFT            (12U)
3523 #define APBH_DMA_BURST_SIZE_CH6(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
3524 
3525 #define APBH_DMA_BURST_SIZE_CH7_MASK             (0xC000U)
3526 #define APBH_DMA_BURST_SIZE_CH7_SHIFT            (14U)
3527 #define APBH_DMA_BURST_SIZE_CH7(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
3528 
3529 #define APBH_DMA_BURST_SIZE_CH8_MASK             (0x30000U)
3530 #define APBH_DMA_BURST_SIZE_CH8_SHIFT            (16U)
3531 /*! CH8
3532  *  0b00..BURST0
3533  *  0b01..BURST4
3534  *  0b10..BURST8
3535  */
3536 #define APBH_DMA_BURST_SIZE_CH8(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
3537 
3538 #define APBH_DMA_BURST_SIZE_CH9_MASK             (0xC0000U)
3539 #define APBH_DMA_BURST_SIZE_CH9_SHIFT            (18U)
3540 #define APBH_DMA_BURST_SIZE_CH9(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
3541 
3542 #define APBH_DMA_BURST_SIZE_CH10_MASK            (0x300000U)
3543 #define APBH_DMA_BURST_SIZE_CH10_SHIFT           (20U)
3544 #define APBH_DMA_BURST_SIZE_CH10(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
3545 
3546 #define APBH_DMA_BURST_SIZE_CH11_MASK            (0xC00000U)
3547 #define APBH_DMA_BURST_SIZE_CH11_SHIFT           (22U)
3548 #define APBH_DMA_BURST_SIZE_CH11(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
3549 
3550 #define APBH_DMA_BURST_SIZE_CH12_MASK            (0x3000000U)
3551 #define APBH_DMA_BURST_SIZE_CH12_SHIFT           (24U)
3552 #define APBH_DMA_BURST_SIZE_CH12(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
3553 
3554 #define APBH_DMA_BURST_SIZE_CH13_MASK            (0xC000000U)
3555 #define APBH_DMA_BURST_SIZE_CH13_SHIFT           (26U)
3556 #define APBH_DMA_BURST_SIZE_CH13(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
3557 
3558 #define APBH_DMA_BURST_SIZE_CH14_MASK            (0x30000000U)
3559 #define APBH_DMA_BURST_SIZE_CH14_SHIFT           (28U)
3560 #define APBH_DMA_BURST_SIZE_CH14(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
3561 
3562 #define APBH_DMA_BURST_SIZE_CH15_MASK            (0xC0000000U)
3563 #define APBH_DMA_BURST_SIZE_CH15_SHIFT           (30U)
3564 #define APBH_DMA_BURST_SIZE_CH15(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
3565 /*! @} */
3566 
3567 /*! @name DEBUG - AHB to APBH DMA Debug Register */
3568 /*! @{ */
3569 
3570 #define APBH_DEBUG_GPMI_ONE_FIFO_MASK            (0x1U)
3571 #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT           (0U)
3572 #define APBH_DEBUG_GPMI_ONE_FIFO(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
3573 /*! @} */
3574 
3575 /*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3576 /*! @{ */
3577 
3578 #define APBH_CH_CURCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
3579 #define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT          (0U)
3580 #define APBH_CH_CURCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
3581 /*! @} */
3582 
3583 /* The count of APBH_CH_CURCMDAR */
3584 #define APBH_CH_CURCMDAR_COUNT                   (16U)
3585 
3586 /*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3587 /*! @{ */
3588 
3589 #define APBH_CH_NXTCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
3590 #define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT          (0U)
3591 #define APBH_CH_NXTCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
3592 /*! @} */
3593 
3594 /* The count of APBH_CH_NXTCMDAR */
3595 #define APBH_CH_NXTCMDAR_COUNT                   (16U)
3596 
3597 /*! @name CH_CMD - APBH DMA Channel n Command Register */
3598 /*! @{ */
3599 
3600 #define APBH_CH_CMD_COMMAND_MASK                 (0x3U)
3601 #define APBH_CH_CMD_COMMAND_SHIFT                (0U)
3602 /*! COMMAND
3603  *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3604  *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3605  *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3606  *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
3607  *        device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
3608  *        pointer if the peripheral sense line is false.
3609  */
3610 #define APBH_CH_CMD_COMMAND(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
3611 
3612 #define APBH_CH_CMD_CHAIN_MASK                   (0x4U)
3613 #define APBH_CH_CMD_CHAIN_SHIFT                  (2U)
3614 #define APBH_CH_CMD_CHAIN(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
3615 
3616 #define APBH_CH_CMD_IRQONCMPLT_MASK              (0x8U)
3617 #define APBH_CH_CMD_IRQONCMPLT_SHIFT             (3U)
3618 #define APBH_CH_CMD_IRQONCMPLT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
3619 
3620 #define APBH_CH_CMD_NANDLOCK_MASK                (0x10U)
3621 #define APBH_CH_CMD_NANDLOCK_SHIFT               (4U)
3622 #define APBH_CH_CMD_NANDLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
3623 
3624 #define APBH_CH_CMD_NANDWAIT4READY_MASK          (0x20U)
3625 #define APBH_CH_CMD_NANDWAIT4READY_SHIFT         (5U)
3626 #define APBH_CH_CMD_NANDWAIT4READY(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
3627 
3628 #define APBH_CH_CMD_SEMAPHORE_MASK               (0x40U)
3629 #define APBH_CH_CMD_SEMAPHORE_SHIFT              (6U)
3630 #define APBH_CH_CMD_SEMAPHORE(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
3631 
3632 #define APBH_CH_CMD_WAIT4ENDCMD_MASK             (0x80U)
3633 #define APBH_CH_CMD_WAIT4ENDCMD_SHIFT            (7U)
3634 #define APBH_CH_CMD_WAIT4ENDCMD(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
3635 
3636 #define APBH_CH_CMD_HALTONTERMINATE_MASK         (0x100U)
3637 #define APBH_CH_CMD_HALTONTERMINATE_SHIFT        (8U)
3638 #define APBH_CH_CMD_HALTONTERMINATE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
3639 
3640 #define APBH_CH_CMD_CMDWORDS_MASK                (0xF000U)
3641 #define APBH_CH_CMD_CMDWORDS_SHIFT               (12U)
3642 #define APBH_CH_CMD_CMDWORDS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
3643 
3644 #define APBH_CH_CMD_XFER_COUNT_MASK              (0xFFFF0000U)
3645 #define APBH_CH_CMD_XFER_COUNT_SHIFT             (16U)
3646 #define APBH_CH_CMD_XFER_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
3647 /*! @} */
3648 
3649 /* The count of APBH_CH_CMD */
3650 #define APBH_CH_CMD_COUNT                        (16U)
3651 
3652 /*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
3653 /*! @{ */
3654 
3655 #define APBH_CH_BAR_ADDRESS_MASK                 (0xFFFFFFFFU)
3656 #define APBH_CH_BAR_ADDRESS_SHIFT                (0U)
3657 #define APBH_CH_BAR_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
3658 /*! @} */
3659 
3660 /* The count of APBH_CH_BAR */
3661 #define APBH_CH_BAR_COUNT                        (16U)
3662 
3663 /*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
3664 /*! @{ */
3665 
3666 #define APBH_CH_SEMA_INCREMENT_SEMA_MASK         (0xFFU)
3667 #define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT        (0U)
3668 #define APBH_CH_SEMA_INCREMENT_SEMA(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
3669 
3670 #define APBH_CH_SEMA_PHORE_MASK                  (0xFF0000U)
3671 #define APBH_CH_SEMA_PHORE_SHIFT                 (16U)
3672 #define APBH_CH_SEMA_PHORE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
3673 /*! @} */
3674 
3675 /* The count of APBH_CH_SEMA */
3676 #define APBH_CH_SEMA_COUNT                       (16U)
3677 
3678 /*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3679 /*! @{ */
3680 
3681 #define APBH_CH_DEBUG1_STATEMACHINE_MASK         (0x1FU)
3682 #define APBH_CH_DEBUG1_STATEMACHINE_SHIFT        (0U)
3683 /*! STATEMACHINE
3684  *  0b00000..This is the idle state of the DMA state machine.
3685  *  0b00001..State in which the DMA is waiting to receive the first word of a command.
3686  *  0b00010..State in which the DMA is waiting to receive the third word of a command.
3687  *  0b00011..State in which the DMA is waiting to receive the second word of a command.
3688  *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3689  *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3690  *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
3691  *           PIO words when PIO count is greater than 1.
3692  *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3693  *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3694  *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3695  *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3696  *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3697  *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3698  *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3699  *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3700  *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3701  *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3702  *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
3703  *           effectively halts. A channel reset is required to exit this state
3704  *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3705  *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
3706  *           indicates that the external device is ready.
3707  */
3708 #define APBH_CH_DEBUG1_STATEMACHINE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
3709 
3710 #define APBH_CH_DEBUG1_RSVD1_MASK                (0xFFFE0U)
3711 #define APBH_CH_DEBUG1_RSVD1_SHIFT               (5U)
3712 #define APBH_CH_DEBUG1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
3713 
3714 #define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK         (0x100000U)
3715 #define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT        (20U)
3716 #define APBH_CH_DEBUG1_WR_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
3717 
3718 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK        (0x200000U)
3719 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT       (21U)
3720 #define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
3721 
3722 #define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK         (0x400000U)
3723 #define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT        (22U)
3724 #define APBH_CH_DEBUG1_RD_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
3725 
3726 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK        (0x800000U)
3727 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT       (23U)
3728 #define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
3729 
3730 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK     (0x1000000U)
3731 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT    (24U)
3732 #define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
3733 
3734 #define APBH_CH_DEBUG1_LOCK_MASK                 (0x2000000U)
3735 #define APBH_CH_DEBUG1_LOCK_SHIFT                (25U)
3736 #define APBH_CH_DEBUG1_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
3737 
3738 #define APBH_CH_DEBUG1_READY_MASK                (0x4000000U)
3739 #define APBH_CH_DEBUG1_READY_SHIFT               (26U)
3740 #define APBH_CH_DEBUG1_READY(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
3741 
3742 #define APBH_CH_DEBUG1_SENSE_MASK                (0x8000000U)
3743 #define APBH_CH_DEBUG1_SENSE_SHIFT               (27U)
3744 #define APBH_CH_DEBUG1_SENSE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
3745 
3746 #define APBH_CH_DEBUG1_END_MASK                  (0x10000000U)
3747 #define APBH_CH_DEBUG1_END_SHIFT                 (28U)
3748 #define APBH_CH_DEBUG1_END(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
3749 
3750 #define APBH_CH_DEBUG1_KICK_MASK                 (0x20000000U)
3751 #define APBH_CH_DEBUG1_KICK_SHIFT                (29U)
3752 #define APBH_CH_DEBUG1_KICK(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
3753 
3754 #define APBH_CH_DEBUG1_BURST_MASK                (0x40000000U)
3755 #define APBH_CH_DEBUG1_BURST_SHIFT               (30U)
3756 #define APBH_CH_DEBUG1_BURST(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
3757 
3758 #define APBH_CH_DEBUG1_REQ_MASK                  (0x80000000U)
3759 #define APBH_CH_DEBUG1_REQ_SHIFT                 (31U)
3760 #define APBH_CH_DEBUG1_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
3761 /*! @} */
3762 
3763 /* The count of APBH_CH_DEBUG1 */
3764 #define APBH_CH_DEBUG1_COUNT                     (16U)
3765 
3766 /*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3767 /*! @{ */
3768 
3769 #define APBH_CH_DEBUG2_AHB_BYTES_MASK            (0xFFFFU)
3770 #define APBH_CH_DEBUG2_AHB_BYTES_SHIFT           (0U)
3771 #define APBH_CH_DEBUG2_AHB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
3772 
3773 #define APBH_CH_DEBUG2_APB_BYTES_MASK            (0xFFFF0000U)
3774 #define APBH_CH_DEBUG2_APB_BYTES_SHIFT           (16U)
3775 #define APBH_CH_DEBUG2_APB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
3776 /*! @} */
3777 
3778 /* The count of APBH_CH_DEBUG2 */
3779 #define APBH_CH_DEBUG2_COUNT                     (16U)
3780 
3781 /*! @name VERSION - APBH Bridge Version Register */
3782 /*! @{ */
3783 
3784 #define APBH_VERSION_STEP_MASK                   (0xFFFFU)
3785 #define APBH_VERSION_STEP_SHIFT                  (0U)
3786 #define APBH_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
3787 
3788 #define APBH_VERSION_MINOR_MASK                  (0xFF0000U)
3789 #define APBH_VERSION_MINOR_SHIFT                 (16U)
3790 #define APBH_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
3791 
3792 #define APBH_VERSION_MAJOR_MASK                  (0xFF000000U)
3793 #define APBH_VERSION_MAJOR_SHIFT                 (24U)
3794 #define APBH_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
3795 /*! @} */
3796 
3797 
3798 /*!
3799  * @}
3800  */ /* end of group APBH_Register_Masks */
3801 
3802 
3803 /* APBH - Peripheral instance base addresses */
3804 /** Peripheral APBH base address */
3805 #define APBH_BASE                                (0x33000000u)
3806 /** Peripheral APBH base pointer */
3807 #define APBH                                     ((APBH_Type *)APBH_BASE)
3808 /** Array initializer of APBH peripheral base addresses */
3809 #define APBH_BASE_ADDRS                          { APBH_BASE }
3810 /** Array initializer of APBH peripheral base pointers */
3811 #define APBH_BASE_PTRS                           { APBH }
3812 /** Interrupt vectors for the APBH peripheral type */
3813 #define APBH_IRQS                                { APBHDMA_IRQn }
3814 
3815 /*!
3816  * @}
3817  */ /* end of group APBH_Peripheral_Access_Layer */
3818 
3819 
3820 /* ----------------------------------------------------------------------------
3821    -- ASRC Peripheral Access Layer
3822    ---------------------------------------------------------------------------- */
3823 
3824 /*!
3825  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
3826  * @{
3827  */
3828 
3829 /** ASRC - Register Layout Typedef */
3830 typedef struct {
3831   __O  uint32_t WRFIFO[4];                         /**< ASRC Input Write FIFO, array offset: 0x0, array step: 0x4 */
3832   __I  uint32_t RDFIFO[4];                         /**< ASRC Output Read FIFO, array offset: 0x10, array step: 0x4 */
3833   __IO uint32_t CTX_CTRL[4];                       /**< ASRC Context Control, array offset: 0x20, array step: 0x4 */
3834   __IO uint32_t CTX_CTRL_EXT1[4];                  /**< ASRC Context Control Extended 1, array offset: 0x30, array step: 0x4 */
3835   __IO uint32_t CTX_CTRL_EXT2[4];                  /**< ASRC Context Control Extended 2, array offset: 0x40, array step: 0x4 */
3836   __IO uint32_t CTRL_IN_ACCESS[4];                 /**< ASRC Control Input Access, array offset: 0x50, array step: 0x4 */
3837   __IO uint32_t PROC_CTRL_SLOT0_R0[4];             /**< ASRC Datapath Processor Control Slot0 Register0, array offset: 0x60, array step: 0x4 */
3838   __IO uint32_t PROC_CTRL_SLOT0_R1[4];             /**< ASRC Datapath Processor Control Slot0 Register1, array offset: 0x70, array step: 0x4 */
3839   __IO uint32_t PROC_CTRL_SLOT0_R2[4];             /**< ASRC Datapath Processor Control Slot0 Register2, array offset: 0x80, array step: 0x4 */
3840   __IO uint32_t PROC_CTRL_SLOT0_R3[4];             /**< ASRC Datapath Processor Control Slot0 Register3, array offset: 0x90, array step: 0x4 */
3841   __IO uint32_t PROC_CTRL_SLOT1_R0[4];             /**< ASRC Datapath Processor Control Slot1 Register0, array offset: 0xA0, array step: 0x4 */
3842   __IO uint32_t PROC_CTRL_SLOT1_R1[4];             /**< ASRC Datapath Processor Control SLOT1 Register1, array offset: 0xB0, array step: 0x4 */
3843   __IO uint32_t PROC_CTRL_SLOT1_R2[4];             /**< ASRC Datapath Processor Control SLOT1 Register2, array offset: 0xC0, array step: 0x4 */
3844   __IO uint32_t PROC_CTRL_SLOT1_R3[4];             /**< ASRC Datapath Processor Control SLOT1 Register3, array offset: 0xD0, array step: 0x4 */
3845   __IO uint32_t CTX_OUT_CTRL[4];                   /**< ASRC Context Output Control, array offset: 0xE0, array step: 0x4 */
3846   __IO uint32_t CTRL_OUT_ACCESS[4];                /**< ASRC Control Output Access, array offset: 0xF0, array step: 0x4 */
3847   __I  uint32_t SAMPLE_FIFO_STATUS[4];             /**< ASRC Sample FIFO Status, array offset: 0x100, array step: 0x4 */
3848   struct {                                         /* offset: 0x110, array step: 0x8 */
3849     __IO uint32_t RS_RATIO_LOW;                      /**< ASRC Resampling Ratio Low, array offset: 0x110, array step: 0x8 */
3850     __IO uint32_t RS_RATIO_HIGH;                     /**< ASRC Resampling Ratio High, array offset: 0x114, array step: 0x8 */
3851   } RS_RATIO_LOW[4];
3852   __IO uint32_t RS_UPDATE_CTRL[4];                 /**< ASRC Resampling Ratio Update Control, array offset: 0x130, array step: 0x4 */
3853   __IO uint32_t RS_UPDATE_RATE[4];                 /**< ASRC Resampling Ratio Update Rate, array offset: 0x140, array step: 0x4 */
3854   __IO uint32_t RS_CT_LOW;                         /**< ASRC Resampling Center Tap Coefficient Low, offset: 0x150 */
3855   __IO uint32_t RS_CT_HIGH;                        /**< ASRC Resampling Center Tap Coefficient High, offset: 0x154 */
3856        uint8_t RESERVED_0[8];
3857   __IO uint32_t PRE_COEFF_FIFO[4];                 /**< ASRC Prefilter Coefficient FIFO, array offset: 0x160, array step: 0x4 */
3858   __O  uint32_t CTX_RS_COEFF_MEM;                  /**< ASRC Context Resampling Coefficient Memory, offset: 0x170 */
3859   __IO uint32_t CTX_RS_COEFF_CTRL;                 /**< ASRC Context Resampling Coefficient Control, offset: 0x174 */
3860   __IO uint32_t IRQ_CTRL;                          /**< ASRC Interrupt Control, offset: 0x178 */
3861   __IO uint32_t IRQ_FLAGS;                         /**< ASRC Interrupt Status Flags, offset: 0x17C */
3862   __IO uint32_t CHANNEL_STATUS_0[4];               /**< ASRC Channel Status 0, array offset: 0x180, array step: 0x4 */
3863   __IO uint32_t CHANNEL_STATUS_1[4];               /**< ASRC Channel Status 1, array offset: 0x190, array step: 0x4 */
3864   __IO uint32_t CHANNEL_STATUS_2[4];               /**< ASRC Channel Status 2, array offset: 0x1A0, array step: 0x4 */
3865   __IO uint32_t CHANNEL_STATUS_3[4];               /**< ASRC Channel Status 3, array offset: 0x1B0, array step: 0x4 */
3866   __IO uint32_t CHANNEL_STATUS_4[4];               /**< ASRC Channel Status 4, array offset: 0x1C0, array step: 0x4 */
3867   __IO uint32_t CHANNEL_STATUS_5[4];               /**< ASRC Channel Status 5, array offset: 0x1D0, array step: 0x4 */
3868 } ASRC_Type;
3869 
3870 /* ----------------------------------------------------------------------------
3871    -- ASRC Register Masks
3872    ---------------------------------------------------------------------------- */
3873 
3874 /*!
3875  * @addtogroup ASRC_Register_Masks ASRC Register Masks
3876  * @{
3877  */
3878 
3879 /*! @name WRFIFO - ASRC Input Write FIFO */
3880 /*! @{ */
3881 
3882 #define ASRC_WRFIFO_CTX_WR_DATA_MASK             (0xFFFFFFFFU)
3883 #define ASRC_WRFIFO_CTX_WR_DATA_SHIFT            (0U)
3884 /*! CTX_WR_DATA - Write Data For CTX Input FIFO */
3885 #define ASRC_WRFIFO_CTX_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << ASRC_WRFIFO_CTX_WR_DATA_SHIFT)) & ASRC_WRFIFO_CTX_WR_DATA_MASK)
3886 /*! @} */
3887 
3888 /* The count of ASRC_WRFIFO */
3889 #define ASRC_WRFIFO_COUNT                        (4U)
3890 
3891 /*! @name RDFIFO - ASRC Output Read FIFO */
3892 /*! @{ */
3893 
3894 #define ASRC_RDFIFO_CTX_RD_DATA_MASK             (0xFFFFFFFFU)
3895 #define ASRC_RDFIFO_CTX_RD_DATA_SHIFT            (0U)
3896 /*! CTX_RD_DATA - Read Data For CTX Output FIFO */
3897 #define ASRC_RDFIFO_CTX_RD_DATA(x)               (((uint32_t)(((uint32_t)(x)) << ASRC_RDFIFO_CTX_RD_DATA_SHIFT)) & ASRC_RDFIFO_CTX_RD_DATA_MASK)
3898 /*! @} */
3899 
3900 /* The count of ASRC_RDFIFO */
3901 #define ASRC_RDFIFO_COUNT                        (4U)
3902 
3903 /*! @name CTX_CTRL - ASRC Context Control */
3904 /*! @{ */
3905 
3906 #define ASRC_CTX_CTRL_NUM_CH_EN_MASK             (0x1FU)
3907 #define ASRC_CTX_CTRL_NUM_CH_EN_SHIFT            (0U)
3908 /*! NUM_CH_EN - Number of Channels In Context */
3909 #define ASRC_CTX_CTRL_NUM_CH_EN(x)               (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_NUM_CH_EN_SHIFT)) & ASRC_CTX_CTRL_NUM_CH_EN_MASK)
3910 
3911 #define ASRC_CTX_CTRL_SIGN_IN_MASK               (0x40U)
3912 #define ASRC_CTX_CTRL_SIGN_IN_SHIFT              (6U)
3913 /*! SIGN_IN - Input Data Sign
3914  *  0b0..Signed Format
3915  *  0b1..Unsigned Format
3916  */
3917 #define ASRC_CTX_CTRL_SIGN_IN(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SIGN_IN_SHIFT)) & ASRC_CTX_CTRL_SIGN_IN_MASK)
3918 
3919 #define ASRC_CTX_CTRL_FLOAT_FMT_MASK             (0x80U)
3920 #define ASRC_CTX_CTRL_FLOAT_FMT_SHIFT            (7U)
3921 /*! FLOAT_FMT - Context Input Floating Point Format
3922  *  0b0..Integer Format
3923  *  0b1..Single Precision Floating Point Format
3924  */
3925 #define ASRC_CTX_CTRL_FLOAT_FMT(x)               (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_CTRL_FLOAT_FMT_MASK)
3926 
3927 #define ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK       (0x300U)
3928 #define ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT      (8U)
3929 /*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
3930  *  0b00..16-bits Per Sample
3931  *  0b01..20-bits Per Sample
3932  *  0b10..24-bits Per Sample
3933  *  0b11..32-bits Per Sample
3934  */
3935 #define ASRC_CTX_CTRL_BITS_PER_SAMPLE(x)         (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK)
3936 
3937 #define ASRC_CTX_CTRL_BIT_REV_MASK               (0x400U)
3938 #define ASRC_CTX_CTRL_BIT_REV_SHIFT              (10U)
3939 /*! BIT_REV - Sample Bit Reversal
3940  *  0b0..Keep Input Ordering
3941  *  0b1..Reverse Bit Ordering
3942  */
3943 #define ASRC_CTX_CTRL_BIT_REV(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_CTRL_BIT_REV_MASK)
3944 
3945 #define ASRC_CTX_CTRL_SAMPLE_POSITION_MASK       (0xF800U)
3946 #define ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT      (11U)
3947 /*! SAMPLE_POSITION - Sample Position */
3948 #define ASRC_CTX_CTRL_SAMPLE_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_CTRL_SAMPLE_POSITION_MASK)
3949 
3950 #define ASRC_CTX_CTRL_FIFO_WTMK_MASK             (0x7F0000U)
3951 #define ASRC_CTX_CTRL_FIFO_WTMK_SHIFT            (16U)
3952 /*! FIFO_WTMK - Context Input FIFO Watermark */
3953 #define ASRC_CTX_CTRL_FIFO_WTMK(x)               (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_CTRL_FIFO_WTMK_MASK)
3954 
3955 #define ASRC_CTX_CTRL_FWMDE_MASK                 (0x10000000U)
3956 #define ASRC_CTX_CTRL_FWMDE_SHIFT                (28U)
3957 /*! FWMDE - FIFO Watermark DMA Enable
3958  *  0b0..Input DMA Requests Not Enabled for This Context
3959  *  0b1..Input DMA Requests Enabled for This Context
3960  */
3961 #define ASRC_CTX_CTRL_FWMDE(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FWMDE_SHIFT)) & ASRC_CTX_CTRL_FWMDE_MASK)
3962 
3963 #define ASRC_CTX_CTRL_RUN_STOP_MASK              (0x20000000U)
3964 #define ASRC_CTX_CTRL_RUN_STOP_SHIFT             (29U)
3965 /*! RUN_STOP - Context Run Stop */
3966 #define ASRC_CTX_CTRL_RUN_STOP(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_STOP_SHIFT)) & ASRC_CTX_CTRL_RUN_STOP_MASK)
3967 
3968 #define ASRC_CTX_CTRL_RUN_EN_MASK                (0x80000000U)
3969 #define ASRC_CTX_CTRL_RUN_EN_SHIFT               (31U)
3970 /*! RUN_EN - Context Run Enable */
3971 #define ASRC_CTX_CTRL_RUN_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_EN_SHIFT)) & ASRC_CTX_CTRL_RUN_EN_MASK)
3972 /*! @} */
3973 
3974 /* The count of ASRC_CTX_CTRL */
3975 #define ASRC_CTX_CTRL_COUNT                      (4U)
3976 
3977 /*! @name CTX_CTRL_EXT1 - ASRC Context Control Extended 1 */
3978 /*! @{ */
3979 
3980 #define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK     (0x3U)
3981 #define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT    (0U)
3982 /*! PF_INIT_MODE - Prefilter Initialization Mode
3983  *  0b00..Do not pre-fill any prefilter taps. The first sample written to the ASRC corresponds to the highest index prefilter filter tap.
3984  *  0b01..Replicate the first sample to fill the right half of the prefilter.
3985  *  0b10..Zero fill the right half of the prefilter.
3986  *  0b11..N/A
3987  */
3988 #define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK)
3989 
3990 #define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK     (0xCU)
3991 #define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT    (2U)
3992 /*! RS_INIT_MODE - Resampler Initialization Mode
3993  *  0b00..Do not pre-fill any resampler taps. The first sample output from the prefilter corresponds to the highest index resampling filter tap.
3994  *  0b01..Replicate the first prefilter output sample to fill the right half of the resampler.
3995  *  0b10..Fill the right half of the re-sampler with zeros.
3996  *  0b11..N/A
3997  */
3998 #define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK)
3999 
4000 #define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK     (0x10U)
4001 #define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT    (4U)
4002 /*! PF_STOP_MODE - Pre-Filter Stop Mode
4003  *  0b0..Replicate the last sample input to the ASRC_WRFIFO for the left-half of the pre-filter on RUN_STOP.
4004  *  0b1..Zero-Fill the left-half of the pre-filter on RUN_STOP.
4005  */
4006 #define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK)
4007 
4008 #define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK     (0x20U)
4009 #define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT    (5U)
4010 /*! RS_STOP_MODE - Resampler Stop Mode
4011  *  0b0..Replicate the final prefilter output for the left-half of the resampler on RUN_STOP.
4012  *  0b1..Zero-Fill the left-half of the resampler on RUN_STOP.
4013  */
4014 #define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK)
4015 
4016 #define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK   (0x40U)
4017 #define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT  (6U)
4018 /*! PF_BYPASS_MODE - Prefilter Bypass Mode
4019  *  0b0..Run the prefilter in normal operation.
4020  *  0b1..Run the prefilter in bypass mode.
4021  */
4022 #define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE(x)     (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK)
4023 
4024 #define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK   (0x80U)
4025 #define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT  (7U)
4026 /*! RS_BYPASS_MODE - Resampler Bypass Mode
4027  *  0b0..Run the resampler in normal operation.
4028  *  0b1..Run the resampler in bypass mode.
4029  */
4030 #define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE(x)     (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK)
4031 
4032 #define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK  (0x100U)
4033 #define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT (8U)
4034 /*! PF_TWO_STAGE_EN - Prefilter Two-Stage Enable
4035  *  0b0..The pre-filter will run in single stage mode (ST1 only)
4036  *  0b1..The pre-filter will run in two stage mode (ST1 and ST2)
4037  */
4038 #define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN(x)    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK)
4039 
4040 #define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK  (0x200U)
4041 #define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT (9U)
4042 /*! PF_ST1_WB_FLOAT - Prefilter Stage1 Writeback Floating Point
4043  *  0b0..The pre-filter stage1 results are stored in 32-bit integer format.
4044  *  0b1..The pre-filter stage1 results are stored in 32-bit floating point format.
4045  */
4046 #define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT(x)    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK)
4047 
4048 #define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK (0xFF0000U)
4049 #define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT (16U)
4050 /*! PF_EXPANSION_FACTOR - Prefilter IFIR Expansion Factor */
4051 #define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK)
4052 
4053 #define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK (0x1000000U)
4054 #define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT (24U)
4055 /*! PF_COEFF_MEM_RST - Prefilter Coefficient Memory Reset */
4056 #define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST(x)   (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK)
4057 
4058 #define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK (0x2000000U)
4059 #define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT (25U)
4060 /*! PF_COEFF_STAGE_WR - Prefilter Coefficient Write Select */
4061 #define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK)
4062 /*! @} */
4063 
4064 /* The count of ASRC_CTX_CTRL_EXT1 */
4065 #define ASRC_CTX_CTRL_EXT1_COUNT                 (4U)
4066 
4067 /*! @name CTX_CTRL_EXT2 - ASRC Context Control Extended 2 */
4068 /*! @{ */
4069 
4070 #define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK     (0x1FFU)
4071 #define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT    (0U)
4072 /*! ST1_NUM_TAPS - Prefilter Stage1 Number of Taps */
4073 #define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK)
4074 
4075 #define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK     (0x1FF0000U)
4076 #define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT    (16U)
4077 /*! ST2_NUM_TAPS - Prefilter Stage2 Number of Taps */
4078 #define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK)
4079 /*! @} */
4080 
4081 /* The count of ASRC_CTX_CTRL_EXT2 */
4082 #define ASRC_CTX_CTRL_EXT2_COUNT                 (4U)
4083 
4084 /*! @name CTRL_IN_ACCESS - ASRC Control Input Access */
4085 /*! @{ */
4086 
4087 #define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK   (0x3FU)
4088 #define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT  (0U)
4089 /*! ACCESS_LENGTH - Number Of Channels Per Source */
4090 #define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH(x)     (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK)
4091 
4092 #define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK    (0x3F00U)
4093 #define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT   (8U)
4094 /*! GROUP_LENGTH - Number of Channels in a Context */
4095 #define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH(x)      (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK)
4096 
4097 #define ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK      (0x3F0000U)
4098 #define ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT     (16U)
4099 /*! ITERATIONS - Number of Sequential Fetches Per Source */
4100 #define ASRC_CTRL_IN_ACCESS_ITERATIONS(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK)
4101 /*! @} */
4102 
4103 /* The count of ASRC_CTRL_IN_ACCESS */
4104 #define ASRC_CTRL_IN_ACCESS_COUNT                (4U)
4105 
4106 /*! @name PROC_CTRL_SLOT0_R0 - ASRC Datapath Processor Control Slot0 Register0 */
4107 /*! @{ */
4108 
4109 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK    (0x1U)
4110 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT   (0U)
4111 /*! SLOT0_EN - SLOT0 Enable
4112  *  0b0..Context SLOT0 is disabled
4113  *  0b1..Context SLOT0 is enabled
4114  */
4115 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN(x)      (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK)
4116 
4117 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK (0x6U)
4118 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT (1U)
4119 /*! SLOT0_CTX_NUM - Context SLOT0 Selection */
4120 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK)
4121 
4122 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK (0x1F00U)
4123 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT (8U)
4124 /*! SLOT0_NUM_CH - SLOT0 Number of Channels
4125  *  0b00000..Context SLOT0 owns 1 of 8 channels
4126  *  0b00001..Context SLOT0 owns 2 of 8 channels
4127  *  0b00010..Context SLOT0 owns 3 of 8 channels
4128  *  0b00011-0b00111..Context SLOT0 owns N of 8 channels
4129  */
4130 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK)
4131 
4132 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK (0x1F0000U)
4133 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT (16U)
4134 /*! SLOT0_MIN_CH - SLOT0 Minimum Global Channel Number */
4135 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK)
4136 
4137 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK (0x1F000000U)
4138 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT (24U)
4139 /*! SLOT0_MAX_CH - SLOT0 Maximum Global Channel Number */
4140 #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK)
4141 /*! @} */
4142 
4143 /* The count of ASRC_PROC_CTRL_SLOT0_R0 */
4144 #define ASRC_PROC_CTRL_SLOT0_R0_COUNT            (4U)
4145 
4146 /*! @name PROC_CTRL_SLOT0_R1 - ASRC Datapath Processor Control Slot0 Register1 */
4147 /*! @{ */
4148 
4149 #define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK (0x1FFFU)
4150 #define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT (0U)
4151 /*! SLOT0_ST1_CHANxEXP - SLOT0 Stage1 Channels x Expansion Factor */
4152 #define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK)
4153 /*! @} */
4154 
4155 /* The count of ASRC_PROC_CTRL_SLOT0_R1 */
4156 #define ASRC_PROC_CTRL_SLOT0_R1_COUNT            (4U)
4157 
4158 /*! @name PROC_CTRL_SLOT0_R2 - ASRC Datapath Processor Control Slot0 Register2 */
4159 /*! @{ */
4160 
4161 #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK (0x1FFFU)
4162 #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT (0U)
4163 /*! SLOT0_ST1_ST_ADDR - SLOT0 Stage1 Start Address */
4164 #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK)
4165 
4166 #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
4167 #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT (16U)
4168 /*! SLOT0_ST1_MEM_ALLOC - SLOT0 Stage1 Memory Allocation */
4169 #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK)
4170 /*! @} */
4171 
4172 /* The count of ASRC_PROC_CTRL_SLOT0_R2 */
4173 #define ASRC_PROC_CTRL_SLOT0_R2_COUNT            (4U)
4174 
4175 /*! @name PROC_CTRL_SLOT0_R3 - ASRC Datapath Processor Control Slot0 Register3 */
4176 /*! @{ */
4177 
4178 #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK (0x1FFFU)
4179 #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT (0U)
4180 /*! SLOT0_ST2_ST_ADDR - SLOT0 Stage2 Start Address */
4181 #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK)
4182 
4183 #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
4184 #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT (16U)
4185 /*! SLOT0_ST2_MEM_ALLOC - SLOT0 Stage2 Memory Allocation */
4186 #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK)
4187 /*! @} */
4188 
4189 /* The count of ASRC_PROC_CTRL_SLOT0_R3 */
4190 #define ASRC_PROC_CTRL_SLOT0_R3_COUNT            (4U)
4191 
4192 /*! @name PROC_CTRL_SLOT1_R0 - ASRC Datapath Processor Control Slot1 Register0 */
4193 /*! @{ */
4194 
4195 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK    (0x1U)
4196 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT   (0U)
4197 /*! SLOT1_EN - SLOT1 Enable
4198  *  0b0..Context SLOT1 is disabled
4199  *  0b1..Context SLOT1 is enabled
4200  */
4201 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN(x)      (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK)
4202 
4203 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK (0x6U)
4204 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT (1U)
4205 /*! SLOT1_CTX_NUM - Context SLOT1 Selection */
4206 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK)
4207 
4208 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK (0x1F00U)
4209 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT (8U)
4210 /*! SLOT1_NUM_CH - SLOT1 Number of Channels
4211  *  0b00000..Context SLOT1 owns 1 of 8 channels
4212  *  0b00001..Context SLOT1 owns 2 of 8 channels
4213  *  0b00010..Context SLOT1 owns 3 of 8 channels
4214  *  0b00011-0b00111..Context SLOT1 owns N of 8 channels
4215  */
4216 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK)
4217 
4218 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK (0x1F0000U)
4219 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT (16U)
4220 /*! SLOT1_MIN_CH - Slot1 Minimum Global Channel Number */
4221 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK)
4222 
4223 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK (0x1F000000U)
4224 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT (24U)
4225 /*! SLOT1_MAX_CH - Slot1 Maximum Global Channel Number */
4226 #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK)
4227 /*! @} */
4228 
4229 /* The count of ASRC_PROC_CTRL_SLOT1_R0 */
4230 #define ASRC_PROC_CTRL_SLOT1_R0_COUNT            (4U)
4231 
4232 /*! @name PROC_CTRL_SLOT1_R1 - ASRC Datapath Processor Control SLOT1 Register1 */
4233 /*! @{ */
4234 
4235 #define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK (0x1FFFU)
4236 #define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT (0U)
4237 /*! SLOT1_ST1_CHANxEXP - SLOT1 Stage1 Channels x Expansion Factor */
4238 #define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK)
4239 /*! @} */
4240 
4241 /* The count of ASRC_PROC_CTRL_SLOT1_R1 */
4242 #define ASRC_PROC_CTRL_SLOT1_R1_COUNT            (4U)
4243 
4244 /*! @name PROC_CTRL_SLOT1_R2 - ASRC Datapath Processor Control SLOT1 Register2 */
4245 /*! @{ */
4246 
4247 #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK (0x1FFFU)
4248 #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT (0U)
4249 /*! SLOT1_ST1_ST_ADDR - SLOT1 Stage1 Start Address */
4250 #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK)
4251 
4252 #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
4253 #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT (16U)
4254 /*! SLOT1_ST1_MEM_ALLOC - SLOT1 Stage1 Memory Allocation */
4255 #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK)
4256 /*! @} */
4257 
4258 /* The count of ASRC_PROC_CTRL_SLOT1_R2 */
4259 #define ASRC_PROC_CTRL_SLOT1_R2_COUNT            (4U)
4260 
4261 /*! @name PROC_CTRL_SLOT1_R3 - ASRC Datapath Processor Control SLOT1 Register3 */
4262 /*! @{ */
4263 
4264 #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK (0x1FFFU)
4265 #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT (0U)
4266 /*! SLOT1_ST2_ST_ADDR - SLOT1 Stage2 Start Address */
4267 #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK)
4268 
4269 #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
4270 #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT (16U)
4271 /*! SLOT1_ST2_MEM_ALLOC - SLOT1 Stage2 Memory Allocation */
4272 #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK)
4273 /*! @} */
4274 
4275 /* The count of ASRC_PROC_CTRL_SLOT1_R3 */
4276 #define ASRC_PROC_CTRL_SLOT1_R3_COUNT            (4U)
4277 
4278 /*! @name CTX_OUT_CTRL - ASRC Context Output Control */
4279 /*! @{ */
4280 
4281 #define ASRC_CTX_OUT_CTRL_DITHER_EN_MASK         (0x1U)
4282 #define ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT        (0U)
4283 /*! DITHER_EN - Output Dither Enable */
4284 #define ASRC_CTX_OUT_CTRL_DITHER_EN(x)           (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_DITHER_EN_MASK)
4285 
4286 #define ASRC_CTX_OUT_CTRL_IEC_EN_MASK            (0x2U)
4287 #define ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT           (1U)
4288 /*! IEC_EN - IEC60958 Bit-Field Insertion Enable
4289  *  0b0..No Data Insertion Enabled.
4290  *  0b1..IEC60958 Bit-Field Insertion Enabled.
4291  */
4292 #define ASRC_CTX_OUT_CTRL_IEC_EN(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_EN_MASK)
4293 
4294 #define ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK        (0x4U)
4295 #define ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT       (2U)
4296 /*! IEC_V_DATA - IEC60958 Validity Flag */
4297 #define ASRC_CTX_OUT_CTRL_IEC_V_DATA(x)          (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK)
4298 
4299 #define ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK          (0x40U)
4300 #define ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT         (6U)
4301 /*! SIGN_OUT - Output Data Sign
4302  *  0b0..Signed Format
4303  *  0b1..Convert to Unsigned
4304  */
4305 #define ASRC_CTX_OUT_CTRL_SIGN_OUT(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT)) & ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK)
4306 
4307 #define ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK         (0x80U)
4308 #define ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT        (7U)
4309 /*! FLOAT_FMT - Context Output Floating Point Format
4310  *  0b0..Integer Format
4311  *  0b1..Single Precision Floating Point Format
4312  */
4313 #define ASRC_CTX_OUT_CTRL_FLOAT_FMT(x)           (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK)
4314 
4315 #define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK   (0x300U)
4316 #define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT  (8U)
4317 /*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
4318  *  0b00..16-bits Per Sample
4319  *  0b01..20-bits Per Sample
4320  *  0b10..24-bits Per Sample
4321  *  0b11..32-bits Per Sample
4322  */
4323 #define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE(x)     (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK)
4324 
4325 #define ASRC_CTX_OUT_CTRL_BIT_REV_MASK           (0x400U)
4326 #define ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT          (10U)
4327 /*! BIT_REV - Sample Bit-Reversal
4328  *  0b0..No change.
4329  *  0b1..Bit-reverse sample data.
4330  */
4331 #define ASRC_CTX_OUT_CTRL_BIT_REV(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_OUT_CTRL_BIT_REV_MASK)
4332 
4333 #define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK   (0xF800U)
4334 #define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT  (11U)
4335 /*! SAMPLE_POSITION - Sample Position */
4336 #define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION(x)     (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK)
4337 
4338 #define ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK         (0x7F0000U)
4339 #define ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT        (16U)
4340 /*! FIFO_WTMK - Context Output FIFO Watermark */
4341 #define ASRC_CTX_OUT_CTRL_FIFO_WTMK(x)           (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK)
4342 
4343 #define ASRC_CTX_OUT_CTRL_FWMDE_MASK             (0x10000000U)
4344 #define ASRC_CTX_OUT_CTRL_FWMDE_SHIFT            (28U)
4345 /*! FWMDE - Output FIFO Watermark DMA Enable
4346  *  0b0..Output DMA Requests Not Enabled for This Context
4347  *  0b1..Output DMA Requests Enabled for This Context
4348  */
4349 #define ASRC_CTX_OUT_CTRL_FWMDE(x)               (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FWMDE_SHIFT)) & ASRC_CTX_OUT_CTRL_FWMDE_MASK)
4350 /*! @} */
4351 
4352 /* The count of ASRC_CTX_OUT_CTRL */
4353 #define ASRC_CTX_OUT_CTRL_COUNT                  (4U)
4354 
4355 /*! @name CTRL_OUT_ACCESS - ASRC Control Output Access */
4356 /*! @{ */
4357 
4358 #define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK  (0x3FU)
4359 #define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT (0U)
4360 /*! ACCESS_LENGTH - Number Of Channels Per Destination */
4361 #define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH(x)    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK)
4362 
4363 #define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK   (0x3F00U)
4364 #define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT  (8U)
4365 /*! GROUP_LENGTH - Number of Channels in a Context */
4366 #define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH(x)     (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK)
4367 
4368 #define ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK     (0x3F0000U)
4369 #define ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT    (16U)
4370 /*! ITERATIONS - Number of Sequential Fetches Per Channel Group */
4371 #define ASRC_CTRL_OUT_ACCESS_ITERATIONS(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK)
4372 /*! @} */
4373 
4374 /* The count of ASRC_CTRL_OUT_ACCESS */
4375 #define ASRC_CTRL_OUT_ACCESS_COUNT               (4U)
4376 
4377 /*! @name SAMPLE_FIFO_STATUS - ASRC Sample FIFO Status */
4378 /*! @{ */
4379 
4380 #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK (0x7FU)
4381 #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT (0U)
4382 /*! NUM_SAMPLE_GROUPS_OUT - Number Of Sample Groups Stored in the output FIFO */
4383 #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK)
4384 
4385 #define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK (0x80U)
4386 #define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT (7U)
4387 /*! OUTFIFO_WTMK - Output FIFO Watermark Flag */
4388 #define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK)
4389 
4390 #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK (0x7F0000U)
4391 #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT (16U)
4392 /*! NUM_SAMPLE_GROUPS_IN - Number Of Sample Groups Stored in Input FIFO */
4393 #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK)
4394 
4395 #define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK (0x800000U)
4396 #define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT (23U)
4397 /*! INFIFO_WTMK - Input FIFO Watermark Flag */
4398 #define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK(x)   (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK)
4399 /*! @} */
4400 
4401 /* The count of ASRC_SAMPLE_FIFO_STATUS */
4402 #define ASRC_SAMPLE_FIFO_STATUS_COUNT            (4U)
4403 
4404 /*! @name RS_RATIO_LOW - ASRC Resampling Ratio Low */
4405 /*! @{ */
4406 
4407 #define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK      (0xFFFFFFFFU)
4408 #define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT     (0U)
4409 /*! RS_RATIO_LOW - Resampling Ratio Low */
4410 #define ASRC_RS_RATIO_LOW_RS_RATIO_LOW(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT)) & ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK)
4411 /*! @} */
4412 
4413 /* The count of ASRC_RS_RATIO_LOW */
4414 #define ASRC_RS_RATIO_LOW_COUNT                  (4U)
4415 
4416 /*! @name RS_RATIO_HIGH - ASRC Resampling Ratio High */
4417 /*! @{ */
4418 
4419 #define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK    (0xFFFU)
4420 #define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT   (0U)
4421 /*! RS_RATIO_HIGH - Resampling Ratio High */
4422 #define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH(x)      (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK)
4423 
4424 #define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK     (0x80000000U)
4425 #define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT    (31U)
4426 /*! RS_RATIO_VLD - Resampling Ratio Valid */
4427 #define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK)
4428 /*! @} */
4429 
4430 /* The count of ASRC_RS_RATIO_HIGH */
4431 #define ASRC_RS_RATIO_HIGH_COUNT                 (4U)
4432 
4433 /*! @name RS_UPDATE_CTRL - ASRC Resampling Ratio Update Control */
4434 /*! @{ */
4435 
4436 #define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK    (0xFFFFFFFFU)
4437 #define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT   (0U)
4438 /*! RS_RATIO_MOD - Resampling Ratio Modifier */
4439 #define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD(x)      (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT)) & ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK)
4440 /*! @} */
4441 
4442 /* The count of ASRC_RS_UPDATE_CTRL */
4443 #define ASRC_RS_UPDATE_CTRL_COUNT                (4U)
4444 
4445 /*! @name RS_UPDATE_RATE - ASRC Resampling Ratio Update Rate */
4446 /*! @{ */
4447 
4448 #define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK (0x7FFFFFFFU)
4449 #define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT (0U)
4450 /*! RS_RATIO_RAMP_RATE - Resampling Ratio Ramp Rate */
4451 #define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT)) & ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK)
4452 /*! @} */
4453 
4454 /* The count of ASRC_RS_UPDATE_RATE */
4455 #define ASRC_RS_UPDATE_RATE_COUNT                (4U)
4456 
4457 /*! @name RS_CT_LOW - ASRC Resampling Center Tap Coefficient Low */
4458 /*! @{ */
4459 
4460 #define ASRC_RS_CT_LOW_RS_CT_LOW_MASK            (0xFFFFFFFFU)
4461 #define ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT           (0U)
4462 /*! RS_CT_LOW - Resampling Center Tap Coefficient LSBs */
4463 #define ASRC_RS_CT_LOW_RS_CT_LOW(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT)) & ASRC_RS_CT_LOW_RS_CT_LOW_MASK)
4464 /*! @} */
4465 
4466 /*! @name RS_CT_HIGH - ASRC Resampling Center Tap Coefficient High */
4467 /*! @{ */
4468 
4469 #define ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK          (0xFFFFFFFFU)
4470 #define ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT         (0U)
4471 /*! RS_CT_HIGH - Resampling Center Tap Coefficient MSBs */
4472 #define ASRC_RS_CT_HIGH_RS_CT_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT)) & ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK)
4473 /*! @} */
4474 
4475 /*! @name PRE_COEFF_FIFO - ASRC Prefilter Coefficient FIFO */
4476 /*! @{ */
4477 
4478 #define ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK      (0xFFFFFFFFU)
4479 #define ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT     (0U)
4480 /*! COEFF_DATA - Coefficient Value For Prefilter */
4481 #define ASRC_PRE_COEFF_FIFO_COEFF_DATA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT)) & ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK)
4482 /*! @} */
4483 
4484 /* The count of ASRC_PRE_COEFF_FIFO */
4485 #define ASRC_PRE_COEFF_FIFO_COUNT                (4U)
4486 
4487 /*! @name CTX_RS_COEFF_MEM - ASRC Context Resampling Coefficient Memory */
4488 /*! @{ */
4489 
4490 #define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK (0xFFFFFFFFU)
4491 #define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT (0U)
4492 /*! RS_COEFF_WDATA - Resampling Coefficient Write Data */
4493 #define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT)) & ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK)
4494 /*! @} */
4495 
4496 /*! @name CTX_RS_COEFF_CTRL - ASRC Context Resampling Coefficient Control */
4497 /*! @{ */
4498 
4499 #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK (0x1U)
4500 #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT (0U)
4501 /*! RS_COEFF_PTR_RST - Resampling Coefficient Write Pointer Reset */
4502 #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT)) & ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK)
4503 
4504 #define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK (0x6U)
4505 #define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT (1U)
4506 /*! NUM_RES_TAPS - Number of Resampling Coefficient Taps
4507  *  0b00..32-Tap Resampling Filter
4508  *  0b01..64-Tap Resampling Filter
4509  *  0b10..128-Tap Resampling Filter
4510  *  0b11..N/A
4511  */
4512 #define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS(x)   (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT)) & ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK)
4513 
4514 #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK (0x7FF0000U)
4515 #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT (16U)
4516 /*! RS_COEFF_ADDR - Resampling Coefficient Address */
4517 #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT)) & ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK)
4518 /*! @} */
4519 
4520 /*! @name IRQ_CTRL - ASRC Interrupt Control */
4521 /*! @{ */
4522 
4523 #define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK       (0xFU)
4524 #define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT      (0U)
4525 /*! INFIFO_OVF_MASK - ASRC Input FIFO Overflow Mask
4526  *  0b0000..The INFIFO_OVF interrupt is enabled for Context 0 to 3.
4527  *  0b0001..The INFIFO_OVF interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4528  *  0b0010..The INFIFO_OVF interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4529  *  0b0011-0b1110..The INFIFO_OVF interrupt is enabled for any context with a 1'b0 bit field.
4530  *  0b1111..The INFIFO_OVF interrupt is disabled for Context 0 to 3.
4531  */
4532 #define ASRC_IRQ_CTRL_INFIFO_OVF_MASK(x)         (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT)) & ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK)
4533 
4534 #define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK (0xF0U)
4535 #define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT (4U)
4536 /*! OUTFIFO_EMPTY_RD_MASK - ASRC Output FIFO Empty Read Mask
4537  *  0b0000..The OUTFIFO_EMPTY_RD interrupt is enabled for Context 0 to 3.
4538  *  0b0001..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4539  *  0b0010..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4540  *  0b0011-0b1110..The OUTFIFO_EMPTY_RD interrupt is enabled for any context with a 1'b0 bit field.
4541  *  0b1111..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 to 3.
4542  */
4543 #define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK(x)   (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT)) & ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK)
4544 
4545 #define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK    (0xF00U)
4546 #define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT   (8U)
4547 /*! RUN_STOP_DONE_MASK - ASRC RUN STOP DONE MASK
4548  *  0b0000..The RUN_STOP_DONE interrupt is enabled for Context 0 to 3.
4549  *  0b0001..The RUN_STOP_DONE interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4550  *  0b0010..The RUN_STOP_DONE interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4551  *  0b0011-0b1110..The RUN_STOP_DONE interrupt is enabled for any context with a 1'b0 bit field.
4552  *  0b1111..The RUN_STOP_DONE interrupt is disabled for Context 0 to 3.
4553  */
4554 #define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK(x)      (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT)) & ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK)
4555 /*! @} */
4556 
4557 /*! @name IRQ_FLAGS - ASRC Interrupt Status Flags */
4558 /*! @{ */
4559 
4560 #define ASRC_IRQ_FLAGS_INFIFO_OVF_MASK           (0xFU)
4561 #define ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT          (0U)
4562 /*! INFIFO_OVF - ASRC Input FIFO Overflow Flag
4563  *  0b0000..No INFIFO_OVF errors have been recorded.
4564  *  0b0001..The ASRC_WRFIFO0 has overflown.
4565  *  0b0010..The ASRC_WRFIFO1 has overflown.
4566  *  0b0011-0b1110..The ASRC_WRFIFOn has overflown. Where n = any bit position set to 0b1.
4567  *  0b1111..ASRC_WRFIFO0, ASRC_WRFIFO1, ASRC_WRFIFO2, and ASRC_WRFIFO3 have overflown.
4568  */
4569 #define ASRC_IRQ_FLAGS_INFIFO_OVF(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT)) & ASRC_IRQ_FLAGS_INFIFO_OVF_MASK)
4570 
4571 #define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK     (0xF0U)
4572 #define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT    (4U)
4573 /*! OUTFIFO_EMPTY_RD - ASRC Output FIFO Empty Read Flag
4574  *  0b0000..No reads have been requested from an empty ASRC_RDFIFO.
4575  *  0b0001..A read has been requested from ASRC_RDFIFO0 when it was empty.
4576  *  0b0010..A read has been requested from ASRC_RDFIFO1 when it was empty.
4577  *  0b0011-0b1110..A read has been requested from ASRC_RDFIFOn when it was empty. n = any bit position with a 0b1.
4578  *  0b1111..A read has been requested from ASRC_RDFIFO0, ASRC_RDFIFO1, ASRC_RDFIFO2, and ASRC_RDFIFO3 while empty.
4579  */
4580 #define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT)) & ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK)
4581 
4582 #define ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK        (0xF00U)
4583 #define ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT       (8U)
4584 /*! RUN_STOP_DONE - ASRC RUN STOP DONE FLAG
4585  *  0b0000..No RUN_STOP operations have been completed.
4586  *  0b0001..The RUN_STOP operation for Context 0 has completed.
4587  *  0b0010..The RUN_STOP operation for Context 1 has completed.
4588  *  0b0011-0b1110..The RUN_STOP operation has completed for any context with a 1'b1 bit field.
4589  *  0b1111..The RUN_STOP operation has completed for Context 0 to 3.
4590  */
4591 #define ASRC_IRQ_FLAGS_RUN_STOP_DONE(x)          (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT)) & ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK)
4592 /*! @} */
4593 
4594 /*! @name CHANNEL_STATUS_0 - ASRC Channel Status 0 */
4595 /*! @{ */
4596 
4597 #define ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK      (0xFFFFFFFFU)
4598 #define ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT     (0U)
4599 /*! CHN_STAT - Channel Status Data */
4600 #define ASRC_CHANNEL_STATUS_0_CHN_STAT(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK)
4601 /*! @} */
4602 
4603 /* The count of ASRC_CHANNEL_STATUS_0 */
4604 #define ASRC_CHANNEL_STATUS_0_COUNT              (4U)
4605 
4606 /*! @name CHANNEL_STATUS_1 - ASRC Channel Status 1 */
4607 /*! @{ */
4608 
4609 #define ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK      (0xFFFFFFFFU)
4610 #define ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT     (0U)
4611 /*! CHN_STAT - Channel Status Data */
4612 #define ASRC_CHANNEL_STATUS_1_CHN_STAT(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK)
4613 /*! @} */
4614 
4615 /* The count of ASRC_CHANNEL_STATUS_1 */
4616 #define ASRC_CHANNEL_STATUS_1_COUNT              (4U)
4617 
4618 /*! @name CHANNEL_STATUS_2 - ASRC Channel Status 2 */
4619 /*! @{ */
4620 
4621 #define ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK      (0xFFFFFFFFU)
4622 #define ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT     (0U)
4623 /*! CHN_STAT - Channel Status Data */
4624 #define ASRC_CHANNEL_STATUS_2_CHN_STAT(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK)
4625 /*! @} */
4626 
4627 /* The count of ASRC_CHANNEL_STATUS_2 */
4628 #define ASRC_CHANNEL_STATUS_2_COUNT              (4U)
4629 
4630 /*! @name CHANNEL_STATUS_3 - ASRC Channel Status 3 */
4631 /*! @{ */
4632 
4633 #define ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK      (0xFFFFFFFFU)
4634 #define ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT     (0U)
4635 /*! CHN_STAT - Channel Status Data */
4636 #define ASRC_CHANNEL_STATUS_3_CHN_STAT(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK)
4637 /*! @} */
4638 
4639 /* The count of ASRC_CHANNEL_STATUS_3 */
4640 #define ASRC_CHANNEL_STATUS_3_COUNT              (4U)
4641 
4642 /*! @name CHANNEL_STATUS_4 - ASRC Channel Status 4 */
4643 /*! @{ */
4644 
4645 #define ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK      (0xFFFFFFFFU)
4646 #define ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT     (0U)
4647 /*! CHN_STAT - Channel Status Data */
4648 #define ASRC_CHANNEL_STATUS_4_CHN_STAT(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK)
4649 /*! @} */
4650 
4651 /* The count of ASRC_CHANNEL_STATUS_4 */
4652 #define ASRC_CHANNEL_STATUS_4_COUNT              (4U)
4653 
4654 /*! @name CHANNEL_STATUS_5 - ASRC Channel Status 5 */
4655 /*! @{ */
4656 
4657 #define ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK      (0xFFFFFFFFU)
4658 #define ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT     (0U)
4659 /*! CHN_STAT - Channel Status Data */
4660 #define ASRC_CHANNEL_STATUS_5_CHN_STAT(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK)
4661 /*! @} */
4662 
4663 /* The count of ASRC_CHANNEL_STATUS_5 */
4664 #define ASRC_CHANNEL_STATUS_5_COUNT              (4U)
4665 
4666 
4667 /*!
4668  * @}
4669  */ /* end of group ASRC_Register_Masks */
4670 
4671 
4672 /* ASRC - Peripheral instance base addresses */
4673 /** Peripheral ASRC base address */
4674 #define ASRC_BASE                                (0x30C90000u)
4675 /** Peripheral ASRC base pointer */
4676 #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
4677 /** Array initializer of ASRC peripheral base addresses */
4678 #define ASRC_BASE_ADDRS                          { ASRC_BASE }
4679 /** Array initializer of ASRC peripheral base pointers */
4680 #define ASRC_BASE_PTRS                           { ASRC }
4681 
4682 /*!
4683  * @}
4684  */ /* end of group ASRC_Peripheral_Access_Layer */
4685 
4686 
4687 /* ----------------------------------------------------------------------------
4688    -- AUDIOMIX Peripheral Access Layer
4689    ---------------------------------------------------------------------------- */
4690 
4691 /*!
4692  * @addtogroup AUDIOMIX_Peripheral_Access_Layer AUDIOMIX Peripheral Access Layer
4693  * @{
4694  */
4695 
4696 /** AUDIOMIX - Register Layout Typedef */
4697 typedef struct {
4698   __IO uint32_t CLKEN0;                            /**< IP Clock Enable Control Register 0, offset: 0x0 */
4699   __IO uint32_t CLKEN1;                            /**< IP Clock Enable Control Register 1, offset: 0x4 */
4700        uint8_t RESERVED_0[248];
4701   __I  uint32_t AUDIODSP_REG0;                     /**< AudioDSP EXPSTATE Register, offset: 0x100 */
4702   __IO uint32_t AUDIODSP_REG1;                     /**< AudioDSP IMPWIRE Register, offset: 0x104 */
4703   __IO uint32_t AUDIODSP_REG2;                     /**< AudioDSP XOCDMODE Register, offset: 0x108 */
4704   __IO uint32_t AUDIODSP_REG3;                     /**< AudioDSP PID Register, offset: 0x10C */
4705        uint8_t RESERVED_1[240];
4706   __IO uint32_t EARC;                              /**< EARC Control Register, offset: 0x200 */
4707        uint8_t RESERVED_2[252];
4708   __IO uint32_t SAI1_MCLK_SEL;                     /**< SAI1 MCLK SELECT Register, offset: 0x300 */
4709   __IO uint32_t SAI2_MCLK_SEL;                     /**< SAI2 MCLK SELECT Register, offset: 0x304 */
4710   __IO uint32_t SAI3_MCLK_SEL;                     /**< SAI3 MCLK SELECT Register, offset: 0x308 */
4711   __IO uint32_t SAI5_MCLK_SEL;                     /**< SAI5 MCLK SELECT Register, offset: 0x30C */
4712   __IO uint32_t SAI6_MCLK_SEL;                     /**< SAI6 MCLK SELECT Register, offset: 0x310 */
4713   __IO uint32_t SAI7_MCLK_SEL;                     /**< SAI7 MCLK SELECT Register, offset: 0x314 */
4714   __IO uint32_t PDM_CLK;                           /**< PDM Root Clock Select Register, offset: 0x318 */
4715        uint8_t RESERVED_3[228];
4716   __IO uint32_t SAI_PLL_GNRL_CTL;                  /**< SAI PLL General control Register, offset: 0x400 */
4717   __IO uint32_t SAI_PLL_FDIV_CTL0;                 /**< SAI PLL Frequency Divider control Register, offset: 0x404 */
4718   __IO uint32_t SAI_PLL_FDIV_CTL1;                 /**< SAI PLL DSM value Register, offset: 0x408 */
4719   __IO uint32_t SAI_PLL_SSCG_CTL;                  /**< SAI PLL SSCG control Register, offset: 0x40C */
4720   __IO uint32_t SAI_PLL_MNIT_CTL;                  /**< SAI PLL SSCG control Register, offset: 0x410 */
4721        uint8_t RESERVED_4[236];
4722   __IO uint32_t AUDIO_EXT_ADDR;                    /**< AUDIOMIX Extra Addr Bits Register, offset: 0x500 */
4723   __IO uint32_t IPG_LP_CTRL;                       /**< IPG Low Power Control Register, offset: 0x504 */
4724   __IO uint32_t AUDIO_AXI_LIMIT;                   /**< AUDIOMIX AXI LIMIT CTRL Register, offset: 0x508 */
4725 } AUDIOMIX_Type;
4726 
4727 /* ----------------------------------------------------------------------------
4728    -- AUDIOMIX Register Masks
4729    ---------------------------------------------------------------------------- */
4730 
4731 /*!
4732  * @addtogroup AUDIOMIX_Register_Masks AUDIOMIX Register Masks
4733  * @{
4734  */
4735 
4736 /*! @name CLKEN0 - IP Clock Enable Control Register 0 */
4737 /*! @{ */
4738 
4739 #define AUDIOMIX_CLKEN0_SAI1_MASK                (0x1U)
4740 #define AUDIOMIX_CLKEN0_SAI1_SHIFT               (0U)
4741 /*! SAI1 - SAI1 clock enable
4742  *  0b1..SAI1 sai clock enable
4743  *  0b0..SAI1 sai clock disable
4744  */
4745 #define AUDIOMIX_CLKEN0_SAI1(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MASK)
4746 
4747 #define AUDIOMIX_CLKEN0_SAI1_MCLK1_MASK          (0x2U)
4748 #define AUDIOMIX_CLKEN0_SAI1_MCLK1_SHIFT         (1U)
4749 /*! SAI1_MCLK1 - SAI1 mclk1 clock enable */
4750 #define AUDIOMIX_CLKEN0_SAI1_MCLK1(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MCLK1_MASK)
4751 
4752 #define AUDIOMIX_CLKEN0_SAI1_MCLK2_MASK          (0x4U)
4753 #define AUDIOMIX_CLKEN0_SAI1_MCLK2_SHIFT         (2U)
4754 /*! SAI1_MCLK2 - SAI1 mclk2 clock enable */
4755 #define AUDIOMIX_CLKEN0_SAI1_MCLK2(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MCLK2_MASK)
4756 
4757 #define AUDIOMIX_CLKEN0_SAI1_MCLK3_MASK          (0x8U)
4758 #define AUDIOMIX_CLKEN0_SAI1_MCLK3_SHIFT         (3U)
4759 /*! SAI1_MCLK3 - SAI1 mclk3 clock enable */
4760 #define AUDIOMIX_CLKEN0_SAI1_MCLK3(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MCLK3_MASK)
4761 
4762 #define AUDIOMIX_CLKEN0_SAI2_MASK                (0x10U)
4763 #define AUDIOMIX_CLKEN0_SAI2_SHIFT               (4U)
4764 /*! SAI2 - SAI2 clock enable
4765  *  0b1..SAI2 sai clock enable
4766  *  0b0..SAI2 sai clock disable
4767  */
4768 #define AUDIOMIX_CLKEN0_SAI2(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MASK)
4769 
4770 #define AUDIOMIX_CLKEN0_SAI2_MCLK1_MASK          (0x20U)
4771 #define AUDIOMIX_CLKEN0_SAI2_MCLK1_SHIFT         (5U)
4772 /*! SAI2_MCLK1 - SAI2 mclk1 clock enable */
4773 #define AUDIOMIX_CLKEN0_SAI2_MCLK1(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MCLK1_MASK)
4774 
4775 #define AUDIOMIX_CLKEN0_SAI2_MCLK2_MASK          (0x40U)
4776 #define AUDIOMIX_CLKEN0_SAI2_MCLK2_SHIFT         (6U)
4777 /*! SAI2_MCLK2 - SAI2 mclk2 clock enable */
4778 #define AUDIOMIX_CLKEN0_SAI2_MCLK2(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MCLK2_MASK)
4779 
4780 #define AUDIOMIX_CLKEN0_SAI2_MCLK3_MASK          (0x80U)
4781 #define AUDIOMIX_CLKEN0_SAI2_MCLK3_SHIFT         (7U)
4782 /*! SAI2_MCLK3 - SAI2 mclk3 clock enable */
4783 #define AUDIOMIX_CLKEN0_SAI2_MCLK3(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MCLK3_MASK)
4784 
4785 #define AUDIOMIX_CLKEN0_SAI3_MASK                (0x100U)
4786 #define AUDIOMIX_CLKEN0_SAI3_SHIFT               (8U)
4787 /*! SAI3 - SAI3 clock enable
4788  *  0b1..SAI3 sai clock enable
4789  *  0b0..SAI3 sai clock disable
4790  */
4791 #define AUDIOMIX_CLKEN0_SAI3(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MASK)
4792 
4793 #define AUDIOMIX_CLKEN0_SAI3_MCLK1_MASK          (0x200U)
4794 #define AUDIOMIX_CLKEN0_SAI3_MCLK1_SHIFT         (9U)
4795 /*! SAI3_MCLK1 - SAI3 mclk1 clock enable */
4796 #define AUDIOMIX_CLKEN0_SAI3_MCLK1(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MCLK1_MASK)
4797 
4798 #define AUDIOMIX_CLKEN0_SAI3_MCLK2_MASK          (0x400U)
4799 #define AUDIOMIX_CLKEN0_SAI3_MCLK2_SHIFT         (10U)
4800 /*! SAI3_MCLK2 - SAI3 mclk2 clock enable */
4801 #define AUDIOMIX_CLKEN0_SAI3_MCLK2(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MCLK2_MASK)
4802 
4803 #define AUDIOMIX_CLKEN0_SAI3_MCLK3_MASK          (0x800U)
4804 #define AUDIOMIX_CLKEN0_SAI3_MCLK3_SHIFT         (11U)
4805 /*! SAI3_MCLK3 - SAI3 mclk3 clock enable */
4806 #define AUDIOMIX_CLKEN0_SAI3_MCLK3(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MCLK3_MASK)
4807 
4808 #define AUDIOMIX_CLKEN0_SAI5_MASK                (0x1000U)
4809 #define AUDIOMIX_CLKEN0_SAI5_SHIFT               (12U)
4810 /*! SAI5 - SAI5 clock enable
4811  *  0b1..SAI5 sai clock enable
4812  *  0b0..SAI5 sai clock disable
4813  */
4814 #define AUDIOMIX_CLKEN0_SAI5(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MASK)
4815 
4816 #define AUDIOMIX_CLKEN0_SAI5_MCLK1_MASK          (0x2000U)
4817 #define AUDIOMIX_CLKEN0_SAI5_MCLK1_SHIFT         (13U)
4818 /*! SAI5_MCLK1 - SAI5 mclk1 clock enable */
4819 #define AUDIOMIX_CLKEN0_SAI5_MCLK1(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MCLK1_MASK)
4820 
4821 #define AUDIOMIX_CLKEN0_SAI5_MCLK2_MASK          (0x4000U)
4822 #define AUDIOMIX_CLKEN0_SAI5_MCLK2_SHIFT         (14U)
4823 /*! SAI5_MCLK2 - SAI5 mclk2 clock enable */
4824 #define AUDIOMIX_CLKEN0_SAI5_MCLK2(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MCLK2_MASK)
4825 
4826 #define AUDIOMIX_CLKEN0_SAI5_MCLK3_MASK          (0x8000U)
4827 #define AUDIOMIX_CLKEN0_SAI5_MCLK3_SHIFT         (15U)
4828 /*! SAI5_MCLK3 - SAI5 mclk3 clock enable */
4829 #define AUDIOMIX_CLKEN0_SAI5_MCLK3(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MCLK3_MASK)
4830 
4831 #define AUDIOMIX_CLKEN0_SAI6_MASK                (0x10000U)
4832 #define AUDIOMIX_CLKEN0_SAI6_SHIFT               (16U)
4833 /*! SAI6 - SAI6 clock enable
4834  *  0b1..SAI6 IPG clock enable
4835  *  0b0..SAI6 IPG clock disable
4836  */
4837 #define AUDIOMIX_CLKEN0_SAI6(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MASK)
4838 
4839 #define AUDIOMIX_CLKEN0_SAI6_MCLK1_MASK          (0x20000U)
4840 #define AUDIOMIX_CLKEN0_SAI6_MCLK1_SHIFT         (17U)
4841 /*! SAI6_MCLK1 - SAI6 mclk1 clock enable */
4842 #define AUDIOMIX_CLKEN0_SAI6_MCLK1(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MCLK1_MASK)
4843 
4844 #define AUDIOMIX_CLKEN0_SAI6_MCLK2_MASK          (0x40000U)
4845 #define AUDIOMIX_CLKEN0_SAI6_MCLK2_SHIFT         (18U)
4846 /*! SAI6_MCLK2 - SAI6 mclk2 clock enable */
4847 #define AUDIOMIX_CLKEN0_SAI6_MCLK2(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MCLK2_MASK)
4848 
4849 #define AUDIOMIX_CLKEN0_SAI6_MCLK3_MASK          (0x80000U)
4850 #define AUDIOMIX_CLKEN0_SAI6_MCLK3_SHIFT         (19U)
4851 /*! SAI6_MCLK3 - SAI6 mclk3 clock enable */
4852 #define AUDIOMIX_CLKEN0_SAI6_MCLK3(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MCLK3_MASK)
4853 
4854 #define AUDIOMIX_CLKEN0_SAI7_MASK                (0x100000U)
4855 #define AUDIOMIX_CLKEN0_SAI7_SHIFT               (20U)
4856 /*! SAI7 - SAI7 clock enable
4857  *  0b1..SAI7 sai clock enable
4858  *  0b0..SAI7 sai clock disable
4859  */
4860 #define AUDIOMIX_CLKEN0_SAI7(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MASK)
4861 
4862 #define AUDIOMIX_CLKEN0_SAI7_MCLK1_MASK          (0x200000U)
4863 #define AUDIOMIX_CLKEN0_SAI7_MCLK1_SHIFT         (21U)
4864 /*! SAI7_MCLK1 - SAI7 mclk1 clock enable */
4865 #define AUDIOMIX_CLKEN0_SAI7_MCLK1(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MCLK1_MASK)
4866 
4867 #define AUDIOMIX_CLKEN0_SAI7_MCLK2_MASK          (0x400000U)
4868 #define AUDIOMIX_CLKEN0_SAI7_MCLK2_SHIFT         (22U)
4869 /*! SAI7_MCLK2 - SAI7 mclk2 clock enable */
4870 #define AUDIOMIX_CLKEN0_SAI7_MCLK2(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MCLK2_MASK)
4871 
4872 #define AUDIOMIX_CLKEN0_SAI7_MCLK3_MASK          (0x800000U)
4873 #define AUDIOMIX_CLKEN0_SAI7_MCLK3_SHIFT         (23U)
4874 /*! SAI7_MCLK3 - SAI7 mclk3 clock enable */
4875 #define AUDIOMIX_CLKEN0_SAI7_MCLK3(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MCLK3_MASK)
4876 
4877 #define AUDIOMIX_CLKEN0_ASRC_MASK                (0x1000000U)
4878 #define AUDIOMIX_CLKEN0_ASRC_SHIFT               (24U)
4879 /*! ASRC - ASRC clock enable */
4880 #define AUDIOMIX_CLKEN0_ASRC(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_ASRC_SHIFT)) & AUDIOMIX_CLKEN0_ASRC_MASK)
4881 
4882 #define AUDIOMIX_CLKEN0_PDM_MASK                 (0x2000000U)
4883 #define AUDIOMIX_CLKEN0_PDM_SHIFT                (25U)
4884 /*! PDM - PDM clock enable */
4885 #define AUDIOMIX_CLKEN0_PDM(x)                   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_PDM_SHIFT)) & AUDIOMIX_CLKEN0_PDM_MASK)
4886 
4887 #define AUDIOMIX_CLKEN0_SDMA2_MASK               (0x4000000U)
4888 #define AUDIOMIX_CLKEN0_SDMA2_SHIFT              (26U)
4889 /*! SDMA2 - SDMA2 clock enable */
4890 #define AUDIOMIX_CLKEN0_SDMA2(x)                 (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SDMA2_SHIFT)) & AUDIOMIX_CLKEN0_SDMA2_MASK)
4891 
4892 #define AUDIOMIX_CLKEN0_SDMA3_MASK               (0x8000000U)
4893 #define AUDIOMIX_CLKEN0_SDMA3_SHIFT              (27U)
4894 /*! SDMA3 - SDMA3 clock enable */
4895 #define AUDIOMIX_CLKEN0_SDMA3(x)                 (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SDMA3_SHIFT)) & AUDIOMIX_CLKEN0_SDMA3_MASK)
4896 
4897 #define AUDIOMIX_CLKEN0_SPBA2_MASK               (0x10000000U)
4898 #define AUDIOMIX_CLKEN0_SPBA2_SHIFT              (28U)
4899 /*! SPBA2 - SPBA2 clock enable */
4900 #define AUDIOMIX_CLKEN0_SPBA2(x)                 (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SPBA2_SHIFT)) & AUDIOMIX_CLKEN0_SPBA2_MASK)
4901 
4902 #define AUDIOMIX_CLKEN0_AUDIODSP_MASK            (0x20000000U)
4903 #define AUDIOMIX_CLKEN0_AUDIODSP_SHIFT           (29U)
4904 /*! AudioDSP - AudioDSP core clock enable */
4905 #define AUDIOMIX_CLKEN0_AUDIODSP(x)              (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_AUDIODSP_SHIFT)) & AUDIOMIX_CLKEN0_AUDIODSP_MASK)
4906 
4907 #define AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_MASK      (0x40000000U)
4908 #define AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_SHIFT     (30U)
4909 /*! AudioDSP_DEBUG - AudioDSP DEBUG clock enable */
4910 #define AUDIOMIX_CLKEN0_AUDIODSP_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_SHIFT)) & AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_MASK)
4911 
4912 #define AUDIOMIX_CLKEN0_EARC_MASK                (0x80000000U)
4913 #define AUDIOMIX_CLKEN0_EARC_SHIFT               (31U)
4914 /*! EARC - EARC clock enable */
4915 #define AUDIOMIX_CLKEN0_EARC(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_EARC_SHIFT)) & AUDIOMIX_CLKEN0_EARC_MASK)
4916 /*! @} */
4917 
4918 /*! @name CLKEN1 - IP Clock Enable Control Register 1 */
4919 /*! @{ */
4920 
4921 #define AUDIOMIX_CLKEN1_OCRAM_A_MASK             (0x1U)
4922 #define AUDIOMIX_CLKEN1_OCRAM_A_SHIFT            (0U)
4923 /*! OCRAM_A - OCRAM_A clock enable */
4924 #define AUDIOMIX_CLKEN1_OCRAM_A(x)               (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_OCRAM_A_SHIFT)) & AUDIOMIX_CLKEN1_OCRAM_A_MASK)
4925 
4926 #define AUDIOMIX_CLKEN1_AUD2HTX_MASK             (0x2U)
4927 #define AUDIOMIX_CLKEN1_AUD2HTX_SHIFT            (1U)
4928 /*! AUD2HTX - AUDIO LINK MASTER clock enable */
4929 #define AUDIOMIX_CLKEN1_AUD2HTX(x)               (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_AUD2HTX_SHIFT)) & AUDIOMIX_CLKEN1_AUD2HTX_MASK)
4930 
4931 #define AUDIOMIX_CLKEN1_EDMA_MASK                (0x4U)
4932 #define AUDIOMIX_CLKEN1_EDMA_SHIFT               (2U)
4933 /*! EDMA - EDMA clock enable */
4934 #define AUDIOMIX_CLKEN1_EDMA(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_EDMA_SHIFT)) & AUDIOMIX_CLKEN1_EDMA_MASK)
4935 
4936 #define AUDIOMIX_CLKEN1_PLL_MASK                 (0x8U)
4937 #define AUDIOMIX_CLKEN1_PLL_SHIFT                (3U)
4938 /*! PLL - PLL clock enable */
4939 #define AUDIOMIX_CLKEN1_PLL(x)                   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_PLL_SHIFT)) & AUDIOMIX_CLKEN1_PLL_MASK)
4940 
4941 #define AUDIOMIX_CLKEN1_MU2_MASK                 (0x10U)
4942 #define AUDIOMIX_CLKEN1_MU2_SHIFT                (4U)
4943 /*! MU2 - MU2 clock enable */
4944 #define AUDIOMIX_CLKEN1_MU2(x)                   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_MU2_SHIFT)) & AUDIOMIX_CLKEN1_MU2_MASK)
4945 
4946 #define AUDIOMIX_CLKEN1_MU3_MASK                 (0x20U)
4947 #define AUDIOMIX_CLKEN1_MU3_SHIFT                (5U)
4948 /*! MU3 - MU3 clock enable */
4949 #define AUDIOMIX_CLKEN1_MU3(x)                   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_MU3_SHIFT)) & AUDIOMIX_CLKEN1_MU3_MASK)
4950 
4951 #define AUDIOMIX_CLKEN1_EARC_PHY_MASK            (0x40U)
4952 #define AUDIOMIX_CLKEN1_EARC_PHY_SHIFT           (6U)
4953 /*! EARC_PHY - EARC PHY audio ss clock enable */
4954 #define AUDIOMIX_CLKEN1_EARC_PHY(x)              (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_EARC_PHY_SHIFT)) & AUDIOMIX_CLKEN1_EARC_PHY_MASK)
4955 /*! @} */
4956 
4957 /*! @name AUDIODSP_REG0 - AudioDSP EXPSTATE Register */
4958 /*! @{ */
4959 
4960 #define AUDIOMIX_AUDIODSP_REG0_EXPSTATE_MASK     (0xFFFFFFFFU)
4961 #define AUDIOMIX_AUDIODSP_REG0_EXPSTATE_SHIFT    (0U)
4962 /*! EXPSTATE - TIE_EXPSTATE output port of the AudioDSP */
4963 #define AUDIOMIX_AUDIODSP_REG0_EXPSTATE(x)       (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG0_EXPSTATE_SHIFT)) & AUDIOMIX_AUDIODSP_REG0_EXPSTATE_MASK)
4964 /*! @} */
4965 
4966 /*! @name AUDIODSP_REG1 - AudioDSP IMPWIRE Register */
4967 /*! @{ */
4968 
4969 #define AUDIOMIX_AUDIODSP_REG1_IMPWIRE_MASK      (0xFFFFFFFFU)
4970 #define AUDIOMIX_AUDIODSP_REG1_IMPWIRE_SHIFT     (0U)
4971 /*! IMPWIRE - TIE_IMPWIRE input port of the AudioDSP */
4972 #define AUDIOMIX_AUDIODSP_REG1_IMPWIRE(x)        (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG1_IMPWIRE_SHIFT)) & AUDIOMIX_AUDIODSP_REG1_IMPWIRE_MASK)
4973 /*! @} */
4974 
4975 /*! @name AUDIODSP_REG2 - AudioDSP XOCDMODE Register */
4976 /*! @{ */
4977 
4978 #define AUDIOMIX_AUDIODSP_REG2_XOCDMODE_MASK     (0x1U)
4979 #define AUDIOMIX_AUDIODSP_REG2_XOCDMODE_SHIFT    (0U)
4980 /*! XOCDMODE - Indicates that the AudioDSP is in OCD halt mode */
4981 #define AUDIOMIX_AUDIODSP_REG2_XOCDMODE(x)       (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_XOCDMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_XOCDMODE_MASK)
4982 
4983 #define AUDIOMIX_AUDIODSP_REG2_PWAITMODE_MASK    (0x2U)
4984 #define AUDIOMIX_AUDIODSP_REG2_PWAITMODE_SHIFT   (1U)
4985 /*! PWAITMODE - Indicates that the AudioDSP is in sleep mode. The processor asserts this signal when
4986  *    it has executed a WAITI instruction and is waiting for an interrupt.
4987  */
4988 #define AUDIOMIX_AUDIODSP_REG2_PWAITMODE(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_PWAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_PWAITMODE_MASK)
4989 
4990 #define AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_MASK (0x10U)
4991 #define AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_SHIFT (4U)
4992 /*! OCDHALTONRESET - AudioDSP enters OCDHaltMode if this signal is samped asserted on reset. */
4993 #define AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_MASK)
4994 
4995 #define AUDIOMIX_AUDIODSP_REG2_RUNSTALL_MASK     (0x20U)
4996 #define AUDIOMIX_AUDIODSP_REG2_RUNSTALL_SHIFT    (5U)
4997 /*! RunStall - AudioDSP RunStall control bit.
4998  *  0b1..stalls the processor
4999  */
5000 #define AUDIOMIX_AUDIODSP_REG2_RUNSTALL(x)       (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_RUNSTALL_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_RUNSTALL_MASK)
5001 
5002 #define AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_MASK (0x40U)
5003 #define AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_SHIFT (6U)
5004 /*! StatVectorSel - Selects between one of two stationary vector bases
5005  *  0b0..default
5006  *  0b1..alternative
5007  */
5008 #define AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL(x)  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_MASK)
5009 
5010 #define AUDIOMIX_AUDIODSP_REG2_ADDRMODE_MASK     (0x100U)
5011 #define AUDIOMIX_AUDIODSP_REG2_ADDRMODE_SHIFT    (8U)
5012 #define AUDIOMIX_AUDIODSP_REG2_ADDRMODE(x)       (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_ADDRMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_ADDRMODE_MASK)
5013 
5014 #define AUDIOMIX_AUDIODSP_REG2_DSMMODE_MASK      (0x200U)
5015 #define AUDIOMIX_AUDIODSP_REG2_DSMMODE_SHIFT     (9U)
5016 /*! DsmMode - AudioDSP in DSM Mode for MU
5017  *  0b0..not in DSM mode
5018  *  0b1..in DSM mode
5019  */
5020 #define AUDIOMIX_AUDIODSP_REG2_DSMMODE(x)        (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_DSMMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_DSMMODE_MASK)
5021 
5022 #define AUDIOMIX_AUDIODSP_REG2_WAITMODE_MASK     (0x400U)
5023 #define AUDIOMIX_AUDIODSP_REG2_WAITMODE_SHIFT    (10U)
5024 /*! WaitMode - AudioDSP in Wait Mode for MU
5025  *  0b0..not in wait mode
5026  *  0b1..in wait mode
5027  */
5028 #define AUDIOMIX_AUDIODSP_REG2_WAITMODE(x)       (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_WAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_WAITMODE_MASK)
5029 
5030 #define AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_MASK    (0x800U)
5031 #define AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_SHIFT   (11U)
5032 /*! m7DsmMode - M7 in DSM Mode for MU3
5033  *  0b0..not in DSM mode
5034  *  0b1..in DSM mode
5035  */
5036 #define AUDIOMIX_AUDIODSP_REG2_M7DSMMODE(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_MASK)
5037 
5038 #define AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_MASK   (0x1000U)
5039 #define AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_SHIFT  (12U)
5040 /*! m7WaitMode - M7 in Wait Mode for MU3
5041  *  0b0..not in wait mode
5042  *  0b1..in wait mode
5043  */
5044 #define AUDIOMIX_AUDIODSP_REG2_M7WAITMODE(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_MASK)
5045 
5046 #define AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_MASK   (0x2000U)
5047 #define AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_SHIFT  (13U)
5048 /*! a53DsmMode - CA53 in DSM Mode for MU2
5049  *  0b0..not in DSM mode
5050  *  0b1..in DSM mode
5051  */
5052 #define AUDIOMIX_AUDIODSP_REG2_A53DSMMODE(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_MASK)
5053 
5054 #define AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_MASK  (0x4000U)
5055 #define AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_SHIFT (14U)
5056 /*! a53WaitMode - CA53 in Wait Mode for MU2
5057  *  0b0..not in wait mode
5058  *  0b1..in wait mode
5059  */
5060 #define AUDIOMIX_AUDIODSP_REG2_A53WAITMODE(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_MASK)
5061 /*! @} */
5062 
5063 /*! @name AUDIODSP_REG3 - AudioDSP PID Register */
5064 /*! @{ */
5065 
5066 #define AUDIOMIX_AUDIODSP_REG3_PID_MASK          (0xFFFFU)
5067 #define AUDIOMIX_AUDIODSP_REG3_PID_SHIFT         (0U)
5068 /*! PID - AudioDSP PID Register. Input to the AudioDSP, latched at reset into the low-order bits of
5069  *    the PRID(processor ID) special register.
5070  */
5071 #define AUDIOMIX_AUDIODSP_REG3_PID(x)            (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG3_PID_SHIFT)) & AUDIOMIX_AUDIODSP_REG3_PID_MASK)
5072 /*! @} */
5073 
5074 /*! @name EARC - EARC Control Register */
5075 /*! @{ */
5076 
5077 #define AUDIOMIX_EARC_RESETB_MASK                (0x1U)
5078 #define AUDIOMIX_EARC_RESETB_SHIFT               (0U)
5079 /*! RESETB - Earc Software Reset.
5080  *  0b0..provide a software reset for EARC controller
5081  *  0b1..return from reset
5082  */
5083 #define AUDIOMIX_EARC_RESETB(x)                  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_EARC_RESETB_SHIFT)) & AUDIOMIX_EARC_RESETB_MASK)
5084 
5085 #define AUDIOMIX_EARC_PHY_RESETB_MASK            (0x2U)
5086 #define AUDIOMIX_EARC_PHY_RESETB_SHIFT           (1U)
5087 /*! PHY_RESETB - Earc PHY Software Reset.
5088  *  0b0..provide a software reset for EARC PHY
5089  *  0b1..return from reset
5090  */
5091 #define AUDIOMIX_EARC_PHY_RESETB(x)              (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_EARC_PHY_RESETB_SHIFT)) & AUDIOMIX_EARC_PHY_RESETB_MASK)
5092 /*! @} */
5093 
5094 /*! @name SAI1_MCLK_SEL - SAI1 MCLK SELECT Register */
5095 /*! @{ */
5096 
5097 #define AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_MASK    (0x1U)
5098 #define AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_SHIFT   (0U)
5099 /*! MCLK1_SEL
5100  *  0b0..SAI1_CLK_ROOT is selected
5101  *  0b1..SAI1.MCLK is selected
5102  */
5103 #define AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_MASK)
5104 
5105 #define AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_MASK    (0x1EU)
5106 #define AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_SHIFT   (1U)
5107 /*! MCLK2_SEL
5108  *  0b0000..SAI1_CLK_ROOT is selected
5109  *  0b0001..SAI2_CLK_ROOT is selected
5110  *  0b0010..SAI3_CLK_ROOT is selected
5111  *  0b0011..Reserved, MCLK2 is 0
5112  *  0b0100..SAI5_CLK_ROOT is selected
5113  *  0b0101..SAI6_CLK_ROOT is selected
5114  *  0b0110..SAI7_CLK_ROOT is selected
5115  *  0b0111..SAI1.MCLK is selected
5116  *  0b1000..SAI2.MCLK is selected
5117  *  0b1001..SAI3.MCLK is selected
5118  *  0b1010..Reserved, MCLK2 is 0
5119  *  0b1011..SAI5.MCLK is selected
5120  *  0b1100..SAI6.MCLK is selected
5121  *  0b1101..SAI7.MCLK is selected
5122  *  0b1110..SPDIF.ETXCLK is selected
5123  */
5124 #define AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_MASK)
5125 /*! @} */
5126 
5127 /*! @name SAI2_MCLK_SEL - SAI2 MCLK SELECT Register */
5128 /*! @{ */
5129 
5130 #define AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_MASK    (0x1U)
5131 #define AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_SHIFT   (0U)
5132 /*! MCLK1_SEL
5133  *  0b0..SAI2_CLK_ROOT is selected
5134  *  0b1..SAI2.MCLK is selected
5135  */
5136 #define AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_MASK)
5137 
5138 #define AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_MASK    (0x1EU)
5139 #define AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_SHIFT   (1U)
5140 /*! MCLK2_SEL
5141  *  0b0000..SAI1_CLK_ROOT is selected
5142  *  0b0001..SAI2_CLK_ROOT is selected
5143  *  0b0010..SAI3_CLK_ROOT is selected
5144  *  0b0011..Reserved, MCLK2 is 0
5145  *  0b0100..SAI5_CLK_ROOT is selected
5146  *  0b0101..SAI6_CLK_ROOT is selected
5147  *  0b0110..SAI7_CLK_ROOT is selected
5148  *  0b0111..SAI1.MCLK is selected
5149  *  0b1000..SAI2.MCLK is selected
5150  *  0b1001..SAI3.MCLK is selected
5151  *  0b1010..Reserved, MCLK is 0
5152  *  0b1011..SAI5.MCLK is selected
5153  *  0b1100..SAI6.MCLK is selected
5154  *  0b1101..SAI7.MCLK is selected
5155  *  0b1110..SPDIF.ETXCLK is selected
5156  */
5157 #define AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_MASK)
5158 /*! @} */
5159 
5160 /*! @name SAI3_MCLK_SEL - SAI3 MCLK SELECT Register */
5161 /*! @{ */
5162 
5163 #define AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_MASK    (0x1U)
5164 #define AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_SHIFT   (0U)
5165 /*! MCLK1_SEL - MCLK1 Select Register
5166  *  0b0..SAI3_CLK_ROOT is selected
5167  *  0b1..SAI3.MCLK is selected
5168  */
5169 #define AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_MASK)
5170 
5171 #define AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_MASK    (0x1EU)
5172 #define AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_SHIFT   (1U)
5173 /*! MCLK2_SEL - MCLK2 Select Register
5174  *  0b0000..SAI1_CLK_ROOT is selected
5175  *  0b0001..SAI2_CLK_ROOT is selected
5176  *  0b0010..SAI3_CLK_ROOT is selected
5177  *  0b0011..Reserved, MCLK2 is 0
5178  *  0b0100..SAI5_CLK_ROOT is selected
5179  *  0b0101..SAI6_CLK_ROOT is selected
5180  *  0b0110..SAI7_CLK_ROOT is selected
5181  *  0b0111..SAI1.MCLK is selected
5182  *  0b1000..SAI2.MCLK is selected
5183  *  0b1001..SAI3.MCLK is selected
5184  *  0b1010..Reserved, MCLK is 0
5185  *  0b1011..SAI5.MCLK is selected
5186  *  0b1100..SAI6.MCLK is selected
5187  *  0b1101..SAI7.MCLK is selected
5188  *  0b1110..SPDIF.ETXCLK is selected
5189  */
5190 #define AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_MASK)
5191 /*! @} */
5192 
5193 /*! @name SAI5_MCLK_SEL - SAI5 MCLK SELECT Register */
5194 /*! @{ */
5195 
5196 #define AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_MASK    (0x1U)
5197 #define AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_SHIFT   (0U)
5198 /*! MCLK1_SEL - MCLK1 Select Register
5199  *  0b0..SAI5_CLK_ROOT is selected
5200  *  0b1..SAI5.MCLK is selected
5201  */
5202 #define AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_MASK)
5203 
5204 #define AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_MASK    (0x1EU)
5205 #define AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_SHIFT   (1U)
5206 /*! MCLK2_SEL - MCLK2 Select Register
5207  *  0b0000..SAI1_CLK_ROOT is selected
5208  *  0b0001..SAI2_CLK_ROOT is selected
5209  *  0b0010..SAI3_CLK_ROOT is selected
5210  *  0b0011..Reserved, MCLK2 is 0
5211  *  0b0100..SAI5_CLK_ROOT is selected
5212  *  0b0101..SAI6_CLK_ROOT is selected
5213  *  0b0110..SAI7_CLK_ROOT is selected
5214  *  0b0111..SAI1.MCLK is selected
5215  *  0b1000..SAI2.MCLK is selected
5216  *  0b1001..SAI3.MCLK is selected
5217  *  0b1010..Reserved, MCLK is 0
5218  *  0b1011..SAI5.MCLK is selected
5219  *  0b1100..SAI6.MCLK is selected
5220  *  0b1101..SAI7.MCLK is selected
5221  *  0b1110..SPDIF.ETXCLK is selected
5222  */
5223 #define AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_MASK)
5224 /*! @} */
5225 
5226 /*! @name SAI6_MCLK_SEL - SAI6 MCLK SELECT Register */
5227 /*! @{ */
5228 
5229 #define AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_MASK    (0x1U)
5230 #define AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_SHIFT   (0U)
5231 /*! MCLK1_SEL - MCLK1 Select Register
5232  *  0b0..SAI6_CLK_ROOT is selected
5233  *  0b1..SAI6.MCLK is selected
5234  */
5235 #define AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_MASK)
5236 
5237 #define AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_MASK    (0x1EU)
5238 #define AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_SHIFT   (1U)
5239 /*! MCLK2_SEL - MCLK2 Select Register
5240  *  0b0000..SAI1_CLK_ROOT is selected
5241  *  0b0001..SAI2_CLK_ROOT is selected
5242  *  0b0010..SAI3_CLK_ROOT is selected
5243  *  0b0011..Reserved, MCLK2 is 0
5244  *  0b0100..SAI5_CLK_ROOT is selected
5245  *  0b0101..SAI6_CLK_ROOT is selected
5246  *  0b0110..SAI7_CLK_ROOT is selected
5247  *  0b0111..SAI1.MCLK is selected
5248  *  0b1000..SAI2.MCLK is selected
5249  *  0b1001..SAI3.MCLK is selected
5250  *  0b1010..Reserved, MCLK is 0
5251  *  0b1011..SAI5.MCLK is selected
5252  *  0b1100..SAI6.MCLK is selected
5253  *  0b1101..SAI7.MCLK is selected
5254  *  0b1110..SPDIF.ETXCLK is selected
5255  */
5256 #define AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_MASK)
5257 /*! @} */
5258 
5259 /*! @name SAI7_MCLK_SEL - SAI7 MCLK SELECT Register */
5260 /*! @{ */
5261 
5262 #define AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_MASK    (0x1U)
5263 #define AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_SHIFT   (0U)
5264 /*! MCLK1_SEL - MCLK1 Select Register
5265  *  0b0..SAI7_CLK_ROOT is selected
5266  *  0b1..SAI7.MCLK is selected
5267  */
5268 #define AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_MASK)
5269 
5270 #define AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_MASK    (0x1EU)
5271 #define AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_SHIFT   (1U)
5272 /*! MCLK2_SEL - MCLK2 Select Register
5273  *  0b0000..SAI1_CLK_ROOT is selected
5274  *  0b0001..SAI2_CLK_ROOT is selected
5275  *  0b0010..SAI3_CLK_ROOT is selected
5276  *  0b0011..Reserved, MCLK2 is 0
5277  *  0b0100..SAI5_CLK_ROOT is selected
5278  *  0b0101..SAI6_CLK_ROOT is selected
5279  *  0b0110..SAI7_CLK_ROOT is selected
5280  *  0b0111..SAI1.MCLK is selected
5281  *  0b1000..SAI2.MCLK is selected
5282  *  0b1001..SAI3.MCLK is selected
5283  *  0b1010..Reserved, MCLK is 0
5284  *  0b1011..SAI5.MCLK is selected
5285  *  0b1100..SAI6.MCLK is selected
5286  *  0b1101..SAI7.MCLK is selected
5287  *  0b1110..SPDIF.ETXCLK is selected
5288  */
5289 #define AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_MASK)
5290 /*! @} */
5291 
5292 /*! @name PDM_CLK - PDM Root Clock Select Register */
5293 /*! @{ */
5294 
5295 #define AUDIOMIX_PDM_CLK_SELECT_MASK             (0x3U)
5296 #define AUDIOMIX_PDM_CLK_SELECT_SHIFT            (0U)
5297 /*! select - PDM Root Clock Select Bits
5298  *  0b00..ccm pdm clock is selected
5299  *  0b01..sai_pll div2 is selected
5300  *  0b10..SAI1_MCLK is selected
5301  *  0b11..reserved.
5302  */
5303 #define AUDIOMIX_PDM_CLK_SELECT(x)               (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_PDM_CLK_SELECT_SHIFT)) & AUDIOMIX_PDM_CLK_SELECT_MASK)
5304 /*! @} */
5305 
5306 /*! @name SAI_PLL_GNRL_CTL - SAI PLL General control Register */
5307 /*! @{ */
5308 
5309 #define AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_MASK (0x3U)
5310 #define AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_SHIFT (0U)
5311 /*! ref_clk_sel - reference clock select */
5312 #define AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_MASK)
5313 
5314 #define AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_MASK (0xCU)
5315 #define AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_SHIFT (2U)
5316 /*! pad_clk_sel - pad clock select */
5317 #define AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_MASK)
5318 
5319 #define AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_MASK    (0x10U)
5320 #define AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_SHIFT   (4U)
5321 /*! bypass - pll bypass */
5322 #define AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_MASK)
5323 
5324 #define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_MASK (0x100U)
5325 #define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_SHIFT (8U)
5326 /*! resetb_override - resetb override */
5327 #define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_MASK)
5328 
5329 #define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_MASK    (0x200U)
5330 #define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_SHIFT   (9U)
5331 /*! resetb - pll resetb */
5332 #define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_MASK)
5333 
5334 #define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_MASK (0x1000U)
5335 #define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_SHIFT (12U)
5336 /*! cke_override - pll cke override. */
5337 #define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_MASK)
5338 
5339 #define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_MASK       (0x2000U)
5340 #define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_SHIFT      (13U)
5341 /*! cke - pll cke */
5342 #define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE(x)         (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_MASK)
5343 
5344 #define AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_MASK (0x10000U)
5345 #define AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_SHIFT (16U)
5346 /*! blk_bypass - blk bypass */
5347 #define AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS(x)  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_MASK)
5348 
5349 #define AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_MASK      (0x80000000U)
5350 #define AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_SHIFT     (31U)
5351 /*! lock - pll lock */
5352 #define AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_MASK)
5353 /*! @} */
5354 
5355 /*! @name SAI_PLL_FDIV_CTL0 - SAI PLL Frequency Divider control Register */
5356 /*! @{ */
5357 
5358 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_MASK (0x7U)
5359 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_SHIFT (0U)
5360 /*! post_div - post divider value */
5361 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV(x)   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_MASK)
5362 
5363 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_MASK  (0x3F0U)
5364 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_SHIFT (4U)
5365 /*! pre_div - pre divider value */
5366 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_MASK)
5367 
5368 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_MASK (0x3FF000U)
5369 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_SHIFT (12U)
5370 /*! main_div - main divider value */
5371 #define AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV(x)   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_MASK)
5372 /*! @} */
5373 
5374 /*! @name SAI_PLL_FDIV_CTL1 - SAI PLL DSM value Register */
5375 /*! @{ */
5376 
5377 #define AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_MASK      (0xFFFFU)
5378 #define AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_SHIFT     (0U)
5379 /*! dsm - pll DSM(K) value */
5380 #define AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM(x)        (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_MASK)
5381 /*! @} */
5382 
5383 /*! @name SAI_PLL_SSCG_CTL - SAI PLL SSCG control Register */
5384 /*! @{ */
5385 
5386 #define AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_MASK    (0x3U)
5387 #define AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_SHIFT   (0U)
5388 /*! sel_pf - pll modulation method control */
5389 #define AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_MASK)
5390 
5391 #define AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_MASK  (0x3F0U)
5392 #define AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_SHIFT (4U)
5393 /*! mrat_ctl - pll modulation rate control */
5394 #define AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_MASK)
5395 
5396 #define AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_MASK (0xFF000U)
5397 #define AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_SHIFT (12U)
5398 /*! mfreq_ctl - pll modulation frequency control */
5399 #define AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL(x)   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_MASK)
5400 
5401 #define AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_MASK   (0x80000000U)
5402 #define AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_SHIFT  (31U)
5403 /*! sscg_en - SSCG Enable Bit */
5404 #define AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_MASK)
5405 /*! @} */
5406 
5407 /*! @name SAI_PLL_MNIT_CTL - SAI PLL SSCG control Register */
5408 /*! @{ */
5409 
5410 #define AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_MASK       (0x7U)
5411 #define AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_SHIFT      (0U)
5412 /*! icp - Charge-pump current control */
5413 #define AUDIOMIX_SAI_PLL_MNIT_CTL_ICP(x)         (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_MASK)
5414 
5415 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_MASK   (0x8U)
5416 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_SHIFT  (3U)
5417 /*! afc_enb - AFC Enable control */
5418 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_MASK)
5419 
5420 #define AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_MASK    (0x1F0U)
5421 #define AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_SHIFT   (4U)
5422 /*! extafc - AFC Enable control */
5423 #define AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC(x)      (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_MASK)
5424 
5425 #define AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_MASK   (0x4000U)
5426 #define AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_SHIFT  (14U)
5427 /*! feed_en - PLL FEED Enable control */
5428 #define AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_MASK)
5429 
5430 #define AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_MASK      (0x8000U)
5431 #define AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_SHIFT     (15U)
5432 /*! fsel - PLL FEED SEL control */
5433 #define AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL(x)        (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_MASK)
5434 
5435 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_MASK (0x20000U)
5436 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_SHIFT (17U)
5437 /*! afcinit_sel - PLL AFC INIT SEL */
5438 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_MASK)
5439 
5440 #define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_MASK (0x40000U)
5441 #define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_SHIFT (18U)
5442 /*! pbias_ctrl_en - PLL PBIAS CTRL EN */
5443 #define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_MASK)
5444 
5445 #define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_MASK (0x80000U)
5446 #define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_SHIFT (19U)
5447 /*! pbias_ctrl - PLL PBIAS CTRL */
5448 #define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_MASK)
5449 
5450 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_MASK   (0x100000U)
5451 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_SHIFT  (20U)
5452 /*! afc_sel - PLL AFC SEL */
5453 #define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_MASK)
5454 /*! @} */
5455 
5456 /*! @name AUDIO_EXT_ADDR - AUDIOMIX Extra Addr Bits Register */
5457 /*! @{ */
5458 
5459 #define AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_MASK       (0x3U)
5460 #define AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_SHIFT      (0U)
5461 /*! sdma2 - SDMA2 Extra Addr Bits */
5462 #define AUDIOMIX_AUDIO_EXT_ADDR_SDMA2(x)         (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_SHIFT)) & AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_MASK)
5463 
5464 #define AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_MASK       (0xCU)
5465 #define AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_SHIFT      (2U)
5466 /*! sdma3 - SDMA3 Extra Addr Bits */
5467 #define AUDIOMIX_AUDIO_EXT_ADDR_SDMA3(x)         (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_SHIFT)) & AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_MASK)
5468 
5469 #define AUDIOMIX_AUDIO_EXT_ADDR_EDMA_MASK        (0x30U)
5470 #define AUDIOMIX_AUDIO_EXT_ADDR_EDMA_SHIFT       (4U)
5471 /*! edma - EDMA extra Addr Bits */
5472 #define AUDIOMIX_AUDIO_EXT_ADDR_EDMA(x)          (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_EXT_ADDR_EDMA_SHIFT)) & AUDIOMIX_AUDIO_EXT_ADDR_EDMA_MASK)
5473 /*! @} */
5474 
5475 /*! @name IPG_LP_CTRL - IPG Low Power Control Register */
5476 /*! @{ */
5477 
5478 #define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_MASK  (0x1U)
5479 #define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_SHIFT (0U)
5480 /*! edma_ipg_stop - EDMA IPG_STOP Bit */
5481 #define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_MASK)
5482 
5483 #define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_MASK (0x2U)
5484 #define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_SHIFT (1U)
5485 /*! sdma2_ipg_stop - SDMA2 IPG_STOP Bit */
5486 #define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP(x)   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_MASK)
5487 
5488 #define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_MASK (0x4U)
5489 #define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_SHIFT (2U)
5490 /*! sdma3_ipg_stop - SDMA3 IPG_STOP Bit */
5491 #define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP(x)   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_MASK)
5492 
5493 #define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_MASK   (0x8U)
5494 #define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_SHIFT  (3U)
5495 /*! pdm_ipg_stop - PDM IPG_STOP Bit */
5496 #define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP(x)     (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_MASK)
5497 
5498 #define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_MASK  (0x10U)
5499 #define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_SHIFT (4U)
5500 /*! sai1_ipg_stop - SAI1 IPG_STOP Bit */
5501 #define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_MASK)
5502 
5503 #define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_MASK  (0x20U)
5504 #define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_SHIFT (5U)
5505 /*! sai2_ipg_stop - SAI2 IPG_STOP Bit */
5506 #define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_MASK)
5507 
5508 #define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_MASK  (0x40U)
5509 #define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_SHIFT (6U)
5510 /*! sai3_ipg_stop - SAI3 IPG_STOP Bit */
5511 #define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_MASK)
5512 
5513 #define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_MASK  (0x80U)
5514 #define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_SHIFT (7U)
5515 /*! sai5_ipg_stop - SAI5 IPG_STOP Bit */
5516 #define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_MASK)
5517 
5518 #define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_MASK  (0x100U)
5519 #define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_SHIFT (8U)
5520 /*! sai6_ipg_stop - SAI6 IPG_STOP Bit */
5521 #define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_MASK)
5522 
5523 #define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_MASK  (0x200U)
5524 #define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_SHIFT (9U)
5525 /*! sai7_ipg_stop - SAI1 IPG_STOP Bit */
5526 #define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_MASK)
5527 
5528 #define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_MASK (0x400U)
5529 #define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_SHIFT (10U)
5530 /*! edma_ipg_stop_ack - EDMA IPG_STOP_ACK Bit */
5531 #define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_MASK)
5532 
5533 #define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_MASK (0x800U)
5534 #define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_SHIFT (11U)
5535 /*! sdma2_ipg_stop_ack - SDMA2 IPG_STOP_ACK Bit */
5536 #define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_MASK)
5537 
5538 #define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_MASK (0x1000U)
5539 #define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_SHIFT (12U)
5540 /*! sdma3_ipg_stop_ack - SDMA3 IPG_STOP_ACK Bit */
5541 #define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_MASK)
5542 
5543 #define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_MASK (0x2000U)
5544 #define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_SHIFT (13U)
5545 /*! pdm_ipg_stop_ack - PDM IPG_STOP_ACK Bit */
5546 #define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_MASK)
5547 
5548 #define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_MASK (0x4000U)
5549 #define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_SHIFT (14U)
5550 /*! sai1_ipg_stop_ack - SAI1 IPG_STOP_ACK Bit */
5551 #define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_MASK)
5552 
5553 #define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_MASK (0x8000U)
5554 #define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_SHIFT (15U)
5555 /*! sai2_ipg_stop_ack - SAI2 IPG_STOP_ACK Bit */
5556 #define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_MASK)
5557 
5558 #define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_MASK (0x10000U)
5559 #define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_SHIFT (16U)
5560 /*! sai3_ipg_stop_ack - SAI3 IPG_STOP_ACK Bit */
5561 #define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_MASK)
5562 
5563 #define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_MASK (0x20000U)
5564 #define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_SHIFT (17U)
5565 /*! sai5_ipg_stop_ack - SAI5 IPG_STOP_ACK Bit */
5566 #define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_MASK)
5567 
5568 #define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_MASK (0x40000U)
5569 #define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_SHIFT (18U)
5570 /*! sai6_ipg_stop_ack - SAI6 IPG_STOP_ACK Bit */
5571 #define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_MASK)
5572 
5573 #define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_MASK (0x80000U)
5574 #define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_SHIFT (19U)
5575 /*! sai7_ipg_stop_ack - SAI1 IPG_STOP_ACK Bit */
5576 #define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_MASK)
5577 /*! @} */
5578 
5579 /*! @name AUDIO_AXI_LIMIT - AUDIOMIX AXI LIMIT CTRL Register */
5580 /*! @{ */
5581 
5582 #define AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_MASK     (0x1U)
5583 #define AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_SHIFT    (0U)
5584 /*! enable - AXI Limit enable */
5585 #define AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_SHIFT)) & AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_MASK)
5586 
5587 #define AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_MASK (0xFFFF0U)
5588 #define AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_SHIFT (4U)
5589 /*! BEAT_LIMIT - Beat Limit. Limit the burst beat number from AudioDSP. */
5590 #define AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT(x)   (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_SHIFT)) & AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_MASK)
5591 /*! @} */
5592 
5593 
5594 /*!
5595  * @}
5596  */ /* end of group AUDIOMIX_Register_Masks */
5597 
5598 
5599 /* AUDIOMIX - Peripheral instance base addresses */
5600 /** Peripheral AUDIOMIX base address */
5601 #define AUDIOMIX_BASE                            (0x30E20000u)
5602 /** Peripheral AUDIOMIX base pointer */
5603 #define AUDIOMIX                                 ((AUDIOMIX_Type *)AUDIOMIX_BASE)
5604 /** Array initializer of AUDIOMIX peripheral base addresses */
5605 #define AUDIOMIX_BASE_ADDRS                      { AUDIOMIX_BASE }
5606 /** Array initializer of AUDIOMIX peripheral base pointers */
5607 #define AUDIOMIX_BASE_PTRS                       { AUDIOMIX }
5608 
5609 /*!
5610  * @}
5611  */ /* end of group AUDIOMIX_Peripheral_Access_Layer */
5612 
5613 
5614 /* ----------------------------------------------------------------------------
5615    -- AUDIOPACKETIZER Peripheral Access Layer
5616    ---------------------------------------------------------------------------- */
5617 
5618 /*!
5619  * @addtogroup AUDIOPACKETIZER_Peripheral_Access_Layer AUDIOPACKETIZER Peripheral Access Layer
5620  * @{
5621  */
5622 
5623 /** AUDIOPACKETIZER - Register Layout Typedef */
5624 typedef struct {
5625   __IO uint8_t AUD_N1;                             /**< Audio Clock Regenerator N Value Register 1 For N expected values, refer to the HDMI 1., offset: 0x0 */
5626   __IO uint8_t AUD_N2;                             /**< Audio Clock Regenerator N Value Register 2 For N expected values, refer to the HDMI 1., offset: 0x1 */
5627   __IO uint8_t AUD_N3;                             /**< Audio Clock Regenerator N Value Register 3 For N expected values, refer to the HDMI 1., offset: 0x2 */
5628   __IO uint8_t AUD_CTS1;                           /**< Audio Clock Regenerator CTS Value Register 1 For CTS expected values, refer to the HDMI 1., offset: 0x3 */
5629   __IO uint8_t AUD_CTS2;                           /**< Audio Clock Regenerator CTS Register 2 For CTS expected values, refer to the HDMI 1., offset: 0x4 */
5630   __IO uint8_t AUD_CTS3;                           /**< Audio Clock Regenerator CTS value Register 3., offset: 0x5 */
5631        uint8_t AUD_INPUTCLKFS;                     /**< Audio Input Clock FS Factor Register, offset: 0x6 */
5632   __IO uint8_t AUD_CTS_DITHER;                     /**< Audio CTS Dither Register, offset: 0x7 */
5633 } AUDIOPACKETIZER_Type;
5634 
5635 /* ----------------------------------------------------------------------------
5636    -- AUDIOPACKETIZER Register Masks
5637    ---------------------------------------------------------------------------- */
5638 
5639 /*!
5640  * @addtogroup AUDIOPACKETIZER_Register_Masks AUDIOPACKETIZER Register Masks
5641  * @{
5642  */
5643 
5644 /*! @name AUD_N1 - Audio Clock Regenerator N Value Register 1 For N expected values, refer to the HDMI 1. */
5645 /*! @{ */
5646 
5647 #define AUDIOPACKETIZER_AUD_N1_AUDN_MASK         (0xFFU)
5648 #define AUDIOPACKETIZER_AUD_N1_AUDN_SHIFT        (0U)
5649 /*! AudN - HDMI Audio Clock Regenerator N value */
5650 #define AUDIOPACKETIZER_AUD_N1_AUDN(x)           (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N1_AUDN_SHIFT)) & AUDIOPACKETIZER_AUD_N1_AUDN_MASK)
5651 /*! @} */
5652 
5653 /*! @name AUD_N2 - Audio Clock Regenerator N Value Register 2 For N expected values, refer to the HDMI 1. */
5654 /*! @{ */
5655 
5656 #define AUDIOPACKETIZER_AUD_N2_AUDN_MASK         (0xFFU)
5657 #define AUDIOPACKETIZER_AUD_N2_AUDN_SHIFT        (0U)
5658 /*! AudN - HDMI Audio Clock Regenerator N value */
5659 #define AUDIOPACKETIZER_AUD_N2_AUDN(x)           (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N2_AUDN_SHIFT)) & AUDIOPACKETIZER_AUD_N2_AUDN_MASK)
5660 /*! @} */
5661 
5662 /*! @name AUD_N3 - Audio Clock Regenerator N Value Register 3 For N expected values, refer to the HDMI 1. */
5663 /*! @{ */
5664 
5665 #define AUDIOPACKETIZER_AUD_N3_AUDN_MASK         (0xFU)
5666 #define AUDIOPACKETIZER_AUD_N3_AUDN_SHIFT        (0U)
5667 /*! AudN - HDMI Audio Clock Regenerator N value */
5668 #define AUDIOPACKETIZER_AUD_N3_AUDN(x)           (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N3_AUDN_SHIFT)) & AUDIOPACKETIZER_AUD_N3_AUDN_MASK)
5669 
5670 #define AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_MASK (0x80U)
5671 #define AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_SHIFT (7U)
5672 /*! ncts_atomic_write - When set, the new N and CTS values are only used when aud_n1 register is written. */
5673 #define AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_SHIFT)) & AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_MASK)
5674 /*! @} */
5675 
5676 /*! @name AUD_CTS1 - Audio Clock Regenerator CTS Value Register 1 For CTS expected values, refer to the HDMI 1. */
5677 /*! @{ */
5678 
5679 #define AUDIOPACKETIZER_AUD_CTS1_AUDCTS_MASK     (0xFFU)
5680 #define AUDIOPACKETIZER_AUD_CTS1_AUDCTS_SHIFT    (0U)
5681 /*! AudCTS - HDMI Audio Clock Regenerator CTS calculated value. */
5682 #define AUDIOPACKETIZER_AUD_CTS1_AUDCTS(x)       (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS1_AUDCTS_SHIFT)) & AUDIOPACKETIZER_AUD_CTS1_AUDCTS_MASK)
5683 /*! @} */
5684 
5685 /*! @name AUD_CTS2 - Audio Clock Regenerator CTS Register 2 For CTS expected values, refer to the HDMI 1. */
5686 /*! @{ */
5687 
5688 #define AUDIOPACKETIZER_AUD_CTS2_AUDCTS_MASK     (0xFFU)
5689 #define AUDIOPACKETIZER_AUD_CTS2_AUDCTS_SHIFT    (0U)
5690 /*! AudCTS - HDMI Audio Clock Regenerator CTS calculated value. */
5691 #define AUDIOPACKETIZER_AUD_CTS2_AUDCTS(x)       (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS2_AUDCTS_SHIFT)) & AUDIOPACKETIZER_AUD_CTS2_AUDCTS_MASK)
5692 /*! @} */
5693 
5694 /*! @name AUD_CTS3 - Audio Clock Regenerator CTS value Register 3. */
5695 /*! @{ */
5696 
5697 #define AUDIOPACKETIZER_AUD_CTS3_AUDCTS_MASK     (0xFU)
5698 #define AUDIOPACKETIZER_AUD_CTS3_AUDCTS_SHIFT    (0U)
5699 /*! AudCTS - HDMI Audio Clock Regenerator CTS calculated value. */
5700 #define AUDIOPACKETIZER_AUD_CTS3_AUDCTS(x)       (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS3_AUDCTS_SHIFT)) & AUDIOPACKETIZER_AUD_CTS3_AUDCTS_MASK)
5701 
5702 #define AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_MASK (0x10U)
5703 #define AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_SHIFT (4U)
5704 /*! CTS_manual - If the CTS_manual bit equals 0b, this registers contains audCTS[19:0] generated by
5705  *    the Cycle time counter according to the specified timing.
5706  */
5707 #define AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL(x)   (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_SHIFT)) & AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_MASK)
5708 
5709 #define AUDIOPACKETIZER_AUD_CTS3_SPARE_MASK      (0xE0U)
5710 #define AUDIOPACKETIZER_AUD_CTS3_SPARE_SHIFT     (5U)
5711 /*! spare - Reserved as "spare" bit with no associated functionality. */
5712 #define AUDIOPACKETIZER_AUD_CTS3_SPARE(x)        (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS3_SPARE_SHIFT)) & AUDIOPACKETIZER_AUD_CTS3_SPARE_MASK)
5713 /*! @} */
5714 
5715 /*! @name AUD_CTS_DITHER - Audio CTS Dither Register */
5716 /*! @{ */
5717 
5718 #define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_MASK (0xFU)
5719 #define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_SHIFT (0U)
5720 /*! divisor - Dither divisor (4'd1 if no CTS Dither) This field should be configured with the value
5721  *    of divisor from the HDMI specification.
5722  */
5723 #define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_SHIFT)) & AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_MASK)
5724 
5725 #define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_MASK (0xF0U)
5726 #define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_SHIFT (4U)
5727 /*! dividend - Dither dividend (4'd1 if no CTS Dither) This field should be configured with the
5728  *    value of dividend from the HDMI specification.
5729  */
5730 #define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_SHIFT)) & AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_MASK)
5731 /*! @} */
5732 
5733 
5734 /*!
5735  * @}
5736  */ /* end of group AUDIOPACKETIZER_Register_Masks */
5737 
5738 
5739 /* AUDIOPACKETIZER - Peripheral instance base addresses */
5740 /** Peripheral AUDIOPACKETIZER base address */
5741 #define AUDIOPACKETIZER_BASE                     (0x32FDB200u)
5742 /** Peripheral AUDIOPACKETIZER base pointer */
5743 #define AUDIOPACKETIZER                          ((AUDIOPACKETIZER_Type *)AUDIOPACKETIZER_BASE)
5744 /** Array initializer of AUDIOPACKETIZER peripheral base addresses */
5745 #define AUDIOPACKETIZER_BASE_ADDRS               { AUDIOPACKETIZER_BASE }
5746 /** Array initializer of AUDIOPACKETIZER peripheral base pointers */
5747 #define AUDIOPACKETIZER_BASE_PTRS                { AUDIOPACKETIZER }
5748 
5749 /*!
5750  * @}
5751  */ /* end of group AUDIOPACKETIZER_Peripheral_Access_Layer */
5752 
5753 
5754 /* ----------------------------------------------------------------------------
5755    -- AUDIOSAMPLEGP Peripheral Access Layer
5756    ---------------------------------------------------------------------------- */
5757 
5758 /*!
5759  * @addtogroup AUDIOSAMPLEGP_Peripheral_Access_Layer AUDIOSAMPLEGP Peripheral Access Layer
5760  * @{
5761  */
5762 
5763 /** AUDIOSAMPLEGP - Register Layout Typedef */
5764 typedef struct {
5765   __IO uint8_t GP_CONF0;                           /**< Audio GPA Software FIFO Reset Control Register 0, offset: 0x0 */
5766   __IO uint8_t GP_CONF1;                           /**< Audio GPA Channel Enable Configuration Register 1, offset: 0x1 */
5767   __IO uint8_t GP_CONF2;                           /**< Audio GPA HBR Enable Register 2, offset: 0x2 */
5768        uint8_t RESERVED_0[3];
5769   __IO uint8_t GP_MASK;                            /**< Audio GPA FIFO Full and Empty Mask Interrupt Register, offset: 0x6 */
5770 } AUDIOSAMPLEGP_Type;
5771 
5772 /* ----------------------------------------------------------------------------
5773    -- AUDIOSAMPLEGP Register Masks
5774    ---------------------------------------------------------------------------- */
5775 
5776 /*!
5777  * @addtogroup AUDIOSAMPLEGP_Register_Masks AUDIOSAMPLEGP Register Masks
5778  * @{
5779  */
5780 
5781 /*! @name GP_CONF0 - Audio GPA Software FIFO Reset Control Register 0 */
5782 /*! @{ */
5783 
5784 #define AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_MASK (0x1U)
5785 #define AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_SHIFT (0U)
5786 /*! sw_audio_fifo_rst - Audio FIFOs software reset - Writing 0b: no action taken - Writing 1b:
5787  *    Resets all audio FIFOs Reading from this register always returns 0b.
5788  */
5789 #define AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_SHIFT)) & AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_MASK)
5790 /*! @} */
5791 
5792 /*! @name GP_CONF1 - Audio GPA Channel Enable Configuration Register 1 */
5793 /*! @{ */
5794 
5795 #define AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_MASK     (0xFFU)
5796 #define AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_SHIFT    (0U)
5797 /*! ch_in_en - Each bit controls the enabling of the respective audio channel. */
5798 #define AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN(x)       (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_SHIFT)) & AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_MASK)
5799 /*! @} */
5800 
5801 /*! @name GP_CONF2 - Audio GPA HBR Enable Register 2 */
5802 /*! @{ */
5803 
5804 #define AUDIOSAMPLEGP_GP_CONF2_HBR_MASK          (0x1U)
5805 #define AUDIOSAMPLEGP_GP_CONF2_HBR_SHIFT         (0U)
5806 /*! HBR - HBR packets enable. */
5807 #define AUDIOSAMPLEGP_GP_CONF2_HBR(x)            (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF2_HBR_SHIFT)) & AUDIOSAMPLEGP_GP_CONF2_HBR_MASK)
5808 
5809 #define AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_MASK  (0x2U)
5810 #define AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_SHIFT (1U)
5811 /*! insert_pcuv - When set (1'b1), this bit enables the insertion of the PCUV (Parity, Channel
5812  *    Status, User bit and Validity) bits on the incoming audio stream (support limited to Linear PCM
5813  *    audio).
5814  */
5815 #define AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV(x)    (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_SHIFT)) & AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_MASK)
5816 /*! @} */
5817 
5818 /*! @name GP_MASK - Audio GPA FIFO Full and Empty Mask Interrupt Register */
5819 /*! @{ */
5820 
5821 #define AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_MASK (0x1U)
5822 #define AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_SHIFT (0U)
5823 /*! fifo_full_mask - FIFO full flag mask */
5824 #define AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK(x)  (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_SHIFT)) & AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_MASK)
5825 
5826 #define AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_MASK (0x2U)
5827 #define AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_SHIFT (1U)
5828 /*! fifo_empty_mask - FIFO empty flag mask */
5829 #define AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_SHIFT)) & AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_MASK)
5830 
5831 #define AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_MASK (0x10U)
5832 #define AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_SHIFT (4U)
5833 /*! fifo_overrun_mask - FIFO overrun mask */
5834 #define AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_SHIFT)) & AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_MASK)
5835 /*! @} */
5836 
5837 
5838 /*!
5839  * @}
5840  */ /* end of group AUDIOSAMPLEGP_Register_Masks */
5841 
5842 
5843 /* AUDIOSAMPLEGP - Peripheral instance base addresses */
5844 /** Peripheral AUDIOSAMPLEGP base address */
5845 #define AUDIOSAMPLEGP_BASE                       (0x32FDB500u)
5846 /** Peripheral AUDIOSAMPLEGP base pointer */
5847 #define AUDIOSAMPLEGP                            ((AUDIOSAMPLEGP_Type *)AUDIOSAMPLEGP_BASE)
5848 /** Array initializer of AUDIOSAMPLEGP peripheral base addresses */
5849 #define AUDIOSAMPLEGP_BASE_ADDRS                 { AUDIOSAMPLEGP_BASE }
5850 /** Array initializer of AUDIOSAMPLEGP peripheral base pointers */
5851 #define AUDIOSAMPLEGP_BASE_PTRS                  { AUDIOSAMPLEGP }
5852 
5853 /*!
5854  * @}
5855  */ /* end of group AUDIOSAMPLEGP_Peripheral_Access_Layer */
5856 
5857 
5858 /* ----------------------------------------------------------------------------
5859    -- BCH Peripheral Access Layer
5860    ---------------------------------------------------------------------------- */
5861 
5862 /*!
5863  * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
5864  * @{
5865  */
5866 
5867 /** BCH - Register Layout Typedef */
5868 typedef struct {
5869   __IO uint32_t CTRL;                              /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
5870   __IO uint32_t CTRL_SET;                          /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
5871   __IO uint32_t CTRL_CLR;                          /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
5872   __IO uint32_t CTRL_TOG;                          /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
5873   __I  uint32_t STATUS0;                           /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
5874        uint8_t RESERVED_0[12];
5875   __IO uint32_t MODE;                              /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
5876        uint8_t RESERVED_1[12];
5877   __IO uint32_t ENCODEPTR;                         /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
5878        uint8_t RESERVED_2[12];
5879   __IO uint32_t DATAPTR;                           /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
5880        uint8_t RESERVED_3[12];
5881   __IO uint32_t METAPTR;                           /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
5882        uint8_t RESERVED_4[28];
5883   __IO uint32_t LAYOUTSELECT;                      /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
5884        uint8_t RESERVED_5[12];
5885   __IO uint32_t FLASH0LAYOUT0;                     /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
5886        uint8_t RESERVED_6[12];
5887   __IO uint32_t FLASH0LAYOUT1;                     /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
5888        uint8_t RESERVED_7[12];
5889   __IO uint32_t FLASH1LAYOUT0;                     /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
5890        uint8_t RESERVED_8[12];
5891   __IO uint32_t FLASH1LAYOUT1;                     /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
5892        uint8_t RESERVED_9[12];
5893   __IO uint32_t FLASH2LAYOUT0;                     /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
5894        uint8_t RESERVED_10[12];
5895   __IO uint32_t FLASH2LAYOUT1;                     /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
5896        uint8_t RESERVED_11[12];
5897   __IO uint32_t FLASH3LAYOUT0;                     /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
5898        uint8_t RESERVED_12[12];
5899   __IO uint32_t FLASH3LAYOUT1;                     /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
5900        uint8_t RESERVED_13[12];
5901   __IO uint32_t DEBUG0;                            /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
5902   __IO uint32_t DEBUG0_SET;                        /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
5903   __IO uint32_t DEBUG0_CLR;                        /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
5904   __IO uint32_t DEBUG0_TOG;                        /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
5905   __I  uint32_t DBGKESREAD;                        /**< KES Debug Read Register, offset: 0x110 */
5906        uint8_t RESERVED_14[12];
5907   __I  uint32_t DBGCSFEREAD;                       /**< Chien Search Debug Read Register, offset: 0x120 */
5908        uint8_t RESERVED_15[12];
5909   __I  uint32_t DBGSYNDGENREAD;                    /**< Syndrome Generator Debug Read Register, offset: 0x130 */
5910        uint8_t RESERVED_16[12];
5911   __I  uint32_t DBGAHBMREAD;                       /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
5912        uint8_t RESERVED_17[12];
5913   __I  uint32_t BLOCKNAME;                         /**< Block Name Register, offset: 0x150 */
5914        uint8_t RESERVED_18[12];
5915   __I  uint32_t VERSION;                           /**< BCH Version Register, offset: 0x160 */
5916        uint8_t RESERVED_19[12];
5917   __IO uint32_t DEBUG1;                            /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
5918 } BCH_Type;
5919 
5920 /* ----------------------------------------------------------------------------
5921    -- BCH Register Masks
5922    ---------------------------------------------------------------------------- */
5923 
5924 /*!
5925  * @addtogroup BCH_Register_Masks BCH Register Masks
5926  * @{
5927  */
5928 
5929 /*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
5930 /*! @{ */
5931 
5932 #define BCH_CTRL_COMPLETE_IRQ_MASK               (0x1U)
5933 #define BCH_CTRL_COMPLETE_IRQ_SHIFT              (0U)
5934 #define BCH_CTRL_COMPLETE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
5935 
5936 #define BCH_CTRL_RSVD0_MASK                      (0x2U)
5937 #define BCH_CTRL_RSVD0_SHIFT                     (1U)
5938 /*! RSVD0 - This field is reserved. */
5939 #define BCH_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
5940 
5941 #define BCH_CTRL_DEBUG_STALL_IRQ_MASK            (0x4U)
5942 #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           (2U)
5943 #define BCH_CTRL_DEBUG_STALL_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
5944 
5945 #define BCH_CTRL_BM_ERROR_IRQ_MASK               (0x8U)
5946 #define BCH_CTRL_BM_ERROR_IRQ_SHIFT              (3U)
5947 #define BCH_CTRL_BM_ERROR_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
5948 
5949 #define BCH_CTRL_RSVD1_MASK                      (0xF0U)
5950 #define BCH_CTRL_RSVD1_SHIFT                     (4U)
5951 /*! RSVD1 - This field is reserved. */
5952 #define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
5953 
5954 #define BCH_CTRL_COMPLETE_IRQ_EN_MASK            (0x100U)
5955 #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           (8U)
5956 #define BCH_CTRL_COMPLETE_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
5957 
5958 #define BCH_CTRL_RSVD2_MASK                      (0x200U)
5959 #define BCH_CTRL_RSVD2_SHIFT                     (9U)
5960 /*! RSVD2 - This field is reserved. */
5961 #define BCH_CTRL_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
5962 
5963 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         (0x400U)
5964 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        (10U)
5965 #define BCH_CTRL_DEBUG_STALL_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
5966 
5967 #define BCH_CTRL_RSVD3_MASK                      (0xF800U)
5968 #define BCH_CTRL_RSVD3_SHIFT                     (11U)
5969 /*! RSVD3 - This field is reserved. */
5970 #define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
5971 
5972 #define BCH_CTRL_M2M_ENABLE_MASK                 (0x10000U)
5973 #define BCH_CTRL_M2M_ENABLE_SHIFT                (16U)
5974 #define BCH_CTRL_M2M_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
5975 
5976 #define BCH_CTRL_M2M_ENCODE_MASK                 (0x20000U)
5977 #define BCH_CTRL_M2M_ENCODE_SHIFT                (17U)
5978 #define BCH_CTRL_M2M_ENCODE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
5979 
5980 #define BCH_CTRL_M2M_LAYOUT_MASK                 (0xC0000U)
5981 #define BCH_CTRL_M2M_LAYOUT_SHIFT                (18U)
5982 #define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
5983 
5984 #define BCH_CTRL_RSVD4_MASK                      (0x300000U)
5985 #define BCH_CTRL_RSVD4_SHIFT                     (20U)
5986 /*! RSVD4 - This field is reserved. */
5987 #define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
5988 
5989 #define BCH_CTRL_DEBUGSYNDROME_MASK              (0x400000U)
5990 #define BCH_CTRL_DEBUGSYNDROME_SHIFT             (22U)
5991 #define BCH_CTRL_DEBUGSYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
5992 
5993 #define BCH_CTRL_RSVD5_MASK                      (0x3F800000U)
5994 #define BCH_CTRL_RSVD5_SHIFT                     (23U)
5995 /*! RSVD5 - This field is reserved. */
5996 #define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
5997 
5998 #define BCH_CTRL_CLKGATE_MASK                    (0x40000000U)
5999 #define BCH_CTRL_CLKGATE_SHIFT                   (30U)
6000 /*! CLKGATE
6001  *  0b0..Allow BCH to operate normally.
6002  *  0b1..Do not clock BCH gates in order to minimize power consumption.
6003  */
6004 #define BCH_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
6005 
6006 #define BCH_CTRL_SFTRST_MASK                     (0x80000000U)
6007 #define BCH_CTRL_SFTRST_SHIFT                    (31U)
6008 /*! SFTRST
6009  *  0b0..Allow BCH to operate normally.
6010  *  0b1..Hold BCH in reset.
6011  */
6012 #define BCH_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
6013 /*! @} */
6014 
6015 /*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
6016 /*! @{ */
6017 
6018 #define BCH_CTRL_SET_COMPLETE_IRQ_MASK           (0x1U)
6019 #define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT          (0U)
6020 #define BCH_CTRL_SET_COMPLETE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
6021 
6022 #define BCH_CTRL_SET_RSVD0_MASK                  (0x2U)
6023 #define BCH_CTRL_SET_RSVD0_SHIFT                 (1U)
6024 /*! RSVD0 - This field is reserved. */
6025 #define BCH_CTRL_SET_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
6026 
6027 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK        (0x4U)
6028 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT       (2U)
6029 #define BCH_CTRL_SET_DEBUG_STALL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
6030 
6031 #define BCH_CTRL_SET_BM_ERROR_IRQ_MASK           (0x8U)
6032 #define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT          (3U)
6033 #define BCH_CTRL_SET_BM_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
6034 
6035 #define BCH_CTRL_SET_RSVD1_MASK                  (0xF0U)
6036 #define BCH_CTRL_SET_RSVD1_SHIFT                 (4U)
6037 /*! RSVD1 - This field is reserved. */
6038 #define BCH_CTRL_SET_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
6039 
6040 #define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK        (0x100U)
6041 #define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT       (8U)
6042 #define BCH_CTRL_SET_COMPLETE_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
6043 
6044 #define BCH_CTRL_SET_RSVD2_MASK                  (0x200U)
6045 #define BCH_CTRL_SET_RSVD2_SHIFT                 (9U)
6046 /*! RSVD2 - This field is reserved. */
6047 #define BCH_CTRL_SET_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
6048 
6049 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK     (0x400U)
6050 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT    (10U)
6051 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
6052 
6053 #define BCH_CTRL_SET_RSVD3_MASK                  (0xF800U)
6054 #define BCH_CTRL_SET_RSVD3_SHIFT                 (11U)
6055 /*! RSVD3 - This field is reserved. */
6056 #define BCH_CTRL_SET_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
6057 
6058 #define BCH_CTRL_SET_M2M_ENABLE_MASK             (0x10000U)
6059 #define BCH_CTRL_SET_M2M_ENABLE_SHIFT            (16U)
6060 #define BCH_CTRL_SET_M2M_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
6061 
6062 #define BCH_CTRL_SET_M2M_ENCODE_MASK             (0x20000U)
6063 #define BCH_CTRL_SET_M2M_ENCODE_SHIFT            (17U)
6064 #define BCH_CTRL_SET_M2M_ENCODE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
6065 
6066 #define BCH_CTRL_SET_M2M_LAYOUT_MASK             (0xC0000U)
6067 #define BCH_CTRL_SET_M2M_LAYOUT_SHIFT            (18U)
6068 #define BCH_CTRL_SET_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
6069 
6070 #define BCH_CTRL_SET_RSVD4_MASK                  (0x300000U)
6071 #define BCH_CTRL_SET_RSVD4_SHIFT                 (20U)
6072 /*! RSVD4 - This field is reserved. */
6073 #define BCH_CTRL_SET_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
6074 
6075 #define BCH_CTRL_SET_DEBUGSYNDROME_MASK          (0x400000U)
6076 #define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT         (22U)
6077 #define BCH_CTRL_SET_DEBUGSYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
6078 
6079 #define BCH_CTRL_SET_RSVD5_MASK                  (0x3F800000U)
6080 #define BCH_CTRL_SET_RSVD5_SHIFT                 (23U)
6081 /*! RSVD5 - This field is reserved. */
6082 #define BCH_CTRL_SET_RSVD5(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
6083 
6084 #define BCH_CTRL_SET_CLKGATE_MASK                (0x40000000U)
6085 #define BCH_CTRL_SET_CLKGATE_SHIFT               (30U)
6086 /*! CLKGATE
6087  *  0b0..Allow BCH to operate normally.
6088  *  0b1..Do not clock BCH gates in order to minimize power consumption.
6089  */
6090 #define BCH_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
6091 
6092 #define BCH_CTRL_SET_SFTRST_MASK                 (0x80000000U)
6093 #define BCH_CTRL_SET_SFTRST_SHIFT                (31U)
6094 /*! SFTRST
6095  *  0b0..Allow BCH to operate normally.
6096  *  0b1..Hold BCH in reset.
6097  */
6098 #define BCH_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
6099 /*! @} */
6100 
6101 /*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
6102 /*! @{ */
6103 
6104 #define BCH_CTRL_CLR_COMPLETE_IRQ_MASK           (0x1U)
6105 #define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT          (0U)
6106 #define BCH_CTRL_CLR_COMPLETE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
6107 
6108 #define BCH_CTRL_CLR_RSVD0_MASK                  (0x2U)
6109 #define BCH_CTRL_CLR_RSVD0_SHIFT                 (1U)
6110 /*! RSVD0 - This field is reserved. */
6111 #define BCH_CTRL_CLR_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
6112 
6113 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK        (0x4U)
6114 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT       (2U)
6115 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
6116 
6117 #define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK           (0x8U)
6118 #define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT          (3U)
6119 #define BCH_CTRL_CLR_BM_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
6120 
6121 #define BCH_CTRL_CLR_RSVD1_MASK                  (0xF0U)
6122 #define BCH_CTRL_CLR_RSVD1_SHIFT                 (4U)
6123 /*! RSVD1 - This field is reserved. */
6124 #define BCH_CTRL_CLR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
6125 
6126 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK        (0x100U)
6127 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT       (8U)
6128 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
6129 
6130 #define BCH_CTRL_CLR_RSVD2_MASK                  (0x200U)
6131 #define BCH_CTRL_CLR_RSVD2_SHIFT                 (9U)
6132 /*! RSVD2 - This field is reserved. */
6133 #define BCH_CTRL_CLR_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
6134 
6135 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK     (0x400U)
6136 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT    (10U)
6137 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
6138 
6139 #define BCH_CTRL_CLR_RSVD3_MASK                  (0xF800U)
6140 #define BCH_CTRL_CLR_RSVD3_SHIFT                 (11U)
6141 /*! RSVD3 - This field is reserved. */
6142 #define BCH_CTRL_CLR_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
6143 
6144 #define BCH_CTRL_CLR_M2M_ENABLE_MASK             (0x10000U)
6145 #define BCH_CTRL_CLR_M2M_ENABLE_SHIFT            (16U)
6146 #define BCH_CTRL_CLR_M2M_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
6147 
6148 #define BCH_CTRL_CLR_M2M_ENCODE_MASK             (0x20000U)
6149 #define BCH_CTRL_CLR_M2M_ENCODE_SHIFT            (17U)
6150 #define BCH_CTRL_CLR_M2M_ENCODE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
6151 
6152 #define BCH_CTRL_CLR_M2M_LAYOUT_MASK             (0xC0000U)
6153 #define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT            (18U)
6154 #define BCH_CTRL_CLR_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
6155 
6156 #define BCH_CTRL_CLR_RSVD4_MASK                  (0x300000U)
6157 #define BCH_CTRL_CLR_RSVD4_SHIFT                 (20U)
6158 /*! RSVD4 - This field is reserved. */
6159 #define BCH_CTRL_CLR_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
6160 
6161 #define BCH_CTRL_CLR_DEBUGSYNDROME_MASK          (0x400000U)
6162 #define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT         (22U)
6163 #define BCH_CTRL_CLR_DEBUGSYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
6164 
6165 #define BCH_CTRL_CLR_RSVD5_MASK                  (0x3F800000U)
6166 #define BCH_CTRL_CLR_RSVD5_SHIFT                 (23U)
6167 /*! RSVD5 - This field is reserved. */
6168 #define BCH_CTRL_CLR_RSVD5(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
6169 
6170 #define BCH_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
6171 #define BCH_CTRL_CLR_CLKGATE_SHIFT               (30U)
6172 /*! CLKGATE
6173  *  0b0..Allow BCH to operate normally.
6174  *  0b1..Do not clock BCH gates in order to minimize power consumption.
6175  */
6176 #define BCH_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
6177 
6178 #define BCH_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
6179 #define BCH_CTRL_CLR_SFTRST_SHIFT                (31U)
6180 /*! SFTRST
6181  *  0b0..Allow BCH to operate normally.
6182  *  0b1..Hold BCH in reset.
6183  */
6184 #define BCH_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
6185 /*! @} */
6186 
6187 /*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
6188 /*! @{ */
6189 
6190 #define BCH_CTRL_TOG_COMPLETE_IRQ_MASK           (0x1U)
6191 #define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT          (0U)
6192 #define BCH_CTRL_TOG_COMPLETE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
6193 
6194 #define BCH_CTRL_TOG_RSVD0_MASK                  (0x2U)
6195 #define BCH_CTRL_TOG_RSVD0_SHIFT                 (1U)
6196 /*! RSVD0 - This field is reserved. */
6197 #define BCH_CTRL_TOG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
6198 
6199 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK        (0x4U)
6200 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT       (2U)
6201 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
6202 
6203 #define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK           (0x8U)
6204 #define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT          (3U)
6205 #define BCH_CTRL_TOG_BM_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
6206 
6207 #define BCH_CTRL_TOG_RSVD1_MASK                  (0xF0U)
6208 #define BCH_CTRL_TOG_RSVD1_SHIFT                 (4U)
6209 /*! RSVD1 - This field is reserved. */
6210 #define BCH_CTRL_TOG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
6211 
6212 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK        (0x100U)
6213 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT       (8U)
6214 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
6215 
6216 #define BCH_CTRL_TOG_RSVD2_MASK                  (0x200U)
6217 #define BCH_CTRL_TOG_RSVD2_SHIFT                 (9U)
6218 /*! RSVD2 - This field is reserved. */
6219 #define BCH_CTRL_TOG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
6220 
6221 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK     (0x400U)
6222 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT    (10U)
6223 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
6224 
6225 #define BCH_CTRL_TOG_RSVD3_MASK                  (0xF800U)
6226 #define BCH_CTRL_TOG_RSVD3_SHIFT                 (11U)
6227 /*! RSVD3 - This field is reserved. */
6228 #define BCH_CTRL_TOG_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
6229 
6230 #define BCH_CTRL_TOG_M2M_ENABLE_MASK             (0x10000U)
6231 #define BCH_CTRL_TOG_M2M_ENABLE_SHIFT            (16U)
6232 #define BCH_CTRL_TOG_M2M_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
6233 
6234 #define BCH_CTRL_TOG_M2M_ENCODE_MASK             (0x20000U)
6235 #define BCH_CTRL_TOG_M2M_ENCODE_SHIFT            (17U)
6236 #define BCH_CTRL_TOG_M2M_ENCODE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
6237 
6238 #define BCH_CTRL_TOG_M2M_LAYOUT_MASK             (0xC0000U)
6239 #define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT            (18U)
6240 #define BCH_CTRL_TOG_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
6241 
6242 #define BCH_CTRL_TOG_RSVD4_MASK                  (0x300000U)
6243 #define BCH_CTRL_TOG_RSVD4_SHIFT                 (20U)
6244 /*! RSVD4 - This field is reserved. */
6245 #define BCH_CTRL_TOG_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
6246 
6247 #define BCH_CTRL_TOG_DEBUGSYNDROME_MASK          (0x400000U)
6248 #define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT         (22U)
6249 #define BCH_CTRL_TOG_DEBUGSYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
6250 
6251 #define BCH_CTRL_TOG_RSVD5_MASK                  (0x3F800000U)
6252 #define BCH_CTRL_TOG_RSVD5_SHIFT                 (23U)
6253 /*! RSVD5 - This field is reserved. */
6254 #define BCH_CTRL_TOG_RSVD5(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
6255 
6256 #define BCH_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
6257 #define BCH_CTRL_TOG_CLKGATE_SHIFT               (30U)
6258 /*! CLKGATE
6259  *  0b0..Allow BCH to operate normally.
6260  *  0b1..Do not clock BCH gates in order to minimize power consumption.
6261  */
6262 #define BCH_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
6263 
6264 #define BCH_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
6265 #define BCH_CTRL_TOG_SFTRST_SHIFT                (31U)
6266 /*! SFTRST
6267  *  0b0..Allow BCH to operate normally.
6268  *  0b1..Hold BCH in reset.
6269  */
6270 #define BCH_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
6271 /*! @} */
6272 
6273 /*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
6274 /*! @{ */
6275 
6276 #define BCH_STATUS0_RSVD0_MASK                   (0x3U)
6277 #define BCH_STATUS0_RSVD0_SHIFT                  (0U)
6278 /*! RSVD0 - This field is reserved. */
6279 #define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
6280 
6281 #define BCH_STATUS0_UNCORRECTABLE_MASK           (0x4U)
6282 #define BCH_STATUS0_UNCORRECTABLE_SHIFT          (2U)
6283 #define BCH_STATUS0_UNCORRECTABLE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
6284 
6285 #define BCH_STATUS0_CORRECTED_MASK               (0x8U)
6286 #define BCH_STATUS0_CORRECTED_SHIFT              (3U)
6287 #define BCH_STATUS0_CORRECTED(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
6288 
6289 #define BCH_STATUS0_ALLONES_MASK                 (0x10U)
6290 #define BCH_STATUS0_ALLONES_SHIFT                (4U)
6291 #define BCH_STATUS0_ALLONES(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
6292 
6293 #define BCH_STATUS0_RSVD1_MASK                   (0xE0U)
6294 #define BCH_STATUS0_RSVD1_SHIFT                  (5U)
6295 /*! RSVD1 - This field is reserved. */
6296 #define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
6297 
6298 #define BCH_STATUS0_STATUS_BLK0_MASK             (0xFF00U)
6299 #define BCH_STATUS0_STATUS_BLK0_SHIFT            (8U)
6300 /*! STATUS_BLK0
6301  *  0b00000000..No errors found on block.
6302  *  0b00000001..One error found on block.
6303  *  0b00000010..One errors found on block.
6304  *  0b00000011..One errors found on block.
6305  *  0b00000100..One errors found on block.
6306  *  0b11111110..Block exhibited uncorrectable errors.
6307  *  0b11111111..Page is erased.
6308  */
6309 #define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
6310 
6311 #define BCH_STATUS0_COMPLETED_CE_MASK            (0xF0000U)
6312 #define BCH_STATUS0_COMPLETED_CE_SHIFT           (16U)
6313 #define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
6314 
6315 #define BCH_STATUS0_HANDLE_MASK                  (0xFFF00000U)
6316 #define BCH_STATUS0_HANDLE_SHIFT                 (20U)
6317 #define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
6318 /*! @} */
6319 
6320 /*! @name MODE - Hardware ECC Accelerator Mode Register */
6321 /*! @{ */
6322 
6323 #define BCH_MODE_ERASE_THRESHOLD_MASK            (0xFFU)
6324 #define BCH_MODE_ERASE_THRESHOLD_SHIFT           (0U)
6325 #define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
6326 
6327 #define BCH_MODE_RSVD_MASK                       (0xFFFFFF00U)
6328 #define BCH_MODE_RSVD_SHIFT                      (8U)
6329 /*! RSVD - This field is reserved. */
6330 #define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
6331 /*! @} */
6332 
6333 /*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
6334 /*! @{ */
6335 
6336 #define BCH_ENCODEPTR_ADDR_MASK                  (0xFFFFFFFFU)
6337 #define BCH_ENCODEPTR_ADDR_SHIFT                 (0U)
6338 #define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
6339 /*! @} */
6340 
6341 /*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
6342 /*! @{ */
6343 
6344 #define BCH_DATAPTR_ADDR_MASK                    (0xFFFFFFFFU)
6345 #define BCH_DATAPTR_ADDR_SHIFT                   (0U)
6346 #define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
6347 /*! @} */
6348 
6349 /*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
6350 /*! @{ */
6351 
6352 #define BCH_METAPTR_ADDR_MASK                    (0xFFFFFFFFU)
6353 #define BCH_METAPTR_ADDR_SHIFT                   (0U)
6354 #define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
6355 /*! @} */
6356 
6357 /*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
6358 /*! @{ */
6359 
6360 #define BCH_LAYOUTSELECT_CS0_SELECT_MASK         (0x3U)
6361 #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        (0U)
6362 #define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
6363 
6364 #define BCH_LAYOUTSELECT_CS1_SELECT_MASK         (0xCU)
6365 #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        (2U)
6366 #define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
6367 
6368 #define BCH_LAYOUTSELECT_CS2_SELECT_MASK         (0x30U)
6369 #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        (4U)
6370 #define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
6371 
6372 #define BCH_LAYOUTSELECT_CS3_SELECT_MASK         (0xC0U)
6373 #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        (6U)
6374 #define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
6375 
6376 #define BCH_LAYOUTSELECT_CS4_SELECT_MASK         (0x300U)
6377 #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        (8U)
6378 #define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
6379 
6380 #define BCH_LAYOUTSELECT_CS5_SELECT_MASK         (0xC00U)
6381 #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        (10U)
6382 #define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
6383 
6384 #define BCH_LAYOUTSELECT_CS6_SELECT_MASK         (0x3000U)
6385 #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        (12U)
6386 #define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
6387 
6388 #define BCH_LAYOUTSELECT_CS7_SELECT_MASK         (0xC000U)
6389 #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        (14U)
6390 #define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
6391 
6392 #define BCH_LAYOUTSELECT_CS8_SELECT_MASK         (0x30000U)
6393 #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        (16U)
6394 #define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
6395 
6396 #define BCH_LAYOUTSELECT_CS9_SELECT_MASK         (0xC0000U)
6397 #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        (18U)
6398 #define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
6399 
6400 #define BCH_LAYOUTSELECT_CS10_SELECT_MASK        (0x300000U)
6401 #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       (20U)
6402 #define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
6403 
6404 #define BCH_LAYOUTSELECT_CS11_SELECT_MASK        (0xC00000U)
6405 #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       (22U)
6406 #define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
6407 
6408 #define BCH_LAYOUTSELECT_CS12_SELECT_MASK        (0x3000000U)
6409 #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       (24U)
6410 #define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
6411 
6412 #define BCH_LAYOUTSELECT_CS13_SELECT_MASK        (0xC000000U)
6413 #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       (26U)
6414 #define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
6415 
6416 #define BCH_LAYOUTSELECT_CS14_SELECT_MASK        (0x30000000U)
6417 #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       (28U)
6418 #define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
6419 
6420 #define BCH_LAYOUTSELECT_CS15_SELECT_MASK        (0xC0000000U)
6421 #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       (30U)
6422 #define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
6423 /*! @} */
6424 
6425 /*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
6426 /*! @{ */
6427 
6428 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
6429 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       (0U)
6430 #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
6431 
6432 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
6433 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
6434 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
6435 
6436 #define BCH_FLASH0LAYOUT0_ECC0_MASK              (0xF800U)
6437 #define BCH_FLASH0LAYOUT0_ECC0_SHIFT             (11U)
6438 /*! ECC0
6439  *  0b00000..No ECC to be performed
6440  *  0b00001..ECC 2 to be performed
6441  *  0b00010..ECC 4 to be performed
6442  *  0b11110..ECC 60 to be performed
6443  *  0b11111..ECC 62 to be performed
6444  */
6445 #define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
6446 
6447 #define BCH_FLASH0LAYOUT0_META_SIZE_MASK         (0xFF0000U)
6448 #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        (16U)
6449 #define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
6450 
6451 #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
6452 #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          (24U)
6453 #define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
6454 /*! @} */
6455 
6456 /*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
6457 /*! @{ */
6458 
6459 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
6460 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       (0U)
6461 #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
6462 
6463 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
6464 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
6465 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
6466 
6467 #define BCH_FLASH0LAYOUT1_ECCN_MASK              (0xF800U)
6468 #define BCH_FLASH0LAYOUT1_ECCN_SHIFT             (11U)
6469 /*! ECCN
6470  *  0b00000..No ECC to be performed
6471  *  0b00001..ECC 2 to be performed
6472  *  0b00010..ECC 4 to be performed
6473  *  0b11110..ECC 60 to be performed
6474  *  0b11111..ECC 62 to be performed
6475  */
6476 #define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
6477 
6478 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
6479 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        (16U)
6480 #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
6481 /*! @} */
6482 
6483 /*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
6484 /*! @{ */
6485 
6486 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
6487 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       (0U)
6488 #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
6489 
6490 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
6491 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
6492 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
6493 
6494 #define BCH_FLASH1LAYOUT0_ECC0_MASK              (0xF800U)
6495 #define BCH_FLASH1LAYOUT0_ECC0_SHIFT             (11U)
6496 /*! ECC0
6497  *  0b00000..No ECC to be performed
6498  *  0b00001..ECC 2 to be performed
6499  *  0b00010..ECC 4 to be performed
6500  *  0b11110..ECC 60 to be performed
6501  *  0b11111..ECC 62 to be performed
6502  */
6503 #define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
6504 
6505 #define BCH_FLASH1LAYOUT0_META_SIZE_MASK         (0xFF0000U)
6506 #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        (16U)
6507 #define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
6508 
6509 #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
6510 #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          (24U)
6511 #define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
6512 /*! @} */
6513 
6514 /*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
6515 /*! @{ */
6516 
6517 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
6518 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       (0U)
6519 #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
6520 
6521 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
6522 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
6523 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
6524 
6525 #define BCH_FLASH1LAYOUT1_ECCN_MASK              (0xF800U)
6526 #define BCH_FLASH1LAYOUT1_ECCN_SHIFT             (11U)
6527 /*! ECCN
6528  *  0b00000..No ECC to be performed
6529  *  0b00001..ECC 2 to be performed
6530  *  0b00010..ECC 4 to be performed
6531  *  0b11110..ECC 60 to be performed
6532  *  0b11111..ECC 62 to be performed
6533  */
6534 #define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
6535 
6536 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
6537 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        (16U)
6538 #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
6539 /*! @} */
6540 
6541 /*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
6542 /*! @{ */
6543 
6544 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
6545 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       (0U)
6546 #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
6547 
6548 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
6549 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
6550 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
6551 
6552 #define BCH_FLASH2LAYOUT0_ECC0_MASK              (0xF800U)
6553 #define BCH_FLASH2LAYOUT0_ECC0_SHIFT             (11U)
6554 /*! ECC0
6555  *  0b00000..No ECC to be performed
6556  *  0b00001..ECC 2 to be performed
6557  *  0b00010..ECC 4 to be performed
6558  *  0b11110..ECC 60 to be performed
6559  *  0b11111..ECC 62 to be performed
6560  */
6561 #define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
6562 
6563 #define BCH_FLASH2LAYOUT0_META_SIZE_MASK         (0xFF0000U)
6564 #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        (16U)
6565 #define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
6566 
6567 #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
6568 #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          (24U)
6569 #define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
6570 /*! @} */
6571 
6572 /*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
6573 /*! @{ */
6574 
6575 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
6576 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       (0U)
6577 #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
6578 
6579 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
6580 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
6581 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
6582 
6583 #define BCH_FLASH2LAYOUT1_ECCN_MASK              (0xF800U)
6584 #define BCH_FLASH2LAYOUT1_ECCN_SHIFT             (11U)
6585 /*! ECCN
6586  *  0b00000..No ECC to be performed
6587  *  0b00001..ECC 2 to be performed
6588  *  0b00010..ECC 4 to be performed
6589  *  0b11110..ECC 60 to be performed
6590  *  0b11111..ECC 62 to be performed
6591  */
6592 #define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
6593 
6594 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
6595 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        (16U)
6596 #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
6597 /*! @} */
6598 
6599 /*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
6600 /*! @{ */
6601 
6602 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
6603 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       (0U)
6604 #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
6605 
6606 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
6607 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
6608 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
6609 
6610 #define BCH_FLASH3LAYOUT0_ECC0_MASK              (0xF800U)
6611 #define BCH_FLASH3LAYOUT0_ECC0_SHIFT             (11U)
6612 /*! ECC0
6613  *  0b00000..No ECC to be performed
6614  *  0b00001..ECC 2 to be performed
6615  *  0b00010..ECC 4 to be performed
6616  *  0b11110..ECC 60 to be performed
6617  *  0b11111..ECC 62 to be performed
6618  */
6619 #define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
6620 
6621 #define BCH_FLASH3LAYOUT0_META_SIZE_MASK         (0xFF0000U)
6622 #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        (16U)
6623 #define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
6624 
6625 #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
6626 #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          (24U)
6627 #define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
6628 /*! @} */
6629 
6630 /*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
6631 /*! @{ */
6632 
6633 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
6634 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       (0U)
6635 #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
6636 
6637 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
6638 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
6639 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
6640 
6641 #define BCH_FLASH3LAYOUT1_ECCN_MASK              (0xF800U)
6642 #define BCH_FLASH3LAYOUT1_ECCN_SHIFT             (11U)
6643 /*! ECCN
6644  *  0b00000..No ECC to be performed
6645  *  0b00001..ECC 2 to be performed
6646  *  0b00010..ECC 4 to be performed
6647  *  0b11110..ECC 60 to be performed
6648  *  0b11111..ECC 62 to be performed
6649  */
6650 #define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
6651 
6652 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
6653 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        (16U)
6654 #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
6655 /*! @} */
6656 
6657 /*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
6658 /*! @{ */
6659 
6660 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         (0x3FU)
6661 #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        (0U)
6662 #define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
6663 
6664 #define BCH_DEBUG0_RSVD0_MASK                    (0xC0U)
6665 #define BCH_DEBUG0_RSVD0_SHIFT                   (6U)
6666 /*! RSVD0 - This field is reserved. */
6667 #define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
6668 
6669 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       (0x100U)
6670 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      (8U)
6671 /*! BM_KES_TEST_BYPASS
6672  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6673  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6674  */
6675 #define BCH_DEBUG0_BM_KES_TEST_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
6676 
6677 #define BCH_DEBUG0_KES_DEBUG_STALL_MASK          (0x200U)
6678 #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         (9U)
6679 /*! KES_DEBUG_STALL
6680  *  0b0..KES FSM proceeds to next block supplied by bus master.
6681  *  0b1..KES FSM waits after current equations are solved and the search engine is started.
6682  */
6683 #define BCH_DEBUG0_KES_DEBUG_STALL(x)            (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
6684 
6685 #define BCH_DEBUG0_KES_DEBUG_STEP_MASK           (0x400U)
6686 #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          (10U)
6687 #define BCH_DEBUG0_KES_DEBUG_STEP(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
6688 
6689 #define BCH_DEBUG0_KES_STANDALONE_MASK           (0x800U)
6690 #define BCH_DEBUG0_KES_STANDALONE_SHIFT          (11U)
6691 /*! KES_STANDALONE
6692  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6693  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6694  */
6695 #define BCH_DEBUG0_KES_STANDALONE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
6696 
6697 #define BCH_DEBUG0_KES_DEBUG_KICK_MASK           (0x1000U)
6698 #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          (12U)
6699 #define BCH_DEBUG0_KES_DEBUG_KICK(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
6700 
6701 #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         (0x2000U)
6702 #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        (13U)
6703 /*! KES_DEBUG_MODE4K
6704  *  0b1..Mode is set for 4K NAND pages.
6705  *  0b1..Mode is set for 2K NAND pages.
6706  */
6707 #define BCH_DEBUG0_KES_DEBUG_MODE4K(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
6708 
6709 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   (0x4000U)
6710 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  (14U)
6711 /*! KES_DEBUG_PAYLOAD_FLAG
6712  *  0b1..Payload is set for 512 bytes data block.
6713  *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
6714  */
6715 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
6716 
6717 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     (0x8000U)
6718 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    (15U)
6719 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
6720 
6721 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
6722 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
6723 /*! KES_DEBUG_SYNDROME_SYMBOL
6724  *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
6725  *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
6726  */
6727 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
6728 
6729 #define BCH_DEBUG0_RSVD1_MASK                    (0xFE000000U)
6730 #define BCH_DEBUG0_RSVD1_SHIFT                   (25U)
6731 /*! RSVD1 - This field is reserved. */
6732 #define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
6733 /*! @} */
6734 
6735 /*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
6736 /*! @{ */
6737 
6738 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK     (0x3FU)
6739 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT    (0U)
6740 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
6741 
6742 #define BCH_DEBUG0_SET_RSVD0_MASK                (0xC0U)
6743 #define BCH_DEBUG0_SET_RSVD0_SHIFT               (6U)
6744 /*! RSVD0 - This field is reserved. */
6745 #define BCH_DEBUG0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
6746 
6747 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK   (0x100U)
6748 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT  (8U)
6749 /*! BM_KES_TEST_BYPASS
6750  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6751  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6752  */
6753 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
6754 
6755 #define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK      (0x200U)
6756 #define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT     (9U)
6757 /*! KES_DEBUG_STALL
6758  *  0b0..KES FSM proceeds to next block supplied by bus master.
6759  *  0b1..KES FSM waits after current equations are solved and the search engine is started.
6760  */
6761 #define BCH_DEBUG0_SET_KES_DEBUG_STALL(x)        (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
6762 
6763 #define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK       (0x400U)
6764 #define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT      (10U)
6765 #define BCH_DEBUG0_SET_KES_DEBUG_STEP(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
6766 
6767 #define BCH_DEBUG0_SET_KES_STANDALONE_MASK       (0x800U)
6768 #define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT      (11U)
6769 /*! KES_STANDALONE
6770  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6771  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6772  */
6773 #define BCH_DEBUG0_SET_KES_STANDALONE(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
6774 
6775 #define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK       (0x1000U)
6776 #define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT      (12U)
6777 #define BCH_DEBUG0_SET_KES_DEBUG_KICK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
6778 
6779 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK     (0x2000U)
6780 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT    (13U)
6781 /*! KES_DEBUG_MODE4K
6782  *  0b1..Mode is set for 4K NAND pages.
6783  *  0b1..Mode is set for 2K NAND pages.
6784  */
6785 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
6786 
6787 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
6788 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
6789 /*! KES_DEBUG_PAYLOAD_FLAG
6790  *  0b1..Payload is set for 512 bytes data block.
6791  *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
6792  */
6793 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
6794 
6795 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
6796 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
6797 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x)   (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
6798 
6799 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
6800 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
6801 /*! KES_DEBUG_SYNDROME_SYMBOL
6802  *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
6803  *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
6804  */
6805 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
6806 
6807 #define BCH_DEBUG0_SET_RSVD1_MASK                (0xFE000000U)
6808 #define BCH_DEBUG0_SET_RSVD1_SHIFT               (25U)
6809 /*! RSVD1 - This field is reserved. */
6810 #define BCH_DEBUG0_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
6811 /*! @} */
6812 
6813 /*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
6814 /*! @{ */
6815 
6816 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK     (0x3FU)
6817 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT    (0U)
6818 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
6819 
6820 #define BCH_DEBUG0_CLR_RSVD0_MASK                (0xC0U)
6821 #define BCH_DEBUG0_CLR_RSVD0_SHIFT               (6U)
6822 /*! RSVD0 - This field is reserved. */
6823 #define BCH_DEBUG0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
6824 
6825 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK   (0x100U)
6826 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT  (8U)
6827 /*! BM_KES_TEST_BYPASS
6828  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6829  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6830  */
6831 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
6832 
6833 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK      (0x200U)
6834 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT     (9U)
6835 /*! KES_DEBUG_STALL
6836  *  0b0..KES FSM proceeds to next block supplied by bus master.
6837  *  0b1..KES FSM waits after current equations are solved and the search engine is started.
6838  */
6839 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x)        (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
6840 
6841 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK       (0x400U)
6842 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT      (10U)
6843 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
6844 
6845 #define BCH_DEBUG0_CLR_KES_STANDALONE_MASK       (0x800U)
6846 #define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT      (11U)
6847 /*! KES_STANDALONE
6848  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6849  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6850  */
6851 #define BCH_DEBUG0_CLR_KES_STANDALONE(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
6852 
6853 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK       (0x1000U)
6854 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT      (12U)
6855 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
6856 
6857 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK     (0x2000U)
6858 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT    (13U)
6859 /*! KES_DEBUG_MODE4K
6860  *  0b1..Mode is set for 4K NAND pages.
6861  *  0b1..Mode is set for 2K NAND pages.
6862  */
6863 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
6864 
6865 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
6866 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
6867 /*! KES_DEBUG_PAYLOAD_FLAG
6868  *  0b1..Payload is set for 512 bytes data block.
6869  *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
6870  */
6871 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
6872 
6873 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
6874 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
6875 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x)   (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
6876 
6877 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
6878 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
6879 /*! KES_DEBUG_SYNDROME_SYMBOL
6880  *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
6881  *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
6882  */
6883 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
6884 
6885 #define BCH_DEBUG0_CLR_RSVD1_MASK                (0xFE000000U)
6886 #define BCH_DEBUG0_CLR_RSVD1_SHIFT               (25U)
6887 /*! RSVD1 - This field is reserved. */
6888 #define BCH_DEBUG0_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
6889 /*! @} */
6890 
6891 /*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
6892 /*! @{ */
6893 
6894 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK     (0x3FU)
6895 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT    (0U)
6896 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
6897 
6898 #define BCH_DEBUG0_TOG_RSVD0_MASK                (0xC0U)
6899 #define BCH_DEBUG0_TOG_RSVD0_SHIFT               (6U)
6900 /*! RSVD0 - This field is reserved. */
6901 #define BCH_DEBUG0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
6902 
6903 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK   (0x100U)
6904 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT  (8U)
6905 /*! BM_KES_TEST_BYPASS
6906  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6907  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6908  */
6909 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
6910 
6911 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK      (0x200U)
6912 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT     (9U)
6913 /*! KES_DEBUG_STALL
6914  *  0b0..KES FSM proceeds to next block supplied by bus master.
6915  *  0b1..KES FSM waits after current equations are solved and the search engine is started.
6916  */
6917 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x)        (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
6918 
6919 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK       (0x400U)
6920 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT      (10U)
6921 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
6922 
6923 #define BCH_DEBUG0_TOG_KES_STANDALONE_MASK       (0x800U)
6924 #define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT      (11U)
6925 /*! KES_STANDALONE
6926  *  0b0..Bus master address generator for SYND_GEN writes operates normally.
6927  *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6928  */
6929 #define BCH_DEBUG0_TOG_KES_STANDALONE(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
6930 
6931 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK       (0x1000U)
6932 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT      (12U)
6933 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
6934 
6935 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK     (0x2000U)
6936 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT    (13U)
6937 /*! KES_DEBUG_MODE4K
6938  *  0b1..Mode is set for 4K NAND pages.
6939  *  0b1..Mode is set for 2K NAND pages.
6940  */
6941 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
6942 
6943 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
6944 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
6945 /*! KES_DEBUG_PAYLOAD_FLAG
6946  *  0b1..Payload is set for 512 bytes data block.
6947  *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
6948  */
6949 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
6950 
6951 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
6952 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
6953 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x)   (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
6954 
6955 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
6956 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
6957 /*! KES_DEBUG_SYNDROME_SYMBOL
6958  *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
6959  *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
6960  */
6961 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
6962 
6963 #define BCH_DEBUG0_TOG_RSVD1_MASK                (0xFE000000U)
6964 #define BCH_DEBUG0_TOG_RSVD1_SHIFT               (25U)
6965 /*! RSVD1 - This field is reserved. */
6966 #define BCH_DEBUG0_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
6967 /*! @} */
6968 
6969 /*! @name DBGKESREAD - KES Debug Read Register */
6970 /*! @{ */
6971 
6972 #define BCH_DBGKESREAD_VALUES_MASK               (0xFFFFFFFFU)
6973 #define BCH_DBGKESREAD_VALUES_SHIFT              (0U)
6974 #define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
6975 /*! @} */
6976 
6977 /*! @name DBGCSFEREAD - Chien Search Debug Read Register */
6978 /*! @{ */
6979 
6980 #define BCH_DBGCSFEREAD_VALUES_MASK              (0xFFFFFFFFU)
6981 #define BCH_DBGCSFEREAD_VALUES_SHIFT             (0U)
6982 #define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
6983 /*! @} */
6984 
6985 /*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
6986 /*! @{ */
6987 
6988 #define BCH_DBGSYNDGENREAD_VALUES_MASK           (0xFFFFFFFFU)
6989 #define BCH_DBGSYNDGENREAD_VALUES_SHIFT          (0U)
6990 #define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
6991 /*! @} */
6992 
6993 /*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
6994 /*! @{ */
6995 
6996 #define BCH_DBGAHBMREAD_VALUES_MASK              (0xFFFFFFFFU)
6997 #define BCH_DBGAHBMREAD_VALUES_SHIFT             (0U)
6998 #define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
6999 /*! @} */
7000 
7001 /*! @name BLOCKNAME - Block Name Register */
7002 /*! @{ */
7003 
7004 #define BCH_BLOCKNAME_NAME_MASK                  (0xFFFFFFFFU)
7005 #define BCH_BLOCKNAME_NAME_SHIFT                 (0U)
7006 #define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
7007 /*! @} */
7008 
7009 /*! @name VERSION - BCH Version Register */
7010 /*! @{ */
7011 
7012 #define BCH_VERSION_STEP_MASK                    (0xFFFFU)
7013 #define BCH_VERSION_STEP_SHIFT                   (0U)
7014 #define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
7015 
7016 #define BCH_VERSION_MINOR_MASK                   (0xFF0000U)
7017 #define BCH_VERSION_MINOR_SHIFT                  (16U)
7018 #define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
7019 
7020 #define BCH_VERSION_MAJOR_MASK                   (0xFF000000U)
7021 #define BCH_VERSION_MAJOR_SHIFT                  (24U)
7022 #define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
7023 /*! @} */
7024 
7025 /*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
7026 /*! @{ */
7027 
7028 #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        (0x1FFU)
7029 #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       (0U)
7030 #define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
7031 
7032 #define BCH_DEBUG1_RSVD_MASK                     (0x7FFFFE00U)
7033 #define BCH_DEBUG1_RSVD_SHIFT                    (9U)
7034 /*! RSVD - This field is reserved. */
7035 #define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
7036 
7037 #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       (0x80000000U)
7038 #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      (31U)
7039 /*! DEBUG1_PREERASECHK
7040  *  0b0..Turn off pre-erase check
7041  *  0b1..Turn on pre-erase check
7042  */
7043 #define BCH_DEBUG1_DEBUG1_PREERASECHK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
7044 /*! @} */
7045 
7046 
7047 /*!
7048  * @}
7049  */ /* end of group BCH_Register_Masks */
7050 
7051 
7052 /* BCH - Peripheral instance base addresses */
7053 /** Peripheral BCH base address */
7054 #define BCH_BASE                                 (0x33004000u)
7055 /** Peripheral BCH base pointer */
7056 #define BCH                                      ((BCH_Type *)BCH_BASE)
7057 /** Array initializer of BCH peripheral base addresses */
7058 #define BCH_BASE_ADDRS                           { BCH_BASE }
7059 /** Array initializer of BCH peripheral base pointers */
7060 #define BCH_BASE_PTRS                            { BCH }
7061 /** Interrupt vectors for the BCH peripheral type */
7062 #define BCH_IRQS                                 { BCH_IRQn }
7063 
7064 /*!
7065  * @}
7066  */ /* end of group BCH_Peripheral_Access_Layer */
7067 
7068 
7069 /* ----------------------------------------------------------------------------
7070    -- CAN Peripheral Access Layer
7071    ---------------------------------------------------------------------------- */
7072 
7073 /*!
7074  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
7075  * @{
7076  */
7077 
7078 /** CAN - Register Layout Typedef */
7079 typedef struct {
7080   __IO uint32_t MCR;                               /**< Module Configuration register, offset: 0x0 */
7081   __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
7082   __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
7083        uint8_t RESERVED_0[4];
7084   __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask register, offset: 0x10 */
7085   __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
7086   __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
7087   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
7088   __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
7089   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
7090   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
7091   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
7092   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
7093   __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
7094   __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
7095        uint8_t RESERVED_1[8];
7096   __I  uint32_t CRCR;                              /**< CRC register, offset: 0x44 */
7097   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
7098   __I  uint32_t RXFIR;                             /**< Rx FIFO Information register, offset: 0x4C */
7099   __IO uint32_t CBT;                               /**< CAN Bit Timing register, offset: 0x50 */
7100        uint8_t RESERVED_2[44];
7101   struct {                                         /* offset: 0x80, array step: 0x10 */
7102     __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
7103     __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
7104     __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
7105     __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
7106   } MB[64];
7107        uint8_t RESERVED_3[1024];
7108   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
7109        uint8_t RESERVED_4[352];
7110   __IO uint32_t MECR;                              /**< Memory Error Control register, offset: 0xAE0 */
7111   __IO uint32_t ERRIAR;                            /**< Error Injection Address register, offset: 0xAE4 */
7112   __IO uint32_t ERRIDPR;                           /**< Error Injection Data Pattern register, offset: 0xAE8 */
7113   __IO uint32_t ERRIPPR;                           /**< Error Injection Parity Pattern register, offset: 0xAEC */
7114   __I  uint32_t RERRAR;                            /**< Error Report Address register, offset: 0xAF0 */
7115   __I  uint32_t RERRDR;                            /**< Error Report Data register, offset: 0xAF4 */
7116   __I  uint32_t RERRSYNR;                          /**< Error Report Syndrome register, offset: 0xAF8 */
7117   __IO uint32_t ERRSR;                             /**< Error Status register, offset: 0xAFC */
7118        uint8_t RESERVED_5[256];
7119   __IO uint32_t FDCTRL;                            /**< CAN FD Control register, offset: 0xC00 */
7120   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing register, offset: 0xC04 */
7121   __I  uint32_t FDCRC;                             /**< CAN FD CRC register, offset: 0xC08 */
7122 } CAN_Type;
7123 
7124 /* ----------------------------------------------------------------------------
7125    -- CAN Register Masks
7126    ---------------------------------------------------------------------------- */
7127 
7128 /*!
7129  * @addtogroup CAN_Register_Masks CAN Register Masks
7130  * @{
7131  */
7132 
7133 /*! @name MCR - Module Configuration register */
7134 /*! @{ */
7135 
7136 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
7137 #define CAN_MCR_MAXMB_SHIFT                      (0U)
7138 /*! MAXMB - Number Of The Last Message Buffer */
7139 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
7140 
7141 #define CAN_MCR_IDAM_MASK                        (0x300U)
7142 #define CAN_MCR_IDAM_SHIFT                       (8U)
7143 /*! IDAM - ID Acceptance Mode
7144  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
7145  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
7146  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
7147  *  0b11..Format D: All frames rejected.
7148  */
7149 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
7150 
7151 #define CAN_MCR_FDEN_MASK                        (0x800U)
7152 #define CAN_MCR_FDEN_SHIFT                       (11U)
7153 /*! FDEN - CAN FD operation enable
7154  *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
7155  *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
7156  */
7157 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
7158 
7159 #define CAN_MCR_AEN_MASK                         (0x1000U)
7160 #define CAN_MCR_AEN_SHIFT                        (12U)
7161 /*! AEN - Abort Enable
7162  *  0b0..Abort disabled.
7163  *  0b1..Abort enabled.
7164  */
7165 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
7166 
7167 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
7168 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
7169 /*! LPRIOEN - Local Priority Enable
7170  *  0b0..Local Priority disabled.
7171  *  0b1..Local Priority enabled.
7172  */
7173 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
7174 
7175 #define CAN_MCR_DMA_MASK                         (0x8000U)
7176 #define CAN_MCR_DMA_SHIFT                        (15U)
7177 /*! DMA - DMA Enable
7178  *  0b0..DMA feature for RX FIFO disabled.
7179  *  0b1..DMA feature for RX FIFO enabled.
7180  */
7181 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
7182 
7183 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
7184 #define CAN_MCR_IRMQ_SHIFT                       (16U)
7185 /*! IRMQ - Individual Rx Masking And Queue Enable
7186  *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
7187  *       applications, the reading of C/S word locks the MB even if it is EMPTY.
7188  *  0b1..Individual Rx masking and queue feature are enabled.
7189  */
7190 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
7191 
7192 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
7193 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
7194 /*! SRXDIS - Self Reception Disable
7195  *  0b0..Self-reception enabled.
7196  *  0b1..Self-reception disabled.
7197  */
7198 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
7199 
7200 #define CAN_MCR_DOZE_MASK                        (0x40000U)
7201 #define CAN_MCR_DOZE_SHIFT                       (18U)
7202 /*! DOZE - Doze Mode Enable
7203  *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
7204  *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
7205  */
7206 #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
7207 
7208 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
7209 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
7210 /*! WAKSRC - Wake Up Source
7211  *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
7212  *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
7213  */
7214 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
7215 
7216 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
7217 #define CAN_MCR_LPMACK_SHIFT                     (20U)
7218 /*! LPMACK - Low-Power Mode Acknowledge
7219  *  0b0..FlexCAN is not in a low-power mode.
7220  *  0b1..FlexCAN is in a low-power mode.
7221  */
7222 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
7223 
7224 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
7225 #define CAN_MCR_WRNEN_SHIFT                      (21U)
7226 /*! WRNEN - Warning Interrupt Enable
7227  *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
7228  *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
7229  */
7230 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
7231 
7232 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
7233 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
7234 /*! SLFWAK - Self Wake Up
7235  *  0b0..FlexCAN Self Wake Up feature is disabled.
7236  *  0b1..FlexCAN Self Wake Up feature is enabled.
7237  */
7238 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
7239 
7240 #define CAN_MCR_SUPV_MASK                        (0x800000U)
7241 #define CAN_MCR_SUPV_SHIFT                       (23U)
7242 /*! SUPV - Supervisor Mode
7243  *  0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses (ips_supervisor_access signal is ignored).
7244  *  0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
7245  *       (ips_supervisor_access negated) behaves as though the access was done to an unimplemented register location
7246  *       (ips_xfr_error asserted in the SkyBlue Interface).
7247  */
7248 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
7249 
7250 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
7251 #define CAN_MCR_FRZACK_SHIFT                     (24U)
7252 /*! FRZACK - Freeze Mode Acknowledge
7253  *  0b0..FlexCAN not in Freeze mode, prescaler running.
7254  *  0b1..FlexCAN in Freeze mode, prescaler stopped.
7255  */
7256 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
7257 
7258 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
7259 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
7260 /*! SOFTRST - Soft Reset
7261  *  0b0..No reset request.
7262  *  0b1..Resets the registers affected by soft reset.
7263  */
7264 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
7265 
7266 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
7267 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
7268 /*! WAKMSK - Wake Up Interrupt Mask
7269  *  0b0..Wake Up interrupt is disabled.
7270  *  0b1..Wake Up interrupt is enabled.
7271  */
7272 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
7273 
7274 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
7275 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
7276 /*! NOTRDY - FlexCAN Not Ready
7277  *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
7278  *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
7279  */
7280 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
7281 
7282 #define CAN_MCR_HALT_MASK                        (0x10000000U)
7283 #define CAN_MCR_HALT_SHIFT                       (28U)
7284 /*! HALT - Halt FlexCAN
7285  *  0b0..No Freeze mode request.
7286  *  0b1..Enters Freeze mode if the FRZ bit is asserted.
7287  */
7288 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
7289 
7290 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
7291 #define CAN_MCR_RFEN_SHIFT                       (29U)
7292 /*! RFEN - Rx FIFO Enable
7293  *  0b0..Rx FIFO not enabled.
7294  *  0b1..Rx FIFO enabled.
7295  */
7296 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
7297 
7298 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
7299 #define CAN_MCR_FRZ_SHIFT                        (30U)
7300 /*! FRZ - Freeze Enable
7301  *  0b0..Not enabled to enter Freeze mode.
7302  *  0b1..Enabled to enter Freeze mode.
7303  */
7304 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
7305 
7306 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
7307 #define CAN_MCR_MDIS_SHIFT                       (31U)
7308 /*! MDIS - Module Disable
7309  *  0b0..Enable the FlexCAN module.
7310  *  0b1..Disable the FlexCAN module.
7311  */
7312 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
7313 /*! @} */
7314 
7315 /*! @name CTRL1 - Control 1 register */
7316 /*! @{ */
7317 
7318 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
7319 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
7320 /*! PROPSEG - Propagation Segment */
7321 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
7322 
7323 #define CAN_CTRL1_LOM_MASK                       (0x8U)
7324 #define CAN_CTRL1_LOM_SHIFT                      (3U)
7325 /*! LOM - Listen-Only Mode
7326  *  0b0..Listen-Only mode is deactivated.
7327  *  0b1..FlexCAN module operates in Listen-Only mode.
7328  */
7329 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
7330 
7331 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
7332 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
7333 /*! LBUF - Lowest Buffer Transmitted First
7334  *  0b0..Buffer with highest priority is transmitted first.
7335  *  0b1..Lowest number buffer is transmitted first.
7336  */
7337 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
7338 
7339 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
7340 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
7341 /*! TSYN - Timer Sync
7342  *  0b0..Timer sync feature disabled
7343  *  0b1..Timer sync feature enabled
7344  */
7345 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
7346 
7347 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
7348 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
7349 /*! BOFFREC - Bus Off Recovery
7350  *  0b0..Automatic recovering from Bus Off state enabled.
7351  *  0b1..Automatic recovering from Bus Off state disabled.
7352  */
7353 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
7354 
7355 #define CAN_CTRL1_SMP_MASK                       (0x80U)
7356 #define CAN_CTRL1_SMP_SHIFT                      (7U)
7357 /*! SMP - CAN Bit Sampling
7358  *  0b0..Just one sample is used to determine the bit value.
7359  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
7360  *       preceding samples; a majority rule is used.
7361  */
7362 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
7363 
7364 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
7365 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
7366 /*! RWRNMSK - Rx Warning Interrupt Mask
7367  *  0b0..Rx Warning interrupt disabled.
7368  *  0b1..Rx Warning interrupt enabled.
7369  */
7370 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
7371 
7372 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
7373 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
7374 /*! TWRNMSK - Tx Warning Interrupt Mask
7375  *  0b0..Tx Warning interrupt disabled.
7376  *  0b1..Tx Warning interrupt enabled.
7377  */
7378 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
7379 
7380 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
7381 #define CAN_CTRL1_LPB_SHIFT                      (12U)
7382 /*! LPB - Loop Back Mode
7383  *  0b0..Loop Back disabled.
7384  *  0b1..Loop Back enabled.
7385  */
7386 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
7387 
7388 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
7389 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
7390 /*! CLKSRC - CAN Engine Clock Source
7391  *  0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
7392  *  0b1..The CAN engine clock source is the peripheral clock.
7393  */
7394 #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
7395 
7396 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
7397 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
7398 /*! ERRMSK - Error Interrupt Mask
7399  *  0b0..Error interrupt disabled.
7400  *  0b1..Error interrupt enabled.
7401  */
7402 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
7403 
7404 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
7405 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
7406 /*! BOFFMSK - Bus Off Interrupt Mask
7407  *  0b0..Bus Off interrupt disabled.
7408  *  0b1..Bus Off interrupt enabled.
7409  */
7410 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
7411 
7412 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
7413 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
7414 /*! PSEG2 - Phase Segment 2 */
7415 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
7416 
7417 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
7418 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
7419 /*! PSEG1 - Phase Segment 1 */
7420 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
7421 
7422 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
7423 #define CAN_CTRL1_RJW_SHIFT                      (22U)
7424 /*! RJW - Resync Jump Width */
7425 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
7426 
7427 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
7428 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
7429 /*! PRESDIV - Prescaler Division Factor */
7430 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
7431 /*! @} */
7432 
7433 /*! @name TIMER - Free Running Timer */
7434 /*! @{ */
7435 
7436 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
7437 #define CAN_TIMER_TIMER_SHIFT                    (0U)
7438 /*! TIMER - Timer Value */
7439 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
7440 /*! @} */
7441 
7442 /*! @name RXMGMASK - Rx Mailboxes Global Mask register */
7443 /*! @{ */
7444 
7445 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
7446 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
7447 /*! MG - Rx Mailboxes Global Mask Bits */
7448 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
7449 /*! @} */
7450 
7451 /*! @name RX14MASK - Rx 14 Mask register */
7452 /*! @{ */
7453 
7454 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
7455 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
7456 /*! RX14M - Rx Buffer 14 Mask Bits */
7457 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
7458 /*! @} */
7459 
7460 /*! @name RX15MASK - Rx 15 Mask register */
7461 /*! @{ */
7462 
7463 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
7464 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
7465 /*! RX15M - Rx Buffer 15 Mask Bits */
7466 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
7467 /*! @} */
7468 
7469 /*! @name ECR - Error Counter */
7470 /*! @{ */
7471 
7472 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
7473 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
7474 /*! TXERRCNT - Transmit Error Counter */
7475 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
7476 
7477 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
7478 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
7479 /*! RXERRCNT - Receive Error Counter */
7480 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
7481 
7482 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
7483 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
7484 /*! TXERRCNT_FAST - Transmit Error Counter for fast bits */
7485 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
7486 
7487 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
7488 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
7489 /*! RXERRCNT_FAST - Receive Error Counter for fast bits */
7490 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
7491 /*! @} */
7492 
7493 /*! @name ESR1 - Error and Status 1 register */
7494 /*! @{ */
7495 
7496 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
7497 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
7498 /*! WAKINT - Wake-Up Interrupt
7499  *  0b0..No such occurrence.
7500  *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
7501  */
7502 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
7503 
7504 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
7505 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
7506 /*! ERRINT - Error Interrupt
7507  *  0b0..No such occurrence.
7508  *  0b1..Indicates setting of any error bit in the Error and Status register.
7509  */
7510 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
7511 
7512 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
7513 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
7514 /*! BOFFINT - Bus Off Interrupt
7515  *  0b0..No such occurrence.
7516  *  0b1..FlexCAN module entered Bus Off state.
7517  */
7518 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
7519 
7520 #define CAN_ESR1_RX_MASK                         (0x8U)
7521 #define CAN_ESR1_RX_SHIFT                        (3U)
7522 /*! RX - FlexCAN In Reception
7523  *  0b0..FlexCAN is not receiving a message.
7524  *  0b1..FlexCAN is receiving a message.
7525  */
7526 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
7527 
7528 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
7529 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
7530 /*! FLTCONF - Fault Confinement State
7531  *  0b00..Error Active
7532  *  0b01..Error Passive
7533  *  0b1x..Bus Off
7534  */
7535 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
7536 
7537 #define CAN_ESR1_TX_MASK                         (0x40U)
7538 #define CAN_ESR1_TX_SHIFT                        (6U)
7539 /*! TX - FlexCAN In Transmission
7540  *  0b0..FlexCAN is not transmitting a message.
7541  *  0b1..FlexCAN is transmitting a message.
7542  */
7543 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
7544 
7545 #define CAN_ESR1_IDLE_MASK                       (0x80U)
7546 #define CAN_ESR1_IDLE_SHIFT                      (7U)
7547 /*! IDLE - IDLE
7548  *  0b0..No such occurrence.
7549  *  0b1..CAN bus is now IDLE.
7550  */
7551 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
7552 
7553 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
7554 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
7555 /*! RXWRN - Rx Error Warning
7556  *  0b0..No such occurrence.
7557  *  0b1..RXERRCNT is greater than or equal to 96.
7558  */
7559 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
7560 
7561 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
7562 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
7563 /*! TXWRN - TX Error Warning
7564  *  0b0..No such occurrence.
7565  *  0b1..TXERRCNT is greater than or equal to 96.
7566  */
7567 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
7568 
7569 #define CAN_ESR1_STFERR_MASK                     (0x400U)
7570 #define CAN_ESR1_STFERR_SHIFT                    (10U)
7571 /*! STFERR - Stuffing Error
7572  *  0b0..No such occurrence.
7573  *  0b1..A stuffing error occurred since last read of this register.
7574  */
7575 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
7576 
7577 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
7578 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
7579 /*! FRMERR - Form Error
7580  *  0b0..No such occurrence.
7581  *  0b1..A Form Error occurred since last read of this register.
7582  */
7583 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
7584 
7585 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
7586 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
7587 /*! CRCERR - Cyclic Redundancy Check Error
7588  *  0b0..No such occurrence.
7589  *  0b1..A CRC error occurred since last read of this register.
7590  */
7591 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
7592 
7593 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
7594 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
7595 /*! ACKERR - Acknowledge Error
7596  *  0b0..No such occurrence.
7597  *  0b1..An ACK error occurred since last read of this register.
7598  */
7599 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
7600 
7601 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
7602 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
7603 /*! BIT0ERR - Bit0 Error
7604  *  0b0..No such occurrence.
7605  *  0b1..At least one bit sent as dominant is received as recessive.
7606  */
7607 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
7608 
7609 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
7610 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
7611 /*! BIT1ERR - Bit1 Error
7612  *  0b0..No such occurrence.
7613  *  0b1..At least one bit sent as recessive is received as dominant.
7614  */
7615 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
7616 
7617 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
7618 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
7619 /*! RWRNINT - Rx Warning Interrupt Flag
7620  *  0b0..No such occurrence.
7621  *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
7622  */
7623 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
7624 
7625 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
7626 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
7627 /*! TWRNINT - Tx Warning Interrupt Flag
7628  *  0b0..No such occurrence.
7629  *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
7630  */
7631 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
7632 
7633 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
7634 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
7635 /*! SYNCH - CAN Synchronization Status
7636  *  0b0..FlexCAN is not synchronized to the CAN bus.
7637  *  0b1..FlexCAN is synchronized to the CAN bus.
7638  */
7639 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
7640 
7641 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
7642 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
7643 /*! BOFFDONEINT - Bus Off Done Interrupt
7644  *  0b0..No such occurrence.
7645  *  0b1..FlexCAN module has completed Bus Off process.
7646  */
7647 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
7648 
7649 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
7650 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
7651 /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
7652  *  0b0..No such occurrence.
7653  *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
7654  */
7655 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
7656 
7657 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
7658 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
7659 /*! ERROVR - Error Overrun
7660  *  0b0..Overrun has not occurred.
7661  *  0b1..Overrun has occurred.
7662  */
7663 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
7664 
7665 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
7666 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
7667 /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
7668  *  0b0..No such occurrence.
7669  *  0b1..A stuffing error occurred since last read of this register.
7670  */
7671 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
7672 
7673 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
7674 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
7675 /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
7676  *  0b0..No such occurrence.
7677  *  0b1..A form error occurred since last read of this register.
7678  */
7679 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
7680 
7681 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
7682 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
7683 /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
7684  *  0b0..No such occurrence.
7685  *  0b1..A CRC error occurred since last read of this register.
7686  */
7687 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
7688 
7689 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
7690 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
7691 /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
7692  *  0b0..No such occurrence.
7693  *  0b1..At least one bit sent as dominant is received as recessive.
7694  */
7695 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
7696 
7697 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
7698 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
7699 /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
7700  *  0b0..No such occurrence.
7701  *  0b1..At least one bit sent as recessive is received as dominant.
7702  */
7703 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
7704 /*! @} */
7705 
7706 /*! @name IMASK2 - Interrupt Masks 2 register */
7707 /*! @{ */
7708 
7709 #define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
7710 #define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
7711 /*! BUF63TO32M - Buffer MBi Mask */
7712 #define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
7713 /*! @} */
7714 
7715 /*! @name IMASK1 - Interrupt Masks 1 register */
7716 /*! @{ */
7717 
7718 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
7719 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
7720 /*! BUF31TO0M - Buffer MBi Mask */
7721 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
7722 /*! @} */
7723 
7724 /*! @name IFLAG2 - Interrupt Flags 2 register */
7725 /*! @{ */
7726 
7727 #define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
7728 #define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
7729 /*! BUF63TO32I - Buffer MBi Interrupt */
7730 #define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
7731 /*! @} */
7732 
7733 /*! @name IFLAG1 - Interrupt Flags 1 register */
7734 /*! @{ */
7735 
7736 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
7737 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
7738 /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
7739  *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
7740  *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
7741  */
7742 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
7743 
7744 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
7745 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
7746 /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */
7747 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
7748 
7749 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
7750 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
7751 /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
7752  *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
7753  *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
7754  *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
7755  */
7756 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
7757 
7758 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
7759 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
7760 /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
7761  *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
7762  *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
7763  */
7764 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
7765 
7766 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
7767 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
7768 /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
7769  *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
7770  *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
7771  */
7772 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
7773 
7774 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
7775 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
7776 /*! BUF31TO8I - Buffer MBi Interrupt */
7777 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
7778 /*! @} */
7779 
7780 /*! @name CTRL2 - Control 2 register */
7781 /*! @{ */
7782 
7783 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
7784 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
7785 /*! EDFLTDIS - Edge Filter Disable
7786  *  0b0..Edge filter is enabled
7787  *  0b1..Edge filter is disabled
7788  */
7789 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
7790 
7791 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
7792 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
7793 /*! ISOCANFDEN - ISO CAN FD Enable
7794  *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
7795  *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
7796  */
7797 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
7798 
7799 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
7800 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
7801 /*! PREXCEN - Protocol Exception Enable
7802  *  0b0..Protocol exception is disabled.
7803  *  0b1..Protocol exception is enabled.
7804  */
7805 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
7806 
7807 #define CAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)
7808 #define CAN_CTRL2_TIMER_SRC_SHIFT                (15U)
7809 /*! TIMER_SRC - Timer Source
7810  *  0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
7811  *  0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
7812  *       to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
7813  *       details about the external time tick.
7814  */
7815 #define CAN_CTRL2_TIMER_SRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
7816 
7817 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
7818 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
7819 /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
7820  *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
7821  *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
7822  *       the incoming frame. Mask bits do apply.
7823  */
7824 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
7825 
7826 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
7827 #define CAN_CTRL2_RRS_SHIFT                      (17U)
7828 /*! RRS - Remote Request Storing
7829  *  0b0..Remote response frame is generated.
7830  *  0b1..Remote request frame is stored.
7831  */
7832 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
7833 
7834 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
7835 #define CAN_CTRL2_MRP_SHIFT                      (18U)
7836 /*! MRP - Mailboxes Reception Priority
7837  *  0b0..Matching starts from Rx FIFO or Enhanced Rx FIFO and continues on mailboxes.
7838  *  0b1..Matching starts from mailboxes and continues on Rx FIFO.
7839  */
7840 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
7841 
7842 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
7843 #define CAN_CTRL2_TASD_SHIFT                     (19U)
7844 /*! TASD - Tx Arbitration Start Delay */
7845 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
7846 
7847 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
7848 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
7849 /*! RFFN - Number Of Rx FIFO Filters */
7850 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
7851 
7852 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
7853 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
7854 /*! WRMFRZ - Write-Access To Memory In Freeze Mode
7855  *  0b0..Maintain the write access restrictions.
7856  *  0b1..Enable unrestricted write access to FlexCAN memory.
7857  */
7858 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
7859 
7860 #define CAN_CTRL2_ECRWRE_MASK                    (0x20000000U)
7861 #define CAN_CTRL2_ECRWRE_SHIFT                   (29U)
7862 /*! ECRWRE - Error-correction Configuration Register Write Enable
7863  *  0b0..Disable update.
7864  *  0b1..Enable update.
7865  */
7866 #define CAN_CTRL2_ECRWRE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
7867 
7868 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
7869 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
7870 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
7871  *  0b0..Bus off done interrupt disabled.
7872  *  0b1..Bus off done interrupt enabled.
7873  */
7874 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
7875 
7876 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
7877 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
7878 /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
7879  *  0b0..ERRINT_FAST error interrupt disabled.
7880  *  0b1..ERRINT_FAST error interrupt enabled.
7881  */
7882 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
7883 /*! @} */
7884 
7885 /*! @name ESR2 - Error and Status 2 register */
7886 /*! @{ */
7887 
7888 #define CAN_ESR2_IMB_MASK                        (0x2000U)
7889 #define CAN_ESR2_IMB_SHIFT                       (13U)
7890 /*! IMB - Inactive Mailbox
7891  *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
7892  *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
7893  */
7894 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
7895 
7896 #define CAN_ESR2_VPS_MASK                        (0x4000U)
7897 #define CAN_ESR2_VPS_SHIFT                       (14U)
7898 /*! VPS - Valid Priority Status
7899  *  0b0..Contents of IMB and LPTM are invalid.
7900  *  0b1..Contents of IMB and LPTM are valid.
7901  */
7902 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
7903 
7904 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
7905 #define CAN_ESR2_LPTM_SHIFT                      (16U)
7906 /*! LPTM - Lowest Priority Tx Mailbox */
7907 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
7908 /*! @} */
7909 
7910 /*! @name CRCR - CRC register */
7911 /*! @{ */
7912 
7913 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
7914 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
7915 /*! TXCRC - Transmitted CRC value */
7916 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
7917 
7918 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
7919 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
7920 /*! MBCRC - CRC Mailbox */
7921 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
7922 /*! @} */
7923 
7924 /*! @name RXFGMASK - Rx FIFO Global Mask register */
7925 /*! @{ */
7926 
7927 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
7928 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
7929 /*! FGM - Rx FIFO Global Mask Bits */
7930 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
7931 /*! @} */
7932 
7933 /*! @name RXFIR - Rx FIFO Information register */
7934 /*! @{ */
7935 
7936 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
7937 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
7938 /*! IDHIT - Identifier Acceptance Filter Hit Indicator */
7939 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
7940 /*! @} */
7941 
7942 /*! @name CBT - CAN Bit Timing register */
7943 /*! @{ */
7944 
7945 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
7946 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
7947 /*! EPSEG2 - Extended Phase Segment 2 */
7948 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
7949 
7950 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
7951 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
7952 /*! EPSEG1 - Extended Phase Segment 1 */
7953 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
7954 
7955 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
7956 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
7957 /*! EPROPSEG - Extended Propagation Segment */
7958 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
7959 
7960 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
7961 #define CAN_CBT_ERJW_SHIFT                       (16U)
7962 /*! ERJW - Extended Resync Jump Width */
7963 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
7964 
7965 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
7966 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
7967 /*! EPRESDIV - Extended Prescaler Division Factor */
7968 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
7969 
7970 #define CAN_CBT_BTF_MASK                         (0x80000000U)
7971 #define CAN_CBT_BTF_SHIFT                        (31U)
7972 /*! BTF - Bit Timing Format Enable
7973  *  0b0..Extended bit time definitions disabled.
7974  *  0b1..Extended bit time definitions enabled.
7975  */
7976 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
7977 /*! @} */
7978 
7979 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
7980 /*! @{ */
7981 
7982 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
7983 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
7984 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
7985  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
7986  *    appears on the CAN bus.
7987  */
7988 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
7989 
7990 #define CAN_CS_DLC_MASK                          (0xF0000U)
7991 #define CAN_CS_DLC_SHIFT                         (16U)
7992 /*! DLC - Length of the data to be stored/transmitted. */
7993 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
7994 
7995 #define CAN_CS_RTR_MASK                          (0x100000U)
7996 #define CAN_CS_RTR_SHIFT                         (20U)
7997 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
7998 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
7999 
8000 #define CAN_CS_IDE_MASK                          (0x200000U)
8001 #define CAN_CS_IDE_SHIFT                         (21U)
8002 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
8003 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
8004 
8005 #define CAN_CS_SRR_MASK                          (0x400000U)
8006 #define CAN_CS_SRR_SHIFT                         (22U)
8007 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
8008 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
8009 
8010 #define CAN_CS_CODE_MASK                         (0xF000000U)
8011 #define CAN_CS_CODE_SHIFT                        (24U)
8012 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
8013  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
8014  */
8015 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
8016 
8017 #define CAN_CS_ESI_MASK                          (0x20000000U)
8018 #define CAN_CS_ESI_SHIFT                         (29U)
8019 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
8020 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
8021 
8022 #define CAN_CS_BRS_MASK                          (0x40000000U)
8023 #define CAN_CS_BRS_SHIFT                         (30U)
8024 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
8025 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
8026 
8027 #define CAN_CS_EDL_MASK                          (0x80000000U)
8028 #define CAN_CS_EDL_SHIFT                         (31U)
8029 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
8030  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
8031  */
8032 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
8033 /*! @} */
8034 
8035 /* The count of CAN_CS */
8036 #define CAN_CS_COUNT                             (64U)
8037 
8038 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
8039 /*! @{ */
8040 
8041 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
8042 #define CAN_ID_EXT_SHIFT                         (0U)
8043 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
8044 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
8045 
8046 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
8047 #define CAN_ID_STD_SHIFT                         (18U)
8048 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
8049 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
8050 
8051 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
8052 #define CAN_ID_PRIO_SHIFT                        (29U)
8053 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
8054  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
8055  *    ID to define the transmission priority.
8056  */
8057 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
8058 /*! @} */
8059 
8060 /* The count of CAN_ID */
8061 #define CAN_ID_COUNT                             (64U)
8062 
8063 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
8064 /*! @{ */
8065 
8066 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
8067 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
8068 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
8069 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
8070 
8071 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
8072 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
8073 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
8074 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
8075 
8076 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
8077 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
8078 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
8079 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
8080 
8081 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
8082 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
8083 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
8084 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
8085 /*! @} */
8086 
8087 /* The count of CAN_WORD0 */
8088 #define CAN_WORD0_COUNT                          (64U)
8089 
8090 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
8091 /*! @{ */
8092 
8093 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
8094 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
8095 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
8096 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
8097 
8098 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
8099 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
8100 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
8101 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
8102 
8103 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
8104 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
8105 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
8106 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
8107 
8108 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
8109 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
8110 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
8111 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
8112 /*! @} */
8113 
8114 /* The count of CAN_WORD1 */
8115 #define CAN_WORD1_COUNT                          (64U)
8116 
8117 /*! @name RXIMR - Rx Individual Mask registers */
8118 /*! @{ */
8119 
8120 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
8121 #define CAN_RXIMR_MI_SHIFT                       (0U)
8122 /*! MI - Individual Mask Bits */
8123 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
8124 /*! @} */
8125 
8126 /* The count of CAN_RXIMR */
8127 #define CAN_RXIMR_COUNT                          (64U)
8128 
8129 /*! @name MECR - Memory Error Control register */
8130 /*! @{ */
8131 
8132 #define CAN_MECR_NCEFAFRZ_MASK                   (0x80U)
8133 #define CAN_MECR_NCEFAFRZ_SHIFT                  (7U)
8134 /*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode
8135  *  0b0..Keep normal operation.
8136  *  0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").
8137  */
8138 #define CAN_MECR_NCEFAFRZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
8139 
8140 #define CAN_MECR_ECCDIS_MASK                     (0x100U)
8141 #define CAN_MECR_ECCDIS_SHIFT                    (8U)
8142 /*! ECCDIS - Error Correction Disable
8143  *  0b0..Enable memory error correction.
8144  *  0b1..Disable memory error correction.
8145  */
8146 #define CAN_MECR_ECCDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
8147 
8148 #define CAN_MECR_RERRDIS_MASK                    (0x200U)
8149 #define CAN_MECR_RERRDIS_SHIFT                   (9U)
8150 /*! RERRDIS - Error Report Disable
8151  *  0b0..Enable updates of the error report registers.
8152  *  0b1..Disable updates of the error report registers.
8153  */
8154 #define CAN_MECR_RERRDIS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
8155 
8156 #define CAN_MECR_EXTERRIE_MASK                   (0x2000U)
8157 #define CAN_MECR_EXTERRIE_SHIFT                  (13U)
8158 /*! EXTERRIE - Extended Error Injection Enable
8159  *  0b0..Error injection is applied only to the 32-bit word.
8160  *  0b1..Error injection is applied to the 64-bit word.
8161  */
8162 #define CAN_MECR_EXTERRIE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
8163 
8164 #define CAN_MECR_FAERRIE_MASK                    (0x4000U)
8165 #define CAN_MECR_FAERRIE_SHIFT                   (14U)
8166 /*! FAERRIE - FlexCAN Access Error Injection Enable
8167  *  0b0..Injection is disabled.
8168  *  0b1..Injection is enabled.
8169  */
8170 #define CAN_MECR_FAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
8171 
8172 #define CAN_MECR_HAERRIE_MASK                    (0x8000U)
8173 #define CAN_MECR_HAERRIE_SHIFT                   (15U)
8174 /*! HAERRIE - Host Access Error Injection Enable
8175  *  0b0..Injection is disabled.
8176  *  0b1..Injection is enabled.
8177  */
8178 #define CAN_MECR_HAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
8179 
8180 #define CAN_MECR_CEI_MSK_MASK                    (0x10000U)
8181 #define CAN_MECR_CEI_MSK_SHIFT                   (16U)
8182 /*! CEI_MSK - Correctable Errors Interrupt Mask
8183  *  0b0..Interrupt is disabled.
8184  *  0b1..Interrupt is enabled.
8185  */
8186 #define CAN_MECR_CEI_MSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
8187 
8188 #define CAN_MECR_FANCEI_MSK_MASK                 (0x40000U)
8189 #define CAN_MECR_FANCEI_MSK_SHIFT                (18U)
8190 /*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask
8191  *  0b0..Interrupt is disabled.
8192  *  0b1..Interrupt is enabled.
8193  */
8194 #define CAN_MECR_FANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
8195 
8196 #define CAN_MECR_HANCEI_MSK_MASK                 (0x80000U)
8197 #define CAN_MECR_HANCEI_MSK_SHIFT                (19U)
8198 /*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask
8199  *  0b0..Interrupt is disabled.
8200  *  0b1..Interrupt is enabled.
8201  */
8202 #define CAN_MECR_HANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
8203 
8204 #define CAN_MECR_ECRWRDIS_MASK                   (0x80000000U)
8205 #define CAN_MECR_ECRWRDIS_SHIFT                  (31U)
8206 /*! ECRWRDIS - Error Configuration Register Write Disable
8207  *  0b0..Write is enabled.
8208  *  0b1..Write is disabled.
8209  */
8210 #define CAN_MECR_ECRWRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
8211 /*! @} */
8212 
8213 /*! @name ERRIAR - Error Injection Address register */
8214 /*! @{ */
8215 
8216 #define CAN_ERRIAR_INJADDR_L_MASK                (0x3U)
8217 #define CAN_ERRIAR_INJADDR_L_SHIFT               (0U)
8218 /*! INJADDR_L - Error Injection Address Low */
8219 #define CAN_ERRIAR_INJADDR_L(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
8220 
8221 #define CAN_ERRIAR_INJADDR_H_MASK                (0x3FFCU)
8222 #define CAN_ERRIAR_INJADDR_H_SHIFT               (2U)
8223 /*! INJADDR_H - Error Injection Address High */
8224 #define CAN_ERRIAR_INJADDR_H(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
8225 /*! @} */
8226 
8227 /*! @name ERRIDPR - Error Injection Data Pattern register */
8228 /*! @{ */
8229 
8230 #define CAN_ERRIDPR_DFLIP_MASK                   (0xFFFFFFFFU)
8231 #define CAN_ERRIDPR_DFLIP_SHIFT                  (0U)
8232 /*! DFLIP - Data flip pattern */
8233 #define CAN_ERRIDPR_DFLIP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
8234 /*! @} */
8235 
8236 /*! @name ERRIPPR - Error Injection Parity Pattern register */
8237 /*! @{ */
8238 
8239 #define CAN_ERRIPPR_PFLIP0_MASK                  (0x1FU)
8240 #define CAN_ERRIPPR_PFLIP0_SHIFT                 (0U)
8241 /*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant) */
8242 #define CAN_ERRIPPR_PFLIP0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
8243 
8244 #define CAN_ERRIPPR_PFLIP1_MASK                  (0x1F00U)
8245 #define CAN_ERRIPPR_PFLIP1_SHIFT                 (8U)
8246 /*! PFLIP1 - Parity Flip Pattern For Byte 1 */
8247 #define CAN_ERRIPPR_PFLIP1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
8248 
8249 #define CAN_ERRIPPR_PFLIP2_MASK                  (0x1F0000U)
8250 #define CAN_ERRIPPR_PFLIP2_SHIFT                 (16U)
8251 /*! PFLIP2 - Parity Flip Pattern For Byte 2 */
8252 #define CAN_ERRIPPR_PFLIP2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
8253 
8254 #define CAN_ERRIPPR_PFLIP3_MASK                  (0x1F000000U)
8255 #define CAN_ERRIPPR_PFLIP3_SHIFT                 (24U)
8256 /*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant) */
8257 #define CAN_ERRIPPR_PFLIP3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
8258 /*! @} */
8259 
8260 /*! @name RERRAR - Error Report Address register */
8261 /*! @{ */
8262 
8263 #define CAN_RERRAR_ERRADDR_MASK                  (0x3FFFU)
8264 #define CAN_RERRAR_ERRADDR_SHIFT                 (0U)
8265 /*! ERRADDR - Address Where Error Detected */
8266 #define CAN_RERRAR_ERRADDR(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
8267 
8268 #define CAN_RERRAR_SAID_MASK                     (0x70000U)
8269 #define CAN_RERRAR_SAID_SHIFT                    (16U)
8270 /*! SAID - SAID */
8271 #define CAN_RERRAR_SAID(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
8272 
8273 #define CAN_RERRAR_NCE_MASK                      (0x1000000U)
8274 #define CAN_RERRAR_NCE_SHIFT                     (24U)
8275 /*! NCE - Non-Correctable Error
8276  *  0b0..Reporting a correctable error
8277  *  0b1..Reporting a non-correctable error
8278  */
8279 #define CAN_RERRAR_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
8280 /*! @} */
8281 
8282 /*! @name RERRDR - Error Report Data register */
8283 /*! @{ */
8284 
8285 #define CAN_RERRDR_RDATA_MASK                    (0xFFFFFFFFU)
8286 #define CAN_RERRDR_RDATA_SHIFT                   (0U)
8287 /*! RDATA - Raw data word read from memory with error */
8288 #define CAN_RERRDR_RDATA(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
8289 /*! @} */
8290 
8291 /*! @name RERRSYNR - Error Report Syndrome register */
8292 /*! @{ */
8293 
8294 #define CAN_RERRSYNR_SYND0_MASK                  (0x1FU)
8295 #define CAN_RERRSYNR_SYND0_SHIFT                 (0U)
8296 /*! SYND0 - Error Syndrome For Byte 0 (least significant) */
8297 #define CAN_RERRSYNR_SYND0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
8298 
8299 #define CAN_RERRSYNR_BE0_MASK                    (0x80U)
8300 #define CAN_RERRSYNR_BE0_SHIFT                   (7U)
8301 /*! BE0 - Byte Enabled For Byte 0 (least significant)
8302  *  0b0..The byte was not read.
8303  *  0b1..The byte was read.
8304  */
8305 #define CAN_RERRSYNR_BE0(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
8306 
8307 #define CAN_RERRSYNR_SYND1_MASK                  (0x1F00U)
8308 #define CAN_RERRSYNR_SYND1_SHIFT                 (8U)
8309 /*! SYND1 - Error Syndrome for Byte 1 */
8310 #define CAN_RERRSYNR_SYND1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
8311 
8312 #define CAN_RERRSYNR_BE1_MASK                    (0x8000U)
8313 #define CAN_RERRSYNR_BE1_SHIFT                   (15U)
8314 /*! BE1 - Byte Enabled For Byte 1
8315  *  0b0..The byte was not read.
8316  *  0b1..The byte was read.
8317  */
8318 #define CAN_RERRSYNR_BE1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
8319 
8320 #define CAN_RERRSYNR_SYND2_MASK                  (0x1F0000U)
8321 #define CAN_RERRSYNR_SYND2_SHIFT                 (16U)
8322 /*! SYND2 - Error Syndrome For Byte 2 */
8323 #define CAN_RERRSYNR_SYND2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
8324 
8325 #define CAN_RERRSYNR_BE2_MASK                    (0x800000U)
8326 #define CAN_RERRSYNR_BE2_SHIFT                   (23U)
8327 /*! BE2 - Byte Enabled For Byte 2
8328  *  0b0..The byte was not read.
8329  *  0b1..The byte was read.
8330  */
8331 #define CAN_RERRSYNR_BE2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
8332 
8333 #define CAN_RERRSYNR_SYND3_MASK                  (0x1F000000U)
8334 #define CAN_RERRSYNR_SYND3_SHIFT                 (24U)
8335 /*! SYND3 - Error Syndrome For Byte 3 (most significant) */
8336 #define CAN_RERRSYNR_SYND3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
8337 
8338 #define CAN_RERRSYNR_BE3_MASK                    (0x80000000U)
8339 #define CAN_RERRSYNR_BE3_SHIFT                   (31U)
8340 /*! BE3 - Byte Enabled For Byte 3 (most significant)
8341  *  0b0..The byte was not read.
8342  *  0b1..The byte was read.
8343  */
8344 #define CAN_RERRSYNR_BE3(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
8345 /*! @} */
8346 
8347 /*! @name ERRSR - Error Status register */
8348 /*! @{ */
8349 
8350 #define CAN_ERRSR_CEIOF_MASK                     (0x1U)
8351 #define CAN_ERRSR_CEIOF_SHIFT                    (0U)
8352 /*! CEIOF - Correctable Error Interrupt Overrun Flag
8353  *  0b0..No overrun on correctable errors
8354  *  0b1..Overrun on correctable errors
8355  */
8356 #define CAN_ERRSR_CEIOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
8357 
8358 #define CAN_ERRSR_FANCEIOF_MASK                  (0x4U)
8359 #define CAN_ERRSR_FANCEIOF_SHIFT                 (2U)
8360 /*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag
8361  *  0b0..No overrun on non-correctable errors in FlexCAN access
8362  *  0b1..Overrun on non-correctable errors in FlexCAN access
8363  */
8364 #define CAN_ERRSR_FANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
8365 
8366 #define CAN_ERRSR_HANCEIOF_MASK                  (0x8U)
8367 #define CAN_ERRSR_HANCEIOF_SHIFT                 (3U)
8368 /*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag
8369  *  0b0..No overrun on non-correctable errors in host access
8370  *  0b1..Overrun on non-correctable errors in host access
8371  */
8372 #define CAN_ERRSR_HANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
8373 
8374 #define CAN_ERRSR_CEIF_MASK                      (0x10000U)
8375 #define CAN_ERRSR_CEIF_SHIFT                     (16U)
8376 /*! CEIF - Correctable Error Interrupt Flag
8377  *  0b0..No correctable errors were detected so far.
8378  *  0b1..A correctable error was detected.
8379  */
8380 #define CAN_ERRSR_CEIF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
8381 
8382 #define CAN_ERRSR_FANCEIF_MASK                   (0x40000U)
8383 #define CAN_ERRSR_FANCEIF_SHIFT                  (18U)
8384 /*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag
8385  *  0b0..No non-correctable errors were detected in FlexCAN accesses so far.
8386  *  0b1..A non-correctable error was detected in a FlexCAN access.
8387  */
8388 #define CAN_ERRSR_FANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
8389 
8390 #define CAN_ERRSR_HANCEIF_MASK                   (0x80000U)
8391 #define CAN_ERRSR_HANCEIF_SHIFT                  (19U)
8392 /*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag
8393  *  0b0..No non-correctable errors were detected in host accesses so far.
8394  *  0b1..A non-correctable error was detected in a host access.
8395  */
8396 #define CAN_ERRSR_HANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
8397 /*! @} */
8398 
8399 /*! @name FDCTRL - CAN FD Control register */
8400 /*! @{ */
8401 
8402 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
8403 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
8404 /*! TDCVAL - Transceiver Delay Compensation Value */
8405 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
8406 
8407 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
8408 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
8409 /*! TDCOFF - Transceiver Delay Compensation Offset */
8410 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
8411 
8412 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
8413 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
8414 /*! TDCFAIL - Transceiver Delay Compensation Fail
8415  *  0b0..Measured loop delay is in range.
8416  *  0b1..Measured loop delay is out of range.
8417  */
8418 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
8419 
8420 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
8421 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
8422 /*! TDCEN - Transceiver Delay Compensation Enable
8423  *  0b0..TDC is disabled
8424  *  0b1..TDC is enabled
8425  */
8426 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
8427 
8428 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
8429 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
8430 /*! MBDSR0 - Message Buffer Data Size for Region 0
8431  *  0b00..Selects 8 bytes per message buffer.
8432  *  0b01..Selects 16 bytes per message buffer.
8433  *  0b10..Selects 32 bytes per message buffer.
8434  *  0b11..Selects 64 bytes per message buffer.
8435  */
8436 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
8437 
8438 #define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
8439 #define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
8440 /*! MBDSR1 - Message Buffer Data Size for Region 1
8441  *  0b00..Selects 8 bytes per message buffer.
8442  *  0b01..Selects 16 bytes per message buffer.
8443  *  0b10..Selects 32 bytes per message buffer.
8444  *  0b11..Selects 64 bytes per message buffer.
8445  */
8446 #define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
8447 
8448 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
8449 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
8450 /*! FDRATE - Bit Rate Switch Enable
8451  *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
8452  *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
8453  */
8454 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
8455 /*! @} */
8456 
8457 /*! @name FDCBT - CAN FD Bit Timing register */
8458 /*! @{ */
8459 
8460 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
8461 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
8462 /*! FPSEG2 - Fast Phase Segment 2 */
8463 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
8464 
8465 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
8466 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
8467 /*! FPSEG1 - Fast Phase Segment 1 */
8468 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
8469 
8470 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
8471 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
8472 /*! FPROPSEG - Fast Propagation Segment */
8473 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
8474 
8475 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
8476 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
8477 /*! FRJW - Fast Resync Jump Width */
8478 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
8479 
8480 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
8481 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
8482 /*! FPRESDIV - Fast Prescaler Division Factor */
8483 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
8484 /*! @} */
8485 
8486 /*! @name FDCRC - CAN FD CRC register */
8487 /*! @{ */
8488 
8489 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
8490 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
8491 /*! FD_TXCRC - Extended Transmitted CRC value */
8492 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
8493 
8494 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
8495 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
8496 /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC */
8497 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
8498 /*! @} */
8499 
8500 
8501 /*!
8502  * @}
8503  */ /* end of group CAN_Register_Masks */
8504 
8505 
8506 /* CAN - Peripheral instance base addresses */
8507 /** Peripheral FLEXCAN1 base address */
8508 #define FLEXCAN1_BASE                            (0x308C0000u)
8509 /** Peripheral FLEXCAN1 base pointer */
8510 #define FLEXCAN1                                 ((CAN_Type *)FLEXCAN1_BASE)
8511 /** Peripheral FLEXCAN2 base address */
8512 #define FLEXCAN2_BASE                            (0x308D0000u)
8513 /** Peripheral FLEXCAN2 base pointer */
8514 #define FLEXCAN2                                 ((CAN_Type *)FLEXCAN2_BASE)
8515 /** Array initializer of CAN peripheral base addresses */
8516 #define CAN_BASE_ADDRS                           { 0u, FLEXCAN1_BASE, FLEXCAN2_BASE }
8517 /** Array initializer of CAN peripheral base pointers */
8518 #define CAN_BASE_PTRS                            { (CAN_Type *)0u, FLEXCAN1, FLEXCAN2 }
8519 /** Interrupt vectors for the CAN peripheral type */
8520 #define CAN_Rx_Warning_IRQS                      { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
8521 #define CAN_Tx_Warning_IRQS                      { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
8522 #define CAN_Wake_Up_IRQS                         { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
8523 #define CAN_Error_IRQS                           { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
8524 #define CAN_Bus_Off_IRQS                         { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
8525 #define CAN_ORed_Message_buffer_IRQS             { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
8526 
8527 /*!
8528  * @}
8529  */ /* end of group CAN_Peripheral_Access_Layer */
8530 
8531 
8532 /* ----------------------------------------------------------------------------
8533    -- CCM Peripheral Access Layer
8534    ---------------------------------------------------------------------------- */
8535 
8536 /*!
8537  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
8538  * @{
8539  */
8540 
8541 /** CCM - Register Layout Typedef */
8542 typedef struct {
8543   __IO uint32_t GPR0;                              /**< General Purpose Register, offset: 0x0 */
8544   __IO uint32_t GPR0_SET;                          /**< General Purpose Register, offset: 0x4 */
8545   __IO uint32_t GPR0_CLR;                          /**< General Purpose Register, offset: 0x8 */
8546   __IO uint32_t GPR0_TOG;                          /**< General Purpose Register, offset: 0xC */
8547        uint8_t RESERVED_0[2032];
8548   struct {                                         /* offset: 0x800, array step: 0x10 */
8549     __IO uint32_t PLL_CTRL;                          /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
8550     __IO uint32_t PLL_CTRL_SET;                      /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
8551     __IO uint32_t PLL_CTRL_CLR;                      /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
8552     __IO uint32_t PLL_CTRL_TOG;                      /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
8553   } PLL_CTRL[39];
8554        uint8_t RESERVED_1[13712];
8555   struct {                                         /* offset: 0x4000, array step: 0x10 */
8556     __IO uint32_t CCGR;                              /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
8557     __IO uint32_t CCGR_SET;                          /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
8558     __IO uint32_t CCGR_CLR;                          /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
8559     __IO uint32_t CCGR_TOG;                          /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
8560   } CCGR[192];
8561        uint8_t RESERVED_2[13312];
8562   struct {                                         /* offset: 0x8000, array step: 0x80 */
8563     __IO uint32_t TARGET_ROOT;                       /**< Target Register, array offset: 0x8000, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8564     __IO uint32_t TARGET_ROOT_SET;                   /**< Target Register, array offset: 0x8004, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8565     __IO uint32_t TARGET_ROOT_CLR;                   /**< Target Register, array offset: 0x8008, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8566     __IO uint32_t TARGET_ROOT_TOG;                   /**< Target Register, array offset: 0x800C, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8567     __IO uint32_t MISC;                              /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8568     __IO uint32_t MISC_ROOT_SET;                     /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8569     __IO uint32_t MISC_ROOT_CLR;                     /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8570     __IO uint32_t MISC_ROOT_TOG;                     /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8571     __IO uint32_t POST;                              /**< Post Divider Register, array offset: 0x8020, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8572     __IO uint32_t POST_ROOT_SET;                     /**< Post Divider Register, array offset: 0x8024, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8573     __IO uint32_t POST_ROOT_CLR;                     /**< Post Divider Register, array offset: 0x8028, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8574     __IO uint32_t POST_ROOT_TOG;                     /**< Post Divider Register, array offset: 0x802C, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8575     __IO uint32_t PRE;                               /**< Pre Divider Register, array offset: 0x8030, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8576     __IO uint32_t PRE_ROOT_SET;                      /**< Pre Divider Register, array offset: 0x8034, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8577     __IO uint32_t PRE_ROOT_CLR;                      /**< Pre Divider Register, array offset: 0x8038, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8578     __IO uint32_t PRE_ROOT_TOG;                      /**< Pre Divider Register, array offset: 0x803C, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8579          uint8_t RESERVED_0[48];
8580     __IO uint32_t ACCESS_CTRL;                       /**< Access Control Register, array offset: 0x8070, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8581     __IO uint32_t ACCESS_CTRL_ROOT_SET;              /**< Access Control Register, array offset: 0x8074, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8582     __IO uint32_t ACCESS_CTRL_ROOT_CLR;              /**< Access Control Register, array offset: 0x8078, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8583     __IO uint32_t ACCESS_CTRL_ROOT_TOG;              /**< Access Control Register, array offset: 0x807C, array step: 0x80, valid indices: [0-8, 16-29, 32-39, 48-49, 64-141] */
8584   } ROOT[142];
8585 } CCM_Type;
8586 
8587 /* ----------------------------------------------------------------------------
8588    -- CCM Register Masks
8589    ---------------------------------------------------------------------------- */
8590 
8591 /*!
8592  * @addtogroup CCM_Register_Masks CCM Register Masks
8593  * @{
8594  */
8595 
8596 /*! @name GPR0 - General Purpose Register */
8597 /*! @{ */
8598 
8599 #define CCM_GPR0_GP0_MASK                        (0xFFFFFFFFU)
8600 #define CCM_GPR0_GP0_SHIFT                       (0U)
8601 #define CCM_GPR0_GP0(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
8602 /*! @} */
8603 
8604 /*! @name GPR0_SET - General Purpose Register */
8605 /*! @{ */
8606 
8607 #define CCM_GPR0_SET_GP0_MASK                    (0xFFFFFFFFU)
8608 #define CCM_GPR0_SET_GP0_SHIFT                   (0U)
8609 #define CCM_GPR0_SET_GP0(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
8610 /*! @} */
8611 
8612 /*! @name GPR0_CLR - General Purpose Register */
8613 /*! @{ */
8614 
8615 #define CCM_GPR0_CLR_GP0_MASK                    (0xFFFFFFFFU)
8616 #define CCM_GPR0_CLR_GP0_SHIFT                   (0U)
8617 #define CCM_GPR0_CLR_GP0(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
8618 /*! @} */
8619 
8620 /*! @name GPR0_TOG - General Purpose Register */
8621 /*! @{ */
8622 
8623 #define CCM_GPR0_TOG_GP0_MASK                    (0xFFFFFFFFU)
8624 #define CCM_GPR0_TOG_GP0_SHIFT                   (0U)
8625 #define CCM_GPR0_TOG_GP0(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
8626 /*! @} */
8627 
8628 /*! @name PLL_CTRL - CCM PLL Control Register */
8629 /*! @{ */
8630 
8631 #define CCM_PLL_CTRL_SETTING0_MASK               (0x3U)
8632 #define CCM_PLL_CTRL_SETTING0_SHIFT              (0U)
8633 /*! SETTING0
8634  *  0b00..Domain clocks not needed
8635  *  0b01..Domain clocks needed when in RUN
8636  *  0b10..Domain clocks needed when in RUN and WAIT
8637  *  0b11..Domain clocks needed all the time
8638  */
8639 #define CCM_PLL_CTRL_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
8640 
8641 #define CCM_PLL_CTRL_SETTING1_MASK               (0x30U)
8642 #define CCM_PLL_CTRL_SETTING1_SHIFT              (4U)
8643 /*! SETTING1
8644  *  0b00..Domain clocks not needed
8645  *  0b01..Domain clocks needed when in RUN
8646  *  0b10..Domain clocks needed when in RUN and WAIT
8647  *  0b11..Domain clocks needed all the time
8648  */
8649 #define CCM_PLL_CTRL_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
8650 
8651 #define CCM_PLL_CTRL_SETTING2_MASK               (0x300U)
8652 #define CCM_PLL_CTRL_SETTING2_SHIFT              (8U)
8653 /*! SETTING2
8654  *  0b00..Domain clocks not needed
8655  *  0b01..Domain clocks needed when in RUN
8656  *  0b10..Domain clocks needed when in RUN and WAIT
8657  *  0b11..Domain clocks needed all the time
8658  */
8659 #define CCM_PLL_CTRL_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
8660 
8661 #define CCM_PLL_CTRL_SETTING3_MASK               (0x3000U)
8662 #define CCM_PLL_CTRL_SETTING3_SHIFT              (12U)
8663 /*! SETTING3
8664  *  0b00..Domain clocks not needed
8665  *  0b01..Domain clocks needed when in RUN
8666  *  0b10..Domain clocks needed when in RUN and WAIT
8667  *  0b11..Domain clocks needed all the time
8668  */
8669 #define CCM_PLL_CTRL_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
8670 /*! @} */
8671 
8672 /* The count of CCM_PLL_CTRL */
8673 #define CCM_PLL_CTRL_COUNT                       (39U)
8674 
8675 /*! @name PLL_CTRL_SET - CCM PLL Control Register */
8676 /*! @{ */
8677 
8678 #define CCM_PLL_CTRL_SET_SETTING0_MASK           (0x3U)
8679 #define CCM_PLL_CTRL_SET_SETTING0_SHIFT          (0U)
8680 /*! SETTING0
8681  *  0b00..Domain clocks not needed
8682  *  0b01..Domain clocks needed when in RUN
8683  *  0b10..Domain clocks needed when in RUN and WAIT
8684  *  0b11..Domain clocks needed all the time
8685  */
8686 #define CCM_PLL_CTRL_SET_SETTING0(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
8687 
8688 #define CCM_PLL_CTRL_SET_SETTING1_MASK           (0x30U)
8689 #define CCM_PLL_CTRL_SET_SETTING1_SHIFT          (4U)
8690 /*! SETTING1
8691  *  0b00..Domain clocks not needed
8692  *  0b01..Domain clocks needed when in RUN
8693  *  0b10..Domain clocks needed when in RUN and WAIT
8694  *  0b11..Domain clocks needed all the time
8695  */
8696 #define CCM_PLL_CTRL_SET_SETTING1(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
8697 
8698 #define CCM_PLL_CTRL_SET_SETTING2_MASK           (0x300U)
8699 #define CCM_PLL_CTRL_SET_SETTING2_SHIFT          (8U)
8700 /*! SETTING2
8701  *  0b00..Domain clocks not needed
8702  *  0b01..Domain clocks needed when in RUN
8703  *  0b10..Domain clocks needed when in RUN and WAIT
8704  *  0b11..Domain clocks needed all the time
8705  */
8706 #define CCM_PLL_CTRL_SET_SETTING2(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
8707 
8708 #define CCM_PLL_CTRL_SET_SETTING3_MASK           (0x3000U)
8709 #define CCM_PLL_CTRL_SET_SETTING3_SHIFT          (12U)
8710 /*! SETTING3
8711  *  0b00..Domain clocks not needed
8712  *  0b01..Domain clocks needed when in RUN
8713  *  0b10..Domain clocks needed when in RUN and WAIT
8714  *  0b11..Domain clocks needed all the time
8715  */
8716 #define CCM_PLL_CTRL_SET_SETTING3(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
8717 /*! @} */
8718 
8719 /* The count of CCM_PLL_CTRL_SET */
8720 #define CCM_PLL_CTRL_SET_COUNT                   (39U)
8721 
8722 /*! @name PLL_CTRL_CLR - CCM PLL Control Register */
8723 /*! @{ */
8724 
8725 #define CCM_PLL_CTRL_CLR_SETTING0_MASK           (0x3U)
8726 #define CCM_PLL_CTRL_CLR_SETTING0_SHIFT          (0U)
8727 /*! SETTING0
8728  *  0b00..Domain clocks not needed
8729  *  0b01..Domain clocks needed when in RUN
8730  *  0b10..Domain clocks needed when in RUN and WAIT
8731  *  0b11..Domain clocks needed all the time
8732  */
8733 #define CCM_PLL_CTRL_CLR_SETTING0(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
8734 
8735 #define CCM_PLL_CTRL_CLR_SETTING1_MASK           (0x30U)
8736 #define CCM_PLL_CTRL_CLR_SETTING1_SHIFT          (4U)
8737 /*! SETTING1
8738  *  0b00..Domain clocks not needed
8739  *  0b01..Domain clocks needed when in RUN
8740  *  0b10..Domain clocks needed when in RUN and WAIT
8741  *  0b11..Domain clocks needed all the time
8742  */
8743 #define CCM_PLL_CTRL_CLR_SETTING1(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
8744 
8745 #define CCM_PLL_CTRL_CLR_SETTING2_MASK           (0x300U)
8746 #define CCM_PLL_CTRL_CLR_SETTING2_SHIFT          (8U)
8747 /*! SETTING2
8748  *  0b00..Domain clocks not needed
8749  *  0b01..Domain clocks needed when in RUN
8750  *  0b10..Domain clocks needed when in RUN and WAIT
8751  *  0b11..Domain clocks needed all the time
8752  */
8753 #define CCM_PLL_CTRL_CLR_SETTING2(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
8754 
8755 #define CCM_PLL_CTRL_CLR_SETTING3_MASK           (0x3000U)
8756 #define CCM_PLL_CTRL_CLR_SETTING3_SHIFT          (12U)
8757 /*! SETTING3
8758  *  0b00..Domain clocks not needed
8759  *  0b01..Domain clocks needed when in RUN
8760  *  0b10..Domain clocks needed when in RUN and WAIT
8761  *  0b11..Domain clocks needed all the time
8762  */
8763 #define CCM_PLL_CTRL_CLR_SETTING3(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
8764 /*! @} */
8765 
8766 /* The count of CCM_PLL_CTRL_CLR */
8767 #define CCM_PLL_CTRL_CLR_COUNT                   (39U)
8768 
8769 /*! @name PLL_CTRL_TOG - CCM PLL Control Register */
8770 /*! @{ */
8771 
8772 #define CCM_PLL_CTRL_TOG_SETTING0_MASK           (0x3U)
8773 #define CCM_PLL_CTRL_TOG_SETTING0_SHIFT          (0U)
8774 /*! SETTING0
8775  *  0b00..Domain clocks not needed
8776  *  0b01..Domain clocks needed when in RUN
8777  *  0b10..Domain clocks needed when in RUN and WAIT
8778  *  0b11..Domain clocks needed all the time
8779  */
8780 #define CCM_PLL_CTRL_TOG_SETTING0(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
8781 
8782 #define CCM_PLL_CTRL_TOG_SETTING1_MASK           (0x30U)
8783 #define CCM_PLL_CTRL_TOG_SETTING1_SHIFT          (4U)
8784 /*! SETTING1
8785  *  0b00..Domain clocks not needed
8786  *  0b01..Domain clocks needed when in RUN
8787  *  0b10..Domain clocks needed when in RUN and WAIT
8788  *  0b11..Domain clocks needed all the time
8789  */
8790 #define CCM_PLL_CTRL_TOG_SETTING1(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
8791 
8792 #define CCM_PLL_CTRL_TOG_SETTING2_MASK           (0x300U)
8793 #define CCM_PLL_CTRL_TOG_SETTING2_SHIFT          (8U)
8794 /*! SETTING2
8795  *  0b00..Domain clocks not needed
8796  *  0b01..Domain clocks needed when in RUN
8797  *  0b10..Domain clocks needed when in RUN and WAIT
8798  *  0b11..Domain clocks needed all the time
8799  */
8800 #define CCM_PLL_CTRL_TOG_SETTING2(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
8801 
8802 #define CCM_PLL_CTRL_TOG_SETTING3_MASK           (0x3000U)
8803 #define CCM_PLL_CTRL_TOG_SETTING3_SHIFT          (12U)
8804 /*! SETTING3
8805  *  0b00..Domain clocks not needed
8806  *  0b01..Domain clocks needed when in RUN
8807  *  0b10..Domain clocks needed when in RUN and WAIT
8808  *  0b11..Domain clocks needed all the time
8809  */
8810 #define CCM_PLL_CTRL_TOG_SETTING3(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
8811 /*! @} */
8812 
8813 /* The count of CCM_PLL_CTRL_TOG */
8814 #define CCM_PLL_CTRL_TOG_COUNT                   (39U)
8815 
8816 /*! @name CCGR - CCM Clock Gating Register */
8817 /*! @{ */
8818 
8819 #define CCM_CCGR_SETTING0_MASK                   (0x3U)
8820 #define CCM_CCGR_SETTING0_SHIFT                  (0U)
8821 /*! SETTING0
8822  *  0b00..Domain clocks not needed
8823  *  0b01..Domain clocks needed when in RUN
8824  *  0b10..Domain clocks needed when in RUN and WAIT
8825  *  0b11..Domain clocks needed all the time
8826  */
8827 #define CCM_CCGR_SETTING0(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
8828 
8829 #define CCM_CCGR_SETTING1_MASK                   (0x30U)
8830 #define CCM_CCGR_SETTING1_SHIFT                  (4U)
8831 /*! SETTING1
8832  *  0b00..Domain clocks not needed
8833  *  0b01..Domain clocks needed when in RUN
8834  *  0b10..Domain clocks needed when in RUN and WAIT
8835  *  0b11..Domain clocks needed all the time
8836  */
8837 #define CCM_CCGR_SETTING1(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
8838 
8839 #define CCM_CCGR_SETTING2_MASK                   (0x300U)
8840 #define CCM_CCGR_SETTING2_SHIFT                  (8U)
8841 /*! SETTING2
8842  *  0b00..Domain clocks not needed
8843  *  0b01..Domain clocks needed when in RUN
8844  *  0b10..Domain clocks needed when in RUN and WAIT
8845  *  0b11..Domain clocks needed all the time
8846  */
8847 #define CCM_CCGR_SETTING2(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
8848 
8849 #define CCM_CCGR_SETTING3_MASK                   (0x3000U)
8850 #define CCM_CCGR_SETTING3_SHIFT                  (12U)
8851 /*! SETTING3
8852  *  0b00..Domain clocks not needed
8853  *  0b01..Domain clocks needed when in RUN
8854  *  0b10..Domain clocks needed when in RUN and WAIT
8855  *  0b11..Domain clocks needed all the time
8856  */
8857 #define CCM_CCGR_SETTING3(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
8858 /*! @} */
8859 
8860 /* The count of CCM_CCGR */
8861 #define CCM_CCGR_COUNT                           (192U)
8862 
8863 /*! @name CCGR_SET - CCM Clock Gating Register */
8864 /*! @{ */
8865 
8866 #define CCM_CCGR_SET_SETTING0_MASK               (0x3U)
8867 #define CCM_CCGR_SET_SETTING0_SHIFT              (0U)
8868 /*! SETTING0
8869  *  0b00..Domain clocks not needed
8870  *  0b01..Domain clocks needed when in RUN
8871  *  0b10..Domain clocks needed when in RUN and WAIT
8872  *  0b11..Domain clocks needed all the time
8873  */
8874 #define CCM_CCGR_SET_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
8875 
8876 #define CCM_CCGR_SET_SETTING1_MASK               (0x30U)
8877 #define CCM_CCGR_SET_SETTING1_SHIFT              (4U)
8878 /*! SETTING1
8879  *  0b00..Domain clocks not needed
8880  *  0b01..Domain clocks needed when in RUN
8881  *  0b10..Domain clocks needed when in RUN and WAIT
8882  *  0b11..Domain clocks needed all the time
8883  */
8884 #define CCM_CCGR_SET_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
8885 
8886 #define CCM_CCGR_SET_SETTING2_MASK               (0x300U)
8887 #define CCM_CCGR_SET_SETTING2_SHIFT              (8U)
8888 /*! SETTING2
8889  *  0b00..Domain clocks not needed
8890  *  0b01..Domain clocks needed when in RUN
8891  *  0b10..Domain clocks needed when in RUN and WAIT
8892  *  0b11..Domain clocks needed all the time
8893  */
8894 #define CCM_CCGR_SET_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
8895 
8896 #define CCM_CCGR_SET_SETTING3_MASK               (0x3000U)
8897 #define CCM_CCGR_SET_SETTING3_SHIFT              (12U)
8898 /*! SETTING3
8899  *  0b00..Domain clocks not needed
8900  *  0b01..Domain clocks needed when in RUN
8901  *  0b10..Domain clocks needed when in RUN and WAIT
8902  *  0b11..Domain clocks needed all the time
8903  */
8904 #define CCM_CCGR_SET_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
8905 /*! @} */
8906 
8907 /* The count of CCM_CCGR_SET */
8908 #define CCM_CCGR_SET_COUNT                       (192U)
8909 
8910 /*! @name CCGR_CLR - CCM Clock Gating Register */
8911 /*! @{ */
8912 
8913 #define CCM_CCGR_CLR_SETTING0_MASK               (0x3U)
8914 #define CCM_CCGR_CLR_SETTING0_SHIFT              (0U)
8915 /*! SETTING0
8916  *  0b00..Domain clocks not needed
8917  *  0b01..Domain clocks needed when in RUN
8918  *  0b10..Domain clocks needed when in RUN and WAIT
8919  *  0b11..Domain clocks needed all the time
8920  */
8921 #define CCM_CCGR_CLR_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
8922 
8923 #define CCM_CCGR_CLR_SETTING1_MASK               (0x30U)
8924 #define CCM_CCGR_CLR_SETTING1_SHIFT              (4U)
8925 /*! SETTING1
8926  *  0b00..Domain clocks not needed
8927  *  0b01..Domain clocks needed when in RUN
8928  *  0b10..Domain clocks needed when in RUN and WAIT
8929  *  0b11..Domain clocks needed all the time
8930  */
8931 #define CCM_CCGR_CLR_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
8932 
8933 #define CCM_CCGR_CLR_SETTING2_MASK               (0x300U)
8934 #define CCM_CCGR_CLR_SETTING2_SHIFT              (8U)
8935 /*! SETTING2
8936  *  0b00..Domain clocks not needed
8937  *  0b01..Domain clocks needed when in RUN
8938  *  0b10..Domain clocks needed when in RUN and WAIT
8939  *  0b11..Domain clocks needed all the time
8940  */
8941 #define CCM_CCGR_CLR_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
8942 
8943 #define CCM_CCGR_CLR_SETTING3_MASK               (0x3000U)
8944 #define CCM_CCGR_CLR_SETTING3_SHIFT              (12U)
8945 /*! SETTING3
8946  *  0b00..Domain clocks not needed
8947  *  0b01..Domain clocks needed when in RUN
8948  *  0b10..Domain clocks needed when in RUN and WAIT
8949  *  0b11..Domain clocks needed all the time
8950  */
8951 #define CCM_CCGR_CLR_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
8952 /*! @} */
8953 
8954 /* The count of CCM_CCGR_CLR */
8955 #define CCM_CCGR_CLR_COUNT                       (192U)
8956 
8957 /*! @name CCGR_TOG - CCM Clock Gating Register */
8958 /*! @{ */
8959 
8960 #define CCM_CCGR_TOG_SETTING0_MASK               (0x3U)
8961 #define CCM_CCGR_TOG_SETTING0_SHIFT              (0U)
8962 /*! SETTING0
8963  *  0b00..Domain clocks not needed
8964  *  0b01..Domain clocks needed when in RUN
8965  *  0b10..Domain clocks needed when in RUN and WAIT
8966  *  0b11..Domain clocks needed all the time
8967  */
8968 #define CCM_CCGR_TOG_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
8969 
8970 #define CCM_CCGR_TOG_SETTING1_MASK               (0x30U)
8971 #define CCM_CCGR_TOG_SETTING1_SHIFT              (4U)
8972 /*! SETTING1
8973  *  0b00..Domain clocks not needed
8974  *  0b01..Domain clocks needed when in RUN
8975  *  0b10..Domain clocks needed when in RUN and WAIT
8976  *  0b11..Domain clocks needed all the time
8977  */
8978 #define CCM_CCGR_TOG_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
8979 
8980 #define CCM_CCGR_TOG_SETTING2_MASK               (0x300U)
8981 #define CCM_CCGR_TOG_SETTING2_SHIFT              (8U)
8982 /*! SETTING2
8983  *  0b00..Domain clocks not needed
8984  *  0b01..Domain clocks needed when in RUN
8985  *  0b10..Domain clocks needed when in RUN and WAIT
8986  *  0b11..Domain clocks needed all the time
8987  */
8988 #define CCM_CCGR_TOG_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
8989 
8990 #define CCM_CCGR_TOG_SETTING3_MASK               (0x3000U)
8991 #define CCM_CCGR_TOG_SETTING3_SHIFT              (12U)
8992 /*! SETTING3
8993  *  0b00..Domain clocks not needed
8994  *  0b01..Domain clocks needed when in RUN
8995  *  0b10..Domain clocks needed when in RUN and WAIT
8996  *  0b11..Domain clocks needed all the time
8997  */
8998 #define CCM_CCGR_TOG_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
8999 /*! @} */
9000 
9001 /* The count of CCM_CCGR_TOG */
9002 #define CCM_CCGR_TOG_COUNT                       (192U)
9003 
9004 /*! @name TARGET_ROOT - Target Register */
9005 /*! @{ */
9006 
9007 #define CCM_TARGET_ROOT_POST_PODF_MASK           (0x3FU)
9008 #define CCM_TARGET_ROOT_POST_PODF_SHIFT          (0U)
9009 /*! POST_PODF
9010  *  0b000000..Divide by 1
9011  *  0b000001..Divide by 2
9012  *  0b000010..Divide by 3
9013  *  0b000011..Divide by 4
9014  *  0b000100..Divide by 5
9015  *  0b000101..Divide by 6
9016  *  0b111111..Divide by 64
9017  */
9018 #define CCM_TARGET_ROOT_POST_PODF(x)             (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
9019 
9020 #define CCM_TARGET_ROOT_PRE_PODF_MASK            (0x70000U)
9021 #define CCM_TARGET_ROOT_PRE_PODF_SHIFT           (16U)
9022 /*! PRE_PODF
9023  *  0b000..Divide by 1
9024  *  0b001..Divide by 2
9025  *  0b010..Divide by 3
9026  *  0b011..Divide by 4
9027  *  0b100..Divide by 5
9028  *  0b101..Divide by 6
9029  *  0b110..Divide by 7
9030  *  0b111..Divide by 8
9031  */
9032 #define CCM_TARGET_ROOT_PRE_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
9033 
9034 #define CCM_TARGET_ROOT_MUX_MASK                 (0x7000000U)
9035 #define CCM_TARGET_ROOT_MUX_SHIFT                (24U)
9036 #define CCM_TARGET_ROOT_MUX(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
9037 
9038 #define CCM_TARGET_ROOT_ENABLE_MASK              (0x10000000U)
9039 #define CCM_TARGET_ROOT_ENABLE_SHIFT             (28U)
9040 /*! ENABLE
9041  *  0b0..clock root is OFF
9042  *  0b1..clock root is ON
9043  */
9044 #define CCM_TARGET_ROOT_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
9045 /*! @} */
9046 
9047 /* The count of CCM_TARGET_ROOT */
9048 #define CCM_TARGET_ROOT_COUNT                    (142U)
9049 
9050 /*! @name TARGET_ROOT_SET - Target Register */
9051 /*! @{ */
9052 
9053 #define CCM_TARGET_ROOT_SET_POST_PODF_MASK       (0x3FU)
9054 #define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT      (0U)
9055 /*! POST_PODF
9056  *  0b000000..Divide by 1
9057  *  0b000001..Divide by 2
9058  *  0b000010..Divide by 3
9059  *  0b000011..Divide by 4
9060  *  0b000100..Divide by 5
9061  *  0b000101..Divide by 6
9062  *  0b111111..Divide by 64
9063  */
9064 #define CCM_TARGET_ROOT_SET_POST_PODF(x)         (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
9065 
9066 #define CCM_TARGET_ROOT_SET_PRE_PODF_MASK        (0x70000U)
9067 #define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT       (16U)
9068 /*! PRE_PODF
9069  *  0b000..Divide by 1
9070  *  0b001..Divide by 2
9071  *  0b010..Divide by 3
9072  *  0b011..Divide by 4
9073  *  0b100..Divide by 5
9074  *  0b101..Divide by 6
9075  *  0b110..Divide by 7
9076  *  0b111..Divide by 8
9077  */
9078 #define CCM_TARGET_ROOT_SET_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
9079 
9080 #define CCM_TARGET_ROOT_SET_MUX_MASK             (0x7000000U)
9081 #define CCM_TARGET_ROOT_SET_MUX_SHIFT            (24U)
9082 #define CCM_TARGET_ROOT_SET_MUX(x)               (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
9083 
9084 #define CCM_TARGET_ROOT_SET_ENABLE_MASK          (0x10000000U)
9085 #define CCM_TARGET_ROOT_SET_ENABLE_SHIFT         (28U)
9086 /*! ENABLE
9087  *  0b0..clock root is OFF
9088  *  0b1..clock root is ON
9089  */
9090 #define CCM_TARGET_ROOT_SET_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
9091 /*! @} */
9092 
9093 /* The count of CCM_TARGET_ROOT_SET */
9094 #define CCM_TARGET_ROOT_SET_COUNT                (142U)
9095 
9096 /*! @name TARGET_ROOT_CLR - Target Register */
9097 /*! @{ */
9098 
9099 #define CCM_TARGET_ROOT_CLR_POST_PODF_MASK       (0x3FU)
9100 #define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT      (0U)
9101 /*! POST_PODF
9102  *  0b000000..Divide by 1
9103  *  0b000001..Divide by 2
9104  *  0b000010..Divide by 3
9105  *  0b000011..Divide by 4
9106  *  0b000100..Divide by 5
9107  *  0b000101..Divide by 6
9108  *  0b111111..Divide by 64
9109  */
9110 #define CCM_TARGET_ROOT_CLR_POST_PODF(x)         (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
9111 
9112 #define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK        (0x70000U)
9113 #define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT       (16U)
9114 /*! PRE_PODF
9115  *  0b000..Divide by 1
9116  *  0b001..Divide by 2
9117  *  0b010..Divide by 3
9118  *  0b011..Divide by 4
9119  *  0b100..Divide by 5
9120  *  0b101..Divide by 6
9121  *  0b110..Divide by 7
9122  *  0b111..Divide by 8
9123  */
9124 #define CCM_TARGET_ROOT_CLR_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
9125 
9126 #define CCM_TARGET_ROOT_CLR_MUX_MASK             (0x7000000U)
9127 #define CCM_TARGET_ROOT_CLR_MUX_SHIFT            (24U)
9128 #define CCM_TARGET_ROOT_CLR_MUX(x)               (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
9129 
9130 #define CCM_TARGET_ROOT_CLR_ENABLE_MASK          (0x10000000U)
9131 #define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT         (28U)
9132 /*! ENABLE
9133  *  0b0..clock root is OFF
9134  *  0b1..clock root is ON
9135  */
9136 #define CCM_TARGET_ROOT_CLR_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
9137 /*! @} */
9138 
9139 /* The count of CCM_TARGET_ROOT_CLR */
9140 #define CCM_TARGET_ROOT_CLR_COUNT                (142U)
9141 
9142 /*! @name TARGET_ROOT_TOG - Target Register */
9143 /*! @{ */
9144 
9145 #define CCM_TARGET_ROOT_TOG_POST_PODF_MASK       (0x3FU)
9146 #define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT      (0U)
9147 /*! POST_PODF
9148  *  0b000000..Divide by 1
9149  *  0b000001..Divide by 2
9150  *  0b000010..Divide by 3
9151  *  0b000011..Divide by 4
9152  *  0b000100..Divide by 5
9153  *  0b000101..Divide by 6
9154  *  0b111111..Divide by 64
9155  */
9156 #define CCM_TARGET_ROOT_TOG_POST_PODF(x)         (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
9157 
9158 #define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK        (0x70000U)
9159 #define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT       (16U)
9160 /*! PRE_PODF
9161  *  0b000..Divide by 1
9162  *  0b001..Divide by 2
9163  *  0b010..Divide by 3
9164  *  0b011..Divide by 4
9165  *  0b100..Divide by 5
9166  *  0b101..Divide by 6
9167  *  0b110..Divide by 7
9168  *  0b111..Divide by 8
9169  */
9170 #define CCM_TARGET_ROOT_TOG_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
9171 
9172 #define CCM_TARGET_ROOT_TOG_MUX_MASK             (0x7000000U)
9173 #define CCM_TARGET_ROOT_TOG_MUX_SHIFT            (24U)
9174 #define CCM_TARGET_ROOT_TOG_MUX(x)               (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
9175 
9176 #define CCM_TARGET_ROOT_TOG_ENABLE_MASK          (0x10000000U)
9177 #define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT         (28U)
9178 /*! ENABLE
9179  *  0b0..clock root is OFF
9180  *  0b1..clock root is ON
9181  */
9182 #define CCM_TARGET_ROOT_TOG_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
9183 /*! @} */
9184 
9185 /* The count of CCM_TARGET_ROOT_TOG */
9186 #define CCM_TARGET_ROOT_TOG_COUNT                (142U)
9187 
9188 /*! @name MISC - Miscellaneous Register */
9189 /*! @{ */
9190 
9191 #define CCM_MISC_AUTHEN_FAIL_MASK                (0x1U)
9192 #define CCM_MISC_AUTHEN_FAIL_SHIFT               (0U)
9193 #define CCM_MISC_AUTHEN_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
9194 
9195 #define CCM_MISC_TIMEOUT_MASK                    (0x10U)
9196 #define CCM_MISC_TIMEOUT_SHIFT                   (4U)
9197 #define CCM_MISC_TIMEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
9198 
9199 #define CCM_MISC_VIOLATE_MASK                    (0x100U)
9200 #define CCM_MISC_VIOLATE_SHIFT                   (8U)
9201 #define CCM_MISC_VIOLATE(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
9202 /*! @} */
9203 
9204 /* The count of CCM_MISC */
9205 #define CCM_MISC_COUNT                           (142U)
9206 
9207 /*! @name MISC_ROOT_SET - Miscellaneous Register */
9208 /*! @{ */
9209 
9210 #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK       (0x1U)
9211 #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT      (0U)
9212 #define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
9213 
9214 #define CCM_MISC_ROOT_SET_TIMEOUT_MASK           (0x10U)
9215 #define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT          (4U)
9216 #define CCM_MISC_ROOT_SET_TIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
9217 
9218 #define CCM_MISC_ROOT_SET_VIOLATE_MASK           (0x100U)
9219 #define CCM_MISC_ROOT_SET_VIOLATE_SHIFT          (8U)
9220 #define CCM_MISC_ROOT_SET_VIOLATE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
9221 /*! @} */
9222 
9223 /* The count of CCM_MISC_ROOT_SET */
9224 #define CCM_MISC_ROOT_SET_COUNT                  (142U)
9225 
9226 /*! @name MISC_ROOT_CLR - Miscellaneous Register */
9227 /*! @{ */
9228 
9229 #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK       (0x1U)
9230 #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT      (0U)
9231 #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
9232 
9233 #define CCM_MISC_ROOT_CLR_TIMEOUT_MASK           (0x10U)
9234 #define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT          (4U)
9235 #define CCM_MISC_ROOT_CLR_TIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
9236 
9237 #define CCM_MISC_ROOT_CLR_VIOLATE_MASK           (0x100U)
9238 #define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT          (8U)
9239 #define CCM_MISC_ROOT_CLR_VIOLATE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
9240 /*! @} */
9241 
9242 /* The count of CCM_MISC_ROOT_CLR */
9243 #define CCM_MISC_ROOT_CLR_COUNT                  (142U)
9244 
9245 /*! @name MISC_ROOT_TOG - Miscellaneous Register */
9246 /*! @{ */
9247 
9248 #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK       (0x1U)
9249 #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT      (0U)
9250 #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
9251 
9252 #define CCM_MISC_ROOT_TOG_TIMEOUT_MASK           (0x10U)
9253 #define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT          (4U)
9254 #define CCM_MISC_ROOT_TOG_TIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
9255 
9256 #define CCM_MISC_ROOT_TOG_VIOLATE_MASK           (0x100U)
9257 #define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT          (8U)
9258 #define CCM_MISC_ROOT_TOG_VIOLATE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
9259 /*! @} */
9260 
9261 /* The count of CCM_MISC_ROOT_TOG */
9262 #define CCM_MISC_ROOT_TOG_COUNT                  (142U)
9263 
9264 /*! @name POST - Post Divider Register */
9265 /*! @{ */
9266 
9267 #define CCM_POST_POST_PODF_MASK                  (0x3FU)
9268 #define CCM_POST_POST_PODF_SHIFT                 (0U)
9269 /*! POST_PODF
9270  *  0b000000..Divide by 1
9271  *  0b000001..Divide by 2
9272  *  0b000010..Divide by 3
9273  *  0b000011..Divide by 4
9274  *  0b000100..Divide by 5
9275  *  0b000101..Divide by 6
9276  *  0b111111..Divide by 64
9277  */
9278 #define CCM_POST_POST_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
9279 
9280 #define CCM_POST_BUSY1_MASK                      (0x80U)
9281 #define CCM_POST_BUSY1_SHIFT                     (7U)
9282 #define CCM_POST_BUSY1(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
9283 
9284 #define CCM_POST_SELECT_MASK                     (0x10000000U)
9285 #define CCM_POST_SELECT_SHIFT                    (28U)
9286 /*! SELECT
9287  *  0b0..select branch A
9288  *  0b1..select branch B
9289  */
9290 #define CCM_POST_SELECT(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
9291 
9292 #define CCM_POST_BUSY2_MASK                      (0x80000000U)
9293 #define CCM_POST_BUSY2_SHIFT                     (31U)
9294 #define CCM_POST_BUSY2(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
9295 /*! @} */
9296 
9297 /* The count of CCM_POST */
9298 #define CCM_POST_COUNT                           (142U)
9299 
9300 /*! @name POST_ROOT_SET - Post Divider Register */
9301 /*! @{ */
9302 
9303 #define CCM_POST_ROOT_SET_POST_PODF_MASK         (0x3FU)
9304 #define CCM_POST_ROOT_SET_POST_PODF_SHIFT        (0U)
9305 /*! POST_PODF
9306  *  0b000000..Divide by 1
9307  *  0b000001..Divide by 2
9308  *  0b000010..Divide by 3
9309  *  0b000011..Divide by 4
9310  *  0b000100..Divide by 5
9311  *  0b000101..Divide by 6
9312  *  0b111111..Divide by 64
9313  */
9314 #define CCM_POST_ROOT_SET_POST_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
9315 
9316 #define CCM_POST_ROOT_SET_BUSY1_MASK             (0x80U)
9317 #define CCM_POST_ROOT_SET_BUSY1_SHIFT            (7U)
9318 #define CCM_POST_ROOT_SET_BUSY1(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
9319 
9320 #define CCM_POST_ROOT_SET_SELECT_MASK            (0x10000000U)
9321 #define CCM_POST_ROOT_SET_SELECT_SHIFT           (28U)
9322 /*! SELECT
9323  *  0b0..select branch A
9324  *  0b1..select branch B
9325  */
9326 #define CCM_POST_ROOT_SET_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
9327 
9328 #define CCM_POST_ROOT_SET_BUSY2_MASK             (0x80000000U)
9329 #define CCM_POST_ROOT_SET_BUSY2_SHIFT            (31U)
9330 #define CCM_POST_ROOT_SET_BUSY2(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
9331 /*! @} */
9332 
9333 /* The count of CCM_POST_ROOT_SET */
9334 #define CCM_POST_ROOT_SET_COUNT                  (142U)
9335 
9336 /*! @name POST_ROOT_CLR - Post Divider Register */
9337 /*! @{ */
9338 
9339 #define CCM_POST_ROOT_CLR_POST_PODF_MASK         (0x3FU)
9340 #define CCM_POST_ROOT_CLR_POST_PODF_SHIFT        (0U)
9341 /*! POST_PODF
9342  *  0b000000..Divide by 1
9343  *  0b000001..Divide by 2
9344  *  0b000010..Divide by 3
9345  *  0b000011..Divide by 4
9346  *  0b000100..Divide by 5
9347  *  0b000101..Divide by 6
9348  *  0b111111..Divide by 64
9349  */
9350 #define CCM_POST_ROOT_CLR_POST_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
9351 
9352 #define CCM_POST_ROOT_CLR_BUSY1_MASK             (0x80U)
9353 #define CCM_POST_ROOT_CLR_BUSY1_SHIFT            (7U)
9354 #define CCM_POST_ROOT_CLR_BUSY1(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
9355 
9356 #define CCM_POST_ROOT_CLR_SELECT_MASK            (0x10000000U)
9357 #define CCM_POST_ROOT_CLR_SELECT_SHIFT           (28U)
9358 /*! SELECT
9359  *  0b0..select branch A
9360  *  0b1..select branch B
9361  */
9362 #define CCM_POST_ROOT_CLR_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
9363 
9364 #define CCM_POST_ROOT_CLR_BUSY2_MASK             (0x80000000U)
9365 #define CCM_POST_ROOT_CLR_BUSY2_SHIFT            (31U)
9366 #define CCM_POST_ROOT_CLR_BUSY2(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
9367 /*! @} */
9368 
9369 /* The count of CCM_POST_ROOT_CLR */
9370 #define CCM_POST_ROOT_CLR_COUNT                  (142U)
9371 
9372 /*! @name POST_ROOT_TOG - Post Divider Register */
9373 /*! @{ */
9374 
9375 #define CCM_POST_ROOT_TOG_POST_PODF_MASK         (0x3FU)
9376 #define CCM_POST_ROOT_TOG_POST_PODF_SHIFT        (0U)
9377 /*! POST_PODF
9378  *  0b000000..Divide by 1
9379  *  0b000001..Divide by 2
9380  *  0b000010..Divide by 3
9381  *  0b000011..Divide by 4
9382  *  0b000100..Divide by 5
9383  *  0b000101..Divide by 6
9384  *  0b111111..Divide by 64
9385  */
9386 #define CCM_POST_ROOT_TOG_POST_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
9387 
9388 #define CCM_POST_ROOT_TOG_BUSY1_MASK             (0x80U)
9389 #define CCM_POST_ROOT_TOG_BUSY1_SHIFT            (7U)
9390 #define CCM_POST_ROOT_TOG_BUSY1(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
9391 
9392 #define CCM_POST_ROOT_TOG_SELECT_MASK            (0x10000000U)
9393 #define CCM_POST_ROOT_TOG_SELECT_SHIFT           (28U)
9394 /*! SELECT
9395  *  0b0..select branch A
9396  *  0b1..select branch B
9397  */
9398 #define CCM_POST_ROOT_TOG_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
9399 
9400 #define CCM_POST_ROOT_TOG_BUSY2_MASK             (0x80000000U)
9401 #define CCM_POST_ROOT_TOG_BUSY2_SHIFT            (31U)
9402 #define CCM_POST_ROOT_TOG_BUSY2(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
9403 /*! @} */
9404 
9405 /* The count of CCM_POST_ROOT_TOG */
9406 #define CCM_POST_ROOT_TOG_COUNT                  (142U)
9407 
9408 /*! @name PRE - Pre Divider Register */
9409 /*! @{ */
9410 
9411 #define CCM_PRE_PRE_PODF_B_MASK                  (0x7U)
9412 #define CCM_PRE_PRE_PODF_B_SHIFT                 (0U)
9413 /*! PRE_PODF_B
9414  *  0b000..Divide by 1
9415  *  0b001..Divide by 2
9416  *  0b010..Divide by 3
9417  *  0b011..Divide by 4
9418  *  0b100..Divide by 5
9419  *  0b101..Divide by 6
9420  *  0b110..Divide by 7
9421  *  0b111..Divide by 8
9422  */
9423 #define CCM_PRE_PRE_PODF_B(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
9424 
9425 #define CCM_PRE_BUSY0_MASK                       (0x8U)
9426 #define CCM_PRE_BUSY0_SHIFT                      (3U)
9427 #define CCM_PRE_BUSY0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
9428 
9429 #define CCM_PRE_MUX_B_MASK                       (0x700U)
9430 #define CCM_PRE_MUX_B_SHIFT                      (8U)
9431 #define CCM_PRE_MUX_B(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
9432 
9433 #define CCM_PRE_EN_B_MASK                        (0x1000U)
9434 #define CCM_PRE_EN_B_SHIFT                       (12U)
9435 /*! EN_B
9436  *  0b0..Clock shutdown
9437  *  0b1..Clock ON
9438  */
9439 #define CCM_PRE_EN_B(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
9440 
9441 #define CCM_PRE_BUSY1_MASK                       (0x8000U)
9442 #define CCM_PRE_BUSY1_SHIFT                      (15U)
9443 #define CCM_PRE_BUSY1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
9444 
9445 #define CCM_PRE_PRE_PODF_A_MASK                  (0x70000U)
9446 #define CCM_PRE_PRE_PODF_A_SHIFT                 (16U)
9447 /*! PRE_PODF_A
9448  *  0b000..Divide by 1
9449  *  0b001..Divide by 2
9450  *  0b010..Divide by 3
9451  *  0b011..Divide by 4
9452  *  0b100..Divide by 5
9453  *  0b101..Divide by 6
9454  *  0b110..Divide by 7
9455  *  0b111..Divide by 8
9456  */
9457 #define CCM_PRE_PRE_PODF_A(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
9458 
9459 #define CCM_PRE_BUSY3_MASK                       (0x80000U)
9460 #define CCM_PRE_BUSY3_SHIFT                      (19U)
9461 #define CCM_PRE_BUSY3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
9462 
9463 #define CCM_PRE_MUX_A_MASK                       (0x7000000U)
9464 #define CCM_PRE_MUX_A_SHIFT                      (24U)
9465 #define CCM_PRE_MUX_A(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
9466 
9467 #define CCM_PRE_EN_A_MASK                        (0x10000000U)
9468 #define CCM_PRE_EN_A_SHIFT                       (28U)
9469 /*! EN_A
9470  *  0b0..Clock shutdown
9471  *  0b1..clock ON
9472  */
9473 #define CCM_PRE_EN_A(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
9474 
9475 #define CCM_PRE_BUSY4_MASK                       (0x80000000U)
9476 #define CCM_PRE_BUSY4_SHIFT                      (31U)
9477 #define CCM_PRE_BUSY4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
9478 /*! @} */
9479 
9480 /* The count of CCM_PRE */
9481 #define CCM_PRE_COUNT                            (142U)
9482 
9483 /*! @name PRE_ROOT_SET - Pre Divider Register */
9484 /*! @{ */
9485 
9486 #define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK         (0x7U)
9487 #define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT        (0U)
9488 /*! PRE_PODF_B
9489  *  0b000..Divide by 1
9490  *  0b001..Divide by 2
9491  *  0b010..Divide by 3
9492  *  0b011..Divide by 4
9493  *  0b100..Divide by 5
9494  *  0b101..Divide by 6
9495  *  0b110..Divide by 7
9496  *  0b111..Divide by 8
9497  */
9498 #define CCM_PRE_ROOT_SET_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
9499 
9500 #define CCM_PRE_ROOT_SET_BUSY0_MASK              (0x8U)
9501 #define CCM_PRE_ROOT_SET_BUSY0_SHIFT             (3U)
9502 #define CCM_PRE_ROOT_SET_BUSY0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
9503 
9504 #define CCM_PRE_ROOT_SET_MUX_B_MASK              (0x700U)
9505 #define CCM_PRE_ROOT_SET_MUX_B_SHIFT             (8U)
9506 #define CCM_PRE_ROOT_SET_MUX_B(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
9507 
9508 #define CCM_PRE_ROOT_SET_EN_B_MASK               (0x1000U)
9509 #define CCM_PRE_ROOT_SET_EN_B_SHIFT              (12U)
9510 /*! EN_B
9511  *  0b0..Clock shutdown
9512  *  0b1..Clock ON
9513  */
9514 #define CCM_PRE_ROOT_SET_EN_B(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
9515 
9516 #define CCM_PRE_ROOT_SET_BUSY1_MASK              (0x8000U)
9517 #define CCM_PRE_ROOT_SET_BUSY1_SHIFT             (15U)
9518 #define CCM_PRE_ROOT_SET_BUSY1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
9519 
9520 #define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK         (0x70000U)
9521 #define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT        (16U)
9522 /*! PRE_PODF_A
9523  *  0b000..Divide by 1
9524  *  0b001..Divide by 2
9525  *  0b010..Divide by 3
9526  *  0b011..Divide by 4
9527  *  0b100..Divide by 5
9528  *  0b101..Divide by 6
9529  *  0b110..Divide by 7
9530  *  0b111..Divide by 8
9531  */
9532 #define CCM_PRE_ROOT_SET_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
9533 
9534 #define CCM_PRE_ROOT_SET_BUSY3_MASK              (0x80000U)
9535 #define CCM_PRE_ROOT_SET_BUSY3_SHIFT             (19U)
9536 #define CCM_PRE_ROOT_SET_BUSY3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
9537 
9538 #define CCM_PRE_ROOT_SET_MUX_A_MASK              (0x7000000U)
9539 #define CCM_PRE_ROOT_SET_MUX_A_SHIFT             (24U)
9540 #define CCM_PRE_ROOT_SET_MUX_A(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
9541 
9542 #define CCM_PRE_ROOT_SET_EN_A_MASK               (0x10000000U)
9543 #define CCM_PRE_ROOT_SET_EN_A_SHIFT              (28U)
9544 /*! EN_A
9545  *  0b0..Clock shutdown
9546  *  0b1..clock ON
9547  */
9548 #define CCM_PRE_ROOT_SET_EN_A(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
9549 
9550 #define CCM_PRE_ROOT_SET_BUSY4_MASK              (0x80000000U)
9551 #define CCM_PRE_ROOT_SET_BUSY4_SHIFT             (31U)
9552 #define CCM_PRE_ROOT_SET_BUSY4(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
9553 /*! @} */
9554 
9555 /* The count of CCM_PRE_ROOT_SET */
9556 #define CCM_PRE_ROOT_SET_COUNT                   (142U)
9557 
9558 /*! @name PRE_ROOT_CLR - Pre Divider Register */
9559 /*! @{ */
9560 
9561 #define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK         (0x7U)
9562 #define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT        (0U)
9563 /*! PRE_PODF_B
9564  *  0b000..Divide by 1
9565  *  0b001..Divide by 2
9566  *  0b010..Divide by 3
9567  *  0b011..Divide by 4
9568  *  0b100..Divide by 5
9569  *  0b101..Divide by 6
9570  *  0b110..Divide by 7
9571  *  0b111..Divide by 8
9572  */
9573 #define CCM_PRE_ROOT_CLR_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
9574 
9575 #define CCM_PRE_ROOT_CLR_BUSY0_MASK              (0x8U)
9576 #define CCM_PRE_ROOT_CLR_BUSY0_SHIFT             (3U)
9577 #define CCM_PRE_ROOT_CLR_BUSY0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
9578 
9579 #define CCM_PRE_ROOT_CLR_MUX_B_MASK              (0x700U)
9580 #define CCM_PRE_ROOT_CLR_MUX_B_SHIFT             (8U)
9581 #define CCM_PRE_ROOT_CLR_MUX_B(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
9582 
9583 #define CCM_PRE_ROOT_CLR_EN_B_MASK               (0x1000U)
9584 #define CCM_PRE_ROOT_CLR_EN_B_SHIFT              (12U)
9585 /*! EN_B
9586  *  0b0..Clock shutdown
9587  *  0b1..Clock ON
9588  */
9589 #define CCM_PRE_ROOT_CLR_EN_B(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
9590 
9591 #define CCM_PRE_ROOT_CLR_BUSY1_MASK              (0x8000U)
9592 #define CCM_PRE_ROOT_CLR_BUSY1_SHIFT             (15U)
9593 #define CCM_PRE_ROOT_CLR_BUSY1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
9594 
9595 #define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK         (0x70000U)
9596 #define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT        (16U)
9597 /*! PRE_PODF_A
9598  *  0b000..Divide by 1
9599  *  0b001..Divide by 2
9600  *  0b010..Divide by 3
9601  *  0b011..Divide by 4
9602  *  0b100..Divide by 5
9603  *  0b101..Divide by 6
9604  *  0b110..Divide by 7
9605  *  0b111..Divide by 8
9606  */
9607 #define CCM_PRE_ROOT_CLR_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
9608 
9609 #define CCM_PRE_ROOT_CLR_BUSY3_MASK              (0x80000U)
9610 #define CCM_PRE_ROOT_CLR_BUSY3_SHIFT             (19U)
9611 #define CCM_PRE_ROOT_CLR_BUSY3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
9612 
9613 #define CCM_PRE_ROOT_CLR_MUX_A_MASK              (0x7000000U)
9614 #define CCM_PRE_ROOT_CLR_MUX_A_SHIFT             (24U)
9615 #define CCM_PRE_ROOT_CLR_MUX_A(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
9616 
9617 #define CCM_PRE_ROOT_CLR_EN_A_MASK               (0x10000000U)
9618 #define CCM_PRE_ROOT_CLR_EN_A_SHIFT              (28U)
9619 /*! EN_A
9620  *  0b0..Clock shutdown
9621  *  0b1..clock ON
9622  */
9623 #define CCM_PRE_ROOT_CLR_EN_A(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
9624 
9625 #define CCM_PRE_ROOT_CLR_BUSY4_MASK              (0x80000000U)
9626 #define CCM_PRE_ROOT_CLR_BUSY4_SHIFT             (31U)
9627 #define CCM_PRE_ROOT_CLR_BUSY4(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
9628 /*! @} */
9629 
9630 /* The count of CCM_PRE_ROOT_CLR */
9631 #define CCM_PRE_ROOT_CLR_COUNT                   (142U)
9632 
9633 /*! @name PRE_ROOT_TOG - Pre Divider Register */
9634 /*! @{ */
9635 
9636 #define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK         (0x7U)
9637 #define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT        (0U)
9638 /*! PRE_PODF_B
9639  *  0b000..Divide by 1
9640  *  0b001..Divide by 2
9641  *  0b010..Divide by 3
9642  *  0b011..Divide by 4
9643  *  0b100..Divide by 5
9644  *  0b101..Divide by 6
9645  *  0b110..Divide by 7
9646  *  0b111..Divide by 8
9647  */
9648 #define CCM_PRE_ROOT_TOG_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
9649 
9650 #define CCM_PRE_ROOT_TOG_BUSY0_MASK              (0x8U)
9651 #define CCM_PRE_ROOT_TOG_BUSY0_SHIFT             (3U)
9652 #define CCM_PRE_ROOT_TOG_BUSY0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
9653 
9654 #define CCM_PRE_ROOT_TOG_MUX_B_MASK              (0x700U)
9655 #define CCM_PRE_ROOT_TOG_MUX_B_SHIFT             (8U)
9656 #define CCM_PRE_ROOT_TOG_MUX_B(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
9657 
9658 #define CCM_PRE_ROOT_TOG_EN_B_MASK               (0x1000U)
9659 #define CCM_PRE_ROOT_TOG_EN_B_SHIFT              (12U)
9660 /*! EN_B
9661  *  0b0..Clock shutdown
9662  *  0b1..Clock ON
9663  */
9664 #define CCM_PRE_ROOT_TOG_EN_B(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
9665 
9666 #define CCM_PRE_ROOT_TOG_BUSY1_MASK              (0x8000U)
9667 #define CCM_PRE_ROOT_TOG_BUSY1_SHIFT             (15U)
9668 #define CCM_PRE_ROOT_TOG_BUSY1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
9669 
9670 #define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK         (0x70000U)
9671 #define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT        (16U)
9672 /*! PRE_PODF_A
9673  *  0b000..Divide by 1
9674  *  0b001..Divide by 2
9675  *  0b010..Divide by 3
9676  *  0b011..Divide by 4
9677  *  0b100..Divide by 5
9678  *  0b101..Divide by 6
9679  *  0b110..Divide by 7
9680  *  0b111..Divide by 8
9681  */
9682 #define CCM_PRE_ROOT_TOG_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
9683 
9684 #define CCM_PRE_ROOT_TOG_BUSY3_MASK              (0x80000U)
9685 #define CCM_PRE_ROOT_TOG_BUSY3_SHIFT             (19U)
9686 #define CCM_PRE_ROOT_TOG_BUSY3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
9687 
9688 #define CCM_PRE_ROOT_TOG_MUX_A_MASK              (0x7000000U)
9689 #define CCM_PRE_ROOT_TOG_MUX_A_SHIFT             (24U)
9690 #define CCM_PRE_ROOT_TOG_MUX_A(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
9691 
9692 #define CCM_PRE_ROOT_TOG_EN_A_MASK               (0x10000000U)
9693 #define CCM_PRE_ROOT_TOG_EN_A_SHIFT              (28U)
9694 /*! EN_A
9695  *  0b0..Clock shutdown
9696  *  0b1..clock ON
9697  */
9698 #define CCM_PRE_ROOT_TOG_EN_A(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
9699 
9700 #define CCM_PRE_ROOT_TOG_BUSY4_MASK              (0x80000000U)
9701 #define CCM_PRE_ROOT_TOG_BUSY4_SHIFT             (31U)
9702 #define CCM_PRE_ROOT_TOG_BUSY4(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
9703 /*! @} */
9704 
9705 /* The count of CCM_PRE_ROOT_TOG */
9706 #define CCM_PRE_ROOT_TOG_COUNT                   (142U)
9707 
9708 /*! @name ACCESS_CTRL - Access Control Register */
9709 /*! @{ */
9710 
9711 #define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK        (0xFU)
9712 #define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT       (0U)
9713 #define CCM_ACCESS_CTRL_DOMAIN0_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
9714 
9715 #define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK        (0xF0U)
9716 #define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT       (4U)
9717 #define CCM_ACCESS_CTRL_DOMAIN1_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
9718 
9719 #define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK        (0xF00U)
9720 #define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT       (8U)
9721 #define CCM_ACCESS_CTRL_DOMAIN2_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
9722 
9723 #define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK        (0xF000U)
9724 #define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT       (12U)
9725 #define CCM_ACCESS_CTRL_DOMAIN3_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
9726 
9727 #define CCM_ACCESS_CTRL_OWNER_ID_MASK            (0x30000U)
9728 #define CCM_ACCESS_CTRL_OWNER_ID_SHIFT           (16U)
9729 /*! OWNER_ID
9730  *  0b00..domaino
9731  *  0b01..domain1
9732  *  0b10..domain2
9733  *  0b11..domain3
9734  */
9735 #define CCM_ACCESS_CTRL_OWNER_ID(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
9736 
9737 #define CCM_ACCESS_CTRL_MUTEX_MASK               (0x100000U)
9738 #define CCM_ACCESS_CTRL_MUTEX_SHIFT              (20U)
9739 /*! MUTEX
9740  *  0b0..Semaphore is free to take
9741  *  0b1..Semaphore is taken
9742  */
9743 #define CCM_ACCESS_CTRL_MUTEX(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
9744 
9745 #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK   (0x1000000U)
9746 #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT  (24U)
9747 /*! DOMAIN0_WHITELIST
9748  *  0b0..Domain cannot change the setting
9749  *  0b1..Domain can change the setting
9750  */
9751 #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
9752 
9753 #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK   (0x2000000U)
9754 #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT  (25U)
9755 /*! DOMAIN1_WHITELIST
9756  *  0b0..Domain cannot change the setting
9757  *  0b1..Domain can change the setting
9758  */
9759 #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
9760 
9761 #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK   (0x4000000U)
9762 #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT  (26U)
9763 /*! DOMAIN2_WHITELIST
9764  *  0b0..Domain cannot change the setting
9765  *  0b1..Domain can change the setting
9766  */
9767 #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
9768 
9769 #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK   (0x8000000U)
9770 #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT  (27U)
9771 /*! DOMAIN3_WHITELIST
9772  *  0b0..Domain cannot change the setting
9773  *  0b1..Domain can change the setting
9774  */
9775 #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
9776 
9777 #define CCM_ACCESS_CTRL_SEMA_EN_MASK             (0x10000000U)
9778 #define CCM_ACCESS_CTRL_SEMA_EN_SHIFT            (28U)
9779 /*! SEMA_EN
9780  *  0b0..Disable
9781  *  0b1..Enable
9782  */
9783 #define CCM_ACCESS_CTRL_SEMA_EN(x)               (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
9784 
9785 #define CCM_ACCESS_CTRL_LOCK_MASK                (0x80000000U)
9786 #define CCM_ACCESS_CTRL_LOCK_SHIFT               (31U)
9787 /*! LOCK
9788  *  0b0..Access control inactive
9789  *  0b1..Access control active
9790  */
9791 #define CCM_ACCESS_CTRL_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
9792 /*! @} */
9793 
9794 /* The count of CCM_ACCESS_CTRL */
9795 #define CCM_ACCESS_CTRL_COUNT                    (142U)
9796 
9797 /*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
9798 /*! @{ */
9799 
9800 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
9801 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
9802 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
9803 
9804 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
9805 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
9806 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
9807 
9808 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
9809 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
9810 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
9811 
9812 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
9813 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
9814 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
9815 
9816 #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK   (0x30000U)
9817 #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT  (16U)
9818 /*! OWNER_ID
9819  *  0b00..domaino
9820  *  0b01..domain1
9821  *  0b10..domain2
9822  *  0b11..domain3
9823  */
9824 #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
9825 
9826 #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK      (0x100000U)
9827 #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT     (20U)
9828 /*! MUTEX
9829  *  0b0..Semaphore is free to take
9830  *  0b1..Semaphore is taken
9831  */
9832 #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
9833 
9834 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
9835 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
9836 /*! DOMAIN0_WHITELIST
9837  *  0b0..Domain cannot change the setting
9838  *  0b1..Domain can change the setting
9839  */
9840 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
9841 
9842 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
9843 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
9844 /*! DOMAIN1_WHITELIST
9845  *  0b0..Domain cannot change the setting
9846  *  0b1..Domain can change the setting
9847  */
9848 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
9849 
9850 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
9851 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
9852 /*! DOMAIN2_WHITELIST
9853  *  0b0..Domain cannot change the setting
9854  *  0b1..Domain can change the setting
9855  */
9856 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
9857 
9858 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
9859 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
9860 /*! DOMAIN3_WHITELIST
9861  *  0b0..Domain cannot change the setting
9862  *  0b1..Domain can change the setting
9863  */
9864 #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
9865 
9866 #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK    (0x10000000U)
9867 #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT   (28U)
9868 /*! SEMA_EN
9869  *  0b0..Disable
9870  *  0b1..Enable
9871  */
9872 #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
9873 
9874 #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK       (0x80000000U)
9875 #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT      (31U)
9876 /*! LOCK
9877  *  0b0..Access control inactive
9878  *  0b1..Access control active
9879  */
9880 #define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
9881 /*! @} */
9882 
9883 /* The count of CCM_ACCESS_CTRL_ROOT_SET */
9884 #define CCM_ACCESS_CTRL_ROOT_SET_COUNT           (142U)
9885 
9886 /*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
9887 /*! @{ */
9888 
9889 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
9890 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
9891 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
9892 
9893 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
9894 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
9895 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
9896 
9897 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
9898 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
9899 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
9900 
9901 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
9902 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
9903 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
9904 
9905 #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK   (0x30000U)
9906 #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT  (16U)
9907 /*! OWNER_ID
9908  *  0b00..domaino
9909  *  0b01..domain1
9910  *  0b10..domain2
9911  *  0b11..domain3
9912  */
9913 #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
9914 
9915 #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK      (0x100000U)
9916 #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT     (20U)
9917 /*! MUTEX
9918  *  0b0..Semaphore is free to take
9919  *  0b1..Semaphore is taken
9920  */
9921 #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
9922 
9923 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
9924 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
9925 /*! DOMAIN0_WHITELIST
9926  *  0b0..Domain cannot change the setting
9927  *  0b1..Domain can change the setting
9928  */
9929 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
9930 
9931 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
9932 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
9933 /*! DOMAIN1_WHITELIST
9934  *  0b0..Domain cannot change the setting
9935  *  0b1..Domain can change the setting
9936  */
9937 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
9938 
9939 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
9940 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
9941 /*! DOMAIN2_WHITELIST
9942  *  0b0..Domain cannot change the setting
9943  *  0b1..Domain can change the setting
9944  */
9945 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
9946 
9947 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
9948 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
9949 /*! DOMAIN3_WHITELIST
9950  *  0b0..Domain cannot change the setting
9951  *  0b1..Domain can change the setting
9952  */
9953 #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
9954 
9955 #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK    (0x10000000U)
9956 #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT   (28U)
9957 /*! SEMA_EN
9958  *  0b0..Disable
9959  *  0b1..Enable
9960  */
9961 #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
9962 
9963 #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK       (0x80000000U)
9964 #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT      (31U)
9965 /*! LOCK
9966  *  0b0..Access control inactive
9967  *  0b1..Access control active
9968  */
9969 #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
9970 /*! @} */
9971 
9972 /* The count of CCM_ACCESS_CTRL_ROOT_CLR */
9973 #define CCM_ACCESS_CTRL_ROOT_CLR_COUNT           (142U)
9974 
9975 /*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
9976 /*! @{ */
9977 
9978 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
9979 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
9980 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
9981 
9982 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
9983 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
9984 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
9985 
9986 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
9987 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
9988 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
9989 
9990 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
9991 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
9992 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
9993 
9994 #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK   (0x30000U)
9995 #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT  (16U)
9996 /*! OWNER_ID
9997  *  0b00..domaino
9998  *  0b01..domain1
9999  *  0b10..domain2
10000  *  0b11..domain3
10001  */
10002 #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
10003 
10004 #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK      (0x100000U)
10005 #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT     (20U)
10006 /*! MUTEX
10007  *  0b0..Semaphore is free to take
10008  *  0b1..Semaphore is taken
10009  */
10010 #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
10011 
10012 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
10013 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
10014 /*! DOMAIN0_WHITELIST
10015  *  0b0..Domain cannot change the setting
10016  *  0b1..Domain can change the setting
10017  */
10018 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
10019 
10020 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
10021 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
10022 /*! DOMAIN1_WHITELIST
10023  *  0b0..Domain cannot change the setting
10024  *  0b1..Domain can change the setting
10025  */
10026 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
10027 
10028 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
10029 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
10030 /*! DOMAIN2_WHITELIST
10031  *  0b0..Domain cannot change the setting
10032  *  0b1..Domain can change the setting
10033  */
10034 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
10035 
10036 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
10037 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
10038 /*! DOMAIN3_WHITELIST
10039  *  0b0..Domain cannot change the setting
10040  *  0b1..Domain can change the setting
10041  */
10042 #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
10043 
10044 #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK    (0x10000000U)
10045 #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT   (28U)
10046 /*! SEMA_EN
10047  *  0b0..Disable
10048  *  0b1..Enable
10049  */
10050 #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
10051 
10052 #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK       (0x80000000U)
10053 #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT      (31U)
10054 /*! LOCK
10055  *  0b0..Access control inactive
10056  *  0b1..Access control active
10057  */
10058 #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
10059 /*! @} */
10060 
10061 /* The count of CCM_ACCESS_CTRL_ROOT_TOG */
10062 #define CCM_ACCESS_CTRL_ROOT_TOG_COUNT           (142U)
10063 
10064 
10065 /*!
10066  * @}
10067  */ /* end of group CCM_Register_Masks */
10068 
10069 
10070 /* CCM - Peripheral instance base addresses */
10071 /** Peripheral CCM base address */
10072 #define CCM_BASE                                 (0x30380000u)
10073 /** Peripheral CCM base pointer */
10074 #define CCM                                      ((CCM_Type *)CCM_BASE)
10075 /** Array initializer of CCM peripheral base addresses */
10076 #define CCM_BASE_ADDRS                           { CCM_BASE }
10077 /** Array initializer of CCM peripheral base pointers */
10078 #define CCM_BASE_PTRS                            { CCM }
10079 /** Interrupt vectors for the CCM peripheral type */
10080 #define CCM_IRQS                                 { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn }
10081 
10082 /*!
10083  * @}
10084  */ /* end of group CCM_Peripheral_Access_Layer */
10085 
10086 
10087 /* ----------------------------------------------------------------------------
10088    -- CCM_ANALOG Peripheral Access Layer
10089    ---------------------------------------------------------------------------- */
10090 
10091 /*!
10092  * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
10093  * @{
10094  */
10095 
10096 /** CCM_ANALOG - Register Layout Typedef */
10097 typedef struct {
10098   __IO uint32_t AUDIO_PLL1_GEN_CTRL;               /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */
10099   __IO uint32_t AUDIO_PLL1_FDIV_CTL0;              /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */
10100   __IO uint32_t AUDIO_PLL1_FDIV_CTL1;              /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */
10101   __IO uint32_t AUDIO_PLL1_SSCG_CTRL;              /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */
10102   __IO uint32_t AUDIO_PLL1_MNIT_CTRL;              /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */
10103   __IO uint32_t AUDIO_PLL2_GEN_CTRL;               /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */
10104   __IO uint32_t AUDIO_PLL2_FDIV_CTL0;              /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */
10105   __IO uint32_t AUDIO_PLL2_FDIV_CTL1;              /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */
10106   __IO uint32_t AUDIO_PLL2_SSCG_CTRL;              /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */
10107   __IO uint32_t AUDIO_PLL2_MNIT_CTRL;              /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */
10108   __IO uint32_t VIDEO_PLL1_GEN_CTRL;               /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */
10109   __IO uint32_t VIDEO_PLL1_FDIV_CTL0;              /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */
10110   __IO uint32_t VIDEO_PLL1_FDIV_CTL1;              /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */
10111   __IO uint32_t VIDEO_PLL1_SSCG_CTRL;              /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */
10112   __IO uint32_t VIDEO_PLL1_MNIT_CTRL;              /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */
10113        uint8_t RESERVED_0[20];
10114   __IO uint32_t DRAM_PLL_GEN_CTRL;                 /**< DRAM PLL General Function Control Register, offset: 0x50 */
10115   __IO uint32_t DRAM_PLL_FDIV_CTL0;                /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */
10116   __IO uint32_t DRAM_PLL_FDIV_CTL1;                /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */
10117   __IO uint32_t DRAM_PLL_SSCG_CTRL;                /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */
10118   __IO uint32_t DRAM_PLL_MNIT_CTRL;                /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */
10119   __IO uint32_t GPU_PLL_GEN_CTRL;                  /**< GPU PLL General Function Control Register, offset: 0x64 */
10120   __IO uint32_t GPU_PLL_FDIV_CTL0;                 /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */
10121   __IO uint32_t GPU_PLL_LOCKD_CTRL;                /**< PLL Lock Detector Control Register, offset: 0x6C */
10122   __IO uint32_t GPU_PLL_MNIT_CTRL;                 /**< PLL Monitoring Control Register, offset: 0x70 */
10123   __IO uint32_t VPU_PLL_GEN_CTRL;                  /**< VPU PLL General Function Control Register, offset: 0x74 */
10124   __IO uint32_t VPU_PLL_FDIV_CTL0;                 /**< VPU PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */
10125   __IO uint32_t VPU_PLL_LOCKD_CTRL;                /**< PLL Lock Detector Control Register, offset: 0x7C */
10126   __IO uint32_t VPU_PLL_MNIT_CTRL;                 /**< PLL Monitoring Control Register, offset: 0x80 */
10127   __IO uint32_t ARM_PLL_GEN_CTRL;                  /**< ARM PLL General Function Control Register, offset: 0x84 */
10128   __IO uint32_t ARM_PLL_FDIV_CTL0;                 /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */
10129   __IO uint32_t ARM_PLL_LOCKD_CTRL;                /**< PLL Lock Detector Control Register, offset: 0x8C */
10130   __IO uint32_t ARM_PLL_MNIT_CTRL;                 /**< PLL Monitoring Control Register, offset: 0x90 */
10131   __IO uint32_t SYS_PLL1_GEN_CTRL;                 /**< SYS PLL1 General Function Control Register, offset: 0x94 */
10132   __IO uint32_t SYS_PLL1_FDIV_CTL0;                /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */
10133   __IO uint32_t SYS_PLL1_LOCKD_CTRL;               /**< PLL Lock Detector Control Register, offset: 0x9C */
10134        uint8_t RESERVED_1[96];
10135   __IO uint32_t SYS_PLL1_MNIT_CTRL;                /**< PLL Monitoring Control Register, offset: 0x100 */
10136   __IO uint32_t SYS_PLL2_GEN_CTRL;                 /**< SYS PLL2 General Function Control Register, offset: 0x104 */
10137   __IO uint32_t SYS_PLL2_FDIV_CTL0;                /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */
10138   __IO uint32_t SYS_PLL2_LOCKD_CTRL;               /**< PLL Lock Detector Control Register, offset: 0x10C */
10139   __IO uint32_t SYS_PLL2_MNIT_CTRL;                /**< PLL Monitoring Control Register, offset: 0x110 */
10140   __IO uint32_t SYS_PLL3_GEN_CTRL;                 /**< SYS PLL3 General Function Control Register, offset: 0x114 */
10141   __IO uint32_t SYS_PLL3_FDIV_CTL0;                /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */
10142   __IO uint32_t SYS_PLL3_LOCKD_CTRL;               /**< PLL Lock Detector Control Register, offset: 0x11C */
10143   __IO uint32_t SYS_PLL3_MNIT_CTRL;                /**< PLL Monitoring Control Register, offset: 0x120 */
10144   __IO uint32_t OSC_MISC_CFG;                      /**< Osc Misc Configuration Register, offset: 0x124 */
10145   __IO uint32_t ANAMIX_PLL_MNIT_CTL;               /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */
10146        uint8_t RESERVED_2[1748];
10147   __I  uint32_t DIGPROG;                           /**< DIGPROG Register, offset: 0x800 */
10148 } CCM_ANALOG_Type;
10149 
10150 /* ----------------------------------------------------------------------------
10151    -- CCM_ANALOG Register Masks
10152    ---------------------------------------------------------------------------- */
10153 
10154 /*!
10155  * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
10156  * @{
10157  */
10158 
10159 /*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
10160 /*! @{ */
10161 
10162 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
10163 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
10164 /*! PLL_REF_CLK_SEL
10165  *  0b00..24M_REF_CLK
10166  *  0b01..PAD_CLK
10167  *  0b10..Reserved
10168  *  0b11..Reserved
10169  */
10170 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
10171 
10172 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
10173 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
10174 /*! PAD_CLK_SEL
10175  *  0b00..CLKIN1 XOR CLKIN2
10176  *  0b01..CLKIN2
10177  *  0b10..CLKIN1
10178  *  0b11..Reserved
10179  */
10180 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
10181 
10182 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
10183 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
10184 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
10185 
10186 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
10187 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
10188 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
10189 
10190 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
10191 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
10192 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK)
10193 
10194 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
10195 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
10196 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
10197 
10198 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
10199 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
10200 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
10201 
10202 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
10203 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
10204 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
10205 
10206 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
10207 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
10208 #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
10209 /*! @} */
10210 
10211 /*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
10212 /*! @{ */
10213 
10214 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
10215 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
10216 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
10217 
10218 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
10219 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
10220 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
10221 
10222 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
10223 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
10224 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
10225 /*! @} */
10226 
10227 /*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
10228 /*! @{ */
10229 
10230 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
10231 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
10232 #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
10233 /*! @} */
10234 
10235 /*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
10236 /*! @{ */
10237 
10238 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
10239 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
10240 /*! SEL_PF
10241  *  0b00..Down spread
10242  *  0b01..Up spread
10243  *  0b1x..Center spread
10244  */
10245 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK)
10246 
10247 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
10248 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
10249 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
10250 
10251 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
10252 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
10253 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
10254 
10255 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
10256 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
10257 /*! SSCG_EN
10258  *  0b1..Enable Spread Spectrum Mode
10259  *  0b0..Disable Spread Spectrum Mode
10260  */
10261 #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
10262 /*! @} */
10263 
10264 /*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
10265 /*! @{ */
10266 
10267 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
10268 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
10269 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK)
10270 
10271 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
10272 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
10273 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK)
10274 
10275 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
10276 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
10277 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK)
10278 
10279 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
10280 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
10281 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK)
10282 
10283 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
10284 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
10285 /*! FSEL
10286  *  0b0..FEED_OUT = FREF
10287  *  0b1..FEED_OUT = FEED
10288  */
10289 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK)
10290 
10291 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
10292 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
10293 /*! AFCINIT_SEL
10294  *  0b0..nominal delay
10295  *  0b1..nominal delay * 2
10296  */
10297 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
10298 
10299 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
10300 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
10301 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
10302 
10303 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
10304 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
10305 /*! PBIAS_CTRL
10306  *  0b0..0.50*VDD
10307  *  0b1..0.67*VDD
10308  */
10309 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
10310 
10311 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
10312 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
10313 #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
10314 /*! @} */
10315 
10316 /*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
10317 /*! @{ */
10318 
10319 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
10320 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
10321 /*! PLL_REF_CLK_SEL
10322  *  0b00..24M_REF_CLK
10323  *  0b01..PAD_CLK
10324  *  0b10..Reserved
10325  *  0b11..Reserved
10326  */
10327 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
10328 
10329 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
10330 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
10331 /*! PAD_CLK_SEL
10332  *  0b00..CLKIN1 XOR CLKIN2
10333  *  0b01..CLKIN2
10334  *  0b10..CLKIN1
10335  *  0b11..Reserved
10336  */
10337 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
10338 
10339 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
10340 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
10341 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
10342 
10343 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
10344 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
10345 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
10346 
10347 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
10348 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
10349 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK)
10350 
10351 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
10352 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
10353 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
10354 
10355 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
10356 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U)
10357 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK)
10358 
10359 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
10360 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
10361 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
10362 
10363 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
10364 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
10365 #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK)
10366 /*! @} */
10367 
10368 /*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
10369 /*! @{ */
10370 
10371 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
10372 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
10373 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
10374 
10375 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
10376 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
10377 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
10378 
10379 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
10380 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
10381 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
10382 /*! @} */
10383 
10384 /*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
10385 /*! @{ */
10386 
10387 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
10388 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U)
10389 #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK)
10390 /*! @} */
10391 
10392 /*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
10393 /*! @{ */
10394 
10395 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U)
10396 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U)
10397 /*! SEL_PF
10398  *  0b00..Down spread
10399  *  0b01..Up spread
10400  *  0b1x..Center spread
10401  */
10402 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK)
10403 
10404 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
10405 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
10406 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK)
10407 
10408 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
10409 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
10410 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
10411 
10412 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
10413 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U)
10414 /*! SSCG_EN
10415  *  0b1..Enable Spread Spectrum Mode
10416  *  0b0..Disable Spread Spectrum Mode
10417  */
10418 #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK)
10419 /*! @} */
10420 
10421 /*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
10422 /*! @{ */
10423 
10424 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U)
10425 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
10426 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK)
10427 
10428 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U)
10429 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U)
10430 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK)
10431 
10432 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
10433 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U)
10434 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK)
10435 
10436 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U)
10437 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U)
10438 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK)
10439 
10440 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U)
10441 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U)
10442 /*! FSEL
10443  *  0b0..FEED_OUT = FREF
10444  *  0b1..FEED_OUT = FEED
10445  */
10446 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK)
10447 
10448 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
10449 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
10450 /*! AFCINIT_SEL
10451  *  0b0..nominal delay
10452  *  0b1..nominal delay * 2
10453  */
10454 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
10455 
10456 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
10457 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
10458 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
10459 
10460 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
10461 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
10462 /*! PBIAS_CTRL
10463  *  0b0..0.50*VDD
10464  *  0b1..0.67*VDD
10465  */
10466 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
10467 
10468 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
10469 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U)
10470 #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK)
10471 /*! @} */
10472 
10473 /*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
10474 /*! @{ */
10475 
10476 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
10477 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
10478 /*! PLL_REF_CLK_SEL
10479  *  0b00..24M_REF_CLK
10480  *  0b01..PAD_CLK
10481  *  0b10..Reserved
10482  *  0b11..Reserved
10483  */
10484 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
10485 
10486 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
10487 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
10488 /*! PAD_CLK_SEL
10489  *  0b00..CLKIN1 XOR CLKIN2
10490  *  0b01..CLKIN2
10491  *  0b10..CLKIN1
10492  *  0b11..Reserved
10493  */
10494 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
10495 
10496 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
10497 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
10498 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
10499 
10500 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
10501 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
10502 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
10503 
10504 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
10505 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
10506 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK)
10507 
10508 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
10509 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
10510 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
10511 
10512 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
10513 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
10514 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
10515 
10516 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
10517 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
10518 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
10519 
10520 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
10521 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
10522 #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
10523 /*! @} */
10524 
10525 /*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
10526 /*! @{ */
10527 
10528 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
10529 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
10530 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
10531 
10532 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
10533 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
10534 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
10535 
10536 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
10537 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
10538 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
10539 /*! @} */
10540 
10541 /*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
10542 /*! @{ */
10543 
10544 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
10545 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
10546 #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
10547 /*! @} */
10548 
10549 /*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
10550 /*! @{ */
10551 
10552 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
10553 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
10554 /*! SEL_PF
10555  *  0b00..Down spread
10556  *  0b01..Up spread
10557  *  0b1x..Center spread
10558  */
10559 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK)
10560 
10561 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
10562 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
10563 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
10564 
10565 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
10566 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
10567 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
10568 
10569 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
10570 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
10571 /*! SSCG_EN
10572  *  0b1..Enable Spread Spectrum Mode
10573  *  0b0..Disable Spread Spectrum Mode
10574  */
10575 #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
10576 /*! @} */
10577 
10578 /*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
10579 /*! @{ */
10580 
10581 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
10582 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
10583 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK)
10584 
10585 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
10586 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
10587 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK)
10588 
10589 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
10590 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
10591 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK)
10592 
10593 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
10594 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
10595 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK)
10596 
10597 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
10598 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
10599 /*! FSEL
10600  *  0b0..FEED_OUT = FREF
10601  *  0b1..FEED_OUT = FEED
10602  */
10603 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK)
10604 
10605 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
10606 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
10607 /*! AFCINIT_SEL
10608  *  0b0..nominal delay
10609  *  0b1..nominal delay * 2
10610  */
10611 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
10612 
10613 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
10614 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
10615 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
10616 
10617 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
10618 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
10619 /*! PBIAS_CTRL
10620  *  0b0..0.50*VDD
10621  *  0b1..0.67*VDD
10622  */
10623 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
10624 
10625 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
10626 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
10627 #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
10628 /*! @} */
10629 
10630 /*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
10631 /*! @{ */
10632 
10633 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
10634 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
10635 /*! PLL_REF_CLK_SEL
10636  *  0b00..24M_REF_CLK
10637  *  0b01..PAD_CLK
10638  *  0b10..Reserved
10639  *  0b11..Reserved
10640  */
10641 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
10642 
10643 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
10644 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
10645 /*! PAD_CLK_SEL
10646  *  0b00..CLKIN1 XOR CLKIN2
10647  *  0b01..CLKIN2
10648  *  0b10..CLKIN1
10649  *  0b11..Reserved
10650  */
10651 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
10652 
10653 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
10654 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
10655 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
10656 
10657 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
10658 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
10659 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
10660 
10661 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
10662 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
10663 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK)
10664 
10665 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
10666 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
10667 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
10668 
10669 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
10670 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U)
10671 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK)
10672 
10673 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
10674 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
10675 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
10676 
10677 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
10678 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
10679 #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK)
10680 /*! @} */
10681 
10682 /*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
10683 /*! @{ */
10684 
10685 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
10686 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
10687 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
10688 
10689 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
10690 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
10691 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
10692 
10693 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
10694 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
10695 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
10696 /*! @} */
10697 
10698 /*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
10699 /*! @{ */
10700 
10701 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
10702 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U)
10703 #define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK)
10704 /*! @} */
10705 
10706 /*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
10707 /*! @{ */
10708 
10709 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U)
10710 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U)
10711 /*! SEL_PF
10712  *  0b00..Down spread
10713  *  0b01..Up spread
10714  *  0b1x..Center spread
10715  */
10716 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK)
10717 
10718 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
10719 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
10720 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK)
10721 
10722 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
10723 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
10724 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
10725 
10726 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
10727 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U)
10728 /*! SSCG_EN
10729  *  0b1..Enable Spread Spectrum Mode
10730  *  0b0..Disable Spread Spectrum Mode
10731  */
10732 #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK)
10733 /*! @} */
10734 
10735 /*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
10736 /*! @{ */
10737 
10738 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK   (0x7U)
10739 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT  (0U)
10740 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK)
10741 
10742 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U)
10743 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U)
10744 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK)
10745 
10746 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
10747 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U)
10748 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK)
10749 
10750 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U)
10751 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U)
10752 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK)
10753 
10754 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK  (0x8000U)
10755 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U)
10756 /*! FSEL
10757  *  0b0..FEED_OUT = FREF
10758  *  0b1..FEED_OUT = FEED
10759  */
10760 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK)
10761 
10762 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
10763 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
10764 /*! AFCINIT_SEL
10765  *  0b0..nominal delay
10766  *  0b1..nominal delay * 2
10767  */
10768 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
10769 
10770 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
10771 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
10772 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
10773 
10774 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
10775 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
10776 /*! PBIAS_CTRL
10777  *  0b0..0.50*VDD
10778  *  0b1..0.67*VDD
10779  */
10780 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
10781 
10782 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
10783 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U)
10784 #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK)
10785 /*! @} */
10786 
10787 /*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
10788 /*! @{ */
10789 
10790 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
10791 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
10792 /*! PLL_REF_CLK_SEL
10793  *  0b00..24M_REF_CLK
10794  *  0b01..PAD_CLK
10795  *  0b10..Reserved
10796  *  0b11..Reserved
10797  */
10798 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
10799 
10800 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
10801 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
10802 /*! PAD_CLK_SEL
10803  *  0b00..CLKIN1 XOR CLKIN2
10804  *  0b01..CLKIN2
10805  *  0b10..CLKIN1
10806  *  0b11..Reserved
10807  */
10808 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
10809 
10810 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
10811 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
10812 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
10813 
10814 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
10815 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
10816 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
10817 
10818 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
10819 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
10820 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK)
10821 
10822 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
10823 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
10824 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
10825 
10826 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
10827 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
10828 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
10829 
10830 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
10831 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
10832 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
10833 
10834 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
10835 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
10836 /*! PLL_LOCK_SEL
10837  *  0b0..Using PLL maximum lock time
10838  *  0b1..Using PLL output lock
10839  */
10840 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
10841 
10842 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
10843 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
10844 #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
10845 /*! @} */
10846 
10847 /*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
10848 /*! @{ */
10849 
10850 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
10851 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
10852 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
10853 
10854 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
10855 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
10856 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
10857 
10858 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
10859 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
10860 #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
10861 /*! @} */
10862 
10863 /*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
10864 /*! @{ */
10865 
10866 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
10867 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
10868 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
10869 
10870 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
10871 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
10872 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
10873 
10874 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
10875 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
10876 #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
10877 /*! @} */
10878 
10879 /*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
10880 /*! @{ */
10881 
10882 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK    (0x3U)
10883 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT   (0U)
10884 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK)
10885 
10886 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
10887 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
10888 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK)
10889 
10890 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
10891 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
10892 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK)
10893 
10894 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
10895 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
10896 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK)
10897 
10898 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK   (0x4000U)
10899 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT  (14U)
10900 /*! FSEL
10901  *  0b0..FEED_OUT = FREF
10902  *  0b1..FEED_OUT = FEED
10903  */
10904 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK)
10905 
10906 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
10907 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
10908 /*! AFCINIT_SEL
10909  *  0b0..nominal delay
10910  *  0b1..nominal delay * 2
10911  */
10912 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
10913 
10914 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
10915 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
10916 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
10917 
10918 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
10919 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
10920 /*! PBIAS_CTRL
10921  *  0b0..0.50*VDD
10922  *  0b1..0.67*VDD
10923  */
10924 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
10925 
10926 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
10927 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
10928 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
10929 
10930 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
10931 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
10932 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
10933 
10934 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
10935 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
10936 #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK)
10937 /*! @} */
10938 
10939 /*! @name VPU_PLL_GEN_CTRL - VPU PLL General Function Control Register */
10940 /*! @{ */
10941 
10942 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
10943 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
10944 /*! PLL_REF_CLK_SEL
10945  *  0b00..24M_REF_CLK
10946  *  0b01..PAD_CLK
10947  *  0b10..Reserved
10948  *  0b11..Reserved
10949  */
10950 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
10951 
10952 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
10953 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
10954 /*! PAD_CLK_SEL
10955  *  0b00..CLKIN1 XOR CLKIN2
10956  *  0b01..CLKIN2
10957  *  0b10..CLKIN1
10958  *  0b11..Reserved
10959  */
10960 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
10961 
10962 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
10963 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
10964 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
10965 
10966 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
10967 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
10968 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
10969 
10970 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
10971 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
10972 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK)
10973 
10974 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
10975 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
10976 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
10977 
10978 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
10979 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
10980 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
10981 
10982 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
10983 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
10984 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
10985 
10986 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
10987 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
10988 /*! PLL_LOCK_SEL
10989  *  0b0..Using PLL maximum lock time
10990  *  0b1..Using PLL output lock
10991  */
10992 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
10993 
10994 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
10995 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
10996 #define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
10997 /*! @} */
10998 
10999 /*! @name VPU_PLL_FDIV_CTL0 - VPU PLL Divide and Fraction Data Control 0 Register */
11000 /*! @{ */
11001 
11002 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
11003 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
11004 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
11005 
11006 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
11007 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
11008 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
11009 
11010 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
11011 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
11012 #define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
11013 /*! @} */
11014 
11015 /*! @name VPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
11016 /*! @{ */
11017 
11018 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
11019 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
11020 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
11021 
11022 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
11023 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
11024 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
11025 
11026 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
11027 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
11028 #define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
11029 /*! @} */
11030 
11031 /*! @name VPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
11032 /*! @{ */
11033 
11034 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK    (0x3U)
11035 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT   (0U)
11036 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK)
11037 
11038 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
11039 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
11040 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK)
11041 
11042 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
11043 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
11044 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK)
11045 
11046 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
11047 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
11048 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK)
11049 
11050 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK   (0x4000U)
11051 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT  (14U)
11052 /*! FSEL
11053  *  0b0..FEED_OUT = FREF
11054  *  0b1..FEED_OUT = FEED
11055  */
11056 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK)
11057 
11058 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
11059 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
11060 /*! AFCINIT_SEL
11061  *  0b0..nominal delay
11062  *  0b1..nominal delay * 2
11063  */
11064 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
11065 
11066 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
11067 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
11068 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
11069 
11070 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
11071 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
11072 /*! PBIAS_CTRL
11073  *  0b0..0.50*VDD
11074  *  0b1..0.67*VDD
11075  */
11076 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
11077 
11078 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
11079 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
11080 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
11081 
11082 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
11083 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
11084 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
11085 
11086 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
11087 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
11088 #define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK)
11089 /*! @} */
11090 
11091 /*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
11092 /*! @{ */
11093 
11094 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
11095 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
11096 /*! PLL_REF_CLK_SEL
11097  *  0b00..24M_REF_CLK
11098  *  0b01..PAD_CLK
11099  *  0b10..Reserved
11100  *  0b11..Reserved
11101  */
11102 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
11103 
11104 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
11105 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
11106 /*! PAD_CLK_SEL
11107  *  0b00..CLKIN1 XOR CLKIN2
11108  *  0b01..CLKIN2
11109  *  0b10..CLKIN1
11110  *  0b11..Reserved
11111  */
11112 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
11113 
11114 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
11115 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
11116 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
11117 
11118 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
11119 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
11120 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
11121 
11122 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
11123 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
11124 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK)
11125 
11126 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
11127 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
11128 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
11129 
11130 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
11131 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
11132 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK)
11133 
11134 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
11135 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
11136 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
11137 
11138 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
11139 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
11140 /*! PLL_LOCK_SEL
11141  *  0b0..Using PLL maximum lock time
11142  *  0b1..Using PLL output lock
11143  */
11144 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
11145 
11146 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
11147 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
11148 #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK)
11149 /*! @} */
11150 
11151 /*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
11152 /*! @{ */
11153 
11154 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
11155 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
11156 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
11157 
11158 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
11159 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
11160 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
11161 
11162 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
11163 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
11164 #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
11165 /*! @} */
11166 
11167 /*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
11168 /*! @{ */
11169 
11170 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
11171 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
11172 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
11173 
11174 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
11175 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
11176 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
11177 
11178 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
11179 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
11180 #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
11181 /*! @} */
11182 
11183 /*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
11184 /*! @{ */
11185 
11186 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK    (0x3U)
11187 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT   (0U)
11188 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK)
11189 
11190 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
11191 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
11192 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK)
11193 
11194 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
11195 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
11196 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK)
11197 
11198 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
11199 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
11200 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK)
11201 
11202 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK   (0x4000U)
11203 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT  (14U)
11204 /*! FSEL
11205  *  0b0..FEED_OUT = FREF
11206  *  0b1..FEED_OUT = FEED
11207  */
11208 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK)
11209 
11210 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
11211 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
11212 /*! AFCINIT_SEL
11213  *  0b0..nominal delay
11214  *  0b1..nominal delay * 2
11215  */
11216 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
11217 
11218 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
11219 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
11220 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
11221 
11222 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
11223 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
11224 /*! PBIAS_CTRL
11225  *  0b0..0.50*VDD
11226  *  0b1..0.67*VDD
11227  */
11228 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
11229 
11230 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
11231 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
11232 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK)
11233 
11234 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
11235 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
11236 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK)
11237 
11238 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
11239 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
11240 #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK)
11241 /*! @} */
11242 
11243 /*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
11244 /*! @{ */
11245 
11246 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
11247 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
11248 /*! PLL_REF_CLK_SEL
11249  *  0b00..24M_REF_CLK
11250  *  0b01..PAD_CLK
11251  *  0b10..Reserved
11252  *  0b11..Reserved
11253  */
11254 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
11255 
11256 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
11257 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
11258 /*! PAD_CLK_SEL
11259  *  0b00..CLKIN1 XOR CLKIN2
11260  *  0b01..CLKIN2
11261  *  0b10..CLKIN1
11262  *  0b11..Reserved
11263  */
11264 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
11265 
11266 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
11267 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
11268 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
11269 
11270 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
11271 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
11272 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
11273 
11274 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
11275 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
11276 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK)
11277 
11278 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
11279 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
11280 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
11281 
11282 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U)
11283 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U)
11284 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK)
11285 
11286 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
11287 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
11288 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
11289 
11290 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
11291 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
11292 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK)
11293 
11294 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
11295 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
11296 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
11297 
11298 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
11299 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
11300 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK)
11301 
11302 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
11303 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
11304 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
11305 
11306 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
11307 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
11308 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK)
11309 
11310 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
11311 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
11312 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
11313 
11314 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
11315 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
11316 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK)
11317 
11318 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
11319 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
11320 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
11321 
11322 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
11323 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
11324 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK)
11325 
11326 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
11327 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
11328 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
11329 
11330 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
11331 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
11332 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK)
11333 
11334 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
11335 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
11336 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
11337 
11338 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
11339 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
11340 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK)
11341 
11342 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
11343 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
11344 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
11345 
11346 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
11347 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
11348 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK)
11349 
11350 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
11351 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
11352 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
11353 
11354 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
11355 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
11356 /*! PLL_LOCK_SEL
11357  *  0b0..Using PLL maximum lock time
11358  *  0b1..Using PLL output lock
11359  */
11360 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK)
11361 
11362 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
11363 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
11364 #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK)
11365 /*! @} */
11366 
11367 /*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
11368 /*! @{ */
11369 
11370 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
11371 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
11372 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
11373 
11374 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
11375 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
11376 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
11377 
11378 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
11379 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
11380 #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
11381 /*! @} */
11382 
11383 /*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
11384 /*! @{ */
11385 
11386 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
11387 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
11388 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK)
11389 
11390 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
11391 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
11392 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK)
11393 
11394 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
11395 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
11396 #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK)
11397 /*! @} */
11398 
11399 /*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
11400 /*! @{ */
11401 
11402 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK   (0x3U)
11403 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT  (0U)
11404 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK)
11405 
11406 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U)
11407 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U)
11408 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK)
11409 
11410 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U)
11411 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U)
11412 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK)
11413 
11414 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U)
11415 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U)
11416 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK)
11417 
11418 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK  (0x4000U)
11419 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U)
11420 /*! FSEL
11421  *  0b0..FEED_OUT = FREF
11422  *  0b1..FEED_OUT = FEED
11423  */
11424 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK)
11425 
11426 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
11427 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
11428 /*! AFCINIT_SEL
11429  *  0b0..nominal delay
11430  *  0b1..nominal delay * 2
11431  */
11432 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
11433 
11434 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
11435 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
11436 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
11437 
11438 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
11439 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
11440 /*! PBIAS_CTRL
11441  *  0b0..0.50*VDD
11442  *  0b1..0.67*VDD
11443  */
11444 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
11445 
11446 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
11447 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U)
11448 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK)
11449 
11450 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
11451 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
11452 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK)
11453 
11454 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U)
11455 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U)
11456 #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK)
11457 /*! @} */
11458 
11459 /*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
11460 /*! @{ */
11461 
11462 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
11463 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
11464 /*! PLL_REF_CLK_SEL
11465  *  0b00..24M_REF_CLK
11466  *  0b01..PAD_CLK
11467  *  0b10..Reserved
11468  *  0b11..Reserved
11469  */
11470 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
11471 
11472 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
11473 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
11474 /*! PAD_CLK_SEL
11475  *  0b00..CLKIN1 XOR CLKIN2
11476  *  0b01..CLKIN2
11477  *  0b10..CLKIN1
11478  *  0b11..Reserved
11479  */
11480 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
11481 
11482 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
11483 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
11484 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
11485 
11486 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
11487 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
11488 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
11489 
11490 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
11491 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
11492 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK)
11493 
11494 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
11495 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
11496 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
11497 
11498 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U)
11499 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U)
11500 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK)
11501 
11502 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
11503 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
11504 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
11505 
11506 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
11507 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
11508 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK)
11509 
11510 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
11511 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
11512 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
11513 
11514 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
11515 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
11516 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK)
11517 
11518 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
11519 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
11520 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
11521 
11522 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
11523 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
11524 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK)
11525 
11526 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
11527 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
11528 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
11529 
11530 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
11531 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
11532 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK)
11533 
11534 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
11535 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
11536 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
11537 
11538 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
11539 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
11540 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK)
11541 
11542 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
11543 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
11544 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
11545 
11546 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
11547 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
11548 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK)
11549 
11550 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
11551 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
11552 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
11553 
11554 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
11555 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
11556 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK)
11557 
11558 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
11559 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
11560 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
11561 
11562 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
11563 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
11564 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK)
11565 
11566 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
11567 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
11568 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
11569 
11570 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
11571 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
11572 /*! PLL_LOCK_SEL
11573  *  0b0..Using PLL maximum lock time
11574  *  0b1..Using PLL output lock
11575  */
11576 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK)
11577 
11578 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
11579 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
11580 #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK)
11581 /*! @} */
11582 
11583 /*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
11584 /*! @{ */
11585 
11586 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
11587 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
11588 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
11589 
11590 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
11591 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
11592 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
11593 
11594 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
11595 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
11596 #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
11597 /*! @} */
11598 
11599 /*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
11600 /*! @{ */
11601 
11602 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
11603 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
11604 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK)
11605 
11606 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
11607 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
11608 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK)
11609 
11610 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
11611 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
11612 #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK)
11613 /*! @} */
11614 
11615 /*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
11616 /*! @{ */
11617 
11618 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK   (0x3U)
11619 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT  (0U)
11620 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK)
11621 
11622 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U)
11623 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U)
11624 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK)
11625 
11626 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U)
11627 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U)
11628 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK)
11629 
11630 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U)
11631 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U)
11632 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK)
11633 
11634 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK  (0x4000U)
11635 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U)
11636 /*! FSEL
11637  *  0b0..FEED_OUT = FREF
11638  *  0b1..FEED_OUT = FEED
11639  */
11640 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK)
11641 
11642 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
11643 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
11644 /*! AFCINIT_SEL
11645  *  0b0..nominal delay
11646  *  0b1..nominal delay * 2
11647  */
11648 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
11649 
11650 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
11651 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
11652 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
11653 
11654 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
11655 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
11656 /*! PBIAS_CTRL
11657  *  0b0..0.50*VDD
11658  *  0b1..0.67*VDD
11659  */
11660 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
11661 
11662 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
11663 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U)
11664 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK)
11665 
11666 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
11667 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
11668 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK)
11669 
11670 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U)
11671 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U)
11672 #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK)
11673 /*! @} */
11674 
11675 /*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
11676 /*! @{ */
11677 
11678 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
11679 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
11680 /*! PLL_REF_CLK_SEL
11681  *  0b00..24M_REF_CLK
11682  *  0b01..PAD_CLK
11683  *  0b10..Reserved
11684  *  0b11..Reserved
11685  */
11686 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
11687 
11688 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
11689 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
11690 /*! PAD_CLK_SEL
11691  *  0b00..CLKIN1 XOR CLKIN2
11692  *  0b01..CLKIN2
11693  *  0b10..CLKIN1
11694  *  0b11..Reserved
11695  */
11696 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK)
11697 
11698 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
11699 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
11700 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK)
11701 
11702 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
11703 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
11704 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
11705 
11706 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U)
11707 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U)
11708 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK)
11709 
11710 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
11711 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
11712 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
11713 
11714 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U)
11715 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U)
11716 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK)
11717 
11718 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
11719 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
11720 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK)
11721 
11722 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
11723 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
11724 /*! PLL_LOCK_SEL
11725  *  0b0..Using PLL maximum lock time
11726  *  0b1..Using PLL output lock
11727  */
11728 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK)
11729 
11730 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
11731 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U)
11732 #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK)
11733 /*! @} */
11734 
11735 /*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
11736 /*! @{ */
11737 
11738 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
11739 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
11740 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK)
11741 
11742 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
11743 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
11744 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK)
11745 
11746 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
11747 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
11748 #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK)
11749 /*! @} */
11750 
11751 /*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
11752 /*! @{ */
11753 
11754 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
11755 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
11756 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK)
11757 
11758 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
11759 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
11760 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK)
11761 
11762 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
11763 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
11764 #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK)
11765 /*! @} */
11766 
11767 /*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
11768 /*! @{ */
11769 
11770 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK   (0x3U)
11771 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT  (0U)
11772 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK)
11773 
11774 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U)
11775 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U)
11776 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK)
11777 
11778 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U)
11779 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U)
11780 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK)
11781 
11782 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U)
11783 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U)
11784 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK)
11785 
11786 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK  (0x4000U)
11787 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U)
11788 /*! FSEL
11789  *  0b0..FEED_OUT = FREF
11790  *  0b1..FEED_OUT = FEED
11791  */
11792 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK)
11793 
11794 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
11795 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
11796 /*! AFCINIT_SEL
11797  *  0b0..nominal delay
11798  *  0b1..nominal delay * 2
11799  */
11800 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK)
11801 
11802 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
11803 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
11804 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
11805 
11806 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
11807 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
11808 /*! PBIAS_CTRL
11809  *  0b0..0.50*VDD
11810  *  0b1..0.67*VDD
11811  */
11812 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK)
11813 
11814 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
11815 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT (19U)
11816 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK)
11817 
11818 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
11819 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
11820 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK)
11821 
11822 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK (0x200000U)
11823 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT (21U)
11824 #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK)
11825 /*! @} */
11826 
11827 /*! @name OSC_MISC_CFG - Osc Misc Configuration Register */
11828 /*! @{ */
11829 
11830 #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U)
11831 #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U)
11832 /*! OSC_32K_SEL
11833  *  0b0..Divided by 24M clock
11834  *  0b1..32K Oscillator
11835  */
11836 #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)
11837 /*! @} */
11838 
11839 /*! @name ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */
11840 /*! @{ */
11841 
11842 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK (0xFU)
11843 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT (0U)
11844 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK)
11845 
11846 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK (0xF0U)
11847 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT (4U)
11848 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK)
11849 
11850 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK (0x100U)
11851 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT (8U)
11852 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK)
11853 
11854 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK (0xF0000U)
11855 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT (16U)
11856 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK)
11857 
11858 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK (0xF00000U)
11859 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT (20U)
11860 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK)
11861 
11862 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK (0x1000000U)
11863 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT (24U)
11864 #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK)
11865 /*! @} */
11866 
11867 /*! @name DIGPROG - DIGPROG Register */
11868 /*! @{ */
11869 
11870 #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK    (0xFFU)
11871 #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT   (0U)
11872 #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK)
11873 
11874 #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)
11875 #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U)
11876 #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK)
11877 
11878 #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)
11879 #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U)
11880 #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK)
11881 /*! @} */
11882 
11883 
11884 /*!
11885  * @}
11886  */ /* end of group CCM_ANALOG_Register_Masks */
11887 
11888 
11889 /* CCM_ANALOG - Peripheral instance base addresses */
11890 /** Peripheral CCM_ANALOG base address */
11891 #define CCM_ANALOG_BASE                          (0x30360000u)
11892 /** Peripheral CCM_ANALOG base pointer */
11893 #define CCM_ANALOG                               ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
11894 /** Array initializer of CCM_ANALOG peripheral base addresses */
11895 #define CCM_ANALOG_BASE_ADDRS                    { CCM_ANALOG_BASE }
11896 /** Array initializer of CCM_ANALOG peripheral base pointers */
11897 #define CCM_ANALOG_BASE_PTRS                     { CCM_ANALOG }
11898 
11899 /*!
11900  * @}
11901  */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
11902 
11903 
11904 /* ----------------------------------------------------------------------------
11905    -- CEC Peripheral Access Layer
11906    ---------------------------------------------------------------------------- */
11907 
11908 /*!
11909  * @addtogroup CEC_Peripheral_Access_Layer CEC Peripheral Access Layer
11910  * @{
11911  */
11912 
11913 /** CEC - Register Layout Typedef */
11914 typedef struct {
11915   __IO uint8_t CEC_CTRL;                           /**< CEC Control Register This register handles the main control of the CEC initiator., offset: 0x0 */
11916        uint8_t RESERVED_0[1];
11917   __IO uint8_t CEC_MASK;                           /**< CEC Interrupt Mask Register This read/write register masks/unmasks the interrupt events., offset: 0x2 */
11918        uint8_t RESERVED_1[2];
11919   __IO uint8_t CEC_ADDR_L;                         /**< CEC Logical Address Register Low This register indicates the logical address(es) allocated to the CEC device., offset: 0x5 */
11920   __IO uint8_t CEC_ADDR_H;                         /**< CEC Logical Address Register High This register indicates the logical address(es) allocated to the CEC device., offset: 0x6 */
11921   __IO uint8_t CEC_TX_CNT;                         /**< CEC TX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the transmitter data buffer., offset: 0x7 */
11922   __I  uint8_t CEC_RX_CNT;                         /**< CEC RX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the receiver data buffer., offset: 0x8 */
11923        uint8_t RESERVED_2[39];
11924   __IO uint8_t CEC_LOCK;                           /**< CEC Buffer Lock Register, offset: 0x30 */
11925   __IO uint8_t CEC_WAKEUPCTRL;                     /**< CEC Wake-up Control Register After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC engine verifies the message opcode[7:0] against one of the previously defined values to generate the wake-up status: Wakeupstatus is 1 when: received opcode is 0x04 and opcode0x04en is 1 or received opcode is 0x0D and opcode0x0Den is 1 or received opcode is 0x41 and opcode0x41en is 1 or received opcode is 0x42 and opcode0x42en is 1 or received opcode is 0x44 and opcode0x44en is 1 or received opcode is 0x70 and opcode0x70en is 1 or received opcode is 0x82 and opcode0x82en is 1 or received opcode is 0x86 and opcode0x86en is 1 Wakeupstatus is 0 when none of the previous conditions are true., offset: 0x31 */
11926 } CEC_Type;
11927 
11928 /* ----------------------------------------------------------------------------
11929    -- CEC Register Masks
11930    ---------------------------------------------------------------------------- */
11931 
11932 /*!
11933  * @addtogroup CEC_Register_Masks CEC Register Masks
11934  * @{
11935  */
11936 
11937 /*! @name CEC_CTRL - CEC Control Register This register handles the main control of the CEC initiator. */
11938 /*! @{ */
11939 
11940 #define CEC_CEC_CTRL_SEND_MASK                   (0x1U)
11941 #define CEC_CEC_CTRL_SEND_SHIFT                  (0U)
11942 /*! send - - 1'b1: Set by software to trigger CEC sending a frame as an initiator. */
11943 #define CEC_CEC_CTRL_SEND(x)                     (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_SEND_SHIFT)) & CEC_CEC_CTRL_SEND_MASK)
11944 
11945 #define CEC_CEC_CTRL_FRAME_TYP_MASK              (0x6U)
11946 #define CEC_CEC_CTRL_FRAME_TYP_SHIFT             (1U)
11947 /*! frame_typ - - 2'b00: Signal Free Time = 3-bit periods. */
11948 #define CEC_CEC_CTRL_FRAME_TYP(x)                (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_FRAME_TYP_SHIFT)) & CEC_CEC_CTRL_FRAME_TYP_MASK)
11949 
11950 #define CEC_CEC_CTRL_BC_NACK_MASK                (0x8U)
11951 #define CEC_CEC_CTRL_BC_NACK_SHIFT               (3U)
11952 /*! bc_nack - - 1'b1: Set by software to NACK the received broadcast message. */
11953 #define CEC_CEC_CTRL_BC_NACK(x)                  (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_BC_NACK_SHIFT)) & CEC_CEC_CTRL_BC_NACK_MASK)
11954 
11955 #define CEC_CEC_CTRL_STANDBY_MASK                (0x10U)
11956 #define CEC_CEC_CTRL_STANDBY_SHIFT               (4U)
11957 /*! standby - - 1: CEC controller responds with a NACK to all messages and generates a wakeup status for opcode. */
11958 #define CEC_CEC_CTRL_STANDBY(x)                  (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_STANDBY_SHIFT)) & CEC_CEC_CTRL_STANDBY_MASK)
11959 
11960 #define CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_MASK (0x20U)
11961 #define CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_SHIFT (5U)
11962 /*! slowdrvsupport_disable - - 1: CEC controller supports IO drivers with risetime of up to 1 CEC clock period. */
11963 #define CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE(x)   (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_SHIFT)) & CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_MASK)
11964 /*! @} */
11965 
11966 /*! @name CEC_MASK - CEC Interrupt Mask Register This read/write register masks/unmasks the interrupt events. */
11967 /*! @{ */
11968 
11969 #define CEC_CEC_MASK_DONE_MASK                   (0x1U)
11970 #define CEC_CEC_MASK_DONE_SHIFT                  (0U)
11971 /*! done - The current transmission is successful (for initiator only) */
11972 #define CEC_CEC_MASK_DONE(x)                     (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_DONE_SHIFT)) & CEC_CEC_MASK_DONE_MASK)
11973 
11974 #define CEC_CEC_MASK_EOM_MASK                    (0x2U)
11975 #define CEC_CEC_MASK_EOM_SHIFT                   (1U)
11976 /*! eom - EOM is detected so that the received data is ready in the receiver data buffer (for follower only) */
11977 #define CEC_CEC_MASK_EOM(x)                      (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_EOM_SHIFT)) & CEC_CEC_MASK_EOM_MASK)
11978 
11979 #define CEC_CEC_MASK_NACK_MASK                   (0x4U)
11980 #define CEC_CEC_MASK_NACK_SHIFT                  (2U)
11981 /*! nack - A frame is not acknowledged in a directly addressed message. */
11982 #define CEC_CEC_MASK_NACK(x)                     (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_NACK_SHIFT)) & CEC_CEC_MASK_NACK_MASK)
11983 
11984 #define CEC_CEC_MASK_ARB_LOST_MASK               (0x8U)
11985 #define CEC_CEC_MASK_ARB_LOST_SHIFT              (3U)
11986 /*! arb_lost - The initiator losses the CEC line arbitration to a second initiator. */
11987 #define CEC_CEC_MASK_ARB_LOST(x)                 (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_ARB_LOST_SHIFT)) & CEC_CEC_MASK_ARB_LOST_MASK)
11988 
11989 #define CEC_CEC_MASK_ERROR_INITIATOR_MASK        (0x10U)
11990 #define CEC_CEC_MASK_ERROR_INITIATOR_SHIFT       (4U)
11991 /*! error_initiator - An error is detected on a CEC line (for initiator only). */
11992 #define CEC_CEC_MASK_ERROR_INITIATOR(x)          (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_ERROR_INITIATOR_SHIFT)) & CEC_CEC_MASK_ERROR_INITIATOR_MASK)
11993 
11994 #define CEC_CEC_MASK_ERROR_FLOW_MASK             (0x20U)
11995 #define CEC_CEC_MASK_ERROR_FLOW_SHIFT            (5U)
11996 /*! error_flow - An error is notified by a follower. */
11997 #define CEC_CEC_MASK_ERROR_FLOW(x)               (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_ERROR_FLOW_SHIFT)) & CEC_CEC_MASK_ERROR_FLOW_MASK)
11998 
11999 #define CEC_CEC_MASK_WAKEUP_MASK                 (0x40U)
12000 #define CEC_CEC_MASK_WAKEUP_SHIFT                (6U)
12001 /*! wakeup - Follower wake-up signal mask */
12002 #define CEC_CEC_MASK_WAKEUP(x)                   (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_WAKEUP_SHIFT)) & CEC_CEC_MASK_WAKEUP_MASK)
12003 /*! @} */
12004 
12005 /*! @name CEC_ADDR_L - CEC Logical Address Register Low This register indicates the logical address(es) allocated to the CEC device. */
12006 /*! @{ */
12007 
12008 #define CEC_CEC_ADDR_L_CEC_ADDR_L_0_MASK         (0x1U)
12009 #define CEC_CEC_ADDR_L_CEC_ADDR_L_0_SHIFT        (0U)
12010 /*! cec_addr_l_0 - Logical address 0 - Device TV */
12011 #define CEC_CEC_ADDR_L_CEC_ADDR_L_0(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_0_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_0_MASK)
12012 
12013 #define CEC_CEC_ADDR_L_CEC_ADDR_L_1_MASK         (0x2U)
12014 #define CEC_CEC_ADDR_L_CEC_ADDR_L_1_SHIFT        (1U)
12015 /*! cec_addr_l_1 - Logical address 1 - Recording Device 1 */
12016 #define CEC_CEC_ADDR_L_CEC_ADDR_L_1(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_1_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_1_MASK)
12017 
12018 #define CEC_CEC_ADDR_L_CEC_ADDR_L_2_MASK         (0x4U)
12019 #define CEC_CEC_ADDR_L_CEC_ADDR_L_2_SHIFT        (2U)
12020 /*! cec_addr_l_2 - Logical address 2 - Recording Device 2 */
12021 #define CEC_CEC_ADDR_L_CEC_ADDR_L_2(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_2_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_2_MASK)
12022 
12023 #define CEC_CEC_ADDR_L_CEC_ADDR_L_3_MASK         (0x8U)
12024 #define CEC_CEC_ADDR_L_CEC_ADDR_L_3_SHIFT        (3U)
12025 /*! cec_addr_l_3 - Logical address 3 - Tuner 1 */
12026 #define CEC_CEC_ADDR_L_CEC_ADDR_L_3(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_3_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_3_MASK)
12027 
12028 #define CEC_CEC_ADDR_L_CEC_ADDR_L_4_MASK         (0x10U)
12029 #define CEC_CEC_ADDR_L_CEC_ADDR_L_4_SHIFT        (4U)
12030 /*! cec_addr_l_4 - Logical address 4 - Playback Device 1 */
12031 #define CEC_CEC_ADDR_L_CEC_ADDR_L_4(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_4_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_4_MASK)
12032 
12033 #define CEC_CEC_ADDR_L_CEC_ADDR_L_5_MASK         (0x20U)
12034 #define CEC_CEC_ADDR_L_CEC_ADDR_L_5_SHIFT        (5U)
12035 /*! cec_addr_l_5 - Logical address 5 - Audio System */
12036 #define CEC_CEC_ADDR_L_CEC_ADDR_L_5(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_5_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_5_MASK)
12037 
12038 #define CEC_CEC_ADDR_L_CEC_ADDR_L_6_MASK         (0x40U)
12039 #define CEC_CEC_ADDR_L_CEC_ADDR_L_6_SHIFT        (6U)
12040 /*! cec_addr_l_6 - Logical address 6 - Tuner 2 */
12041 #define CEC_CEC_ADDR_L_CEC_ADDR_L_6(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_6_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_6_MASK)
12042 
12043 #define CEC_CEC_ADDR_L_CEC_ADDR_L_7_MASK         (0x80U)
12044 #define CEC_CEC_ADDR_L_CEC_ADDR_L_7_SHIFT        (7U)
12045 /*! cec_addr_l_7 - Logical address 7 - Tuner 3 */
12046 #define CEC_CEC_ADDR_L_CEC_ADDR_L_7(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_7_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_7_MASK)
12047 /*! @} */
12048 
12049 /*! @name CEC_ADDR_H - CEC Logical Address Register High This register indicates the logical address(es) allocated to the CEC device. */
12050 /*! @{ */
12051 
12052 #define CEC_CEC_ADDR_H_CEC_ADDR_H_0_MASK         (0x1U)
12053 #define CEC_CEC_ADDR_H_CEC_ADDR_H_0_SHIFT        (0U)
12054 /*! cec_addr_h_0 - Logical address 8 - Playback Device 2 */
12055 #define CEC_CEC_ADDR_H_CEC_ADDR_H_0(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_0_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_0_MASK)
12056 
12057 #define CEC_CEC_ADDR_H_CEC_ADDR_H_1_MASK         (0x2U)
12058 #define CEC_CEC_ADDR_H_CEC_ADDR_H_1_SHIFT        (1U)
12059 /*! cec_addr_h_1 - Logical address 9 - Playback Device 3 */
12060 #define CEC_CEC_ADDR_H_CEC_ADDR_H_1(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_1_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_1_MASK)
12061 
12062 #define CEC_CEC_ADDR_H_CEC_ADDR_H_2_MASK         (0x4U)
12063 #define CEC_CEC_ADDR_H_CEC_ADDR_H_2_SHIFT        (2U)
12064 /*! cec_addr_h_2 - Logical address 10 - Tuner 4 */
12065 #define CEC_CEC_ADDR_H_CEC_ADDR_H_2(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_2_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_2_MASK)
12066 
12067 #define CEC_CEC_ADDR_H_CEC_ADDR_H_3_MASK         (0x8U)
12068 #define CEC_CEC_ADDR_H_CEC_ADDR_H_3_SHIFT        (3U)
12069 /*! cec_addr_h_3 - Logical address 11 - Playback Device 3 */
12070 #define CEC_CEC_ADDR_H_CEC_ADDR_H_3(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_3_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_3_MASK)
12071 
12072 #define CEC_CEC_ADDR_H_CEC_ADDR_H_4_MASK         (0x10U)
12073 #define CEC_CEC_ADDR_H_CEC_ADDR_H_4_SHIFT        (4U)
12074 /*! cec_addr_h_4 - Logical address 12 - Reserved */
12075 #define CEC_CEC_ADDR_H_CEC_ADDR_H_4(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_4_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_4_MASK)
12076 
12077 #define CEC_CEC_ADDR_H_CEC_ADDR_H_5_MASK         (0x20U)
12078 #define CEC_CEC_ADDR_H_CEC_ADDR_H_5_SHIFT        (5U)
12079 /*! cec_addr_h_5 - Logical address 13 - Reserved */
12080 #define CEC_CEC_ADDR_H_CEC_ADDR_H_5(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_5_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_5_MASK)
12081 
12082 #define CEC_CEC_ADDR_H_CEC_ADDR_H_6_MASK         (0x40U)
12083 #define CEC_CEC_ADDR_H_CEC_ADDR_H_6_SHIFT        (6U)
12084 /*! cec_addr_h_6 - Logical address 14 - Free use */
12085 #define CEC_CEC_ADDR_H_CEC_ADDR_H_6(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_6_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_6_MASK)
12086 
12087 #define CEC_CEC_ADDR_H_CEC_ADDR_H_7_MASK         (0x80U)
12088 #define CEC_CEC_ADDR_H_CEC_ADDR_H_7_SHIFT        (7U)
12089 /*! cec_addr_h_7 - Logical address 15 - Unregistered (as initiator address), Broadcast (as destination address) */
12090 #define CEC_CEC_ADDR_H_CEC_ADDR_H_7(x)           (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_7_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_7_MASK)
12091 /*! @} */
12092 
12093 /*! @name CEC_TX_CNT - CEC TX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the transmitter data buffer. */
12094 /*! @{ */
12095 
12096 #define CEC_CEC_TX_CNT_CEC_TX_CNT_MASK           (0x1FU)
12097 #define CEC_CEC_TX_CNT_CEC_TX_CNT_SHIFT          (0U)
12098 /*! cec_tx_cnt - CEC Transmitter Counter register 5'd0: No data needs to be transmitted 5'd1: Frame size is 1 byte . */
12099 #define CEC_CEC_TX_CNT_CEC_TX_CNT(x)             (((uint8_t)(((uint8_t)(x)) << CEC_CEC_TX_CNT_CEC_TX_CNT_SHIFT)) & CEC_CEC_TX_CNT_CEC_TX_CNT_MASK)
12100 /*! @} */
12101 
12102 /*! @name CEC_RX_CNT - CEC RX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the receiver data buffer. */
12103 /*! @{ */
12104 
12105 #define CEC_CEC_RX_CNT_CEC_RX_CNT_MASK           (0x1FU)
12106 #define CEC_CEC_RX_CNT_CEC_RX_CNT_SHIFT          (0U)
12107 /*! cec_rx_cnt - CEC Receiver Counter register: 5'd0: No data received 5'd1: 1-byte data is received . */
12108 #define CEC_CEC_RX_CNT_CEC_RX_CNT(x)             (((uint8_t)(((uint8_t)(x)) << CEC_CEC_RX_CNT_CEC_RX_CNT_SHIFT)) & CEC_CEC_RX_CNT_CEC_RX_CNT_MASK)
12109 /*! @} */
12110 
12111 /*! @name CEC_LOCK - CEC Buffer Lock Register */
12112 /*! @{ */
12113 
12114 #define CEC_CEC_LOCK_LOCKED_BUFFER_MASK          (0x1U)
12115 #define CEC_CEC_LOCK_LOCKED_BUFFER_SHIFT         (0U)
12116 /*! locked_buffer - When a frame is received, this bit would be active. */
12117 #define CEC_CEC_LOCK_LOCKED_BUFFER(x)            (((uint8_t)(((uint8_t)(x)) << CEC_CEC_LOCK_LOCKED_BUFFER_SHIFT)) & CEC_CEC_LOCK_LOCKED_BUFFER_MASK)
12118 /*! @} */
12119 
12120 /*! @name CEC_WAKEUPCTRL - CEC Wake-up Control Register After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC engine verifies the message opcode[7:0] against one of the previously defined values to generate the wake-up status: Wakeupstatus is 1 when: received opcode is 0x04 and opcode0x04en is 1 or received opcode is 0x0D and opcode0x0Den is 1 or received opcode is 0x41 and opcode0x41en is 1 or received opcode is 0x42 and opcode0x42en is 1 or received opcode is 0x44 and opcode0x44en is 1 or received opcode is 0x70 and opcode0x70en is 1 or received opcode is 0x82 and opcode0x82en is 1 or received opcode is 0x86 and opcode0x86en is 1 Wakeupstatus is 0 when none of the previous conditions are true. */
12121 /*! @{ */
12122 
12123 #define CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_MASK     (0x1U)
12124 #define CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_SHIFT    (0U)
12125 /*! opcode0x04en - OPCODE 0x04 wake up enable */
12126 #define CEC_CEC_WAKEUPCTRL_OPCODE0X04EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_MASK)
12127 
12128 #define CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_MASK     (0x2U)
12129 #define CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_SHIFT    (1U)
12130 /*! opcode0x0Den - OPCODE 0x0D wake up enable */
12131 #define CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_MASK)
12132 
12133 #define CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_MASK     (0x4U)
12134 #define CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_SHIFT    (2U)
12135 /*! opcode0x41en - OPCODE 0x41 wake up enable */
12136 #define CEC_CEC_WAKEUPCTRL_OPCODE0X41EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_MASK)
12137 
12138 #define CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_MASK     (0x8U)
12139 #define CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_SHIFT    (3U)
12140 /*! opcode0x42en - OPCODE 0x42 wake up enable */
12141 #define CEC_CEC_WAKEUPCTRL_OPCODE0X42EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_MASK)
12142 
12143 #define CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_MASK     (0x10U)
12144 #define CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_SHIFT    (4U)
12145 /*! opcode0x44en - OPCODE 0x44 wake up enable */
12146 #define CEC_CEC_WAKEUPCTRL_OPCODE0X44EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_MASK)
12147 
12148 #define CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_MASK     (0x20U)
12149 #define CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_SHIFT    (5U)
12150 /*! opcode0x70en - OPCODE 0x70 wake up enable */
12151 #define CEC_CEC_WAKEUPCTRL_OPCODE0X70EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_MASK)
12152 
12153 #define CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_MASK     (0x40U)
12154 #define CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_SHIFT    (6U)
12155 /*! opcode0x82en - OPCODE 0x82 wake up enable */
12156 #define CEC_CEC_WAKEUPCTRL_OPCODE0X82EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_MASK)
12157 
12158 #define CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_MASK     (0x80U)
12159 #define CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_SHIFT    (7U)
12160 /*! opcode0x86en - OPCODE 0x86 wake up enable */
12161 #define CEC_CEC_WAKEUPCTRL_OPCODE0X86EN(x)       (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_MASK)
12162 /*! @} */
12163 
12164 
12165 /*!
12166  * @}
12167  */ /* end of group CEC_Register_Masks */
12168 
12169 
12170 /* CEC - Peripheral instance base addresses */
12171 /** Peripheral CEC base address */
12172 #define CEC_BASE                                 (0x32FDFD00u)
12173 /** Peripheral CEC base pointer */
12174 #define CEC                                      ((CEC_Type *)CEC_BASE)
12175 /** Array initializer of CEC peripheral base addresses */
12176 #define CEC_BASE_ADDRS                           { CEC_BASE }
12177 /** Array initializer of CEC peripheral base pointers */
12178 #define CEC_BASE_PTRS                            { CEC }
12179 
12180 /*!
12181  * @}
12182  */ /* end of group CEC_Peripheral_Access_Layer */
12183 
12184 
12185 /* ----------------------------------------------------------------------------
12186    -- COLORSPACECONVERTER Peripheral Access Layer
12187    ---------------------------------------------------------------------------- */
12188 
12189 /*!
12190  * @addtogroup COLORSPACECONVERTER_Peripheral_Access_Layer COLORSPACECONVERTER Peripheral Access Layer
12191  * @{
12192  */
12193 
12194 /** COLORSPACECONVERTER - Register Layout Typedef */
12195 typedef struct {
12196   __IO uint8_t CSC_CFG;                            /**< Color Space Converter Interpolation and Decimation Configuration Register, offset: 0x0 */
12197   __IO uint8_t CSC_SCALE;                          /**< Color Space Converter Scale and Deep Color Configuration Register, offset: 0x1 */
12198   __IO uint8_t CSC_COEF_A1_MSB;                    /**< Color Space Converter Matrix A1 Coefficient Register MSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations., offset: 0x2 */
12199   __IO uint8_t CSC_COEF_A1_LSB;                    /**< Color Space Converter Matrix A1 Coefficient Register LSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations., offset: 0x3 */
12200   __IO uint8_t CSC_COEF_A2_MSB;                    /**< Color Space Converter Matrix A2 Coefficient Register MSB Color Space Conversion A2 coefficient., offset: 0x4 */
12201   __IO uint8_t CSC_COEF_A2_LSB;                    /**< Color Space Converter Matrix A2 Coefficient Register LSB Color Space Conversion A2 coefficient., offset: 0x5 */
12202   __IO uint8_t CSC_COEF_A3_MSB;                    /**< Color Space Converter Matrix A3 Coefficient Register MSB Color Space Conversion A3 coefficient., offset: 0x6 */
12203   __IO uint8_t CSC_COEF_A3_LSB;                    /**< Color Space Converter Matrix A3 Coefficient Register LSB Color Space Conversion A3 coefficient., offset: 0x7 */
12204   __IO uint8_t CSC_COEF_A4_MSB;                    /**< Color Space Converter Matrix A4 Coefficient Register MSB Color Space Conversion A4 coefficient., offset: 0x8 */
12205   __IO uint8_t CSC_COEF_A4_LSB;                    /**< Color Space Converter Matrix A4 Coefficient Register LSB Color Space Conversion A4 coefficient., offset: 0x9 */
12206   __IO uint8_t CSC_COEF_B1_MSB;                    /**< Color Space Converter Matrix B1 Coefficient Register MSB Color Space Conversion B1 coefficient., offset: 0xA */
12207   __IO uint8_t CSC_COEF_B1_LSB;                    /**< Color Space Converter Matrix B1 Coefficient Register LSB Color Space Conversion B1 coefficient., offset: 0xB */
12208   __IO uint8_t CSC_COEF_B2_MSB;                    /**< Color Space Converter Matrix B2 Coefficient Register MSB Color Space Conversion B2 coefficient., offset: 0xC */
12209   __IO uint8_t CSC_COEF_B2_LSB;                    /**< Color Space Converter Matrix B2 Coefficient Register LSB Color Space Conversion B2 coefficient., offset: 0xD */
12210   __IO uint8_t CSC_COEF_B3_MSB;                    /**< Color Space Converter Matrix B3 Coefficient Register MSB Color Space Conversion B3 coefficient., offset: 0xE */
12211   __IO uint8_t CSC_COEF_B3_LSB;                    /**< Color Space Converter Matrix B3 Coefficient Register LSB Color Space Conversion B3 coefficient., offset: 0xF */
12212   __IO uint8_t CSC_COEF_B4_MSB;                    /**< Color Space Converter Matrix B4 Coefficient Register MSB Color Space Conversion B4 coefficient., offset: 0x10 */
12213   __IO uint8_t CSC_COEF_B4_LSB;                    /**< Color Space Converter Matrix B4 Coefficient Register LSB Color Space Conversion B4 coefficient., offset: 0x11 */
12214   __IO uint8_t CSC_COEF_C1_MSB;                    /**< Color Space Converter Matrix C1 Coefficient Register MSB Color Space Conversion C1 coefficient., offset: 0x12 */
12215   __IO uint8_t CSC_COEF_C1_LSB;                    /**< Color Space Converter Matrix C1 Coefficient Register LSB Color Space Conversion C1 coefficient., offset: 0x13 */
12216   __IO uint8_t CSC_COEF_C2_MSB;                    /**< Color Space Converter Matrix C2 Coefficient Register MSB Color Space Conversion C2 coefficient., offset: 0x14 */
12217   __IO uint8_t CSC_COEF_C2_LSB;                    /**< Color Space Converter Matrix C2 Coefficient Register LSB Color Space Conversion C2 coefficient., offset: 0x15 */
12218   __IO uint8_t CSC_COEF_C3_MSB;                    /**< Color Space Converter Matrix C3 Coefficient Register MSB Color Space Conversion C3 coefficient., offset: 0x16 */
12219   __IO uint8_t CSC_COEF_C3_LSB;                    /**< Color Space Converter Matrix C3 Coefficient Register LSB Color Space Conversion C3 coefficient., offset: 0x17 */
12220   __IO uint8_t CSC_COEF_C4_MSB;                    /**< Color Space Converter Matrix C4 Coefficient Register MSB Color Space Conversion C4 coefficient., offset: 0x18 */
12221   __IO uint8_t CSC_COEF_C4_LSB;                    /**< Color Space Converter Matrix C4 Coefficient Register LSB Color Space Conversion C4 coefficient., offset: 0x19 */
12222   __IO uint8_t CSC_LIMIT_UP_MSB;                   /**< Color Space Converter Matrix Output Up Limit Register MSB For more details, refer to the HDMI 1., offset: 0x1A */
12223   __IO uint8_t CSC_LIMIT_UP_LSB;                   /**< Color Space Converter Matrix output Up Limit Register LSB For more details, refer to the HDMI 1., offset: 0x1B */
12224   __IO uint8_t CSC_LIMIT_DN_MSB;                   /**< Color Space Converter Matrix output Down Limit Register MSB For more details, refer to the HDMI 1., offset: 0x1C */
12225   __IO uint8_t CSC_LIMIT_DN_LSB;                   /**< Color Space Converter Matrix output Down Limit Register LSB For more details, refer to the HDMI 1., offset: 0x1D */
12226 } COLORSPACECONVERTER_Type;
12227 
12228 /* ----------------------------------------------------------------------------
12229    -- COLORSPACECONVERTER Register Masks
12230    ---------------------------------------------------------------------------- */
12231 
12232 /*!
12233  * @addtogroup COLORSPACECONVERTER_Register_Masks COLORSPACECONVERTER Register Masks
12234  * @{
12235  */
12236 
12237 /*! @name CSC_CFG - Color Space Converter Interpolation and Decimation Configuration Register */
12238 /*! @{ */
12239 
12240 #define COLORSPACECONVERTER_CSC_CFG_DECMODE_MASK (0x3U)
12241 #define COLORSPACECONVERTER_CSC_CFG_DECMODE_SHIFT (0U)
12242 /*! decmode - Chroma decimation configuration: decmode[1:0] | Chroma Decimation 00 | decimation
12243  *    disabled 01 | Hd (z) =1 10 | Hd(z)=1/ 4 + 1/2z^(-1 )+1/4 z^(-2) 11 | Hd(z)x2^(11)= -5+12z^(-2) -
12244  *    22z^(-4)+39z^(-8) +109z^(-10) -204z^(-12)+648z^(-14) + 1024z^(-15) +648z^(-16) -204z^(-18)
12245  *    +109z^(-20)- 65z^(-22) +39z^(-24) -22z^(-26) +12z^(-28)-5z^(-30)
12246  */
12247 #define COLORSPACECONVERTER_CSC_CFG_DECMODE(x)   (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_DECMODE_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_DECMODE_MASK)
12248 
12249 #define COLORSPACECONVERTER_CSC_CFG_SPARE_1_MASK (0xCU)
12250 #define COLORSPACECONVERTER_CSC_CFG_SPARE_1_SHIFT (2U)
12251 /*! spare_1 - Reserved as "spare" register with no associated functionality. */
12252 #define COLORSPACECONVERTER_CSC_CFG_SPARE_1(x)   (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_SPARE_1_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_SPARE_1_MASK)
12253 
12254 #define COLORSPACECONVERTER_CSC_CFG_INTMODE_MASK (0x30U)
12255 #define COLORSPACECONVERTER_CSC_CFG_INTMODE_SHIFT (4U)
12256 /*! intmode - Chroma interpolation configuration: intmode[1:0] | Chroma Interpolation 00 |
12257  *    interpolation disabled 01 | Hu (z) =1 + z^(-1) 10 | Hu(z)=1/ 2 + z^(-11)+1/2 z^(-2) 11 | interpolation
12258  *    disabled
12259  */
12260 #define COLORSPACECONVERTER_CSC_CFG_INTMODE(x)   (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_INTMODE_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_INTMODE_MASK)
12261 
12262 #define COLORSPACECONVERTER_CSC_CFG_SPARE_2_MASK (0x40U)
12263 #define COLORSPACECONVERTER_CSC_CFG_SPARE_2_SHIFT (6U)
12264 /*! spare_2 - Reserved as "spare" register with no associated functionality. */
12265 #define COLORSPACECONVERTER_CSC_CFG_SPARE_2(x)   (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_SPARE_2_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_SPARE_2_MASK)
12266 
12267 #define COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_MASK (0x80U)
12268 #define COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_SHIFT (7U)
12269 /*! csc_limit - When set (1'b1), the range limitation values defined in registers csc_mat_uplim and
12270  *    csc_mat_dnlim are applied to the output of the Color Space Conversion matrix.
12271  */
12272 #define COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_MASK)
12273 /*! @} */
12274 
12275 /*! @name CSC_SCALE - Color Space Converter Scale and Deep Color Configuration Register */
12276 /*! @{ */
12277 
12278 #define COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_MASK (0x3U)
12279 #define COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_SHIFT (0U)
12280 /*! cscscale - Defines the cscscale[1:0] scale factor to apply to all coefficients in Color Space Conversion. */
12281 #define COLORSPACECONVERTER_CSC_SCALE_CSCSCALE(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_SHIFT)) & COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_MASK)
12282 
12283 #define COLORSPACECONVERTER_CSC_SCALE_SPARE_MASK (0xCU)
12284 #define COLORSPACECONVERTER_CSC_SCALE_SPARE_SHIFT (2U)
12285 /*! spare - The is a Reserved as "spare" register with no associated functionality. */
12286 #define COLORSPACECONVERTER_CSC_SCALE_SPARE(x)   (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_SCALE_SPARE_SHIFT)) & COLORSPACECONVERTER_CSC_SCALE_SPARE_MASK)
12287 
12288 #define COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_MASK (0xF0U)
12289 #define COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_SHIFT (4U)
12290 /*! csc_color_depth - Color space converter color depth configuration: csc_colordepth[3:0] | Action
12291  *    0000 | 24 bit per pixel video (8 bit per component).
12292  */
12293 #define COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_SHIFT)) & COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_MASK)
12294 /*! @} */
12295 
12296 /*! @name CSC_COEF_A1_MSB - Color Space Converter Matrix A1 Coefficient Register MSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations. */
12297 /*! @{ */
12298 
12299 #define COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_MASK (0xFFU)
12300 #define COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_SHIFT (0U)
12301 /*! csc_coef_a1_msb - Color Space Converter Matrix A1 Coefficient Register MSB */
12302 #define COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_MASK)
12303 /*! @} */
12304 
12305 /*! @name CSC_COEF_A1_LSB - Color Space Converter Matrix A1 Coefficient Register LSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations. */
12306 /*! @{ */
12307 
12308 #define COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_MASK (0xFFU)
12309 #define COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_SHIFT (0U)
12310 /*! csc_coef_a1_lsb - Color Space Converter Matrix A1 Coefficient Register LSB */
12311 #define COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_MASK)
12312 /*! @} */
12313 
12314 /*! @name CSC_COEF_A2_MSB - Color Space Converter Matrix A2 Coefficient Register MSB Color Space Conversion A2 coefficient. */
12315 /*! @{ */
12316 
12317 #define COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_MASK (0xFFU)
12318 #define COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_SHIFT (0U)
12319 /*! csc_coef_a2_msb - Color Space Converter Matrix A2 Coefficient Register MSB */
12320 #define COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_MASK)
12321 /*! @} */
12322 
12323 /*! @name CSC_COEF_A2_LSB - Color Space Converter Matrix A2 Coefficient Register LSB Color Space Conversion A2 coefficient. */
12324 /*! @{ */
12325 
12326 #define COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_MASK (0xFFU)
12327 #define COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_SHIFT (0U)
12328 /*! csc_coef_a2_lsb - Color Space Converter Matrix A2 Coefficient Register LSB */
12329 #define COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_MASK)
12330 /*! @} */
12331 
12332 /*! @name CSC_COEF_A3_MSB - Color Space Converter Matrix A3 Coefficient Register MSB Color Space Conversion A3 coefficient. */
12333 /*! @{ */
12334 
12335 #define COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_MASK (0xFFU)
12336 #define COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_SHIFT (0U)
12337 /*! csc_coef_a3_msb - Color Space Converter Matrix A3 Coefficient Register MSB */
12338 #define COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_MASK)
12339 /*! @} */
12340 
12341 /*! @name CSC_COEF_A3_LSB - Color Space Converter Matrix A3 Coefficient Register LSB Color Space Conversion A3 coefficient. */
12342 /*! @{ */
12343 
12344 #define COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_MASK (0xFFU)
12345 #define COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_SHIFT (0U)
12346 /*! csc_coef_a3_lsb - Color Space Converter Matrix A3 Coefficient Register LSB */
12347 #define COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_MASK)
12348 /*! @} */
12349 
12350 /*! @name CSC_COEF_A4_MSB - Color Space Converter Matrix A4 Coefficient Register MSB Color Space Conversion A4 coefficient. */
12351 /*! @{ */
12352 
12353 #define COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_MASK (0xFFU)
12354 #define COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_SHIFT (0U)
12355 /*! csc_coef_a4_msb - Color Space Converter Matrix A4 Coefficient Register MSB */
12356 #define COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_MASK)
12357 /*! @} */
12358 
12359 /*! @name CSC_COEF_A4_LSB - Color Space Converter Matrix A4 Coefficient Register LSB Color Space Conversion A4 coefficient. */
12360 /*! @{ */
12361 
12362 #define COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_MASK (0xFFU)
12363 #define COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_SHIFT (0U)
12364 /*! csc_coef_a4_lsb - Color Space Converter Matrix A4 Coefficient Register LSB */
12365 #define COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_MASK)
12366 /*! @} */
12367 
12368 /*! @name CSC_COEF_B1_MSB - Color Space Converter Matrix B1 Coefficient Register MSB Color Space Conversion B1 coefficient. */
12369 /*! @{ */
12370 
12371 #define COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_MASK (0xFFU)
12372 #define COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_SHIFT (0U)
12373 /*! csc_coef_b1_msb - Color Space Converter Matrix B1 Coefficient Register MSB */
12374 #define COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_MASK)
12375 /*! @} */
12376 
12377 /*! @name CSC_COEF_B1_LSB - Color Space Converter Matrix B1 Coefficient Register LSB Color Space Conversion B1 coefficient. */
12378 /*! @{ */
12379 
12380 #define COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_MASK (0xFFU)
12381 #define COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_SHIFT (0U)
12382 /*! csc_coef_b1_lsb - Color Space Converter Matrix B1 Coefficient Register LSB */
12383 #define COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_MASK)
12384 /*! @} */
12385 
12386 /*! @name CSC_COEF_B2_MSB - Color Space Converter Matrix B2 Coefficient Register MSB Color Space Conversion B2 coefficient. */
12387 /*! @{ */
12388 
12389 #define COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_MASK (0xFFU)
12390 #define COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_SHIFT (0U)
12391 /*! csc_coef_b2_msb - Color Space Converter Matrix B2 Coefficient Register MSB */
12392 #define COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_MASK)
12393 /*! @} */
12394 
12395 /*! @name CSC_COEF_B2_LSB - Color Space Converter Matrix B2 Coefficient Register LSB Color Space Conversion B2 coefficient. */
12396 /*! @{ */
12397 
12398 #define COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_MASK (0xFFU)
12399 #define COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_SHIFT (0U)
12400 /*! csc_coef_b2_lsb - Color Space Converter Matrix B2 Coefficient Register LSB */
12401 #define COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_MASK)
12402 /*! @} */
12403 
12404 /*! @name CSC_COEF_B3_MSB - Color Space Converter Matrix B3 Coefficient Register MSB Color Space Conversion B3 coefficient. */
12405 /*! @{ */
12406 
12407 #define COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_MASK (0xFFU)
12408 #define COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_SHIFT (0U)
12409 /*! csc_coef_b3_msb - Color Space Converter Matrix B3 Coefficient Register MSB */
12410 #define COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_MASK)
12411 /*! @} */
12412 
12413 /*! @name CSC_COEF_B3_LSB - Color Space Converter Matrix B3 Coefficient Register LSB Color Space Conversion B3 coefficient. */
12414 /*! @{ */
12415 
12416 #define COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_MASK (0xFFU)
12417 #define COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_SHIFT (0U)
12418 /*! csc_coef_b3_lsb - Color Space Converter Matrix B3 Coefficient Register LSB */
12419 #define COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_MASK)
12420 /*! @} */
12421 
12422 /*! @name CSC_COEF_B4_MSB - Color Space Converter Matrix B4 Coefficient Register MSB Color Space Conversion B4 coefficient. */
12423 /*! @{ */
12424 
12425 #define COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_MASK (0xFFU)
12426 #define COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_SHIFT (0U)
12427 /*! csc_coef_b4_msb - Color Space Converter Matrix B4 Coefficient Register MSB */
12428 #define COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_MASK)
12429 /*! @} */
12430 
12431 /*! @name CSC_COEF_B4_LSB - Color Space Converter Matrix B4 Coefficient Register LSB Color Space Conversion B4 coefficient. */
12432 /*! @{ */
12433 
12434 #define COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_MASK (0xFFU)
12435 #define COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_SHIFT (0U)
12436 /*! csc_coef_b4_lsb - Color Space Converter Matrix B4 Coefficient Register LSB */
12437 #define COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_MASK)
12438 /*! @} */
12439 
12440 /*! @name CSC_COEF_C1_MSB - Color Space Converter Matrix C1 Coefficient Register MSB Color Space Conversion C1 coefficient. */
12441 /*! @{ */
12442 
12443 #define COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_MASK (0xFFU)
12444 #define COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_SHIFT (0U)
12445 /*! csc_coef_c1_msb - Color Space Converter Matrix C1 Coefficient Register MSB */
12446 #define COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_MASK)
12447 /*! @} */
12448 
12449 /*! @name CSC_COEF_C1_LSB - Color Space Converter Matrix C1 Coefficient Register LSB Color Space Conversion C1 coefficient. */
12450 /*! @{ */
12451 
12452 #define COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_MASK (0xFFU)
12453 #define COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_SHIFT (0U)
12454 /*! csc_coef_c1_lsb - Color Space Converter Matrix C1 Coefficient Register LSB */
12455 #define COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_MASK)
12456 /*! @} */
12457 
12458 /*! @name CSC_COEF_C2_MSB - Color Space Converter Matrix C2 Coefficient Register MSB Color Space Conversion C2 coefficient. */
12459 /*! @{ */
12460 
12461 #define COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_MASK (0xFFU)
12462 #define COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_SHIFT (0U)
12463 /*! csc_coef_c2_msb - Color Space Converter Matrix C2 Coefficient Register MSB */
12464 #define COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_MASK)
12465 /*! @} */
12466 
12467 /*! @name CSC_COEF_C2_LSB - Color Space Converter Matrix C2 Coefficient Register LSB Color Space Conversion C2 coefficient. */
12468 /*! @{ */
12469 
12470 #define COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_MASK (0xFFU)
12471 #define COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_SHIFT (0U)
12472 /*! csc_coef_c2_lsb - Color Space Converter Matrix C2 Coefficient Register LSB */
12473 #define COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_MASK)
12474 /*! @} */
12475 
12476 /*! @name CSC_COEF_C3_MSB - Color Space Converter Matrix C3 Coefficient Register MSB Color Space Conversion C3 coefficient. */
12477 /*! @{ */
12478 
12479 #define COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_MASK (0xFFU)
12480 #define COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_SHIFT (0U)
12481 /*! csc_coef_c3_msb - Color Space Converter Matrix C3 Coefficient Register MSB */
12482 #define COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_MASK)
12483 /*! @} */
12484 
12485 /*! @name CSC_COEF_C3_LSB - Color Space Converter Matrix C3 Coefficient Register LSB Color Space Conversion C3 coefficient. */
12486 /*! @{ */
12487 
12488 #define COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_MASK (0xFFU)
12489 #define COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_SHIFT (0U)
12490 /*! csc_coef_c3_lsb - Color Space Converter Matrix C3 Coefficient Register LSB */
12491 #define COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_MASK)
12492 /*! @} */
12493 
12494 /*! @name CSC_COEF_C4_MSB - Color Space Converter Matrix C4 Coefficient Register MSB Color Space Conversion C4 coefficient. */
12495 /*! @{ */
12496 
12497 #define COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_MASK (0xFFU)
12498 #define COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_SHIFT (0U)
12499 /*! csc_coef_c4_msb - Color Space Converter Matrix C4 Coefficient Register MSB */
12500 #define COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_MASK)
12501 /*! @} */
12502 
12503 /*! @name CSC_COEF_C4_LSB - Color Space Converter Matrix C4 Coefficient Register LSB Color Space Conversion C4 coefficient. */
12504 /*! @{ */
12505 
12506 #define COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_MASK (0xFFU)
12507 #define COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_SHIFT (0U)
12508 /*! csc_coef_c4_lsb - Color Space Converter Matrix C4 Coefficient Register LSB */
12509 #define COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_MASK)
12510 /*! @} */
12511 
12512 /*! @name CSC_LIMIT_UP_MSB - Color Space Converter Matrix Output Up Limit Register MSB For more details, refer to the HDMI 1. */
12513 /*! @{ */
12514 
12515 #define COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_MASK (0xFFU)
12516 #define COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_SHIFT (0U)
12517 /*! csc_limit_up_msb - Color Space Converter Matrix Output Upper Limit Register MSB */
12518 #define COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_MASK)
12519 /*! @} */
12520 
12521 /*! @name CSC_LIMIT_UP_LSB - Color Space Converter Matrix output Up Limit Register LSB For more details, refer to the HDMI 1. */
12522 /*! @{ */
12523 
12524 #define COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_MASK (0xFFU)
12525 #define COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_SHIFT (0U)
12526 /*! csc_limit_up_lsb - Color Space Converter Matrix Output Upper Limit Register LSB */
12527 #define COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_MASK)
12528 /*! @} */
12529 
12530 /*! @name CSC_LIMIT_DN_MSB - Color Space Converter Matrix output Down Limit Register MSB For more details, refer to the HDMI 1. */
12531 /*! @{ */
12532 
12533 #define COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_MASK (0xFFU)
12534 #define COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_SHIFT (0U)
12535 /*! csc_limit_dn_msb - Color Space Converter Matrix output Down Limit Register MSB */
12536 #define COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_MASK)
12537 /*! @} */
12538 
12539 /*! @name CSC_LIMIT_DN_LSB - Color Space Converter Matrix output Down Limit Register LSB For more details, refer to the HDMI 1. */
12540 /*! @{ */
12541 
12542 #define COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_MASK (0xFFU)
12543 #define COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_SHIFT (0U)
12544 /*! csc_limit_dn_lsb - Color Space Converter Matrix Output Down Limit Register LSB */
12545 #define COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_MASK)
12546 /*! @} */
12547 
12548 
12549 /*!
12550  * @}
12551  */ /* end of group COLORSPACECONVERTER_Register_Masks */
12552 
12553 
12554 /* COLORSPACECONVERTER - Peripheral instance base addresses */
12555 /** Peripheral COLORSPACECONVERTER base address */
12556 #define COLORSPACECONVERTER_BASE                 (0x32FDC100u)
12557 /** Peripheral COLORSPACECONVERTER base pointer */
12558 #define COLORSPACECONVERTER                      ((COLORSPACECONVERTER_Type *)COLORSPACECONVERTER_BASE)
12559 /** Array initializer of COLORSPACECONVERTER peripheral base addresses */
12560 #define COLORSPACECONVERTER_BASE_ADDRS           { COLORSPACECONVERTER_BASE }
12561 /** Array initializer of COLORSPACECONVERTER peripheral base pointers */
12562 #define COLORSPACECONVERTER_BASE_PTRS            { COLORSPACECONVERTER }
12563 
12564 /*!
12565  * @}
12566  */ /* end of group COLORSPACECONVERTER_Peripheral_Access_Layer */
12567 
12568 
12569 /* ----------------------------------------------------------------------------
12570    -- DDRC Peripheral Access Layer
12571    ---------------------------------------------------------------------------- */
12572 
12573 /*!
12574  * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
12575  * @{
12576  */
12577 
12578 /** DDRC - Register Layout Typedef */
12579 typedef struct {
12580   __IO uint32_t MSTR;                              /**< Master Register0, offset: 0x0 */
12581   __I  uint32_t STAT;                              /**< Operating Mode Status Register, offset: 0x4 */
12582   __IO uint32_t MSTR1;                             /**< Operating Mode Status Register, offset: 0x8 */
12583   __IO uint32_t MRCTRL3;                           /**< Operating Mode Status Register, offset: 0xC */
12584   __IO uint32_t MRCTRL0;                           /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
12585   __IO uint32_t MRCTRL1;                           /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
12586   __I  uint32_t MRSTAT;                            /**< Mode Register Read/Write Status Register, offset: 0x18 */
12587   __IO uint32_t MRCTRL2;                           /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
12588   __IO uint32_t DERATEEN;                          /**< Temperature Derate Enable Register, offset: 0x20 */
12589   __IO uint32_t DERATEINT;                         /**< Temperature Derate Interval Register, offset: 0x24 */
12590        uint8_t RESERVED_0[8];
12591   __IO uint32_t PWRCTL;                            /**< Low Power Control Register, offset: 0x30 */
12592   __IO uint32_t PWRTMG;                            /**< Low Power Timing Register, offset: 0x34 */
12593   __IO uint32_t HWLPCTL;                           /**< Hardware Low Power Control Register, offset: 0x38 */
12594        uint8_t RESERVED_1[20];
12595   __IO uint32_t RFSHCTL0;                          /**< Refresh Control Register 0, offset: 0x50 */
12596   __IO uint32_t RFSHCTL1;                          /**< Refresh Control Register 1, offset: 0x54 */
12597        uint8_t RESERVED_2[8];
12598   __IO uint32_t RFSHCTL3;                          /**< Refresh Control Register 3, offset: 0x60 */
12599   __IO uint32_t RFSHTMG;                           /**< Refresh Timing Register, offset: 0x64 */
12600        uint8_t RESERVED_3[8];
12601   __IO uint32_t ECCCFG0;                           /**< ECC Configuration Register 0, offset: 0x70 */
12602   __IO uint32_t ECCCFG1;                           /**< ECC Configuration Register 1, offset: 0x74 */
12603        uint8_t RESERVED_4[88];
12604   __IO uint32_t INIT0;                             /**< SDRAM Initialization Register 0, offset: 0xD0 */
12605   __IO uint32_t INIT1;                             /**< SDRAM Initialization Register 1, offset: 0xD4 */
12606   __IO uint32_t INIT2;                             /**< SDRAM Initialization Register 2, offset: 0xD8 */
12607   __IO uint32_t INIT3;                             /**< SDRAM Initialization Register 3, offset: 0xDC */
12608   __IO uint32_t INIT4;                             /**< SDRAM Initialization Register 4, offset: 0xE0 */
12609   __IO uint32_t INIT5;                             /**< SDRAM Initialization Register 5, offset: 0xE4 */
12610   __IO uint32_t INIT6;                             /**< SDRAM Initialization Register 6, offset: 0xE8 */
12611   __IO uint32_t INIT7;                             /**< SDRAM Initialization Register 7, offset: 0xEC */
12612   __IO uint32_t DIMMCTL;                           /**< DIMM Control Register, offset: 0xF0 */
12613   __IO uint32_t RANKCTL;                           /**< Rank Control Register, offset: 0xF4 */
12614        uint8_t RESERVED_5[8];
12615   __IO uint32_t DRAMTMG0;                          /**< SDRAM Timing Register 0, offset: 0x100 */
12616   __IO uint32_t DRAMTMG1;                          /**< SDRAM Timing Register 1, offset: 0x104 */
12617   __IO uint32_t DRAMTMG2;                          /**< SDRAM Timing Register 2, offset: 0x108 */
12618   __IO uint32_t DRAMTMG3;                          /**< SDRAM Timing Register 3, offset: 0x10C */
12619   __IO uint32_t DRAMTMG4;                          /**< SDRAM Timing Register 4, offset: 0x110 */
12620   __IO uint32_t DRAMTMG5;                          /**< SDRAM Timing Register 5, offset: 0x114 */
12621   __IO uint32_t DRAMTMG6;                          /**< SDRAM Timing Register 6, offset: 0x118 */
12622   __IO uint32_t DRAMTMG7;                          /**< SDRAM Timing Register 7, offset: 0x11C */
12623   __IO uint32_t DRAMTMG8;                          /**< SDRAM Timing Register 8, offset: 0x120 */
12624   __IO uint32_t DRAMTMG9;                          /**< SDRAM Timing Register 9, offset: 0x124 */
12625   __IO uint32_t DRAMTMG10;                         /**< SDRAM Timing Register 10, offset: 0x128 */
12626   __IO uint32_t DRAMTMG11;                         /**< SDRAM Timing Register 11, offset: 0x12C */
12627   __IO uint32_t DRAMTMG12;                         /**< SDRAM Timing Register 12, offset: 0x130 */
12628   __IO uint32_t DRAMTMG13;                         /**< SDRAM Timing Register 13, offset: 0x134 */
12629   __IO uint32_t DRAMTMG14;                         /**< SDRAM Timing Register 14, offset: 0x138 */
12630   __IO uint32_t DRAMTMG15;                         /**< SDRAM Timing Register 15, offset: 0x13C */
12631        uint8_t RESERVED_6[64];
12632   __IO uint32_t ZQCTL0;                            /**< ZQ Control Register 0, offset: 0x180 */
12633   __IO uint32_t ZQCTL1;                            /**< ZQ Control Register 1, offset: 0x184 */
12634   __IO uint32_t ZQCTL2;                            /**< ZQ Control Register 2, offset: 0x188 */
12635   __I  uint32_t ZQSTAT;                            /**< ZQ Status Register, offset: 0x18C */
12636   __IO uint32_t DFITMG0;                           /**< DFI Timing Register 0, offset: 0x190 */
12637   __IO uint32_t DFITMG1;                           /**< DFI Timing Register 1, offset: 0x194 */
12638   __IO uint32_t DFILPCFG0;                         /**< DFI Low Power Configuration Register 0, offset: 0x198 */
12639   __IO uint32_t DFILPCFG1;                         /**< DFI Low Power Configuration Register 1, offset: 0x19C */
12640   __IO uint32_t DFIUPD0;                           /**< DFI Update Register 0, offset: 0x1A0 */
12641   __IO uint32_t DFIUPD1;                           /**< DFI Update Register 1, offset: 0x1A4 */
12642   __IO uint32_t DFIUPD2;                           /**< DFI Update Register 2, offset: 0x1A8 */
12643        uint8_t RESERVED_7[4];
12644   __IO uint32_t DFIMISC;                           /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
12645   __IO uint32_t DFITMG2;                           /**< DFI Timing Register 2, offset: 0x1B4 */
12646   __IO uint32_t DFITMG3;                           /**< DFI Timing Register 3, offset: 0x1B8 */
12647   __I  uint32_t DFISTAT;                           /**< DFI Status Register, offset: 0x1BC */
12648   __IO uint32_t DBICTL;                            /**< DM/DBI Control Register, offset: 0x1C0 */
12649        uint8_t RESERVED_8[60];
12650   __IO uint32_t ADDRMAP0;                          /**< Address Map Register 0, offset: 0x200 */
12651   __IO uint32_t ADDRMAP1;                          /**< Address Map Register 1, offset: 0x204 */
12652   __IO uint32_t ADDRMAP2;                          /**< Address Map Register 2, offset: 0x208 */
12653   __IO uint32_t ADDRMAP3;                          /**< Address Map Register 3, offset: 0x20C */
12654   __IO uint32_t ADDRMAP4;                          /**< Address Map Register 4, offset: 0x210 */
12655   __IO uint32_t ADDRMAP5;                          /**< Address Map Register 5, offset: 0x214 */
12656   __IO uint32_t ADDRMAP6;                          /**< Address Map Register 6, offset: 0x218 */
12657   __IO uint32_t ADDRMAP7;                          /**< Address Map Register 7, offset: 0x21C */
12658   __IO uint32_t ADDRMAP8;                          /**< Address Map Register 8, offset: 0x220 */
12659   __IO uint32_t ADDRMAP9;                          /**< Address Map Register 9, offset: 0x224 */
12660   __IO uint32_t ADDRMAP10;                         /**< Address Map Register 10, offset: 0x228 */
12661   __IO uint32_t ADDRMAP11;                         /**< Address Map Register 11, offset: 0x22C */
12662        uint8_t RESERVED_9[16];
12663   __IO uint32_t ODTCFG;                            /**< ODT Configuration Register, offset: 0x240 */
12664   __IO uint32_t ODTMAP;                            /**< ODT/Rank Map Register, offset: 0x244 */
12665        uint8_t RESERVED_10[8];
12666   __IO uint32_t SCHED;                             /**< Scheduler Control Register, offset: 0x250 */
12667   __IO uint32_t SCHED1;                            /**< Scheduler Control Register 1, offset: 0x254 */
12668        uint8_t RESERVED_11[4];
12669   __IO uint32_t PERFHPR1;                          /**< High Priority Read CAM Register 1, offset: 0x25C */
12670        uint8_t RESERVED_12[4];
12671   __IO uint32_t PERFLPR1;                          /**< Low Priority Read CAM Register 1, offset: 0x264 */
12672        uint8_t RESERVED_13[4];
12673   __IO uint32_t PERFWR1;                           /**< Write CAM Register 1, offset: 0x26C */
12674        uint8_t RESERVED_14[144];
12675   __IO uint32_t DBG0;                              /**< Debug Register 0, offset: 0x300 */
12676   __IO uint32_t DBG1;                              /**< Debug Register 1, offset: 0x304 */
12677   __I  uint32_t DBGCAM;                            /**< CAM Debug Register, offset: 0x308 */
12678   __IO uint32_t DBGCMD;                            /**< Command Debug Register, offset: 0x30C */
12679   __I  uint32_t DBGSTAT;                           /**< Status Debug Register, offset: 0x310 */
12680        uint8_t RESERVED_15[12];
12681   __IO uint32_t SWCTL;                             /**< Software Register Programming Control Enable, offset: 0x320 */
12682   __I  uint32_t SWSTAT;                            /**< Software Register Programming Control Status, offset: 0x324 */
12683        uint8_t RESERVED_16[68];
12684   __IO uint32_t POISONCFG;                         /**< AXI Poison Configuration Register., offset: 0x36C */
12685   __I  uint32_t POISONSTAT;                        /**< AXI Poison Status Register, offset: 0x370 */
12686        uint8_t RESERVED_17[136];
12687   __I  uint32_t PSTAT;                             /**< Port Status Register, offset: 0x3FC */
12688   __IO uint32_t PCCFG;                             /**< Port Common Configuration Register, offset: 0x400 */
12689   __IO uint32_t PCFGR_0;                           /**< Port n Configuration Read Register, offset: 0x404 */
12690   __IO uint32_t PCFGW_0;                           /**< Port n Configuration Write Register, offset: 0x408 */
12691        uint8_t RESERVED_18[132];
12692   __IO uint32_t PCTRL_0;                           /**< Port n Control Register, offset: 0x490 */
12693   __IO uint32_t PCFGQOS0_0;                        /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
12694   __IO uint32_t PCFGQOS1_0;                        /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
12695   __IO uint32_t PCFGWQOS0_0;                       /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
12696   __IO uint32_t PCFGWQOS1_0;                       /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
12697        uint8_t RESERVED_19[7036];
12698   __IO uint32_t DERATEEN_SHADOW;                   /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
12699   __IO uint32_t DERATEINT_SHADOW;                  /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
12700        uint8_t RESERVED_20[40];
12701   __IO uint32_t RFSHCTL0_SHADOW;                   /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
12702        uint8_t RESERVED_21[16];
12703   __IO uint32_t RFSHTMG_SHADOW;                    /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
12704        uint8_t RESERVED_22[116];
12705   __IO uint32_t INIT3_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
12706   __IO uint32_t INIT4_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
12707        uint8_t RESERVED_23[4];
12708   __IO uint32_t INIT6_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
12709   __IO uint32_t INIT7_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
12710        uint8_t RESERVED_24[16];
12711   __IO uint32_t DRAMTMG0_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
12712   __IO uint32_t DRAMTMG1_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
12713   __IO uint32_t DRAMTMG2_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
12714   __IO uint32_t DRAMTMG3_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
12715   __IO uint32_t DRAMTMG4_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
12716   __IO uint32_t DRAMTMG5_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
12717   __IO uint32_t DRAMTMG6_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
12718   __IO uint32_t DRAMTMG7_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
12719   __IO uint32_t DRAMTMG8_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
12720   __IO uint32_t DRAMTMG9_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
12721   __IO uint32_t DRAMTMG10_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
12722   __IO uint32_t DRAMTMG11_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
12723   __IO uint32_t DRAMTMG12_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
12724   __IO uint32_t DRAMTMG13_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
12725   __IO uint32_t DRAMTMG14_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
12726   __IO uint32_t DRAMTMG15_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
12727        uint8_t RESERVED_25[64];
12728   __IO uint32_t ZQCTL0_SHADOW;                     /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
12729        uint8_t RESERVED_26[12];
12730   __IO uint32_t DFITMG0_SHADOW;                    /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
12731   __IO uint32_t DFITMG1_SHADOW;                    /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
12732        uint8_t RESERVED_27[28];
12733   __IO uint32_t DFITMG2_SHADOW;                    /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
12734   __IO uint32_t DFITMG3_SHADOW;                    /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
12735        uint8_t RESERVED_28[132];
12736   __IO uint32_t ODTCFG_SHADOW;                     /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
12737 } DDRC_Type;
12738 
12739 /* ----------------------------------------------------------------------------
12740    -- DDRC Register Masks
12741    ---------------------------------------------------------------------------- */
12742 
12743 /*!
12744  * @addtogroup DDRC_Register_Masks DDRC Register Masks
12745  * @{
12746  */
12747 
12748 /*! @name MSTR - Master Register0 */
12749 /*! @{ */
12750 
12751 #define DDRC_MSTR_LPDDR2_MASK                    (0x4U)
12752 #define DDRC_MSTR_LPDDR2_SHIFT                   (2U)
12753 /*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use
12754  *    Present only in designs configured to support LPDDR2.
12755  */
12756 #define DDRC_MSTR_LPDDR2(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_LPDDR2_SHIFT)) & DDRC_MSTR_LPDDR2_MASK)
12757 
12758 #define DDRC_MSTR_LPDDR3_MASK                    (0x8U)
12759 #define DDRC_MSTR_LPDDR3_SHIFT                   (3U)
12760 /*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use
12761  *    Present only in designs configured to support LPDDR3.
12762  */
12763 #define DDRC_MSTR_LPDDR3(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_LPDDR3_SHIFT)) & DDRC_MSTR_LPDDR3_MASK)
12764 
12765 #define DDRC_MSTR_DDR4_MASK                      (0x10U)
12766 #define DDRC_MSTR_DDR4_SHIFT                     (4U)
12767 /*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present
12768  *    only in designs configured to support DDR4.
12769  */
12770 #define DDRC_MSTR_DDR4(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_DDR4_SHIFT)) & DDRC_MSTR_DDR4_MASK)
12771 
12772 #define DDRC_MSTR_LPDDR4_MASK                    (0x20U)
12773 #define DDRC_MSTR_LPDDR4_SHIFT                   (5U)
12774 /*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use
12775  *    Present only in designs configured to support LPDDR4.
12776  */
12777 #define DDRC_MSTR_LPDDR4(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_LPDDR4_SHIFT)) & DDRC_MSTR_LPDDR4_MASK)
12778 
12779 #define DDRC_MSTR_BURSTCHOP_MASK                 (0x200U)
12780 #define DDRC_MSTR_BURSTCHOP_SHIFT                (9U)
12781 /*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads
12782  *    is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode
12783  *    (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is
12784  *    exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled
12785  *    (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1),
12786  *    burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported.
12787  */
12788 #define DDRC_MSTR_BURSTCHOP(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_BURSTCHOP_SHIFT)) & DDRC_MSTR_BURSTCHOP_MASK)
12789 
12790 #define DDRC_MSTR_GEARDOWN_MODE_MASK             (0x800U)
12791 #define DDRC_MSTR_GEARDOWN_MODE_SHIFT            (11U)
12792 /*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in
12793  *    normal mode (1N). This register can be changed, only when the Controller is in self-refresh
12794  *    mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported
12795  *    if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported
12796  *    if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value
12797  *    is don't care
12798  */
12799 #define DDRC_MSTR_GEARDOWN_MODE(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_GEARDOWN_MODE_SHIFT)) & DDRC_MSTR_GEARDOWN_MODE_MASK)
12800 
12801 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK            (0x3000U)
12802 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT           (12U)
12803 /*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus
12804  *    width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 -
12805  *    Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a
12806  *    multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple
12807  *    of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus
12808  *    width (excluding any ECC width).
12809  */
12810 #define DDRC_MSTR_DATA_BUS_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT)) & DDRC_MSTR_DATA_BUS_WIDTH_MASK)
12811 
12812 #define DDRC_MSTR_BURST_RDWR_MASK                (0xF0000U)
12813 #define DDRC_MSTR_BURST_RDWR_SHIFT               (16U)
12814 /*! burst_rdwr - SDRAM burst length used
12815  *  0b0001..Burst length of 2 (only supported for mDDR)
12816  *  0b0010..Burst length of 4
12817  *  0b0100..Burst length of 8
12818  *  0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
12819  */
12820 #define DDRC_MSTR_BURST_RDWR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_BURST_RDWR_SHIFT)) & DDRC_MSTR_BURST_RDWR_MASK)
12821 
12822 #define DDRC_MSTR_ACTIVE_RANKS_MASK              (0x3000000U)
12823 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT             (24U)
12824 /*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For
12825  *    two-rank configurations, only bits[25:24] are present.
12826  */
12827 #define DDRC_MSTR_ACTIVE_RANKS(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ACTIVE_RANKS_SHIFT)) & DDRC_MSTR_ACTIVE_RANKS_MASK)
12828 
12829 #define DDRC_MSTR_FREQUENCY_MODE_MASK            (0x20000000U)
12830 #define DDRC_MSTR_FREQUENCY_MODE_SHIFT           (29U)
12831 /*! frequency_mode - Choose which registers are used.
12832  *  0b0..Original Registers
12833  *  0b1..Shadow Registers
12834  */
12835 #define DDRC_MSTR_FREQUENCY_MODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_FREQUENCY_MODE_SHIFT)) & DDRC_MSTR_FREQUENCY_MODE_MASK)
12836 
12837 #define DDRC_MSTR_DEVICE_CONFIG_MASK             (0xC0000000U)
12838 #define DDRC_MSTR_DEVICE_CONFIG_SHIFT            (30U)
12839 /*! device_config - Indicates the configuration of the device used in the system.
12840  *  0b00..x4 device
12841  *  0b01..x8 device
12842  *  0b10..x16 device
12843  *  0b11..x32 device
12844  */
12845 #define DDRC_MSTR_DEVICE_CONFIG(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_DEVICE_CONFIG_SHIFT)) & DDRC_MSTR_DEVICE_CONFIG_MASK)
12846 /*! @} */
12847 
12848 /*! @name STAT - Operating Mode Status Register */
12849 /*! @{ */
12850 
12851 #define DDRC_STAT_OPERATING_MODE_MASK            (0x7U)
12852 #define DDRC_STAT_OPERATING_MODE_SHIFT           (0U)
12853 /*! operating_mode - Operating mode */
12854 #define DDRC_STAT_OPERATING_MODE(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_OPERATING_MODE_SHIFT)) & DDRC_STAT_OPERATING_MODE_MASK)
12855 
12856 #define DDRC_STAT_SELFREF_TYPE_MASK              (0x30U)
12857 #define DDRC_STAT_SELFREF_TYPE_SHIFT             (4U)
12858 /*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
12859  *    it was under Automatic Self Refresh control only or not.
12860  *  0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
12861  *        CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
12862  *        in-progress.
12863  *  0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
12864  *        Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
12865  *  0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
12866  *        Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
12867  *        (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
12868  */
12869 #define DDRC_STAT_SELFREF_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_SELFREF_TYPE_SHIFT)) & DDRC_STAT_SELFREF_TYPE_MASK)
12870 
12871 #define DDRC_STAT_SELFREF_STATE_MASK             (0x300U)
12872 #define DDRC_STAT_SELFREF_STATE_SHIFT            (8U)
12873 /*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
12874  *    for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
12875  *  0b00..SDRAM is not in Self Refresh.
12876  *  0b01..Self refresh 1
12877  *  0b10..Self refresh power down
12878  *  0b11..Self refresh
12879  */
12880 #define DDRC_STAT_SELFREF_STATE(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_SELFREF_STATE_SHIFT)) & DDRC_STAT_SELFREF_STATE_MASK)
12881 /*! @} */
12882 
12883 /*! @name MSTR1 - Operating Mode Status Register */
12884 /*! @{ */
12885 
12886 #define DDRC_MSTR1_RANK_TMGREG_SEL_MASK          (0x3U)
12887 #define DDRC_MSTR1_RANK_TMGREG_SEL_SHIFT         (0U)
12888 /*! rank_tmgreg_sel - rank_tmgreg_sel
12889  *  0b00..USE DRAMTMGx registers for the rank
12890  *  0b01..USE MRAMTMGx registers for the rank
12891  */
12892 #define DDRC_MSTR1_RANK_TMGREG_SEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_RANK_TMGREG_SEL_SHIFT)) & DDRC_MSTR1_RANK_TMGREG_SEL_MASK)
12893 
12894 #define DDRC_MSTR1_ALT_ADDRMAP_EN_MASK           (0x10000U)
12895 #define DDRC_MSTR1_ALT_ADDRMAP_EN_SHIFT          (16U)
12896 /*! alt_addrmap_en - Enable Alternative Address Map
12897  *  0b0..Disable Alternative Address Map
12898  *  0b1..Enable Alternative Address Map
12899  */
12900 #define DDRC_MSTR1_ALT_ADDRMAP_EN(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_ALT_ADDRMAP_EN_SHIFT)) & DDRC_MSTR1_ALT_ADDRMAP_EN_MASK)
12901 /*! @} */
12902 
12903 /*! @name MRCTRL3 - Operating Mode Status Register */
12904 /*! @{ */
12905 
12906 #define DDRC_MRCTRL3_MR_RANK_SEL_MASK            (0x3U)
12907 #define DDRC_MRCTRL3_MR_RANK_SEL_SHIFT           (0U)
12908 /*! mr_rank_sel - mr_rank_sel */
12909 #define DDRC_MRCTRL3_MR_RANK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_MR_RANK_SEL_SHIFT)) & DDRC_MRCTRL3_MR_RANK_SEL_MASK)
12910 /*! @} */
12911 
12912 /*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
12913 /*! @{ */
12914 
12915 #define DDRC_MRCTRL0_MR_TYPE_MASK                (0x1U)
12916 #define DDRC_MRCTRL0_MR_TYPE_SHIFT               (0U)
12917 /*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
12918  *  0b0..Write
12919  *  0b1..Read
12920  */
12921 #define DDRC_MRCTRL0_MR_TYPE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_TYPE_SHIFT)) & DDRC_MRCTRL0_MR_TYPE_MASK)
12922 
12923 #define DDRC_MRCTRL0_MPR_EN_MASK                 (0x2U)
12924 #define DDRC_MRCTRL0_MPR_EN_SHIFT                (1U)
12925 /*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
12926  *  0b0..MRS
12927  *  0b1..WR/RD for MPR
12928  */
12929 #define DDRC_MRCTRL0_MPR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MPR_EN_SHIFT)) & DDRC_MRCTRL0_MPR_EN_MASK)
12930 
12931 #define DDRC_MRCTRL0_PDA_EN_MASK                 (0x4U)
12932 #define DDRC_MRCTRL0_PDA_EN_SHIFT                (2U)
12933 /*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
12934  *    pba_mode=1, PBA access is initiated instead of PDA access.
12935  *  0b0..MRS
12936  *  0b1..MRS in Per DRAM Addressability
12937  */
12938 #define DDRC_MRCTRL0_PDA_EN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_PDA_EN_SHIFT)) & DDRC_MRCTRL0_PDA_EN_MASK)
12939 
12940 #define DDRC_MRCTRL0_SW_INIT_INT_MASK            (0x8U)
12941 #define DDRC_MRCTRL0_SW_INIT_INT_SHIFT           (3U)
12942 /*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
12943  *    automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
12944  *    DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
12945  *    program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
12946  *    independent channel mode, note that this must be programmed to both channels beforehand. Note that
12947  *    this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
12948  *    initialization routine will not re-start.
12949  *  0b0..Software intervention is not allowed
12950  *  0b1..Software intervention is allowed
12951  */
12952 #define DDRC_MRCTRL0_SW_INIT_INT(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_SW_INIT_INT_SHIFT)) & DDRC_MRCTRL0_SW_INIT_INT_MASK)
12953 
12954 #define DDRC_MRCTRL0_MR_RANK_MASK                (0x30U)
12955 #define DDRC_MRCTRL0_MR_RANK_SHIFT               (4U)
12956 /*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access
12957  *    all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which
12958  *    implement address mirroring, it may be necessary to access ranks individually. Examples (assume
12959  *    DDRC is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 -
12960  *    select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3
12961  */
12962 #define DDRC_MRCTRL0_MR_RANK(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_RANK_SHIFT)) & DDRC_MRCTRL0_MR_RANK_MASK)
12963 
12964 #define DDRC_MRCTRL0_MR_ADDR_MASK                (0xF000U)
12965 #define DDRC_MRCTRL0_MR_ADDR_SHIFT               (12U)
12966 /*! mr_addr - Address of the mode register that is to be written to.
12967  *  0b0000..MR0
12968  *  0b0001..MR1
12969  *  0b0010..MR2
12970  *  0b0011..MR3
12971  *  0b0100..MR4
12972  *  0b0101..MR5
12973  *  0b0110..MR6
12974  *  0b0111..MR7
12975  */
12976 #define DDRC_MRCTRL0_MR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_ADDR_SHIFT)) & DDRC_MRCTRL0_MR_ADDR_MASK)
12977 
12978 #define DDRC_MRCTRL0_PBA_MODE_MASK               (0x40000000U)
12979 #define DDRC_MRCTRL0_PBA_MODE_SHIFT              (30U)
12980 /*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with
12981  *    setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability
12982  *    mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by
12983  *    MRSTAT.pda_done in the same way as PDA.
12984  */
12985 #define DDRC_MRCTRL0_PBA_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_PBA_MODE_SHIFT)) & DDRC_MRCTRL0_PBA_MODE_MASK)
12986 
12987 #define DDRC_MRCTRL0_MR_WR_MASK                  (0x80000000U)
12988 #define DDRC_MRCTRL0_MR_WR_SHIFT                 (31U)
12989 /*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When
12990  *    the MR operation is complete, the DDRC automatically clears this bit. The other register fields
12991  *    of this register must be written in a separate APB transaction, before setting this mr_wr bit.
12992  *    It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
12993  */
12994 #define DDRC_MRCTRL0_MR_WR(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_WR_SHIFT)) & DDRC_MRCTRL0_MR_WR_MASK)
12995 /*! @} */
12996 
12997 /*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
12998 /*! @{ */
12999 
13000 #define DDRC_MRCTRL1_MR_DATA_MASK                (0x3FFFFU)
13001 #define DDRC_MRCTRL1_MR_DATA_SHIFT               (0U)
13002 /*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For
13003  *    LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes,
13004  *    don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all
13005  *    other configurations.
13006  */
13007 #define DDRC_MRCTRL1_MR_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_MR_DATA_SHIFT)) & DDRC_MRCTRL1_MR_DATA_MASK)
13008 /*! @} */
13009 
13010 /*! @name MRSTAT - Mode Register Read/Write Status Register */
13011 /*! @{ */
13012 
13013 #define DDRC_MRSTAT_MR_WR_BUSY_MASK              (0x1U)
13014 #define DDRC_MRSTAT_MR_WR_BUSY_SHIFT             (0U)
13015 /*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
13016  *    signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
13017  *    MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
13018  *    'MRSTAT.mr_wr_busy' is high.
13019  *  0b0..Indicates that the SoC core can initiate a mode register write operation
13020  *  0b1..Indicates that mode register write operation is in progress
13021  */
13022 #define DDRC_MRSTAT_MR_WR_BUSY(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_MR_WR_BUSY_SHIFT)) & DDRC_MRSTAT_MR_WR_BUSY_MASK)
13023 
13024 #define DDRC_MRSTAT_PDA_DONE_MASK                (0x100U)
13025 #define DDRC_MRSTAT_PDA_DONE_SHIFT               (8U)
13026 /*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
13027  *    low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
13028  *    are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
13029  *    recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
13030  *    perform PDA operation next time
13031  *  0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
13032  *  0b1..Indicates that mode register write operation related to PDA/PBA has competed.
13033  */
13034 #define DDRC_MRSTAT_PDA_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_PDA_DONE_SHIFT)) & DDRC_MRSTAT_PDA_DONE_MASK)
13035 /*! @} */
13036 
13037 /*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
13038 /*! @{ */
13039 
13040 #define DDRC_MRCTRL2_MR_DEVICE_SEL_MASK          (0xFFFFFFFFU)
13041 #define DDRC_MRCTRL2_MR_DEVICE_SEL_SHIFT         (0U)
13042 /*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode.
13043  *    Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to
13044  *    Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied
13045  *    to that device. A '0' indicates that the MRS commands should be skipped for that device.
13046  */
13047 #define DDRC_MRCTRL2_MR_DEVICE_SEL(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_MR_DEVICE_SEL_SHIFT)) & DDRC_MRCTRL2_MR_DEVICE_SEL_MASK)
13048 /*! @} */
13049 
13050 /*! @name DERATEEN - Temperature Derate Enable Register */
13051 /*! @{ */
13052 
13053 #define DDRC_DERATEEN_DERATE_ENABLE_MASK         (0x1U)
13054 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT        (0U)
13055 /*! derate_enable - Enables derating. Present only in designs configured to support
13056  *    LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
13057  *  0b0..Timing parameter derating is disabled
13058  *  0b1..Timing parameter derating is enabled using MR4 read value.
13059  */
13060 #define DDRC_DERATEEN_DERATE_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_DERATE_ENABLE_SHIFT)) & DDRC_DERATEEN_DERATE_ENABLE_MASK)
13061 
13062 #define DDRC_DERATEEN_DERATE_VALUE_MASK          (0x2U)
13063 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT         (1U)
13064 /*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
13065  *    Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
13066  *    core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
13067  *    register field should be set to 1; otherwise it should be set to 0.
13068  *  0b0..Derating uses +1
13069  *  0b1..Derating uses +2
13070  */
13071 #define DDRC_DERATEEN_DERATE_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_DERATE_VALUE_MASK)
13072 
13073 #define DDRC_DERATEEN_DERATE_BYTE_MASK           (0xF0U)
13074 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT          (4U)
13075 /*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
13076  *    Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
13077  *    MEMC_DRAM_TOTAL_DATA_WIDTH.
13078  */
13079 #define DDRC_DERATEEN_DERATE_BYTE(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_DERATE_BYTE_SHIFT)) & DDRC_DERATEEN_DERATE_BYTE_MASK)
13080 
13081 #define DDRC_DERATEEN_RC_DERATE_VALUE_MASK       (0x300U)
13082 #define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT      (8U)
13083 /*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
13084  *    LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
13085  *    core_ddrc_core_clk period, and rounding up the next integer.
13086  *  0b00..Derating uses +1
13087  *  0b01..Derating uses +2
13088  *  0b10..Derating uses +3
13089  *  0b11..Derating uses +4
13090  */
13091 #define DDRC_DERATEEN_RC_DERATE_VALUE(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_RC_DERATE_VALUE_MASK)
13092 /*! @} */
13093 
13094 /*! @name DERATEINT - Temperature Derate Interval Register */
13095 /*! @{ */
13096 
13097 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK    (0xFFFFFFFFU)
13098 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT   (0U)
13099 /*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
13100  *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
13101  *    zero. Unit: DFI clock cycle.
13102  */
13103 #define DDRC_DERATEINT_MR4_READ_INTERVAL(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT)) & DDRC_DERATEINT_MR4_READ_INTERVAL_MASK)
13104 /*! @} */
13105 
13106 /*! @name PWRCTL - Low Power Control Register */
13107 /*! @{ */
13108 
13109 #define DDRC_PWRCTL_SELFREF_EN_MASK              (0x1U)
13110 #define DDRC_PWRCTL_SELFREF_EN_SHIFT             (0U)
13111 /*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number
13112  *    of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit
13113  *    may be re-programmed during the course of normal operation.
13114  */
13115 #define DDRC_PWRCTL_SELFREF_EN(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_SELFREF_EN_SHIFT)) & DDRC_PWRCTL_SELFREF_EN_MASK)
13116 
13117 #define DDRC_PWRCTL_POWERDOWN_EN_MASK            (0x2U)
13118 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT           (1U)
13119 /*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles
13120  *    "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be
13121  *    re-programmed during the course of normal operation.
13122  */
13123 #define DDRC_PWRCTL_POWERDOWN_EN(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_POWERDOWN_EN_SHIFT)) & DDRC_PWRCTL_POWERDOWN_EN_MASK)
13124 
13125 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK        (0x4U)
13126 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT       (2U)
13127 /*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the
13128  *    transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down
13129  *    mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only
13130  *    in designs configured to support mDDR or LPDDR2 or LPDDR3. For
13131  *    non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
13132  */
13133 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT)) & DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK)
13134 
13135 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK (0x8U)
13136 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT (3U)
13137 /*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not
13138  *    required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of
13139  *    dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can
13140  *    be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3,
13141  *    can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal
13142  *    operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in
13143  *    Power Down during Normal operation (Clock Stop)
13144  */
13145 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT)) & DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK)
13146 
13147 #define DDRC_PWRCTL_MPSM_EN_MASK                 (0x10U)
13148 #define DDRC_PWRCTL_MPSM_EN_SHIFT                (4U)
13149 /*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the
13150  *    transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power
13151  *    saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register
13152  *    should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY
13153  *    parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to
13154  *    toggle. FOR PERFORMANCE ONLY.
13155  */
13156 #define DDRC_PWRCTL_MPSM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_MPSM_EN_SHIFT)) & DDRC_PWRCTL_MPSM_EN_MASK)
13157 
13158 #define DDRC_PWRCTL_SELFREF_SW_MASK              (0x20U)
13159 #define DDRC_PWRCTL_SELFREF_SW_SHIFT             (5U)
13160 /*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
13161  *    immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
13162  *    Entry/Exit to Self Refresh.
13163  *  0b0..Software Exit from Self Refresh
13164  *  0b1..Software Entry to Self Refresh
13165  */
13166 #define DDRC_PWRCTL_SELFREF_SW(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_SELFREF_SW_SHIFT)) & DDRC_PWRCTL_SELFREF_SW_MASK)
13167 
13168 #define DDRC_PWRCTL_STAY_IN_SELFREF_MASK         (0x40U)
13169 #define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT        (6U)
13170 /*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
13171  *    down state or exit Self refresh power down state for LPDDR4. This register controls transition
13172  *    from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
13173  *    transition from Self refresh state
13174  *  0b0..
13175  *  0b1..
13176  */
13177 #define DDRC_PWRCTL_STAY_IN_SELFREF(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT)) & DDRC_PWRCTL_STAY_IN_SELFREF_MASK)
13178 /*! @} */
13179 
13180 /*! @name PWRTMG - Low Power Timing Register */
13181 /*! @{ */
13182 
13183 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK        (0x1FU)
13184 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT       (0U)
13185 /*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
13186  *    automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there
13187  *    are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit:
13188  *    Multiples of 32 DFI clocks FOR PERFORMANCE ONLY.
13189  */
13190 #define DDRC_PWRTMG_POWERDOWN_TO_X32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT)) & DDRC_PWRTMG_POWERDOWN_TO_X32_MASK)
13191 
13192 #define DDRC_PWRTMG_T_DPD_X4096_MASK             (0xFF00U)
13193 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT            (8U)
13194 /*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as
13195  *    mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is
13196  *    de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI
13197  *    clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
13198  *    ONLY.
13199  */
13200 #define DDRC_PWRTMG_T_DPD_X4096(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_T_DPD_X4096_SHIFT)) & DDRC_PWRTMG_T_DPD_X4096_MASK)
13201 
13202 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK          (0xFF0000U)
13203 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT         (16U)
13204 /*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
13205  *    automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there
13206  *    are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit:
13207  *    Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
13208  */
13209 #define DDRC_PWRTMG_SELFREF_TO_X32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT)) & DDRC_PWRTMG_SELFREF_TO_X32_MASK)
13210 /*! @} */
13211 
13212 /*! @name HWLPCTL - Hardware Low Power Control Register */
13213 /*! @{ */
13214 
13215 #define DDRC_HWLPCTL_HW_LP_EN_MASK               (0x1U)
13216 #define DDRC_HWLPCTL_HW_LP_EN_SHIFT              (0U)
13217 /*! hw_lp_en - Enable for Hardware Low Power Interface. */
13218 #define DDRC_HWLPCTL_HW_LP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_HW_LP_EN_SHIFT)) & DDRC_HWLPCTL_HW_LP_EN_MASK)
13219 
13220 #define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK     (0x2U)
13221 #define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT    (1U)
13222 /*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be
13223  *    used to exit from the automatic clock stop, automatic power down or automatic self-refresh
13224  *    modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power
13225  *    Interface and/or Software (PWRCTL.selfref_sw).
13226  */
13227 #define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT)) & DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK)
13228 
13229 #define DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK         (0xFFF0000U)
13230 #define DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT        (16U)
13231 /*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command
13232  *    channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The
13233  *    DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware
13234  *    idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR
13235  *    PERFORMANCE ONLY.
13236  */
13237 #define DDRC_HWLPCTL_HW_LP_IDLE_X32(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT)) & DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK)
13238 /*! @} */
13239 
13240 /*! @name RFSHCTL0 - Refresh Control Register 0 */
13241 /*! @{ */
13242 
13243 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK      (0x4U)
13244 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT     (2U)
13245 /*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
13246  *    not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
13247  *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
13248  *  0b1..Per bank refresh
13249  *  0b0..All bank refresh
13250  */
13251 #define DDRC_RFSHCTL0_PER_BANK_REFRESH(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT)) & DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK)
13252 
13253 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK         (0x1F0U)
13254 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT        (4U)
13255 /*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
13256  *    accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
13257  *    perform a refresh is a one-time penalty that must be paid for each group of refreshes.
13258  *    Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
13259  *    Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
13260  *    the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
13261  *    refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
13262  *    DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
13263  *    per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
13264  *    feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
13265  *    mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
13266  *    must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
13267  *    due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
13268  *    situation, the refresh burst will be delayed until the PHY-initiated update is complete.
13269  */
13270 #define DDRC_RFSHCTL0_REFRESH_BURST(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT)) & DDRC_RFSHCTL0_REFRESH_BURST_MASK)
13271 
13272 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK        (0x1F000U)
13273 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT       (12U)
13274 /*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
13275  *    but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
13276  *    performed. A speculative refresh is a refresh performed at a time when refresh would be
13277  *    useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
13278  *    determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
13279  *    the last refresh, then a speculative refresh is performed. Speculative refreshes continues
13280  *    successively until there are no refreshes pending or until new reads or writes are issued to the
13281  *    DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
13282  */
13283 #define DDRC_RFSHCTL0_REFRESH_TO_X32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT)) & DDRC_RFSHCTL0_REFRESH_TO_X32_MASK)
13284 
13285 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK        (0xF00000U)
13286 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT       (20U)
13287 /*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
13288  *    page timer expires. A critical refresh is to be issued before this threshold is reached. It is
13289  *    recommended that this not be changed from the default value, currently shown as 0x2. It must
13290  *    always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
13291  *    internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
13292  *    (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
13293  *    RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
13294  */
13295 #define DDRC_RFSHCTL0_REFRESH_MARGIN(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT)) & DDRC_RFSHCTL0_REFRESH_MARGIN_MASK)
13296 /*! @} */
13297 
13298 /*! @name RFSHCTL1 - Refresh Control Register 1 */
13299 /*! @{ */
13300 
13301 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK (0xFFFU)
13302 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT (0U)
13303 /*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank
13304  *    configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
13305  *    proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
13306  *    of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
13307  */
13308 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT)) & DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK)
13309 
13310 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK (0xFFF0000U)
13311 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT (16U)
13312 /*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank
13313  *    configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
13314  *    proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
13315  *    of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
13316  */
13317 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT)) & DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK)
13318 /*! @} */
13319 
13320 /*! @name RFSHCTL3 - Refresh Control Register 3 */
13321 /*! @{ */
13322 
13323 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK      (0x1U)
13324 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT     (0U)
13325 /*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is
13326  *    disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh,
13327  *    reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh
13328  *    transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4
13329  *    CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is
13330  *    not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled
13331  *    (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This
13332  *    register field is changeable on the fly.
13333  */
13334 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT)) & DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK)
13335 
13336 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK  (0x2U)
13337 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT (1U)
13338 /*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
13339  *    the refresh register(s) have been updated. refresh_update_level must not be toggled when the
13340  *    DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when
13341  *    exiting reset.
13342  */
13343 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT)) & DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK)
13344 
13345 #define DDRC_RFSHCTL3_REFRESH_MODE_MASK          (0x70U)
13346 #define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT         (4U)
13347 /*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x -
13348  *    010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not
13349  *    supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if
13350  *    RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC.
13351  *    Note: This must be set up while the Controller is in reset or while the Controller is in
13352  *    self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic
13353  *    register will be supported in future version of the DDRC. Note: This register field has effect only
13354  *    if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1).
13355  */
13356 #define DDRC_RFSHCTL3_REFRESH_MODE(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT)) & DDRC_RFSHCTL3_REFRESH_MODE_MASK)
13357 /*! @} */
13358 
13359 /*! @name RFSHTMG - Refresh Timing Register */
13360 /*! @{ */
13361 
13362 #define DDRC_RFSHTMG_T_RFC_MIN_MASK              (0x3FFU)
13363 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT             (0U)
13364 /*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
13365  *    operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
13366  *    is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
13367  *    LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
13368  *    is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
13369  *    equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
13370  *    on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
13371  *    appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
13372  *    Unit: Clocks.
13373  */
13374 #define DDRC_RFSHTMG_T_RFC_MIN(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_T_RFC_MIN_SHIFT)) & DDRC_RFSHTMG_T_RFC_MIN_MASK)
13375 
13376 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK       (0x8000U)
13377 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT      (15U)
13378 /*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
13379  *    DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
13380  *    devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
13381  *    parameter not used - 1 - tREFBW parameter used
13382  */
13383 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT)) & DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK)
13384 
13385 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK          (0xFFF0000U)
13386 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT         (16U)
13387 /*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
13388  *    for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
13389  *    LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
13390  *    should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
13391  *    register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
13392  *    program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
13393  *    on the refresh mode. The user should program the appropriate value from the spec based on the
13394  *    value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
13395  *    greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
13396  *    DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
13397  *    2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
13398  *    RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
13399  */
13400 #define DDRC_RFSHTMG_T_RFC_NOM_X32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT)) & DDRC_RFSHTMG_T_RFC_NOM_X32_MASK)
13401 /*! @} */
13402 
13403 /*! @name ECCCFG0 - ECC Configuration Register 0 */
13404 /*! @{ */
13405 
13406 #define DDRC_ECCCFG0_ECC_MODE_MASK               (0x7U)
13407 #define DDRC_ECCCFG0_ECC_MODE_SHIFT              (0U)
13408 /*! ecc_mode - ECC mode indicator. */
13409 #define DDRC_ECCCFG0_ECC_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_MODE_SHIFT)) & DDRC_ECCCFG0_ECC_MODE_MASK)
13410 
13411 #define DDRC_ECCCFG0_DIS_SCRUB_MASK              (0x10U)
13412 #define DDRC_ECCCFG0_DIS_SCRUB_SHIFT             (4U)
13413 /*! dis_scrub - Disables ECC scrubs. */
13414 #define DDRC_ECCCFG0_DIS_SCRUB(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_DIS_SCRUB_SHIFT)) & DDRC_ECCCFG0_DIS_SCRUB_MASK)
13415 
13416 #define DDRC_ECCCFG0_ECC_AP_EN_MASK              (0x40U)
13417 #define DDRC_ECCCFG0_ECC_AP_EN_SHIFT             (6U)
13418 /*! ecc_ap_en - Enables address protection feature. Only supported when inline ECC is enabled. */
13419 #define DDRC_ECCCFG0_ECC_AP_EN(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_AP_EN_SHIFT)) & DDRC_ECCCFG0_ECC_AP_EN_MASK)
13420 
13421 #define DDRC_ECCCFG0_ECC_REGION_REMAP_EN_MASK    (0x80U)
13422 #define DDRC_ECCCFG0_ECC_REGION_REMAP_EN_SHIFT   (7U)
13423 /*! ecc_region_remap_en - Enables remapping ECC region feature. Only supported when inline ECC is enabled. */
13424 #define DDRC_ECCCFG0_ECC_REGION_REMAP_EN(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_REMAP_EN_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_REMAP_EN_MASK)
13425 
13426 #define DDRC_ECCCFG0_ECC_REGION_MAP_MASK         (0x7F00U)
13427 #define DDRC_ECCCFG0_ECC_REGION_MAP_SHIFT        (8U)
13428 /*! ecc_region_map - Selectable Protected Region setting. */
13429 #define DDRC_ECCCFG0_ECC_REGION_MAP(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_MAP_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_MAP_MASK)
13430 
13431 #define DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_MASK (0x3F0000U)
13432 #define DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_SHIFT (16U)
13433 /*! blk_channel_idle_time_x32 - Indicates the number of cycles on HIF interface with no access to
13434  *    protected regions which causes flush of all the block channels.
13435  */
13436 #define DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_SHIFT)) & DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_MASK)
13437 
13438 #define DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_MASK   (0x7000000U)
13439 #define DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_SHIFT  (24U)
13440 /*! ecc_ap_err_threshold - Sets threshold for address parity error. */
13441 #define DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_SHIFT)) & DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_MASK)
13442 
13443 #define DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_MASK   (0x20000000U)
13444 #define DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_SHIFT  (29U)
13445 /*! ecc_region_map_other - When ECCCFG0[ecc_region_map_granu] > 0, there is a region which is not
13446  *    controlled by ecc_region_map. This register defines the region to be protected or non-protected
13447  *    for Inline ECC. This register is valid only when ECCCFG0[ecc_region_map_granu]>0 &&
13448  *    ECCCFG0[ecc_mode]=4.
13449  */
13450 #define DDRC_ECCCFG0_ECC_REGION_MAP_OTHER(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_MASK)
13451 
13452 #define DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_MASK   (0xC0000000U)
13453 #define DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT  (30U)
13454 /*! ecc_region_map_granu - Indicates granularity of selectable protected region */
13455 #define DDRC_ECCCFG0_ECC_REGION_MAP_GRANU(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_MASK)
13456 /*! @} */
13457 
13458 /*! @name ECCCFG1 - ECC Configuration Register 1 */
13459 /*! @{ */
13460 
13461 #define DDRC_ECCCFG1_DATA_POISON_EN_MASK         (0x1U)
13462 #define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT        (0U)
13463 /*! data_poison_en - Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers. */
13464 #define DDRC_ECCCFG1_DATA_POISON_EN(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT)) & DDRC_ECCCFG1_DATA_POISON_EN_MASK)
13465 
13466 #define DDRC_ECCCFG1_DATA_POISON_BIT_MASK        (0x2U)
13467 #define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT       (1U)
13468 /*! data_poison_bit - Selects whether to poison 1 or 2 bits. */
13469 #define DDRC_ECCCFG1_DATA_POISON_BIT(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT)) & DDRC_ECCCFG1_DATA_POISON_BIT_MASK)
13470 
13471 #define DDRC_ECCCFG1_POISON_CHIP_EN_MASK         (0x4U)
13472 #define DDRC_ECCCFG1_POISON_CHIP_EN_SHIFT        (2U)
13473 /*! poison_chip_en - Indicates the data poison based on chip (that is, persistently poisons the DRAM
13474  *    data once its cs is selected to mimic chip failure). It is valid if ECCCFG1[data_poison_en]=1.
13475  */
13476 #define DDRC_ECCCFG1_POISON_CHIP_EN(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_POISON_CHIP_EN_SHIFT)) & DDRC_ECCCFG1_POISON_CHIP_EN_MASK)
13477 
13478 #define DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_MASK (0x10U)
13479 #define DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_SHIFT (4U)
13480 /*! ecc_region_parity_lock - Locks the parity section of the ECC region (hole) which is the highest
13481  *    system address part of the memory that stores ECC parity for protected region.
13482  */
13483 #define DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_SHIFT)) & DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_MASK)
13484 
13485 #define DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_MASK  (0x20U)
13486 #define DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_SHIFT (5U)
13487 /*! ecc_region_waste_lock - Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock. */
13488 #define DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_SHIFT)) & DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_MASK)
13489 
13490 #define DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_MASK (0x80U)
13491 #define DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_SHIFT (7U)
13492 /*! blk_channel_active_term - If enabled, block channel is terminated when full block write or full
13493  *    block read is performed (all address within block are written or read). This is debug
13494  *    register, and this must be set to 1 for normal operation.
13495  */
13496 #define DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_SHIFT)) & DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_MASK)
13497 
13498 #define DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_MASK     (0xF00U)
13499 #define DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_SHIFT    (8U)
13500 /*! active_blk_channel - Indicated the number of active block channels. */
13501 #define DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_SHIFT)) & DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_MASK)
13502 /*! @} */
13503 
13504 /*! @name INIT0 - SDRAM Initialization Register 0 */
13505 /*! @{ */
13506 
13507 #define DDRC_INIT0_PRE_CKE_X1024_MASK            (0xFFFU)
13508 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT           (0U)
13509 /*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM
13510  *    initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be
13511  *    programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2
13512  *    ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC
13513  *    spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this
13514  *    should include the time needed to satisfy tSTAB
13515  */
13516 #define DDRC_INIT0_PRE_CKE_X1024(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_PRE_CKE_X1024_SHIFT)) & DDRC_INIT0_PRE_CKE_X1024_MASK)
13517 
13518 #define DDRC_INIT0_POST_CKE_X1024_MASK           (0x3FF0000U)
13519 #define DDRC_INIT0_POST_CKE_X1024_SHIFT          (16U)
13520 /*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization
13521  *    sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value
13522  *    to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be
13523  *    programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us.
13524  *    When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
13525  *    value divided by 2, and round it up to the next integer value.
13526  */
13527 #define DDRC_INIT0_POST_CKE_X1024(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_POST_CKE_X1024_SHIFT)) & DDRC_INIT0_POST_CKE_X1024_MASK)
13528 
13529 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK           (0xC0000000U)
13530 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT          (30U)
13531 /*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
13532  *    bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
13533  *    Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
13534  *    power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
13535  *    power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
13536  *    after power-up.
13537  *  0b00..SDRAM Initialization routine is run after power-up
13538  *  0b01..SDRAM Initialization routine is skipped after power-up
13539  *  0b10..SDRAM Initialization routine is run after power-up
13540  *  0b11..SDRAM Initialization routine is skipped after power-up
13541  */
13542 #define DDRC_INIT0_SKIP_DRAM_INIT(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT)) & DDRC_INIT0_SKIP_DRAM_INIT_MASK)
13543 /*! @} */
13544 
13545 /*! @name INIT1 - SDRAM Initialization Register 1 */
13546 /*! @{ */
13547 
13548 #define DDRC_INIT1_PRE_OCD_X32_MASK              (0xFU)
13549 #define DDRC_INIT1_PRE_OCD_X32_SHIFT             (0U)
13550 /*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a
13551  *    global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for
13552  *    this; it may be set to zero.
13553  */
13554 #define DDRC_INIT1_PRE_OCD_X32(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_PRE_OCD_X32_SHIFT)) & DDRC_INIT1_PRE_OCD_X32_MASK)
13555 
13556 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK          (0x1FF0000U)
13557 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT         (16U)
13558 /*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is
13559  *    only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this
13560  *    should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode,
13561  *    program this to JEDEC spec value divided by 2, and round it up to the next integer value.
13562  *    Unit: 1024 DFI clock cycles.
13563  */
13564 #define DDRC_INIT1_DRAM_RSTN_X1024(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT)) & DDRC_INIT1_DRAM_RSTN_X1024_MASK)
13565 /*! @} */
13566 
13567 /*! @name INIT2 - SDRAM Initialization Register 2 */
13568 /*! @{ */
13569 
13570 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK      (0xFU)
13571 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT     (0U)
13572 /*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs
13573  *    configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the
13574  *    controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by
13575  *    2, and round it up to the next integer value. Unit: DFI clock cycles.
13576  */
13577 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT)) & DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK)
13578 
13579 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK     (0xFF00U)
13580 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT    (8U)
13581 /*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs
13582  *    configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program
13583  *    this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI
13584  *    clock cycles.
13585  */
13586 #define DDRC_INIT2_IDLE_AFTER_RESET_X32(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT)) & DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK)
13587 /*! @} */
13588 
13589 /*! @name INIT3 - SDRAM Initialization Register 3 */
13590 /*! @{ */
13591 
13592 #define DDRC_INIT3_EMR_MASK                      (0xFFFFU)
13593 #define DDRC_INIT3_EMR_SHIFT                     (0U)
13594 /*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
13595  *    register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
13596  *    register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
13597  *    the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
13598  *    Value to write to MR2 register
13599  */
13600 #define DDRC_INIT3_EMR(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_EMR_SHIFT)) & DDRC_INIT3_EMR_MASK)
13601 
13602 #define DDRC_INIT3_MR_MASK                       (0xFFFF0000U)
13603 #define DDRC_INIT3_MR_SHIFT                      (16U)
13604 /*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
13605  *    DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
13606  *    write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
13607  */
13608 #define DDRC_INIT3_MR(x)                         (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_MR_SHIFT)) & DDRC_INIT3_MR_MASK)
13609 /*! @} */
13610 
13611 /*! @name INIT4 - SDRAM Initialization Register 4 */
13612 /*! @{ */
13613 
13614 #define DDRC_INIT4_EMR3_MASK                     (0xFFFFU)
13615 #define DDRC_INIT4_EMR3_SHIFT                    (0U)
13616 /*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
13617  *    mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
13618  */
13619 #define DDRC_INIT4_EMR3(x)                       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_EMR3_SHIFT)) & DDRC_INIT4_EMR3_MASK)
13620 
13621 #define DDRC_INIT4_EMR2_MASK                     (0xFFFF0000U)
13622 #define DDRC_INIT4_EMR2_SHIFT                    (16U)
13623 /*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
13624  *    LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
13625  */
13626 #define DDRC_INIT4_EMR2(x)                       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_EMR2_SHIFT)) & DDRC_INIT4_EMR2_MASK)
13627 /*! @} */
13628 
13629 /*! @name INIT5 - SDRAM Initialization Register 5 */
13630 /*! @{ */
13631 
13632 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK      (0x3FFU)
13633 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT     (0U)
13634 /*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in
13635  *    designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI
13636  *    clock cycles.
13637  */
13638 #define DDRC_INIT5_MAX_AUTO_INIT_X1024(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT)) & DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK)
13639 
13640 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK           (0xFF0000U)
13641 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT          (16U)
13642 /*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support
13643  *    DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires
13644  *    1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2
13645  *    frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the
13646  *    next integer value. Unit: 32 DFI clock cycles.
13647  */
13648 #define DDRC_INIT5_DEV_ZQINIT_X32(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT)) & DDRC_INIT5_DEV_ZQINIT_X32_MASK)
13649 /*! @} */
13650 
13651 /*! @name INIT6 - SDRAM Initialization Register 6 */
13652 /*! @{ */
13653 
13654 #define DDRC_INIT6_MR5_MASK                      (0xFFFFU)
13655 #define DDRC_INIT6_MR5_SHIFT                     (0U)
13656 /*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. */
13657 #define DDRC_INIT6_MR5(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_MR5_SHIFT)) & DDRC_INIT6_MR5_MASK)
13658 
13659 #define DDRC_INIT6_MR4_MASK                      (0xFFFF0000U)
13660 #define DDRC_INIT6_MR4_SHIFT                     (16U)
13661 /*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. */
13662 #define DDRC_INIT6_MR4(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_MR4_SHIFT)) & DDRC_INIT6_MR4_MASK)
13663 /*! @} */
13664 
13665 /*! @name INIT7 - SDRAM Initialization Register 7 */
13666 /*! @{ */
13667 
13668 #define DDRC_INIT7_MR6_MASK                      (0xFFFF0000U)
13669 #define DDRC_INIT7_MR6_SHIFT                     (16U)
13670 /*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. */
13671 #define DDRC_INIT7_MR6(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_MR6_SHIFT)) & DDRC_INIT7_MR6_MASK)
13672 /*! @} */
13673 
13674 /*! @name DIMMCTL - DIMM Control Register */
13675 /*! @{ */
13676 
13677 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK     (0x1U)
13678 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT    (0U)
13679 /*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
13680  *    LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
13681  *    Even if this bit is set it does not take care of software driven MR commands (via
13682  *    MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
13683  *  0b0..Do not stagger accesses
13684  *  0b1..(non-DDR4) Send all commands to even and odd ranks separately
13685  */
13686 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT)) & DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK)
13687 
13688 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK      (0x2U)
13689 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT     (1U)
13690 /*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
13691  *    multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
13692  *    mirroring for odd ranks, which means that the following address, bank address and bank group
13693  *    bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
13694  *    the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
13695  *    initialization routine, these bits are swapped within the DDRC to compensate for this
13696  *    UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
13697  *    UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
13698  *    DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
13699  *    software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
13700  *    SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
13701  *    because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
13702  *  0b0..Do not implement address mirroring
13703  *  0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
13704  *       automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
13705  */
13706 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT)) & DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK)
13707 
13708 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK     (0x4U)
13709 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT    (2U)
13710 /*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
13711  *    RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
13712  *    following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
13713  *    A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
13714  *    DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
13715  *    separate A-side and B-side mode register accesses are generated. For B-side mode register
13716  *    accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
13717  *    is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
13718  *    on the address of any other memory accesses, or of software-driven mode register accesses.
13719  *  0b0..Do not implement output inversion for B-side DRAMs.
13720  *  0b1..Implement output inversion for B-side DRAMs.
13721  */
13722 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT)) & DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK)
13723 
13724 #define DDRC_DIMMCTL_MRS_A17_EN_MASK             (0x8U)
13725 #define DDRC_DIMMCTL_MRS_A17_EN_SHIFT            (3U)
13726 /*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
13727  *    specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
13728  *    which do not have A17 are attached and the Output Inversion are enabled, this must be set to
13729  *    0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
13730  *    the address of any other memory accesses, or of software-driven mode register accesses.
13731  *  0b0..Disabled
13732  *  0b1..Enabled
13733  */
13734 #define DDRC_DIMMCTL_MRS_A17_EN(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_MRS_A17_EN_SHIFT)) & DDRC_DIMMCTL_MRS_A17_EN_MASK)
13735 
13736 #define DDRC_DIMMCTL_MRS_BG1_EN_MASK             (0x10U)
13737 #define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT            (4U)
13738 /*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
13739  *    specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
13740  *    which do not have BG1 are attached and both the CA parity and the Output Inversion are
13741  *    enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
13742  *    This has no effect on the address of any other memory accesses, or of software-driven mode
13743  *    register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
13744  *    of odd ranks.
13745  *  0b0..Disabled
13746  *  0b1..Enabled
13747  */
13748 #define DDRC_DIMMCTL_MRS_BG1_EN(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT)) & DDRC_DIMMCTL_MRS_BG1_EN_MASK)
13749 
13750 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK  (0x20U)
13751 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT (5U)
13752 /*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
13753  *    BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
13754  *    with x16 devices.
13755  *  0b0..BG0 and BG1 are swapped if address mirroring is enabled.
13756  *  0b1..BG0 and BG1 are NOT swapped.
13757  */
13758 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT)) & DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK)
13759 
13760 #define DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_MASK   (0x40U)
13761 #define DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_SHIFT  (6U)
13762 /*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM
13763  *    commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set
13764  *    to 1. Otherwise, this bit must be set to 0.
13765  */
13766 #define DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_SHIFT)) & DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_MASK)
13767 /*! @} */
13768 
13769 /*! @name RANKCTL - Rank Control Register */
13770 /*! @{ */
13771 
13772 #define DDRC_RANKCTL_MAX_RANK_RD_MASK            (0xFU)
13773 #define DDRC_RANKCTL_MAX_RANK_RD_SHIFT           (0U)
13774 /*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can
13775  *    be performed back-to-back. Reads to different ranks require additional gap dictated by the
13776  *    register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to
13777  *    give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus
13778  *    access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles
13779  *    (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the
13780  *    same rank are eligible to be scheduled. This prevents reads from other ranks from having fair
13781  *    access to the data bus. This parameter represents the maximum number of reads that can be
13782  *    scheduled consecutively to the same rank. After this number is reached, a delay equal to
13783  *    RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be
13784  *    scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This
13785  *    feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on
13786  *    the same rank as long as commands are available for it. Minimum programmable value is 0 (feature
13787  *    disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
13788  */
13789 #define DDRC_RANKCTL_MAX_RANK_RD(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_MAX_RANK_RD_SHIFT)) & DDRC_RANKCTL_MAX_RANK_RD_MASK)
13790 
13791 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK       (0xF0U)
13792 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT      (4U)
13793 /*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of
13794  *    gap in data responses when performing consecutive reads to different ranks. This is used to
13795  *    switch the delays in the PHY to match the rank requirements. This value should consider both
13796  *    PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for
13797  *    value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased
13798  *    by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT
13799  *    requirement: The value programmed in this register takes care of the ODT switch off timing requirement
13800  *    when switching ranks during reads. When the controller is operating in 1:1 mode, program this
13801  *    to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2
13802  *    mode, program this to the larger value divided by two and round it up to the next integer.
13803  *    Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer
13804  *    (DDR4DB01) Specification.
13805  */
13806 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT)) & DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK)
13807 
13808 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK       (0xF00U)
13809 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT      (8U)
13810 /*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of
13811  *    gap in data responses when performing consecutive writes to different ranks. This is used to
13812  *    switch the delays in the PHY to match the rank requirements. This value should consider both
13813  *    PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for
13814  *    value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble
13815  *    is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to
13816  *    1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this
13817  *    register takes care of the ODT switch off timing requirement when switching ranks during writes.
13818  *    For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in
13819  *    1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the
13820  *    controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to
13821  *    the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in
13822  *    JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
13823  */
13824 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT)) & DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK)
13825 /*! @} */
13826 
13827 /*! @name DRAMTMG0 - SDRAM Timing Register 0 */
13828 /*! @{ */
13829 
13830 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK             (0x3FU)
13831 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT            (0U)
13832 /*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
13833  *    controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
13834  *    up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
13835  *    program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
13836  */
13837 #define DDRC_DRAMTMG0_T_RAS_MIN(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT)) & DDRC_DRAMTMG0_T_RAS_MIN_MASK)
13838 
13839 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK             (0x7F00U)
13840 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT            (8U)
13841 /*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
13842  *    maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
13843  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
13844  *    No rounding up. Unit: Multiples of 1024 clocks.
13845  */
13846 #define DDRC_DRAMTMG0_T_RAS_MAX(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT)) & DDRC_DRAMTMG0_T_RAS_MAX_MASK)
13847 
13848 #define DDRC_DRAMTMG0_T_FAW_MASK                 (0x3F0000U)
13849 #define DDRC_DRAMTMG0_T_FAW_SHIFT                (16U)
13850 /*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
13851  *    design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
13852  *    is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
13853  *    integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
13854  *    mode. Unit: Clocks
13855  */
13856 #define DDRC_DRAMTMG0_T_FAW(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_T_FAW_SHIFT)) & DDRC_DRAMTMG0_T_FAW_MASK)
13857 
13858 #define DDRC_DRAMTMG0_WR2PRE_MASK                (0x7F000000U)
13859 #define DDRC_DRAMTMG0_WR2PRE_SHIFT               (24U)
13860 /*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
13861  *    + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
13862  *    frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
13863  *    the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
13864  *    - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
13865  *    cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
13866  *    frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
13867  *    is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
13868  *    and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
13869  *    may be necessary to adjust the value of this parameter to compensate for the extra cycle of
13870  *    latency through the LRDIMM.
13871  */
13872 #define DDRC_DRAMTMG0_WR2PRE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_WR2PRE_SHIFT)) & DDRC_DRAMTMG0_WR2PRE_MASK)
13873 /*! @} */
13874 
13875 /*! @name DRAMTMG1 - SDRAM Timing Register 1 */
13876 /*! @{ */
13877 
13878 #define DDRC_DRAMTMG1_T_RC_MASK                  (0x7FU)
13879 #define DDRC_DRAMTMG1_T_RC_SHIFT                 (0U)
13880 /*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
13881  *    frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
13882  *    Clocks.
13883  */
13884 #define DDRC_DRAMTMG1_T_RC(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_T_RC_SHIFT)) & DDRC_DRAMTMG1_T_RC_MASK)
13885 
13886 #define DDRC_DRAMTMG1_RD2PRE_MASK                (0x3F00U)
13887 #define DDRC_DRAMTMG1_RD2PRE_SHIFT               (8U)
13888 /*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
13889  *    2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
13890  *    or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
13891  *    LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
13892  *    - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
13893  *    use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
13894  *    divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
13895  *    mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
13896  *    Unit: Clocks.
13897  */
13898 #define DDRC_DRAMTMG1_RD2PRE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_RD2PRE_SHIFT)) & DDRC_DRAMTMG1_RD2PRE_MASK)
13899 
13900 #define DDRC_DRAMTMG1_T_XP_MASK                  (0x1F0000U)
13901 #define DDRC_DRAMTMG1_T_XP_SHIFT                 (16U)
13902 /*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
13903  *    programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
13904  *    set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
13905  *    this to (tXP/2) and round it up to the next integer value. Units: Clocks
13906  */
13907 #define DDRC_DRAMTMG1_T_XP(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_T_XP_SHIFT)) & DDRC_DRAMTMG1_T_XP_MASK)
13908 /*! @} */
13909 
13910 /*! @name DRAMTMG2 - SDRAM Timing Register 2 */
13911 /*! @{ */
13912 
13913 #define DDRC_DRAMTMG2_WR2RD_MASK                 (0x3FU)
13914 #define DDRC_DRAMTMG2_WR2RD_SHIFT                (0U)
13915 /*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
13916  *    write command to read command for same bank group. In others, minimum time from write command to
13917  *    read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
13918  *    global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
13919  *    = burst length. This must match the value programmed in the BL bit of the mode register to
13920  *    the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
13921  *    directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
13922  *    directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
13923  *    When the controller is operating in 1:2 mode, divide the value calculated using the above
13924  *    equation by 2, and round it up to next integer.
13925  */
13926 #define DDRC_DRAMTMG2_WR2RD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_WR2RD_SHIFT)) & DDRC_DRAMTMG2_WR2RD_MASK)
13927 
13928 #define DDRC_DRAMTMG2_RD2WR_MASK                 (0x3F00U)
13929 #define DDRC_DRAMTMG2_RD2WR_SHIFT                (8U)
13930 /*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
13931  *    + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
13932  *    + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
13933  *    RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
13934  *    Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
13935  *    the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
13936  *    WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
13937  *    the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
13938  *    preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
13939  *    LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
13940  *    tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
13941  *    value calculated using the above equation by 2, and round it up to next integer. Note that,
13942  *    depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
13943  *    to compensate for the extra cycle of latency through the LRDIMM.
13944  */
13945 #define DDRC_DRAMTMG2_RD2WR(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_RD2WR_SHIFT)) & DDRC_DRAMTMG2_RD2WR_MASK)
13946 
13947 #define DDRC_DRAMTMG2_READ_LATENCY_MASK          (0x3F0000U)
13948 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT         (16U)
13949 /*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
13950  *    set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
13951  *    the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
13952  *    the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
13953  *    above equation by 2, and round it up to next integer. This register field is not required for
13954  *    DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
13955  *    DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
13956  */
13957 #define DDRC_DRAMTMG2_READ_LATENCY(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_READ_LATENCY_SHIFT)) & DDRC_DRAMTMG2_READ_LATENCY_MASK)
13958 
13959 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK         (0x3F000000U)
13960 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT        (24U)
13961 /*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
13962  *    set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
13963  *    using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
13964  *    cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
13965  *    mode, divide the value calculated using the above equation by 2, and round it up to next
13966  *    integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
13967  *    as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
13968  *    protocols Unit: clocks
13969  */
13970 #define DDRC_DRAMTMG2_WRITE_LATENCY(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT)) & DDRC_DRAMTMG2_WRITE_LATENCY_MASK)
13971 /*! @} */
13972 
13973 /*! @name DRAMTMG3 - SDRAM Timing Register 3 */
13974 /*! @{ */
13975 
13976 #define DDRC_DRAMTMG3_T_MOD_MASK                 (0x3FFU)
13977 #define DDRC_DRAMTMG3_T_MOD_SHIFT                (0U)
13978 /*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
13979  *    following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
13980  *    Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
13981  *    next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
13982  *    RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
13983  *    compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
13984  *    Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
13985  *    is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
13986  *    controller is operating in 1:2 frequency ratio mode.
13987  */
13988 #define DDRC_DRAMTMG3_T_MOD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_T_MOD_SHIFT)) & DDRC_DRAMTMG3_T_MOD_MASK)
13989 
13990 #define DDRC_DRAMTMG3_T_MRD_MASK                 (0x3F000U)
13991 #define DDRC_DRAMTMG3_T_MRD_SHIFT                (12U)
13992 /*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
13993  *    SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
13994  *    command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
13995  *    operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
13996  *    value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
13997  */
13998 #define DDRC_DRAMTMG3_T_MRD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_T_MRD_SHIFT)) & DDRC_DRAMTMG3_T_MRD_MASK)
13999 
14000 #define DDRC_DRAMTMG3_T_MRW_MASK                 (0x3FF00000U)
14001 #define DDRC_DRAMTMG3_T_MRW_SHIFT                (20U)
14002 /*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
14003  *    configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
14004  *    typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
14005  *    this register is used for the time from a MRW/MRR to all other commands. When the controller
14006  *    is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
14007  *    round it up to the next integer value. For LDPDR3, this register is used for the time from a
14008  *    MRW/MRR to a MRW/MRR.
14009  */
14010 #define DDRC_DRAMTMG3_T_MRW(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_T_MRW_SHIFT)) & DDRC_DRAMTMG3_T_MRW_MASK)
14011 /*! @} */
14012 
14013 /*! @name DRAMTMG4 - SDRAM Timing Register 4 */
14014 /*! @{ */
14015 
14016 #define DDRC_DRAMTMG4_T_RP_MASK                  (0x1FU)
14017 #define DDRC_DRAMTMG4_T_RP_SHIFT                 (0U)
14018 /*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
14019  *    operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
14020  *    operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
14021  *    1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
14022  *    to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
14023  */
14024 #define DDRC_DRAMTMG4_T_RP(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_RP_SHIFT)) & DDRC_DRAMTMG4_T_RP_MASK)
14025 
14026 #define DDRC_DRAMTMG4_T_RRD_MASK                 (0xF00U)
14027 #define DDRC_DRAMTMG4_T_RRD_SHIFT                (8U)
14028 /*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
14029  *    group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
14030  *    is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
14031  *    up to the next integer value. Unit: Clocks.
14032  */
14033 #define DDRC_DRAMTMG4_T_RRD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_RRD_SHIFT)) & DDRC_DRAMTMG4_T_RRD_MASK)
14034 
14035 #define DDRC_DRAMTMG4_T_CCD_MASK                 (0xF0000U)
14036 #define DDRC_DRAMTMG4_T_CCD_SHIFT                (16U)
14037 /*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
14038  *    group. Others: tCCD: This is the minimum time between two reads or two writes. When the
14039  *    controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
14040  *    up to the next integer value. Unit: clocks.
14041  */
14042 #define DDRC_DRAMTMG4_T_CCD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_CCD_SHIFT)) & DDRC_DRAMTMG4_T_CCD_MASK)
14043 
14044 #define DDRC_DRAMTMG4_T_RCD_MASK                 (0x1F000000U)
14045 #define DDRC_DRAMTMG4_T_RCD_SHIFT                (24U)
14046 /*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
14047  *    controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
14048  *    it up to the next integer value. Minimum value allowed for this register is 1, which implies
14049  *    minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
14050  *    mode. Unit: Clocks.
14051  */
14052 #define DDRC_DRAMTMG4_T_RCD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_RCD_SHIFT)) & DDRC_DRAMTMG4_T_RCD_MASK)
14053 /*! @} */
14054 
14055 /*! @name DRAMTMG5 - SDRAM Timing Register 5 */
14056 /*! @{ */
14057 
14058 #define DDRC_DRAMTMG5_T_CKE_MASK                 (0x1FU)
14059 #define DDRC_DRAMTMG5_T_CKE_SHIFT                (0U)
14060 /*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
14061  *    LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
14062  *    tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
14063  *    the controller is operating in 1:2 frequency ratio mode, program this to (value described
14064  *    above)/2 and round it up to the next integer value. Unit: Clocks.
14065  */
14066 #define DDRC_DRAMTMG5_T_CKE(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKE_SHIFT)) & DDRC_DRAMTMG5_T_CKE_MASK)
14067 
14068 #define DDRC_DRAMTMG5_T_CKESR_MASK               (0x3F00U)
14069 #define DDRC_DRAMTMG5_T_CKESR_SHIFT              (8U)
14070 /*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
14071  *    in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
14072  *    - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
14073  *    latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
14074  *    by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
14075  *    recommended value divided by two and round it up to next integer.
14076  */
14077 #define DDRC_DRAMTMG5_T_CKESR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKESR_SHIFT)) & DDRC_DRAMTMG5_T_CKESR_MASK)
14078 
14079 #define DDRC_DRAMTMG5_T_CKSRE_MASK               (0xF0000U)
14080 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT              (16U)
14081 /*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
14082  *    Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
14083  *    LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
14084  *    PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
14085  *    be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
14086  *    this to recommended value divided by two and round it up to next integer.
14087  */
14088 #define DDRC_DRAMTMG5_T_CKSRE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKSRE_SHIFT)) & DDRC_DRAMTMG5_T_CKSRE_MASK)
14089 
14090 #define DDRC_DRAMTMG5_T_CKSRX_MASK               (0xF000000U)
14091 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT              (24U)
14092 /*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
14093  *    before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
14094  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
14095  *    controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
14096  *    two and round it up to next integer.
14097  */
14098 #define DDRC_DRAMTMG5_T_CKSRX(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKSRX_SHIFT)) & DDRC_DRAMTMG5_T_CKSRX_MASK)
14099 /*! @} */
14100 
14101 /*! @name DRAMTMG6 - SDRAM Timing Register 6 */
14102 /*! @{ */
14103 
14104 #define DDRC_DRAMTMG6_T_CKCSX_MASK               (0xFU)
14105 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT              (0U)
14106 /*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
14107  *    issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
14108  *    Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
14109  *    When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
14110  *    divided by two and round it up to next integer. This is only present for designs supporting
14111  *    mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
14112  */
14113 #define DDRC_DRAMTMG6_T_CKCSX(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_T_CKCSX_SHIFT)) & DDRC_DRAMTMG6_T_CKCSX_MASK)
14114 
14115 #define DDRC_DRAMTMG6_T_CKDPDX_MASK              (0xF0000U)
14116 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT             (16U)
14117 /*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
14118  *    before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
14119  *    1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
14120  *    program this to recommended value divided by two and round it up to next integer. This is only
14121  *    present for designs supporting mDDR or LPDDR2 devices.
14122  */
14123 #define DDRC_DRAMTMG6_T_CKDPDX(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_T_CKDPDX_SHIFT)) & DDRC_DRAMTMG6_T_CKDPDX_MASK)
14124 
14125 #define DDRC_DRAMTMG6_T_CKDPDE_MASK              (0xF000000U)
14126 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT             (24U)
14127 /*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
14128  *    Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
14129  *    LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
14130  *    recommended value divided by two and round it up to next integer. This is only present for designs
14131  *    supporting mDDR or LPDDR2/LPDDR3 devices.
14132  */
14133 #define DDRC_DRAMTMG6_T_CKDPDE(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_T_CKDPDE_SHIFT)) & DDRC_DRAMTMG6_T_CKDPDE_MASK)
14134 /*! @} */
14135 
14136 /*! @name DRAMTMG7 - SDRAM Timing Register 7 */
14137 /*! @{ */
14138 
14139 #define DDRC_DRAMTMG7_T_CKPDX_MASK               (0xFU)
14140 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT              (0U)
14141 /*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
14142  *    issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
14143  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
14144  *    same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
14145  *    program this to recommended value divided by two and round it up to next integer. This is only
14146  *    present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
14147  */
14148 #define DDRC_DRAMTMG7_T_CKPDX(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_T_CKPDX_SHIFT)) & DDRC_DRAMTMG7_T_CKPDX_MASK)
14149 
14150 #define DDRC_DRAMTMG7_T_CKPDE_MASK               (0xF00U)
14151 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT              (8U)
14152 /*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
14153  *    Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
14154  *    - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
14155  *    DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
14156  *    to recommended value divided by two and round it up to next integer. This is only present for
14157  *    designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
14158  */
14159 #define DDRC_DRAMTMG7_T_CKPDE(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_T_CKPDE_SHIFT)) & DDRC_DRAMTMG7_T_CKPDE_MASK)
14160 /*! @} */
14161 
14162 /*! @name DRAMTMG8 - SDRAM Timing Register 8 */
14163 /*! @{ */
14164 
14165 #define DDRC_DRAMTMG8_T_XS_X32_MASK              (0x7FU)
14166 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT             (0U)
14167 /*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
14168  *    operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
14169  *    up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
14170  *    DDR4 SDRAMs.
14171  */
14172 #define DDRC_DRAMTMG8_T_XS_X32(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_X32_MASK)
14173 
14174 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK          (0x7F00U)
14175 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT         (8U)
14176 /*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
14177  *    is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
14178  *    round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
14179  *    DDR4 SDRAMs.
14180  */
14181 #define DDRC_DRAMTMG8_T_XS_DLL_X32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_DLL_X32_MASK)
14182 
14183 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK        (0x7F0000U)
14184 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT       (16U)
14185 /*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
14186  *    Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
14187  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
14188  *    Note: Ensure this is less than or equal to t_xs_x32.
14189  */
14190 #define DDRC_DRAMTMG8_T_XS_ABORT_X32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK)
14191 
14192 #define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK         (0x7F000000U)
14193 #define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT        (24U)
14194 /*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
14195  *    mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
14196  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
14197  *    This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
14198  *    t_xs_x32.
14199  */
14200 #define DDRC_DRAMTMG8_T_XS_FAST_X32(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_FAST_X32_MASK)
14201 /*! @} */
14202 
14203 /*! @name DRAMTMG9 - SDRAM Timing Register 9 */
14204 /*! @{ */
14205 
14206 #define DDRC_DRAMTMG9_WR2RD_S_MASK               (0x3FU)
14207 #define DDRC_DRAMTMG9_WR2RD_S_SHIFT              (0U)
14208 /*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
14209  *    bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
14210  *    global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
14211  *    - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
14212  *    programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
14213  *    command delay for different bank group. This comes directly from the SDRAM specification. When
14214  *    the controller is operating in 1:2 mode, divide the value calculated using the above equation
14215  *    by 2, and round it up to next integer.
14216  */
14217 #define DDRC_DRAMTMG9_WR2RD_S(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_WR2RD_S_SHIFT)) & DDRC_DRAMTMG9_WR2RD_S_MASK)
14218 
14219 #define DDRC_DRAMTMG9_T_RRD_S_MASK               (0xF00U)
14220 #define DDRC_DRAMTMG9_T_RRD_S_SHIFT              (8U)
14221 /*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
14222  *    group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
14223  *    and round it up to the next integer value. Present only in designs configured to support DDR4.
14224  *    Unit: Clocks.
14225  */
14226 #define DDRC_DRAMTMG9_T_RRD_S(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_T_RRD_S_SHIFT)) & DDRC_DRAMTMG9_T_RRD_S_MASK)
14227 
14228 #define DDRC_DRAMTMG9_T_CCD_S_MASK               (0x70000U)
14229 #define DDRC_DRAMTMG9_T_CCD_S_SHIFT              (16U)
14230 /*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
14231  *    group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
14232  *    the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
14233  *    it up to the next integer value. Present only in designs configured to support DDR4. Unit:
14234  *    clocks.
14235  */
14236 #define DDRC_DRAMTMG9_T_CCD_S(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_T_CCD_S_SHIFT)) & DDRC_DRAMTMG9_T_CCD_S_MASK)
14237 
14238 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK      (0x40000000U)
14239 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT     (30U)
14240 /*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 */
14241 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT)) & DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK)
14242 /*! @} */
14243 
14244 /*! @name DRAMTMG10 - SDRAM Timing Register 10 */
14245 /*! @{ */
14246 
14247 #define DDRC_DRAMTMG10_T_GEAR_HOLD_MASK          (0x3U)
14248 #define DDRC_DRAMTMG10_T_GEAR_HOLD_SHIFT         (0U)
14249 /*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
14250  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
14251  *    1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
14252  *    value. Unit: Clocks
14253  */
14254 #define DDRC_DRAMTMG10_T_GEAR_HOLD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_GEAR_HOLD_SHIFT)) & DDRC_DRAMTMG10_T_GEAR_HOLD_MASK)
14255 
14256 #define DDRC_DRAMTMG10_T_GEAR_SETUP_MASK         (0xCU)
14257 #define DDRC_DRAMTMG10_T_GEAR_SETUP_SHIFT        (2U)
14258 /*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
14259  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
14260  *    1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
14261  *    value. Unit: Clocks
14262  */
14263 #define DDRC_DRAMTMG10_T_GEAR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_GEAR_SETUP_SHIFT)) & DDRC_DRAMTMG10_T_GEAR_SETUP_MASK)
14264 
14265 #define DDRC_DRAMTMG10_T_CMD_GEAR_MASK           (0x1F00U)
14266 #define DDRC_DRAMTMG10_T_CMD_GEAR_SHIFT          (8U)
14267 /*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
14268  *    defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
14269  *    this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
14270  *    and round it up to the next integer value. Unit: Clocks
14271  */
14272 #define DDRC_DRAMTMG10_T_CMD_GEAR(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_CMD_GEAR_SHIFT)) & DDRC_DRAMTMG10_T_CMD_GEAR_MASK)
14273 
14274 #define DDRC_DRAMTMG10_T_SYNC_GEAR_MASK          (0x1F0000U)
14275 #define DDRC_DRAMTMG10_T_SYNC_GEAR_SHIFT         (16U)
14276 /*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
14277  *    number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
14278  *    tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
14279  *    When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
14280  *    to the next integer value. Unit: Clocks
14281  */
14282 #define DDRC_DRAMTMG10_T_SYNC_GEAR(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_SYNC_GEAR_SHIFT)) & DDRC_DRAMTMG10_T_SYNC_GEAR_MASK)
14283 /*! @} */
14284 
14285 /*! @name DRAMTMG11 - SDRAM Timing Register 11 */
14286 /*! @{ */
14287 
14288 #define DDRC_DRAMTMG11_T_CKMPE_MASK              (0x1FU)
14289 #define DDRC_DRAMTMG11_T_CKMPE_SHIFT             (0U)
14290 /*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
14291  *    configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
14292  *    mode, divide the value calculated using the above equation by 2, and round it up to next
14293  *    integer.
14294  */
14295 #define DDRC_DRAMTMG11_T_CKMPE(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_T_CKMPE_SHIFT)) & DDRC_DRAMTMG11_T_CKMPE_MASK)
14296 
14297 #define DDRC_DRAMTMG11_T_MPX_S_MASK              (0x300U)
14298 #define DDRC_DRAMTMG11_T_MPX_S_SHIFT             (8U)
14299 /*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
14300  *    frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
14301  *    Present only in designs configured to support DDR4. Unit: Clocks.
14302  */
14303 #define DDRC_DRAMTMG11_T_MPX_S(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_T_MPX_S_SHIFT)) & DDRC_DRAMTMG11_T_MPX_S_MASK)
14304 
14305 #define DDRC_DRAMTMG11_T_MPX_LH_MASK             (0x1F0000U)
14306 #define DDRC_DRAMTMG11_T_MPX_LH_SHIFT            (16U)
14307 /*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
14308  *    controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
14309  *    only in designs configured to support DDR4. Unit: clocks.
14310  */
14311 #define DDRC_DRAMTMG11_T_MPX_LH(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_T_MPX_LH_SHIFT)) & DDRC_DRAMTMG11_T_MPX_LH_MASK)
14312 
14313 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK    (0x7F000000U)
14314 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT   (24U)
14315 /*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
14316  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
14317  *    round it up to the next integer value. Present only in designs configured to support DDR4.
14318  *    Unit: Multiples of 32 clocks.
14319  */
14320 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT)) & DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK)
14321 /*! @} */
14322 
14323 /*! @name DRAMTMG12 - SDRAM Timing Register 12 */
14324 /*! @{ */
14325 
14326 #define DDRC_DRAMTMG12_T_MRD_PDA_MASK            (0x1FU)
14327 #define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT           (0U)
14328 /*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
14329  *    controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
14330  *    to the next integer value.
14331  */
14332 #define DDRC_DRAMTMG12_T_MRD_PDA(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT)) & DDRC_DRAMTMG12_T_MRD_PDA_MASK)
14333 
14334 #define DDRC_DRAMTMG12_T_CKEHCMD_MASK            (0xF00U)
14335 #define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT           (8U)
14336 /*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
14337  *    operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
14338  *    integer value.
14339  */
14340 #define DDRC_DRAMTMG12_T_CKEHCMD(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT)) & DDRC_DRAMTMG12_T_CKEHCMD_MASK)
14341 
14342 #define DDRC_DRAMTMG12_T_CMDCKE_MASK             (0x30000U)
14343 #define DDRC_DRAMTMG12_T_CMDCKE_SHIFT            (16U)
14344 /*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
14345  *    or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
14346  *    (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
14347  */
14348 #define DDRC_DRAMTMG12_T_CMDCKE(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_T_CMDCKE_SHIFT)) & DDRC_DRAMTMG12_T_CMDCKE_MASK)
14349 /*! @} */
14350 
14351 /*! @name DRAMTMG13 - SDRAM Timing Register 13 */
14352 /*! @{ */
14353 
14354 #define DDRC_DRAMTMG13_T_PPD_MASK                (0x7U)
14355 #define DDRC_DRAMTMG13_T_PPD_SHIFT               (0U)
14356 /*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
14357  *    controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
14358  *    the next integer value. Unit: Clocks.
14359  */
14360 #define DDRC_DRAMTMG13_T_PPD(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_T_PPD_SHIFT)) & DDRC_DRAMTMG13_T_PPD_MASK)
14361 
14362 #define DDRC_DRAMTMG13_T_CCD_MW_MASK             (0x3F0000U)
14363 #define DDRC_DRAMTMG13_T_CCD_MW_SHIFT            (16U)
14364 /*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
14365  *    command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
14366  *    this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
14367  */
14368 #define DDRC_DRAMTMG13_T_CCD_MW(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_T_CCD_MW_SHIFT)) & DDRC_DRAMTMG13_T_CCD_MW_MASK)
14369 
14370 #define DDRC_DRAMTMG13_ODTLOFF_MASK              (0x7F000000U)
14371 #define DDRC_DRAMTMG13_ODTLOFF_SHIFT             (24U)
14372 /*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
14373  *    the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
14374  *    it up to the next integer value. Unit: Clocks.
14375  */
14376 #define DDRC_DRAMTMG13_ODTLOFF(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_ODTLOFF_SHIFT)) & DDRC_DRAMTMG13_ODTLOFF_MASK)
14377 /*! @} */
14378 
14379 /*! @name DRAMTMG14 - SDRAM Timing Register 14 */
14380 /*! @{ */
14381 
14382 #define DDRC_DRAMTMG14_T_XSR_MASK                (0xFFFU)
14383 #define DDRC_DRAMTMG14_T_XSR_SHIFT               (0U)
14384 /*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
14385  *    frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
14386  *    Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
14387  */
14388 #define DDRC_DRAMTMG14_T_XSR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_T_XSR_SHIFT)) & DDRC_DRAMTMG14_T_XSR_MASK)
14389 /*! @} */
14390 
14391 /*! @name DRAMTMG15 - SDRAM Timing Register 15 */
14392 /*! @{ */
14393 
14394 #define DDRC_DRAMTMG15_T_STAB_X32_MASK           (0xFFU)
14395 #define DDRC_DRAMTMG15_T_STAB_X32_SHIFT          (0U)
14396 /*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
14397  *    RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
14398  *    clock must be stable for a time specified by tSTAB - in the case of input clock frequency
14399  *    change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
14400  *    DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
14401  *    recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
14402  *    cycles.
14403  */
14404 #define DDRC_DRAMTMG15_T_STAB_X32(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_T_STAB_X32_SHIFT)) & DDRC_DRAMTMG15_T_STAB_X32_MASK)
14405 
14406 #define DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_MASK     (0x80000000U)
14407 #define DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_SHIFT    (31U)
14408 /*! en_dfi_lp_t_stab - Enable DFI tSTAB
14409  *  0b0..Disable using tSTAB when exiting DFI LP
14410  *  0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
14411  */
14412 #define DDRC_DRAMTMG15_EN_DFI_LP_T_STAB(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_SHIFT)) & DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_MASK)
14413 /*! @} */
14414 
14415 /*! @name ZQCTL0 - ZQ Control Register 0 */
14416 /*! @{ */
14417 
14418 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK          (0x3FFU)
14419 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT         (0U)
14420 /*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
14421  *    of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
14422  *    When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
14423  *    round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
14424  *    LPDDR2/LPDDR3/LPDDR4 devices.
14425  */
14426 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT)) & DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK)
14427 
14428 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK           (0x7FF0000U)
14429 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT          (16U)
14430 /*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
14431  *    clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
14432  *    issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
14433  *    this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
14434  *    tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
14435  *    up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
14436  *    LPDDR2/LPDDR3/LPDDR4 devices.
14437  */
14438 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT)) & DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK)
14439 
14440 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK          (0x10000000U)
14441 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT         (28U)
14442 /*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
14443  *    configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
14444  *    MPSM mode.
14445  *  0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
14446  *       This is only present for designs supporting DDR4 devices.
14447  *  0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
14448  */
14449 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT)) & DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK)
14450 
14451 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK      (0x20000000U)
14452 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT     (29U)
14453 /*! zq_resistor_shared - ZQ resistor sharing
14454  *  0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
14455  *  0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
14456  *       sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
14457  *       commands to different ranks do not overlap.
14458  */
14459 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT)) & DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK)
14460 
14461 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK            (0x40000000U)
14462 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT           (30U)
14463 /*! dis_srx_zqcl - Disable ZQCL/MPC
14464  *  0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
14465  *       when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
14466  *       DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
14467  *  0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
14468  *       when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
14469  */
14470 #define DDRC_ZQCTL0_DIS_SRX_ZQCL(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT)) & DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK)
14471 
14472 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK             (0x80000000U)
14473 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT            (31U)
14474 /*! dis_auto_zq - Disable Auto ZQCS/MPC
14475  *  0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
14476  *  0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
14477  *       instead to issue ZQ calibration request from APB module.
14478  */
14479 #define DDRC_ZQCTL0_DIS_AUTO_ZQ(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT)) & DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK)
14480 /*! @} */
14481 
14482 /*! @name ZQCTL1 - ZQ Control Register 1 */
14483 /*! @{ */
14484 
14485 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK (0xFFFFFU)
14486 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT (0U)
14487 /*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ
14488  *    calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.
14489  *    Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs
14490  *    supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
14491  */
14492 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT)) & DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK)
14493 
14494 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK          (0x3FF00000U)
14495 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT         (20U)
14496 /*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ
14497  *    calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency
14498  *    ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only
14499  *    present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
14500  */
14501 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT)) & DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK)
14502 /*! @} */
14503 
14504 /*! @name ZQCTL2 - ZQ Control Register 2 */
14505 /*! @{ */
14506 
14507 #define DDRC_ZQCTL2_ZQ_RESET_MASK                (0x1U)
14508 #define DDRC_ZQCTL2_ZQ_RESET_SHIFT               (0U)
14509 /*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset
14510  *    operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this
14511  *    signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down
14512  *    operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
14513  */
14514 #define DDRC_ZQCTL2_ZQ_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_ZQ_RESET_SHIFT)) & DDRC_ZQCTL2_ZQ_RESET_MASK)
14515 /*! @} */
14516 
14517 /*! @name ZQSTAT - ZQ Status Register */
14518 /*! @{ */
14519 
14520 #define DDRC_ZQSTAT_ZQ_RESET_BUSY_MASK           (0x1U)
14521 #define DDRC_ZQSTAT_ZQ_RESET_BUSY_SHIFT          (0U)
14522 /*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
14523  *    signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
14524  *    Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
14525  *    not to perform ZQ Reset commands when this signal is high.
14526  *  0b0..Indicates that the SoC core can initiate a ZQ Reset operation
14527  *  0b1..Indicates that ZQ Reset operation is in progress
14528  */
14529 #define DDRC_ZQSTAT_ZQ_RESET_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_ZQ_RESET_BUSY_SHIFT)) & DDRC_ZQSTAT_ZQ_RESET_BUSY_MASK)
14530 /*! @} */
14531 
14532 /*! @name DFITMG0 - DFI Timing Register 0 */
14533 /*! @{ */
14534 
14535 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK         (0x3FU)
14536 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT        (0U)
14537 /*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
14538  *    (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
14539  *    specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
14540  *    necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
14541  *    the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
14542  *    clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
14543  */
14544 #define DDRC_DFITMG0_DFI_TPHY_WRLAT(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT)) & DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK)
14545 
14546 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK        (0x3F00U)
14547 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT       (8U)
14548 /*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
14549  *    when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
14550  *    DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
14551  *    supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
14552  *    DFITMG0.dfi_wrdata_use_sdr.
14553  */
14554 #define DDRC_DFITMG0_DFI_TPHY_WRDATA(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT)) & DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK)
14555 
14556 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK     (0x8000U)
14557 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT    (15U)
14558 /*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
14559  *    HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
14560  *    is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
14561  *    DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
14562  *    HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
14563  *    for correct value.
14564  */
14565 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK)
14566 
14567 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK        (0x7F0000U)
14568 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT       (16U)
14569 /*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
14570  *    assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
14571  *    to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
14572  *    may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
14573  *    compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
14574  *    DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
14575  */
14576 #define DDRC_DFITMG0_DFI_T_RDDATA_EN(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT)) & DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK)
14577 
14578 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK     (0x800000U)
14579 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT    (23U)
14580 /*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
14581  *    using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
14582  *    DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
14583  *    clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
14584  *    value.
14585  */
14586 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK)
14587 
14588 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK       (0x1F000000U)
14589 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT      (24U)
14590 /*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
14591  *    of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
14592  *    assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
14593  *    parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
14594  *    is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
14595  *    of DFI clock.
14596  */
14597 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT)) & DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK)
14598 /*! @} */
14599 
14600 /*! @name DFITMG1 - DFI Timing Register 1 */
14601 /*! @{ */
14602 
14603 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK  (0x1FU)
14604 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U)
14605 /*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
14606  *    dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
14607  *    DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
14608  *    phase aligned, this timing parameter should be rounded up to the next integer value.
14609  */
14610 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT)) & DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK)
14611 
14612 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK (0x1F00U)
14613 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U)
14614 /*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
14615  *    dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
14616  *    boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
14617  *    this timing parameter should be rounded up to the next integer value.
14618  */
14619 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT)) & DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK)
14620 
14621 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK     (0x1F0000U)
14622 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT    (16U)
14623 /*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
14624  *    signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
14625  *    This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
14626  *    correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
14627  *    3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
14628  *    programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
14629  *    and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
14630  *    Clocks
14631  */
14632 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT)) & DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK)
14633 
14634 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK        (0x3000000U)
14635 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT       (24U)
14636 /*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
14637  *    asserted and when the associated dfi_parity_in signal is driven.
14638  */
14639 #define DDRC_DFITMG1_DFI_T_PARIN_LAT(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT)) & DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK)
14640 
14641 #define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK          (0xF0000000U)
14642 #define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT         (28U)
14643 /*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
14644  *    asserted and when the associated command is driven. This field is used for CAL mode, should be
14645  *    set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
14646  *    can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
14647  */
14648 #define DDRC_DFITMG1_DFI_T_CMD_LAT(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT)) & DDRC_DFITMG1_DFI_T_CMD_LAT_MASK)
14649 /*! @} */
14650 
14651 /*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
14652 /*! @{ */
14653 
14654 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK         (0x1U)
14655 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT        (0U)
14656 /*! dfi_lp_en_pd - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled */
14657 #define DDRC_DFILPCFG0_DFI_LP_EN_PD(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK)
14658 
14659 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK     (0xF0U)
14660 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT    (4U)
14661 /*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
14662  *    mode is entered. Determines the DFI's tlp_wakeup time:
14663  *  0b0000..16 cycles
14664  *  0b0001..32 cycles
14665  *  0b0010..64 cycles
14666  *  0b0011..128 cycles
14667  *  0b0100..256 cycles
14668  *  0b0101..512 cycles
14669  *  0b0110..1024 cycles
14670  *  0b0111..2048 cycles
14671  *  0b1000..4096 cycles
14672  *  0b1001..8192 cycles
14673  *  0b1010..16384 cycles
14674  *  0b1011..32768 cycles
14675  *  0b1100..65536 cycles
14676  *  0b1101..131072 cycles
14677  *  0b1110..262144 cycles
14678  *  0b1111..Unlimited cycles
14679  */
14680 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK)
14681 
14682 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK         (0x100U)
14683 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT        (8U)
14684 /*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
14685  *  0b0..Disabled
14686  *  0b1..Enabled
14687  */
14688 #define DDRC_DFILPCFG0_DFI_LP_EN_SR(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK)
14689 
14690 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK     (0xF000U)
14691 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT    (12U)
14692 /*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
14693  *    mode is entered. Determines the DFI's tlp_wakeup time:
14694  *  0b0000..16 cycles
14695  *  0b0001..32 cycles
14696  *  0b0010..64 cycles
14697  *  0b0011..128 cycles
14698  *  0b0100..256 cycles
14699  *  0b0101..512 cycles
14700  *  0b0110..1024 cycles
14701  *  0b0111..2048 cycles
14702  *  0b1000..4096 cycles
14703  *  0b1001..8192 cycles
14704  *  0b1010..16384 cycles
14705  *  0b1011..32768 cycles
14706  *  0b1100..65536 cycles
14707  *  0b1101..131072 cycles
14708  *  0b1110..262144 cycles
14709  *  0b1111..Unlimited cycles
14710  */
14711 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK)
14712 
14713 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK        (0x10000U)
14714 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT       (16U)
14715 /*! dfi_lp_en_dpd - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. -
14716  *    0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3
14717  *    devices.
14718  */
14719 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK)
14720 
14721 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK    (0xF00000U)
14722 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT   (20U)
14723 /*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
14724  *    Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
14725  *    supporting mDDR or LPDDR2/LPDDR3 devices.
14726  *  0b0000..16 cycles
14727  *  0b0001..32 cycles
14728  *  0b0010..64 cycles
14729  *  0b0011..128 cycles
14730  *  0b0100..256 cycles
14731  *  0b0101..512 cycles
14732  *  0b0110..1024 cycles
14733  *  0b0111..2048 cycles
14734  *  0b1000..4096 cycles
14735  *  0b1001..8192 cycles
14736  *  0b1010..16384 cycles
14737  *  0b1011..32768 cycles
14738  *  0b1100..65536 cycles
14739  *  0b1101..131072 cycles
14740  *  0b1110..262144 cycles
14741  *  0b1111..Unlimited cycles
14742  */
14743 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK)
14744 
14745 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK         (0x1F000000U)
14746 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT        (24U)
14747 /*! dfi_tlp_resp - Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both
14748  *    Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1
14749  *    specification onwards, recommends using a fixed value of 7 always.
14750  */
14751 #define DDRC_DFILPCFG0_DFI_TLP_RESP(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT)) & DDRC_DFILPCFG0_DFI_TLP_RESP_MASK)
14752 /*! @} */
14753 
14754 /*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
14755 /*! @{ */
14756 
14757 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK       (0x1U)
14758 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT      (0U)
14759 /*! dfi_lp_en_mpsm - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode
14760  *    Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4
14761  *    devices.
14762  */
14763 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT)) & DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK)
14764 
14765 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK   (0xF0U)
14766 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT  (4U)
14767 /*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
14768  *    Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
14769  *  0b0000..16 cycles
14770  *  0b0001..32 cycles
14771  *  0b0010..64 cycles
14772  *  0b0011..128 cycles
14773  *  0b0100..256 cycles
14774  *  0b0101..512 cycles
14775  *  0b0110..1024 cycles
14776  *  0b0111..2048 cycles
14777  *  0b1000..4096 cycles
14778  *  0b1001..8192 cycles
14779  *  0b1010..16384 cycles
14780  *  0b1011..32768 cycles
14781  *  0b1100..65536 cycles
14782  *  0b1101..131072 cycles
14783  *  0b1110..262144 cycles
14784  *  0b1111..Unlimited cycles
14785  */
14786 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT)) & DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK)
14787 /*! @} */
14788 
14789 /*! @name DFIUPD0 - DFI Update Register 0 */
14790 /*! @{ */
14791 
14792 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK       (0x3FFU)
14793 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT      (0U)
14794 /*! dfi_t_ctrlup_min - Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req
14795  *    signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does
14796  *    not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest
14797  *    value to assign to this variable is 0x3.
14798  */
14799 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT)) & DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK)
14800 
14801 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK       (0x3FF0000U)
14802 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT      (16U)
14803 /*! dfi_t_ctrlup_max - Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req
14804  *    signal can assert. Lowest value to assign to this variable is 0x40.
14805  */
14806 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT)) & DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK)
14807 
14808 #define DDRC_DFIUPD0_CTRLUPD_PRE_SRX_MASK        (0x20000000U)
14809 #define DDRC_DFIUPD0_CTRLUPD_PRE_SRX_SHIFT       (29U)
14810 /*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
14811  *    : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
14812  *    because no dfi_ctrlupd_req will be issued when SRX.
14813  *  0b0..send ctrlupd after SRX
14814  *  0b1..send ctrlupd before SRX
14815  */
14816 #define DDRC_DFIUPD0_CTRLUPD_PRE_SRX(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_CTRLUPD_PRE_SRX_SHIFT)) & DDRC_DFIUPD0_CTRLUPD_PRE_SRX_MASK)
14817 
14818 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK   (0x40000000U)
14819 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT  (30U)
14820 /*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
14821  *  0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
14822  *  0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
14823  */
14824 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT)) & DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK)
14825 
14826 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK       (0x80000000U)
14827 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT      (31U)
14828 /*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
14829  *  0b0..DDRC issues dfi_ctrlupd_req periodically.
14830  *  0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
14831  *       signal using register reg_ddrc_ctrlupd.
14832  */
14833 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT)) & DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK)
14834 /*! @} */
14835 
14836 /*! @name DFIUPD1 - DFI Update Register 1 */
14837 /*! @{ */
14838 
14839 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK (0xFFU)
14840 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT (0U)
14841 /*! dfi_t_ctrlupd_interval_max_x1024 - This is the maximum amount of time between DDRC initiated DFI
14842  *    update requests. This timer resets with each update request; when the timer expires
14843  *    dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
14844  *    idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used
14845  *    to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain
14846  *    calibration over PVT, but frequent updates may impact performance. Minimum allowed value for
14847  *    this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be
14848  *    greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles
14849  */
14850 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT)) & DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK)
14851 
14852 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK (0xFF0000U)
14853 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT (16U)
14854 /*! dfi_t_ctrlupd_interval_min_x1024 - This is the minimum amount of time between DDRC initiated DFI
14855  *    update requests (which is executed whenever the DDRC is idle). Set this number higher to
14856  *    reduce the frequency of update requests, which can have a small impact on the latency of the first
14857  *    read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI
14858  *    clock cycles
14859  */
14860 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT)) & DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK)
14861 /*! @} */
14862 
14863 /*! @name DFIUPD2 - DFI Update Register 2 */
14864 /*! @{ */
14865 
14866 #define DDRC_DFIUPD2_DFI_PHYUPD_EN_MASK          (0x80000000U)
14867 #define DDRC_DFIUPD2_DFI_PHYUPD_EN_SHIFT         (31U)
14868 /*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
14869  *  0b0..Disabled
14870  *  0b1..Enabled
14871  */
14872 #define DDRC_DFIUPD2_DFI_PHYUPD_EN(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_DFI_PHYUPD_EN_SHIFT)) & DDRC_DFIUPD2_DFI_PHYUPD_EN_MASK)
14873 /*! @} */
14874 
14875 /*! @name DFIMISC - DFI Miscellaneous Control Register */
14876 /*! @{ */
14877 
14878 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK   (0x1U)
14879 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT  (0U)
14880 /*! dfi_init_complete_en - PHY initialization complete enable signal. When asserted the
14881  *    dfi_init_complete signal can be used to trigger SDRAM initialisation
14882  */
14883 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT)) & DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK)
14884 
14885 #define DDRC_DFIMISC_PHY_DBI_MODE_MASK           (0x2U)
14886 #define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT          (1U)
14887 /*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
14888  *  0b0..DDRC implements DBI functionality.
14889  *  0b1..PHY implements DBI functionality.
14890  */
14891 #define DDRC_DFIMISC_PHY_DBI_MODE(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT)) & DDRC_DFIMISC_PHY_DBI_MODE_MASK)
14892 
14893 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK   (0x4U)
14894 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT  (2U)
14895 /*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
14896  *  0b0..Signals are active low
14897  *  0b1..Signals are active high
14898  */
14899 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT)) & DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK)
14900 
14901 #define DDRC_DFIMISC_CTL_IDLE_EN_MASK            (0x10U)
14902 #define DDRC_DFIMISC_CTL_IDLE_EN_SHIFT           (4U)
14903 /*! ctl_idle_en - Enables support of ctl_idle signal, which is non-DFI related pin specific to
14904  *    certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle
14905  *    functionality.
14906  */
14907 #define DDRC_DFIMISC_CTL_IDLE_EN(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_CTL_IDLE_EN_SHIFT)) & DDRC_DFIMISC_CTL_IDLE_EN_MASK)
14908 
14909 #define DDRC_DFIMISC_DFI_INIT_START_MASK         (0x20U)
14910 #define DDRC_DFIMISC_DFI_INIT_START_SHIFT        (5U)
14911 /*! dfi_init_start - PHY init start request signal.When asserted it triggers the PHY init start request */
14912 #define DDRC_DFIMISC_DFI_INIT_START(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_INIT_START_SHIFT)) & DDRC_DFIMISC_DFI_INIT_START_MASK)
14913 
14914 #define DDRC_DFIMISC_DFI_FREQUENCY_MASK          (0x1F00U)
14915 #define DDRC_DFIMISC_DFI_FREQUENCY_SHIFT         (8U)
14916 /*! dfi_frequency - Indicates the operating frequency of the system. The number of supported
14917  *    frequencies and the mapping of signal values to clock frequencies are defined by the PHY.
14918  */
14919 #define DDRC_DFIMISC_DFI_FREQUENCY(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_FREQUENCY_SHIFT)) & DDRC_DFIMISC_DFI_FREQUENCY_MASK)
14920 /*! @} */
14921 
14922 /*! @name DFITMG2 - DFI Timing Register 2 */
14923 /*! @{ */
14924 
14925 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK       (0x3FU)
14926 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT      (0U)
14927 /*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
14928  *    DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
14929  *    to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
14930  */
14931 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT)) & DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK)
14932 
14933 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK       (0x7F00U)
14934 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT      (8U)
14935 /*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
14936  *    control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
14937  *    to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
14938  */
14939 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT)) & DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK)
14940 /*! @} */
14941 
14942 /*! @name DFITMG3 - DFI Timing Register 3 */
14943 /*! @{ */
14944 
14945 #define DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_MASK   (0x1FU)
14946 #define DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_SHIFT  (0U)
14947 /*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
14948  *    ready to receive commands. Refer to PHY specification for correct value. When the controller is
14949  *    operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
14950  *    the next integer value. Unit: Clocks
14951  */
14952 #define DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_SHIFT)) & DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_MASK)
14953 /*! @} */
14954 
14955 /*! @name DFISTAT - DFI Status Register */
14956 /*! @{ */
14957 
14958 #define DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK      (0x1U)
14959 #define DDRC_DFISTAT_DFI_INIT_COMPLETE_SHIFT     (0U)
14960 /*! dfi_init_complete - The status flag register which announces when the DFI initialization has
14961  *    been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete
14962  *    flag is polled to know when the initialization is done.
14963  */
14964 #define DDRC_DFISTAT_DFI_INIT_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_DFI_INIT_COMPLETE_SHIFT)) & DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK)
14965 
14966 #define DDRC_DFISTAT_DFI_LP_ACK_MASK             (0x2U)
14967 #define DDRC_DFISTAT_DFI_LP_ACK_SHIFT            (1U)
14968 /*! dfi_lp_ack - Stores the value of the dfi_lp_ack input to the controller. */
14969 #define DDRC_DFISTAT_DFI_LP_ACK(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_DFI_LP_ACK_SHIFT)) & DDRC_DFISTAT_DFI_LP_ACK_MASK)
14970 /*! @} */
14971 
14972 /*! @name DBICTL - DM/DBI Control Register */
14973 /*! @{ */
14974 
14975 #define DDRC_DBICTL_DM_EN_MASK                   (0x1U)
14976 #define DDRC_DBICTL_DM_EN_SHIFT                  (0U)
14977 /*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
14978  *    register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
14979  *    must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
14980  *    from this signal
14981  *  0b0..DM is disabled
14982  *  0b1..DM is enabled
14983  */
14984 #define DDRC_DBICTL_DM_EN(x)                     (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_DM_EN_SHIFT)) & DDRC_DBICTL_DM_EN_MASK)
14985 
14986 #define DDRC_DBICTL_WR_DBI_EN_MASK               (0x2U)
14987 #define DDRC_DBICTL_WR_DBI_EN_SHIFT              (1U)
14988 /*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
14989  *    When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
14990  *  0b0..Write DBI is disabled
14991  *  0b1..Write DBI is enabled.
14992  */
14993 #define DDRC_DBICTL_WR_DBI_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_WR_DBI_EN_SHIFT)) & DDRC_DBICTL_WR_DBI_EN_MASK)
14994 
14995 #define DDRC_DBICTL_RD_DBI_EN_MASK               (0x4U)
14996 #define DDRC_DBICTL_RD_DBI_EN_SHIFT              (2U)
14997 /*! rd_dbi_en - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is
14998  *    enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When
14999  *    x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
15000  */
15001 #define DDRC_DBICTL_RD_DBI_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_RD_DBI_EN_SHIFT)) & DDRC_DBICTL_RD_DBI_EN_MASK)
15002 /*! @} */
15003 
15004 /*! @name ADDRMAP0 - Address Map Register 0 */
15005 /*! @{ */
15006 
15007 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK       (0x1FU)
15008 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT      (0U)
15009 /*! addrmap_cs_bit0 - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28,
15010  *    and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
15011  *    to the value of this field. If set to 31, rank address bit 0 is set to 0.
15012  */
15013 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT)) & DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK)
15014 /*! @} */
15015 
15016 /*! @name ADDRMAP1 - Address Map Register 1 */
15017 /*! @{ */
15018 
15019 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK       (0x1FU)
15020 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT      (0U)
15021 /*! addrmap_bank_b0 - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31
15022  *    Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined
15023  *    by adding the internal base to the value of this field.
15024  */
15025 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT)) & DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK)
15026 
15027 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK       (0x1F00U)
15028 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT      (8U)
15029 /*! addrmap_bank_b1 - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31
15030  *    Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined
15031  *    by adding the internal base to the value of this field.
15032  */
15033 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT)) & DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK)
15034 
15035 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK       (0x1F0000U)
15036 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT      (16U)
15037 /*! addrmap_bank_b2 - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30
15038  *    and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
15039  *    to the value of this field. If set to 31, bank address bit 2 is set to 0.
15040  */
15041 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT)) & DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK)
15042 /*! @} */
15043 
15044 /*! @name ADDRMAP2 - Address Map Register 2 */
15045 /*! @{ */
15046 
15047 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK        (0xFU)
15048 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT       (0U)
15049 /*! addrmap_col_b2 - - Full bus width mode: Selects the HIF address bit used as column address bit
15050  *    2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter
15051  *    bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7
15052  *    Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the
15053  *    value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to
15054  *    program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and -
15055  *    PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and
15056  *    ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to
15057  *    0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1
15058  *    and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus
15059  *    Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to
15060  *    column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it
15061  *    is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If
15062  *    MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0
15063  *    so that HIF[2] maps to column address bit 3.
15064  */
15065 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK)
15066 
15067 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK        (0xF00U)
15068 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT       (8U)
15069 /*! addrmap_col_b3 - - Full bus width mode: Selects the HIF address bit used as column address bit
15070  *    3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter
15071  *    bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7
15072  *    Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the
15073  *    value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width
15074  *    (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0.
15075  */
15076 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK)
15077 
15078 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK        (0xF0000U)
15079 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT       (16U)
15080 /*! addrmap_col_b4 - - Full bus width mode: Selects the HIF address bit used as column address bit
15081  *    4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter
15082  *    bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7,
15083  *    and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
15084  *    to the value of this field. If set to 15, this column address bit is set to 0.
15085  */
15086 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK)
15087 
15088 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK        (0xF000000U)
15089 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT       (24U)
15090 /*! addrmap_col_b5 - - Full bus width mode: Selects the HIF address bit used as column address bit
15091  *    5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter
15092  *    bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7,
15093  *    and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal
15094  *    base to the value of this field. If set to 15, this column address bit is set to 0.
15095  */
15096 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK)
15097 /*! @} */
15098 
15099 /*! @name ADDRMAP3 - Address Map Register 3 */
15100 /*! @{ */
15101 
15102 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK        (0xFU)
15103 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT       (0U)
15104 /*! addrmap_col_b6 - - Full bus width mode: Selects the HIF address bit used as column address bit
15105  *    6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter
15106  *    bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7,
15107  *    and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
15108  *    to the value of this field. If set to 15, this column address bit is set to 0.
15109  */
15110 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK)
15111 
15112 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK        (0xF00U)
15113 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT       (8U)
15114 /*! addrmap_col_b7 - - Full bus width mode: Selects the HIF address bit used as column address bit
15115  *    7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter
15116  *    bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7,
15117  *    and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base
15118  *    to the value of this field. If set to 15, this column address bit is set to 0.
15119  */
15120 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK)
15121 
15122 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK        (0xF0000U)
15123 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT       (16U)
15124 /*! addrmap_col_b8 - - Full bus width mode: Selects the HIF address bit used as column address bit
15125  *    8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter
15126  *    bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3
15127  *    mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined
15128  *    by adding the internal base to the value of this field. If set to 15, this column address bit
15129  *    is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
15130  *    indicating auto-precharge, and hence no source address bit can be mapped to column address
15131  *    bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
15132  *    column bit 10 is used.
15133  */
15134 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK)
15135 
15136 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK        (0xF000000U)
15137 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT       (24U)
15138 /*! addrmap_col_b9 - - Full bus width mode: Selects the HIF address bit used as column address bit
15139  *    9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
15140  *    LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address
15141  *    bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
15142  *    HIF address bit is determined by adding the internal base to the value of this field. If set to
15143  *    15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
15144  *    address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
15145  *    mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
15146  *    auto-precharge in the CA bus and hence column bit 10 is used.
15147  */
15148 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK)
15149 /*! @} */
15150 
15151 /*! @name ADDRMAP4 - Address Map Register 4 */
15152 /*! @{ */
15153 
15154 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK       (0xFU)
15155 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT      (0U)
15156 /*! addrmap_col_b10 - - Full bus width mode: Selects the HIF address bit used as column address bit
15157  *    11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as
15158  *    column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it
15159  *    unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
15160  *    address bit is determined by adding the internal base to the value of this field. If set to
15161  *    15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
15162  *    address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
15163  *    mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge
15164  *    in the CA bus and hence column bit 10 is used.
15165  */
15166 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT)) & DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK)
15167 
15168 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK       (0xF00U)
15169 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT      (8U)
15170 /*! addrmap_col_b11 - - Full bus width mode: Selects the HIF address bit used as column address bit
15171  *    13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should
15172  *    be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to
15173  *    4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by
15174  *    adding the internal base to the value of this field. If set to 15, this column address bit is
15175  *    set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
15176  *    indicating auto-precharge, and hence no source address bit can be mapped to column address bit
15177  *    10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column
15178  *    bit 10 is used.
15179  */
15180 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT)) & DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK)
15181 /*! @} */
15182 
15183 /*! @name ADDRMAP5 - Address Map Register 5 */
15184 /*! @{ */
15185 
15186 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK        (0xFU)
15187 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT       (0U)
15188 /*! addrmap_row_b0 - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11
15189  *    Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by
15190  *    adding the internal base to the value of this field.
15191  */
15192 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK)
15193 
15194 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK        (0xF00U)
15195 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT       (8U)
15196 /*! addrmap_row_b1 - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11
15197  *    Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by
15198  *    adding the internal base to the value of this field.
15199  */
15200 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK)
15201 
15202 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK     (0xF0000U)
15203 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT    (16U)
15204 /*! addrmap_row_b2_10 - Selects the HIF address bits used as row address bits 2 to 10. Valid Range:
15205  *    0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for
15206  *    row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit
15207  *    for each of the row address bits is determined by adding the internal base to the value of this
15208  *    field. When value 15 is used the values of row address bits 2 to 10 are defined by registers
15209  *    ADDRMAP9, ADDRMAP10, ADDRMAP11.
15210  */
15211 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK)
15212 
15213 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK       (0xF000000U)
15214 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT      (24U)
15215 /*! addrmap_row_b11 - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11,
15216  *    and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal
15217  *    base to the value of this field. If set to 15, row address bit 11 is set to 0.
15218  */
15219 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK)
15220 /*! @} */
15221 
15222 /*! @name ADDRMAP6 - Address Map Register 6 */
15223 /*! @{ */
15224 
15225 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK       (0xFU)
15226 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT      (0U)
15227 /*! addrmap_row_b12 - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11,
15228  *    and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal
15229  *    base to the value of this field. If set to 15, row address bit 12 is set to 0.
15230  */
15231 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK)
15232 
15233 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK       (0xF00U)
15234 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT      (8U)
15235 /*! addrmap_row_b13 - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11,
15236  *    and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal
15237  *    base to the value of this field. If set to 15, row address bit 13 is set to 0.
15238  */
15239 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK)
15240 
15241 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK       (0xF0000U)
15242 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT      (16U)
15243 /*! addrmap_row_b14 - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11,
15244  *    and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal
15245  *    base to the value of this field. If set to 15, row address bit 14 is set to 0.
15246  */
15247 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK)
15248 
15249 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK       (0xF000000U)
15250 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT      (24U)
15251 /*! addrmap_row_b15 - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11,
15252  *    and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal
15253  *    base to the value of this field. If set to 15, row address bit 15 is set to 0.
15254  */
15255 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK)
15256 
15257 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK       (0x80000000U)
15258 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT      (31U)
15259 /*! lpddr3_6gb_12gb - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 -
15260  *    LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as
15261  *    invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs
15262  *    configured to support LPDDR3.
15263  */
15264 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT)) & DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK)
15265 /*! @} */
15266 
15267 /*! @name ADDRMAP7 - Address Map Register 7 */
15268 /*! @{ */
15269 
15270 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK       (0xFU)
15271 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT      (0U)
15272 /*! addrmap_row_b16 - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11,
15273  *    and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal
15274  *    base to the value of this field. If set to 15, row address bit 16 is set to 0.
15275  */
15276 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT)) & DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK)
15277 
15278 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK       (0xF00U)
15279 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT      (8U)
15280 /*! addrmap_row_b17 - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11,
15281  *    and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal
15282  *    base to the value of this field. If set to 15, row address bit 17 is set to 0.
15283  */
15284 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT)) & DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK)
15285 /*! @} */
15286 
15287 /*! @name ADDRMAP8 - Address Map Register 8 */
15288 /*! @{ */
15289 
15290 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK         (0x1FU)
15291 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT        (0U)
15292 /*! addrmap_bg_b0 - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to
15293  *    31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is
15294  *    determined by adding the internal base to the value of this field.
15295  */
15296 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT)) & DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK)
15297 
15298 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK         (0x3F00U)
15299 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT        (8U)
15300 /*! addrmap_bg_b1 - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to
15301  *    31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address
15302  *    bits is determined by adding the internal base to the value of this field. If set to 63, bank
15303  *    group address bit 1 is set to 0.
15304  */
15305 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT)) & DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK)
15306 /*! @} */
15307 
15308 /*! @name ADDRMAP9 - Address Map Register 9 */
15309 /*! @{ */
15310 
15311 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK        (0xFU)
15312 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT       (0U)
15313 /*! addrmap_row_b2 - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11
15314  *    Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by
15315  *    adding the internal base to the value of this field. This register field is used only when
15316  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15317  */
15318 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK)
15319 
15320 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK        (0xF00U)
15321 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT       (8U)
15322 /*! addrmap_row_b3 - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11
15323  *    Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by
15324  *    adding the internal base to the value of this field. This register field is used only when
15325  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15326  */
15327 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK)
15328 
15329 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK        (0xF0000U)
15330 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT       (16U)
15331 /*! addrmap_row_b4 - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11
15332  *    Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by
15333  *    adding the internal base to the value of this field. This register field is used only when
15334  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15335  */
15336 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK)
15337 
15338 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK        (0xF000000U)
15339 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT       (24U)
15340 /*! addrmap_row_b5 - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11
15341  *    Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by
15342  *    adding the internal base to the value of this field. This register field is used only when
15343  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15344  */
15345 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK)
15346 /*! @} */
15347 
15348 /*! @name ADDRMAP10 - Address Map Register 10 */
15349 /*! @{ */
15350 
15351 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK       (0xFU)
15352 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT      (0U)
15353 /*! addrmap_row_b6 - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11
15354  *    Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by
15355  *    adding the internal base to the value of this field. This register field is used only when
15356  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15357  */
15358 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK)
15359 
15360 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK       (0xF00U)
15361 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT      (8U)
15362 /*! addrmap_row_b7 - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11
15363  *    Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by
15364  *    adding the internal base to the value of this field. This register field is used only when
15365  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15366  */
15367 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK)
15368 
15369 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK       (0xF0000U)
15370 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT      (16U)
15371 /*! addrmap_row_b8 - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11
15372  *    Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by
15373  *    adding the internal base to the value of this field. This register field is used only when
15374  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15375  */
15376 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK)
15377 
15378 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK       (0xF000000U)
15379 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT      (24U)
15380 /*! addrmap_row_b9 - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11
15381  *    Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by
15382  *    adding the internal base to the value of this field. This register field is used only when
15383  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15384  */
15385 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK)
15386 /*! @} */
15387 
15388 /*! @name ADDRMAP11 - Address Map Register 11 */
15389 /*! @{ */
15390 
15391 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK      (0xFU)
15392 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT     (0U)
15393 /*! addrmap_row_b10 - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11
15394  *    Internal Base: 16 The selected HIF address bit for each of the row address bits is determined
15395  *    by adding the internal base to the value of this field. This register field is used only when
15396  *    ADDRMAP5.addrmap_row_b2_10 is set to value 15.
15397  */
15398 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT)) & DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK)
15399 /*! @} */
15400 
15401 /*! @name ODTCFG - ODT Configuration Register */
15402 /*! @{ */
15403 
15404 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK            (0x7CU)
15405 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT           (2U)
15406 /*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
15407  *    values associated with that command. ODT setting must remain constant for the entire time that
15408  *    DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
15409  *    (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
15410  *    CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
15411  *    mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
15412  *    preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
15413  *    not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
15414  */
15415 #define DDRC_ODTCFG_RD_ODT_DELAY(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_RD_ODT_DELAY_MASK)
15416 
15417 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK             (0xF00U)
15418 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT            (8U)
15419 /*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
15420  *    is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
15421  *    DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
15422  *    write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
15423  *    RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
15424  */
15425 #define DDRC_ODTCFG_RD_ODT_HOLD(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_RD_ODT_HOLD_MASK)
15426 
15427 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK            (0x1F0000U)
15428 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT           (16U)
15429 /*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
15430  *    values associated with that command. ODT setting must remain constant for the entire time that
15431  *    DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
15432  *    AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
15433  *    for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
15434  *    - WL - 1 - RU(tODTon(max)/tCK))
15435  */
15436 #define DDRC_ODTCFG_WR_ODT_DELAY(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_WR_ODT_DELAY_MASK)
15437 
15438 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK             (0xF000000U)
15439 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT            (24U)
15440 /*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
15441  *    is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
15442  *    - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
15443  *    5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
15444  *    CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
15445  */
15446 #define DDRC_ODTCFG_WR_ODT_HOLD(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_WR_ODT_HOLD_MASK)
15447 /*! @} */
15448 
15449 /*! @name ODTMAP - ODT/Rank Map Register */
15450 /*! @{ */
15451 
15452 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK            (0x3U)
15453 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT           (0U)
15454 /*! rank0_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank
15455  *    has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
15456  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
15457  *    rank, set its bit to 1 to enable its ODT.
15458  */
15459 #define DDRC_ODTMAP_RANK0_WR_ODT(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT)) & DDRC_ODTMAP_RANK0_WR_ODT_MASK)
15460 
15461 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK            (0x30U)
15462 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT           (4U)
15463 /*! rank0_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 0. Each
15464  *    rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
15465  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
15466  *    rank, set its bit to 1 to enable its ODT.
15467  */
15468 #define DDRC_ODTMAP_RANK0_RD_ODT(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT)) & DDRC_ODTMAP_RANK0_RD_ODT_MASK)
15469 
15470 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK            (0x300U)
15471 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT           (8U)
15472 /*! rank1_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank
15473  *    has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
15474  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
15475  *    rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
15476  */
15477 #define DDRC_ODTMAP_RANK1_WR_ODT(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT)) & DDRC_ODTMAP_RANK1_WR_ODT_MASK)
15478 
15479 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK            (0x3000U)
15480 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT           (12U)
15481 /*! rank1_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 1. Each
15482  *    rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
15483  *    Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
15484  *    rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more
15485  *    ranks
15486  */
15487 #define DDRC_ODTMAP_RANK1_RD_ODT(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT)) & DDRC_ODTMAP_RANK1_RD_ODT_MASK)
15488 /*! @} */
15489 
15490 /*! @name SCHED - Scheduler Control Register */
15491 /*! @{ */
15492 
15493 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK          (0x1U)
15494 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT         (0U)
15495 /*! force_low_pri_n - Active low signal. When asserted ('0'), all incoming transactions are forced
15496  *    to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read
15497  *    commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all
15498  *    Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands.
15499  *    Forcing the incoming transactions to low priority implicitly turns off Bypass path for read
15500  *    commands. FOR PERFORMANCE ONLY.
15501  */
15502 #define DDRC_SCHED_FORCE_LOW_PRI_N(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT)) & DDRC_SCHED_FORCE_LOW_PRI_N_MASK)
15503 
15504 #define DDRC_SCHED_PREFER_WRITE_MASK             (0x2U)
15505 #define DDRC_SCHED_PREFER_WRITE_SHIFT            (1U)
15506 /*! prefer_write - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. */
15507 #define DDRC_SCHED_PREFER_WRITE(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_PREFER_WRITE_SHIFT)) & DDRC_SCHED_PREFER_WRITE_MASK)
15508 
15509 #define DDRC_SCHED_PAGECLOSE_MASK                (0x4U)
15510 #define DDRC_SCHED_PAGECLOSE_SHIFT               (2U)
15511 /*! pageclose - If true, bank is kept open only while there are page hit transactions available in
15512  *    the CAM to that bank. The last read or write command in the CAM with a bank and page hit will
15513  *    be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and
15514  *    SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued
15515  *    in some cases where there is a mode switch between Write and Read or between LPR and HPR. The
15516  *    Read and Write commands that are executed as part of the ECC scrub requests are also executed
15517  *    without auto-precharge. If false, the bank remains open until there is a need to close it (to
15518  *    open a different page, or for page timeout or refresh timeout) - also known as open page
15519  *    policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF
15520  *    interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page
15521  *    policies. FOR PERFORMANCE ONLY.
15522  */
15523 #define DDRC_SCHED_PAGECLOSE(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_PAGECLOSE_SHIFT)) & DDRC_SCHED_PAGECLOSE_MASK)
15524 
15525 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK          (0x1F00U)
15526 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT         (8U)
15527 /*! lpr_num_entries - Number of entries in the low priority transaction store is this value + 1.
15528  *    (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high
15529  *    priority transaction store. Setting this to maximum value allocates all entries to low
15530  *    priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and
15531  *    the rest to high priority transaction store. Note: In ECC configurations, the numbers of
15532  *    write and low priority read credits issued is one less than in the non-ECC case. One entry each is
15533  *    reserved in the write and low-priority read CAMs for storing the RMW requests arising out of
15534  *    single bit error correction RMW operation.
15535  */
15536 #define DDRC_SCHED_LPR_NUM_ENTRIES(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT)) & DDRC_SCHED_LPR_NUM_ENTRIES_MASK)
15537 
15538 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK   (0xFF0000U)
15539 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT  (16U)
15540 /*! go2critical_hysteresis - UNUSED */
15541 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT)) & DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK)
15542 
15543 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK            (0x7F000000U)
15544 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT           (24U)
15545 /*! rdwr_idle_gap - When the preferred transaction store is empty for these many clock cycles,
15546  *    switch to the alternate transaction store if it is non-empty. The read transaction store (both high
15547  *    and low priority) is the default preferred transaction store and the write transaction store
15548  *    is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal
15549  *    value for this register. When set to 0x0, the transaction store switching will happen
15550  *    immediately when the switching conditions become true. FOR PERFORMANCE ONLY
15551  */
15552 #define DDRC_SCHED_RDWR_IDLE_GAP(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT)) & DDRC_SCHED_RDWR_IDLE_GAP_MASK)
15553 /*! @} */
15554 
15555 /*! @name SCHED1 - Scheduler Control Register 1 */
15556 /*! @{ */
15557 
15558 #define DDRC_SCHED1_PAGECLOSE_TIMER_MASK         (0xFFU)
15559 #define DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT        (0U)
15560 /*! pageclose_timer - This field works in conjunction with SCHED.pageclose. It only has meaning if
15561  *    SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be
15562  *    scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes
15563  *    an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for
15564  *    details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an
15565  *    auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit.
15566  *    Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per
15567  *    bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page
15568  *    hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a
15569  *    page hit. Once the timer has reached zero, an explcit precharge will be attempted to be
15570  *    scheduled.
15571  */
15572 #define DDRC_SCHED1_PAGECLOSE_TIMER(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT)) & DDRC_SCHED1_PAGECLOSE_TIMER_MASK)
15573 /*! @} */
15574 
15575 /*! @name PERFHPR1 - High Priority Read CAM Register 1 */
15576 /*! @{ */
15577 
15578 #define DDRC_PERFHPR1_HPR_MAX_STARVE_MASK        (0xFFFFU)
15579 #define DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT       (0U)
15580 /*! hpr_max_starve - Number of DFI clocks that the HPR queue can be starved before it goes critical.
15581  *    The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
15582  *    disable the starvation functionality; during normal operation, this function should not be disabled
15583  *    as it will cause excessive latencies. FOR PERFORMANCE ONLY.
15584  */
15585 #define DDRC_PERFHPR1_HPR_MAX_STARVE(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT)) & DDRC_PERFHPR1_HPR_MAX_STARVE_MASK)
15586 
15587 #define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK   (0xFF000000U)
15588 #define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT  (24U)
15589 /*! hpr_xact_run_length - Number of transactions that are serviced once the HPR queue goes critical
15590  *    is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
15591  *    Transaction. FOR PERFORMANCE ONLY.
15592  */
15593 #define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT)) & DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK)
15594 /*! @} */
15595 
15596 /*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
15597 /*! @{ */
15598 
15599 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK        (0xFFFFU)
15600 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT       (0U)
15601 /*! lpr_max_starve - Number of DFI clocks that the LPR queue can be starved before it goes critical.
15602  *    The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
15603  *    disable the starvation functionality; during normal operation, this function should not be disabled
15604  *    as it will cause excessive latencies. FOR PERFORMANCE ONLY.
15605  */
15606 #define DDRC_PERFLPR1_LPR_MAX_STARVE(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT)) & DDRC_PERFLPR1_LPR_MAX_STARVE_MASK)
15607 
15608 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK   (0xFF000000U)
15609 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT  (24U)
15610 /*! lpr_xact_run_length - Number of transactions that are serviced once the LPR queue goes critical
15611  *    is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
15612  *    Transaction. FOR PERFORMANCE ONLY.
15613  */
15614 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT)) & DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK)
15615 /*! @} */
15616 
15617 /*! @name PERFWR1 - Write CAM Register 1 */
15618 /*! @{ */
15619 
15620 #define DDRC_PERFWR1_W_MAX_STARVE_MASK           (0xFFFFU)
15621 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT          (0U)
15622 /*! w_max_starve - Number of DFI clocks that the WR queue can be starved before it goes critical.
15623  *    The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable
15624  *    the starvation functionality; during normal operation, this function should not be disabled as
15625  *    it will cause excessive latencies. FOR PERFORMANCE ONLY.
15626  */
15627 #define DDRC_PERFWR1_W_MAX_STARVE(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_W_MAX_STARVE_SHIFT)) & DDRC_PERFWR1_W_MAX_STARVE_MASK)
15628 
15629 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK      (0xFF000000U)
15630 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT     (24U)
15631 /*! w_xact_run_length - Number of transactions that are serviced once the WR queue goes critical is
15632  *    the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction.
15633  *    FOR PERFORMANCE ONLY.
15634  */
15635 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT)) & DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK)
15636 /*! @} */
15637 
15638 /*! @name DBG0 - Debug Register 0 */
15639 /*! @{ */
15640 
15641 #define DDRC_DBG0_DIS_WC_MASK                    (0x1U)
15642 #define DDRC_DBG0_DIS_WC_SHIFT                   (0U)
15643 /*! dis_wc - When 1, disable write combine. FOR DEBUG ONLY */
15644 #define DDRC_DBG0_DIS_WC(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_WC_SHIFT)) & DDRC_DBG0_DIS_WC_MASK)
15645 
15646 #define DDRC_DBG0_DIS_RD_BYPASS_MASK             (0x2U)
15647 #define DDRC_DBG0_DIS_RD_BYPASS_SHIFT            (1U)
15648 /*! dis_rd_bypass - Only present in designs supporting read bypass. When 1, disable bypass path for
15649  *    high priority read page hits FOR DEBUG ONLY.
15650  */
15651 #define DDRC_DBG0_DIS_RD_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_RD_BYPASS_SHIFT)) & DDRC_DBG0_DIS_RD_BYPASS_MASK)
15652 
15653 #define DDRC_DBG0_DIS_ACT_BYPASS_MASK            (0x4U)
15654 #define DDRC_DBG0_DIS_ACT_BYPASS_SHIFT           (2U)
15655 /*! dis_act_bypass - Only present in designs supporting activate bypass. When 1, disable bypass path
15656  *    for high priority read activates FOR DEBUG ONLY.
15657  */
15658 #define DDRC_DBG0_DIS_ACT_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_ACT_BYPASS_SHIFT)) & DDRC_DBG0_DIS_ACT_BYPASS_MASK)
15659 
15660 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK    (0x10U)
15661 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT   (4U)
15662 /*! dis_collision_page_opt - When this is set to '0', auto-precharge is disabled for the flushed
15663  *    command in a collision case. Collision cases are write followed by read to same address, read
15664  *    followed by write to same address, or write followed by write to same address with DBG0.dis_wc
15665  *    bit = 1 (where same address comparisons exclude the two address bits representing critical
15666  *    word). FOR DEBUG ONLY.
15667  */
15668 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT)) & DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK)
15669 /*! @} */
15670 
15671 /*! @name DBG1 - Debug Register 1 */
15672 /*! @{ */
15673 
15674 #define DDRC_DBG1_DIS_DQ_MASK                    (0x1U)
15675 #define DDRC_DBG1_DIS_DQ_SHIFT                   (0U)
15676 /*! dis_dq - When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled.
15677  *    All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this
15678  *    is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which
15679  *    makes it safe to modify certain register fields associated with reads and writes (see User
15680  *    Guide for details). After setting this bit, it is strongly recommended to poll
15681  *    DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which
15682  *    affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit
15683  *    is intended to be switched on-the-fly.
15684  */
15685 #define DDRC_DBG1_DIS_DQ(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_DIS_DQ_SHIFT)) & DDRC_DBG1_DIS_DQ_MASK)
15686 
15687 #define DDRC_DBG1_DIS_HIF_MASK                   (0x2U)
15688 #define DDRC_DBG1_DIS_HIF_SHIFT                  (1U)
15689 /*! dis_hif - When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the
15690  *    hif_cmd_valid and all other associated request signals. This bit is intended to be switched
15691  *    on-the-fly.
15692  */
15693 #define DDRC_DBG1_DIS_HIF(x)                     (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_DIS_HIF_SHIFT)) & DDRC_DBG1_DIS_HIF_MASK)
15694 /*! @} */
15695 
15696 /*! @name DBGCAM - CAM Debug Register */
15697 /*! @{ */
15698 
15699 #define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK         (0x3FU)
15700 #define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT        (0U)
15701 /*! dbg_hpr_q_depth - High priority read queue depth FOR DEBUG ONLY */
15702 #define DDRC_DBGCAM_DBG_HPR_Q_DEPTH(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT)) & DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK)
15703 
15704 #define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK         (0x3F00U)
15705 #define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT        (8U)
15706 /*! dbg_lpr_q_depth - Low priority read queue depth The last entry of Lpr queue is reserved for ECC
15707  *    SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG
15708  *    ONLY
15709  */
15710 #define DDRC_DBGCAM_DBG_LPR_Q_DEPTH(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT)) & DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK)
15711 
15712 #define DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK           (0x3F0000U)
15713 #define DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT          (16U)
15714 /*! dbg_w_q_depth - Write queue depth The last entry of WR queue is reserved for ECC SCRUB
15715  *    operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY
15716  */
15717 #define DDRC_DBGCAM_DBG_W_Q_DEPTH(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT)) & DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK)
15718 
15719 #define DDRC_DBGCAM_DBG_STALL_MASK               (0x1000000U)
15720 #define DDRC_DBGCAM_DBG_STALL_SHIFT              (24U)
15721 /*! dbg_stall - Stall FOR DEBUG ONLY */
15722 #define DDRC_DBGCAM_DBG_STALL(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_STALL_SHIFT)) & DDRC_DBGCAM_DBG_STALL_MASK)
15723 
15724 #define DDRC_DBGCAM_DBG_RD_Q_EMPTY_MASK          (0x2000000U)
15725 #define DDRC_DBGCAM_DBG_RD_Q_EMPTY_SHIFT         (25U)
15726 /*! dbg_rd_q_empty - When 1, all the Read command queues and Read data buffers inside DDRC are
15727  *    empty. This register is to be used for debug purpose. An example use-case scenario: When Controller
15728  *    enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
15729  *    executed all the commands in its queues and the write and read data drained. Hence this register
15730  *    should be 1 at that time. FOR DEBUG ONLY
15731  */
15732 #define DDRC_DBGCAM_DBG_RD_Q_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_RD_Q_EMPTY_SHIFT)) & DDRC_DBGCAM_DBG_RD_Q_EMPTY_MASK)
15733 
15734 #define DDRC_DBGCAM_DBG_WR_Q_EMPTY_MASK          (0x4000000U)
15735 #define DDRC_DBGCAM_DBG_WR_Q_EMPTY_SHIFT         (26U)
15736 /*! dbg_wr_q_empty - When 1, all the Write command queues and Write data buffers inside DDRC are
15737  *    empty. This register is to be used for debug purpose. An example use-case scenario: When
15738  *    Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
15739  *    executed all the commands in its queues and the write and read data drained. Hence this register
15740  *    should be 1 at that time. FOR DEBUG ONLY
15741  */
15742 #define DDRC_DBGCAM_DBG_WR_Q_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_WR_Q_EMPTY_SHIFT)) & DDRC_DBGCAM_DBG_WR_Q_EMPTY_MASK)
15743 
15744 #define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK  (0x10000000U)
15745 #define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT (28U)
15746 /*! rd_data_pipeline_empty - This bit indicates that the read data pipeline on the DFI interface is
15747  *    empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
15748  *    ensure that all remaining commands/data have completed.
15749  */
15750 #define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT)) & DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK)
15751 
15752 #define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK  (0x20000000U)
15753 #define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT (29U)
15754 /*! wr_data_pipeline_empty - This bit indicates that the write data pipeline on the DFI interface is
15755  *    empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
15756  *    ensure that all remaining commands/data have completed.
15757  */
15758 #define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT)) & DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK)
15759 
15760 #define DDRC_DBGCAM_DBG_STALL_WR_MASK            (0x40000000U)
15761 #define DDRC_DBGCAM_DBG_STALL_WR_SHIFT           (30U)
15762 /*! dbg_stall_wr - Stall for Write channel FOR DEBUG ONLY */
15763 #define DDRC_DBGCAM_DBG_STALL_WR(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_STALL_WR_SHIFT)) & DDRC_DBGCAM_DBG_STALL_WR_MASK)
15764 
15765 #define DDRC_DBGCAM_DBG_STALL_RD_MASK            (0x80000000U)
15766 #define DDRC_DBGCAM_DBG_STALL_RD_SHIFT           (31U)
15767 /*! dbg_stall_rd - Stall for Read channel FOR DEBUG ONLY */
15768 #define DDRC_DBGCAM_DBG_STALL_RD(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_STALL_RD_SHIFT)) & DDRC_DBGCAM_DBG_STALL_RD_MASK)
15769 /*! @} */
15770 
15771 /*! @name DBGCMD - Command Debug Register */
15772 /*! @{ */
15773 
15774 #define DDRC_DBGCMD_RANK0_REFRESH_MASK           (0x1U)
15775 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT          (0U)
15776 /*! rank0_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
15777  *    0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When
15778  *    DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
15779  *    to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
15780  *    recommended NOT to set this register bit if in Init or Deep power-down operating modes or
15781  *    Maximum Power Saving Mode.
15782  */
15783 #define DDRC_DBGCMD_RANK0_REFRESH(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_RANK0_REFRESH_SHIFT)) & DDRC_DBGCMD_RANK0_REFRESH_MASK)
15784 
15785 #define DDRC_DBGCMD_RANK1_REFRESH_MASK           (0x2U)
15786 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT          (1U)
15787 /*! rank1_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
15788  *    1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When
15789  *    DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
15790  *    to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
15791  *    recommended NOT to set this register bit if in Init or Deep power-down operating modes or
15792  *    Maximum Power Saving Mode.
15793  */
15794 #define DDRC_DBGCMD_RANK1_REFRESH(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_RANK1_REFRESH_SHIFT)) & DDRC_DBGCMD_RANK1_REFRESH_MASK)
15795 
15796 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK          (0x10U)
15797 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT         (4U)
15798 /*! zq_calib_short - Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ
15799  *    calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the
15800  *    DDRC, the bit is automatically cleared. This operation can be performed only when
15801  *    ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register
15802  *    bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep
15803  *    power-down operating modes and Maximum Power Saving Mode.
15804  */
15805 #define DDRC_DBGCMD_ZQ_CALIB_SHORT(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT)) & DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK)
15806 
15807 #define DDRC_DBGCMD_CTRLUPD_MASK                 (0x20U)
15808 #define DDRC_DBGCMD_CTRLUPD_SHIFT                (5U)
15809 /*! ctrlupd - Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the
15810  *    PHY. When this request is stored in the DDRC, the bit is automatically cleared. This
15811  *    operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
15812  */
15813 #define DDRC_DBGCMD_CTRLUPD(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_CTRLUPD_SHIFT)) & DDRC_DBGCMD_CTRLUPD_MASK)
15814 /*! @} */
15815 
15816 /*! @name DBGSTAT - Status Debug Register */
15817 /*! @{ */
15818 
15819 #define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_MASK     (0x1U)
15820 #define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT    (0U)
15821 /*! rank0_refresh_busy - SoC core may initiate a rank0_refresh operation (refresh operation to rank
15822  *    0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh
15823  *    is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is
15824  *    recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that
15825  *    the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh
15826  *    operation has not been stored yet in the DDRC
15827  */
15828 #define DDRC_DBGSTAT_RANK0_REFRESH_BUSY(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT)) & DDRC_DBGSTAT_RANK0_REFRESH_BUSY_MASK)
15829 
15830 #define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_MASK     (0x2U)
15831 #define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT    (1U)
15832 /*! rank1_refresh_busy - SoC core may initiate a rank1_refresh operation (refresh operation to rank
15833  *    1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh
15834  *    is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is
15835  *    recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that
15836  *    the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh
15837  *    operation has not been stored yet in the DDRC
15838  */
15839 #define DDRC_DBGSTAT_RANK1_REFRESH_BUSY(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT)) & DDRC_DBGSTAT_RANK1_REFRESH_BUSY_MASK)
15840 
15841 #define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK    (0x10U)
15842 #define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT   (4U)
15843 /*! zq_calib_short_busy - SoC core may initiate a ZQCS (ZQ calibration short) operation only if this
15844  *    signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It
15845  *    goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform
15846  *    ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS
15847  *    operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC
15848  */
15849 #define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT)) & DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK)
15850 
15851 #define DDRC_DBGSTAT_CTRLUPD_BUSY_MASK           (0x20U)
15852 #define DDRC_DBGSTAT_CTRLUPD_BUSY_SHIFT          (5U)
15853 /*! ctrlupd_busy - SoC core may initiate a ctrlupd operation only if this signal is low. This signal
15854  *    goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the
15855  *    ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations
15856  *    when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1
15857  *    - Indicates that ctrlupd operation has not been initiated yet in the DDRC
15858  */
15859 #define DDRC_DBGSTAT_CTRLUPD_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_CTRLUPD_BUSY_SHIFT)) & DDRC_DBGSTAT_CTRLUPD_BUSY_MASK)
15860 /*! @} */
15861 
15862 /*! @name SWCTL - Software Register Programming Control Enable */
15863 /*! @{ */
15864 
15865 #define DDRC_SWCTL_SW_DONE_MASK                  (0x1U)
15866 #define DDRC_SWCTL_SW_DONE_SHIFT                 (0U)
15867 /*! sw_done - Enable quasi-dynamic register programming outside reset. Program register to 0 to
15868  *    enable quasi-dynamic programming. Set back register to 1 once programming is done.
15869  */
15870 #define DDRC_SWCTL_SW_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_SW_DONE_SHIFT)) & DDRC_SWCTL_SW_DONE_MASK)
15871 /*! @} */
15872 
15873 /*! @name SWSTAT - Software Register Programming Control Status */
15874 /*! @{ */
15875 
15876 #define DDRC_SWSTAT_SW_DONE_ACK_MASK             (0x1U)
15877 #define DDRC_SWSTAT_SW_DONE_ACK_SHIFT            (0U)
15878 /*! sw_done_ack - Register programming done. This register is the echo of SWCTL.sw_done. Wait for
15879  *    sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure
15880  *    that the correct registers values are propagated to the destination clock domains.
15881  */
15882 #define DDRC_SWSTAT_SW_DONE_ACK(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_SW_DONE_ACK_SHIFT)) & DDRC_SWSTAT_SW_DONE_ACK_MASK)
15883 /*! @} */
15884 
15885 /*! @name POISONCFG - AXI Poison Configuration Register. */
15886 /*! @{ */
15887 
15888 #define DDRC_POISONCFG_WR_POISON_SLVERR_EN_MASK  (0x1U)
15889 #define DDRC_POISONCFG_WR_POISON_SLVERR_EN_SHIFT (0U)
15890 /*! wr_poison_slverr_en - If set to 1, enables SLVERR response for write transaction poisoning */
15891 #define DDRC_POISONCFG_WR_POISON_SLVERR_EN(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_WR_POISON_SLVERR_EN_SHIFT)) & DDRC_POISONCFG_WR_POISON_SLVERR_EN_MASK)
15892 
15893 #define DDRC_POISONCFG_WR_POISON_INTR_EN_MASK    (0x10U)
15894 #define DDRC_POISONCFG_WR_POISON_INTR_EN_SHIFT   (4U)
15895 /*! wr_poison_intr_en - If set to 1, enables interrupts for write transaction poisoning */
15896 #define DDRC_POISONCFG_WR_POISON_INTR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_WR_POISON_INTR_EN_SHIFT)) & DDRC_POISONCFG_WR_POISON_INTR_EN_MASK)
15897 
15898 #define DDRC_POISONCFG_WR_POISON_INTR_CLR_MASK   (0x100U)
15899 #define DDRC_POISONCFG_WR_POISON_INTR_CLR_SHIFT  (8U)
15900 /*! wr_poison_intr_clr - Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for
15901  *    correct value to propagate to core logic and clear the interrupts.
15902  */
15903 #define DDRC_POISONCFG_WR_POISON_INTR_CLR(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_WR_POISON_INTR_CLR_SHIFT)) & DDRC_POISONCFG_WR_POISON_INTR_CLR_MASK)
15904 
15905 #define DDRC_POISONCFG_RD_POISON_SLVERR_EN_MASK  (0x10000U)
15906 #define DDRC_POISONCFG_RD_POISON_SLVERR_EN_SHIFT (16U)
15907 /*! rd_poison_slverr_en - If set to 1, enables SLVERR response for read transaction poisoning */
15908 #define DDRC_POISONCFG_RD_POISON_SLVERR_EN(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_RD_POISON_SLVERR_EN_SHIFT)) & DDRC_POISONCFG_RD_POISON_SLVERR_EN_MASK)
15909 
15910 #define DDRC_POISONCFG_RD_POISON_INTR_EN_MASK    (0x100000U)
15911 #define DDRC_POISONCFG_RD_POISON_INTR_EN_SHIFT   (20U)
15912 /*! rd_poison_intr_en - If set to 1, enables interrupts for read transaction poisoning */
15913 #define DDRC_POISONCFG_RD_POISON_INTR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_RD_POISON_INTR_EN_SHIFT)) & DDRC_POISONCFG_RD_POISON_INTR_EN_MASK)
15914 
15915 #define DDRC_POISONCFG_RD_POISON_INTR_CLR_MASK   (0x1000000U)
15916 #define DDRC_POISONCFG_RD_POISON_INTR_CLR_SHIFT  (24U)
15917 /*! rd_poison_intr_clr - Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for
15918  *    correct value to propagate to core logic and clear the interrupts.
15919  */
15920 #define DDRC_POISONCFG_RD_POISON_INTR_CLR(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_RD_POISON_INTR_CLR_SHIFT)) & DDRC_POISONCFG_RD_POISON_INTR_CLR_MASK)
15921 /*! @} */
15922 
15923 /*! @name POISONSTAT - AXI Poison Status Register */
15924 /*! @{ */
15925 
15926 #define DDRC_POISONSTAT_WR_POISON_INTR_0_MASK    (0x1U)
15927 #define DDRC_POISONSTAT_WR_POISON_INTR_0_SHIFT   (0U)
15928 /*! wr_poison_intr_0 - Write transaction poisoning error interrupt for port 0. This register is a
15929  *    APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
15930  *    poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and
15931  *    so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB
15932  *    clock.
15933  */
15934 #define DDRC_POISONSTAT_WR_POISON_INTR_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_WR_POISON_INTR_0_SHIFT)) & DDRC_POISONSTAT_WR_POISON_INTR_0_MASK)
15935 
15936 #define DDRC_POISONSTAT_RD_POISON_INTR_0_MASK    (0x10000U)
15937 #define DDRC_POISONSTAT_RD_POISON_INTR_0_SHIFT   (16U)
15938 /*! rd_poison_intr_0 - Read transaction poisoning error interrupt for port 0. This register is a APB
15939  *    clock copy (double register synchronizer) of the interrupt asserted when a transaction is
15940  *    poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and
15941  *    so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock.
15942  */
15943 #define DDRC_POISONSTAT_RD_POISON_INTR_0(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_RD_POISON_INTR_0_SHIFT)) & DDRC_POISONSTAT_RD_POISON_INTR_0_MASK)
15944 /*! @} */
15945 
15946 /*! @name PSTAT - Port Status Register */
15947 /*! @{ */
15948 
15949 #define DDRC_PSTAT_RD_PORT_BUSY_0_MASK           (0x1U)
15950 #define DDRC_PSTAT_RD_PORT_BUSY_0_SHIFT          (0U)
15951 /*! rd_port_busy_0 - Indicates if there are outstanding reads for AXI port 0. */
15952 #define DDRC_PSTAT_RD_PORT_BUSY_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_RD_PORT_BUSY_0_SHIFT)) & DDRC_PSTAT_RD_PORT_BUSY_0_MASK)
15953 
15954 #define DDRC_PSTAT_WR_PORT_BUSY_0_MASK           (0x10000U)
15955 #define DDRC_PSTAT_WR_PORT_BUSY_0_SHIFT          (16U)
15956 /*! wr_port_busy_0 - Indicates if there are outstanding writes for AXI port 0. */
15957 #define DDRC_PSTAT_WR_PORT_BUSY_0(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_WR_PORT_BUSY_0_SHIFT)) & DDRC_PSTAT_WR_PORT_BUSY_0_MASK)
15958 /*! @} */
15959 
15960 /*! @name PCCFG - Port Common Configuration Register */
15961 /*! @{ */
15962 
15963 #define DDRC_PCCFG_GO2CRITICAL_EN_MASK           (0x1U)
15964 #define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT          (0U)
15965 /*! go2critical_en - If set to 1 (enabled), sets co_gs_go2critical_wr and
15966  *    co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from
15967  *    AXI master. If set to 0 (disabled), co_gs_go2critical_wr and
15968  *    co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
15969  */
15970 #define DDRC_PCCFG_GO2CRITICAL_EN(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT)) & DDRC_PCCFG_GO2CRITICAL_EN_MASK)
15971 
15972 #define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK          (0x10U)
15973 #define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT         (4U)
15974 /*! pagematch_limit - Page match four limit. If set to 1, limits the number of consecutive same page
15975  *    DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is
15976  *    enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC
15977  *    transactions.
15978  */
15979 #define DDRC_PCCFG_PAGEMATCH_LIMIT(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT)) & DDRC_PCCFG_PAGEMATCH_LIMIT_MASK)
15980 
15981 #define DDRC_PCCFG_BL_EXP_MODE_MASK              (0x100U)
15982 #define DDRC_PCCFG_BL_EXP_MODE_SHIFT             (8U)
15983 /*! bl_exp_mode - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every
15984  *    AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then
15985  *    XPI will use half of the memory burst length as a unit. This applies to both reads and
15986  *    writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in
15987  *    cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l
15988  *    penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if
15989  *    DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the
15990  *    following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
15991  *    MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
15992  *    MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or
15993  *    CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel
15994  *    Interleave is enabled
15995  */
15996 #define DDRC_PCCFG_BL_EXP_MODE(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_BL_EXP_MODE_SHIFT)) & DDRC_PCCFG_BL_EXP_MODE_MASK)
15997 /*! @} */
15998 
15999 /*! @name PCFGR_0 - Port n Configuration Read Register */
16000 /*! @{ */
16001 
16002 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK       (0x3FFU)
16003 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT      (0U)
16004 /*! rd_port_priority - Determines the initial load value of read aging counters. These counters will
16005  *    be parallel loaded after reset, or after each grant to the corresponding port. The aging
16006  *    counters down-count every clock cycle where the port is requesting but not granted. The higher
16007  *    significant 5-bits of the read aging counter sets the priority of the read channel of a given
16008  *    port. Port's priority will increase as the higher significant 5-bits of the counter starts to
16009  *    decrease. When the aging counter becomes 0, the corresponding port channel will have the highest
16010  *    priority level (timeout condition - Priority0). For multi-port configurations, the aging
16011  *    counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are
16012  *    enabled (timeout is still applicable). For single port configurations, the aging counters are
16013  *    only used when they timeout (become 0) to force read-write direction switching. In this case,
16014  *    external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read
16015  *    priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by
16016  *    command basis. Note: The two LSBs of this register field are tied internally to 2'b00.
16017  */
16018 #define DDRC_PCFGR_0_RD_PORT_PRIORITY(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT)) & DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK)
16019 
16020 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK       (0x1000U)
16021 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT      (12U)
16022 /*! rd_port_aging_en - If set to 1, enables aging function for the read channel of the port. */
16023 #define DDRC_PCFGR_0_RD_PORT_AGING_EN(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT)) & DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK)
16024 
16025 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK      (0x2000U)
16026 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT     (13U)
16027 /*! rd_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled
16028  *    and arurgent is asserted by the master, that port becomes the highest priority and
16029  *    co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in
16030  *    PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is
16031  *    independent of address handshaking (it is not associated with any particular command).
16032  */
16033 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT)) & DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK)
16034 
16035 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK   (0x4000U)
16036 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT  (14U)
16037 /*! rd_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
16038  *    requesting port is granted, the port is continued to be granted if the following immediate commands are
16039  *    to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
16040  *    register.
16041  */
16042 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT)) & DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK)
16043 
16044 #define DDRC_PCFGR_0_RDWR_ORDERED_EN_MASK        (0x10000U)
16045 #define DDRC_PCFGR_0_RDWR_ORDERED_EN_SHIFT       (16U)
16046 /*! rdwr_ordered_en - Enable ordered read/writes. If set to 1, preserves the ordering between read
16047  *    transaction and write transaction issued to the same address, on a given port. In other words,
16048  *    the controller ensures that all same address read and write commands from the application port
16049  *    interface are transported to the DFI interface in the order of acceptance. This feature is
16050  *    useful in cases where software coherency is desired for masters issuing back-to-back read/write
16051  *    transactions without waiting for write/read responses. Note that this register has an effect
16052  *    only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter.
16053  */
16054 #define DDRC_PCFGR_0_RDWR_ORDERED_EN(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RDWR_ORDERED_EN_SHIFT)) & DDRC_PCFGR_0_RDWR_ORDERED_EN_MASK)
16055 /*! @} */
16056 
16057 /*! @name PCFGW_0 - Port n Configuration Write Register */
16058 /*! @{ */
16059 
16060 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK       (0x3FFU)
16061 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT      (0U)
16062 /*! wr_port_priority - Determines the initial load value of write aging counters. These counters
16063  *    will be parallel loaded after reset, or after each grant to the corresponding port. The aging
16064  *    counters down-count every clock cycle where the port is requesting but not granted. The higher
16065  *    significant 5-bits of the write aging counter sets the initial priority of the write channel of
16066  *    a given port. Port's priority will increase as the higher significant 5-bits of the counter
16067  *    starts to decrease. When the aging counter becomes 0, the corresponding port channel will have
16068  *    the highest priority level. For multi-port configurations, the aging counters cannot be used to
16069  *    set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is
16070  *    still applicable). For single port configurations, the aging counters are only used when they
16071  *    timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register
16072  *    field are tied internally to 2'b00.
16073  */
16074 #define DDRC_PCFGW_0_WR_PORT_PRIORITY(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT)) & DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK)
16075 
16076 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK       (0x1000U)
16077 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT      (12U)
16078 /*! wr_port_aging_en - If set to 1, enables aging function for the write channel of the port. */
16079 #define DDRC_PCFGW_0_WR_PORT_AGING_EN(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT)) & DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK)
16080 
16081 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK      (0x2000U)
16082 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT     (13U)
16083 /*! wr_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled
16084  *    and awurgent is asserted by the master, that port becomes the highest priority and
16085  *    co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that
16086  *    awurgent signal can be asserted anytime and as long as required which is independent of address
16087  *    handshaking (it is not associated with any particular command).
16088  */
16089 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT)) & DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK)
16090 
16091 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK   (0x4000U)
16092 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT  (14U)
16093 /*! wr_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
16094  *    requesting port is granted, the port is continued to be granted if the following immediate commands are
16095  *    to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
16096  *    register.
16097  */
16098 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT)) & DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK)
16099 /*! @} */
16100 
16101 /*! @name PCTRL_0 - Port n Control Register */
16102 /*! @{ */
16103 
16104 #define DDRC_PCTRL_0_PORT_EN_MASK                (0x1U)
16105 #define DDRC_PCTRL_0_PORT_EN_SHIFT               (0U)
16106 /*! port_en - Enables AXI port n. */
16107 #define DDRC_PCTRL_0_PORT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_PORT_EN_SHIFT)) & DDRC_PCTRL_0_PORT_EN_MASK)
16108 /*! @} */
16109 
16110 /*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
16111 /*! @{ */
16112 
16113 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK     (0xFU)
16114 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT    (0U)
16115 /*! rqos_map_level1 - Separation level1 indicating the end of region0 mapping; start of region0 is
16116  *    0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which
16117  *    corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where
16118  *    the higher the value corresponds to higher port priority. All of the map_level* registers must
16119  *    be set to distinct values.
16120  */
16121 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT)) & DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK)
16122 
16123 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK    (0x30000U)
16124 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT   (16U)
16125 /*! rqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
16126  *    LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address
16127  *    queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled
16128  *    (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
16129  *    traffic.
16130  */
16131 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT)) & DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK)
16132 
16133 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK    (0x300000U)
16134 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT   (20U)
16135 /*! rqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0 :
16136  *    LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address
16137  *    queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled
16138  *    (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
16139  *    traffic.
16140  */
16141 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT)) & DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK)
16142 /*! @} */
16143 
16144 /*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
16145 /*! @{ */
16146 
16147 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK   (0x7FFU)
16148 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT  (0U)
16149 /*! rqos_map_timeoutb - Specifies the timeout value for transactions mapped to the blue address queue. */
16150 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT)) & DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK)
16151 
16152 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK   (0x7FF0000U)
16153 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT  (16U)
16154 /*! rqos_map_timeoutr - Specifies the timeout value for transactions mapped to the red address queue. */
16155 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT)) & DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK)
16156 /*! @} */
16157 
16158 /*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
16159 /*! @{ */
16160 
16161 #define DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK     (0xFU)
16162 #define DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT    (0U)
16163 /*! wqos_map_level - Separation level indicating the end of region0 mapping; start of region0 is 0.
16164  *    Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos
16165  *    values are used directly as port priorities, where the higher the value corresponds to higher
16166  *    port priority.
16167  */
16168 #define DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT)) & DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK)
16169 
16170 #define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK   (0x30000U)
16171 #define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT  (16U)
16172 /*! wqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
16173  *    NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set
16174  *    to 1 (VPW), VPW traffic is aliased to NPW traffic.
16175  */
16176 #define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT)) & DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK)
16177 
16178 #define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK   (0x300000U)
16179 #define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT  (20U)
16180 /*! wqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0:
16181  *    NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is
16182  *    set to 1 (VPW), VPW traffic is aliased to LPW traffic.
16183  */
16184 #define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT)) & DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK)
16185 /*! @} */
16186 
16187 /*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
16188 /*! @{ */
16189 
16190 #define DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK   (0x7FFU)
16191 #define DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT  (0U)
16192 /*! wqos_map_timeout - Specifies the timeout value for write transactions. */
16193 #define DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT)) & DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK)
16194 /*! @} */
16195 
16196 /*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
16197 /*! @{ */
16198 
16199 #define DDRC_DERATEEN_SHADOW_DERATE_ENABLE_MASK  (0x1U)
16200 #define DDRC_DERATEEN_SHADOW_DERATE_ENABLE_SHIFT (0U)
16201 /*! derate_enable - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing
16202  *    parameter derating is enabled using MR4 read value. Present only in designs configured to support
16203  *    LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
16204  */
16205 #define DDRC_DERATEEN_SHADOW_DERATE_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_DERATE_ENABLE_SHIFT)) & DDRC_DERATEEN_SHADOW_DERATE_ENABLE_MASK)
16206 
16207 #define DDRC_DERATEEN_SHADOW_DERATE_VALUE_MASK   (0x2U)
16208 #define DDRC_DERATEEN_SHADOW_DERATE_VALUE_SHIFT  (1U)
16209 /*! derate_value - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in
16210  *    designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as
16211  *    derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of
16212  *    core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it
16213  *    should be set to 0.
16214  */
16215 #define DDRC_DERATEEN_SHADOW_DERATE_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_SHADOW_DERATE_VALUE_MASK)
16216 
16217 #define DDRC_DERATEEN_SHADOW_DERATE_BYTE_MASK    (0xF0U)
16218 #define DDRC_DERATEEN_SHADOW_DERATE_BYTE_SHIFT   (4U)
16219 /*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
16220  *    Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
16221  *    MEMC_DRAM_TOTAL_DATA_WIDTH.
16222  */
16223 #define DDRC_DERATEEN_SHADOW_DERATE_BYTE(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_DERATE_BYTE_SHIFT)) & DDRC_DERATEEN_SHADOW_DERATE_BYTE_MASK)
16224 
16225 #define DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_MASK (0x300U)
16226 #define DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_SHIFT (8U)
16227 /*! rc_derate_value - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2.
16228  *    - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support
16229  *    LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by
16230  *    the core_ddrc_core_clk period, and rounding up the next integer.
16231  */
16232 #define DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_MASK)
16233 /*! @} */
16234 
16235 /*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
16236 /*! @{ */
16237 
16238 #define DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_MASK (0xFFFFFFFFU)
16239 #define DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_SHIFT (0U)
16240 /*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
16241  *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
16242  *    zero. Unit: DFI clock cycle.
16243  */
16244 #define DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_SHIFT)) & DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_MASK)
16245 /*! @} */
16246 
16247 /*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
16248 /*! @{ */
16249 
16250 #define DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_MASK (0x4U)
16251 #define DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_SHIFT (2U)
16252 /*! per_bank_refresh - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
16253  *    traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should
16254  *    be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support
16255  *    LPDDR2/LPDDR3/LPDDR4
16256  */
16257 #define DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_SHIFT)) & DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_MASK)
16258 
16259 #define DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_MASK  (0x1F0U)
16260 #define DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_SHIFT (4U)
16261 /*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
16262  *    accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
16263  *    perform a refresh is a one-time penalty that must be paid for each group of refreshes.
16264  *    Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
16265  *    Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
16266  *    the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
16267  *    refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
16268  *    DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
16269  *    per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
16270  *    feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
16271  *    mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
16272  *    must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
16273  *    due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
16274  *    situation, the refresh burst will be delayed until the PHY-initiated update is complete.
16275  */
16276 #define DDRC_RFSHCTL0_SHADOW_REFRESH_BURST(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_SHIFT)) & DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_MASK)
16277 
16278 #define DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_MASK (0x1F000U)
16279 #define DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_SHIFT (12U)
16280 /*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
16281  *    but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
16282  *    performed. A speculative refresh is a refresh performed at a time when refresh would be
16283  *    useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
16284  *    determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
16285  *    the last refresh, then a speculative refresh is performed. Speculative refreshes continues
16286  *    successively until there are no refreshes pending or until new reads or writes are issued to the
16287  *    DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
16288  */
16289 #define DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_MASK)
16290 
16291 #define DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_MASK (0xF00000U)
16292 #define DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_SHIFT (20U)
16293 /*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
16294  *    page timer expires. A critical refresh is to be issued before this threshold is reached. It is
16295  *    recommended that this not be changed from the default value, currently shown as 0x2. It must
16296  *    always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
16297  *    internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
16298  *    (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
16299  *    RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
16300  */
16301 #define DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_SHIFT)) & DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_MASK)
16302 /*! @} */
16303 
16304 /*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
16305 /*! @{ */
16306 
16307 #define DDRC_RFSHTMG_SHADOW_T_RFC_MIN_MASK       (0x3FFU)
16308 #define DDRC_RFSHTMG_SHADOW_T_RFC_MIN_SHIFT      (0U)
16309 /*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
16310  *    operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
16311  *    is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
16312  *    LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
16313  *    is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
16314  *    equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
16315  *    on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
16316  *    appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
16317  *    Unit: Clocks.
16318  */
16319 #define DDRC_RFSHTMG_SHADOW_T_RFC_MIN(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_T_RFC_MIN_SHIFT)) & DDRC_RFSHTMG_SHADOW_T_RFC_MIN_MASK)
16320 
16321 #define DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_MASK (0x8000U)
16322 #define DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_SHIFT (15U)
16323 /*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
16324  *    DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
16325  *    devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
16326  *    parameter not used - 1 - tREFBW parameter used
16327  */
16328 #define DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_SHIFT)) & DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_MASK)
16329 
16330 #define DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_MASK   (0xFFF0000U)
16331 #define DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_SHIFT  (16U)
16332 /*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
16333  *    for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
16334  *    LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
16335  *    should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
16336  *    register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
16337  *    program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
16338  *    on the refresh mode. The user should program the appropriate value from the spec based on the
16339  *    value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
16340  *    greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
16341  *    DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
16342  *    2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
16343  *    RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
16344  */
16345 #define DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_SHIFT)) & DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_MASK)
16346 /*! @} */
16347 
16348 /*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
16349 /*! @{ */
16350 
16351 #define DDRC_INIT3_SHADOW_EMR_MASK               (0xFFFFU)
16352 #define DDRC_INIT3_SHADOW_EMR_SHIFT              (0U)
16353 /*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
16354  *    register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
16355  *    register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
16356  *    the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
16357  *    Value to write to MR2 register
16358  */
16359 #define DDRC_INIT3_SHADOW_EMR(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_EMR_SHIFT)) & DDRC_INIT3_SHADOW_EMR_MASK)
16360 
16361 #define DDRC_INIT3_SHADOW_MR_MASK                (0xFFFF0000U)
16362 #define DDRC_INIT3_SHADOW_MR_SHIFT               (16U)
16363 /*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
16364  *    DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
16365  *    write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
16366  */
16367 #define DDRC_INIT3_SHADOW_MR(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_MR_SHIFT)) & DDRC_INIT3_SHADOW_MR_MASK)
16368 /*! @} */
16369 
16370 /*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
16371 /*! @{ */
16372 
16373 #define DDRC_INIT4_SHADOW_EMR3_MASK              (0xFFFFU)
16374 #define DDRC_INIT4_SHADOW_EMR3_SHIFT             (0U)
16375 /*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
16376  *    mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
16377  */
16378 #define DDRC_INIT4_SHADOW_EMR3(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_EMR3_SHIFT)) & DDRC_INIT4_SHADOW_EMR3_MASK)
16379 
16380 #define DDRC_INIT4_SHADOW_EMR2_MASK              (0xFFFF0000U)
16381 #define DDRC_INIT4_SHADOW_EMR2_SHIFT             (16U)
16382 /*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
16383  *    LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
16384  */
16385 #define DDRC_INIT4_SHADOW_EMR2(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_EMR2_SHIFT)) & DDRC_INIT4_SHADOW_EMR2_MASK)
16386 /*! @} */
16387 
16388 /*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
16389 /*! @{ */
16390 
16391 #define DDRC_INIT6_SHADOW_MR5_MASK               (0xFFFFU)
16392 #define DDRC_INIT6_SHADOW_MR5_SHIFT              (0U)
16393 /*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. */
16394 #define DDRC_INIT6_SHADOW_MR5(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_MR5_SHIFT)) & DDRC_INIT6_SHADOW_MR5_MASK)
16395 
16396 #define DDRC_INIT6_SHADOW_MR4_MASK               (0xFFFF0000U)
16397 #define DDRC_INIT6_SHADOW_MR4_SHIFT              (16U)
16398 /*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. */
16399 #define DDRC_INIT6_SHADOW_MR4(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_MR4_SHIFT)) & DDRC_INIT6_SHADOW_MR4_MASK)
16400 /*! @} */
16401 
16402 /*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
16403 /*! @{ */
16404 
16405 #define DDRC_INIT7_SHADOW_MR6_MASK               (0xFFFF0000U)
16406 #define DDRC_INIT7_SHADOW_MR6_SHIFT              (16U)
16407 /*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. */
16408 #define DDRC_INIT7_SHADOW_MR6(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_MR6_SHIFT)) & DDRC_INIT7_SHADOW_MR6_MASK)
16409 /*! @} */
16410 
16411 /*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
16412 /*! @{ */
16413 
16414 #define DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_MASK      (0x3FU)
16415 #define DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_SHIFT     (0U)
16416 /*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
16417  *    controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
16418  *    up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
16419  *    program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
16420  */
16421 #define DDRC_DRAMTMG0_SHADOW_T_RAS_MIN(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_SHIFT)) & DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_MASK)
16422 
16423 #define DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_MASK      (0x7F00U)
16424 #define DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_SHIFT     (8U)
16425 /*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
16426  *    maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
16427  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
16428  *    No rounding up. Unit: Multiples of 1024 clocks.
16429  */
16430 #define DDRC_DRAMTMG0_SHADOW_T_RAS_MAX(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_SHIFT)) & DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_MASK)
16431 
16432 #define DDRC_DRAMTMG0_SHADOW_T_FAW_MASK          (0x3F0000U)
16433 #define DDRC_DRAMTMG0_SHADOW_T_FAW_SHIFT         (16U)
16434 /*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
16435  *    design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
16436  *    is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
16437  *    integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
16438  *    mode. Unit: Clocks
16439  */
16440 #define DDRC_DRAMTMG0_SHADOW_T_FAW(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_T_FAW_SHIFT)) & DDRC_DRAMTMG0_SHADOW_T_FAW_MASK)
16441 
16442 #define DDRC_DRAMTMG0_SHADOW_WR2PRE_MASK         (0x7F000000U)
16443 #define DDRC_DRAMTMG0_SHADOW_WR2PRE_SHIFT        (24U)
16444 /*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
16445  *    + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
16446  *    frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
16447  *    the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
16448  *    - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
16449  *    cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
16450  *    frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
16451  *    is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
16452  *    and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
16453  *    may be necessary to adjust the value of this parameter to compensate for the extra cycle of
16454  *    latency through the LRDIMM.
16455  */
16456 #define DDRC_DRAMTMG0_SHADOW_WR2PRE(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_WR2PRE_SHIFT)) & DDRC_DRAMTMG0_SHADOW_WR2PRE_MASK)
16457 /*! @} */
16458 
16459 /*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
16460 /*! @{ */
16461 
16462 #define DDRC_DRAMTMG1_SHADOW_T_RC_MASK           (0x7FU)
16463 #define DDRC_DRAMTMG1_SHADOW_T_RC_SHIFT          (0U)
16464 /*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
16465  *    frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
16466  *    Clocks.
16467  */
16468 #define DDRC_DRAMTMG1_SHADOW_T_RC(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_T_RC_SHIFT)) & DDRC_DRAMTMG1_SHADOW_T_RC_MASK)
16469 
16470 #define DDRC_DRAMTMG1_SHADOW_RD2PRE_MASK         (0x3F00U)
16471 #define DDRC_DRAMTMG1_SHADOW_RD2PRE_SHIFT        (8U)
16472 /*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
16473  *    2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
16474  *    or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
16475  *    LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
16476  *    - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
16477  *    use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
16478  *    divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
16479  *    mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
16480  *    Unit: Clocks.
16481  */
16482 #define DDRC_DRAMTMG1_SHADOW_RD2PRE(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_RD2PRE_SHIFT)) & DDRC_DRAMTMG1_SHADOW_RD2PRE_MASK)
16483 
16484 #define DDRC_DRAMTMG1_SHADOW_T_XP_MASK           (0x1F0000U)
16485 #define DDRC_DRAMTMG1_SHADOW_T_XP_SHIFT          (16U)
16486 /*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
16487  *    programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
16488  *    set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
16489  *    this to (tXP/2) and round it up to the next integer value. Units: Clocks
16490  */
16491 #define DDRC_DRAMTMG1_SHADOW_T_XP(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_T_XP_SHIFT)) & DDRC_DRAMTMG1_SHADOW_T_XP_MASK)
16492 /*! @} */
16493 
16494 /*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
16495 /*! @{ */
16496 
16497 #define DDRC_DRAMTMG2_SHADOW_WR2RD_MASK          (0x3FU)
16498 #define DDRC_DRAMTMG2_SHADOW_WR2RD_SHIFT         (0U)
16499 /*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
16500  *    write command to read command for same bank group. In others, minimum time from write command to
16501  *    read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
16502  *    global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
16503  *    = burst length. This must match the value programmed in the BL bit of the mode register to
16504  *    the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
16505  *    directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
16506  *    directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
16507  *    When the controller is operating in 1:2 mode, divide the value calculated using the above
16508  *    equation by 2, and round it up to next integer.
16509  */
16510 #define DDRC_DRAMTMG2_SHADOW_WR2RD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_WR2RD_SHIFT)) & DDRC_DRAMTMG2_SHADOW_WR2RD_MASK)
16511 
16512 #define DDRC_DRAMTMG2_SHADOW_RD2WR_MASK          (0x3F00U)
16513 #define DDRC_DRAMTMG2_SHADOW_RD2WR_SHIFT         (8U)
16514 /*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
16515  *    + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
16516  *    + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
16517  *    RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
16518  *    Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
16519  *    the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
16520  *    WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
16521  *    the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
16522  *    preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
16523  *    LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
16524  *    tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
16525  *    value calculated using the above equation by 2, and round it up to next integer. Note that,
16526  *    depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
16527  *    to compensate for the extra cycle of latency through the LRDIMM.
16528  */
16529 #define DDRC_DRAMTMG2_SHADOW_RD2WR(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_RD2WR_SHIFT)) & DDRC_DRAMTMG2_SHADOW_RD2WR_MASK)
16530 
16531 #define DDRC_DRAMTMG2_SHADOW_READ_LATENCY_MASK   (0x3F0000U)
16532 #define DDRC_DRAMTMG2_SHADOW_READ_LATENCY_SHIFT  (16U)
16533 /*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
16534  *    set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
16535  *    the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
16536  *    the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
16537  *    above equation by 2, and round it up to next integer. This register field is not required for
16538  *    DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
16539  *    DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
16540  */
16541 #define DDRC_DRAMTMG2_SHADOW_READ_LATENCY(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_READ_LATENCY_SHIFT)) & DDRC_DRAMTMG2_SHADOW_READ_LATENCY_MASK)
16542 
16543 #define DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_MASK  (0x3F000000U)
16544 #define DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_SHIFT (24U)
16545 /*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
16546  *    set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
16547  *    using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
16548  *    cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
16549  *    mode, divide the value calculated using the above equation by 2, and round it up to next
16550  *    integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
16551  *    as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
16552  *    protocols Unit: clocks
16553  */
16554 #define DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_SHIFT)) & DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_MASK)
16555 /*! @} */
16556 
16557 /*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
16558 /*! @{ */
16559 
16560 #define DDRC_DRAMTMG3_SHADOW_T_MOD_MASK          (0x3FFU)
16561 #define DDRC_DRAMTMG3_SHADOW_T_MOD_SHIFT         (0U)
16562 /*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
16563  *    following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
16564  *    Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
16565  *    next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
16566  *    RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
16567  *    compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
16568  *    Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
16569  *    is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
16570  *    controller is operating in 1:2 frequency ratio mode.
16571  */
16572 #define DDRC_DRAMTMG3_SHADOW_T_MOD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_T_MOD_SHIFT)) & DDRC_DRAMTMG3_SHADOW_T_MOD_MASK)
16573 
16574 #define DDRC_DRAMTMG3_SHADOW_T_MRD_MASK          (0x3F000U)
16575 #define DDRC_DRAMTMG3_SHADOW_T_MRD_SHIFT         (12U)
16576 /*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
16577  *    SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
16578  *    command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
16579  *    operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
16580  *    value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
16581  */
16582 #define DDRC_DRAMTMG3_SHADOW_T_MRD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_T_MRD_SHIFT)) & DDRC_DRAMTMG3_SHADOW_T_MRD_MASK)
16583 
16584 #define DDRC_DRAMTMG3_SHADOW_T_MRW_MASK          (0x3FF00000U)
16585 #define DDRC_DRAMTMG3_SHADOW_T_MRW_SHIFT         (20U)
16586 /*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
16587  *    configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
16588  *    typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
16589  *    this register is used for the time from a MRW/MRR to all other commands. When the controller
16590  *    is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
16591  *    round it up to the next integer value. For LDPDR3, this register is used for the time from a
16592  *    MRW/MRR to a MRW/MRR.
16593  */
16594 #define DDRC_DRAMTMG3_SHADOW_T_MRW(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_T_MRW_SHIFT)) & DDRC_DRAMTMG3_SHADOW_T_MRW_MASK)
16595 /*! @} */
16596 
16597 /*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
16598 /*! @{ */
16599 
16600 #define DDRC_DRAMTMG4_SHADOW_T_RP_MASK           (0x1FU)
16601 #define DDRC_DRAMTMG4_SHADOW_T_RP_SHIFT          (0U)
16602 /*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
16603  *    operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
16604  *    operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
16605  *    1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
16606  *    to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
16607  */
16608 #define DDRC_DRAMTMG4_SHADOW_T_RP(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_RP_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_RP_MASK)
16609 
16610 #define DDRC_DRAMTMG4_SHADOW_T_RRD_MASK          (0xF00U)
16611 #define DDRC_DRAMTMG4_SHADOW_T_RRD_SHIFT         (8U)
16612 /*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
16613  *    group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
16614  *    is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
16615  *    up to the next integer value. Unit: Clocks.
16616  */
16617 #define DDRC_DRAMTMG4_SHADOW_T_RRD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_RRD_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_RRD_MASK)
16618 
16619 #define DDRC_DRAMTMG4_SHADOW_T_CCD_MASK          (0xF0000U)
16620 #define DDRC_DRAMTMG4_SHADOW_T_CCD_SHIFT         (16U)
16621 /*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
16622  *    group. Others: tCCD: This is the minimum time between two reads or two writes. When the
16623  *    controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
16624  *    up to the next integer value. Unit: clocks.
16625  */
16626 #define DDRC_DRAMTMG4_SHADOW_T_CCD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_CCD_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_CCD_MASK)
16627 
16628 #define DDRC_DRAMTMG4_SHADOW_T_RCD_MASK          (0x1F000000U)
16629 #define DDRC_DRAMTMG4_SHADOW_T_RCD_SHIFT         (24U)
16630 /*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
16631  *    controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
16632  *    it up to the next integer value. Minimum value allowed for this register is 1, which implies
16633  *    minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
16634  *    mode. Unit: Clocks.
16635  */
16636 #define DDRC_DRAMTMG4_SHADOW_T_RCD(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_RCD_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_RCD_MASK)
16637 /*! @} */
16638 
16639 /*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
16640 /*! @{ */
16641 
16642 #define DDRC_DRAMTMG5_SHADOW_T_CKE_MASK          (0x1FU)
16643 #define DDRC_DRAMTMG5_SHADOW_T_CKE_SHIFT         (0U)
16644 /*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
16645  *    LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
16646  *    tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
16647  *    the controller is operating in 1:2 frequency ratio mode, program this to (value described
16648  *    above)/2 and round it up to the next integer value. Unit: Clocks.
16649  */
16650 #define DDRC_DRAMTMG5_SHADOW_T_CKE(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKE_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKE_MASK)
16651 
16652 #define DDRC_DRAMTMG5_SHADOW_T_CKESR_MASK        (0x3F00U)
16653 #define DDRC_DRAMTMG5_SHADOW_T_CKESR_SHIFT       (8U)
16654 /*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
16655  *    in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
16656  *    - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
16657  *    latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
16658  *    by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
16659  *    recommended value divided by two and round it up to next integer.
16660  */
16661 #define DDRC_DRAMTMG5_SHADOW_T_CKESR(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKESR_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKESR_MASK)
16662 
16663 #define DDRC_DRAMTMG5_SHADOW_T_CKSRE_MASK        (0xF0000U)
16664 #define DDRC_DRAMTMG5_SHADOW_T_CKSRE_SHIFT       (16U)
16665 /*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
16666  *    Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
16667  *    LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
16668  *    PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
16669  *    be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
16670  *    this to recommended value divided by two and round it up to next integer.
16671  */
16672 #define DDRC_DRAMTMG5_SHADOW_T_CKSRE(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKSRE_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKSRE_MASK)
16673 
16674 #define DDRC_DRAMTMG5_SHADOW_T_CKSRX_MASK        (0xF000000U)
16675 #define DDRC_DRAMTMG5_SHADOW_T_CKSRX_SHIFT       (24U)
16676 /*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
16677  *    before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
16678  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
16679  *    controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
16680  *    two and round it up to next integer.
16681  */
16682 #define DDRC_DRAMTMG5_SHADOW_T_CKSRX(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKSRX_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKSRX_MASK)
16683 /*! @} */
16684 
16685 /*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
16686 /*! @{ */
16687 
16688 #define DDRC_DRAMTMG6_SHADOW_T_CKCSX_MASK        (0xFU)
16689 #define DDRC_DRAMTMG6_SHADOW_T_CKCSX_SHIFT       (0U)
16690 /*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
16691  *    issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
16692  *    Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
16693  *    When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
16694  *    divided by two and round it up to next integer. This is only present for designs supporting
16695  *    mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
16696  */
16697 #define DDRC_DRAMTMG6_SHADOW_T_CKCSX(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_T_CKCSX_SHIFT)) & DDRC_DRAMTMG6_SHADOW_T_CKCSX_MASK)
16698 
16699 #define DDRC_DRAMTMG6_SHADOW_T_CKDPDX_MASK       (0xF0000U)
16700 #define DDRC_DRAMTMG6_SHADOW_T_CKDPDX_SHIFT      (16U)
16701 /*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
16702  *    before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
16703  *    1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
16704  *    program this to recommended value divided by two and round it up to next integer. This is only
16705  *    present for designs supporting mDDR or LPDDR2 devices.
16706  */
16707 #define DDRC_DRAMTMG6_SHADOW_T_CKDPDX(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_T_CKDPDX_SHIFT)) & DDRC_DRAMTMG6_SHADOW_T_CKDPDX_MASK)
16708 
16709 #define DDRC_DRAMTMG6_SHADOW_T_CKDPDE_MASK       (0xF000000U)
16710 #define DDRC_DRAMTMG6_SHADOW_T_CKDPDE_SHIFT      (24U)
16711 /*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
16712  *    Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
16713  *    LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
16714  *    recommended value divided by two and round it up to next integer. This is only present for designs
16715  *    supporting mDDR or LPDDR2/LPDDR3 devices.
16716  */
16717 #define DDRC_DRAMTMG6_SHADOW_T_CKDPDE(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_T_CKDPDE_SHIFT)) & DDRC_DRAMTMG6_SHADOW_T_CKDPDE_MASK)
16718 /*! @} */
16719 
16720 /*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
16721 /*! @{ */
16722 
16723 #define DDRC_DRAMTMG7_SHADOW_T_CKPDX_MASK        (0xFU)
16724 #define DDRC_DRAMTMG7_SHADOW_T_CKPDX_SHIFT       (0U)
16725 /*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
16726  *    issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
16727  *    LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
16728  *    same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
16729  *    program this to recommended value divided by two and round it up to next integer. This is only
16730  *    present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
16731  */
16732 #define DDRC_DRAMTMG7_SHADOW_T_CKPDX(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_T_CKPDX_SHIFT)) & DDRC_DRAMTMG7_SHADOW_T_CKPDX_MASK)
16733 
16734 #define DDRC_DRAMTMG7_SHADOW_T_CKPDE_MASK        (0xF00U)
16735 #define DDRC_DRAMTMG7_SHADOW_T_CKPDE_SHIFT       (8U)
16736 /*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
16737  *    Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
16738  *    - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
16739  *    DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
16740  *    to recommended value divided by two and round it up to next integer. This is only present for
16741  *    designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
16742  */
16743 #define DDRC_DRAMTMG7_SHADOW_T_CKPDE(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_T_CKPDE_SHIFT)) & DDRC_DRAMTMG7_SHADOW_T_CKPDE_MASK)
16744 /*! @} */
16745 
16746 /*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
16747 /*! @{ */
16748 
16749 #define DDRC_DRAMTMG8_SHADOW_T_XS_X32_MASK       (0x7FU)
16750 #define DDRC_DRAMTMG8_SHADOW_T_XS_X32_SHIFT      (0U)
16751 /*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
16752  *    operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
16753  *    up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
16754  *    DDR4 SDRAMs.
16755  */
16756 #define DDRC_DRAMTMG8_SHADOW_T_XS_X32(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_X32_MASK)
16757 
16758 #define DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_MASK   (0x7F00U)
16759 #define DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_SHIFT  (8U)
16760 /*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
16761  *    is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
16762  *    round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
16763  *    DDR4 SDRAMs.
16764  */
16765 #define DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_MASK)
16766 
16767 #define DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_MASK (0x7F0000U)
16768 #define DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_SHIFT (16U)
16769 /*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
16770  *    Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
16771  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
16772  *    Note: Ensure this is less than or equal to t_xs_x32.
16773  */
16774 #define DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_MASK)
16775 
16776 #define DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_MASK  (0x7F000000U)
16777 #define DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_SHIFT (24U)
16778 /*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
16779  *    mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
16780  *    above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
16781  *    This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
16782  *    t_xs_x32.
16783  */
16784 #define DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_MASK)
16785 /*! @} */
16786 
16787 /*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
16788 /*! @{ */
16789 
16790 #define DDRC_DRAMTMG9_SHADOW_WR2RD_S_MASK        (0x3FU)
16791 #define DDRC_DRAMTMG9_SHADOW_WR2RD_S_SHIFT       (0U)
16792 /*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
16793  *    bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
16794  *    global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
16795  *    - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
16796  *    programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
16797  *    command delay for different bank group. This comes directly from the SDRAM specification. When
16798  *    the controller is operating in 1:2 mode, divide the value calculated using the above equation
16799  *    by 2, and round it up to next integer.
16800  */
16801 #define DDRC_DRAMTMG9_SHADOW_WR2RD_S(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_WR2RD_S_SHIFT)) & DDRC_DRAMTMG9_SHADOW_WR2RD_S_MASK)
16802 
16803 #define DDRC_DRAMTMG9_SHADOW_T_RRD_S_MASK        (0xF00U)
16804 #define DDRC_DRAMTMG9_SHADOW_T_RRD_S_SHIFT       (8U)
16805 /*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
16806  *    group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
16807  *    and round it up to the next integer value. Present only in designs configured to support DDR4.
16808  *    Unit: Clocks.
16809  */
16810 #define DDRC_DRAMTMG9_SHADOW_T_RRD_S(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_T_RRD_S_SHIFT)) & DDRC_DRAMTMG9_SHADOW_T_RRD_S_MASK)
16811 
16812 #define DDRC_DRAMTMG9_SHADOW_T_CCD_S_MASK        (0x70000U)
16813 #define DDRC_DRAMTMG9_SHADOW_T_CCD_S_SHIFT       (16U)
16814 /*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
16815  *    group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
16816  *    the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
16817  *    it up to the next integer value. Present only in designs configured to support DDR4. Unit:
16818  *    clocks.
16819  */
16820 #define DDRC_DRAMTMG9_SHADOW_T_CCD_S(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_T_CCD_S_SHIFT)) & DDRC_DRAMTMG9_SHADOW_T_CCD_S_MASK)
16821 
16822 #define DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_MASK (0x40000000U)
16823 #define DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_SHIFT (30U)
16824 /*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 */
16825 #define DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_SHIFT)) & DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_MASK)
16826 /*! @} */
16827 
16828 /*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
16829 /*! @{ */
16830 
16831 #define DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_MASK   (0x3U)
16832 #define DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_SHIFT  (0U)
16833 /*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
16834  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
16835  *    1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
16836  *    value. Unit: Clocks
16837  */
16838 #define DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_MASK)
16839 
16840 #define DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_MASK  (0xCU)
16841 #define DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_SHIFT (2U)
16842 /*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
16843  *    DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
16844  *    1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
16845  *    value. Unit: Clocks
16846  */
16847 #define DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_MASK)
16848 
16849 #define DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_MASK    (0x1F00U)
16850 #define DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_SHIFT   (8U)
16851 /*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
16852  *    defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
16853  *    this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
16854  *    and round it up to the next integer value. Unit: Clocks
16855  */
16856 #define DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_MASK)
16857 
16858 #define DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_MASK   (0x1F0000U)
16859 #define DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_SHIFT  (16U)
16860 /*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
16861  *    number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
16862  *    tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
16863  *    When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
16864  *    to the next integer value. Unit: Clocks
16865  */
16866 #define DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_MASK)
16867 /*! @} */
16868 
16869 /*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
16870 /*! @{ */
16871 
16872 #define DDRC_DRAMTMG11_SHADOW_T_CKMPE_MASK       (0x1FU)
16873 #define DDRC_DRAMTMG11_SHADOW_T_CKMPE_SHIFT      (0U)
16874 /*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
16875  *    configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
16876  *    mode, divide the value calculated using the above equation by 2, and round it up to next
16877  *    integer.
16878  */
16879 #define DDRC_DRAMTMG11_SHADOW_T_CKMPE(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_T_CKMPE_SHIFT)) & DDRC_DRAMTMG11_SHADOW_T_CKMPE_MASK)
16880 
16881 #define DDRC_DRAMTMG11_SHADOW_T_MPX_S_MASK       (0x300U)
16882 #define DDRC_DRAMTMG11_SHADOW_T_MPX_S_SHIFT      (8U)
16883 /*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
16884  *    frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
16885  *    Present only in designs configured to support DDR4. Unit: Clocks.
16886  */
16887 #define DDRC_DRAMTMG11_SHADOW_T_MPX_S(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_T_MPX_S_SHIFT)) & DDRC_DRAMTMG11_SHADOW_T_MPX_S_MASK)
16888 
16889 #define DDRC_DRAMTMG11_SHADOW_T_MPX_LH_MASK      (0x1F0000U)
16890 #define DDRC_DRAMTMG11_SHADOW_T_MPX_LH_SHIFT     (16U)
16891 /*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
16892  *    controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
16893  *    only in designs configured to support DDR4. Unit: clocks.
16894  */
16895 #define DDRC_DRAMTMG11_SHADOW_T_MPX_LH(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_T_MPX_LH_SHIFT)) & DDRC_DRAMTMG11_SHADOW_T_MPX_LH_MASK)
16896 
16897 #define DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_MASK (0x7F000000U)
16898 #define DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_SHIFT (24U)
16899 /*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
16900  *    When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
16901  *    round it up to the next integer value. Present only in designs configured to support DDR4.
16902  *    Unit: Multiples of 32 clocks.
16903  */
16904 #define DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_MASK)
16905 /*! @} */
16906 
16907 /*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
16908 /*! @{ */
16909 
16910 #define DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_MASK     (0x1FU)
16911 #define DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_SHIFT    (0U)
16912 /*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
16913  *    controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
16914  *    to the next integer value.
16915  */
16916 #define DDRC_DRAMTMG12_SHADOW_T_MRD_PDA(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_SHIFT)) & DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_MASK)
16917 
16918 #define DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_MASK     (0xF00U)
16919 #define DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_SHIFT    (8U)
16920 /*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
16921  *    operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
16922  *    integer value.
16923  */
16924 #define DDRC_DRAMTMG12_SHADOW_T_CKEHCMD(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_SHIFT)) & DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_MASK)
16925 
16926 #define DDRC_DRAMTMG12_SHADOW_T_CMDCKE_MASK      (0x30000U)
16927 #define DDRC_DRAMTMG12_SHADOW_T_CMDCKE_SHIFT     (16U)
16928 /*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
16929  *    or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
16930  *    (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
16931  */
16932 #define DDRC_DRAMTMG12_SHADOW_T_CMDCKE(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_T_CMDCKE_SHIFT)) & DDRC_DRAMTMG12_SHADOW_T_CMDCKE_MASK)
16933 /*! @} */
16934 
16935 /*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
16936 /*! @{ */
16937 
16938 #define DDRC_DRAMTMG13_SHADOW_T_PPD_MASK         (0x7U)
16939 #define DDRC_DRAMTMG13_SHADOW_T_PPD_SHIFT        (0U)
16940 /*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
16941  *    controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
16942  *    the next integer value. Unit: Clocks.
16943  */
16944 #define DDRC_DRAMTMG13_SHADOW_T_PPD(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_T_PPD_SHIFT)) & DDRC_DRAMTMG13_SHADOW_T_PPD_MASK)
16945 
16946 #define DDRC_DRAMTMG13_SHADOW_T_CCD_MW_MASK      (0x3F0000U)
16947 #define DDRC_DRAMTMG13_SHADOW_T_CCD_MW_SHIFT     (16U)
16948 /*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
16949  *    command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
16950  *    this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
16951  */
16952 #define DDRC_DRAMTMG13_SHADOW_T_CCD_MW(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_T_CCD_MW_SHIFT)) & DDRC_DRAMTMG13_SHADOW_T_CCD_MW_MASK)
16953 
16954 #define DDRC_DRAMTMG13_SHADOW_ODTLOFF_MASK       (0x7F000000U)
16955 #define DDRC_DRAMTMG13_SHADOW_ODTLOFF_SHIFT      (24U)
16956 /*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
16957  *    the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
16958  *    it up to the next integer value. Unit: Clocks.
16959  */
16960 #define DDRC_DRAMTMG13_SHADOW_ODTLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_ODTLOFF_SHIFT)) & DDRC_DRAMTMG13_SHADOW_ODTLOFF_MASK)
16961 /*! @} */
16962 
16963 /*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
16964 /*! @{ */
16965 
16966 #define DDRC_DRAMTMG14_SHADOW_T_XSR_MASK         (0xFFFU)
16967 #define DDRC_DRAMTMG14_SHADOW_T_XSR_SHIFT        (0U)
16968 /*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
16969  *    frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
16970  *    Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
16971  */
16972 #define DDRC_DRAMTMG14_SHADOW_T_XSR(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_T_XSR_SHIFT)) & DDRC_DRAMTMG14_SHADOW_T_XSR_MASK)
16973 /*! @} */
16974 
16975 /*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
16976 /*! @{ */
16977 
16978 #define DDRC_DRAMTMG15_SHADOW_T_STAB_X32_MASK    (0xFFU)
16979 #define DDRC_DRAMTMG15_SHADOW_T_STAB_X32_SHIFT   (0U)
16980 /*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
16981  *    RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
16982  *    clock must be stable for a time specified by tSTAB - in the case of input clock frequency
16983  *    change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
16984  *    DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
16985  *    recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
16986  *    cycles.
16987  */
16988 #define DDRC_DRAMTMG15_SHADOW_T_STAB_X32(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_T_STAB_X32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_T_STAB_X32_MASK)
16989 
16990 #define DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_MASK (0x80000000U)
16991 #define DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_SHIFT (31U)
16992 /*! en_dfi_lp_t_stab - - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is
16993  *    stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when
16994  *    exiting DFI LP
16995  */
16996 #define DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_SHIFT)) & DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_MASK)
16997 /*! @} */
16998 
16999 /*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
17000 /*! @{ */
17001 
17002 #define DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_MASK   (0x3FFU)
17003 #define DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_SHIFT  (0U)
17004 /*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
17005  *    of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
17006  *    When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
17007  *    round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
17008  *    LPDDR2/LPDDR3/LPDDR4 devices.
17009  */
17010 #define DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_SHIFT)) & DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_MASK)
17011 
17012 #define DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_MASK    (0x7FF0000U)
17013 #define DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_SHIFT   (16U)
17014 /*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
17015  *    clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
17016  *    issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
17017  *    this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
17018  *    tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
17019  *    up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
17020  *    LPDDR2/LPDDR3/LPDDR4 devices.
17021  */
17022 #define DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_SHIFT)) & DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_MASK)
17023 
17024 #define DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_MASK   (0x10000000U)
17025 #define DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_SHIFT  (28U)
17026 /*! dis_mpsmx_zqcl - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only
17027  *    applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving
17028  *    Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting
17029  *    DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the
17030  *    DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after
17031  *    exiting MPSM mode.
17032  */
17033 #define DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_SHIFT)) & DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_MASK)
17034 
17035 #define DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_MASK (0x20000000U)
17036 #define DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_SHIFT (29U)
17037 /*! zq_resistor_shared - - 1 - Denotes that ZQ resistor is shared between ranks. Means
17038  *    ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
17039  *    tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 -
17040  *    ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or
17041  *    LPDDR2/LPDDR3/LPDDR4 devices.
17042  */
17043 #define DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_SHIFT)) & DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_MASK)
17044 
17045 #define DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_MASK     (0x40000000U)
17046 #define DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_SHIFT    (30U)
17047 /*! dis_srx_zqcl - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at
17048  *    Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 -
17049  *    Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only
17050  *    applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for
17051  *    designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
17052  */
17053 #define DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_SHIFT)) & DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_MASK)
17054 
17055 #define DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_MASK      (0x80000000U)
17056 #define DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_SHIFT     (31U)
17057 /*! dis_auto_zq - - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register
17058  *    DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 -
17059  *    Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
17060  *    This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
17061  */
17062 #define DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_SHIFT)) & DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_MASK)
17063 /*! @} */
17064 
17065 /*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
17066 /*! @{ */
17067 
17068 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK  (0x3FU)
17069 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT (0U)
17070 /*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
17071  *    (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
17072  *    specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
17073  *    necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
17074  *    the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
17075  *    clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
17076  */
17077 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK)
17078 
17079 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK (0x3F00U)
17080 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT (8U)
17081 /*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
17082  *    when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
17083  *    DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
17084  *    supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
17085  *    DFITMG0.dfi_wrdata_use_sdr.
17086  */
17087 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK)
17088 
17089 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK (0x8000U)
17090 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT (15U)
17091 /*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
17092  *    HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
17093  *    is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
17094  *    DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
17095  *    HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
17096  *    for correct value.
17097  */
17098 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK)
17099 
17100 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK (0x7F0000U)
17101 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT (16U)
17102 /*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
17103  *    assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
17104  *    to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
17105  *    may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
17106  *    compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
17107  *    DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
17108  */
17109 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK)
17110 
17111 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK (0x800000U)
17112 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT (23U)
17113 /*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
17114  *    using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
17115  *    DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
17116  *    clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
17117  *    value.
17118  */
17119 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK)
17120 
17121 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK (0x1F000000U)
17122 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT (24U)
17123 /*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
17124  *    of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
17125  *    assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
17126  *    parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
17127  *    is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
17128  *    of DFI clock.
17129  */
17130 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK)
17131 /*! @} */
17132 
17133 /*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
17134 /*! @{ */
17135 
17136 #define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_MASK (0x1FU)
17137 #define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U)
17138 /*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
17139  *    dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
17140  *    DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
17141  *    phase aligned, this timing parameter should be rounded up to the next integer value.
17142  */
17143 #define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_MASK)
17144 
17145 #define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_MASK (0x1F00U)
17146 #define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U)
17147 /*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
17148  *    dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
17149  *    boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
17150  *    this timing parameter should be rounded up to the next integer value.
17151  */
17152 #define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_MASK)
17153 
17154 #define DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_MASK (0x1F0000U)
17155 #define DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_SHIFT (16U)
17156 /*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
17157  *    signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
17158  *    This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
17159  *    correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
17160  *    3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
17161  *    programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
17162  *    and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
17163  *    Clocks
17164  */
17165 #define DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_MASK)
17166 
17167 #define DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_MASK (0x3000000U)
17168 #define DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_SHIFT (24U)
17169 /*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
17170  *    asserted and when the associated dfi_parity_in signal is driven.
17171  */
17172 #define DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_MASK)
17173 
17174 #define DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_MASK   (0xF0000000U)
17175 #define DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_SHIFT  (28U)
17176 /*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
17177  *    asserted and when the associated command is driven. This field is used for CAL mode, should be
17178  *    set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
17179  *    can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
17180  */
17181 #define DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_MASK)
17182 /*! @} */
17183 
17184 /*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
17185 /*! @{ */
17186 
17187 #define DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_MASK (0x3FU)
17188 #define DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_SHIFT (0U)
17189 /*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
17190  *    DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
17191  *    to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
17192  */
17193 #define DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_SHIFT)) & DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_MASK)
17194 
17195 #define DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_MASK (0x7F00U)
17196 #define DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_SHIFT (8U)
17197 /*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
17198  *    control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
17199  *    to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
17200  */
17201 #define DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT(x)  (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_SHIFT)) & DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_MASK)
17202 /*! @} */
17203 
17204 /*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
17205 /*! @{ */
17206 
17207 #define DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_MASK (0x1FU)
17208 #define DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_SHIFT (0U)
17209 /*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
17210  *    ready to receive commands. Refer to PHY specification for correct value. When the controller is
17211  *    operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
17212  *    the next integer value. Unit: Clocks
17213  */
17214 #define DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_SHIFT)) & DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_MASK)
17215 /*! @} */
17216 
17217 /*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
17218 /*! @{ */
17219 
17220 #define DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_MASK     (0x7CU)
17221 #define DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_SHIFT    (2U)
17222 /*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
17223  *    values associated with that command. ODT setting must remain constant for the entire time that
17224  *    DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
17225  *    (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
17226  *    CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
17227  *    mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
17228  *    preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
17229  *    not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
17230  */
17231 #define DDRC_ODTCFG_SHADOW_RD_ODT_DELAY(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_MASK)
17232 
17233 #define DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_MASK      (0xF00U)
17234 #define DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_SHIFT     (8U)
17235 /*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
17236  *    is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
17237  *    DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
17238  *    write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
17239  *    RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
17240  */
17241 #define DDRC_ODTCFG_SHADOW_RD_ODT_HOLD(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_MASK)
17242 
17243 #define DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_MASK     (0x1F0000U)
17244 #define DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_SHIFT    (16U)
17245 /*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
17246  *    values associated with that command. ODT setting must remain constant for the entire time that
17247  *    DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
17248  *    AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
17249  *    for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
17250  *    - WL - 1 - RU(tODTon(max)/tCK))
17251  */
17252 #define DDRC_ODTCFG_SHADOW_WR_ODT_DELAY(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_MASK)
17253 
17254 #define DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_MASK      (0xF000000U)
17255 #define DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_SHIFT     (24U)
17256 /*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
17257  *    is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
17258  *    - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
17259  *    5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
17260  *    CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
17261  */
17262 #define DDRC_ODTCFG_SHADOW_WR_ODT_HOLD(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_MASK)
17263 /*! @} */
17264 
17265 
17266 /*!
17267  * @}
17268  */ /* end of group DDRC_Register_Masks */
17269 
17270 
17271 /* DDRC - Peripheral instance base addresses */
17272 /** Peripheral DDRC base address */
17273 #define DDRC_BASE                                (0x3D400000u)
17274 /** Peripheral DDRC base pointer */
17275 #define DDRC                                     ((DDRC_Type *)DDRC_BASE)
17276 /** Array initializer of DDRC peripheral base addresses */
17277 #define DDRC_BASE_ADDRS                          { DDRC_BASE }
17278 /** Array initializer of DDRC peripheral base pointers */
17279 #define DDRC_BASE_PTRS                           { DDRC }
17280 
17281 /*!
17282  * @}
17283  */ /* end of group DDRC_Peripheral_Access_Layer */
17284 
17285 
17286 /* ----------------------------------------------------------------------------
17287    -- DDR_BLK_CTL Peripheral Access Layer
17288    ---------------------------------------------------------------------------- */
17289 
17290 /*!
17291  * @addtogroup DDR_BLK_CTL_Peripheral_Access_Layer DDR_BLK_CTL Peripheral Access Layer
17292  * @{
17293  */
17294 
17295 /** DDR_BLK_CTL - Register Layout Typedef */
17296 typedef struct {
17297        uint8_t RESERVED_0[256];
17298   __IO uint32_t DDR_SS_GPR0;                       /**< DDR Subsystem General Purpose Register 0, offset: 0x100 */
17299 } DDR_BLK_CTL_Type;
17300 
17301 /* ----------------------------------------------------------------------------
17302    -- DDR_BLK_CTL Register Masks
17303    ---------------------------------------------------------------------------- */
17304 
17305 /*!
17306  * @addtogroup DDR_BLK_CTL_Register_Masks DDR_BLK_CTL Register Masks
17307  * @{
17308  */
17309 
17310 /*! @name DDR_SS_GPR0 - DDR Subsystem General Purpose Register 0 */
17311 /*! @{ */
17312 
17313 #define DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_MASK    (0xFFFFFFFFU)
17314 #define DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_SHIFT   (0U)
17315 /*! DDR_MODE - DDR Mode
17316  *  0b00000000000000000000000000000001..LPDDR4 Mode
17317  *  0b00000000000000000000000000000000..DDR4/DDR4L Mode
17318  */
17319 #define DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE(x)      (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_SHIFT)) & DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_MASK)
17320 /*! @} */
17321 
17322 
17323 /*!
17324  * @}
17325  */ /* end of group DDR_BLK_CTL_Register_Masks */
17326 
17327 
17328 /* DDR_BLK_CTL - Peripheral instance base addresses */
17329 /** Peripheral DDR_BLK_CTRL base address */
17330 #define DDR_BLK_CTRL_BASE                        (0x3D000000u)
17331 /** Peripheral DDR_BLK_CTRL base pointer */
17332 #define DDR_BLK_CTRL                             ((DDR_BLK_CTL_Type *)DDR_BLK_CTRL_BASE)
17333 /** Array initializer of DDR_BLK_CTL peripheral base addresses */
17334 #define DDR_BLK_CTL_BASE_ADDRS                   { DDR_BLK_CTRL_BASE }
17335 /** Array initializer of DDR_BLK_CTL peripheral base pointers */
17336 #define DDR_BLK_CTL_BASE_PTRS                    { DDR_BLK_CTRL }
17337 
17338 /*!
17339  * @}
17340  */ /* end of group DDR_BLK_CTL_Peripheral_Access_Layer */
17341 
17342 
17343 /* ----------------------------------------------------------------------------
17344    -- DMA Peripheral Access Layer
17345    ---------------------------------------------------------------------------- */
17346 
17347 /*!
17348  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
17349  * @{
17350  */
17351 
17352 /** DMA - Register Layout Typedef */
17353 typedef struct {
17354   __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
17355   __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
17356   __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
17357   __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
17358        uint8_t RESERVED_0[240];
17359   __IO uint32_t CH_GRPRI[32];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
17360        uint8_t RESERVED_1[65152];
17361   struct {                                         /* offset: 0x10000, array step: 0x1000 */
17362     __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x10000, array step: 0x1000 */
17363     __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x10004, array step: 0x1000 */
17364     __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x1000 */
17365     __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x1000C, array step: 0x1000 */
17366     __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x10010, array step: 0x1000 */
17367          uint8_t RESERVED_0[12];
17368     __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x10020, array step: 0x1000 */
17369     __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x1000 */
17370     __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x1000 */
17371     union {                                          /* offset: 0x10028, array step: 0x1000 */
17372       __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x10028, array step: 0x1000 */
17373       __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x1000 */
17374     };
17375     __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x1000 */
17376     __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x10030, array step: 0x1000 */
17377     __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x1000 */
17378     union {                                          /* offset: 0x10036, array step: 0x1000 */
17379       __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x1000 */
17380       __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x1000 */
17381     };
17382     __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x1000 */
17383     __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x1003C, array step: 0x1000 */
17384     union {                                          /* offset: 0x1003E, array step: 0x1000 */
17385       __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x1000 */
17386       __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x1000 */
17387     };
17388          uint8_t RESERVED_1[4032];
17389   } CH[32];
17390 } DMA_Type;
17391 
17392 /* ----------------------------------------------------------------------------
17393    -- DMA Register Masks
17394    ---------------------------------------------------------------------------- */
17395 
17396 /*!
17397  * @addtogroup DMA_Register_Masks DMA Register Masks
17398  * @{
17399  */
17400 
17401 /*! @name MP_CSR - Management Page Control */
17402 /*! @{ */
17403 
17404 #define DMA_MP_CSR_EDBG_MASK                     (0x2U)
17405 #define DMA_MP_CSR_EDBG_SHIFT                    (1U)
17406 /*! EDBG - Enable Debug
17407  *  0b0..Debug mode disabled
17408  *  0b1..Debug mode is enabled.
17409  */
17410 #define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
17411 
17412 #define DMA_MP_CSR_ERCA_MASK                     (0x4U)
17413 #define DMA_MP_CSR_ERCA_SHIFT                    (2U)
17414 /*! ERCA - Enable Round Robin Channel Arbitration
17415  *  0b0..Round-robin channel arbitration disabled
17416  *  0b1..Round-robin channel arbitration enabled
17417  */
17418 #define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
17419 
17420 #define DMA_MP_CSR_HAE_MASK                      (0x10U)
17421 #define DMA_MP_CSR_HAE_SHIFT                     (4U)
17422 /*! HAE - Halt After Error
17423  *  0b0..Normal operation
17424  *  0b1..Any error causes the HALT field to be set to 1
17425  */
17426 #define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
17427 
17428 #define DMA_MP_CSR_HALT_MASK                     (0x20U)
17429 #define DMA_MP_CSR_HALT_SHIFT                    (5U)
17430 /*! HALT - Halt DMA Operations
17431  *  0b0..Normal operation
17432  *  0b1..Stall the start of any new channels
17433  */
17434 #define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
17435 
17436 #define DMA_MP_CSR_GCLC_MASK                     (0x40U)
17437 #define DMA_MP_CSR_GCLC_SHIFT                    (6U)
17438 /*! GCLC - Global Channel Linking Control
17439  *  0b0..Channel linking disabled for all channels
17440  *  0b1..Channel linking available and controlled by each channel's link settings
17441  */
17442 #define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
17443 
17444 #define DMA_MP_CSR_GMRC_MASK                     (0x80U)
17445 #define DMA_MP_CSR_GMRC_SHIFT                    (7U)
17446 /*! GMRC - Global Master ID Replication Control
17447  *  0b0..Master ID replication disabled for all channels
17448  *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
17449  */
17450 #define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
17451 
17452 #define DMA_MP_CSR_ECX_MASK                      (0x100U)
17453 #define DMA_MP_CSR_ECX_SHIFT                     (8U)
17454 /*! ECX - Cancel Transfer With Error
17455  *  0b0..Normal operation
17456  *  0b1..Cancel the remaining data transfer
17457  */
17458 #define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
17459 
17460 #define DMA_MP_CSR_CX_MASK                       (0x200U)
17461 #define DMA_MP_CSR_CX_SHIFT                      (9U)
17462 /*! CX - Cancel Transfer
17463  *  0b0..Normal operation
17464  *  0b1..Cancel the remaining data transfer
17465  */
17466 #define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
17467 
17468 #define DMA_MP_CSR_ACTIVE_ID_MASK                (0x1F000000U)
17469 #define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
17470 /*! ACTIVE_ID - Active Channel ID */
17471 #define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)
17472 
17473 #define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
17474 #define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
17475 /*! ACTIVE - DMA Active Status
17476  *  0b0..eDMA is idle
17477  *  0b1..eDMA is executing a channel
17478  */
17479 #define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
17480 /*! @} */
17481 
17482 /*! @name MP_ES - Management Page Error Status */
17483 /*! @{ */
17484 
17485 #define DMA_MP_ES_DBE_MASK                       (0x1U)
17486 #define DMA_MP_ES_DBE_SHIFT                      (0U)
17487 /*! DBE - Destination Bus Error
17488  *  0b0..No destination bus error
17489  *  0b1..Last recorded error was a bus error on a destination write
17490  */
17491 #define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
17492 
17493 #define DMA_MP_ES_SBE_MASK                       (0x2U)
17494 #define DMA_MP_ES_SBE_SHIFT                      (1U)
17495 /*! SBE - Source Bus Error
17496  *  0b0..No source bus error
17497  *  0b1..Last recorded error was a bus error on a source read
17498  */
17499 #define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
17500 
17501 #define DMA_MP_ES_SGE_MASK                       (0x4U)
17502 #define DMA_MP_ES_SGE_SHIFT                      (2U)
17503 /*! SGE - Scatter/Gather Configuration Error
17504  *  0b0..No scatter/gather configuration error
17505  *  0b1..Last recorded error was a configuration error detected in the TCDn_DLASTSGA field
17506  */
17507 #define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
17508 
17509 #define DMA_MP_ES_NCE_MASK                       (0x8U)
17510 #define DMA_MP_ES_NCE_SHIFT                      (3U)
17511 /*! NCE - NBYTES/CITER Configuration Error
17512  *  0b0..No NBYTES/CITER configuration error
17513  *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
17514  */
17515 #define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
17516 
17517 #define DMA_MP_ES_DOE_MASK                       (0x10U)
17518 #define DMA_MP_ES_DOE_SHIFT                      (4U)
17519 /*! DOE - Destination Offset Error
17520  *  0b0..No destination offset configuration error
17521  *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
17522  */
17523 #define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
17524 
17525 #define DMA_MP_ES_DAE_MASK                       (0x20U)
17526 #define DMA_MP_ES_DAE_SHIFT                      (5U)
17527 /*! DAE - Destination Address Error
17528  *  0b0..No destination address configuration error
17529  *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
17530  */
17531 #define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
17532 
17533 #define DMA_MP_ES_SOE_MASK                       (0x40U)
17534 #define DMA_MP_ES_SOE_SHIFT                      (6U)
17535 /*! SOE - Source Offset Error
17536  *  0b0..No source offset configuration error
17537  *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
17538  */
17539 #define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
17540 
17541 #define DMA_MP_ES_SAE_MASK                       (0x80U)
17542 #define DMA_MP_ES_SAE_SHIFT                      (7U)
17543 /*! SAE - Source Address Error
17544  *  0b0..No source address configuration error
17545  *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
17546  */
17547 #define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
17548 
17549 #define DMA_MP_ES_ECX_MASK                       (0x100U)
17550 #define DMA_MP_ES_ECX_SHIFT                      (8U)
17551 /*! ECX - Transfer Canceled
17552  *  0b0..No canceled transfers
17553  *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
17554  */
17555 #define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
17556 
17557 #define DMA_MP_ES_ERRCHN_MASK                    (0x1F000000U)
17558 #define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
17559 /*! ERRCHN - Error Channel Number or Canceled Channel Number */
17560 #define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)
17561 
17562 #define DMA_MP_ES_VLD_MASK                       (0x80000000U)
17563 #define DMA_MP_ES_VLD_SHIFT                      (31U)
17564 /*! VLD - Valid
17565  *  0b0..No ERR fields are set to 1
17566  *  0b1..At least one ERR field is set to 1, indicating a valid error exists that software has not cleared
17567  */
17568 #define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
17569 /*! @} */
17570 
17571 /*! @name MP_INT - Management Page Interrupt Request Status */
17572 /*! @{ */
17573 
17574 #define DMA_MP_INT_INT_MASK                      (0xFFFFFFFFU)
17575 #define DMA_MP_INT_INT_SHIFT                     (0U)
17576 /*! INT - Interrupt Request Status */
17577 #define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
17578 /*! @} */
17579 
17580 /*! @name MP_HRS - Management Page Hardware Request Status */
17581 /*! @{ */
17582 
17583 #define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
17584 #define DMA_MP_HRS_HRS_SHIFT                     (0U)
17585 /*! HRS - Hardware Request Status */
17586 #define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
17587 /*! @} */
17588 
17589 /*! @name CH_GRPRI - Channel Arbitration Group */
17590 /*! @{ */
17591 
17592 #define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
17593 #define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
17594 /*! GRPRI - Arbitration Group For Channel n */
17595 #define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
17596 /*! @} */
17597 
17598 /* The count of DMA_CH_GRPRI */
17599 #define DMA_CH_GRPRI_COUNT                       (32U)
17600 
17601 /*! @name CH_CSR - Channel Control and Status */
17602 /*! @{ */
17603 
17604 #define DMA_CH_CSR_ERQ_MASK                      (0x1U)
17605 #define DMA_CH_CSR_ERQ_SHIFT                     (0U)
17606 /*! ERQ - Enable DMA Request
17607  *  0b0..DMA hardware request signal for corresponding channel disabled
17608  *  0b1..DMA hardware request signal for corresponding channel enabled
17609  */
17610 #define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
17611 
17612 #define DMA_CH_CSR_EARQ_MASK                     (0x2U)
17613 #define DMA_CH_CSR_EARQ_SHIFT                    (1U)
17614 /*! EARQ - Enable Asynchronous DMA Request In Stop Mode For Channel
17615  *  0b0..Disable asynchronous DMA request for the channel
17616  *  0b1..Enable asynchronous DMA request for the channel
17617  */
17618 #define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
17619 
17620 #define DMA_CH_CSR_EEI_MASK                      (0x4U)
17621 #define DMA_CH_CSR_EEI_SHIFT                     (2U)
17622 /*! EEI - Enable Error Interrupt
17623  *  0b0..Error signal for corresponding channel does not generate error interrupt
17624  *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
17625  */
17626 #define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
17627 
17628 #define DMA_CH_CSR_EBW_MASK                      (0x8U)
17629 #define DMA_CH_CSR_EBW_SHIFT                     (3U)
17630 /*! EBW - Enable Buffered Writes
17631  *  0b0..Buffered writes on system bus disabled
17632  *  0b1..Buffered writes on system bus enabled
17633  */
17634 #define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)
17635 
17636 #define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
17637 #define DMA_CH_CSR_DONE_SHIFT                    (30U)
17638 /*! DONE - Channel Done */
17639 #define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
17640 
17641 #define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
17642 #define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
17643 /*! ACTIVE - Channel Active */
17644 #define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
17645 /*! @} */
17646 
17647 /* The count of DMA_CH_CSR */
17648 #define DMA_CH_CSR_COUNT                         (32U)
17649 
17650 /*! @name CH_ES - Channel Error Status */
17651 /*! @{ */
17652 
17653 #define DMA_CH_ES_DBE_MASK                       (0x1U)
17654 #define DMA_CH_ES_DBE_SHIFT                      (0U)
17655 /*! DBE - Destination Bus Error
17656  *  0b0..No destination bus error
17657  *  0b1..Last recorded error was bus error on destination write
17658  */
17659 #define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
17660 
17661 #define DMA_CH_ES_SBE_MASK                       (0x2U)
17662 #define DMA_CH_ES_SBE_SHIFT                      (1U)
17663 /*! SBE - Source Bus Error
17664  *  0b0..No source bus error
17665  *  0b1..Last recorded error was bus error on source read
17666  */
17667 #define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
17668 
17669 #define DMA_CH_ES_SGE_MASK                       (0x4U)
17670 #define DMA_CH_ES_SGE_SHIFT                      (2U)
17671 /*! SGE - Scatter/Gather Configuration Error
17672  *  0b0..No scatter/gather configuration error
17673  *  0b1..Last recorded error was a configuration error detected in the TCDn_DLASTSGA field
17674  */
17675 #define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
17676 
17677 #define DMA_CH_ES_NCE_MASK                       (0x8U)
17678 #define DMA_CH_ES_NCE_SHIFT                      (3U)
17679 /*! NCE - NBYTES/CITER Configuration Error
17680  *  0b0..No NBYTES/CITER configuration error
17681  *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
17682  */
17683 #define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
17684 
17685 #define DMA_CH_ES_DOE_MASK                       (0x10U)
17686 #define DMA_CH_ES_DOE_SHIFT                      (4U)
17687 /*! DOE - Destination Offset Error
17688  *  0b0..No destination offset configuration error
17689  *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
17690  */
17691 #define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
17692 
17693 #define DMA_CH_ES_DAE_MASK                       (0x20U)
17694 #define DMA_CH_ES_DAE_SHIFT                      (5U)
17695 /*! DAE - Destination Address Error
17696  *  0b0..No destination address configuration error
17697  *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
17698  */
17699 #define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
17700 
17701 #define DMA_CH_ES_SOE_MASK                       (0x40U)
17702 #define DMA_CH_ES_SOE_SHIFT                      (6U)
17703 /*! SOE - Source Offset Error
17704  *  0b0..No source offset configuration error
17705  *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
17706  */
17707 #define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
17708 
17709 #define DMA_CH_ES_SAE_MASK                       (0x80U)
17710 #define DMA_CH_ES_SAE_SHIFT                      (7U)
17711 /*! SAE - Source Address Error
17712  *  0b0..No source address configuration error
17713  *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
17714  */
17715 #define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
17716 
17717 #define DMA_CH_ES_ERR_MASK                       (0x80000000U)
17718 #define DMA_CH_ES_ERR_SHIFT                      (31U)
17719 /*! ERR - Error In Channel
17720  *  0b0..An error in this channel has not occurred
17721  *  0b1..An error in this channel has occurred
17722  */
17723 #define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
17724 /*! @} */
17725 
17726 /* The count of DMA_CH_ES */
17727 #define DMA_CH_ES_COUNT                          (32U)
17728 
17729 /*! @name CH_INT - Channel Interrupt Status */
17730 /*! @{ */
17731 
17732 #define DMA_CH_INT_INT_MASK                      (0x1U)
17733 #define DMA_CH_INT_INT_SHIFT                     (0U)
17734 /*! INT - Interrupt Request
17735  *  0b0..Interrupt request for corresponding channel cleared
17736  *  0b1..Interrupt request for corresponding channel active
17737  */
17738 #define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
17739 /*! @} */
17740 
17741 /* The count of DMA_CH_INT */
17742 #define DMA_CH_INT_COUNT                         (32U)
17743 
17744 /*! @name CH_SBR - Channel System Bus */
17745 /*! @{ */
17746 
17747 #define DMA_CH_SBR_MID_MASK                      (0x1FU)
17748 #define DMA_CH_SBR_MID_SHIFT                     (0U)
17749 /*! MID - Master ID */
17750 #define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
17751 
17752 #define DMA_CH_SBR_PAL_MASK                      (0x8000U)
17753 #define DMA_CH_SBR_PAL_SHIFT                     (15U)
17754 /*! PAL - Privileged Access Level
17755  *  0b0..User protection level for DMA transfers
17756  *  0b1..Privileged protection level for DMA transfers
17757  */
17758 #define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
17759 
17760 #define DMA_CH_SBR_ATTR_MASK                     (0x7E0000U)
17761 #define DMA_CH_SBR_ATTR_SHIFT                    (17U)
17762 /*! ATTR - Attribute Output */
17763 #define DMA_CH_SBR_ATTR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
17764 /*! @} */
17765 
17766 /* The count of DMA_CH_SBR */
17767 #define DMA_CH_SBR_COUNT                         (32U)
17768 
17769 /*! @name CH_PRI - Channel Priority */
17770 /*! @{ */
17771 
17772 #define DMA_CH_PRI_APL_MASK                      (0x7U)
17773 #define DMA_CH_PRI_APL_SHIFT                     (0U)
17774 /*! APL - Arbitration Priority Level */
17775 #define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
17776 
17777 #define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
17778 #define DMA_CH_PRI_DPA_SHIFT                     (30U)
17779 /*! DPA - Disable Preempt Ability
17780  *  0b0..Channel can suspend a lower-priority channel
17781  *  0b1..Channel cannot suspend any other channel, regardless of channel priority
17782  */
17783 #define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
17784 
17785 #define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
17786 #define DMA_CH_PRI_ECP_SHIFT                     (31U)
17787 /*! ECP - Enable Channel Preemption
17788  *  0b0..Channel cannot be suspended by a higher-priority channel's service request
17789  *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
17790  */
17791 #define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
17792 /*! @} */
17793 
17794 /* The count of DMA_CH_PRI */
17795 #define DMA_CH_PRI_COUNT                         (32U)
17796 
17797 /*! @name TCD_SADDR - TCD Source Address */
17798 /*! @{ */
17799 
17800 #define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
17801 #define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
17802 /*! SADDR - Source Address */
17803 #define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
17804 /*! @} */
17805 
17806 /* The count of DMA_TCD_SADDR */
17807 #define DMA_TCD_SADDR_COUNT                      (32U)
17808 
17809 /*! @name TCD_SOFF - TCD Signed Source Address Offset */
17810 /*! @{ */
17811 
17812 #define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
17813 #define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
17814 /*! SOFF - Source Address Signed Offset */
17815 #define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
17816 /*! @} */
17817 
17818 /* The count of DMA_TCD_SOFF */
17819 #define DMA_TCD_SOFF_COUNT                       (32U)
17820 
17821 /*! @name TCD_ATTR - TCD Transfer Attributes */
17822 /*! @{ */
17823 
17824 #define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
17825 #define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
17826 /*! DSIZE - Destination Data Transfer Size */
17827 #define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
17828 
17829 #define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
17830 #define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
17831 /*! DMOD - Destination Address Modulo */
17832 #define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
17833 
17834 #define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
17835 #define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
17836 /*! SSIZE - Source Data Transfer Size
17837  *  0b000..8-bit
17838  *  0b001..16-bit
17839  *  0b010..32-bit
17840  *  0b011..64-bit
17841  *  0b100..16-byte
17842  *  0b101..32-byte
17843  *  0b110..64-byte
17844  *  0b111..Reserved
17845  */
17846 #define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
17847 
17848 #define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
17849 #define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
17850 /*! SMOD - Source Address Modulo
17851  *  0b00000..Source address modulo feature disabled
17852  *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
17853  */
17854 #define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
17855 /*! @} */
17856 
17857 /* The count of DMA_TCD_ATTR */
17858 #define DMA_TCD_ATTR_COUNT                       (32U)
17859 
17860 /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
17861 /*! @{ */
17862 
17863 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
17864 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
17865 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
17866 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
17867 
17868 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
17869 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
17870 /*! DMLOE - Destination Minor Loop Offset Enable
17871  *  0b0..Minor loop offset not applied to DADDR
17872  *  0b1..Minor loop offset applied to DADDR
17873  */
17874 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
17875 
17876 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
17877 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
17878 /*! SMLOE - Source Minor Loop Offset Enable
17879  *  0b0..Minor loop offset not applied to SADDR
17880  *  0b1..Minor loop offset applied to SADDR
17881  */
17882 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
17883 /*! @} */
17884 
17885 /* The count of DMA_TCD_NBYTES_MLOFFNO */
17886 #define DMA_TCD_NBYTES_MLOFFNO_COUNT             (32U)
17887 
17888 /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
17889 /*! @{ */
17890 
17891 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
17892 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
17893 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
17894 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
17895 
17896 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
17897 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
17898 /*! MLOFF - Minor Loop Offset */
17899 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
17900 
17901 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
17902 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
17903 /*! DMLOE - Destination Minor Loop Offset Enable
17904  *  0b0..Minor loop offset not applied to DADDR
17905  *  0b1..Minor loop offset applied to DADDR
17906  */
17907 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
17908 
17909 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
17910 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
17911 /*! SMLOE - Source Minor Loop Offset Enable
17912  *  0b0..Minor loop offset not applied to SADDR
17913  *  0b1..Minor loop offset applied to SADDR
17914  */
17915 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
17916 /*! @} */
17917 
17918 /* The count of DMA_TCD_NBYTES_MLOFFYES */
17919 #define DMA_TCD_NBYTES_MLOFFYES_COUNT            (32U)
17920 
17921 /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
17922 /*! @{ */
17923 
17924 #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
17925 #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
17926 /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
17927 #define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
17928 /*! @} */
17929 
17930 /* The count of DMA_TCD_SLAST_SDA */
17931 #define DMA_TCD_SLAST_SDA_COUNT                  (32U)
17932 
17933 /*! @name TCD_DADDR - TCD Destination Address */
17934 /*! @{ */
17935 
17936 #define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
17937 #define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
17938 /*! DADDR - Destination Address */
17939 #define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
17940 /*! @} */
17941 
17942 /* The count of DMA_TCD_DADDR */
17943 #define DMA_TCD_DADDR_COUNT                      (32U)
17944 
17945 /*! @name TCD_DOFF - TCD Signed Destination Address Offset */
17946 /*! @{ */
17947 
17948 #define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
17949 #define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
17950 /*! DOFF - Destination Address Signed Offset */
17951 #define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
17952 /*! @} */
17953 
17954 /* The count of DMA_TCD_DOFF */
17955 #define DMA_TCD_DOFF_COUNT                       (32U)
17956 
17957 /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
17958 /*! @{ */
17959 
17960 #define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
17961 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
17962 /*! CITER - Current Major Iteration Count */
17963 #define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
17964 
17965 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
17966 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
17967 /*! ELINK - Enable Link
17968  *  0b0..Channel-to-channel linking disabled
17969  *  0b1..Channel-to-channel linking enabled
17970  */
17971 #define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
17972 /*! @} */
17973 
17974 /* The count of DMA_TCD_CITER_ELINKNO */
17975 #define DMA_TCD_CITER_ELINKNO_COUNT              (32U)
17976 
17977 /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
17978 /*! @{ */
17979 
17980 #define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
17981 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
17982 /*! CITER - Current Major Iteration Count */
17983 #define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
17984 
17985 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x3E00U)
17986 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
17987 /*! LINKCH - Minor Loop Link Channel Number */
17988 #define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
17989 
17990 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
17991 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
17992 /*! ELINK - Enable Link
17993  *  0b0..Channel-to-channel linking disabled
17994  *  0b1..Channel-to-channel linking enabled
17995  */
17996 #define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
17997 /*! @} */
17998 
17999 /* The count of DMA_TCD_CITER_ELINKYES */
18000 #define DMA_TCD_CITER_ELINKYES_COUNT             (32U)
18001 
18002 /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
18003 /*! @{ */
18004 
18005 #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
18006 #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
18007 /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
18008 #define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
18009 /*! @} */
18010 
18011 /* The count of DMA_TCD_DLAST_SGA */
18012 #define DMA_TCD_DLAST_SGA_COUNT                  (32U)
18013 
18014 /*! @name TCD_CSR - TCD Control and Status */
18015 /*! @{ */
18016 
18017 #define DMA_TCD_CSR_START_MASK                   (0x1U)
18018 #define DMA_TCD_CSR_START_SHIFT                  (0U)
18019 /*! START - Channel Start
18020  *  0b0..Channel not explicitly started
18021  *  0b1..Channel explicitly started via a software-initiated service request
18022  */
18023 #define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
18024 
18025 #define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
18026 #define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
18027 /*! INTMAJOR - Enable Interrupt If Major count complete
18028  *  0b0..End-of-major loop interrupt disabled
18029  *  0b1..End-of-major loop interrupt enabled
18030  */
18031 #define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
18032 
18033 #define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
18034 #define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
18035 /*! INTHALF - Enable Interrupt If Major Counter Half-complete
18036  *  0b0..Halfway point interrupt disabled
18037  *  0b1..Halfway point interrupt enabled
18038  */
18039 #define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
18040 
18041 #define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
18042 #define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
18043 /*! DREQ - Disable Request
18044  *  0b0..No operation
18045  *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
18046  */
18047 #define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
18048 
18049 #define DMA_TCD_CSR_ESG_MASK                     (0x10U)
18050 #define DMA_TCD_CSR_ESG_SHIFT                    (4U)
18051 /*! ESG - Enable Scatter/Gather Processing
18052  *  0b0..Current channel's TCD is normal format
18053  *  0b1..Current channel's TCD specifies scatter/gather format.
18054  */
18055 #define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
18056 
18057 #define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
18058 #define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
18059 /*! MAJORELINK - Enable Link When Major Loop Complete
18060  *  0b0..Channel-to-channel linking disabled
18061  *  0b1..Channel-to-channel linking enabled
18062  */
18063 #define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
18064 
18065 #define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
18066 #define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
18067 /*! EEOP - Enable End-Of-Packet Processing
18068  *  0b0..End-of-packet operation disabled
18069  *  0b1..End-of-packet hardware input signal enabled
18070  */
18071 #define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
18072 
18073 #define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
18074 #define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
18075 /*! ESDA - Enable Store Destination Address
18076  *  0b0..Ability to store destination address to system memory disabled
18077  *  0b1..Ability to store destination address to system memory enabled
18078  */
18079 #define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
18080 
18081 #define DMA_TCD_CSR_MAJORLINKCH_MASK             (0x1F00U)
18082 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
18083 /*! MAJORLINKCH - Major Loop Link Channel Number */
18084 #define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)
18085 
18086 #define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
18087 #define DMA_TCD_CSR_BWC_SHIFT                    (14U)
18088 /*! BWC - Bandwidth Control
18089  *  0b00..No eDMA engine stalls
18090  *  0b01..Reserved
18091  *  0b10..eDMA engine stalls for 4 cycles after each R/W
18092  *  0b11..eDMA engine stalls for 8 cycles after each R/W
18093  */
18094 #define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
18095 /*! @} */
18096 
18097 /* The count of DMA_TCD_CSR */
18098 #define DMA_TCD_CSR_COUNT                        (32U)
18099 
18100 /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
18101 /*! @{ */
18102 
18103 #define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
18104 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
18105 /*! BITER - Starting Major Iteration Count */
18106 #define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
18107 
18108 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
18109 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
18110 /*! ELINK - Enables Link
18111  *  0b0..Channel-to-channel linking disabled
18112  *  0b1..Channel-to-channel linking enabled
18113  */
18114 #define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
18115 /*! @} */
18116 
18117 /* The count of DMA_TCD_BITER_ELINKNO */
18118 #define DMA_TCD_BITER_ELINKNO_COUNT              (32U)
18119 
18120 /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
18121 /*! @{ */
18122 
18123 #define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
18124 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
18125 /*! BITER - Starting Major Iteration Count */
18126 #define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
18127 
18128 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x3E00U)
18129 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
18130 /*! LINKCH - Link Channel Number */
18131 #define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
18132 
18133 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
18134 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
18135 /*! ELINK - Enable Link
18136  *  0b0..Channel-to-channel linking disabled
18137  *  0b1..Channel-to-channel linking enabled
18138  */
18139 #define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
18140 /*! @} */
18141 
18142 /* The count of DMA_TCD_BITER_ELINKYES */
18143 #define DMA_TCD_BITER_ELINKYES_COUNT             (32U)
18144 
18145 
18146 /*!
18147  * @}
18148  */ /* end of group DMA_Register_Masks */
18149 
18150 
18151 /* DMA - Peripheral instance base addresses */
18152 /** Peripheral EDMA1 base address */
18153 #define EDMA1_BASE                               (0x30E30000u)
18154 /** Peripheral EDMA1 base pointer */
18155 #define EDMA1                                    ((DMA_Type *)EDMA1_BASE)
18156 /** Array initializer of DMA peripheral base addresses */
18157 #define DMA_BASE_ADDRS                           { EDMA1_BASE }
18158 /** Array initializer of DMA peripheral base pointers */
18159 #define DMA_BASE_PTRS                            { EDMA1 }
18160 /** Interrupt vectors for the DMA peripheral type */
18161 #define DMA_IRQS                                 { { EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn } }
18162 #define DMA_ERROR_IRQS                           { EDMA1_ERR_IRQn }
18163 
18164 /*!
18165  * @}
18166  */ /* end of group DMA_Peripheral_Access_Layer */
18167 
18168 
18169 /* ----------------------------------------------------------------------------
18170    -- DWC_DDRPHYA_ANIB Peripheral Access Layer
18171    ---------------------------------------------------------------------------- */
18172 
18173 /*!
18174  * @addtogroup DWC_DDRPHYA_ANIB_Peripheral_Access_Layer DWC_DDRPHYA_ANIB Peripheral Access Layer
18175  * @{
18176  */
18177 
18178 /** DWC_DDRPHYA_ANIB - Register Layout Typedef */
18179 typedef struct {
18180        uint8_t RESERVED_0[52];
18181   __IO uint16_t MTESTMUXSEL;                       /**< Digital Observation Pin control, offset: 0x34 */
18182        uint8_t RESERVED_1[24];
18183   __IO uint16_t AFORCEDRVCONT;                     /**< Force Address/Command Driven (Lanes A3-A0), offset: 0x4E */
18184   __IO uint16_t AFORCETRICONT;                     /**< Force Address/Command Tristate (Lanes A3-A0), offset: 0x50 */
18185        uint8_t RESERVED_2[52];
18186   __IO uint16_t ATXIMPEDANCE;                      /**< Address TX impedance controls, offset: 0x86 */
18187        uint8_t RESERVED_3[30];
18188   __I  uint16_t ATESTPRBSERR;                      /**< Address Loopback PRBS Error status for an entire ACX4 block, offset: 0xA6 */
18189        uint8_t RESERVED_4[2];
18190   __IO uint16_t ATXSLEWRATE;                       /**< Address TX slew rate and predriver controls, offset: 0xAA */
18191   __I  uint16_t ATESTPRBSERRCNT;                   /**< Address Loopback Test Result register, offset: 0xAC */
18192        uint8_t RESERVED_5[82];
18193   __IO uint16_t ATXDLY_P0;                         /**< Address/Command Delay, per pstate., offset: 0x100 */
18194        uint8_t RESERVED_6[2097150];
18195   __IO uint16_t ATXDLY_P1;                         /**< Address/Command Delay, per pstate., offset: 0x200100 */
18196        uint8_t RESERVED_7[2097150];
18197   __IO uint16_t ATXDLY_P2;                         /**< Address/Command Delay, per pstate., offset: 0x400100 */
18198        uint8_t RESERVED_8[2097150];
18199   __IO uint16_t ATXDLY_P3;                         /**< Address/Command Delay, per pstate., offset: 0x600100 */
18200 } DWC_DDRPHYA_ANIB_Type;
18201 
18202 /* ----------------------------------------------------------------------------
18203    -- DWC_DDRPHYA_ANIB Register Masks
18204    ---------------------------------------------------------------------------- */
18205 
18206 /*!
18207  * @addtogroup DWC_DDRPHYA_ANIB_Register_Masks DWC_DDRPHYA_ANIB Register Masks
18208  * @{
18209  */
18210 
18211 /*! @name MTESTMUXSEL - Digital Observation Pin control */
18212 /*! @{ */
18213 
18214 #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_MASK (0x3FU)
18215 #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_SHIFT (0U)
18216 /*! MtestMuxSel - Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin. */
18217 #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_SHIFT)) & DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_MASK)
18218 /*! @} */
18219 
18220 /*! @name AFORCEDRVCONT - Force Address/Command Driven (Lanes A3-A0) */
18221 /*! @{ */
18222 
18223 #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_MASK (0xFU)
18224 #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_SHIFT (0U)
18225 /*! AForceDrvCont - Force continuous drive, per-lane, of the ACX4 instance controlled by this
18226  *    register Setting this register will cause the PHY to drive the target lane when dfi_init_complete==1
18227  *    Bit [0] = controls lane 0 of the target ACX4 block Bit [1] = controls lane 1 of the target
18228  *    ACX4 block Bit [2] = controls lane 2 of the target ACX4 block Bit [3] = controls lane 3 of the
18229  *    target ACX4 block
18230  */
18231 #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_SHIFT)) & DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_MASK)
18232 /*! @} */
18233 
18234 /*! @name AFORCETRICONT - Force Address/Command Tristate (Lanes A3-A0) */
18235 /*! @{ */
18236 
18237 #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_MASK (0xFU)
18238 #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_SHIFT (0U)
18239 /*! AForceTriCont - Force tristate control, per-lane, of the ACX4 instance controlled by this
18240  *    register Setting this register will cause the PHY to tristate the target lane when
18241  *    dfi_init_complete==1 Bit [0] = controls lane 0 of the target ACX4 block Bit [1] = controls lane 1 of the target
18242  *    ACX4 block Bit [2] = controls lane 2 of the target ACX4 block Bit [3] = controls lane 3 of
18243  *    the target ACX4 block
18244  */
18245 #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_SHIFT)) & DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_MASK)
18246 /*! @} */
18247 
18248 /*! @name ATXIMPEDANCE - Address TX impedance controls */
18249 /*! @{ */
18250 
18251 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_MASK (0x1FU)
18252 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_SHIFT (0U)
18253 /*! ADrvStrenP - 5 bit bus used to select the target pull up output impedance. */
18254 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_SHIFT)) & DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_MASK)
18255 
18256 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_MASK (0x3E0U)
18257 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_SHIFT (5U)
18258 /*! ADrvStrenN - 5 bit bus used to select the target pull down output impedance. */
18259 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_SHIFT)) & DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_MASK)
18260 /*! @} */
18261 
18262 /*! @name ATESTPRBSERR - Address Loopback PRBS Error status for an entire ACX4 block */
18263 /*! @{ */
18264 
18265 #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_MASK (0xFU)
18266 #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_SHIFT (0U)
18267 /*! ATestPrbsErr - Overall error indicator for each prbs bump checker. */
18268 #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_SHIFT)) & DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_MASK)
18269 /*! @} */
18270 
18271 /*! @name ATXSLEWRATE - Address TX slew rate and predriver controls */
18272 /*! @{ */
18273 
18274 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_MASK (0xFU)
18275 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_SHIFT (0U)
18276 /*! ATxPreP - 4 bit binary trim for the driver pull up slew rate. */
18277 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_MASK)
18278 
18279 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_MASK (0xF0U)
18280 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_SHIFT (4U)
18281 /*! ATxPreN - 4 bit binary trim for the driver pull down slew rate. */
18282 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_MASK)
18283 
18284 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_MASK (0x700U)
18285 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_SHIFT (8U)
18286 /*! ATxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
18287 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_MASK)
18288 /*! @} */
18289 
18290 /*! @name ATESTPRBSERRCNT - Address Loopback Test Result register */
18291 /*! @{ */
18292 
18293 #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_MASK (0xFFFFU)
18294 #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_SHIFT (0U)
18295 /*! ATestPrbsErrCnt - Overall error indicator for each prbs bump checker. */
18296 #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_SHIFT)) & DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_MASK)
18297 /*! @} */
18298 
18299 /*! @name ATXDLY_P0 - Address/Command Delay, per pstate. */
18300 /*! @{ */
18301 
18302 #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_MASK (0x7FU)
18303 #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_SHIFT (0U)
18304 /*! ATxDly_p0 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4. */
18305 #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_MASK)
18306 /*! @} */
18307 
18308 /*! @name ATXDLY_P1 - Address/Command Delay, per pstate. */
18309 /*! @{ */
18310 
18311 #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_MASK (0x7FU)
18312 #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_SHIFT (0U)
18313 /*! ATxDly_p1 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4. */
18314 #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_MASK)
18315 /*! @} */
18316 
18317 /*! @name ATXDLY_P2 - Address/Command Delay, per pstate. */
18318 /*! @{ */
18319 
18320 #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_MASK (0x7FU)
18321 #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_SHIFT (0U)
18322 /*! ATxDly_p2 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4. */
18323 #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_MASK)
18324 /*! @} */
18325 
18326 /*! @name ATXDLY_P3 - Address/Command Delay, per pstate. */
18327 /*! @{ */
18328 
18329 #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_MASK (0x7FU)
18330 #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_SHIFT (0U)
18331 /*! ATxDly_p3 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4. */
18332 #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_MASK)
18333 /*! @} */
18334 
18335 
18336 /*!
18337  * @}
18338  */ /* end of group DWC_DDRPHYA_ANIB_Register_Masks */
18339 
18340 
18341 /* DWC_DDRPHYA_ANIB - Peripheral instance base addresses */
18342 /** Peripheral DWC_DDRPHYA_ANIB0 base address */
18343 #define DWC_DDRPHYA_ANIB0_BASE                   (0x3C000000u)
18344 /** Peripheral DWC_DDRPHYA_ANIB0 base pointer */
18345 #define DWC_DDRPHYA_ANIB0                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB0_BASE)
18346 /** Peripheral DWC_DDRPHYA_ANIB1 base address */
18347 #define DWC_DDRPHYA_ANIB1_BASE                   (0x3C001000u)
18348 /** Peripheral DWC_DDRPHYA_ANIB1 base pointer */
18349 #define DWC_DDRPHYA_ANIB1                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB1_BASE)
18350 /** Peripheral DWC_DDRPHYA_ANIB2 base address */
18351 #define DWC_DDRPHYA_ANIB2_BASE                   (0x3C002000u)
18352 /** Peripheral DWC_DDRPHYA_ANIB2 base pointer */
18353 #define DWC_DDRPHYA_ANIB2                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB2_BASE)
18354 /** Peripheral DWC_DDRPHYA_ANIB3 base address */
18355 #define DWC_DDRPHYA_ANIB3_BASE                   (0x3C003000u)
18356 /** Peripheral DWC_DDRPHYA_ANIB3 base pointer */
18357 #define DWC_DDRPHYA_ANIB3                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB3_BASE)
18358 /** Peripheral DWC_DDRPHYA_ANIB4 base address */
18359 #define DWC_DDRPHYA_ANIB4_BASE                   (0x3C004000u)
18360 /** Peripheral DWC_DDRPHYA_ANIB4 base pointer */
18361 #define DWC_DDRPHYA_ANIB4                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB4_BASE)
18362 /** Peripheral DWC_DDRPHYA_ANIB5 base address */
18363 #define DWC_DDRPHYA_ANIB5_BASE                   (0x3C005000u)
18364 /** Peripheral DWC_DDRPHYA_ANIB5 base pointer */
18365 #define DWC_DDRPHYA_ANIB5                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB5_BASE)
18366 /** Peripheral DWC_DDRPHYA_ANIB6 base address */
18367 #define DWC_DDRPHYA_ANIB6_BASE                   (0x3C006000u)
18368 /** Peripheral DWC_DDRPHYA_ANIB6 base pointer */
18369 #define DWC_DDRPHYA_ANIB6                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB6_BASE)
18370 /** Peripheral DWC_DDRPHYA_ANIB7 base address */
18371 #define DWC_DDRPHYA_ANIB7_BASE                   (0x3C007000u)
18372 /** Peripheral DWC_DDRPHYA_ANIB7 base pointer */
18373 #define DWC_DDRPHYA_ANIB7                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB7_BASE)
18374 /** Peripheral DWC_DDRPHYA_ANIB8 base address */
18375 #define DWC_DDRPHYA_ANIB8_BASE                   (0x3C008000u)
18376 /** Peripheral DWC_DDRPHYA_ANIB8 base pointer */
18377 #define DWC_DDRPHYA_ANIB8                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB8_BASE)
18378 /** Peripheral DWC_DDRPHYA_ANIB9 base address */
18379 #define DWC_DDRPHYA_ANIB9_BASE                   (0x3C009000u)
18380 /** Peripheral DWC_DDRPHYA_ANIB9 base pointer */
18381 #define DWC_DDRPHYA_ANIB9                        ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB9_BASE)
18382 /** Array initializer of DWC_DDRPHYA_ANIB peripheral base addresses */
18383 #define DWC_DDRPHYA_ANIB_BASE_ADDRS              { DWC_DDRPHYA_ANIB0_BASE, DWC_DDRPHYA_ANIB1_BASE, DWC_DDRPHYA_ANIB2_BASE, DWC_DDRPHYA_ANIB3_BASE, DWC_DDRPHYA_ANIB4_BASE, DWC_DDRPHYA_ANIB5_BASE, DWC_DDRPHYA_ANIB6_BASE, DWC_DDRPHYA_ANIB7_BASE, DWC_DDRPHYA_ANIB8_BASE, DWC_DDRPHYA_ANIB9_BASE }
18384 /** Array initializer of DWC_DDRPHYA_ANIB peripheral base pointers */
18385 #define DWC_DDRPHYA_ANIB_BASE_PTRS               { DWC_DDRPHYA_ANIB0, DWC_DDRPHYA_ANIB1, DWC_DDRPHYA_ANIB2, DWC_DDRPHYA_ANIB3, DWC_DDRPHYA_ANIB4, DWC_DDRPHYA_ANIB5, DWC_DDRPHYA_ANIB6, DWC_DDRPHYA_ANIB7, DWC_DDRPHYA_ANIB8, DWC_DDRPHYA_ANIB9 }
18386 
18387 /*!
18388  * @}
18389  */ /* end of group DWC_DDRPHYA_ANIB_Peripheral_Access_Layer */
18390 
18391 
18392 /* ----------------------------------------------------------------------------
18393    -- DWC_DDRPHYA_APBONLY Peripheral Access Layer
18394    ---------------------------------------------------------------------------- */
18395 
18396 /*!
18397  * @addtogroup DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer DWC_DDRPHYA_APBONLY Peripheral Access Layer
18398  * @{
18399  */
18400 
18401 /** DWC_DDRPHYA_APBONLY - Register Layout Typedef */
18402 typedef struct {
18403   __IO uint16_t MICROCONTMUXSEL;                   /**< PMU Config Mux Select, offset: 0x0 */
18404        uint8_t RESERVED_0[6];
18405   __I  uint16_t UCTSHADOWREGS;                     /**< PMU/Controller Protocol - Controller Read-only Shadow, offset: 0x8 */
18406        uint8_t RESERVED_1[86];
18407   __IO uint16_t DCTWRITEONLY;                      /**< Reserved for future use., offset: 0x60 */
18408   __IO uint16_t DCTWRITEPROT;                      /**< DCT downstream mailbox protocol CSR., offset: 0x62 */
18409   __I  uint16_t UCTWRITEONLYSHADOW;                /**< Read-only view of the csr UctDatWriteOnly, offset: 0x64 */
18410        uint8_t RESERVED_2[2];
18411   __I  uint16_t UCTDATWRITEONLYSHADOW;             /**< Read-only view of the csr UctDatWriteOnly, offset: 0x68 */
18412        uint8_t RESERVED_3[4];
18413   __IO uint16_t DFICFGRDDATAVALIDTICKS;            /**< Number of DfiClk ticks required for valid csr Rd Data., offset: 0x6E */
18414        uint8_t RESERVED_4[194];
18415   __IO uint16_t MICRORESET;                        /**< Controls reset and clock shutdown on the local microcontroller, offset: 0x132 */
18416        uint8_t RESERVED_5[192];
18417   __I  uint16_t DFIINITCOMPLETESHADOW;             /**< dfi_init_complete - Controller Read-only Shadow, offset: 0x1F4 */
18418 } DWC_DDRPHYA_APBONLY_Type;
18419 
18420 /* ----------------------------------------------------------------------------
18421    -- DWC_DDRPHYA_APBONLY Register Masks
18422    ---------------------------------------------------------------------------- */
18423 
18424 /*!
18425  * @addtogroup DWC_DDRPHYA_APBONLY_Register_Masks DWC_DDRPHYA_APBONLY Register Masks
18426  * @{
18427  */
18428 
18429 /*! @name MICROCONTMUXSEL - PMU Config Mux Select */
18430 /*! @{ */
18431 
18432 #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_MASK (0x1U)
18433 #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_SHIFT (0U)
18434 /*! MicroContMuxSel - This register controls access to the PHY configuration registers. */
18435 #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_SHIFT)) & DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_MASK)
18436 /*! @} */
18437 
18438 /*! @name UCTSHADOWREGS - PMU/Controller Protocol - Controller Read-only Shadow */
18439 /*! @{ */
18440 
18441 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_MASK (0x1U)
18442 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_SHIFT (0U)
18443 /*! UctWriteProtShadow - When set to 0, the PMU has a message for the user */
18444 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_MASK)
18445 
18446 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_MASK (0x2U)
18447 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_SHIFT (1U)
18448 /*! UctDatWriteProtShadow - Reserved for future use. */
18449 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_MASK)
18450 /*! @} */
18451 
18452 /*! @name DCTWRITEONLY - Reserved for future use. */
18453 /*! @{ */
18454 
18455 #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_MASK (0xFFFFU)
18456 #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_SHIFT (0U)
18457 /*! DctWriteOnly - Reserved for future use. */
18458 #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_SHIFT)) & DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_MASK)
18459 /*! @} */
18460 
18461 /*! @name DCTWRITEPROT - DCT downstream mailbox protocol CSR. */
18462 /*! @{ */
18463 
18464 #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_MASK (0x1U)
18465 #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_SHIFT (0U)
18466 /*! DctWriteProt - By setting this register to 0, the user acknowledges the receipt of the message. */
18467 #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_SHIFT)) & DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_MASK)
18468 /*! @} */
18469 
18470 /*! @name UCTWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
18471 /*! @{ */
18472 
18473 #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_MASK (0xFFFFU)
18474 #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_SHIFT (0U)
18475 /*! UctWriteOnlyShadow - Used to pass the message ID for major messages. */
18476 #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_MASK)
18477 /*! @} */
18478 
18479 /*! @name UCTDATWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
18480 /*! @{ */
18481 
18482 #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_MASK (0xFFFFU)
18483 #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_SHIFT (0U)
18484 /*! UctDatWriteOnlyShadow - Used to pass the upper 16 bits for streaming messages. */
18485 #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_MASK)
18486 /*! @} */
18487 
18488 /*! @name DFICFGRDDATAVALIDTICKS - Number of DfiClk ticks required for valid csr Rd Data. */
18489 /*! @{ */
18490 
18491 #define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_MASK (0x3FU)
18492 #define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_SHIFT (0U)
18493 /*! DfiCfgRdDataValidTicks - Roundtrip delay of a register read access. */
18494 #define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_SHIFT)) & DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_MASK)
18495 /*! @} */
18496 
18497 /*! @name MICRORESET - Controls reset and clock shutdown on the local microcontroller */
18498 /*! @{ */
18499 
18500 #define DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_MASK (0x1U)
18501 #define DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_SHIFT (0U)
18502 /*! StallToMicro - Set this bit to stall the microcontroller by hardware. */
18503 #define DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_MASK)
18504 
18505 #define DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_MASK (0x2U)
18506 #define DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_SHIFT (1U)
18507 /*! TestWakeup - Reserved. */
18508 #define DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_MASK)
18509 
18510 #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_MASK (0x4U)
18511 #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_SHIFT (2U)
18512 /*! RSVDMicro - RSVD */
18513 #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_MASK)
18514 
18515 #define DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_MASK (0x8U)
18516 #define DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_SHIFT (3U)
18517 /*! ResetToMicro - Set this bit to apply synchronous reset to the microcontroller. */
18518 #define DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_MASK)
18519 /*! @} */
18520 
18521 /*! @name DFIINITCOMPLETESHADOW - dfi_init_complete - Controller Read-only Shadow */
18522 /*! @{ */
18523 
18524 #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_MASK (0x1U)
18525 #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_SHIFT (0U)
18526 /*! DfiInitCompleteShadow - This csr presents a read-only view (a shadow) of the Register
18527  *    DfiInitComplete which is used by the sequencer to control the state of dfi_init_complete.
18528  */
18529 #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_MASK)
18530 /*! @} */
18531 
18532 
18533 /*!
18534  * @}
18535  */ /* end of group DWC_DDRPHYA_APBONLY_Register_Masks */
18536 
18537 
18538 /* DWC_DDRPHYA_APBONLY - Peripheral instance base addresses */
18539 /** Peripheral DWC_DDRPHYA_APBONLY0 base address */
18540 #define DWC_DDRPHYA_APBONLY0_BASE                (0x3C0D0000u)
18541 /** Peripheral DWC_DDRPHYA_APBONLY0 base pointer */
18542 #define DWC_DDRPHYA_APBONLY0                     ((DWC_DDRPHYA_APBONLY_Type *)DWC_DDRPHYA_APBONLY0_BASE)
18543 /** Array initializer of DWC_DDRPHYA_APBONLY peripheral base addresses */
18544 #define DWC_DDRPHYA_APBONLY_BASE_ADDRS           { DWC_DDRPHYA_APBONLY0_BASE }
18545 /** Array initializer of DWC_DDRPHYA_APBONLY peripheral base pointers */
18546 #define DWC_DDRPHYA_APBONLY_BASE_PTRS            { DWC_DDRPHYA_APBONLY0 }
18547 
18548 /*!
18549  * @}
18550  */ /* end of group DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer */
18551 
18552 
18553 /* ----------------------------------------------------------------------------
18554    -- DWC_DDRPHYA_DBYTE Peripheral Access Layer
18555    ---------------------------------------------------------------------------- */
18556 
18557 /*!
18558  * @addtogroup DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer DWC_DDRPHYA_DBYTE Peripheral Access Layer
18559  * @{
18560  */
18561 
18562 /** DWC_DDRPHYA_DBYTE - Register Layout Typedef */
18563 typedef struct {
18564   __IO uint16_t DBYTEMISCMODE;                     /**< DBYTE Module Disable, offset: 0x0 */
18565        uint8_t RESERVED_0[50];
18566   __IO uint16_t MTESTMUXSEL;                       /**< Digital Observation Pin control, offset: 0x34 */
18567        uint8_t RESERVED_1[10];
18568   __IO uint16_t DFIMRL_P0;                         /**< DFI MaxReadLatency, offset: 0x40 */
18569        uint8_t RESERVED_2[30];
18570   __IO uint16_t VREFDAC1_R0;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x60 */
18571        uint8_t RESERVED_3[30];
18572   __IO uint16_t VREFDAC0_R0;                       /**< VrefDAC0 control for DQ Receiver, offset: 0x80 */
18573   __IO uint16_t TXIMPEDANCECTRL0_B0_P0;            /**< Data TX impedance controls, offset: 0x82 */
18574        uint8_t RESERVED_4[2];
18575   __IO uint16_t DQDQSRCVCNTRL_B0_P0;               /**< Dq/Dqs receiver control, offset: 0x86 */
18576        uint8_t RESERVED_5[8];
18577   __IO uint16_t TXEQUALIZATIONMODE_P0;             /**< Tx dq driver equalization mode controls., offset: 0x90 */
18578   __IO uint16_t TXIMPEDANCECTRL1_B0_P0;            /**< TX impedance controls, offset: 0x92 */
18579   __IO uint16_t DQDQSRCVCNTRL1;                    /**< Dq/Dqs receiver control, offset: 0x94 */
18580   __IO uint16_t TXIMPEDANCECTRL2_B0_P0;            /**< TX equalization impedance controls, offset: 0x96 */
18581   __IO uint16_t DQDQSRCVCNTRL2_P0;                 /**< Dq/Dqs receiver control, offset: 0x98 */
18582   __IO uint16_t TXODTDRVSTREN_B0_P0;               /**< TX ODT driver strength control, offset: 0x9A */
18583        uint8_t RESERVED_6[16];
18584   __I  uint16_t RXFIFOCHECKSTATUS;                 /**< Status of RX FIFO Consistency Checks, offset: 0xAC */
18585   __I  uint16_t RXFIFOCHECKERRVALUES;              /**< Contains the captured values associated with an RxFifo consistency error, offset: 0xAE */
18586   __I  uint16_t RXFIFOINFO;                        /**< Data Receive FIFO Pointer Values, offset: 0xB0 */
18587   __IO uint16_t RXFIFOVISIBILITY;                  /**< RX FIFO visibility, offset: 0xB2 */
18588   __I  uint16_t RXFIFOCONTENTSDQ3210;              /**< RX FIFO contents, lane[3:0], offset: 0xB4 */
18589   __I  uint16_t RXFIFOCONTENTSDQ7654;              /**< RX FIFO contents, lane[7:4], offset: 0xB6 */
18590   __I  uint16_t RXFIFOCONTENTSDBI;                 /**< RX FIFO contents, dbi, offset: 0xB8 */
18591        uint8_t RESERVED_7[4];
18592   __IO uint16_t TXSLEWRATE_B0_P0;                  /**< TX slew rate controls, offset: 0xBE */
18593        uint8_t RESERVED_8[16];
18594   __IO uint16_t RXPBDLYTG0_R0;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xD0 */
18595   __IO uint16_t RXPBDLYTG1_R0;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xD2 */
18596   __IO uint16_t RXPBDLYTG2_R0;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xD4 */
18597   __IO uint16_t RXPBDLYTG3_R0;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xD6 */
18598        uint8_t RESERVED_9[40];
18599   __IO uint16_t RXENDLYTG0_U0_P0;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x100 */
18600   __IO uint16_t RXENDLYTG1_U0_P0;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x102 */
18601   __IO uint16_t RXENDLYTG2_U0_P0;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x104 */
18602   __IO uint16_t RXENDLYTG3_U0_P0;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x106 */
18603        uint8_t RESERVED_10[16];
18604   __IO uint16_t RXCLKDLYTG0_U0_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x118 */
18605   __IO uint16_t RXCLKDLYTG1_U0_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x11A */
18606   __IO uint16_t RXCLKDLYTG2_U0_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x11C */
18607   __IO uint16_t RXCLKDLYTG3_U0_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x11E */
18608   __IO uint16_t RXCLKCDLYTG0_U0_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x120 */
18609   __IO uint16_t RXCLKCDLYTG1_U0_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x122 */
18610   __IO uint16_t RXCLKCDLYTG2_U0_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x124 */
18611        uint8_t RESERVED_11[2];
18612   __IO uint16_t RXCLKCDLYTG3_U0_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x128 */
18613        uint8_t RESERVED_12[22];
18614   __IO uint16_t DQLNSEL[8];                        /**< Maps Phy DQ lane to memory DQ0, array offset: 0x140, array step: 0x2 */
18615        uint8_t RESERVED_13[48];
18616   __IO uint16_t TXDQDLYTG0_R0_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x180 */
18617   __IO uint16_t TXDQDLYTG1_R0_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x182 */
18618   __IO uint16_t TXDQDLYTG2_R0_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x184 */
18619   __IO uint16_t TXDQDLYTG3_R0_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x186 */
18620        uint8_t RESERVED_14[24];
18621   __IO uint16_t TXDQSDLYTG0_U0_P0;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x1A0 */
18622   __IO uint16_t TXDQSDLYTG1_U0_P0;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x1A2 */
18623   __IO uint16_t TXDQSDLYTG2_U0_P0;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x1A4 */
18624   __IO uint16_t TXDQSDLYTG3_U0_P0;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x1A6 */
18625        uint8_t RESERVED_15[32];
18626   __I  uint16_t DXLCDLSTATUS;                      /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
18627        uint8_t RESERVED_16[150];
18628   __IO uint16_t VREFDAC1_R1;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x260 */
18629        uint8_t RESERVED_17[30];
18630   __IO uint16_t VREFDAC0_R1;                       /**< VrefDAC0 control for DQ Receiver, offset: 0x280 */
18631   __IO uint16_t TXIMPEDANCECTRL0_B1_P0;            /**< Data TX impedance controls, offset: 0x282 */
18632        uint8_t RESERVED_18[2];
18633   __IO uint16_t DQDQSRCVCNTRL_B1_P0;               /**< Dq/Dqs receiver control, offset: 0x286 */
18634        uint8_t RESERVED_19[10];
18635   __IO uint16_t TXIMPEDANCECTRL1_B1_P0;            /**< TX impedance controls, offset: 0x292 */
18636        uint8_t RESERVED_20[2];
18637   __IO uint16_t TXIMPEDANCECTRL2_B1_P0;            /**< TX equalization impedance controls, offset: 0x296 */
18638        uint8_t RESERVED_21[2];
18639   __IO uint16_t TXODTDRVSTREN_B1_P0;               /**< TX ODT driver strength control, offset: 0x29A */
18640        uint8_t RESERVED_22[34];
18641   __IO uint16_t TXSLEWRATE_B1_P0;                  /**< TX slew rate controls, offset: 0x2BE */
18642        uint8_t RESERVED_23[16];
18643   __IO uint16_t RXPBDLYTG0_R1;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x2D0 */
18644   __IO uint16_t RXPBDLYTG1_R1;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x2D2 */
18645   __IO uint16_t RXPBDLYTG2_R1;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x2D4 */
18646   __IO uint16_t RXPBDLYTG3_R1;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x2D6 */
18647        uint8_t RESERVED_24[40];
18648   __IO uint16_t RXENDLYTG0_U1_P0;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x300 */
18649   __IO uint16_t RXENDLYTG1_U1_P0;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x302 */
18650   __IO uint16_t RXENDLYTG2_U1_P0;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x304 */
18651   __IO uint16_t RXENDLYTG3_U1_P0;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x306 */
18652        uint8_t RESERVED_25[16];
18653   __IO uint16_t RXCLKDLYTG0_U1_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x318 */
18654   __IO uint16_t RXCLKDLYTG1_U1_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x31A */
18655   __IO uint16_t RXCLKDLYTG2_U1_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x31C */
18656   __IO uint16_t RXCLKDLYTG3_U1_P0;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x31E */
18657   __IO uint16_t RXCLKCDLYTG0_U1_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x320 */
18658   __IO uint16_t RXCLKCDLYTG1_U1_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x322 */
18659   __IO uint16_t RXCLKCDLYTG2_U1_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x324 */
18660        uint8_t RESERVED_26[2];
18661   __IO uint16_t RXCLKCDLYTG3_U1_P0;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x328 */
18662        uint8_t RESERVED_27[86];
18663   __IO uint16_t TXDQDLYTG0_R1_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x380 */
18664   __IO uint16_t TXDQDLYTG1_R1_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x382 */
18665   __IO uint16_t TXDQDLYTG2_R1_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x384 */
18666   __IO uint16_t TXDQDLYTG3_R1_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x386 */
18667        uint8_t RESERVED_28[24];
18668   __IO uint16_t TXDQSDLYTG0_U1_P0;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x3A0 */
18669   __IO uint16_t TXDQSDLYTG1_U1_P0;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x3A2 */
18670   __IO uint16_t TXDQSDLYTG2_U1_P0;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x3A4 */
18671   __IO uint16_t TXDQSDLYTG3_U1_P0;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x3A6 */
18672        uint8_t RESERVED_29[184];
18673   __IO uint16_t VREFDAC1_R2;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x460 */
18674        uint8_t RESERVED_30[30];
18675   __IO uint16_t VREFDAC0_R2;                       /**< VrefDAC0 control for DQ Receiver, offset: 0x480 */
18676        uint8_t RESERVED_31[78];
18677   __IO uint16_t RXPBDLYTG0_R2;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x4D0 */
18678   __IO uint16_t RXPBDLYTG1_R2;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x4D2 */
18679   __IO uint16_t RXPBDLYTG2_R2;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x4D4 */
18680   __IO uint16_t RXPBDLYTG3_R2;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x4D6 */
18681        uint8_t RESERVED_32[168];
18682   __IO uint16_t TXDQDLYTG0_R2_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x580 */
18683   __IO uint16_t TXDQDLYTG1_R2_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x582 */
18684   __IO uint16_t TXDQDLYTG2_R2_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x584 */
18685   __IO uint16_t TXDQDLYTG3_R2_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x586 */
18686        uint8_t RESERVED_33[216];
18687   __IO uint16_t VREFDAC1_R3;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x660 */
18688        uint8_t RESERVED_34[30];
18689   __IO uint16_t VREFDAC0_R3;                       /**< VrefDAC0 control for DQ Receiver, offset: 0x680 */
18690        uint8_t RESERVED_35[78];
18691   __IO uint16_t RXPBDLYTG0_R3;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x6D0 */
18692   __IO uint16_t RXPBDLYTG1_R3;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x6D2 */
18693   __IO uint16_t RXPBDLYTG2_R3;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x6D4 */
18694   __IO uint16_t RXPBDLYTG3_R3;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x6D6 */
18695        uint8_t RESERVED_36[168];
18696   __IO uint16_t TXDQDLYTG0_R3_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x780 */
18697   __IO uint16_t TXDQDLYTG1_R3_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x782 */
18698   __IO uint16_t TXDQDLYTG2_R3_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x784 */
18699   __IO uint16_t TXDQDLYTG3_R3_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x786 */
18700        uint8_t RESERVED_37[216];
18701   __IO uint16_t VREFDAC1_R4;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x860 */
18702        uint8_t RESERVED_38[30];
18703   __IO uint16_t VREFDAC0_R4;                       /**< VrefDAC0 control for DQ Receiver, offset: 0x880 */
18704        uint8_t RESERVED_39[78];
18705   __IO uint16_t RXPBDLYTG0_R4;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x8D0 */
18706   __IO uint16_t RXPBDLYTG1_R4;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x8D2 */
18707   __IO uint16_t RXPBDLYTG2_R4;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x8D4 */
18708   __IO uint16_t RXPBDLYTG3_R4;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x8D6 */
18709        uint8_t RESERVED_40[168];
18710   __IO uint16_t TXDQDLYTG0_R4_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x980 */
18711   __IO uint16_t TXDQDLYTG1_R4_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x982 */
18712   __IO uint16_t TXDQDLYTG2_R4_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x984 */
18713   __IO uint16_t TXDQDLYTG3_R4_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x986 */
18714        uint8_t RESERVED_41[216];
18715   __IO uint16_t VREFDAC1_R5;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xA60 */
18716        uint8_t RESERVED_42[30];
18717   __IO uint16_t VREFDAC0_R5;                       /**< VrefDAC0 control for DQ Receiver, offset: 0xA80 */
18718        uint8_t RESERVED_43[78];
18719   __IO uint16_t RXPBDLYTG0_R5;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xAD0 */
18720   __IO uint16_t RXPBDLYTG1_R5;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xAD2 */
18721   __IO uint16_t RXPBDLYTG2_R5;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xAD4 */
18722   __IO uint16_t RXPBDLYTG3_R5;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xAD6 */
18723        uint8_t RESERVED_44[168];
18724   __IO uint16_t TXDQDLYTG0_R5_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0xB80 */
18725   __IO uint16_t TXDQDLYTG1_R5_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0xB82 */
18726   __IO uint16_t TXDQDLYTG2_R5_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0xB84 */
18727   __IO uint16_t TXDQDLYTG3_R5_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0xB86 */
18728        uint8_t RESERVED_45[216];
18729   __IO uint16_t VREFDAC1_R6;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xC60 */
18730        uint8_t RESERVED_46[30];
18731   __IO uint16_t VREFDAC0_R6;                       /**< VrefDAC0 control for DQ Receiver, offset: 0xC80 */
18732        uint8_t RESERVED_47[78];
18733   __IO uint16_t RXPBDLYTG0_R6;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xCD0 */
18734   __IO uint16_t RXPBDLYTG1_R6;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xCD2 */
18735   __IO uint16_t RXPBDLYTG2_R6;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xCD4 */
18736   __IO uint16_t RXPBDLYTG3_R6;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xCD6 */
18737        uint8_t RESERVED_48[168];
18738   __IO uint16_t TXDQDLYTG0_R6_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0xD80 */
18739   __IO uint16_t TXDQDLYTG1_R6_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0xD82 */
18740   __IO uint16_t TXDQDLYTG2_R6_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0xD84 */
18741   __IO uint16_t TXDQDLYTG3_R6_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0xD86 */
18742        uint8_t RESERVED_49[216];
18743   __IO uint16_t VREFDAC1_R7;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xE60 */
18744        uint8_t RESERVED_50[30];
18745   __IO uint16_t VREFDAC0_R7;                       /**< VrefDAC0 control for DQ Receiver, offset: 0xE80 */
18746        uint8_t RESERVED_51[78];
18747   __IO uint16_t RXPBDLYTG0_R7;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xED0 */
18748   __IO uint16_t RXPBDLYTG1_R7;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xED2 */
18749   __IO uint16_t RXPBDLYTG2_R7;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xED4 */
18750   __IO uint16_t RXPBDLYTG3_R7;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xED6 */
18751        uint8_t RESERVED_52[168];
18752   __IO uint16_t TXDQDLYTG0_R7_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0xF80 */
18753   __IO uint16_t TXDQDLYTG1_R7_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0xF82 */
18754   __IO uint16_t TXDQDLYTG2_R7_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0xF84 */
18755   __IO uint16_t TXDQDLYTG3_R7_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0xF86 */
18756        uint8_t RESERVED_53[216];
18757   __IO uint16_t VREFDAC1_R8;                       /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x1060 */
18758        uint8_t RESERVED_54[30];
18759   __IO uint16_t VREFDAC0_R8;                       /**< VrefDAC0 control for DQ Receiver, offset: 0x1080 */
18760        uint8_t RESERVED_55[78];
18761   __IO uint16_t RXPBDLYTG0_R8;                     /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x10D0 */
18762   __IO uint16_t RXPBDLYTG1_R8;                     /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x10D2 */
18763   __IO uint16_t RXPBDLYTG2_R8;                     /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x10D4 */
18764   __IO uint16_t RXPBDLYTG3_R8;                     /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x10D6 */
18765        uint8_t RESERVED_56[168];
18766   __IO uint16_t TXDQDLYTG0_R8_P0;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x1180 */
18767   __IO uint16_t TXDQDLYTG1_R8_P0;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x1182 */
18768   __IO uint16_t TXDQDLYTG2_R8_P0;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x1184 */
18769   __IO uint16_t TXDQDLYTG3_R8_P0;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x1186 */
18770        uint8_t RESERVED_57[2092728];
18771   __IO uint16_t DFIMRL_P1;                         /**< DFI MaxReadLatency, offset: 0x200040 */
18772        uint8_t RESERVED_58[64];
18773   __IO uint16_t TXIMPEDANCECTRL0_B0_P1;            /**< Data TX impedance controls, offset: 0x200082 */
18774        uint8_t RESERVED_59[2];
18775   __IO uint16_t DQDQSRCVCNTRL_B0_P1;               /**< Dq/Dqs receiver control, offset: 0x200086 */
18776        uint8_t RESERVED_60[8];
18777   __IO uint16_t TXEQUALIZATIONMODE_P1;             /**< Tx dq driver equalization mode controls., offset: 0x200090 */
18778   __IO uint16_t TXIMPEDANCECTRL1_B0_P1;            /**< TX impedance controls, offset: 0x200092 */
18779        uint8_t RESERVED_61[2];
18780   __IO uint16_t TXIMPEDANCECTRL2_B0_P1;            /**< TX equalization impedance controls, offset: 0x200096 */
18781   __IO uint16_t DQDQSRCVCNTRL2_P1;                 /**< Dq/Dqs receiver control, offset: 0x200098 */
18782   __IO uint16_t TXODTDRVSTREN_B0_P1;               /**< TX ODT driver strength control, offset: 0x20009A */
18783        uint8_t RESERVED_62[34];
18784   __IO uint16_t TXSLEWRATE_B0_P1;                  /**< TX slew rate controls, offset: 0x2000BE */
18785        uint8_t RESERVED_63[64];
18786   __IO uint16_t RXENDLYTG0_U0_P1;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200100 */
18787   __IO uint16_t RXENDLYTG1_U0_P1;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200102 */
18788   __IO uint16_t RXENDLYTG2_U0_P1;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200104 */
18789   __IO uint16_t RXENDLYTG3_U0_P1;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200106 */
18790        uint8_t RESERVED_64[16];
18791   __IO uint16_t RXCLKDLYTG0_U0_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200118 */
18792   __IO uint16_t RXCLKDLYTG1_U0_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20011A */
18793   __IO uint16_t RXCLKDLYTG2_U0_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20011C */
18794   __IO uint16_t RXCLKDLYTG3_U0_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20011E */
18795   __IO uint16_t RXCLKCDLYTG0_U0_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200120 */
18796   __IO uint16_t RXCLKCDLYTG1_U0_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200122 */
18797   __IO uint16_t RXCLKCDLYTG2_U0_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200124 */
18798        uint8_t RESERVED_65[2];
18799   __IO uint16_t RXCLKCDLYTG3_U0_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200128 */
18800        uint8_t RESERVED_66[86];
18801   __IO uint16_t TXDQDLYTG0_R0_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200180 */
18802   __IO uint16_t TXDQDLYTG1_R0_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200182 */
18803   __IO uint16_t TXDQDLYTG2_R0_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200184 */
18804   __IO uint16_t TXDQDLYTG3_R0_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200186 */
18805        uint8_t RESERVED_67[24];
18806   __IO uint16_t TXDQSDLYTG0_U0_P1;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2001A0 */
18807   __IO uint16_t TXDQSDLYTG1_U0_P1;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2001A2 */
18808   __IO uint16_t TXDQSDLYTG2_U0_P1;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2001A4 */
18809   __IO uint16_t TXDQSDLYTG3_U0_P1;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2001A6 */
18810        uint8_t RESERVED_68[218];
18811   __IO uint16_t TXIMPEDANCECTRL0_B1_P1;            /**< Data TX impedance controls, offset: 0x200282 */
18812        uint8_t RESERVED_69[2];
18813   __IO uint16_t DQDQSRCVCNTRL_B1_P1;               /**< Dq/Dqs receiver control, offset: 0x200286 */
18814        uint8_t RESERVED_70[10];
18815   __IO uint16_t TXIMPEDANCECTRL1_B1_P1;            /**< TX impedance controls, offset: 0x200292 */
18816        uint8_t RESERVED_71[2];
18817   __IO uint16_t TXIMPEDANCECTRL2_B1_P1;            /**< TX equalization impedance controls, offset: 0x200296 */
18818        uint8_t RESERVED_72[2];
18819   __IO uint16_t TXODTDRVSTREN_B1_P1;               /**< TX ODT driver strength control, offset: 0x20029A */
18820        uint8_t RESERVED_73[34];
18821   __IO uint16_t TXSLEWRATE_B1_P1;                  /**< TX slew rate controls, offset: 0x2002BE */
18822        uint8_t RESERVED_74[64];
18823   __IO uint16_t RXENDLYTG0_U1_P1;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200300 */
18824   __IO uint16_t RXENDLYTG1_U1_P1;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200302 */
18825   __IO uint16_t RXENDLYTG2_U1_P1;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200304 */
18826   __IO uint16_t RXENDLYTG3_U1_P1;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200306 */
18827        uint8_t RESERVED_75[16];
18828   __IO uint16_t RXCLKDLYTG0_U1_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200318 */
18829   __IO uint16_t RXCLKDLYTG1_U1_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20031A */
18830   __IO uint16_t RXCLKDLYTG2_U1_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20031C */
18831   __IO uint16_t RXCLKDLYTG3_U1_P1;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20031E */
18832   __IO uint16_t RXCLKCDLYTG0_U1_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200320 */
18833   __IO uint16_t RXCLKCDLYTG1_U1_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200322 */
18834   __IO uint16_t RXCLKCDLYTG2_U1_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200324 */
18835        uint8_t RESERVED_76[2];
18836   __IO uint16_t RXCLKCDLYTG3_U1_P1;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200328 */
18837        uint8_t RESERVED_77[86];
18838   __IO uint16_t TXDQDLYTG0_R1_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200380 */
18839   __IO uint16_t TXDQDLYTG1_R1_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200382 */
18840   __IO uint16_t TXDQDLYTG2_R1_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200384 */
18841   __IO uint16_t TXDQDLYTG3_R1_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200386 */
18842        uint8_t RESERVED_78[24];
18843   __IO uint16_t TXDQSDLYTG0_U1_P1;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2003A0 */
18844   __IO uint16_t TXDQSDLYTG1_U1_P1;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2003A2 */
18845   __IO uint16_t TXDQSDLYTG2_U1_P1;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2003A4 */
18846   __IO uint16_t TXDQSDLYTG3_U1_P1;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2003A6 */
18847        uint8_t RESERVED_79[472];
18848   __IO uint16_t TXDQDLYTG0_R2_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200580 */
18849   __IO uint16_t TXDQDLYTG1_R2_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200582 */
18850   __IO uint16_t TXDQDLYTG2_R2_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200584 */
18851   __IO uint16_t TXDQDLYTG3_R2_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200586 */
18852        uint8_t RESERVED_80[504];
18853   __IO uint16_t TXDQDLYTG0_R3_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200780 */
18854   __IO uint16_t TXDQDLYTG1_R3_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200782 */
18855   __IO uint16_t TXDQDLYTG2_R3_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200784 */
18856   __IO uint16_t TXDQDLYTG3_R3_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200786 */
18857        uint8_t RESERVED_81[504];
18858   __IO uint16_t TXDQDLYTG0_R4_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200980 */
18859   __IO uint16_t TXDQDLYTG1_R4_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200982 */
18860   __IO uint16_t TXDQDLYTG2_R4_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200984 */
18861   __IO uint16_t TXDQDLYTG3_R4_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200986 */
18862        uint8_t RESERVED_82[504];
18863   __IO uint16_t TXDQDLYTG0_R5_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200B80 */
18864   __IO uint16_t TXDQDLYTG1_R5_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200B82 */
18865   __IO uint16_t TXDQDLYTG2_R5_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200B84 */
18866   __IO uint16_t TXDQDLYTG3_R5_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200B86 */
18867        uint8_t RESERVED_83[504];
18868   __IO uint16_t TXDQDLYTG0_R6_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200D80 */
18869   __IO uint16_t TXDQDLYTG1_R6_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200D82 */
18870   __IO uint16_t TXDQDLYTG2_R6_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200D84 */
18871   __IO uint16_t TXDQDLYTG3_R6_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200D86 */
18872        uint8_t RESERVED_84[504];
18873   __IO uint16_t TXDQDLYTG0_R7_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x200F80 */
18874   __IO uint16_t TXDQDLYTG1_R7_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x200F82 */
18875   __IO uint16_t TXDQDLYTG2_R7_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x200F84 */
18876   __IO uint16_t TXDQDLYTG3_R7_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x200F86 */
18877        uint8_t RESERVED_85[504];
18878   __IO uint16_t TXDQDLYTG0_R8_P1;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x201180 */
18879   __IO uint16_t TXDQDLYTG1_R8_P1;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x201182 */
18880   __IO uint16_t TXDQDLYTG2_R8_P1;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x201184 */
18881   __IO uint16_t TXDQDLYTG3_R8_P1;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x201186 */
18882        uint8_t RESERVED_86[2092728];
18883   __IO uint16_t DFIMRL_P2;                         /**< DFI MaxReadLatency, offset: 0x400040 */
18884        uint8_t RESERVED_87[64];
18885   __IO uint16_t TXIMPEDANCECTRL0_B0_P2;            /**< Data TX impedance controls, offset: 0x400082 */
18886        uint8_t RESERVED_88[2];
18887   __IO uint16_t DQDQSRCVCNTRL_B0_P2;               /**< Dq/Dqs receiver control, offset: 0x400086 */
18888        uint8_t RESERVED_89[8];
18889   __IO uint16_t TXEQUALIZATIONMODE_P2;             /**< Tx dq driver equalization mode controls., offset: 0x400090 */
18890   __IO uint16_t TXIMPEDANCECTRL1_B0_P2;            /**< TX impedance controls, offset: 0x400092 */
18891        uint8_t RESERVED_90[2];
18892   __IO uint16_t TXIMPEDANCECTRL2_B0_P2;            /**< TX equalization impedance controls, offset: 0x400096 */
18893   __IO uint16_t DQDQSRCVCNTRL2_P2;                 /**< Dq/Dqs receiver control, offset: 0x400098 */
18894   __IO uint16_t TXODTDRVSTREN_B0_P2;               /**< TX ODT driver strength control, offset: 0x40009A */
18895        uint8_t RESERVED_91[34];
18896   __IO uint16_t TXSLEWRATE_B0_P2;                  /**< TX slew rate controls, offset: 0x4000BE */
18897        uint8_t RESERVED_92[64];
18898   __IO uint16_t RXENDLYTG0_U0_P2;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400100 */
18899   __IO uint16_t RXENDLYTG1_U0_P2;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400102 */
18900   __IO uint16_t RXENDLYTG2_U0_P2;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400104 */
18901   __IO uint16_t RXENDLYTG3_U0_P2;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400106 */
18902        uint8_t RESERVED_93[16];
18903   __IO uint16_t RXCLKDLYTG0_U0_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400118 */
18904   __IO uint16_t RXCLKDLYTG1_U0_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40011A */
18905   __IO uint16_t RXCLKDLYTG2_U0_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40011C */
18906   __IO uint16_t RXCLKDLYTG3_U0_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40011E */
18907   __IO uint16_t RXCLKCDLYTG0_U0_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400120 */
18908   __IO uint16_t RXCLKCDLYTG1_U0_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400122 */
18909   __IO uint16_t RXCLKCDLYTG2_U0_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400124 */
18910        uint8_t RESERVED_94[2];
18911   __IO uint16_t RXCLKCDLYTG3_U0_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400128 */
18912        uint8_t RESERVED_95[50];
18913   __IO uint16_t PPTDQSCNTINVTRNTG0_P2;             /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015C */
18914   __IO uint16_t PPTDQSCNTINVTRNTG1_P2;             /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015E */
18915        uint8_t RESERVED_96[32];
18916   __IO uint16_t TXDQDLYTG0_R0_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400180 */
18917   __IO uint16_t TXDQDLYTG1_R0_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400182 */
18918   __IO uint16_t TXDQDLYTG2_R0_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400184 */
18919   __IO uint16_t TXDQDLYTG3_R0_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400186 */
18920        uint8_t RESERVED_97[24];
18921   __IO uint16_t TXDQSDLYTG0_U0_P2;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4001A0 */
18922   __IO uint16_t TXDQSDLYTG1_U0_P2;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4001A2 */
18923   __IO uint16_t TXDQSDLYTG2_U0_P2;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4001A4 */
18924   __IO uint16_t TXDQSDLYTG3_U0_P2;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4001A6 */
18925        uint8_t RESERVED_98[218];
18926   __IO uint16_t TXIMPEDANCECTRL0_B1_P2;            /**< Data TX impedance controls, offset: 0x400282 */
18927        uint8_t RESERVED_99[2];
18928   __IO uint16_t DQDQSRCVCNTRL_B1_P2;               /**< Dq/Dqs receiver control, offset: 0x400286 */
18929        uint8_t RESERVED_100[10];
18930   __IO uint16_t TXIMPEDANCECTRL1_B1_P2;            /**< TX impedance controls, offset: 0x400292 */
18931        uint8_t RESERVED_101[2];
18932   __IO uint16_t TXIMPEDANCECTRL2_B1_P2;            /**< TX equalization impedance controls, offset: 0x400296 */
18933        uint8_t RESERVED_102[2];
18934   __IO uint16_t TXODTDRVSTREN_B1_P2;               /**< TX ODT driver strength control, offset: 0x40029A */
18935        uint8_t RESERVED_103[34];
18936   __IO uint16_t TXSLEWRATE_B1_P2;                  /**< TX slew rate controls, offset: 0x4002BE */
18937        uint8_t RESERVED_104[64];
18938   __IO uint16_t RXENDLYTG0_U1_P2;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400300 */
18939   __IO uint16_t RXENDLYTG1_U1_P2;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400302 */
18940   __IO uint16_t RXENDLYTG2_U1_P2;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400304 */
18941   __IO uint16_t RXENDLYTG3_U1_P2;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400306 */
18942        uint8_t RESERVED_105[16];
18943   __IO uint16_t RXCLKDLYTG0_U1_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400318 */
18944   __IO uint16_t RXCLKDLYTG1_U1_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40031A */
18945   __IO uint16_t RXCLKDLYTG2_U1_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40031C */
18946   __IO uint16_t RXCLKDLYTG3_U1_P2;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40031E */
18947   __IO uint16_t RXCLKCDLYTG0_U1_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400320 */
18948   __IO uint16_t RXCLKCDLYTG1_U1_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400322 */
18949   __IO uint16_t RXCLKCDLYTG2_U1_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400324 */
18950        uint8_t RESERVED_106[2];
18951   __IO uint16_t RXCLKCDLYTG3_U1_P2;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400328 */
18952        uint8_t RESERVED_107[86];
18953   __IO uint16_t TXDQDLYTG0_R1_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400380 */
18954   __IO uint16_t TXDQDLYTG1_R1_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400382 */
18955   __IO uint16_t TXDQDLYTG2_R1_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400384 */
18956   __IO uint16_t TXDQDLYTG3_R1_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400386 */
18957        uint8_t RESERVED_108[24];
18958   __IO uint16_t TXDQSDLYTG0_U1_P2;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4003A0 */
18959   __IO uint16_t TXDQSDLYTG1_U1_P2;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4003A2 */
18960   __IO uint16_t TXDQSDLYTG2_U1_P2;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4003A4 */
18961   __IO uint16_t TXDQSDLYTG3_U1_P2;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4003A6 */
18962        uint8_t RESERVED_109[472];
18963   __IO uint16_t TXDQDLYTG0_R2_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400580 */
18964   __IO uint16_t TXDQDLYTG1_R2_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400582 */
18965   __IO uint16_t TXDQDLYTG2_R2_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400584 */
18966   __IO uint16_t TXDQDLYTG3_R2_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400586 */
18967        uint8_t RESERVED_110[504];
18968   __IO uint16_t TXDQDLYTG0_R3_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400780 */
18969   __IO uint16_t TXDQDLYTG1_R3_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400782 */
18970   __IO uint16_t TXDQDLYTG2_R3_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400784 */
18971   __IO uint16_t TXDQDLYTG3_R3_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400786 */
18972        uint8_t RESERVED_111[504];
18973   __IO uint16_t TXDQDLYTG0_R4_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400980 */
18974   __IO uint16_t TXDQDLYTG1_R4_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400982 */
18975   __IO uint16_t TXDQDLYTG2_R4_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400984 */
18976   __IO uint16_t TXDQDLYTG3_R4_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400986 */
18977        uint8_t RESERVED_112[504];
18978   __IO uint16_t TXDQDLYTG0_R5_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400B80 */
18979   __IO uint16_t TXDQDLYTG1_R5_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400B82 */
18980   __IO uint16_t TXDQDLYTG2_R5_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400B84 */
18981   __IO uint16_t TXDQDLYTG3_R5_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400B86 */
18982        uint8_t RESERVED_113[504];
18983   __IO uint16_t TXDQDLYTG0_R6_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400D80 */
18984   __IO uint16_t TXDQDLYTG1_R6_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400D82 */
18985   __IO uint16_t TXDQDLYTG2_R6_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400D84 */
18986   __IO uint16_t TXDQDLYTG3_R6_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400D86 */
18987        uint8_t RESERVED_114[504];
18988   __IO uint16_t TXDQDLYTG0_R7_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x400F80 */
18989   __IO uint16_t TXDQDLYTG1_R7_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x400F82 */
18990   __IO uint16_t TXDQDLYTG2_R7_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x400F84 */
18991   __IO uint16_t TXDQDLYTG3_R7_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x400F86 */
18992        uint8_t RESERVED_115[504];
18993   __IO uint16_t TXDQDLYTG0_R8_P2;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x401180 */
18994   __IO uint16_t TXDQDLYTG1_R8_P2;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x401182 */
18995   __IO uint16_t TXDQDLYTG2_R8_P2;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x401184 */
18996   __IO uint16_t TXDQDLYTG3_R8_P2;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x401186 */
18997        uint8_t RESERVED_116[2092728];
18998   __IO uint16_t DFIMRL_P3;                         /**< DFI MaxReadLatency, offset: 0x600040 */
18999        uint8_t RESERVED_117[64];
19000   __IO uint16_t TXIMPEDANCECTRL0_B0_P3;            /**< Data TX impedance controls, offset: 0x600082 */
19001        uint8_t RESERVED_118[2];
19002   __IO uint16_t DQDQSRCVCNTRL_B0_P3;               /**< Dq/Dqs receiver control, offset: 0x600086 */
19003        uint8_t RESERVED_119[8];
19004   __IO uint16_t TXEQUALIZATIONMODE_P3;             /**< Tx dq driver equalization mode controls., offset: 0x600090 */
19005   __IO uint16_t TXIMPEDANCECTRL1_B0_P3;            /**< TX impedance controls, offset: 0x600092 */
19006        uint8_t RESERVED_120[2];
19007   __IO uint16_t TXIMPEDANCECTRL2_B0_P3;            /**< TX equalization impedance controls, offset: 0x600096 */
19008   __IO uint16_t DQDQSRCVCNTRL2_P3;                 /**< Dq/Dqs receiver control, offset: 0x600098 */
19009   __IO uint16_t TXODTDRVSTREN_B0_P3;               /**< TX ODT driver strength control, offset: 0x60009A */
19010        uint8_t RESERVED_121[34];
19011   __IO uint16_t TXSLEWRATE_B0_P3;                  /**< TX slew rate controls, offset: 0x6000BE */
19012        uint8_t RESERVED_122[64];
19013   __IO uint16_t RXENDLYTG0_U0_P3;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600100 */
19014   __IO uint16_t RXENDLYTG1_U0_P3;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600102 */
19015   __IO uint16_t RXENDLYTG2_U0_P3;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600104 */
19016   __IO uint16_t RXENDLYTG3_U0_P3;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600106 */
19017        uint8_t RESERVED_123[16];
19018   __IO uint16_t RXCLKDLYTG0_U0_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600118 */
19019   __IO uint16_t RXCLKDLYTG1_U0_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60011A */
19020   __IO uint16_t RXCLKDLYTG2_U0_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60011C */
19021   __IO uint16_t RXCLKDLYTG3_U0_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60011E */
19022   __IO uint16_t RXCLKCDLYTG0_U0_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600120 */
19023   __IO uint16_t RXCLKCDLYTG1_U0_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600122 */
19024   __IO uint16_t RXCLKCDLYTG2_U0_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600124 */
19025        uint8_t RESERVED_124[2];
19026   __IO uint16_t RXCLKCDLYTG3_U0_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600128 */
19027        uint8_t RESERVED_125[50];
19028   __IO uint16_t PPTDQSCNTINVTRNTG0_P3;             /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015C */
19029   __IO uint16_t PPTDQSCNTINVTRNTG1_P3;             /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015E */
19030        uint8_t RESERVED_126[32];
19031   __IO uint16_t TXDQDLYTG0_R0_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600180 */
19032   __IO uint16_t TXDQDLYTG1_R0_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600182 */
19033   __IO uint16_t TXDQDLYTG2_R0_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600184 */
19034   __IO uint16_t TXDQDLYTG3_R0_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600186 */
19035        uint8_t RESERVED_127[24];
19036   __IO uint16_t TXDQSDLYTG0_U0_P3;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6001A0 */
19037   __IO uint16_t TXDQSDLYTG1_U0_P3;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6001A2 */
19038   __IO uint16_t TXDQSDLYTG2_U0_P3;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6001A4 */
19039   __IO uint16_t TXDQSDLYTG3_U0_P3;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6001A6 */
19040        uint8_t RESERVED_128[218];
19041   __IO uint16_t TXIMPEDANCECTRL0_B1_P3;            /**< Data TX impedance controls, offset: 0x600282 */
19042        uint8_t RESERVED_129[2];
19043   __IO uint16_t DQDQSRCVCNTRL_B1_P3;               /**< Dq/Dqs receiver control, offset: 0x600286 */
19044        uint8_t RESERVED_130[10];
19045   __IO uint16_t TXIMPEDANCECTRL1_B1_P3;            /**< TX impedance controls, offset: 0x600292 */
19046        uint8_t RESERVED_131[2];
19047   __IO uint16_t TXIMPEDANCECTRL2_B1_P3;            /**< TX equalization impedance controls, offset: 0x600296 */
19048        uint8_t RESERVED_132[2];
19049   __IO uint16_t TXODTDRVSTREN_B1_P3;               /**< TX ODT driver strength control, offset: 0x60029A */
19050        uint8_t RESERVED_133[34];
19051   __IO uint16_t TXSLEWRATE_B1_P3;                  /**< TX slew rate controls, offset: 0x6002BE */
19052        uint8_t RESERVED_134[64];
19053   __IO uint16_t RXENDLYTG0_U1_P3;                  /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600300 */
19054   __IO uint16_t RXENDLYTG1_U1_P3;                  /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600302 */
19055   __IO uint16_t RXENDLYTG2_U1_P3;                  /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600304 */
19056   __IO uint16_t RXENDLYTG3_U1_P3;                  /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600306 */
19057        uint8_t RESERVED_135[16];
19058   __IO uint16_t RXCLKDLYTG0_U1_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600318 */
19059   __IO uint16_t RXCLKDLYTG1_U1_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60031A */
19060   __IO uint16_t RXCLKDLYTG2_U1_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60031C */
19061   __IO uint16_t RXCLKDLYTG3_U1_P3;                 /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60031E */
19062   __IO uint16_t RXCLKCDLYTG0_U1_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600320 */
19063   __IO uint16_t RXCLKCDLYTG1_U1_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600322 */
19064   __IO uint16_t RXCLKCDLYTG2_U1_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600324 */
19065        uint8_t RESERVED_136[2];
19066   __IO uint16_t RXCLKCDLYTG3_U1_P3;                /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600328 */
19067        uint8_t RESERVED_137[86];
19068   __IO uint16_t TXDQDLYTG0_R1_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600380 */
19069   __IO uint16_t TXDQDLYTG1_R1_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600382 */
19070   __IO uint16_t TXDQDLYTG2_R1_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600384 */
19071   __IO uint16_t TXDQDLYTG3_R1_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600386 */
19072        uint8_t RESERVED_138[24];
19073   __IO uint16_t TXDQSDLYTG0_U1_P3;                 /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6003A0 */
19074   __IO uint16_t TXDQSDLYTG1_U1_P3;                 /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6003A2 */
19075   __IO uint16_t TXDQSDLYTG2_U1_P3;                 /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6003A4 */
19076   __IO uint16_t TXDQSDLYTG3_U1_P3;                 /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6003A6 */
19077        uint8_t RESERVED_139[472];
19078   __IO uint16_t TXDQDLYTG0_R2_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600580 */
19079   __IO uint16_t TXDQDLYTG1_R2_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600582 */
19080   __IO uint16_t TXDQDLYTG2_R2_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600584 */
19081   __IO uint16_t TXDQDLYTG3_R2_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600586 */
19082        uint8_t RESERVED_140[504];
19083   __IO uint16_t TXDQDLYTG0_R3_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600780 */
19084   __IO uint16_t TXDQDLYTG1_R3_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600782 */
19085   __IO uint16_t TXDQDLYTG2_R3_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600784 */
19086   __IO uint16_t TXDQDLYTG3_R3_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600786 */
19087        uint8_t RESERVED_141[504];
19088   __IO uint16_t TXDQDLYTG0_R4_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600980 */
19089   __IO uint16_t TXDQDLYTG1_R4_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600982 */
19090   __IO uint16_t TXDQDLYTG2_R4_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600984 */
19091   __IO uint16_t TXDQDLYTG3_R4_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600986 */
19092        uint8_t RESERVED_142[504];
19093   __IO uint16_t TXDQDLYTG0_R5_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600B80 */
19094   __IO uint16_t TXDQDLYTG1_R5_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600B82 */
19095   __IO uint16_t TXDQDLYTG2_R5_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600B84 */
19096   __IO uint16_t TXDQDLYTG3_R5_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600B86 */
19097        uint8_t RESERVED_143[504];
19098   __IO uint16_t TXDQDLYTG0_R6_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600D80 */
19099   __IO uint16_t TXDQDLYTG1_R6_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600D82 */
19100   __IO uint16_t TXDQDLYTG2_R6_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600D84 */
19101   __IO uint16_t TXDQDLYTG3_R6_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600D86 */
19102        uint8_t RESERVED_144[504];
19103   __IO uint16_t TXDQDLYTG0_R7_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x600F80 */
19104   __IO uint16_t TXDQDLYTG1_R7_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x600F82 */
19105   __IO uint16_t TXDQDLYTG2_R7_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x600F84 */
19106   __IO uint16_t TXDQDLYTG3_R7_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x600F86 */
19107        uint8_t RESERVED_145[504];
19108   __IO uint16_t TXDQDLYTG0_R8_P3;                  /**< Write DQ Delay (Timing Group 0)., offset: 0x601180 */
19109   __IO uint16_t TXDQDLYTG1_R8_P3;                  /**< Write DQ Delay (Timing Group 1)., offset: 0x601182 */
19110   __IO uint16_t TXDQDLYTG2_R8_P3;                  /**< Write DQ Delay (Timing Group 2)., offset: 0x601184 */
19111   __IO uint16_t TXDQDLYTG3_R8_P3;                  /**< Write DQ Delay (Timing Group 3)., offset: 0x601186 */
19112 } DWC_DDRPHYA_DBYTE_Type;
19113 
19114 /* ----------------------------------------------------------------------------
19115    -- DWC_DDRPHYA_DBYTE Register Masks
19116    ---------------------------------------------------------------------------- */
19117 
19118 /*!
19119  * @addtogroup DWC_DDRPHYA_DBYTE_Register_Masks DWC_DDRPHYA_DBYTE Register Masks
19120  * @{
19121  */
19122 
19123 /*! @name DBYTEMISCMODE - DBYTE Module Disable */
19124 /*! @{ */
19125 
19126 #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_MASK (0x4U)
19127 #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_SHIFT (2U)
19128 /*! DByteDisable - Controls whether this DBYTE module is disabled. */
19129 #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_SHIFT)) & DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_MASK)
19130 /*! @} */
19131 
19132 /*! @name MTESTMUXSEL - Digital Observation Pin control */
19133 /*! @{ */
19134 
19135 #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_MASK (0x3FU)
19136 #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_SHIFT (0U)
19137 /*! MtestMuxSel - Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin. */
19138 #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_SHIFT)) & DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_MASK)
19139 /*! @} */
19140 
19141 /*! @name DFIMRL_P0 - DFI MaxReadLatency */
19142 /*! @{ */
19143 
19144 #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_MASK (0x1FU)
19145 #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_SHIFT (0U)
19146 /*! DFIMRL_p0 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
19147  *    until after all dbytes have their read data valid.
19148  */
19149 #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_MASK)
19150 /*! @} */
19151 
19152 /*! @name VREFDAC1_R0 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
19153 /*! @{ */
19154 
19155 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_MASK (0x7FU)
19156 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_SHIFT (0U)
19157 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
19158  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
19159  *    have different ranges, depending on the Mission Mode settings for
19160  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
19161  */
19162 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_MASK)
19163 /*! @} */
19164 
19165 /*! @name VREFDAC0_R0 - VrefDAC0 control for DQ Receiver */
19166 /*! @{ */
19167 
19168 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_MASK (0x7FU)
19169 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_SHIFT (0U)
19170 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
19171  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
19172  *    VREF generators have different ranges, depending on the Mission Mode settings for
19173  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
19174  */
19175 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_MASK)
19176 /*! @} */
19177 
19178 /*! @name TXIMPEDANCECTRL0_B0_P0 - Data TX impedance controls */
19179 /*! @{ */
19180 
19181 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_MASK (0x3FU)
19182 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_SHIFT (0U)
19183 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19184  *    used to select the target pull down output impedance.
19185  */
19186 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_MASK)
19187 
19188 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_MASK (0xFC0U)
19189 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_SHIFT (6U)
19190 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19191  *    used to select the target pull down output impedance.
19192  */
19193 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_MASK)
19194 /*! @} */
19195 
19196 /*! @name DQDQSRCVCNTRL_B0_P0 - Dq/Dqs receiver control */
19197 /*! @{ */
19198 
19199 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_MASK (0x1U)
19200 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_SHIFT (0U)
19201 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
19202 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_MASK)
19203 
19204 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_MASK (0x2U)
19205 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_SHIFT (1U)
19206 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
19207 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_MASK)
19208 
19209 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_MASK (0xCU)
19210 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_SHIFT (2U)
19211 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
19212  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
19213  *    should not be overridden.
19214  */
19215 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_MASK)
19216 
19217 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_MASK (0x70U)
19218 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_SHIFT (4U)
19219 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
19220 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_MASK)
19221 
19222 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_MASK (0xF80U)
19223 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_SHIFT (7U)
19224 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
19225 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_MASK)
19226 /*! @} */
19227 
19228 /*! @name TXEQUALIZATIONMODE_P0 - Tx dq driver equalization mode controls. */
19229 /*! @{ */
19230 
19231 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_MASK (0x3U)
19232 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_SHIFT (0U)
19233 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_MASK)
19234 /*! @} */
19235 
19236 /*! @name TXIMPEDANCECTRL1_B0_P0 - TX impedance controls */
19237 /*! @{ */
19238 
19239 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_MASK (0x3FU)
19240 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_SHIFT (0U)
19241 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19242  *    used to select the target pull up output impedance used in equalization.
19243  */
19244 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_MASK)
19245 
19246 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_MASK (0xFC0U)
19247 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_SHIFT (6U)
19248 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19249  *    used to select the target pull up output impedance used in equalization.
19250  */
19251 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_MASK)
19252 /*! @} */
19253 
19254 /*! @name DQDQSRCVCNTRL1 - Dq/Dqs receiver control */
19255 /*! @{ */
19256 
19257 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_MASK (0x1FFU)
19258 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_SHIFT (0U)
19259 /*! PowerDownRcvr - Active high signal which powers down the receiver. */
19260 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_MASK)
19261 
19262 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_MASK (0x200U)
19263 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_SHIFT (9U)
19264 /*! PowerDownRcvrDqs - Active high signal which powers down the receiver. */
19265 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_MASK)
19266 
19267 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_MASK (0x400U)
19268 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_SHIFT (10U)
19269 /*! RxPadStandbyEn - Enables the rxdq/rxdqs StandBy power savings, per pad-group. */
19270 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_MASK)
19271 
19272 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_MASK (0x800U)
19273 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_SHIFT (11U)
19274 /*! EnLPReqPDR - Reserved for future use */
19275 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_MASK)
19276 /*! @} */
19277 
19278 /*! @name TXIMPEDANCECTRL2_B0_P0 - TX equalization impedance controls */
19279 /*! @{ */
19280 
19281 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_MASK (0x3FU)
19282 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_SHIFT (0U)
19283 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
19284  *    bus used to select the target pull up output impedance used in equalization.
19285  */
19286 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_MASK)
19287 
19288 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_MASK (0xFC0U)
19289 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_SHIFT (6U)
19290 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
19291  *    bus used to select the target pull down output impedance used in equalization.
19292  */
19293 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_MASK)
19294 /*! @} */
19295 
19296 /*! @name DQDQSRCVCNTRL2_P0 - Dq/Dqs receiver control */
19297 /*! @{ */
19298 
19299 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_MASK (0x1U)
19300 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_SHIFT (0U)
19301 /*! EnRxAgressivePDR - reserved */
19302 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_MASK)
19303 /*! @} */
19304 
19305 /*! @name TXODTDRVSTREN_B0_P0 - TX ODT driver strength control */
19306 /*! @{ */
19307 
19308 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_MASK (0x3FU)
19309 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_SHIFT (0U)
19310 /*! ODTStrenP - Selects the ODT pull-up impedance. */
19311 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_MASK)
19312 
19313 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_MASK (0xFC0U)
19314 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_SHIFT (6U)
19315 /*! ODTStrenN - Selects the ODT pull-down impedance. */
19316 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_MASK)
19317 /*! @} */
19318 
19319 /*! @name RXFIFOCHECKSTATUS - Status of RX FIFO Consistency Checks */
19320 /*! @{ */
19321 
19322 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_MASK (0x1U)
19323 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_SHIFT (0U)
19324 /*! RxFifoRdLocErr - If set, the read pointer (DFI side) on the read FIFO associated with data bits [3:0] had a non-zero value at least once. */
19325 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_MASK)
19326 
19327 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_MASK (0x2U)
19328 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_SHIFT (1U)
19329 /*! RxFifoWrLocErr - If set, the write pointer (DQS side) on the read FIFO associated with data bits
19330  *    [3:0] has a non-zero value at least once.
19331  */
19332 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_MASK)
19333 
19334 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_MASK (0x4U)
19335 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_SHIFT (2U)
19336 /*! RxFifoRdLocUErr - If set, the read pointer (DFI side) on the read FIFO associated with data bits [7:4] has a non-zero value at least once. */
19337 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_MASK)
19338 
19339 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_MASK (0x8U)
19340 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_SHIFT (3U)
19341 /*! RxFifoWrLocUErr - If set, the write pointer (DQS side) on the read FIFO associated with data
19342  *    bits [7:4] has a non-zero value at least once.
19343  */
19344 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_MASK)
19345 /*! @} */
19346 
19347 /*! @name RXFIFOCHECKERRVALUES - Contains the captured values associated with an RxFifo consistency error */
19348 /*! @{ */
19349 
19350 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_MASK (0xFU)
19351 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_SHIFT (0U)
19352 /*! RxFifoRdLocErrValue - The first error value captured for the read pointer (DFI side) on the read FIFO associated with data bits [3:0]; */
19353 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_MASK)
19354 
19355 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_MASK (0xF0U)
19356 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_SHIFT (4U)
19357 /*! RxFifoWrLocErrValue - The first error value captured for the write pointer (DQS side) on the read FIFO associated with data bits [3:0]; */
19358 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_MASK)
19359 
19360 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_MASK (0xF00U)
19361 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_SHIFT (8U)
19362 /*! RxFifoRdLocUErrValue - The first error value captured for the read pointer (DFI side) on the read FIFO associated with data bits [7:4]; */
19363 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_MASK)
19364 
19365 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_MASK (0xF000U)
19366 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_SHIFT (12U)
19367 /*! RxFifoWrLocUErrValue - The first error value captured for the write pointer (DQS side) on the read FIFO associated with data bits [7:4]; */
19368 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_MASK)
19369 /*! @} */
19370 
19371 /*! @name RXFIFOINFO - Data Receive FIFO Pointer Values */
19372 /*! @{ */
19373 
19374 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_MASK (0xFU)
19375 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_SHIFT (0U)
19376 /*! RxFifoRdLoc - The Mission mode read pointer of the lower-nibble Rx fifo. */
19377 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_MASK)
19378 
19379 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_MASK (0xF0U)
19380 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_SHIFT (4U)
19381 /*! RxFifoWrLoc - The Mission mode write pointer of the lower-nibble Rx fifo. */
19382 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_MASK)
19383 
19384 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_MASK (0xF00U)
19385 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_SHIFT (8U)
19386 /*! RxFifoRdLocU - The Mission mode read pointer of the upper-nibble Rx fifo. */
19387 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_MASK)
19388 
19389 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_MASK (0xF000U)
19390 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_SHIFT (12U)
19391 /*! RxFifoWrLocU - The Mission mode write pointer of the upper-nibble Rx fifo. */
19392 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_MASK)
19393 /*! @} */
19394 
19395 /*! @name RXFIFOVISIBILITY - RX FIFO visibility */
19396 /*! @{ */
19397 
19398 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_MASK (0x7U)
19399 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_SHIFT (0U)
19400 /*! RxFifoRdPtr - If CSR RxFifoRdPtrOVr is set, then this CSR selects the rxfifo entry is visible in
19401  *    CSR This 3b field addresses 4b units of the 8x4b (32entry) fifo; that is,
19402  *    rdfifo_nibble_address[2:0]=csrRxFifoRdPtr[2:0] For example, Register RxFifoRdPtr[2:0]=2 will enable reading
19403  *    bit-entries 11.
19404  */
19405 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_MASK)
19406 
19407 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_MASK (0x8U)
19408 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_SHIFT (3U)
19409 /*! RxFifoRdPtrOvr - 0 : Normal operation - mission mode read pointer is enabled 1 : Override -
19410  *    Control of the rx fifo read pointer is ceded to CSR RxFifoRdPtr.
19411  */
19412 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_MASK)
19413 
19414 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_MASK (0x10U)
19415 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_SHIFT (4U)
19416 /*! RxFifoRdEn - Pulse set 0-->1-->0 this bit to capture the Fifo Contents. */
19417 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_MASK)
19418 /*! @} */
19419 
19420 /*! @name RXFIFOCONTENTSDQ3210 - RX FIFO contents, lane[3:0] */
19421 /*! @{ */
19422 
19423 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_MASK (0xFFFFU)
19424 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_SHIFT (0U)
19425 /*! RxFifoContentsDQ3210 - A window into the contents of the RxFifo, as controlled by CSR
19426  *    RxFifoVisibility This register reads 4b at a time from lane0.
19427  */
19428 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_MASK)
19429 /*! @} */
19430 
19431 /*! @name RXFIFOCONTENTSDQ7654 - RX FIFO contents, lane[7:4] */
19432 /*! @{ */
19433 
19434 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_MASK (0xFFFFU)
19435 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_SHIFT (0U)
19436 /*! RxFifoContentsDQ7654 - A window into the contents of the RxFifo, as controlled by CSR
19437  *    RxFifoVisibility This register reads 4b at a time from lane4.
19438  */
19439 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_MASK)
19440 /*! @} */
19441 
19442 /*! @name RXFIFOCONTENTSDBI - RX FIFO contents, dbi */
19443 /*! @{ */
19444 
19445 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_MASK (0xFU)
19446 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_SHIFT (0U)
19447 /*! RxFifoContentsDBI - A window into the contents of the RxFifo, as controlled by CSR
19448  *    RxFifoVisibility This register reads 4b at a time from DBI from the four fifo entries addressed by
19449  *    rdfifo_nibble_address[2:0]=RxFifoRdPtr[2:0] Register [ 3: 0] = dbi_ui3,dbi_ui2,dbi_ui1,dbi_ui0 Note
19450  *    that the DBYTE DBI lane is the same as the memory DBI; it is not subject to mapping using csr
19451  *    Dq<7.
19452  */
19453 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_MASK)
19454 /*! @} */
19455 
19456 /*! @name TXSLEWRATE_B0_P0 - TX slew rate controls */
19457 /*! @{ */
19458 
19459 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_MASK (0xFU)
19460 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_SHIFT (0U)
19461 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
19462 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_MASK)
19463 
19464 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_MASK (0xF0U)
19465 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_SHIFT (4U)
19466 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
19467 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_MASK)
19468 
19469 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_MASK (0x700U)
19470 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_SHIFT (8U)
19471 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
19472 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_MASK)
19473 /*! @} */
19474 
19475 /*! @name RXPBDLYTG0_R0 - Read DQ per-bit BDL delay (Timing Group 0). */
19476 /*! @{ */
19477 
19478 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_MASK (0x7FU)
19479 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_SHIFT (0U)
19480 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
19481 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_MASK)
19482 /*! @} */
19483 
19484 /*! @name RXPBDLYTG1_R0 - Read DQ per-bit BDL delay (Timing Group 1). */
19485 /*! @{ */
19486 
19487 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_MASK (0x7FU)
19488 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_SHIFT (0U)
19489 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
19490 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_MASK)
19491 /*! @} */
19492 
19493 /*! @name RXPBDLYTG2_R0 - Read DQ per-bit BDL delay (Timing Group 2). */
19494 /*! @{ */
19495 
19496 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_MASK (0x7FU)
19497 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_SHIFT (0U)
19498 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
19499 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_MASK)
19500 /*! @} */
19501 
19502 /*! @name RXPBDLYTG3_R0 - Read DQ per-bit BDL delay (Timing Group 3). */
19503 /*! @{ */
19504 
19505 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_MASK (0x7FU)
19506 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_SHIFT (0U)
19507 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
19508 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_MASK)
19509 /*! @} */
19510 
19511 /*! @name RXENDLYTG0_U0_P0 - Trained Receive Enable Delay (For Timing Group 0) */
19512 /*! @{ */
19513 
19514 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_MASK (0x7FFU)
19515 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_SHIFT (0U)
19516 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
19517  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19518  */
19519 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_MASK)
19520 /*! @} */
19521 
19522 /*! @name RXENDLYTG1_U0_P0 - Trained Receive Enable Delay (For Timing Group 1) */
19523 /*! @{ */
19524 
19525 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_MASK (0x7FFU)
19526 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_SHIFT (0U)
19527 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
19528  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19529  */
19530 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_MASK)
19531 /*! @} */
19532 
19533 /*! @name RXENDLYTG2_U0_P0 - Trained Receive Enable Delay (For Timing Group 2) */
19534 /*! @{ */
19535 
19536 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_MASK (0x7FFU)
19537 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_SHIFT (0U)
19538 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
19539  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19540  */
19541 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_MASK)
19542 /*! @} */
19543 
19544 /*! @name RXENDLYTG3_U0_P0 - Trained Receive Enable Delay (For Timing Group 3) */
19545 /*! @{ */
19546 
19547 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_MASK (0x7FFU)
19548 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_SHIFT (0U)
19549 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
19550  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19551  */
19552 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_MASK)
19553 /*! @} */
19554 
19555 /*! @name RXCLKDLYTG0_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
19556 /*! @{ */
19557 
19558 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
19559 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_SHIFT (0U)
19560 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
19561 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_MASK)
19562 /*! @} */
19563 
19564 /*! @name RXCLKDLYTG1_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
19565 /*! @{ */
19566 
19567 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
19568 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_SHIFT (0U)
19569 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
19570 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_MASK)
19571 /*! @} */
19572 
19573 /*! @name RXCLKDLYTG2_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
19574 /*! @{ */
19575 
19576 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
19577 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_SHIFT (0U)
19578 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
19579 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_MASK)
19580 /*! @} */
19581 
19582 /*! @name RXCLKDLYTG3_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
19583 /*! @{ */
19584 
19585 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
19586 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_SHIFT (0U)
19587 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
19588 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_MASK)
19589 /*! @} */
19590 
19591 /*! @name RXCLKCDLYTG0_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
19592 /*! @{ */
19593 
19594 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
19595 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
19596 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
19597 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_MASK)
19598 /*! @} */
19599 
19600 /*! @name RXCLKCDLYTG1_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
19601 /*! @{ */
19602 
19603 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
19604 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
19605 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
19606 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_MASK)
19607 /*! @} */
19608 
19609 /*! @name RXCLKCDLYTG2_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
19610 /*! @{ */
19611 
19612 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
19613 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
19614 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
19615 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_MASK)
19616 /*! @} */
19617 
19618 /*! @name RXCLKCDLYTG3_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
19619 /*! @{ */
19620 
19621 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
19622 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
19623 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
19624 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_MASK)
19625 /*! @} */
19626 
19627 /*! @name DQLNSEL - Maps Phy DQ lane to memory DQ0 */
19628 /*! @{ */
19629 
19630 #define DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_MASK   (0x7U)
19631 #define DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_SHIFT  (0U)
19632 /*! DqLnSel - Supports mapping of PHY dq to dram dq within a byte (swizzle). */
19633 #define DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL(x)     (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_MASK)
19634 /*! @} */
19635 
19636 /* The count of DWC_DDRPHYA_DBYTE_DQLNSEL */
19637 #define DWC_DDRPHYA_DBYTE_DQLNSEL_COUNT          (8U)
19638 
19639 /*! @name TXDQDLYTG0_R0_P0 - Write DQ Delay (Timing Group 0). */
19640 /*! @{ */
19641 
19642 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
19643 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
19644 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
19645 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_MASK)
19646 /*! @} */
19647 
19648 /*! @name TXDQDLYTG1_R0_P0 - Write DQ Delay (Timing Group 1). */
19649 /*! @{ */
19650 
19651 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
19652 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
19653 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
19654 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_MASK)
19655 /*! @} */
19656 
19657 /*! @name TXDQDLYTG2_R0_P0 - Write DQ Delay (Timing Group 2). */
19658 /*! @{ */
19659 
19660 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
19661 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
19662 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
19663 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_MASK)
19664 /*! @} */
19665 
19666 /*! @name TXDQDLYTG3_R0_P0 - Write DQ Delay (Timing Group 3). */
19667 /*! @{ */
19668 
19669 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
19670 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
19671 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
19672 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_MASK)
19673 /*! @} */
19674 
19675 /*! @name TXDQSDLYTG0_U0_P0 - Write DQS Delay (Timing Group DEST=0). */
19676 /*! @{ */
19677 
19678 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
19679 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_SHIFT (0U)
19680 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
19681 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_MASK)
19682 /*! @} */
19683 
19684 /*! @name TXDQSDLYTG1_U0_P0 - Write DQS Delay (Timing Group DEST=1). */
19685 /*! @{ */
19686 
19687 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
19688 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_SHIFT (0U)
19689 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
19690 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_MASK)
19691 /*! @} */
19692 
19693 /*! @name TXDQSDLYTG2_U0_P0 - Write DQS Delay (Timing Group DEST=2). */
19694 /*! @{ */
19695 
19696 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
19697 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_SHIFT (0U)
19698 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
19699 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_MASK)
19700 /*! @} */
19701 
19702 /*! @name TXDQSDLYTG3_U0_P0 - Write DQS Delay (Timing Group DEST=3). */
19703 /*! @{ */
19704 
19705 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
19706 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_SHIFT (0U)
19707 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
19708 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_MASK)
19709 /*! @} */
19710 
19711 /*! @name DXLCDLSTATUS - Debug status of the DBYTE LCDL */
19712 /*! @{ */
19713 
19714 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_MASK (0x3FFU)
19715 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_SHIFT (0U)
19716 /*! DxLcdlFineSnapVal - Value of the LCDL 1UI estimate code, latched by pulse on csr LcdlFineSnap while csr LcdlTstEnable=1. */
19717 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_MASK)
19718 
19719 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_MASK (0x400U)
19720 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_SHIFT (10U)
19721 /*! DxLcdlPhdSnapVal - Value of the LCDL phase-detector output, latched by pulse on csr LcdlFineSnap. */
19722 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_MASK)
19723 
19724 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_MASK (0x800U)
19725 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_SHIFT (11U)
19726 /*! DxLcdlStickyLock - latched value of whether the LCDL ever achieved lock after the assertion of LcdlTstEnable. */
19727 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_MASK)
19728 
19729 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_MASK (0x1000U)
19730 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_SHIFT (12U)
19731 /*! DxLcdlStickyUnlock - latched value of whether the LCDL ever lost lock after the assertion of LcdlTstEnable. */
19732 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_MASK)
19733 
19734 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_MASK (0x2000U)
19735 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_SHIFT (13U)
19736 /*! DxLcdlLiveLock - present value of whether the LCDL is locked, valid when LcdlTstEnable=1. */
19737 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_MASK)
19738 /*! @} */
19739 
19740 /*! @name VREFDAC1_R1 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
19741 /*! @{ */
19742 
19743 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_MASK (0x7FU)
19744 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_SHIFT (0U)
19745 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
19746  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
19747  *    have different ranges, depending on the Mission Mode settings for
19748  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
19749  */
19750 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_MASK)
19751 /*! @} */
19752 
19753 /*! @name VREFDAC0_R1 - VrefDAC0 control for DQ Receiver */
19754 /*! @{ */
19755 
19756 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_MASK (0x7FU)
19757 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_SHIFT (0U)
19758 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
19759  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
19760  *    VREF generators have different ranges, depending on the Mission Mode settings for
19761  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
19762  */
19763 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_MASK)
19764 /*! @} */
19765 
19766 /*! @name TXIMPEDANCECTRL0_B1_P0 - Data TX impedance controls */
19767 /*! @{ */
19768 
19769 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_MASK (0x3FU)
19770 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_SHIFT (0U)
19771 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19772  *    used to select the target pull down output impedance.
19773  */
19774 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_MASK)
19775 
19776 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_MASK (0xFC0U)
19777 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_SHIFT (6U)
19778 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19779  *    used to select the target pull down output impedance.
19780  */
19781 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_MASK)
19782 /*! @} */
19783 
19784 /*! @name DQDQSRCVCNTRL_B1_P0 - Dq/Dqs receiver control */
19785 /*! @{ */
19786 
19787 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_MASK (0x1U)
19788 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_SHIFT (0U)
19789 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
19790 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_MASK)
19791 
19792 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_MASK (0x2U)
19793 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_SHIFT (1U)
19794 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
19795 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_MASK)
19796 
19797 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_MASK (0xCU)
19798 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_SHIFT (2U)
19799 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
19800  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
19801  *    should not be overridden.
19802  */
19803 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_MASK)
19804 
19805 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_MASK (0x70U)
19806 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_SHIFT (4U)
19807 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
19808 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_MASK)
19809 
19810 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_MASK (0xF80U)
19811 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_SHIFT (7U)
19812 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
19813 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_MASK)
19814 /*! @} */
19815 
19816 /*! @name TXIMPEDANCECTRL1_B1_P0 - TX impedance controls */
19817 /*! @{ */
19818 
19819 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_MASK (0x3FU)
19820 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_SHIFT (0U)
19821 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19822  *    used to select the target pull up output impedance used in equalization.
19823  */
19824 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_MASK)
19825 
19826 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_MASK (0xFC0U)
19827 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_SHIFT (6U)
19828 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
19829  *    used to select the target pull up output impedance used in equalization.
19830  */
19831 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_MASK)
19832 /*! @} */
19833 
19834 /*! @name TXIMPEDANCECTRL2_B1_P0 - TX equalization impedance controls */
19835 /*! @{ */
19836 
19837 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_MASK (0x3FU)
19838 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_SHIFT (0U)
19839 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
19840  *    bus used to select the target pull up output impedance used in equalization.
19841  */
19842 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_MASK)
19843 
19844 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_MASK (0xFC0U)
19845 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_SHIFT (6U)
19846 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
19847  *    bus used to select the target pull down output impedance used in equalization.
19848  */
19849 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_MASK)
19850 /*! @} */
19851 
19852 /*! @name TXODTDRVSTREN_B1_P0 - TX ODT driver strength control */
19853 /*! @{ */
19854 
19855 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_MASK (0x3FU)
19856 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_SHIFT (0U)
19857 /*! ODTStrenP - Selects the ODT pull-up impedance. */
19858 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_MASK)
19859 
19860 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_MASK (0xFC0U)
19861 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_SHIFT (6U)
19862 /*! ODTStrenN - Selects the ODT pull-down impedance. */
19863 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_MASK)
19864 /*! @} */
19865 
19866 /*! @name TXSLEWRATE_B1_P0 - TX slew rate controls */
19867 /*! @{ */
19868 
19869 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_MASK (0xFU)
19870 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_SHIFT (0U)
19871 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
19872 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_MASK)
19873 
19874 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_MASK (0xF0U)
19875 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_SHIFT (4U)
19876 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
19877 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_MASK)
19878 
19879 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_MASK (0x700U)
19880 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_SHIFT (8U)
19881 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
19882 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_MASK)
19883 /*! @} */
19884 
19885 /*! @name RXPBDLYTG0_R1 - Read DQ per-bit BDL delay (Timing Group 0). */
19886 /*! @{ */
19887 
19888 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_MASK (0x7FU)
19889 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_SHIFT (0U)
19890 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
19891 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_MASK)
19892 /*! @} */
19893 
19894 /*! @name RXPBDLYTG1_R1 - Read DQ per-bit BDL delay (Timing Group 1). */
19895 /*! @{ */
19896 
19897 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_MASK (0x7FU)
19898 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_SHIFT (0U)
19899 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
19900 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_MASK)
19901 /*! @} */
19902 
19903 /*! @name RXPBDLYTG2_R1 - Read DQ per-bit BDL delay (Timing Group 2). */
19904 /*! @{ */
19905 
19906 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_MASK (0x7FU)
19907 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_SHIFT (0U)
19908 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
19909 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_MASK)
19910 /*! @} */
19911 
19912 /*! @name RXPBDLYTG3_R1 - Read DQ per-bit BDL delay (Timing Group 3). */
19913 /*! @{ */
19914 
19915 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_MASK (0x7FU)
19916 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_SHIFT (0U)
19917 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
19918 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_MASK)
19919 /*! @} */
19920 
19921 /*! @name RXENDLYTG0_U1_P0 - Trained Receive Enable Delay (For Timing Group 0) */
19922 /*! @{ */
19923 
19924 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_MASK (0x7FFU)
19925 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_SHIFT (0U)
19926 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
19927  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19928  */
19929 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_MASK)
19930 /*! @} */
19931 
19932 /*! @name RXENDLYTG1_U1_P0 - Trained Receive Enable Delay (For Timing Group 1) */
19933 /*! @{ */
19934 
19935 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_MASK (0x7FFU)
19936 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_SHIFT (0U)
19937 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
19938  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19939  */
19940 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_MASK)
19941 /*! @} */
19942 
19943 /*! @name RXENDLYTG2_U1_P0 - Trained Receive Enable Delay (For Timing Group 2) */
19944 /*! @{ */
19945 
19946 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_MASK (0x7FFU)
19947 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_SHIFT (0U)
19948 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
19949  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19950  */
19951 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_MASK)
19952 /*! @} */
19953 
19954 /*! @name RXENDLYTG3_U1_P0 - Trained Receive Enable Delay (For Timing Group 3) */
19955 /*! @{ */
19956 
19957 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_MASK (0x7FFU)
19958 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_SHIFT (0U)
19959 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
19960  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
19961  */
19962 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_MASK)
19963 /*! @} */
19964 
19965 /*! @name RXCLKDLYTG0_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
19966 /*! @{ */
19967 
19968 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
19969 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_SHIFT (0U)
19970 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
19971 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_MASK)
19972 /*! @} */
19973 
19974 /*! @name RXCLKDLYTG1_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
19975 /*! @{ */
19976 
19977 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
19978 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_SHIFT (0U)
19979 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
19980 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_MASK)
19981 /*! @} */
19982 
19983 /*! @name RXCLKDLYTG2_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
19984 /*! @{ */
19985 
19986 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
19987 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_SHIFT (0U)
19988 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
19989 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_MASK)
19990 /*! @} */
19991 
19992 /*! @name RXCLKDLYTG3_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
19993 /*! @{ */
19994 
19995 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
19996 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_SHIFT (0U)
19997 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
19998 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_MASK)
19999 /*! @} */
20000 
20001 /*! @name RXCLKCDLYTG0_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
20002 /*! @{ */
20003 
20004 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
20005 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
20006 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
20007 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_MASK)
20008 /*! @} */
20009 
20010 /*! @name RXCLKCDLYTG1_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
20011 /*! @{ */
20012 
20013 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
20014 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
20015 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
20016 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_MASK)
20017 /*! @} */
20018 
20019 /*! @name RXCLKCDLYTG2_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
20020 /*! @{ */
20021 
20022 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
20023 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
20024 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
20025 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_MASK)
20026 /*! @} */
20027 
20028 /*! @name RXCLKCDLYTG3_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
20029 /*! @{ */
20030 
20031 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
20032 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
20033 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
20034 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_MASK)
20035 /*! @} */
20036 
20037 /*! @name TXDQDLYTG0_R1_P0 - Write DQ Delay (Timing Group 0). */
20038 /*! @{ */
20039 
20040 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20041 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20042 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20043 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_MASK)
20044 /*! @} */
20045 
20046 /*! @name TXDQDLYTG1_R1_P0 - Write DQ Delay (Timing Group 1). */
20047 /*! @{ */
20048 
20049 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20050 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20051 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20052 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_MASK)
20053 /*! @} */
20054 
20055 /*! @name TXDQDLYTG2_R1_P0 - Write DQ Delay (Timing Group 2). */
20056 /*! @{ */
20057 
20058 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20059 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20060 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20061 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_MASK)
20062 /*! @} */
20063 
20064 /*! @name TXDQDLYTG3_R1_P0 - Write DQ Delay (Timing Group 3). */
20065 /*! @{ */
20066 
20067 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20068 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20069 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20070 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_MASK)
20071 /*! @} */
20072 
20073 /*! @name TXDQSDLYTG0_U1_P0 - Write DQS Delay (Timing Group DEST=0). */
20074 /*! @{ */
20075 
20076 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
20077 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_SHIFT (0U)
20078 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
20079 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_MASK)
20080 /*! @} */
20081 
20082 /*! @name TXDQSDLYTG1_U1_P0 - Write DQS Delay (Timing Group DEST=1). */
20083 /*! @{ */
20084 
20085 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
20086 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_SHIFT (0U)
20087 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
20088 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_MASK)
20089 /*! @} */
20090 
20091 /*! @name TXDQSDLYTG2_U1_P0 - Write DQS Delay (Timing Group DEST=2). */
20092 /*! @{ */
20093 
20094 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
20095 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_SHIFT (0U)
20096 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
20097 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_MASK)
20098 /*! @} */
20099 
20100 /*! @name TXDQSDLYTG3_U1_P0 - Write DQS Delay (Timing Group DEST=3). */
20101 /*! @{ */
20102 
20103 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
20104 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_SHIFT (0U)
20105 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
20106 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_MASK)
20107 /*! @} */
20108 
20109 /*! @name VREFDAC1_R2 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20110 /*! @{ */
20111 
20112 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_MASK (0x7FU)
20113 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_SHIFT (0U)
20114 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20115  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20116  *    have different ranges, depending on the Mission Mode settings for
20117  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20118  */
20119 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_MASK)
20120 /*! @} */
20121 
20122 /*! @name VREFDAC0_R2 - VrefDAC0 control for DQ Receiver */
20123 /*! @{ */
20124 
20125 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_MASK (0x7FU)
20126 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_SHIFT (0U)
20127 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20128  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20129  *    VREF generators have different ranges, depending on the Mission Mode settings for
20130  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20131  */
20132 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_MASK)
20133 /*! @} */
20134 
20135 /*! @name RXPBDLYTG0_R2 - Read DQ per-bit BDL delay (Timing Group 0). */
20136 /*! @{ */
20137 
20138 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_MASK (0x7FU)
20139 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_SHIFT (0U)
20140 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20141 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_MASK)
20142 /*! @} */
20143 
20144 /*! @name RXPBDLYTG1_R2 - Read DQ per-bit BDL delay (Timing Group 1). */
20145 /*! @{ */
20146 
20147 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_MASK (0x7FU)
20148 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_SHIFT (0U)
20149 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20150 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_MASK)
20151 /*! @} */
20152 
20153 /*! @name RXPBDLYTG2_R2 - Read DQ per-bit BDL delay (Timing Group 2). */
20154 /*! @{ */
20155 
20156 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_MASK (0x7FU)
20157 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_SHIFT (0U)
20158 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20159 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_MASK)
20160 /*! @} */
20161 
20162 /*! @name RXPBDLYTG3_R2 - Read DQ per-bit BDL delay (Timing Group 3). */
20163 /*! @{ */
20164 
20165 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_MASK (0x7FU)
20166 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_SHIFT (0U)
20167 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20168 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_MASK)
20169 /*! @} */
20170 
20171 /*! @name TXDQDLYTG0_R2_P0 - Write DQ Delay (Timing Group 0). */
20172 /*! @{ */
20173 
20174 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20175 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20176 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20177 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_MASK)
20178 /*! @} */
20179 
20180 /*! @name TXDQDLYTG1_R2_P0 - Write DQ Delay (Timing Group 1). */
20181 /*! @{ */
20182 
20183 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20184 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20185 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20186 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_MASK)
20187 /*! @} */
20188 
20189 /*! @name TXDQDLYTG2_R2_P0 - Write DQ Delay (Timing Group 2). */
20190 /*! @{ */
20191 
20192 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20193 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20194 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20195 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_MASK)
20196 /*! @} */
20197 
20198 /*! @name TXDQDLYTG3_R2_P0 - Write DQ Delay (Timing Group 3). */
20199 /*! @{ */
20200 
20201 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20202 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20203 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20204 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_MASK)
20205 /*! @} */
20206 
20207 /*! @name VREFDAC1_R3 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20208 /*! @{ */
20209 
20210 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_MASK (0x7FU)
20211 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_SHIFT (0U)
20212 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20213  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20214  *    have different ranges, depending on the Mission Mode settings for
20215  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20216  */
20217 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_MASK)
20218 /*! @} */
20219 
20220 /*! @name VREFDAC0_R3 - VrefDAC0 control for DQ Receiver */
20221 /*! @{ */
20222 
20223 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_MASK (0x7FU)
20224 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_SHIFT (0U)
20225 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20226  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20227  *    VREF generators have different ranges, depending on the Mission Mode settings for
20228  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20229  */
20230 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_MASK)
20231 /*! @} */
20232 
20233 /*! @name RXPBDLYTG0_R3 - Read DQ per-bit BDL delay (Timing Group 0). */
20234 /*! @{ */
20235 
20236 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_MASK (0x7FU)
20237 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_SHIFT (0U)
20238 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20239 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_MASK)
20240 /*! @} */
20241 
20242 /*! @name RXPBDLYTG1_R3 - Read DQ per-bit BDL delay (Timing Group 1). */
20243 /*! @{ */
20244 
20245 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_MASK (0x7FU)
20246 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_SHIFT (0U)
20247 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20248 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_MASK)
20249 /*! @} */
20250 
20251 /*! @name RXPBDLYTG2_R3 - Read DQ per-bit BDL delay (Timing Group 2). */
20252 /*! @{ */
20253 
20254 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_MASK (0x7FU)
20255 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_SHIFT (0U)
20256 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20257 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_MASK)
20258 /*! @} */
20259 
20260 /*! @name RXPBDLYTG3_R3 - Read DQ per-bit BDL delay (Timing Group 3). */
20261 /*! @{ */
20262 
20263 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_MASK (0x7FU)
20264 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_SHIFT (0U)
20265 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20266 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_MASK)
20267 /*! @} */
20268 
20269 /*! @name TXDQDLYTG0_R3_P0 - Write DQ Delay (Timing Group 0). */
20270 /*! @{ */
20271 
20272 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20273 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20274 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20275 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_MASK)
20276 /*! @} */
20277 
20278 /*! @name TXDQDLYTG1_R3_P0 - Write DQ Delay (Timing Group 1). */
20279 /*! @{ */
20280 
20281 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20282 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20283 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20284 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_MASK)
20285 /*! @} */
20286 
20287 /*! @name TXDQDLYTG2_R3_P0 - Write DQ Delay (Timing Group 2). */
20288 /*! @{ */
20289 
20290 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20291 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20292 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20293 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_MASK)
20294 /*! @} */
20295 
20296 /*! @name TXDQDLYTG3_R3_P0 - Write DQ Delay (Timing Group 3). */
20297 /*! @{ */
20298 
20299 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20300 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20301 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20302 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_MASK)
20303 /*! @} */
20304 
20305 /*! @name VREFDAC1_R4 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20306 /*! @{ */
20307 
20308 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_MASK (0x7FU)
20309 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_SHIFT (0U)
20310 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20311  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20312  *    have different ranges, depending on the Mission Mode settings for
20313  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20314  */
20315 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_MASK)
20316 /*! @} */
20317 
20318 /*! @name VREFDAC0_R4 - VrefDAC0 control for DQ Receiver */
20319 /*! @{ */
20320 
20321 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_MASK (0x7FU)
20322 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_SHIFT (0U)
20323 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20324  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20325  *    VREF generators have different ranges, depending on the Mission Mode settings for
20326  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20327  */
20328 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_MASK)
20329 /*! @} */
20330 
20331 /*! @name RXPBDLYTG0_R4 - Read DQ per-bit BDL delay (Timing Group 0). */
20332 /*! @{ */
20333 
20334 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_MASK (0x7FU)
20335 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_SHIFT (0U)
20336 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20337 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_MASK)
20338 /*! @} */
20339 
20340 /*! @name RXPBDLYTG1_R4 - Read DQ per-bit BDL delay (Timing Group 1). */
20341 /*! @{ */
20342 
20343 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_MASK (0x7FU)
20344 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_SHIFT (0U)
20345 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20346 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_MASK)
20347 /*! @} */
20348 
20349 /*! @name RXPBDLYTG2_R4 - Read DQ per-bit BDL delay (Timing Group 2). */
20350 /*! @{ */
20351 
20352 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_MASK (0x7FU)
20353 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_SHIFT (0U)
20354 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20355 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_MASK)
20356 /*! @} */
20357 
20358 /*! @name RXPBDLYTG3_R4 - Read DQ per-bit BDL delay (Timing Group 3). */
20359 /*! @{ */
20360 
20361 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_MASK (0x7FU)
20362 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_SHIFT (0U)
20363 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20364 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_MASK)
20365 /*! @} */
20366 
20367 /*! @name TXDQDLYTG0_R4_P0 - Write DQ Delay (Timing Group 0). */
20368 /*! @{ */
20369 
20370 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20371 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20372 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20373 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_MASK)
20374 /*! @} */
20375 
20376 /*! @name TXDQDLYTG1_R4_P0 - Write DQ Delay (Timing Group 1). */
20377 /*! @{ */
20378 
20379 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20380 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20381 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20382 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_MASK)
20383 /*! @} */
20384 
20385 /*! @name TXDQDLYTG2_R4_P0 - Write DQ Delay (Timing Group 2). */
20386 /*! @{ */
20387 
20388 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20389 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20390 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20391 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_MASK)
20392 /*! @} */
20393 
20394 /*! @name TXDQDLYTG3_R4_P0 - Write DQ Delay (Timing Group 3). */
20395 /*! @{ */
20396 
20397 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20398 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20399 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20400 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_MASK)
20401 /*! @} */
20402 
20403 /*! @name VREFDAC1_R5 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20404 /*! @{ */
20405 
20406 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_MASK (0x7FU)
20407 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_SHIFT (0U)
20408 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20409  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20410  *    have different ranges, depending on the Mission Mode settings for
20411  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20412  */
20413 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_MASK)
20414 /*! @} */
20415 
20416 /*! @name VREFDAC0_R5 - VrefDAC0 control for DQ Receiver */
20417 /*! @{ */
20418 
20419 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_MASK (0x7FU)
20420 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_SHIFT (0U)
20421 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20422  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20423  *    VREF generators have different ranges, depending on the Mission Mode settings for
20424  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20425  */
20426 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_MASK)
20427 /*! @} */
20428 
20429 /*! @name RXPBDLYTG0_R5 - Read DQ per-bit BDL delay (Timing Group 0). */
20430 /*! @{ */
20431 
20432 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_MASK (0x7FU)
20433 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_SHIFT (0U)
20434 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20435 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_MASK)
20436 /*! @} */
20437 
20438 /*! @name RXPBDLYTG1_R5 - Read DQ per-bit BDL delay (Timing Group 1). */
20439 /*! @{ */
20440 
20441 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_MASK (0x7FU)
20442 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_SHIFT (0U)
20443 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20444 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_MASK)
20445 /*! @} */
20446 
20447 /*! @name RXPBDLYTG2_R5 - Read DQ per-bit BDL delay (Timing Group 2). */
20448 /*! @{ */
20449 
20450 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_MASK (0x7FU)
20451 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_SHIFT (0U)
20452 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20453 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_MASK)
20454 /*! @} */
20455 
20456 /*! @name RXPBDLYTG3_R5 - Read DQ per-bit BDL delay (Timing Group 3). */
20457 /*! @{ */
20458 
20459 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_MASK (0x7FU)
20460 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_SHIFT (0U)
20461 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20462 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_MASK)
20463 /*! @} */
20464 
20465 /*! @name TXDQDLYTG0_R5_P0 - Write DQ Delay (Timing Group 0). */
20466 /*! @{ */
20467 
20468 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20469 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20470 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20471 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_MASK)
20472 /*! @} */
20473 
20474 /*! @name TXDQDLYTG1_R5_P0 - Write DQ Delay (Timing Group 1). */
20475 /*! @{ */
20476 
20477 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20478 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20479 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20480 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_MASK)
20481 /*! @} */
20482 
20483 /*! @name TXDQDLYTG2_R5_P0 - Write DQ Delay (Timing Group 2). */
20484 /*! @{ */
20485 
20486 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20487 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20488 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20489 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_MASK)
20490 /*! @} */
20491 
20492 /*! @name TXDQDLYTG3_R5_P0 - Write DQ Delay (Timing Group 3). */
20493 /*! @{ */
20494 
20495 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20496 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20497 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20498 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_MASK)
20499 /*! @} */
20500 
20501 /*! @name VREFDAC1_R6 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20502 /*! @{ */
20503 
20504 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_MASK (0x7FU)
20505 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_SHIFT (0U)
20506 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20507  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20508  *    have different ranges, depending on the Mission Mode settings for
20509  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20510  */
20511 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_MASK)
20512 /*! @} */
20513 
20514 /*! @name VREFDAC0_R6 - VrefDAC0 control for DQ Receiver */
20515 /*! @{ */
20516 
20517 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_MASK (0x7FU)
20518 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_SHIFT (0U)
20519 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20520  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20521  *    VREF generators have different ranges, depending on the Mission Mode settings for
20522  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20523  */
20524 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_MASK)
20525 /*! @} */
20526 
20527 /*! @name RXPBDLYTG0_R6 - Read DQ per-bit BDL delay (Timing Group 0). */
20528 /*! @{ */
20529 
20530 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_MASK (0x7FU)
20531 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_SHIFT (0U)
20532 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20533 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_MASK)
20534 /*! @} */
20535 
20536 /*! @name RXPBDLYTG1_R6 - Read DQ per-bit BDL delay (Timing Group 1). */
20537 /*! @{ */
20538 
20539 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_MASK (0x7FU)
20540 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_SHIFT (0U)
20541 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20542 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_MASK)
20543 /*! @} */
20544 
20545 /*! @name RXPBDLYTG2_R6 - Read DQ per-bit BDL delay (Timing Group 2). */
20546 /*! @{ */
20547 
20548 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_MASK (0x7FU)
20549 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_SHIFT (0U)
20550 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20551 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_MASK)
20552 /*! @} */
20553 
20554 /*! @name RXPBDLYTG3_R6 - Read DQ per-bit BDL delay (Timing Group 3). */
20555 /*! @{ */
20556 
20557 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_MASK (0x7FU)
20558 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_SHIFT (0U)
20559 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20560 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_MASK)
20561 /*! @} */
20562 
20563 /*! @name TXDQDLYTG0_R6_P0 - Write DQ Delay (Timing Group 0). */
20564 /*! @{ */
20565 
20566 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20567 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20568 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20569 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_MASK)
20570 /*! @} */
20571 
20572 /*! @name TXDQDLYTG1_R6_P0 - Write DQ Delay (Timing Group 1). */
20573 /*! @{ */
20574 
20575 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20576 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20577 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20578 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_MASK)
20579 /*! @} */
20580 
20581 /*! @name TXDQDLYTG2_R6_P0 - Write DQ Delay (Timing Group 2). */
20582 /*! @{ */
20583 
20584 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20585 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20586 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20587 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_MASK)
20588 /*! @} */
20589 
20590 /*! @name TXDQDLYTG3_R6_P0 - Write DQ Delay (Timing Group 3). */
20591 /*! @{ */
20592 
20593 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20594 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20595 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20596 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_MASK)
20597 /*! @} */
20598 
20599 /*! @name VREFDAC1_R7 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20600 /*! @{ */
20601 
20602 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_MASK (0x7FU)
20603 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_SHIFT (0U)
20604 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20605  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20606  *    have different ranges, depending on the Mission Mode settings for
20607  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20608  */
20609 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_MASK)
20610 /*! @} */
20611 
20612 /*! @name VREFDAC0_R7 - VrefDAC0 control for DQ Receiver */
20613 /*! @{ */
20614 
20615 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_MASK (0x7FU)
20616 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_SHIFT (0U)
20617 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20618  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20619  *    VREF generators have different ranges, depending on the Mission Mode settings for
20620  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20621  */
20622 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_MASK)
20623 /*! @} */
20624 
20625 /*! @name RXPBDLYTG0_R7 - Read DQ per-bit BDL delay (Timing Group 0). */
20626 /*! @{ */
20627 
20628 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_MASK (0x7FU)
20629 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_SHIFT (0U)
20630 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20631 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_MASK)
20632 /*! @} */
20633 
20634 /*! @name RXPBDLYTG1_R7 - Read DQ per-bit BDL delay (Timing Group 1). */
20635 /*! @{ */
20636 
20637 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_MASK (0x7FU)
20638 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_SHIFT (0U)
20639 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20640 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_MASK)
20641 /*! @} */
20642 
20643 /*! @name RXPBDLYTG2_R7 - Read DQ per-bit BDL delay (Timing Group 2). */
20644 /*! @{ */
20645 
20646 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_MASK (0x7FU)
20647 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_SHIFT (0U)
20648 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20649 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_MASK)
20650 /*! @} */
20651 
20652 /*! @name RXPBDLYTG3_R7 - Read DQ per-bit BDL delay (Timing Group 3). */
20653 /*! @{ */
20654 
20655 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_MASK (0x7FU)
20656 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_SHIFT (0U)
20657 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20658 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_MASK)
20659 /*! @} */
20660 
20661 /*! @name TXDQDLYTG0_R7_P0 - Write DQ Delay (Timing Group 0). */
20662 /*! @{ */
20663 
20664 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20665 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20666 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20667 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_MASK)
20668 /*! @} */
20669 
20670 /*! @name TXDQDLYTG1_R7_P0 - Write DQ Delay (Timing Group 1). */
20671 /*! @{ */
20672 
20673 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20674 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20675 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20676 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_MASK)
20677 /*! @} */
20678 
20679 /*! @name TXDQDLYTG2_R7_P0 - Write DQ Delay (Timing Group 2). */
20680 /*! @{ */
20681 
20682 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20683 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20684 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20685 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_MASK)
20686 /*! @} */
20687 
20688 /*! @name TXDQDLYTG3_R7_P0 - Write DQ Delay (Timing Group 3). */
20689 /*! @{ */
20690 
20691 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20692 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20693 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20694 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_MASK)
20695 /*! @} */
20696 
20697 /*! @name VREFDAC1_R8 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
20698 /*! @{ */
20699 
20700 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_MASK (0x7FU)
20701 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_SHIFT (0U)
20702 /*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
20703  *    enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
20704  *    have different ranges, depending on the Mission Mode settings for
20705  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
20706  */
20707 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_MASK)
20708 /*! @} */
20709 
20710 /*! @name VREFDAC0_R8 - VrefDAC0 control for DQ Receiver */
20711 /*! @{ */
20712 
20713 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_MASK (0x7FU)
20714 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_SHIFT (0U)
20715 /*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
20716  *    is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
20717  *    VREF generators have different ranges, depending on the Mission Mode settings for
20718  *    DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
20719  */
20720 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_MASK)
20721 /*! @} */
20722 
20723 /*! @name RXPBDLYTG0_R8 - Read DQ per-bit BDL delay (Timing Group 0). */
20724 /*! @{ */
20725 
20726 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_MASK (0x7FU)
20727 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_SHIFT (0U)
20728 /*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0). */
20729 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_MASK)
20730 /*! @} */
20731 
20732 /*! @name RXPBDLYTG1_R8 - Read DQ per-bit BDL delay (Timing Group 1). */
20733 /*! @{ */
20734 
20735 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_MASK (0x7FU)
20736 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_SHIFT (0U)
20737 /*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1). */
20738 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_MASK)
20739 /*! @} */
20740 
20741 /*! @name RXPBDLYTG2_R8 - Read DQ per-bit BDL delay (Timing Group 2). */
20742 /*! @{ */
20743 
20744 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_MASK (0x7FU)
20745 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_SHIFT (0U)
20746 /*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2). */
20747 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_MASK)
20748 /*! @} */
20749 
20750 /*! @name RXPBDLYTG3_R8 - Read DQ per-bit BDL delay (Timing Group 3). */
20751 /*! @{ */
20752 
20753 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_MASK (0x7FU)
20754 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_SHIFT (0U)
20755 /*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3). */
20756 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_MASK)
20757 /*! @} */
20758 
20759 /*! @name TXDQDLYTG0_R8_P0 - Write DQ Delay (Timing Group 0). */
20760 /*! @{ */
20761 
20762 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
20763 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
20764 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
20765 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_MASK)
20766 /*! @} */
20767 
20768 /*! @name TXDQDLYTG1_R8_P0 - Write DQ Delay (Timing Group 1). */
20769 /*! @{ */
20770 
20771 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
20772 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
20773 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
20774 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_MASK)
20775 /*! @} */
20776 
20777 /*! @name TXDQDLYTG2_R8_P0 - Write DQ Delay (Timing Group 2). */
20778 /*! @{ */
20779 
20780 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
20781 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
20782 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
20783 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_MASK)
20784 /*! @} */
20785 
20786 /*! @name TXDQDLYTG3_R8_P0 - Write DQ Delay (Timing Group 3). */
20787 /*! @{ */
20788 
20789 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
20790 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
20791 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
20792 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_MASK)
20793 /*! @} */
20794 
20795 /*! @name DFIMRL_P1 - DFI MaxReadLatency */
20796 /*! @{ */
20797 
20798 #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_MASK (0x1FU)
20799 #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_SHIFT (0U)
20800 /*! DFIMRL_p1 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
20801  *    until after all dbytes have their read data valid.
20802  */
20803 #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_MASK)
20804 /*! @} */
20805 
20806 /*! @name TXIMPEDANCECTRL0_B0_P1 - Data TX impedance controls */
20807 /*! @{ */
20808 
20809 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_MASK (0x3FU)
20810 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_SHIFT (0U)
20811 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
20812  *    used to select the target pull down output impedance.
20813  */
20814 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_MASK)
20815 
20816 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_MASK (0xFC0U)
20817 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_SHIFT (6U)
20818 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
20819  *    used to select the target pull down output impedance.
20820  */
20821 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_MASK)
20822 /*! @} */
20823 
20824 /*! @name DQDQSRCVCNTRL_B0_P1 - Dq/Dqs receiver control */
20825 /*! @{ */
20826 
20827 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_MASK (0x1U)
20828 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_SHIFT (0U)
20829 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
20830 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_MASK)
20831 
20832 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_MASK (0x2U)
20833 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_SHIFT (1U)
20834 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
20835 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_MASK)
20836 
20837 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_MASK (0xCU)
20838 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_SHIFT (2U)
20839 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
20840  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
20841  *    should not be overridden.
20842  */
20843 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_MASK)
20844 
20845 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_MASK (0x70U)
20846 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_SHIFT (4U)
20847 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
20848 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_MASK)
20849 
20850 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_MASK (0xF80U)
20851 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_SHIFT (7U)
20852 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
20853 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_MASK)
20854 /*! @} */
20855 
20856 /*! @name TXEQUALIZATIONMODE_P1 - Tx dq driver equalization mode controls. */
20857 /*! @{ */
20858 
20859 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_MASK (0x3U)
20860 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_SHIFT (0U)
20861 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_MASK)
20862 /*! @} */
20863 
20864 /*! @name TXIMPEDANCECTRL1_B0_P1 - TX impedance controls */
20865 /*! @{ */
20866 
20867 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_MASK (0x3FU)
20868 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_SHIFT (0U)
20869 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
20870  *    used to select the target pull up output impedance used in equalization.
20871  */
20872 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_MASK)
20873 
20874 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_MASK (0xFC0U)
20875 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_SHIFT (6U)
20876 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
20877  *    used to select the target pull up output impedance used in equalization.
20878  */
20879 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_MASK)
20880 /*! @} */
20881 
20882 /*! @name TXIMPEDANCECTRL2_B0_P1 - TX equalization impedance controls */
20883 /*! @{ */
20884 
20885 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_MASK (0x3FU)
20886 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_SHIFT (0U)
20887 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
20888  *    bus used to select the target pull up output impedance used in equalization.
20889  */
20890 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_MASK)
20891 
20892 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_MASK (0xFC0U)
20893 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_SHIFT (6U)
20894 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
20895  *    bus used to select the target pull down output impedance used in equalization.
20896  */
20897 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_MASK)
20898 /*! @} */
20899 
20900 /*! @name DQDQSRCVCNTRL2_P1 - Dq/Dqs receiver control */
20901 /*! @{ */
20902 
20903 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_MASK (0x1U)
20904 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_SHIFT (0U)
20905 /*! EnRxAgressivePDR - reserved */
20906 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_MASK)
20907 /*! @} */
20908 
20909 /*! @name TXODTDRVSTREN_B0_P1 - TX ODT driver strength control */
20910 /*! @{ */
20911 
20912 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_MASK (0x3FU)
20913 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_SHIFT (0U)
20914 /*! ODTStrenP - Selects the ODT pull-up impedance. */
20915 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_MASK)
20916 
20917 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_MASK (0xFC0U)
20918 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_SHIFT (6U)
20919 /*! ODTStrenN - Selects the ODT pull-down impedance. */
20920 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_MASK)
20921 /*! @} */
20922 
20923 /*! @name TXSLEWRATE_B0_P1 - TX slew rate controls */
20924 /*! @{ */
20925 
20926 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_MASK (0xFU)
20927 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_SHIFT (0U)
20928 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
20929 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_MASK)
20930 
20931 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_MASK (0xF0U)
20932 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_SHIFT (4U)
20933 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
20934 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_MASK)
20935 
20936 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_MASK (0x700U)
20937 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_SHIFT (8U)
20938 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
20939 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_MASK)
20940 /*! @} */
20941 
20942 /*! @name RXENDLYTG0_U0_P1 - Trained Receive Enable Delay (For Timing Group 0) */
20943 /*! @{ */
20944 
20945 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_MASK (0x7FFU)
20946 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_SHIFT (0U)
20947 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
20948  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
20949  */
20950 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_MASK)
20951 /*! @} */
20952 
20953 /*! @name RXENDLYTG1_U0_P1 - Trained Receive Enable Delay (For Timing Group 1) */
20954 /*! @{ */
20955 
20956 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_MASK (0x7FFU)
20957 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_SHIFT (0U)
20958 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
20959  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
20960  */
20961 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_MASK)
20962 /*! @} */
20963 
20964 /*! @name RXENDLYTG2_U0_P1 - Trained Receive Enable Delay (For Timing Group 2) */
20965 /*! @{ */
20966 
20967 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_MASK (0x7FFU)
20968 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_SHIFT (0U)
20969 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
20970  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
20971  */
20972 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_MASK)
20973 /*! @} */
20974 
20975 /*! @name RXENDLYTG3_U0_P1 - Trained Receive Enable Delay (For Timing Group 3) */
20976 /*! @{ */
20977 
20978 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_MASK (0x7FFU)
20979 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_SHIFT (0U)
20980 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
20981  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
20982  */
20983 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_MASK)
20984 /*! @} */
20985 
20986 /*! @name RXCLKDLYTG0_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
20987 /*! @{ */
20988 
20989 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
20990 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_SHIFT (0U)
20991 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
20992 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_MASK)
20993 /*! @} */
20994 
20995 /*! @name RXCLKDLYTG1_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
20996 /*! @{ */
20997 
20998 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
20999 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_SHIFT (0U)
21000 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
21001 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_MASK)
21002 /*! @} */
21003 
21004 /*! @name RXCLKDLYTG2_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
21005 /*! @{ */
21006 
21007 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
21008 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_SHIFT (0U)
21009 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
21010 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_MASK)
21011 /*! @} */
21012 
21013 /*! @name RXCLKDLYTG3_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
21014 /*! @{ */
21015 
21016 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
21017 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_SHIFT (0U)
21018 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
21019 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_MASK)
21020 /*! @} */
21021 
21022 /*! @name RXCLKCDLYTG0_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21023 /*! @{ */
21024 
21025 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
21026 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
21027 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21028 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_MASK)
21029 /*! @} */
21030 
21031 /*! @name RXCLKCDLYTG1_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21032 /*! @{ */
21033 
21034 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
21035 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
21036 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
21037 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_MASK)
21038 /*! @} */
21039 
21040 /*! @name RXCLKCDLYTG2_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
21041 /*! @{ */
21042 
21043 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
21044 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
21045 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
21046 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_MASK)
21047 /*! @} */
21048 
21049 /*! @name RXCLKCDLYTG3_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
21050 /*! @{ */
21051 
21052 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
21053 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
21054 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
21055 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_MASK)
21056 /*! @} */
21057 
21058 /*! @name TXDQDLYTG0_R0_P1 - Write DQ Delay (Timing Group 0). */
21059 /*! @{ */
21060 
21061 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21062 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21063 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21064 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_MASK)
21065 /*! @} */
21066 
21067 /*! @name TXDQDLYTG1_R0_P1 - Write DQ Delay (Timing Group 1). */
21068 /*! @{ */
21069 
21070 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21071 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21072 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21073 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_MASK)
21074 /*! @} */
21075 
21076 /*! @name TXDQDLYTG2_R0_P1 - Write DQ Delay (Timing Group 2). */
21077 /*! @{ */
21078 
21079 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21080 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21081 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21082 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_MASK)
21083 /*! @} */
21084 
21085 /*! @name TXDQDLYTG3_R0_P1 - Write DQ Delay (Timing Group 3). */
21086 /*! @{ */
21087 
21088 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21089 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21090 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21091 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_MASK)
21092 /*! @} */
21093 
21094 /*! @name TXDQSDLYTG0_U0_P1 - Write DQS Delay (Timing Group DEST=0). */
21095 /*! @{ */
21096 
21097 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
21098 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_SHIFT (0U)
21099 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
21100 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_MASK)
21101 /*! @} */
21102 
21103 /*! @name TXDQSDLYTG1_U0_P1 - Write DQS Delay (Timing Group DEST=1). */
21104 /*! @{ */
21105 
21106 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
21107 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_SHIFT (0U)
21108 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
21109 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_MASK)
21110 /*! @} */
21111 
21112 /*! @name TXDQSDLYTG2_U0_P1 - Write DQS Delay (Timing Group DEST=2). */
21113 /*! @{ */
21114 
21115 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
21116 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_SHIFT (0U)
21117 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
21118 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_MASK)
21119 /*! @} */
21120 
21121 /*! @name TXDQSDLYTG3_U0_P1 - Write DQS Delay (Timing Group DEST=3). */
21122 /*! @{ */
21123 
21124 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
21125 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_SHIFT (0U)
21126 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
21127 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_MASK)
21128 /*! @} */
21129 
21130 /*! @name TXIMPEDANCECTRL0_B1_P1 - Data TX impedance controls */
21131 /*! @{ */
21132 
21133 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_MASK (0x3FU)
21134 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_SHIFT (0U)
21135 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21136  *    used to select the target pull down output impedance.
21137  */
21138 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_MASK)
21139 
21140 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_MASK (0xFC0U)
21141 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_SHIFT (6U)
21142 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21143  *    used to select the target pull down output impedance.
21144  */
21145 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_MASK)
21146 /*! @} */
21147 
21148 /*! @name DQDQSRCVCNTRL_B1_P1 - Dq/Dqs receiver control */
21149 /*! @{ */
21150 
21151 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_MASK (0x1U)
21152 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_SHIFT (0U)
21153 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
21154 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_MASK)
21155 
21156 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_MASK (0x2U)
21157 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_SHIFT (1U)
21158 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
21159 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_MASK)
21160 
21161 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_MASK (0xCU)
21162 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_SHIFT (2U)
21163 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
21164  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
21165  *    should not be overridden.
21166  */
21167 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_MASK)
21168 
21169 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_MASK (0x70U)
21170 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_SHIFT (4U)
21171 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
21172 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_MASK)
21173 
21174 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_MASK (0xF80U)
21175 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_SHIFT (7U)
21176 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
21177 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_MASK)
21178 /*! @} */
21179 
21180 /*! @name TXIMPEDANCECTRL1_B1_P1 - TX impedance controls */
21181 /*! @{ */
21182 
21183 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_MASK (0x3FU)
21184 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_SHIFT (0U)
21185 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21186  *    used to select the target pull up output impedance used in equalization.
21187  */
21188 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_MASK)
21189 
21190 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_MASK (0xFC0U)
21191 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_SHIFT (6U)
21192 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21193  *    used to select the target pull up output impedance used in equalization.
21194  */
21195 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_MASK)
21196 /*! @} */
21197 
21198 /*! @name TXIMPEDANCECTRL2_B1_P1 - TX equalization impedance controls */
21199 /*! @{ */
21200 
21201 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_MASK (0x3FU)
21202 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_SHIFT (0U)
21203 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
21204  *    bus used to select the target pull up output impedance used in equalization.
21205  */
21206 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_MASK)
21207 
21208 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_MASK (0xFC0U)
21209 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_SHIFT (6U)
21210 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
21211  *    bus used to select the target pull down output impedance used in equalization.
21212  */
21213 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_MASK)
21214 /*! @} */
21215 
21216 /*! @name TXODTDRVSTREN_B1_P1 - TX ODT driver strength control */
21217 /*! @{ */
21218 
21219 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_MASK (0x3FU)
21220 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_SHIFT (0U)
21221 /*! ODTStrenP - Selects the ODT pull-up impedance. */
21222 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_MASK)
21223 
21224 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_MASK (0xFC0U)
21225 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_SHIFT (6U)
21226 /*! ODTStrenN - Selects the ODT pull-down impedance. */
21227 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_MASK)
21228 /*! @} */
21229 
21230 /*! @name TXSLEWRATE_B1_P1 - TX slew rate controls */
21231 /*! @{ */
21232 
21233 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_MASK (0xFU)
21234 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_SHIFT (0U)
21235 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
21236 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_MASK)
21237 
21238 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_MASK (0xF0U)
21239 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_SHIFT (4U)
21240 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
21241 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_MASK)
21242 
21243 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_MASK (0x700U)
21244 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_SHIFT (8U)
21245 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
21246 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_MASK)
21247 /*! @} */
21248 
21249 /*! @name RXENDLYTG0_U1_P1 - Trained Receive Enable Delay (For Timing Group 0) */
21250 /*! @{ */
21251 
21252 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_MASK (0x7FFU)
21253 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_SHIFT (0U)
21254 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
21255  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21256  */
21257 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_MASK)
21258 /*! @} */
21259 
21260 /*! @name RXENDLYTG1_U1_P1 - Trained Receive Enable Delay (For Timing Group 1) */
21261 /*! @{ */
21262 
21263 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_MASK (0x7FFU)
21264 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_SHIFT (0U)
21265 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
21266  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21267  */
21268 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_MASK)
21269 /*! @} */
21270 
21271 /*! @name RXENDLYTG2_U1_P1 - Trained Receive Enable Delay (For Timing Group 2) */
21272 /*! @{ */
21273 
21274 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_MASK (0x7FFU)
21275 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_SHIFT (0U)
21276 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
21277  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21278  */
21279 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_MASK)
21280 /*! @} */
21281 
21282 /*! @name RXENDLYTG3_U1_P1 - Trained Receive Enable Delay (For Timing Group 3) */
21283 /*! @{ */
21284 
21285 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_MASK (0x7FFU)
21286 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_SHIFT (0U)
21287 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
21288  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21289  */
21290 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_MASK)
21291 /*! @} */
21292 
21293 /*! @name RXCLKDLYTG0_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
21294 /*! @{ */
21295 
21296 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
21297 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_SHIFT (0U)
21298 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
21299 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_MASK)
21300 /*! @} */
21301 
21302 /*! @name RXCLKDLYTG1_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
21303 /*! @{ */
21304 
21305 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
21306 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_SHIFT (0U)
21307 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
21308 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_MASK)
21309 /*! @} */
21310 
21311 /*! @name RXCLKDLYTG2_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
21312 /*! @{ */
21313 
21314 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
21315 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_SHIFT (0U)
21316 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
21317 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_MASK)
21318 /*! @} */
21319 
21320 /*! @name RXCLKDLYTG3_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
21321 /*! @{ */
21322 
21323 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
21324 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_SHIFT (0U)
21325 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
21326 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_MASK)
21327 /*! @} */
21328 
21329 /*! @name RXCLKCDLYTG0_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21330 /*! @{ */
21331 
21332 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
21333 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
21334 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21335 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_MASK)
21336 /*! @} */
21337 
21338 /*! @name RXCLKCDLYTG1_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21339 /*! @{ */
21340 
21341 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
21342 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
21343 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
21344 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_MASK)
21345 /*! @} */
21346 
21347 /*! @name RXCLKCDLYTG2_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
21348 /*! @{ */
21349 
21350 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
21351 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
21352 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
21353 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_MASK)
21354 /*! @} */
21355 
21356 /*! @name RXCLKCDLYTG3_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
21357 /*! @{ */
21358 
21359 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
21360 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
21361 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
21362 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_MASK)
21363 /*! @} */
21364 
21365 /*! @name TXDQDLYTG0_R1_P1 - Write DQ Delay (Timing Group 0). */
21366 /*! @{ */
21367 
21368 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21369 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21370 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21371 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_MASK)
21372 /*! @} */
21373 
21374 /*! @name TXDQDLYTG1_R1_P1 - Write DQ Delay (Timing Group 1). */
21375 /*! @{ */
21376 
21377 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21378 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21379 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21380 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_MASK)
21381 /*! @} */
21382 
21383 /*! @name TXDQDLYTG2_R1_P1 - Write DQ Delay (Timing Group 2). */
21384 /*! @{ */
21385 
21386 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21387 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21388 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21389 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_MASK)
21390 /*! @} */
21391 
21392 /*! @name TXDQDLYTG3_R1_P1 - Write DQ Delay (Timing Group 3). */
21393 /*! @{ */
21394 
21395 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21396 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21397 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21398 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_MASK)
21399 /*! @} */
21400 
21401 /*! @name TXDQSDLYTG0_U1_P1 - Write DQS Delay (Timing Group DEST=0). */
21402 /*! @{ */
21403 
21404 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
21405 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_SHIFT (0U)
21406 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
21407 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_MASK)
21408 /*! @} */
21409 
21410 /*! @name TXDQSDLYTG1_U1_P1 - Write DQS Delay (Timing Group DEST=1). */
21411 /*! @{ */
21412 
21413 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
21414 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_SHIFT (0U)
21415 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
21416 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_MASK)
21417 /*! @} */
21418 
21419 /*! @name TXDQSDLYTG2_U1_P1 - Write DQS Delay (Timing Group DEST=2). */
21420 /*! @{ */
21421 
21422 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
21423 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_SHIFT (0U)
21424 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
21425 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_MASK)
21426 /*! @} */
21427 
21428 /*! @name TXDQSDLYTG3_U1_P1 - Write DQS Delay (Timing Group DEST=3). */
21429 /*! @{ */
21430 
21431 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
21432 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_SHIFT (0U)
21433 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
21434 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_MASK)
21435 /*! @} */
21436 
21437 /*! @name TXDQDLYTG0_R2_P1 - Write DQ Delay (Timing Group 0). */
21438 /*! @{ */
21439 
21440 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21441 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21442 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21443 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_MASK)
21444 /*! @} */
21445 
21446 /*! @name TXDQDLYTG1_R2_P1 - Write DQ Delay (Timing Group 1). */
21447 /*! @{ */
21448 
21449 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21450 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21451 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21452 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_MASK)
21453 /*! @} */
21454 
21455 /*! @name TXDQDLYTG2_R2_P1 - Write DQ Delay (Timing Group 2). */
21456 /*! @{ */
21457 
21458 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21459 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21460 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21461 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_MASK)
21462 /*! @} */
21463 
21464 /*! @name TXDQDLYTG3_R2_P1 - Write DQ Delay (Timing Group 3). */
21465 /*! @{ */
21466 
21467 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21468 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21469 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21470 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_MASK)
21471 /*! @} */
21472 
21473 /*! @name TXDQDLYTG0_R3_P1 - Write DQ Delay (Timing Group 0). */
21474 /*! @{ */
21475 
21476 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21477 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21478 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21479 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_MASK)
21480 /*! @} */
21481 
21482 /*! @name TXDQDLYTG1_R3_P1 - Write DQ Delay (Timing Group 1). */
21483 /*! @{ */
21484 
21485 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21486 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21487 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21488 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_MASK)
21489 /*! @} */
21490 
21491 /*! @name TXDQDLYTG2_R3_P1 - Write DQ Delay (Timing Group 2). */
21492 /*! @{ */
21493 
21494 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21495 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21496 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21497 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_MASK)
21498 /*! @} */
21499 
21500 /*! @name TXDQDLYTG3_R3_P1 - Write DQ Delay (Timing Group 3). */
21501 /*! @{ */
21502 
21503 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21504 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21505 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21506 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_MASK)
21507 /*! @} */
21508 
21509 /*! @name TXDQDLYTG0_R4_P1 - Write DQ Delay (Timing Group 0). */
21510 /*! @{ */
21511 
21512 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21513 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21514 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21515 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_MASK)
21516 /*! @} */
21517 
21518 /*! @name TXDQDLYTG1_R4_P1 - Write DQ Delay (Timing Group 1). */
21519 /*! @{ */
21520 
21521 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21522 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21523 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21524 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_MASK)
21525 /*! @} */
21526 
21527 /*! @name TXDQDLYTG2_R4_P1 - Write DQ Delay (Timing Group 2). */
21528 /*! @{ */
21529 
21530 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21531 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21532 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21533 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_MASK)
21534 /*! @} */
21535 
21536 /*! @name TXDQDLYTG3_R4_P1 - Write DQ Delay (Timing Group 3). */
21537 /*! @{ */
21538 
21539 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21540 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21541 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21542 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_MASK)
21543 /*! @} */
21544 
21545 /*! @name TXDQDLYTG0_R5_P1 - Write DQ Delay (Timing Group 0). */
21546 /*! @{ */
21547 
21548 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21549 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21550 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21551 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_MASK)
21552 /*! @} */
21553 
21554 /*! @name TXDQDLYTG1_R5_P1 - Write DQ Delay (Timing Group 1). */
21555 /*! @{ */
21556 
21557 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21558 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21559 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21560 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_MASK)
21561 /*! @} */
21562 
21563 /*! @name TXDQDLYTG2_R5_P1 - Write DQ Delay (Timing Group 2). */
21564 /*! @{ */
21565 
21566 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21567 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21568 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21569 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_MASK)
21570 /*! @} */
21571 
21572 /*! @name TXDQDLYTG3_R5_P1 - Write DQ Delay (Timing Group 3). */
21573 /*! @{ */
21574 
21575 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21576 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21577 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21578 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_MASK)
21579 /*! @} */
21580 
21581 /*! @name TXDQDLYTG0_R6_P1 - Write DQ Delay (Timing Group 0). */
21582 /*! @{ */
21583 
21584 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21585 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21586 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21587 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_MASK)
21588 /*! @} */
21589 
21590 /*! @name TXDQDLYTG1_R6_P1 - Write DQ Delay (Timing Group 1). */
21591 /*! @{ */
21592 
21593 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21594 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21595 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21596 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_MASK)
21597 /*! @} */
21598 
21599 /*! @name TXDQDLYTG2_R6_P1 - Write DQ Delay (Timing Group 2). */
21600 /*! @{ */
21601 
21602 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21603 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21604 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21605 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_MASK)
21606 /*! @} */
21607 
21608 /*! @name TXDQDLYTG3_R6_P1 - Write DQ Delay (Timing Group 3). */
21609 /*! @{ */
21610 
21611 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21612 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21613 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21614 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_MASK)
21615 /*! @} */
21616 
21617 /*! @name TXDQDLYTG0_R7_P1 - Write DQ Delay (Timing Group 0). */
21618 /*! @{ */
21619 
21620 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21621 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21622 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21623 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_MASK)
21624 /*! @} */
21625 
21626 /*! @name TXDQDLYTG1_R7_P1 - Write DQ Delay (Timing Group 1). */
21627 /*! @{ */
21628 
21629 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21630 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21631 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21632 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_MASK)
21633 /*! @} */
21634 
21635 /*! @name TXDQDLYTG2_R7_P1 - Write DQ Delay (Timing Group 2). */
21636 /*! @{ */
21637 
21638 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21639 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21640 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21641 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_MASK)
21642 /*! @} */
21643 
21644 /*! @name TXDQDLYTG3_R7_P1 - Write DQ Delay (Timing Group 3). */
21645 /*! @{ */
21646 
21647 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21648 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21649 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21650 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_MASK)
21651 /*! @} */
21652 
21653 /*! @name TXDQDLYTG0_R8_P1 - Write DQ Delay (Timing Group 0). */
21654 /*! @{ */
21655 
21656 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21657 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
21658 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21659 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_MASK)
21660 /*! @} */
21661 
21662 /*! @name TXDQDLYTG1_R8_P1 - Write DQ Delay (Timing Group 1). */
21663 /*! @{ */
21664 
21665 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21666 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
21667 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21668 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_MASK)
21669 /*! @} */
21670 
21671 /*! @name TXDQDLYTG2_R8_P1 - Write DQ Delay (Timing Group 2). */
21672 /*! @{ */
21673 
21674 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21675 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
21676 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21677 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_MASK)
21678 /*! @} */
21679 
21680 /*! @name TXDQDLYTG3_R8_P1 - Write DQ Delay (Timing Group 3). */
21681 /*! @{ */
21682 
21683 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
21684 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
21685 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
21686 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_MASK)
21687 /*! @} */
21688 
21689 /*! @name DFIMRL_P2 - DFI MaxReadLatency */
21690 /*! @{ */
21691 
21692 #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_MASK (0x1FU)
21693 #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_SHIFT (0U)
21694 /*! DFIMRL_p2 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
21695  *    until after all dbytes have their read data valid.
21696  */
21697 #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_MASK)
21698 /*! @} */
21699 
21700 /*! @name TXIMPEDANCECTRL0_B0_P2 - Data TX impedance controls */
21701 /*! @{ */
21702 
21703 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_MASK (0x3FU)
21704 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_SHIFT (0U)
21705 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21706  *    used to select the target pull down output impedance.
21707  */
21708 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_MASK)
21709 
21710 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_MASK (0xFC0U)
21711 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_SHIFT (6U)
21712 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21713  *    used to select the target pull down output impedance.
21714  */
21715 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_MASK)
21716 /*! @} */
21717 
21718 /*! @name DQDQSRCVCNTRL_B0_P2 - Dq/Dqs receiver control */
21719 /*! @{ */
21720 
21721 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_MASK (0x1U)
21722 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_SHIFT (0U)
21723 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
21724 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_MASK)
21725 
21726 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_MASK (0x2U)
21727 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_SHIFT (1U)
21728 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
21729 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_MASK)
21730 
21731 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_MASK (0xCU)
21732 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_SHIFT (2U)
21733 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
21734  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
21735  *    should not be overridden.
21736  */
21737 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_MASK)
21738 
21739 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_MASK (0x70U)
21740 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_SHIFT (4U)
21741 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
21742 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_MASK)
21743 
21744 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_MASK (0xF80U)
21745 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_SHIFT (7U)
21746 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
21747 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_MASK)
21748 /*! @} */
21749 
21750 /*! @name TXEQUALIZATIONMODE_P2 - Tx dq driver equalization mode controls. */
21751 /*! @{ */
21752 
21753 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_MASK (0x3U)
21754 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_SHIFT (0U)
21755 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_MASK)
21756 /*! @} */
21757 
21758 /*! @name TXIMPEDANCECTRL1_B0_P2 - TX impedance controls */
21759 /*! @{ */
21760 
21761 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_MASK (0x3FU)
21762 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_SHIFT (0U)
21763 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21764  *    used to select the target pull up output impedance used in equalization.
21765  */
21766 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_MASK)
21767 
21768 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_MASK (0xFC0U)
21769 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_SHIFT (6U)
21770 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
21771  *    used to select the target pull up output impedance used in equalization.
21772  */
21773 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_MASK)
21774 /*! @} */
21775 
21776 /*! @name TXIMPEDANCECTRL2_B0_P2 - TX equalization impedance controls */
21777 /*! @{ */
21778 
21779 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_MASK (0x3FU)
21780 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_SHIFT (0U)
21781 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
21782  *    bus used to select the target pull up output impedance used in equalization.
21783  */
21784 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_MASK)
21785 
21786 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_MASK (0xFC0U)
21787 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_SHIFT (6U)
21788 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
21789  *    bus used to select the target pull down output impedance used in equalization.
21790  */
21791 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_MASK)
21792 /*! @} */
21793 
21794 /*! @name DQDQSRCVCNTRL2_P2 - Dq/Dqs receiver control */
21795 /*! @{ */
21796 
21797 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_MASK (0x1U)
21798 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_SHIFT (0U)
21799 /*! EnRxAgressivePDR - reserved */
21800 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_MASK)
21801 /*! @} */
21802 
21803 /*! @name TXODTDRVSTREN_B0_P2 - TX ODT driver strength control */
21804 /*! @{ */
21805 
21806 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_MASK (0x3FU)
21807 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_SHIFT (0U)
21808 /*! ODTStrenP - Selects the ODT pull-up impedance. */
21809 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_MASK)
21810 
21811 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_MASK (0xFC0U)
21812 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_SHIFT (6U)
21813 /*! ODTStrenN - Selects the ODT pull-down impedance. */
21814 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_MASK)
21815 /*! @} */
21816 
21817 /*! @name TXSLEWRATE_B0_P2 - TX slew rate controls */
21818 /*! @{ */
21819 
21820 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_MASK (0xFU)
21821 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_SHIFT (0U)
21822 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
21823 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_MASK)
21824 
21825 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_MASK (0xF0U)
21826 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_SHIFT (4U)
21827 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
21828 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_MASK)
21829 
21830 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_MASK (0x700U)
21831 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_SHIFT (8U)
21832 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
21833 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_MASK)
21834 /*! @} */
21835 
21836 /*! @name RXENDLYTG0_U0_P2 - Trained Receive Enable Delay (For Timing Group 0) */
21837 /*! @{ */
21838 
21839 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_MASK (0x7FFU)
21840 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_SHIFT (0U)
21841 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
21842  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21843  */
21844 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_MASK)
21845 /*! @} */
21846 
21847 /*! @name RXENDLYTG1_U0_P2 - Trained Receive Enable Delay (For Timing Group 1) */
21848 /*! @{ */
21849 
21850 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_MASK (0x7FFU)
21851 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_SHIFT (0U)
21852 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
21853  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21854  */
21855 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_MASK)
21856 /*! @} */
21857 
21858 /*! @name RXENDLYTG2_U0_P2 - Trained Receive Enable Delay (For Timing Group 2) */
21859 /*! @{ */
21860 
21861 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_MASK (0x7FFU)
21862 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_SHIFT (0U)
21863 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
21864  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21865  */
21866 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_MASK)
21867 /*! @} */
21868 
21869 /*! @name RXENDLYTG3_U0_P2 - Trained Receive Enable Delay (For Timing Group 3) */
21870 /*! @{ */
21871 
21872 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_MASK (0x7FFU)
21873 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_SHIFT (0U)
21874 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
21875  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
21876  */
21877 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_MASK)
21878 /*! @} */
21879 
21880 /*! @name RXCLKDLYTG0_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
21881 /*! @{ */
21882 
21883 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
21884 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_SHIFT (0U)
21885 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
21886 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_MASK)
21887 /*! @} */
21888 
21889 /*! @name RXCLKDLYTG1_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
21890 /*! @{ */
21891 
21892 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
21893 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_SHIFT (0U)
21894 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
21895 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_MASK)
21896 /*! @} */
21897 
21898 /*! @name RXCLKDLYTG2_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
21899 /*! @{ */
21900 
21901 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
21902 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_SHIFT (0U)
21903 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
21904 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_MASK)
21905 /*! @} */
21906 
21907 /*! @name RXCLKDLYTG3_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
21908 /*! @{ */
21909 
21910 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
21911 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_SHIFT (0U)
21912 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
21913 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_MASK)
21914 /*! @} */
21915 
21916 /*! @name RXCLKCDLYTG0_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21917 /*! @{ */
21918 
21919 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
21920 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
21921 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21922 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_MASK)
21923 /*! @} */
21924 
21925 /*! @name RXCLKCDLYTG1_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
21926 /*! @{ */
21927 
21928 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
21929 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
21930 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
21931 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_MASK)
21932 /*! @} */
21933 
21934 /*! @name RXCLKCDLYTG2_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
21935 /*! @{ */
21936 
21937 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
21938 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
21939 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
21940 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_MASK)
21941 /*! @} */
21942 
21943 /*! @name RXCLKCDLYTG3_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
21944 /*! @{ */
21945 
21946 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
21947 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
21948 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
21949 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_MASK)
21950 /*! @} */
21951 
21952 /*! @name PPTDQSCNTINVTRNTG0_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
21953 /*! @{ */
21954 
21955 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_MASK (0xFFFFU)
21956 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_SHIFT (0U)
21957 /*! PptDqsCntInvTrnTg0_p2 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation. */
21958 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_MASK)
21959 /*! @} */
21960 
21961 /*! @name PPTDQSCNTINVTRNTG1_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
21962 /*! @{ */
21963 
21964 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_MASK (0xFFFFU)
21965 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_SHIFT (0U)
21966 /*! PptDqsCntInvTrnTg1_p2 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation. */
21967 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_MASK)
21968 /*! @} */
21969 
21970 /*! @name TXDQDLYTG0_R0_P2 - Write DQ Delay (Timing Group 0). */
21971 /*! @{ */
21972 
21973 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
21974 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
21975 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
21976 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_MASK)
21977 /*! @} */
21978 
21979 /*! @name TXDQDLYTG1_R0_P2 - Write DQ Delay (Timing Group 1). */
21980 /*! @{ */
21981 
21982 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
21983 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
21984 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
21985 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_MASK)
21986 /*! @} */
21987 
21988 /*! @name TXDQDLYTG2_R0_P2 - Write DQ Delay (Timing Group 2). */
21989 /*! @{ */
21990 
21991 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
21992 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
21993 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
21994 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_MASK)
21995 /*! @} */
21996 
21997 /*! @name TXDQDLYTG3_R0_P2 - Write DQ Delay (Timing Group 3). */
21998 /*! @{ */
21999 
22000 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22001 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22002 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22003 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_MASK)
22004 /*! @} */
22005 
22006 /*! @name TXDQSDLYTG0_U0_P2 - Write DQS Delay (Timing Group DEST=0). */
22007 /*! @{ */
22008 
22009 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
22010 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_SHIFT (0U)
22011 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
22012 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_MASK)
22013 /*! @} */
22014 
22015 /*! @name TXDQSDLYTG1_U0_P2 - Write DQS Delay (Timing Group DEST=1). */
22016 /*! @{ */
22017 
22018 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
22019 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_SHIFT (0U)
22020 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
22021 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_MASK)
22022 /*! @} */
22023 
22024 /*! @name TXDQSDLYTG2_U0_P2 - Write DQS Delay (Timing Group DEST=2). */
22025 /*! @{ */
22026 
22027 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
22028 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_SHIFT (0U)
22029 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
22030 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_MASK)
22031 /*! @} */
22032 
22033 /*! @name TXDQSDLYTG3_U0_P2 - Write DQS Delay (Timing Group DEST=3). */
22034 /*! @{ */
22035 
22036 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
22037 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_SHIFT (0U)
22038 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
22039 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_MASK)
22040 /*! @} */
22041 
22042 /*! @name TXIMPEDANCECTRL0_B1_P2 - Data TX impedance controls */
22043 /*! @{ */
22044 
22045 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_MASK (0x3FU)
22046 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_SHIFT (0U)
22047 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22048  *    used to select the target pull down output impedance.
22049  */
22050 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_MASK)
22051 
22052 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_MASK (0xFC0U)
22053 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_SHIFT (6U)
22054 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22055  *    used to select the target pull down output impedance.
22056  */
22057 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_MASK)
22058 /*! @} */
22059 
22060 /*! @name DQDQSRCVCNTRL_B1_P2 - Dq/Dqs receiver control */
22061 /*! @{ */
22062 
22063 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_MASK (0x1U)
22064 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_SHIFT (0U)
22065 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
22066 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_MASK)
22067 
22068 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_MASK (0x2U)
22069 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_SHIFT (1U)
22070 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
22071 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_MASK)
22072 
22073 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_MASK (0xCU)
22074 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_SHIFT (2U)
22075 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
22076  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
22077  *    should not be overridden.
22078  */
22079 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_MASK)
22080 
22081 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_MASK (0x70U)
22082 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_SHIFT (4U)
22083 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
22084 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_MASK)
22085 
22086 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_MASK (0xF80U)
22087 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_SHIFT (7U)
22088 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
22089 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_MASK)
22090 /*! @} */
22091 
22092 /*! @name TXIMPEDANCECTRL1_B1_P2 - TX impedance controls */
22093 /*! @{ */
22094 
22095 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_MASK (0x3FU)
22096 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_SHIFT (0U)
22097 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22098  *    used to select the target pull up output impedance used in equalization.
22099  */
22100 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_MASK)
22101 
22102 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_MASK (0xFC0U)
22103 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_SHIFT (6U)
22104 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22105  *    used to select the target pull up output impedance used in equalization.
22106  */
22107 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_MASK)
22108 /*! @} */
22109 
22110 /*! @name TXIMPEDANCECTRL2_B1_P2 - TX equalization impedance controls */
22111 /*! @{ */
22112 
22113 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_MASK (0x3FU)
22114 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_SHIFT (0U)
22115 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
22116  *    bus used to select the target pull up output impedance used in equalization.
22117  */
22118 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_MASK)
22119 
22120 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_MASK (0xFC0U)
22121 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_SHIFT (6U)
22122 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
22123  *    bus used to select the target pull down output impedance used in equalization.
22124  */
22125 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_MASK)
22126 /*! @} */
22127 
22128 /*! @name TXODTDRVSTREN_B1_P2 - TX ODT driver strength control */
22129 /*! @{ */
22130 
22131 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_MASK (0x3FU)
22132 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_SHIFT (0U)
22133 /*! ODTStrenP - Selects the ODT pull-up impedance. */
22134 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_MASK)
22135 
22136 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_MASK (0xFC0U)
22137 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_SHIFT (6U)
22138 /*! ODTStrenN - Selects the ODT pull-down impedance. */
22139 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_MASK)
22140 /*! @} */
22141 
22142 /*! @name TXSLEWRATE_B1_P2 - TX slew rate controls */
22143 /*! @{ */
22144 
22145 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_MASK (0xFU)
22146 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_SHIFT (0U)
22147 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
22148 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_MASK)
22149 
22150 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_MASK (0xF0U)
22151 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_SHIFT (4U)
22152 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
22153 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_MASK)
22154 
22155 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_MASK (0x700U)
22156 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_SHIFT (8U)
22157 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
22158 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_MASK)
22159 /*! @} */
22160 
22161 /*! @name RXENDLYTG0_U1_P2 - Trained Receive Enable Delay (For Timing Group 0) */
22162 /*! @{ */
22163 
22164 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_MASK (0x7FFU)
22165 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_SHIFT (0U)
22166 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
22167  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22168  */
22169 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_MASK)
22170 /*! @} */
22171 
22172 /*! @name RXENDLYTG1_U1_P2 - Trained Receive Enable Delay (For Timing Group 1) */
22173 /*! @{ */
22174 
22175 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_MASK (0x7FFU)
22176 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_SHIFT (0U)
22177 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
22178  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22179  */
22180 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_MASK)
22181 /*! @} */
22182 
22183 /*! @name RXENDLYTG2_U1_P2 - Trained Receive Enable Delay (For Timing Group 2) */
22184 /*! @{ */
22185 
22186 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_MASK (0x7FFU)
22187 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_SHIFT (0U)
22188 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
22189  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22190  */
22191 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_MASK)
22192 /*! @} */
22193 
22194 /*! @name RXENDLYTG3_U1_P2 - Trained Receive Enable Delay (For Timing Group 3) */
22195 /*! @{ */
22196 
22197 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_MASK (0x7FFU)
22198 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_SHIFT (0U)
22199 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
22200  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22201  */
22202 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_MASK)
22203 /*! @} */
22204 
22205 /*! @name RXCLKDLYTG0_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
22206 /*! @{ */
22207 
22208 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
22209 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_SHIFT (0U)
22210 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
22211 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_MASK)
22212 /*! @} */
22213 
22214 /*! @name RXCLKDLYTG1_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
22215 /*! @{ */
22216 
22217 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
22218 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_SHIFT (0U)
22219 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
22220 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_MASK)
22221 /*! @} */
22222 
22223 /*! @name RXCLKDLYTG2_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
22224 /*! @{ */
22225 
22226 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
22227 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_SHIFT (0U)
22228 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
22229 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_MASK)
22230 /*! @} */
22231 
22232 /*! @name RXCLKDLYTG3_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
22233 /*! @{ */
22234 
22235 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
22236 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_SHIFT (0U)
22237 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
22238 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_MASK)
22239 /*! @} */
22240 
22241 /*! @name RXCLKCDLYTG0_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
22242 /*! @{ */
22243 
22244 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
22245 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
22246 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
22247 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_MASK)
22248 /*! @} */
22249 
22250 /*! @name RXCLKCDLYTG1_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
22251 /*! @{ */
22252 
22253 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
22254 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
22255 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
22256 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_MASK)
22257 /*! @} */
22258 
22259 /*! @name RXCLKCDLYTG2_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
22260 /*! @{ */
22261 
22262 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
22263 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
22264 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
22265 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_MASK)
22266 /*! @} */
22267 
22268 /*! @name RXCLKCDLYTG3_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
22269 /*! @{ */
22270 
22271 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
22272 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
22273 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
22274 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_MASK)
22275 /*! @} */
22276 
22277 /*! @name TXDQDLYTG0_R1_P2 - Write DQ Delay (Timing Group 0). */
22278 /*! @{ */
22279 
22280 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22281 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22282 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22283 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_MASK)
22284 /*! @} */
22285 
22286 /*! @name TXDQDLYTG1_R1_P2 - Write DQ Delay (Timing Group 1). */
22287 /*! @{ */
22288 
22289 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22290 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22291 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22292 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_MASK)
22293 /*! @} */
22294 
22295 /*! @name TXDQDLYTG2_R1_P2 - Write DQ Delay (Timing Group 2). */
22296 /*! @{ */
22297 
22298 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22299 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22300 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22301 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_MASK)
22302 /*! @} */
22303 
22304 /*! @name TXDQDLYTG3_R1_P2 - Write DQ Delay (Timing Group 3). */
22305 /*! @{ */
22306 
22307 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22308 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22309 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22310 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_MASK)
22311 /*! @} */
22312 
22313 /*! @name TXDQSDLYTG0_U1_P2 - Write DQS Delay (Timing Group DEST=0). */
22314 /*! @{ */
22315 
22316 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
22317 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_SHIFT (0U)
22318 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
22319 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_MASK)
22320 /*! @} */
22321 
22322 /*! @name TXDQSDLYTG1_U1_P2 - Write DQS Delay (Timing Group DEST=1). */
22323 /*! @{ */
22324 
22325 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
22326 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_SHIFT (0U)
22327 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
22328 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_MASK)
22329 /*! @} */
22330 
22331 /*! @name TXDQSDLYTG2_U1_P2 - Write DQS Delay (Timing Group DEST=2). */
22332 /*! @{ */
22333 
22334 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
22335 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_SHIFT (0U)
22336 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
22337 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_MASK)
22338 /*! @} */
22339 
22340 /*! @name TXDQSDLYTG3_U1_P2 - Write DQS Delay (Timing Group DEST=3). */
22341 /*! @{ */
22342 
22343 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
22344 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_SHIFT (0U)
22345 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
22346 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_MASK)
22347 /*! @} */
22348 
22349 /*! @name TXDQDLYTG0_R2_P2 - Write DQ Delay (Timing Group 0). */
22350 /*! @{ */
22351 
22352 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22353 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22354 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22355 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_MASK)
22356 /*! @} */
22357 
22358 /*! @name TXDQDLYTG1_R2_P2 - Write DQ Delay (Timing Group 1). */
22359 /*! @{ */
22360 
22361 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22362 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22363 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22364 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_MASK)
22365 /*! @} */
22366 
22367 /*! @name TXDQDLYTG2_R2_P2 - Write DQ Delay (Timing Group 2). */
22368 /*! @{ */
22369 
22370 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22371 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22372 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22373 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_MASK)
22374 /*! @} */
22375 
22376 /*! @name TXDQDLYTG3_R2_P2 - Write DQ Delay (Timing Group 3). */
22377 /*! @{ */
22378 
22379 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22380 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22381 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22382 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_MASK)
22383 /*! @} */
22384 
22385 /*! @name TXDQDLYTG0_R3_P2 - Write DQ Delay (Timing Group 0). */
22386 /*! @{ */
22387 
22388 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22389 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22390 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22391 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_MASK)
22392 /*! @} */
22393 
22394 /*! @name TXDQDLYTG1_R3_P2 - Write DQ Delay (Timing Group 1). */
22395 /*! @{ */
22396 
22397 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22398 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22399 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22400 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_MASK)
22401 /*! @} */
22402 
22403 /*! @name TXDQDLYTG2_R3_P2 - Write DQ Delay (Timing Group 2). */
22404 /*! @{ */
22405 
22406 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22407 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22408 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22409 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_MASK)
22410 /*! @} */
22411 
22412 /*! @name TXDQDLYTG3_R3_P2 - Write DQ Delay (Timing Group 3). */
22413 /*! @{ */
22414 
22415 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22416 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22417 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22418 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_MASK)
22419 /*! @} */
22420 
22421 /*! @name TXDQDLYTG0_R4_P2 - Write DQ Delay (Timing Group 0). */
22422 /*! @{ */
22423 
22424 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22425 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22426 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22427 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_MASK)
22428 /*! @} */
22429 
22430 /*! @name TXDQDLYTG1_R4_P2 - Write DQ Delay (Timing Group 1). */
22431 /*! @{ */
22432 
22433 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22434 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22435 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22436 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_MASK)
22437 /*! @} */
22438 
22439 /*! @name TXDQDLYTG2_R4_P2 - Write DQ Delay (Timing Group 2). */
22440 /*! @{ */
22441 
22442 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22443 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22444 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22445 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_MASK)
22446 /*! @} */
22447 
22448 /*! @name TXDQDLYTG3_R4_P2 - Write DQ Delay (Timing Group 3). */
22449 /*! @{ */
22450 
22451 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22452 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22453 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22454 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_MASK)
22455 /*! @} */
22456 
22457 /*! @name TXDQDLYTG0_R5_P2 - Write DQ Delay (Timing Group 0). */
22458 /*! @{ */
22459 
22460 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22461 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22462 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22463 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_MASK)
22464 /*! @} */
22465 
22466 /*! @name TXDQDLYTG1_R5_P2 - Write DQ Delay (Timing Group 1). */
22467 /*! @{ */
22468 
22469 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22470 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22471 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22472 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_MASK)
22473 /*! @} */
22474 
22475 /*! @name TXDQDLYTG2_R5_P2 - Write DQ Delay (Timing Group 2). */
22476 /*! @{ */
22477 
22478 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22479 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22480 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22481 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_MASK)
22482 /*! @} */
22483 
22484 /*! @name TXDQDLYTG3_R5_P2 - Write DQ Delay (Timing Group 3). */
22485 /*! @{ */
22486 
22487 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22488 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22489 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22490 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_MASK)
22491 /*! @} */
22492 
22493 /*! @name TXDQDLYTG0_R6_P2 - Write DQ Delay (Timing Group 0). */
22494 /*! @{ */
22495 
22496 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22497 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22498 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22499 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_MASK)
22500 /*! @} */
22501 
22502 /*! @name TXDQDLYTG1_R6_P2 - Write DQ Delay (Timing Group 1). */
22503 /*! @{ */
22504 
22505 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22506 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22507 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22508 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_MASK)
22509 /*! @} */
22510 
22511 /*! @name TXDQDLYTG2_R6_P2 - Write DQ Delay (Timing Group 2). */
22512 /*! @{ */
22513 
22514 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22515 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22516 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22517 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_MASK)
22518 /*! @} */
22519 
22520 /*! @name TXDQDLYTG3_R6_P2 - Write DQ Delay (Timing Group 3). */
22521 /*! @{ */
22522 
22523 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22524 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22525 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22526 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_MASK)
22527 /*! @} */
22528 
22529 /*! @name TXDQDLYTG0_R7_P2 - Write DQ Delay (Timing Group 0). */
22530 /*! @{ */
22531 
22532 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22533 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22534 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22535 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_MASK)
22536 /*! @} */
22537 
22538 /*! @name TXDQDLYTG1_R7_P2 - Write DQ Delay (Timing Group 1). */
22539 /*! @{ */
22540 
22541 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22542 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22543 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22544 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_MASK)
22545 /*! @} */
22546 
22547 /*! @name TXDQDLYTG2_R7_P2 - Write DQ Delay (Timing Group 2). */
22548 /*! @{ */
22549 
22550 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22551 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22552 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22553 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_MASK)
22554 /*! @} */
22555 
22556 /*! @name TXDQDLYTG3_R7_P2 - Write DQ Delay (Timing Group 3). */
22557 /*! @{ */
22558 
22559 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22560 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22561 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22562 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_MASK)
22563 /*! @} */
22564 
22565 /*! @name TXDQDLYTG0_R8_P2 - Write DQ Delay (Timing Group 0). */
22566 /*! @{ */
22567 
22568 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22569 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
22570 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22571 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_MASK)
22572 /*! @} */
22573 
22574 /*! @name TXDQDLYTG1_R8_P2 - Write DQ Delay (Timing Group 1). */
22575 /*! @{ */
22576 
22577 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22578 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
22579 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22580 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_MASK)
22581 /*! @} */
22582 
22583 /*! @name TXDQDLYTG2_R8_P2 - Write DQ Delay (Timing Group 2). */
22584 /*! @{ */
22585 
22586 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22587 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
22588 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22589 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_MASK)
22590 /*! @} */
22591 
22592 /*! @name TXDQDLYTG3_R8_P2 - Write DQ Delay (Timing Group 3). */
22593 /*! @{ */
22594 
22595 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22596 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
22597 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22598 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_MASK)
22599 /*! @} */
22600 
22601 /*! @name DFIMRL_P3 - DFI MaxReadLatency */
22602 /*! @{ */
22603 
22604 #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_MASK (0x1FU)
22605 #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_SHIFT (0U)
22606 /*! DFIMRL_p3 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
22607  *    until after all dbytes have their read data valid.
22608  */
22609 #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_MASK)
22610 /*! @} */
22611 
22612 /*! @name TXIMPEDANCECTRL0_B0_P3 - Data TX impedance controls */
22613 /*! @{ */
22614 
22615 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_MASK (0x3FU)
22616 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_SHIFT (0U)
22617 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22618  *    used to select the target pull down output impedance.
22619  */
22620 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_MASK)
22621 
22622 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_MASK (0xFC0U)
22623 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_SHIFT (6U)
22624 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22625  *    used to select the target pull down output impedance.
22626  */
22627 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_MASK)
22628 /*! @} */
22629 
22630 /*! @name DQDQSRCVCNTRL_B0_P3 - Dq/Dqs receiver control */
22631 /*! @{ */
22632 
22633 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_MASK (0x1U)
22634 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_SHIFT (0U)
22635 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
22636 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_MASK)
22637 
22638 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_MASK (0x2U)
22639 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_SHIFT (1U)
22640 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
22641 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_MASK)
22642 
22643 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_MASK (0xCU)
22644 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_SHIFT (2U)
22645 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
22646  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
22647  *    should not be overridden.
22648  */
22649 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_MASK)
22650 
22651 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_MASK (0x70U)
22652 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_SHIFT (4U)
22653 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
22654 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_MASK)
22655 
22656 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_MASK (0xF80U)
22657 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_SHIFT (7U)
22658 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
22659 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_MASK)
22660 /*! @} */
22661 
22662 /*! @name TXEQUALIZATIONMODE_P3 - Tx dq driver equalization mode controls. */
22663 /*! @{ */
22664 
22665 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_MASK (0x3U)
22666 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_SHIFT (0U)
22667 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_MASK)
22668 /*! @} */
22669 
22670 /*! @name TXIMPEDANCECTRL1_B0_P3 - TX impedance controls */
22671 /*! @{ */
22672 
22673 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_MASK (0x3FU)
22674 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_SHIFT (0U)
22675 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22676  *    used to select the target pull up output impedance used in equalization.
22677  */
22678 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_MASK)
22679 
22680 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_MASK (0xFC0U)
22681 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_SHIFT (6U)
22682 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22683  *    used to select the target pull up output impedance used in equalization.
22684  */
22685 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_MASK)
22686 /*! @} */
22687 
22688 /*! @name TXIMPEDANCECTRL2_B0_P3 - TX equalization impedance controls */
22689 /*! @{ */
22690 
22691 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_MASK (0x3FU)
22692 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_SHIFT (0U)
22693 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
22694  *    bus used to select the target pull up output impedance used in equalization.
22695  */
22696 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_MASK)
22697 
22698 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_MASK (0xFC0U)
22699 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_SHIFT (6U)
22700 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
22701  *    bus used to select the target pull down output impedance used in equalization.
22702  */
22703 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_MASK)
22704 /*! @} */
22705 
22706 /*! @name DQDQSRCVCNTRL2_P3 - Dq/Dqs receiver control */
22707 /*! @{ */
22708 
22709 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_MASK (0x1U)
22710 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_SHIFT (0U)
22711 /*! EnRxAgressivePDR - reserved */
22712 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_MASK)
22713 /*! @} */
22714 
22715 /*! @name TXODTDRVSTREN_B0_P3 - TX ODT driver strength control */
22716 /*! @{ */
22717 
22718 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_MASK (0x3FU)
22719 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_SHIFT (0U)
22720 /*! ODTStrenP - Selects the ODT pull-up impedance. */
22721 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_MASK)
22722 
22723 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_MASK (0xFC0U)
22724 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_SHIFT (6U)
22725 /*! ODTStrenN - Selects the ODT pull-down impedance. */
22726 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_MASK)
22727 /*! @} */
22728 
22729 /*! @name TXSLEWRATE_B0_P3 - TX slew rate controls */
22730 /*! @{ */
22731 
22732 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_MASK (0xFU)
22733 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_SHIFT (0U)
22734 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
22735 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_MASK)
22736 
22737 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_MASK (0xF0U)
22738 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_SHIFT (4U)
22739 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
22740 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_MASK)
22741 
22742 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_MASK (0x700U)
22743 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_SHIFT (8U)
22744 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
22745 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_MASK)
22746 /*! @} */
22747 
22748 /*! @name RXENDLYTG0_U0_P3 - Trained Receive Enable Delay (For Timing Group 0) */
22749 /*! @{ */
22750 
22751 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_MASK (0x7FFU)
22752 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_SHIFT (0U)
22753 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
22754  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22755  */
22756 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_MASK)
22757 /*! @} */
22758 
22759 /*! @name RXENDLYTG1_U0_P3 - Trained Receive Enable Delay (For Timing Group 1) */
22760 /*! @{ */
22761 
22762 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_MASK (0x7FFU)
22763 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_SHIFT (0U)
22764 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
22765  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22766  */
22767 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_MASK)
22768 /*! @} */
22769 
22770 /*! @name RXENDLYTG2_U0_P3 - Trained Receive Enable Delay (For Timing Group 2) */
22771 /*! @{ */
22772 
22773 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_MASK (0x7FFU)
22774 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_SHIFT (0U)
22775 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
22776  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22777  */
22778 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_MASK)
22779 /*! @} */
22780 
22781 /*! @name RXENDLYTG3_U0_P3 - Trained Receive Enable Delay (For Timing Group 3) */
22782 /*! @{ */
22783 
22784 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_MASK (0x7FFU)
22785 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_SHIFT (0U)
22786 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
22787  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
22788  */
22789 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_MASK)
22790 /*! @} */
22791 
22792 /*! @name RXCLKDLYTG0_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
22793 /*! @{ */
22794 
22795 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
22796 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_SHIFT (0U)
22797 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
22798 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_MASK)
22799 /*! @} */
22800 
22801 /*! @name RXCLKDLYTG1_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
22802 /*! @{ */
22803 
22804 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
22805 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_SHIFT (0U)
22806 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
22807 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_MASK)
22808 /*! @} */
22809 
22810 /*! @name RXCLKDLYTG2_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
22811 /*! @{ */
22812 
22813 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
22814 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_SHIFT (0U)
22815 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
22816 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_MASK)
22817 /*! @} */
22818 
22819 /*! @name RXCLKDLYTG3_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
22820 /*! @{ */
22821 
22822 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
22823 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_SHIFT (0U)
22824 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
22825 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_MASK)
22826 /*! @} */
22827 
22828 /*! @name RXCLKCDLYTG0_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
22829 /*! @{ */
22830 
22831 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
22832 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
22833 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
22834 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_MASK)
22835 /*! @} */
22836 
22837 /*! @name RXCLKCDLYTG1_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
22838 /*! @{ */
22839 
22840 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
22841 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
22842 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
22843 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_MASK)
22844 /*! @} */
22845 
22846 /*! @name RXCLKCDLYTG2_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
22847 /*! @{ */
22848 
22849 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
22850 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
22851 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
22852 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_MASK)
22853 /*! @} */
22854 
22855 /*! @name RXCLKCDLYTG3_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
22856 /*! @{ */
22857 
22858 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
22859 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
22860 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
22861 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_MASK)
22862 /*! @} */
22863 
22864 /*! @name PPTDQSCNTINVTRNTG0_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
22865 /*! @{ */
22866 
22867 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_MASK (0xFFFFU)
22868 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_SHIFT (0U)
22869 /*! PptDqsCntInvTrnTg0_p3 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation. */
22870 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_MASK)
22871 /*! @} */
22872 
22873 /*! @name PPTDQSCNTINVTRNTG1_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
22874 /*! @{ */
22875 
22876 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_MASK (0xFFFFU)
22877 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_SHIFT (0U)
22878 /*! PptDqsCntInvTrnTg1_p3 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation. */
22879 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_MASK)
22880 /*! @} */
22881 
22882 /*! @name TXDQDLYTG0_R0_P3 - Write DQ Delay (Timing Group 0). */
22883 /*! @{ */
22884 
22885 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
22886 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
22887 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
22888 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_MASK)
22889 /*! @} */
22890 
22891 /*! @name TXDQDLYTG1_R0_P3 - Write DQ Delay (Timing Group 1). */
22892 /*! @{ */
22893 
22894 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
22895 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
22896 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
22897 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_MASK)
22898 /*! @} */
22899 
22900 /*! @name TXDQDLYTG2_R0_P3 - Write DQ Delay (Timing Group 2). */
22901 /*! @{ */
22902 
22903 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
22904 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
22905 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
22906 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_MASK)
22907 /*! @} */
22908 
22909 /*! @name TXDQDLYTG3_R0_P3 - Write DQ Delay (Timing Group 3). */
22910 /*! @{ */
22911 
22912 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
22913 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
22914 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
22915 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_MASK)
22916 /*! @} */
22917 
22918 /*! @name TXDQSDLYTG0_U0_P3 - Write DQS Delay (Timing Group DEST=0). */
22919 /*! @{ */
22920 
22921 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
22922 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_SHIFT (0U)
22923 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
22924 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_MASK)
22925 /*! @} */
22926 
22927 /*! @name TXDQSDLYTG1_U0_P3 - Write DQS Delay (Timing Group DEST=1). */
22928 /*! @{ */
22929 
22930 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
22931 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_SHIFT (0U)
22932 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
22933 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_MASK)
22934 /*! @} */
22935 
22936 /*! @name TXDQSDLYTG2_U0_P3 - Write DQS Delay (Timing Group DEST=2). */
22937 /*! @{ */
22938 
22939 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
22940 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_SHIFT (0U)
22941 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
22942 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_MASK)
22943 /*! @} */
22944 
22945 /*! @name TXDQSDLYTG3_U0_P3 - Write DQS Delay (Timing Group DEST=3). */
22946 /*! @{ */
22947 
22948 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
22949 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_SHIFT (0U)
22950 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
22951 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_MASK)
22952 /*! @} */
22953 
22954 /*! @name TXIMPEDANCECTRL0_B1_P3 - Data TX impedance controls */
22955 /*! @{ */
22956 
22957 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_MASK (0x3FU)
22958 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_SHIFT (0U)
22959 /*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22960  *    used to select the target pull down output impedance.
22961  */
22962 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_MASK)
22963 
22964 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_MASK (0xFC0U)
22965 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_SHIFT (6U)
22966 /*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
22967  *    used to select the target pull down output impedance.
22968  */
22969 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_MASK)
22970 /*! @} */
22971 
22972 /*! @name DQDQSRCVCNTRL_B1_P3 - Dq/Dqs receiver control */
22973 /*! @{ */
22974 
22975 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_MASK (0x1U)
22976 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_SHIFT (0U)
22977 /*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers. */
22978 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_MASK)
22979 
22980 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_MASK (0x2U)
22981 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_SHIFT (1U)
22982 /*! ExtVrefRange - Extends the range available in the local per-bit VREF generator. */
22983 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_MASK)
22984 
22985 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_MASK (0xCU)
22986 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_SHIFT (2U)
22987 /*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
22988  *    Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
22989  *    should not be overridden.
22990  */
22991 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_MASK)
22992 
22993 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_MASK (0x70U)
22994 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_SHIFT (4U)
22995 /*! MajorModeDbyte - Selects the major mode of operation for the receiver. */
22996 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_MASK)
22997 
22998 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_MASK (0xF80U)
22999 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_SHIFT (7U)
23000 /*! GainCurrAdj - Adjust gain current of RX amplifier stage. */
23001 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_MASK)
23002 /*! @} */
23003 
23004 /*! @name TXIMPEDANCECTRL1_B1_P3 - TX impedance controls */
23005 /*! @{ */
23006 
23007 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_MASK (0x3FU)
23008 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_SHIFT (0U)
23009 /*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
23010  *    used to select the target pull up output impedance used in equalization.
23011  */
23012 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_MASK)
23013 
23014 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_MASK (0xFC0U)
23015 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_SHIFT (6U)
23016 /*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
23017  *    used to select the target pull up output impedance used in equalization.
23018  */
23019 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_MASK)
23020 /*! @} */
23021 
23022 /*! @name TXIMPEDANCECTRL2_B1_P3 - TX equalization impedance controls */
23023 /*! @{ */
23024 
23025 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_MASK (0x3FU)
23026 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_SHIFT (0U)
23027 /*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
23028  *    bus used to select the target pull up output impedance used in equalization.
23029  */
23030 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_MASK)
23031 
23032 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_MASK (0xFC0U)
23033 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_SHIFT (6U)
23034 /*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
23035  *    bus used to select the target pull down output impedance used in equalization.
23036  */
23037 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_MASK)
23038 /*! @} */
23039 
23040 /*! @name TXODTDRVSTREN_B1_P3 - TX ODT driver strength control */
23041 /*! @{ */
23042 
23043 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_MASK (0x3FU)
23044 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_SHIFT (0U)
23045 /*! ODTStrenP - Selects the ODT pull-up impedance. */
23046 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_MASK)
23047 
23048 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_MASK (0xFC0U)
23049 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_SHIFT (6U)
23050 /*! ODTStrenN - Selects the ODT pull-down impedance. */
23051 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_MASK)
23052 /*! @} */
23053 
23054 /*! @name TXSLEWRATE_B1_P3 - TX slew rate controls */
23055 /*! @{ */
23056 
23057 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_MASK (0xFU)
23058 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_SHIFT (0U)
23059 /*! TxPreP - 4 bit binary trim for the driver pull up slew rate. */
23060 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_MASK)
23061 
23062 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_MASK (0xF0U)
23063 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_SHIFT (4U)
23064 /*! TxPreN - 4 bit binary trim for the driver pull down slew rate. */
23065 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_MASK)
23066 
23067 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_MASK (0x700U)
23068 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_SHIFT (8U)
23069 /*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments. */
23070 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_MASK)
23071 /*! @} */
23072 
23073 /*! @name RXENDLYTG0_U1_P3 - Trained Receive Enable Delay (For Timing Group 0) */
23074 /*! @{ */
23075 
23076 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_MASK (0x7FFU)
23077 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_SHIFT (0U)
23078 /*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
23079  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
23080  */
23081 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_MASK)
23082 /*! @} */
23083 
23084 /*! @name RXENDLYTG1_U1_P3 - Trained Receive Enable Delay (For Timing Group 1) */
23085 /*! @{ */
23086 
23087 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_MASK (0x7FFU)
23088 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_SHIFT (0U)
23089 /*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
23090  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
23091  */
23092 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_MASK)
23093 /*! @} */
23094 
23095 /*! @name RXENDLYTG2_U1_P3 - Trained Receive Enable Delay (For Timing Group 2) */
23096 /*! @{ */
23097 
23098 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_MASK (0x7FFU)
23099 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_SHIFT (0U)
23100 /*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
23101  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
23102  */
23103 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_MASK)
23104 /*! @} */
23105 
23106 /*! @name RXENDLYTG3_U1_P3 - Trained Receive Enable Delay (For Timing Group 3) */
23107 /*! @{ */
23108 
23109 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_MASK (0x7FFU)
23110 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_SHIFT (0U)
23111 /*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
23112  *    from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
23113  */
23114 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_MASK)
23115 /*! @} */
23116 
23117 /*! @name RXCLKDLYTG0_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
23118 /*! @{ */
23119 
23120 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
23121 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_SHIFT (0U)
23122 /*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
23123 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_MASK)
23124 /*! @} */
23125 
23126 /*! @name RXCLKDLYTG1_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
23127 /*! @{ */
23128 
23129 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
23130 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_SHIFT (0U)
23131 /*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
23132 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_MASK)
23133 /*! @} */
23134 
23135 /*! @name RXCLKDLYTG2_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
23136 /*! @{ */
23137 
23138 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
23139 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_SHIFT (0U)
23140 /*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
23141 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_MASK)
23142 /*! @} */
23143 
23144 /*! @name RXCLKDLYTG3_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
23145 /*! @{ */
23146 
23147 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
23148 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_SHIFT (0U)
23149 /*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
23150 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_MASK)
23151 /*! @} */
23152 
23153 /*! @name RXCLKCDLYTG0_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
23154 /*! @{ */
23155 
23156 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
23157 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
23158 /*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
23159 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_MASK)
23160 /*! @} */
23161 
23162 /*! @name RXCLKCDLYTG1_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
23163 /*! @{ */
23164 
23165 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
23166 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
23167 /*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1). */
23168 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_MASK)
23169 /*! @} */
23170 
23171 /*! @name RXCLKCDLYTG2_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
23172 /*! @{ */
23173 
23174 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
23175 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
23176 /*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
23177 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_MASK)
23178 /*! @} */
23179 
23180 /*! @name RXCLKCDLYTG3_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
23181 /*! @{ */
23182 
23183 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
23184 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
23185 /*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
23186 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_MASK)
23187 /*! @} */
23188 
23189 /*! @name TXDQDLYTG0_R1_P3 - Write DQ Delay (Timing Group 0). */
23190 /*! @{ */
23191 
23192 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23193 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23194 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23195 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_MASK)
23196 /*! @} */
23197 
23198 /*! @name TXDQDLYTG1_R1_P3 - Write DQ Delay (Timing Group 1). */
23199 /*! @{ */
23200 
23201 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23202 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23203 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23204 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_MASK)
23205 /*! @} */
23206 
23207 /*! @name TXDQDLYTG2_R1_P3 - Write DQ Delay (Timing Group 2). */
23208 /*! @{ */
23209 
23210 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23211 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23212 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23213 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_MASK)
23214 /*! @} */
23215 
23216 /*! @name TXDQDLYTG3_R1_P3 - Write DQ Delay (Timing Group 3). */
23217 /*! @{ */
23218 
23219 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23220 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23221 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23222 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_MASK)
23223 /*! @} */
23224 
23225 /*! @name TXDQSDLYTG0_U1_P3 - Write DQS Delay (Timing Group DEST=0). */
23226 /*! @{ */
23227 
23228 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
23229 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_SHIFT (0U)
23230 /*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0). */
23231 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_MASK)
23232 /*! @} */
23233 
23234 /*! @name TXDQSDLYTG1_U1_P3 - Write DQS Delay (Timing Group DEST=1). */
23235 /*! @{ */
23236 
23237 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
23238 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_SHIFT (0U)
23239 /*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1). */
23240 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_MASK)
23241 /*! @} */
23242 
23243 /*! @name TXDQSDLYTG2_U1_P3 - Write DQS Delay (Timing Group DEST=2). */
23244 /*! @{ */
23245 
23246 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
23247 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_SHIFT (0U)
23248 /*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2). */
23249 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_MASK)
23250 /*! @} */
23251 
23252 /*! @name TXDQSDLYTG3_U1_P3 - Write DQS Delay (Timing Group DEST=3). */
23253 /*! @{ */
23254 
23255 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
23256 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_SHIFT (0U)
23257 /*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3). */
23258 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_MASK)
23259 /*! @} */
23260 
23261 /*! @name TXDQDLYTG0_R2_P3 - Write DQ Delay (Timing Group 0). */
23262 /*! @{ */
23263 
23264 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23265 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23266 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23267 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_MASK)
23268 /*! @} */
23269 
23270 /*! @name TXDQDLYTG1_R2_P3 - Write DQ Delay (Timing Group 1). */
23271 /*! @{ */
23272 
23273 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23274 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23275 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23276 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_MASK)
23277 /*! @} */
23278 
23279 /*! @name TXDQDLYTG2_R2_P3 - Write DQ Delay (Timing Group 2). */
23280 /*! @{ */
23281 
23282 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23283 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23284 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23285 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_MASK)
23286 /*! @} */
23287 
23288 /*! @name TXDQDLYTG3_R2_P3 - Write DQ Delay (Timing Group 3). */
23289 /*! @{ */
23290 
23291 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23292 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23293 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23294 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_MASK)
23295 /*! @} */
23296 
23297 /*! @name TXDQDLYTG0_R3_P3 - Write DQ Delay (Timing Group 0). */
23298 /*! @{ */
23299 
23300 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23301 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23302 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23303 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_MASK)
23304 /*! @} */
23305 
23306 /*! @name TXDQDLYTG1_R3_P3 - Write DQ Delay (Timing Group 1). */
23307 /*! @{ */
23308 
23309 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23310 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23311 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23312 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_MASK)
23313 /*! @} */
23314 
23315 /*! @name TXDQDLYTG2_R3_P3 - Write DQ Delay (Timing Group 2). */
23316 /*! @{ */
23317 
23318 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23319 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23320 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23321 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_MASK)
23322 /*! @} */
23323 
23324 /*! @name TXDQDLYTG3_R3_P3 - Write DQ Delay (Timing Group 3). */
23325 /*! @{ */
23326 
23327 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23328 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23329 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23330 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_MASK)
23331 /*! @} */
23332 
23333 /*! @name TXDQDLYTG0_R4_P3 - Write DQ Delay (Timing Group 0). */
23334 /*! @{ */
23335 
23336 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23337 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23338 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23339 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_MASK)
23340 /*! @} */
23341 
23342 /*! @name TXDQDLYTG1_R4_P3 - Write DQ Delay (Timing Group 1). */
23343 /*! @{ */
23344 
23345 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23346 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23347 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23348 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_MASK)
23349 /*! @} */
23350 
23351 /*! @name TXDQDLYTG2_R4_P3 - Write DQ Delay (Timing Group 2). */
23352 /*! @{ */
23353 
23354 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23355 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23356 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23357 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_MASK)
23358 /*! @} */
23359 
23360 /*! @name TXDQDLYTG3_R4_P3 - Write DQ Delay (Timing Group 3). */
23361 /*! @{ */
23362 
23363 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23364 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23365 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23366 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_MASK)
23367 /*! @} */
23368 
23369 /*! @name TXDQDLYTG0_R5_P3 - Write DQ Delay (Timing Group 0). */
23370 /*! @{ */
23371 
23372 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23373 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23374 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23375 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_MASK)
23376 /*! @} */
23377 
23378 /*! @name TXDQDLYTG1_R5_P3 - Write DQ Delay (Timing Group 1). */
23379 /*! @{ */
23380 
23381 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23382 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23383 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23384 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_MASK)
23385 /*! @} */
23386 
23387 /*! @name TXDQDLYTG2_R5_P3 - Write DQ Delay (Timing Group 2). */
23388 /*! @{ */
23389 
23390 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23391 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23392 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23393 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_MASK)
23394 /*! @} */
23395 
23396 /*! @name TXDQDLYTG3_R5_P3 - Write DQ Delay (Timing Group 3). */
23397 /*! @{ */
23398 
23399 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23400 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23401 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23402 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_MASK)
23403 /*! @} */
23404 
23405 /*! @name TXDQDLYTG0_R6_P3 - Write DQ Delay (Timing Group 0). */
23406 /*! @{ */
23407 
23408 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23409 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23410 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23411 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_MASK)
23412 /*! @} */
23413 
23414 /*! @name TXDQDLYTG1_R6_P3 - Write DQ Delay (Timing Group 1). */
23415 /*! @{ */
23416 
23417 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23418 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23419 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23420 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_MASK)
23421 /*! @} */
23422 
23423 /*! @name TXDQDLYTG2_R6_P3 - Write DQ Delay (Timing Group 2). */
23424 /*! @{ */
23425 
23426 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23427 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23428 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23429 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_MASK)
23430 /*! @} */
23431 
23432 /*! @name TXDQDLYTG3_R6_P3 - Write DQ Delay (Timing Group 3). */
23433 /*! @{ */
23434 
23435 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23436 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23437 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23438 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_MASK)
23439 /*! @} */
23440 
23441 /*! @name TXDQDLYTG0_R7_P3 - Write DQ Delay (Timing Group 0). */
23442 /*! @{ */
23443 
23444 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23445 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23446 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23447 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_MASK)
23448 /*! @} */
23449 
23450 /*! @name TXDQDLYTG1_R7_P3 - Write DQ Delay (Timing Group 1). */
23451 /*! @{ */
23452 
23453 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23454 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23455 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23456 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_MASK)
23457 /*! @} */
23458 
23459 /*! @name TXDQDLYTG2_R7_P3 - Write DQ Delay (Timing Group 2). */
23460 /*! @{ */
23461 
23462 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23463 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23464 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23465 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_MASK)
23466 /*! @} */
23467 
23468 /*! @name TXDQDLYTG3_R7_P3 - Write DQ Delay (Timing Group 3). */
23469 /*! @{ */
23470 
23471 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23472 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23473 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23474 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_MASK)
23475 /*! @} */
23476 
23477 /*! @name TXDQDLYTG0_R8_P3 - Write DQ Delay (Timing Group 0). */
23478 /*! @{ */
23479 
23480 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
23481 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
23482 /*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0). */
23483 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_MASK)
23484 /*! @} */
23485 
23486 /*! @name TXDQDLYTG1_R8_P3 - Write DQ Delay (Timing Group 1). */
23487 /*! @{ */
23488 
23489 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
23490 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
23491 /*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1). */
23492 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_MASK)
23493 /*! @} */
23494 
23495 /*! @name TXDQDLYTG2_R8_P3 - Write DQ Delay (Timing Group 2). */
23496 /*! @{ */
23497 
23498 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
23499 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
23500 /*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2). */
23501 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_MASK)
23502 /*! @} */
23503 
23504 /*! @name TXDQDLYTG3_R8_P3 - Write DQ Delay (Timing Group 3). */
23505 /*! @{ */
23506 
23507 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
23508 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
23509 /*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3). */
23510 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_MASK)
23511 /*! @} */
23512 
23513 
23514 /*!
23515  * @}
23516  */ /* end of group DWC_DDRPHYA_DBYTE_Register_Masks */
23517 
23518 
23519 /* DWC_DDRPHYA_DBYTE - Peripheral instance base addresses */
23520 /** Peripheral DWC_DDRPHYA_DBYTE0 base address */
23521 #define DWC_DDRPHYA_DBYTE0_BASE                  (0x3C010000u)
23522 /** Peripheral DWC_DDRPHYA_DBYTE0 base pointer */
23523 #define DWC_DDRPHYA_DBYTE0                       ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE0_BASE)
23524 /** Peripheral DWC_DDRPHYA_DBYTE1 base address */
23525 #define DWC_DDRPHYA_DBYTE1_BASE                  (0x3C011000u)
23526 /** Peripheral DWC_DDRPHYA_DBYTE1 base pointer */
23527 #define DWC_DDRPHYA_DBYTE1                       ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE1_BASE)
23528 /** Peripheral DWC_DDRPHYA_DBYTE2 base address */
23529 #define DWC_DDRPHYA_DBYTE2_BASE                  (0x3C012000u)
23530 /** Peripheral DWC_DDRPHYA_DBYTE2 base pointer */
23531 #define DWC_DDRPHYA_DBYTE2                       ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE2_BASE)
23532 /** Peripheral DWC_DDRPHYA_DBYTE3 base address */
23533 #define DWC_DDRPHYA_DBYTE3_BASE                  (0x3C013000u)
23534 /** Peripheral DWC_DDRPHYA_DBYTE3 base pointer */
23535 #define DWC_DDRPHYA_DBYTE3                       ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE3_BASE)
23536 /** Array initializer of DWC_DDRPHYA_DBYTE peripheral base addresses */
23537 #define DWC_DDRPHYA_DBYTE_BASE_ADDRS             { DWC_DDRPHYA_DBYTE0_BASE, DWC_DDRPHYA_DBYTE1_BASE, DWC_DDRPHYA_DBYTE2_BASE, DWC_DDRPHYA_DBYTE3_BASE }
23538 /** Array initializer of DWC_DDRPHYA_DBYTE peripheral base pointers */
23539 #define DWC_DDRPHYA_DBYTE_BASE_PTRS              { DWC_DDRPHYA_DBYTE0, DWC_DDRPHYA_DBYTE1, DWC_DDRPHYA_DBYTE2, DWC_DDRPHYA_DBYTE3 }
23540 
23541 /*!
23542  * @}
23543  */ /* end of group DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer */
23544 
23545 
23546 /* ----------------------------------------------------------------------------
23547    -- DWC_DDRPHYA_DRTUB Peripheral Access Layer
23548    ---------------------------------------------------------------------------- */
23549 
23550 /*!
23551  * @addtogroup DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer DWC_DDRPHYA_DRTUB Peripheral Access Layer
23552  * @{
23553  */
23554 
23555 /** DWC_DDRPHYA_DRTUB - Register Layout Typedef */
23556 typedef struct {
23557        uint8_t RESERVED_0[256];
23558   __IO uint16_t UCCLKHCLKENABLES;                  /**< Ucclk and Hclk enables, offset: 0x100 */
23559   __IO uint16_t CURPSTATE0B;                       /**< PIE current Pstate value, offset: 0x102 */
23560        uint8_t RESERVED_1[214];
23561   __I  uint16_t CUSTPUBREV;                        /**< Customer settable by the customer, offset: 0x1DA */
23562   __I  uint16_t PUBREV;                            /**< The hardware version of this PUB, excluding the PHY, offset: 0x1DC */
23563 } DWC_DDRPHYA_DRTUB_Type;
23564 
23565 /* ----------------------------------------------------------------------------
23566    -- DWC_DDRPHYA_DRTUB Register Masks
23567    ---------------------------------------------------------------------------- */
23568 
23569 /*!
23570  * @addtogroup DWC_DDRPHYA_DRTUB_Register_Masks DWC_DDRPHYA_DRTUB Register Masks
23571  * @{
23572  */
23573 
23574 /*! @name UCCLKHCLKENABLES - Ucclk and Hclk enables */
23575 /*! @{ */
23576 
23577 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_MASK (0x1U)
23578 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_SHIFT (0U)
23579 /*! UcclkEn - When training has completed (and assuming no further need for the microcontroller),
23580  *    the enable should be set to 0 to reduce power.
23581  */
23582 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_SHIFT)) & DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_MASK)
23583 
23584 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_MASK (0x2U)
23585 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_SHIFT (1U)
23586 /*! HclkEn - When training has completed (and assuming no further need for the training hardware),
23587  *    the enable should be set to 0 to reduce power.
23588  */
23589 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_SHIFT)) & DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_MASK)
23590 /*! @} */
23591 
23592 /*! @name CURPSTATE0B - PIE current Pstate value */
23593 /*! @{ */
23594 
23595 #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_MASK (0xFU)
23596 #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_SHIFT (0U)
23597 /*! CurPstate0b - PIE current Pstate value This register is used to select values for writing by the
23598  *    Pstate sequencer and is written in the beginning of the Pstate switch.
23599  */
23600 #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_SHIFT)) & DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_MASK)
23601 /*! @} */
23602 
23603 /*! @name CUSTPUBREV - Customer settable by the customer */
23604 /*! @{ */
23605 
23606 #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK (0x3FU)
23607 #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT (0U)
23608 /*! CUSTPUBREV - The customer settable PUB version number. */
23609 #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT)) & DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK)
23610 /*! @} */
23611 
23612 /*! @name PUBREV - The hardware version of this PUB, excluding the PHY */
23613 /*! @{ */
23614 
23615 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK     (0xFU)
23616 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT    (0U)
23617 /*! PUBMNR - Indicates minor update of the PUB. */
23618 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x)       (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK)
23619 
23620 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK     (0xF0U)
23621 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT    (4U)
23622 /*! PUBMDR - Indicates moderate revision of the PUB. */
23623 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x)       (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK)
23624 
23625 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK     (0xFF00U)
23626 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT    (8U)
23627 /*! PUBMJR - Indicates major revision of the PUB. */
23628 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x)       (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK)
23629 /*! @} */
23630 
23631 
23632 /*!
23633  * @}
23634  */ /* end of group DWC_DDRPHYA_DRTUB_Register_Masks */
23635 
23636 
23637 /* DWC_DDRPHYA_DRTUB - Peripheral instance base addresses */
23638 /** Peripheral DWC_DDRPHYA_DRTUB0 base address */
23639 #define DWC_DDRPHYA_DRTUB0_BASE                  (0x3C0C0000u)
23640 /** Peripheral DWC_DDRPHYA_DRTUB0 base pointer */
23641 #define DWC_DDRPHYA_DRTUB0                       ((DWC_DDRPHYA_DRTUB_Type *)DWC_DDRPHYA_DRTUB0_BASE)
23642 /** Array initializer of DWC_DDRPHYA_DRTUB peripheral base addresses */
23643 #define DWC_DDRPHYA_DRTUB_BASE_ADDRS             { DWC_DDRPHYA_DRTUB0_BASE }
23644 /** Array initializer of DWC_DDRPHYA_DRTUB peripheral base pointers */
23645 #define DWC_DDRPHYA_DRTUB_BASE_PTRS              { DWC_DDRPHYA_DRTUB0 }
23646 
23647 /*!
23648  * @}
23649  */ /* end of group DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer */
23650 
23651 
23652 /* ----------------------------------------------------------------------------
23653    -- DWC_DDRPHYA_INITENG Peripheral Access Layer
23654    ---------------------------------------------------------------------------- */
23655 
23656 /*!
23657  * @addtogroup DWC_DDRPHYA_INITENG_Peripheral_Access_Layer DWC_DDRPHYA_INITENG Peripheral Access Layer
23658  * @{
23659  */
23660 
23661 /** DWC_DDRPHYA_INITENG - Register Layout Typedef */
23662 typedef struct {
23663        uint8_t RESERVED_0[80];
23664   __IO uint16_t PHYINLP3;                          /**< Indicator for PIE Lower Power 3 (LP3) Status, offset: 0x50 */
23665 } DWC_DDRPHYA_INITENG_Type;
23666 
23667 /* ----------------------------------------------------------------------------
23668    -- DWC_DDRPHYA_INITENG Register Masks
23669    ---------------------------------------------------------------------------- */
23670 
23671 /*!
23672  * @addtogroup DWC_DDRPHYA_INITENG_Register_Masks DWC_DDRPHYA_INITENG Register Masks
23673  * @{
23674  */
23675 
23676 /*! @name PHYINLP3 - Indicator for PIE Lower Power 3 (LP3) Status */
23677 /*! @{ */
23678 
23679 #define DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_MASK (0x1U)
23680 #define DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_SHIFT (0U)
23681 /*! PhyInLP3 - Read Only. */
23682 #define DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_SHIFT)) & DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_MASK)
23683 /*! @} */
23684 
23685 
23686 /*!
23687  * @}
23688  */ /* end of group DWC_DDRPHYA_INITENG_Register_Masks */
23689 
23690 
23691 /* DWC_DDRPHYA_INITENG - Peripheral instance base addresses */
23692 /** Peripheral DWC_DDRPHYA_INITENG0 base address */
23693 #define DWC_DDRPHYA_INITENG0_BASE                (0x3C090000u)
23694 /** Peripheral DWC_DDRPHYA_INITENG0 base pointer */
23695 #define DWC_DDRPHYA_INITENG0                     ((DWC_DDRPHYA_INITENG_Type *)DWC_DDRPHYA_INITENG0_BASE)
23696 /** Array initializer of DWC_DDRPHYA_INITENG peripheral base addresses */
23697 #define DWC_DDRPHYA_INITENG_BASE_ADDRS           { DWC_DDRPHYA_INITENG0_BASE }
23698 /** Array initializer of DWC_DDRPHYA_INITENG peripheral base pointers */
23699 #define DWC_DDRPHYA_INITENG_BASE_PTRS            { DWC_DDRPHYA_INITENG0 }
23700 
23701 /*!
23702  * @}
23703  */ /* end of group DWC_DDRPHYA_INITENG_Peripheral_Access_Layer */
23704 
23705 
23706 /* ----------------------------------------------------------------------------
23707    -- DWC_DDRPHYA_MASTER Peripheral Access Layer
23708    ---------------------------------------------------------------------------- */
23709 
23710 /*!
23711  * @addtogroup DWC_DDRPHYA_MASTER_Peripheral_Access_Layer DWC_DDRPHYA_MASTER Peripheral Access Layer
23712  * @{
23713  */
23714 
23715 /** DWC_DDRPHYA_MASTER - Register Layout Typedef */
23716 typedef struct {
23717   __IO uint16_t RXFIFOINIT;                        /**< Rx FIFO pointer initialization control, offset: 0x0 */
23718   __IO uint16_t FORCECLKDISABLE;                   /**< Clock gating control, offset: 0x2 */
23719        uint8_t RESERVED_0[2];
23720   __IO uint16_t FORCEINTERNALUPDATE;               /**< This Register used by Training Firmware to force an internal PHY Update Event., offset: 0x6 */
23721   __I  uint16_t PHYCONFIG;                         /**< Read Only displays PHY Configuration., offset: 0x8 */
23722   __IO uint16_t PGCR;                              /**< PHY General Configuration Register(PGCR)., offset: 0xA */
23723        uint8_t RESERVED_1[2];
23724   __IO uint16_t TESTBUMPCNTRL1;                    /**< Test Bump Control1, offset: 0xE */
23725   __IO uint16_t CALUCLKINFO_P0;                    /**< Impedance Calibration Clock Ratio, offset: 0x10 */
23726        uint8_t RESERVED_2[2];
23727   __IO uint16_t TESTBUMPCNTRL;                     /**< Test Bump Control, offset: 0x14 */
23728   __IO uint16_t SEQ0BDLY0_P0;                      /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x16 */
23729   __IO uint16_t SEQ0BDLY1_P0;                      /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x18 */
23730   __IO uint16_t SEQ0BDLY2_P0;                      /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x1A */
23731   __IO uint16_t SEQ0BDLY3_P0;                      /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x1C */
23732   __I  uint16_t PHYALERTSTATUS;                    /**< PHY Alert status bit, offset: 0x1E */
23733   __IO uint16_t PPTTRAINSETUP_P0;                  /**< Setup Intervals for DFI PHY Master operations, offset: 0x20 */
23734        uint8_t RESERVED_3[2];
23735   __IO uint16_t ATESTMODE;                         /**< ATestMode control, offset: 0x24 */
23736        uint8_t RESERVED_4[2];
23737   __I  uint16_t TXCALBINP;                         /**< TX P Impedance Calibration observation, offset: 0x28 */
23738   __I  uint16_t TXCALBINN;                         /**< TX N Impedance Calibration observation, offset: 0x2A */
23739   __IO uint16_t TXCALPOVR;                         /**< TX P Impedance Calibration override, offset: 0x2C */
23740   __IO uint16_t TXCALNOVR;                         /**< TX N Impedance Calibration override, offset: 0x2E */
23741   __IO uint16_t DFIMODE;                           /**< Enables for update and low-power interfaces for DFI0 and DFI1, offset: 0x30 */
23742   __IO uint16_t TRISTATEMODECA_P0;                 /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x32 */
23743   __IO uint16_t MTESTMUXSEL;                       /**< Digital Observation Pin control, offset: 0x34 */
23744   __IO uint16_t MTESTPGMINFO;                      /**< Digital Observation Pin program info for debug, offset: 0x36 */
23745   __IO uint16_t DYNPWRDNUP;                        /**< Dynaimc Power Up/Down control, offset: 0x38 */
23746        uint8_t RESERVED_5[2];
23747   __IO uint16_t PHYTID;                            /**< PHY Technology ID Register, offset: 0x3C */
23748        uint8_t RESERVED_6[2];
23749   __IO uint16_t HWTMRL_P0;                         /**< HWT MaxReadLatency., offset: 0x40 */
23750   __IO uint16_t DFIPHYUPD;                         /**< DFI PhyUpdate Request time counter (in MEMCLKs), offset: 0x42 */
23751   __IO uint16_t PDAMRSWRITEMODE;                   /**< Controls the write DQ generation for Per-Dram-Addressing of MRS, offset: 0x44 */
23752   __IO uint16_t DFIGEARDOWNCTL;                    /**< Controls whether dfi_geardown_en will cause CS and CKE timing to change., offset: 0x46 */
23753   __IO uint16_t DQSPREAMBLECONTROL_P0;             /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x48 */
23754   __IO uint16_t MASTERX4CONFIG;                    /**< DBYTE module controls to select X4 Dram device mode, offset: 0x4A */
23755   __IO uint16_t WRLEVBITS;                         /**< Write level feedback DQ observability select., offset: 0x4C */
23756   __IO uint16_t ENABLECSMULTICAST;                 /**< In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0], offset: 0x4E */
23757   __IO uint16_t HWTLPCSMULTICAST;                  /**< Drives cs_n[0] onto cs_n[1] during training, offset: 0x50 */
23758        uint8_t RESERVED_7[6];
23759   __IO uint16_t ACX4ANIBDIS;                       /**< Disable for unused ACX Nibbles, offset: 0x58 */
23760   __IO uint16_t DMIPINPRESENT_P0;                  /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x5A */
23761   __IO uint16_t ARDPTRINITVAL_P0;                  /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x5C */
23762        uint8_t RESERVED_8[22];
23763   __IO uint16_t DBYTEDLLMODECNTRL;                 /**< DLL Mode control CSR for DBYTEs, offset: 0x74 */
23764        uint8_t RESERVED_9[20];
23765   __IO uint16_t CALOFFSETS;                        /**< Impedance Calibration offsets control, offset: 0x8A */
23766        uint8_t RESERVED_10[2];
23767   __IO uint16_t SARINITVALS;                       /**< Sar Init Vals, offset: 0x8E */
23768        uint8_t RESERVED_11[2];
23769   __IO uint16_t CALPEXTOVR;                        /**< Impedance Calibration PExt Override control, offset: 0x92 */
23770   __IO uint16_t CALCMPR5OVR;                       /**< Impedance Calibration Cmpr 50 control, offset: 0x94 */
23771   __IO uint16_t CALNINTOVR;                        /**< Impedance Calibration NInt Override control, offset: 0x96 */
23772        uint8_t RESERVED_12[8];
23773   __IO uint16_t CALDRVSTR0;                        /**< Impedance Calibration driver strength control, offset: 0xA0 */
23774        uint8_t RESERVED_13[10];
23775   __IO uint16_t PROCODTTIMECTL_P0;                 /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0xAC */
23776        uint8_t RESERVED_14[8];
23777   __IO uint16_t MEMALERTCONTROL;                   /**< This Register is used to configure the MemAlert Receiver, offset: 0xB6 */
23778   __IO uint16_t MEMALERTCONTROL2;                  /**< This Register is used to configure the MemAlert Receiver, offset: 0xB8 */
23779        uint8_t RESERVED_15[6];
23780   __IO uint16_t MEMRESETL;                         /**< Protection and control of BP_MemReset_L, offset: 0xC0 */
23781        uint8_t RESERVED_16[24];
23782   __IO uint16_t DRIVECSLOWONTOHIGH;                /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */
23783   __IO uint16_t PUBMODE;                           /**< PUBMODE - HWT Mux Select, offset: 0xDC */
23784   __I  uint16_t MISCPHYSTATUS;                     /**< Misc PHY status bits, offset: 0xDE */
23785   __IO uint16_t CORELOOPBACKSEL;                   /**< Controls whether the loopback path bypasses the final PAD node., offset: 0xE0 */
23786   __IO uint16_t DLLTRAINPARAM;                     /**< DLL Various Training Parameters, offset: 0xE2 */
23787        uint8_t RESERVED_17[4];
23788   __IO uint16_t HWTLPCSENBYPASS;                   /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE8 */
23789   __IO uint16_t DFICAMODE;                         /**< Dfi Command/Address Mode, offset: 0xEA */
23790        uint8_t RESERVED_18[4];
23791   __IO uint16_t DLLCONTROL;                        /**< DLL Lock State machine control register, offset: 0xF0 */
23792   __IO uint16_t PULSEDLLUPDATEPHASE;               /**< DLL update phase control, offset: 0xF2 */
23793        uint8_t RESERVED_19[4];
23794   __IO uint16_t DLLGAINCTL_P0;                     /**< DLL gain control, offset: 0xF8 */
23795        uint8_t RESERVED_20[22];
23796   __IO uint16_t CALRATE;                           /**< Impedance Calibration Control, offset: 0x110 */
23797   __IO uint16_t CALZAP;                            /**< Impedance Calibration Zap/Reset, offset: 0x112 */
23798        uint8_t RESERVED_21[2];
23799   __IO uint16_t PSTATE;                            /**< PSTATE Selection, offset: 0x116 */
23800        uint8_t RESERVED_22[2];
23801   __IO uint16_t PLLOUTGATECONTROL;                 /**< PLL Output Control, offset: 0x11A */
23802        uint8_t RESERVED_23[4];
23803   __IO uint16_t PORCONTROL;                        /**< PMU Power-on Reset Control (PLL/DLL Lock Done), offset: 0x120 */
23804        uint8_t RESERVED_24[12];
23805   __I  uint16_t CALBUSY;                           /**< Impedance Calibration Busy Status, offset: 0x12E */
23806   __IO uint16_t CALMISC2;                          /**< Miscellaneous impedance calibration controls., offset: 0x130 */
23807        uint8_t RESERVED_25[2];
23808   __IO uint16_t CALMISC;                           /**< Controls for disabling the impedance calibration of certain targets., offset: 0x134 */
23809   __I  uint16_t CALVREFS;                          /**< offset: 0x136 */
23810   __I  uint16_t CALCMPR5;                          /**< Impedance Calibration Cmpr control, offset: 0x138 */
23811   __I  uint16_t CALNINT;                           /**< Impedance Calibration NInt control, offset: 0x13A */
23812   __I  uint16_t CALPEXT;                           /**< Impedance Calibration PExt control, offset: 0x13C */
23813        uint8_t RESERVED_26[18];
23814   __IO uint16_t CALCMPINVERT;                      /**< Impedance Calibration Cmp Invert control, offset: 0x150 */
23815        uint8_t RESERVED_27[10];
23816   __IO uint16_t CALCMPANACNTRL;                    /**< Impedance Calibration Cmpana control, offset: 0x15C */
23817        uint8_t RESERVED_28[2];
23818   __IO uint16_t DFIRDDATACSDESTMAP_P0;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x160 */
23819        uint8_t RESERVED_29[2];
23820   __IO uint16_t VREFINGLOBAL_P0;                   /**< PHY Global Vref Controls, offset: 0x164 */
23821        uint8_t RESERVED_30[2];
23822   __IO uint16_t DFIWRDATACSDESTMAP_P0;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x168 */
23823   __I  uint16_t MASUPDGOODCTR;                     /**< Counts successful PHY Master Interface Updates (PPTs), offset: 0x16A */
23824   __I  uint16_t PHYUPD0GOODCTR;                    /**< Counts successful PHY-initiated DFI0 Interface Updates, offset: 0x16C */
23825   __I  uint16_t PHYUPD1GOODCTR;                    /**< Counts successful PHY-initiated DFI1 Interface Updates, offset: 0x16E */
23826   __I  uint16_t CTLUPD0GOODCTR;                    /**< Counts successful Memory Controller DFI0 Interface Updates, offset: 0x170 */
23827   __I  uint16_t CTLUPD1GOODCTR;                    /**< Counts successful Memory Controller DFI1 Interface Updates, offset: 0x172 */
23828   __I  uint16_t MASUPDFAILCTR;                     /**< Counts unsuccessful PHY Master Interface Updates, offset: 0x174 */
23829   __I  uint16_t PHYUPD0FAILCTR;                    /**< Counts unsuccessful PHY-initiated DFI0 Interface Updates, offset: 0x176 */
23830   __I  uint16_t PHYUPD1FAILCTR;                    /**< Counts unsuccessful PHY-initiated DFI1 Interface Updates, offset: 0x178 */
23831   __IO uint16_t PHYPERFCTRENABLE;                  /**< Enables for Performance Counters, offset: 0x17A */
23832        uint8_t RESERVED_31[10];
23833   __IO uint16_t PLLPWRDN;                          /**< PLL Power Down, offset: 0x186 */
23834   __IO uint16_t PLLRESET;                          /**< PLL Reset, offset: 0x188 */
23835   __IO uint16_t PLLCTRL2_P0;                       /**< PState dependent PLL Control Register 2, offset: 0x18A */
23836   __IO uint16_t PLLCTRL0;                          /**< PLL Control Register 0, offset: 0x18C */
23837   __IO uint16_t PLLCTRL1_P0;                       /**< PState dependent PLL Control Register 1, offset: 0x18E */
23838   __IO uint16_t PLLTST;                            /**< PLL Testing Control Register, offset: 0x190 */
23839   __I  uint16_t PLLLOCKSTATUS;                     /**< PLL's pll_lock pin output, offset: 0x192 */
23840   __IO uint16_t PLLTESTMODE_P0;                    /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x194 */
23841   __IO uint16_t PLLCTRL3;                          /**< PLL Control Register 3, offset: 0x196 */
23842   __IO uint16_t PLLCTRL4_P0;                       /**< PState dependent PLL Control Register 4, offset: 0x198 */
23843   __I  uint16_t PLLENDOFCAL;                       /**< PLL's eoc (end of calibration) output, offset: 0x19A */
23844   __I  uint16_t PLLSTANDBYEFF;                     /**< PLL's standby_eff (effective standby) output, offset: 0x19C */
23845   __I  uint16_t PLLDACVALOUT;                      /**< PLL's Dacval_out output, offset: 0x19E */
23846        uint8_t RESERVED_32[38];
23847   __IO uint16_t LCDLDBGCNTL;                       /**< Controls for use in observing and testing the LCDLs., offset: 0x1C6 */
23848   __I  uint16_t ACLCDLSTATUS;                      /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
23849        uint8_t RESERVED_33[16];
23850   __I  uint16_t CUSTPHYREV;                        /**< Customer settable by the customer, offset: 0x1DA */
23851   __I  uint16_t PHYREV;                            /**< The hardware version of this PHY, excluding the PUB, offset: 0x1DC */
23852   __IO uint16_t LP3EXITSEQ0BSTARTVECTOR;           /**< Start vector value to be used for LP3-exit or Init PIE Sequence, offset: 0x1DE */
23853   __IO uint16_t DFIFREQXLAT0;                      /**< DFI Frequency Translation Register 0, offset: 0x1E0 */
23854   __IO uint16_t DFIFREQXLAT1;                      /**< DFI Frequency Translation Register 1, offset: 0x1E2 */
23855   __IO uint16_t DFIFREQXLAT2;                      /**< DFI Frequency Translation Register 2, offset: 0x1E4 */
23856   __IO uint16_t DFIFREQXLAT3;                      /**< DFI Frequency Translation Register 3, offset: 0x1E6 */
23857   __IO uint16_t DFIFREQXLAT4;                      /**< DFI Frequency Translation Register 4, offset: 0x1E8 */
23858   __IO uint16_t DFIFREQXLAT5;                      /**< DFI Frequency Translation Register 5, offset: 0x1EA */
23859   __IO uint16_t DFIFREQXLAT6;                      /**< DFI Frequency Translation Register 6, offset: 0x1EC */
23860   __IO uint16_t DFIFREQXLAT7;                      /**< DFI Frequency Translation Register 7, offset: 0x1EE */
23861   __IO uint16_t TXRDPTRINIT;                       /**< TxRdPtrInit control register, offset: 0x1F0 */
23862   __IO uint16_t DFIINITCOMPLETE;                   /**< DFI Init Complete control, offset: 0x1F2 */
23863   __IO uint16_t DFIFREQRATIO_P0;                   /**< DFI Frequency Ratio, offset: 0x1F4 */
23864   __IO uint16_t RXFIFOCHECKS;                      /**< Enable more frequent consistency checks of the RX FIFOs, offset: 0x1F6 */
23865        uint8_t RESERVED_34[6];
23866   __IO uint16_t MTESTDTOCTRL;                      /**< offset: 0x1FE */
23867   __IO uint16_t MAPCAA0TODFI;                      /**< Maps PHY CAA lane 0 from dfi0_address of the index of the register contents, offset: 0x200 */
23868   __IO uint16_t MAPCAA1TODFI;                      /**< Maps PHY CAA lane 1 from dfi0_address of the index of the register contents, offset: 0x202 */
23869   __IO uint16_t MAPCAA2TODFI;                      /**< Maps PHY CAA lane 2 from dfi0_address of the index of the register contents, offset: 0x204 */
23870   __IO uint16_t MAPCAA3TODFI;                      /**< Maps PHY CAA lane 3 from dfi0_address of the index of the register contents, offset: 0x206 */
23871   __IO uint16_t MAPCAA4TODFI;                      /**< Maps PHY CAA lane 4 from dfi0_address of the index of the register contents, offset: 0x208 */
23872   __IO uint16_t MAPCAA5TODFI;                      /**< Maps PHY CAA lane 5 from dfi0_address of the index of the register contents, offset: 0x20A */
23873   __IO uint16_t MAPCAA6TODFI;                      /**< Maps PHY CAA lane 6 from dfi0_address of the index of the register contents, offset: 0x20C */
23874   __IO uint16_t MAPCAA7TODFI;                      /**< Maps PHY CAA lane 7 from dfi0_address of the index of the register contents, offset: 0x20E */
23875   __IO uint16_t MAPCAA8TODFI;                      /**< Maps PHY CAA lane 8 from dfi0_address of the index of the register contents, offset: 0x210 */
23876   __IO uint16_t MAPCAA9TODFI;                      /**< Maps PHY CAA lane 9 from dfi0_address of the index of the register contents, offset: 0x212 */
23877        uint8_t RESERVED_35[12];
23878   __IO uint16_t MAPCAB0TODFI;                      /**< Maps PHY CAB lane 0 from dfi1_address of the index of the register contents, offset: 0x220 */
23879   __IO uint16_t MAPCAB1TODFI;                      /**< Maps PHY CAB lane 1 from dfi1_address of the index of the register contents, offset: 0x222 */
23880   __IO uint16_t MAPCAB2TODFI;                      /**< Maps PHY CAB lane 2 from dfi1_address of the index of the register contents, offset: 0x224 */
23881   __IO uint16_t MAPCAB3TODFI;                      /**< Maps PHY CAB lane 3 from dfi1_address of the index of the register contents, offset: 0x226 */
23882   __IO uint16_t MAPCAB4TODFI;                      /**< Maps PHY CAB lane 4 from dfi1_address of the index of the register contents, offset: 0x228 */
23883   __IO uint16_t MAPCAB5TODFI;                      /**< Maps PHY CAB lane 5 from dfi1_address of the index of the register contents, offset: 0x22A */
23884   __IO uint16_t MAPCAB6TODFI;                      /**< Maps PHY CAB lane 6 from dfi1_address of the index of the register contents, offset: 0x22C */
23885   __IO uint16_t MAPCAB7TODFI;                      /**< Maps PHY CAB lane 7 from dfi1_address of the index of the register contents, offset: 0x22E */
23886   __IO uint16_t MAPCAB8TODFI;                      /**< Maps PHY CAB lane 8 from dfi1_address of the index of the register contents, offset: 0x230 */
23887   __IO uint16_t MAPCAB9TODFI;                      /**< Maps PHY CAB lane 9 from dfi1_address of the index of the register contents, offset: 0x232 */
23888        uint8_t RESERVED_36[2];
23889   __IO uint16_t PHYINTERRUPTENABLE;                /**< Interrupt Enable Bits, offset: 0x236 */
23890   __IO uint16_t PHYINTERRUPTFWCONTROL;             /**< Interrupt Firmware Control Bits, offset: 0x238 */
23891   __IO uint16_t PHYINTERRUPTMASK;                  /**< Interrupt Mask Bits, offset: 0x23A */
23892   __IO uint16_t PHYINTERRUPTCLEAR;                 /**< Interrupt Clear Bits, offset: 0x23C */
23893   __I  uint16_t PHYINTERRUPTSTATUS;                /**< Interrupt Status Bits, offset: 0x23E */
23894   __IO uint16_t HWTSWIZZLEHWTADDRESS0;             /**< Signal swizzle selection for HWT swizzle, offset: 0x240 */
23895   __IO uint16_t HWTSWIZZLEHWTADDRESS1;             /**< Signal swizzle selection for HWT swizzle, offset: 0x242 */
23896   __IO uint16_t HWTSWIZZLEHWTADDRESS2;             /**< Signal swizzle selection for HWT swizzle, offset: 0x244 */
23897   __IO uint16_t HWTSWIZZLEHWTADDRESS3;             /**< Signal swizzle selection for HWT swizzle, offset: 0x246 */
23898   __IO uint16_t HWTSWIZZLEHWTADDRESS4;             /**< Signal swizzle selection for HWT swizzle, offset: 0x248 */
23899   __IO uint16_t HWTSWIZZLEHWTADDRESS5;             /**< Signal swizzle selection for HWT swizzle, offset: 0x24A */
23900   __IO uint16_t HWTSWIZZLEHWTADDRESS6;             /**< Signal swizzle selection for HWT swizzle, offset: 0x24C */
23901   __IO uint16_t HWTSWIZZLEHWTADDRESS7;             /**< Signal swizzle selection for HWT swizzle, offset: 0x24E */
23902   __IO uint16_t HWTSWIZZLEHWTADDRESS8;             /**< Signal swizzle selection for HWT swizzle, offset: 0x250 */
23903   __IO uint16_t HWTSWIZZLEHWTADDRESS9;             /**< Signal swizzle selection for HWT swizzle, offset: 0x252 */
23904   __IO uint16_t HWTSWIZZLEHWTADDRESS10;            /**< Signal swizzle selection for HWT swizzle, offset: 0x254 */
23905   __IO uint16_t HWTSWIZZLEHWTADDRESS11;            /**< Signal swizzle selection for HWT swizzle, offset: 0x256 */
23906   __IO uint16_t HWTSWIZZLEHWTADDRESS12;            /**< Signal swizzle selection for HWT swizzle, offset: 0x258 */
23907   __IO uint16_t HWTSWIZZLEHWTADDRESS13;            /**< Signal swizzle selection for HWT swizzle, offset: 0x25A */
23908   __IO uint16_t HWTSWIZZLEHWTADDRESS14;            /**< Signal swizzle selection for HWT swizzle, offset: 0x25C */
23909   __IO uint16_t HWTSWIZZLEHWTADDRESS15;            /**< Signal swizzle selection for HWT swizzle, offset: 0x25E */
23910   __IO uint16_t HWTSWIZZLEHWTADDRESS17;            /**< Signal swizzle selection for HWT swizzle, offset: 0x260 */
23911   __IO uint16_t HWTSWIZZLEHWTACTN;                 /**< Signal swizzle selection for HWT swizzle, offset: 0x262 */
23912   __IO uint16_t HWTSWIZZLEHWTBANK0;                /**< Signal swizzle selection for HWT swizzle, offset: 0x264 */
23913   __IO uint16_t HWTSWIZZLEHWTBANK1;                /**< Signal swizzle selection for HWT swizzle, offset: 0x266 */
23914   __IO uint16_t HWTSWIZZLEHWTBANK2;                /**< Signal swizzle selection for HWT swizzle, offset: 0x268 */
23915   __IO uint16_t HWTSWIZZLEHWTBG0;                  /**< Signal swizzle selection for HWT swizzle, offset: 0x26A */
23916   __IO uint16_t HWTSWIZZLEHWTBG1;                  /**< Signal swizzle selection for HWT swizzle, offset: 0x26C */
23917   __IO uint16_t HWTSWIZZLEHWTCASN;                 /**< Signal swizzle selection for HWT swizzle, offset: 0x26E */
23918   __IO uint16_t HWTSWIZZLEHWTRASN;                 /**< Signal swizzle selection for HWT swizzle, offset: 0x270 */
23919   __IO uint16_t HWTSWIZZLEHWTWEN;                  /**< Signal swizzle selection for HWT swizzle, offset: 0x272 */
23920   __IO uint16_t HWTSWIZZLEHWTPARITYIN;             /**< Signal swizzle selection for HWT swizzle, offset: 0x274 */
23921        uint8_t RESERVED_37[2];
23922   __IO uint16_t DFIHANDSHAKEDELAYS0;               /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x278 */
23923   __IO uint16_t DFIHANDSHAKEDELAYS1;               /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x27A */
23924        uint8_t RESERVED_38[2096532];
23925   __IO uint16_t CALUCLKINFO_P1;                    /**< Impedance Calibration Clock Ratio, offset: 0x200010 */
23926        uint8_t RESERVED_39[4];
23927   __IO uint16_t SEQ0BDLY0_P1;                      /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x200016 */
23928   __IO uint16_t SEQ0BDLY1_P1;                      /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x200018 */
23929   __IO uint16_t SEQ0BDLY2_P1;                      /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x20001A */
23930   __IO uint16_t SEQ0BDLY3_P1;                      /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x20001C */
23931        uint8_t RESERVED_40[2];
23932   __IO uint16_t PPTTRAINSETUP_P1;                  /**< Setup Intervals for DFI PHY Master operations, offset: 0x200020 */
23933        uint8_t RESERVED_41[16];
23934   __IO uint16_t TRISTATEMODECA_P1;                 /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x200032 */
23935        uint8_t RESERVED_42[12];
23936   __IO uint16_t HWTMRL_P1;                         /**< HWT MaxReadLatency., offset: 0x200040 */
23937        uint8_t RESERVED_43[6];
23938   __IO uint16_t DQSPREAMBLECONTROL_P1;             /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x200048 */
23939        uint8_t RESERVED_44[16];
23940   __IO uint16_t DMIPINPRESENT_P1;                  /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x20005A */
23941   __IO uint16_t ARDPTRINITVAL_P1;                  /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x20005C */
23942        uint8_t RESERVED_45[78];
23943   __IO uint16_t PROCODTTIMECTL_P1;                 /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x2000AC */
23944        uint8_t RESERVED_46[74];
23945   __IO uint16_t DLLGAINCTL_P1;                     /**< DLL gain control, offset: 0x2000F8 */
23946        uint8_t RESERVED_47[102];
23947   __IO uint16_t DFIRDDATACSDESTMAP_P1;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200160 */
23948        uint8_t RESERVED_48[2];
23949   __IO uint16_t VREFINGLOBAL_P1;                   /**< PHY Global Vref Controls, offset: 0x200164 */
23950        uint8_t RESERVED_49[2];
23951   __IO uint16_t DFIWRDATACSDESTMAP_P1;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200168 */
23952        uint8_t RESERVED_50[32];
23953   __IO uint16_t PLLCTRL2_P1;                       /**< PState dependent PLL Control Register 2, offset: 0x20018A */
23954        uint8_t RESERVED_51[2];
23955   __IO uint16_t PLLCTRL1_P1;                       /**< PState dependent PLL Control Register 1, offset: 0x20018E */
23956        uint8_t RESERVED_52[4];
23957   __IO uint16_t PLLTESTMODE_P1;                    /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x200194 */
23958        uint8_t RESERVED_53[2];
23959   __IO uint16_t PLLCTRL4_P1;                       /**< PState dependent PLL Control Register 4, offset: 0x200198 */
23960        uint8_t RESERVED_54[90];
23961   __IO uint16_t DFIFREQRATIO_P1;                   /**< DFI Frequency Ratio, offset: 0x2001F4 */
23962        uint8_t RESERVED_55[2096666];
23963   __IO uint16_t CALUCLKINFO_P2;                    /**< Impedance Calibration Clock Ratio, offset: 0x400010 */
23964        uint8_t RESERVED_56[4];
23965   __IO uint16_t SEQ0BDLY0_P2;                      /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x400016 */
23966   __IO uint16_t SEQ0BDLY1_P2;                      /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x400018 */
23967   __IO uint16_t SEQ0BDLY2_P2;                      /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x40001A */
23968   __IO uint16_t SEQ0BDLY3_P2;                      /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x40001C */
23969        uint8_t RESERVED_57[2];
23970   __IO uint16_t PPTTRAINSETUP_P2;                  /**< Setup Intervals for DFI PHY Master operations, offset: 0x400020 */
23971        uint8_t RESERVED_58[16];
23972   __IO uint16_t TRISTATEMODECA_P2;                 /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x400032 */
23973        uint8_t RESERVED_59[12];
23974   __IO uint16_t HWTMRL_P2;                         /**< HWT MaxReadLatency., offset: 0x400040 */
23975        uint8_t RESERVED_60[6];
23976   __IO uint16_t DQSPREAMBLECONTROL_P2;             /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x400048 */
23977        uint8_t RESERVED_61[16];
23978   __IO uint16_t DMIPINPRESENT_P2;                  /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x40005A */
23979   __IO uint16_t ARDPTRINITVAL_P2;                  /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x40005C */
23980        uint8_t RESERVED_62[78];
23981   __IO uint16_t PROCODTTIMECTL_P2;                 /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x4000AC */
23982        uint8_t RESERVED_63[74];
23983   __IO uint16_t DLLGAINCTL_P2;                     /**< DLL gain control, offset: 0x4000F8 */
23984        uint8_t RESERVED_64[102];
23985   __IO uint16_t DFIRDDATACSDESTMAP_P2;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400160 */
23986        uint8_t RESERVED_65[2];
23987   __IO uint16_t VREFINGLOBAL_P2;                   /**< PHY Global Vref Controls, offset: 0x400164 */
23988        uint8_t RESERVED_66[2];
23989   __IO uint16_t DFIWRDATACSDESTMAP_P2;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400168 */
23990        uint8_t RESERVED_67[32];
23991   __IO uint16_t PLLCTRL2_P2;                       /**< PState dependent PLL Control Register 2, offset: 0x40018A */
23992        uint8_t RESERVED_68[2];
23993   __IO uint16_t PLLCTRL1_P2;                       /**< PState dependent PLL Control Register 1, offset: 0x40018E */
23994        uint8_t RESERVED_69[4];
23995   __IO uint16_t PLLTESTMODE_P2;                    /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x400194 */
23996        uint8_t RESERVED_70[2];
23997   __IO uint16_t PLLCTRL4_P2;                       /**< PState dependent PLL Control Register 4, offset: 0x400198 */
23998        uint8_t RESERVED_71[90];
23999   __IO uint16_t DFIFREQRATIO_P2;                   /**< DFI Frequency Ratio, offset: 0x4001F4 */
24000        uint8_t RESERVED_72[2096666];
24001   __IO uint16_t CALUCLKINFO_P3;                    /**< Impedance Calibration Clock Ratio, offset: 0x600010 */
24002        uint8_t RESERVED_73[4];
24003   __IO uint16_t SEQ0BDLY0_P3;                      /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x600016 */
24004   __IO uint16_t SEQ0BDLY1_P3;                      /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x600018 */
24005   __IO uint16_t SEQ0BDLY2_P3;                      /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x60001A */
24006   __IO uint16_t SEQ0BDLY3_P3;                      /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x60001C */
24007        uint8_t RESERVED_74[2];
24008   __IO uint16_t PPTTRAINSETUP_P3;                  /**< Setup Intervals for DFI PHY Master operations, offset: 0x600020 */
24009        uint8_t RESERVED_75[16];
24010   __IO uint16_t TRISTATEMODECA_P3;                 /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x600032 */
24011        uint8_t RESERVED_76[12];
24012   __IO uint16_t HWTMRL_P3;                         /**< HWT MaxReadLatency., offset: 0x600040 */
24013        uint8_t RESERVED_77[6];
24014   __IO uint16_t DQSPREAMBLECONTROL_P3;             /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x600048 */
24015        uint8_t RESERVED_78[16];
24016   __IO uint16_t DMIPINPRESENT_P3;                  /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x60005A */
24017   __IO uint16_t ARDPTRINITVAL_P3;                  /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x60005C */
24018        uint8_t RESERVED_79[78];
24019   __IO uint16_t PROCODTTIMECTL_P3;                 /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x6000AC */
24020        uint8_t RESERVED_80[74];
24021   __IO uint16_t DLLGAINCTL_P3;                     /**< DLL gain control, offset: 0x6000F8 */
24022        uint8_t RESERVED_81[102];
24023   __IO uint16_t DFIRDDATACSDESTMAP_P3;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600160 */
24024        uint8_t RESERVED_82[2];
24025   __IO uint16_t VREFINGLOBAL_P3;                   /**< PHY Global Vref Controls, offset: 0x600164 */
24026        uint8_t RESERVED_83[2];
24027   __IO uint16_t DFIWRDATACSDESTMAP_P3;             /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600168 */
24028        uint8_t RESERVED_84[32];
24029   __IO uint16_t PLLCTRL2_P3;                       /**< PState dependent PLL Control Register 2, offset: 0x60018A */
24030        uint8_t RESERVED_85[2];
24031   __IO uint16_t PLLCTRL1_P3;                       /**< PState dependent PLL Control Register 1, offset: 0x60018E */
24032        uint8_t RESERVED_86[4];
24033   __IO uint16_t PLLTESTMODE_P3;                    /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x600194 */
24034        uint8_t RESERVED_87[2];
24035   __IO uint16_t PLLCTRL4_P3;                       /**< PState dependent PLL Control Register 4, offset: 0x600198 */
24036        uint8_t RESERVED_88[90];
24037   __IO uint16_t DFIFREQRATIO_P3;                   /**< DFI Frequency Ratio, offset: 0x6001F4 */
24038 } DWC_DDRPHYA_MASTER_Type;
24039 
24040 /* ----------------------------------------------------------------------------
24041    -- DWC_DDRPHYA_MASTER Register Masks
24042    ---------------------------------------------------------------------------- */
24043 
24044 /*!
24045  * @addtogroup DWC_DDRPHYA_MASTER_Register_Masks DWC_DDRPHYA_MASTER Register Masks
24046  * @{
24047  */
24048 
24049 /*! @name RXFIFOINIT - Rx FIFO pointer initialization control */
24050 /*! @{ */
24051 
24052 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_MASK (0x1U)
24053 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_SHIFT (0U)
24054 /*! RxFifoInitPtr - Setting this bit will reset the PHY RXDATAFIFO read and write pointers. */
24055 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_MASK)
24056 
24057 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_MASK (0x2U)
24058 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_SHIFT (1U)
24059 /*! InhibitRxFifoRd - This field is reserved for training FW use. */
24060 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_MASK)
24061 /*! @} */
24062 
24063 /*! @name FORCECLKDISABLE - Clock gating control */
24064 /*! @{ */
24065 
24066 #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_MASK (0xFU)
24067 #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_SHIFT (0U)
24068 /*! ForceClkDisable - This CSR forces the gating of MEMCLKs driven from the PHY ForceClkDisable[0] -
24069  *    controls CLK_H/L0 ForceClkDisable[1] - controls CLK_H/L1 (if present) ForceClkDisable[2] -
24070  *    controls CLK_H/L2 (if present) ForceClkDisable[3] - controls CLK_H/L3 (if present)
24071  */
24072 #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_SHIFT)) & DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_MASK)
24073 /*! @} */
24074 
24075 /*! @name FORCEINTERNALUPDATE - This Register used by Training Firmware to force an internal PHY Update Event. */
24076 /*! @{ */
24077 
24078 #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_MASK (0x1U)
24079 #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_SHIFT (0U)
24080 /*! ForceInternalUpdate - This Register is used by Training Firmware to force an internal PHY Update Event. */
24081 #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_SHIFT)) & DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_MASK)
24082 /*! @} */
24083 
24084 /*! @name PHYCONFIG - Read Only displays PHY Configuration. */
24085 /*! @{ */
24086 
24087 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_MASK (0xFU)
24088 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_SHIFT (0U)
24089 /*! PhyConfigAnibs - Returns the following value . */
24090 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_MASK)
24091 
24092 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_MASK (0xF0U)
24093 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_SHIFT (4U)
24094 /*! PhyConfigDbytes - Returns the following value . */
24095 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_MASK)
24096 
24097 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_MASK (0x300U)
24098 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_SHIFT (8U)
24099 /*! PhyConfigDfi - Returns the following value . */
24100 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_MASK)
24101 /*! @} */
24102 
24103 /*! @name PGCR - PHY General Configuration Register(PGCR). */
24104 /*! @{ */
24105 
24106 #define DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_MASK (0x1U)
24107 #define DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_SHIFT (0U)
24108 /*! RxClkRiseFallMode - This register field controls independent training for RxClk_c and RxClk_t. */
24109 #define DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_SHIFT)) & DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_MASK)
24110 /*! @} */
24111 
24112 /*! @name TESTBUMPCNTRL1 - Test Bump Control1 */
24113 /*! @{ */
24114 
24115 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_MASK (0x7U)
24116 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_SHIFT (0U)
24117 /*! TestMajorMode - Selects the major mode of operation for the receiver. */
24118 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_MASK)
24119 
24120 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_MASK (0x8U)
24121 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_SHIFT (3U)
24122 /*! TestBiasBypassEn - Do not use, for debug only */
24123 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_MASK)
24124 
24125 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_MASK (0xF0U)
24126 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_SHIFT (4U)
24127 /*! TestAnalogOutCtrl - Select receiver internal analog signals to monitor at analog test point
24128  *    0xxx: AnalogTestOut=HiZ 1000: AnalogTestOut=VSS 1001: AnalogTestOut=vref_dfe0 -- observe by
24129  *    sweeping MALERTVrefLevel 1010: AnalogTestOut=vref_dfe1 -- observe by sweeping MALERTVrefLevel 1011:
24130  *    AnalogTestOut=VSS 1100: AnalogTestOut=vstg2 1101: AnalogTestOut=vcasc_cs1 1110:
24131  *    AnalogTestOut=vbias_cs1 Recommended mission mode default = 4'b0000
24132  */
24133 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_MASK)
24134 
24135 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_MASK (0x1F00U)
24136 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_SHIFT (8U)
24137 /*! TestGainCurrAdj - Adjust gain and current of analog observe RX amplifier stage at analog test
24138  *    point Recommended mission mode default = 5'b01011
24139  */
24140 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_MASK)
24141 
24142 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_MASK (0x2000U)
24143 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_SHIFT (13U)
24144 /*! TestSelExternalVref - Do not use, for debug only */
24145 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_MASK)
24146 
24147 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_MASK (0x4000U)
24148 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_SHIFT (14U)
24149 /*! TestExtVrefRange - Setting this bit will extend the VREF DAC range for debug. */
24150 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_MASK)
24151 
24152 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_MASK (0x8000U)
24153 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_SHIFT (15U)
24154 /*! TestPowerGateEn - Do not use, for debug only */
24155 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_MASK)
24156 /*! @} */
24157 
24158 /*! @name CALUCLKINFO_P0 - Impedance Calibration Clock Ratio */
24159 /*! @{ */
24160 
24161 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_MASK (0x3FFU)
24162 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_SHIFT (0U)
24163 /*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24. */
24164 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_MASK)
24165 /*! @} */
24166 
24167 /*! @name TESTBUMPCNTRL - Test Bump Control */
24168 /*! @{ */
24169 
24170 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_MASK (0x3U)
24171 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_SHIFT (0U)
24172 /*! TestBumpEn - Field TestBumpEn[1:0] controls the output function of: the signal BP_ALERT_N. */
24173 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_MASK)
24174 
24175 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_MASK (0x4U)
24176 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_SHIFT (2U)
24177 /*! TestBumpToggle - This field controls the output function of the signal Digital Observation Pin,
24178  *    if available in the configuration of the PHY.
24179  */
24180 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_MASK)
24181 
24182 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_MASK (0x1F8U)
24183 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_SHIFT (3U)
24184 /*! TestBumpDataSel - RVSD. */
24185 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_MASK)
24186 
24187 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_MASK (0x200U)
24188 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_SHIFT (9U)
24189 /*! ForceMtestOnAlert - When set, causes the Digital Observation output pin to be driven onto BP_ALERT_N */
24190 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_MASK)
24191 /*! @} */
24192 
24193 /*! @name SEQ0BDLY0_P0 - PHY Initialization Engine (PIE) Delay Register 0 */
24194 /*! @{ */
24195 
24196 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_MASK (0xFFFFU)
24197 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_SHIFT (0U)
24198 /*! Seq0BDLY0_p0 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
24199  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
24200  */
24201 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_MASK)
24202 /*! @} */
24203 
24204 /*! @name SEQ0BDLY1_P0 - PHY Initialization Engine (PIE) Delay Register 1 */
24205 /*! @{ */
24206 
24207 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_MASK (0xFFFFU)
24208 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_SHIFT (0U)
24209 /*! Seq0BDLY1_p0 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
24210  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
24211  */
24212 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_MASK)
24213 /*! @} */
24214 
24215 /*! @name SEQ0BDLY2_P0 - PHY Initialization Engine (PIE) Delay Register 2 */
24216 /*! @{ */
24217 
24218 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_MASK (0xFFFFU)
24219 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_SHIFT (0U)
24220 /*! Seq0BDLY2_p0 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
24221  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
24222  */
24223 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_MASK)
24224 /*! @} */
24225 
24226 /*! @name SEQ0BDLY3_P0 - PHY Initialization Engine (PIE) Delay Register 3 */
24227 /*! @{ */
24228 
24229 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_MASK (0xFFFFU)
24230 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_SHIFT (0U)
24231 /*! Seq0BDLY3_p0 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
24232  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
24233  */
24234 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_MASK)
24235 /*! @} */
24236 
24237 /*! @name PHYALERTSTATUS - PHY Alert status bit */
24238 /*! @{ */
24239 
24240 #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_MASK (0x1U)
24241 #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_SHIFT (0U)
24242 /*! PhyAlert - Current state of ALERT_N. */
24243 #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_SHIFT)) & DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_MASK)
24244 /*! @} */
24245 
24246 /*! @name PPTTRAINSETUP_P0 - Setup Intervals for DFI PHY Master operations */
24247 /*! @{ */
24248 
24249 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_MASK (0xFU)
24250 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_SHIFT (0U)
24251 /*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next. */
24252 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_MASK)
24253 
24254 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_MASK (0x70U)
24255 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_SHIFT (4U)
24256 /*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted. */
24257 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_MASK)
24258 /*! @} */
24259 
24260 /*! @name ATESTMODE - ATestMode control */
24261 /*! @{ */
24262 
24263 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_MASK (0x1U)
24264 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_SHIFT (0U)
24265 /*! ATestPrbsEn - Enables loopback PRBS7 testing of all the DDR output pins in this chiplet. */
24266 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_MASK)
24267 
24268 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_MASK (0x2U)
24269 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_SHIFT (1U)
24270 /*! ATestClkEn - Enables the clock for loopback PRBS7 testing for all BP_A* pins. */
24271 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_MASK)
24272 
24273 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_MASK (0x1CU)
24274 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_SHIFT (2U)
24275 /*! ATestModeSel - Master Mode select for ATest (Loopback) 000 - Mission mode, all ATest disabled,
24276  *    loopback receivers powered down 001 - External Loopback mode [Single data rate pattern -
24277  *    dfi_cas sent to all lanes] 010 - Internal Loopback mode [Single data rate pattern] 011 - Internal
24278  *    Loopback mode [Double data rate pattern] 100 - External Loopback mode [Single data rate pattern
24279  *    - corresponding DFI signal sent to each lane]
24280  */
24281 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_MASK)
24282 /*! @} */
24283 
24284 /*! @name TXCALBINP - TX P Impedance Calibration observation */
24285 /*! @{ */
24286 
24287 #define DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_MASK (0x1FU)
24288 #define DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_SHIFT (0U)
24289 /*! TxCalBinP - This csr holds the binary result of the 31 bit thermometer pullup code. */
24290 #define DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_MASK)
24291 /*! @} */
24292 
24293 /*! @name TXCALBINN - TX N Impedance Calibration observation */
24294 /*! @{ */
24295 
24296 #define DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_MASK (0x1FU)
24297 #define DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_SHIFT (0U)
24298 /*! TxCalBinN - This csr holds the binary result of the 31 bit thermometer pulldown code. */
24299 #define DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_MASK)
24300 /*! @} */
24301 
24302 /*! @name TXCALPOVR - TX P Impedance Calibration override */
24303 /*! @{ */
24304 
24305 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_MASK (0x1FU)
24306 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_SHIFT (0U)
24307 /*! TxCalBinPOvrVal - The binary value which can overide the Register TxCalBinP calibrator results if Register TxCalBinPOvrEn is set. */
24308 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_MASK)
24309 
24310 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_MASK (0x20U)
24311 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_SHIFT (5U)
24312 /*! TxCalBinPOvrEn - 1 = use the override value present in Register TxCalBinPOvrVal 0 = don't. */
24313 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_MASK)
24314 /*! @} */
24315 
24316 /*! @name TXCALNOVR - TX N Impedance Calibration override */
24317 /*! @{ */
24318 
24319 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_MASK (0x1FU)
24320 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_SHIFT (0U)
24321 /*! TxCalBinNOvrVal - The binary value which can overide the Register TxCalBinN calibrator results if Register TxCalBinPOvrEn is set. */
24322 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_MASK)
24323 
24324 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_MASK (0x20U)
24325 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_SHIFT (5U)
24326 /*! TxCalBinNOvrEn - 1 = use the override value present in Register TxCalBinNOvrVal 0 = don't. */
24327 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_MASK)
24328 /*! @} */
24329 
24330 /*! @name DFIMODE - Enables for update and low-power interfaces for DFI0 and DFI1 */
24331 /*! @{ */
24332 
24333 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_MASK (0x1U)
24334 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_SHIFT (0U)
24335 /*! Dfi0Enable - Enables operation for the PHY logic associated with DFI0 */
24336 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_MASK)
24337 
24338 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_MASK (0x2U)
24339 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_SHIFT (1U)
24340 /*! Dfi1Enable - Enables operation for the PHY logic associated with DFI1 */
24341 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_MASK)
24342 
24343 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_MASK (0x4U)
24344 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_SHIFT (2U)
24345 /*! Dfi1Override - DFI0 is used to control the PHY logic associated with both DFI0 and DFI1 */
24346 #define DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_MASK)
24347 /*! @} */
24348 
24349 /*! @name TRISTATEMODECA_P0 - Mode select register for MEMCLK/Address/Command Tristates */
24350 /*! @{ */
24351 
24352 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_MASK (0x1U)
24353 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_SHIFT (0U)
24354 /*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled. */
24355 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_MASK)
24356 
24357 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_MASK (0x2U)
24358 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_SHIFT (1U)
24359 /*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode. */
24360 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_MASK)
24361 
24362 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_MASK (0xCU)
24363 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_SHIFT (2U)
24364 /*! CkDisVal - The PHY provides 4 memory clocks, n=0. */
24365 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_MASK)
24366 /*! @} */
24367 
24368 /*! @name MTESTMUXSEL - Digital Observation Pin control */
24369 /*! @{ */
24370 
24371 #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_MASK (0x3FU)
24372 #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_SHIFT (0U)
24373 /*! MtestMuxSel - Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin. */
24374 #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_MASK)
24375 /*! @} */
24376 
24377 /*! @name MTESTPGMINFO - Digital Observation Pin program info for debug */
24378 /*! @{ */
24379 
24380 #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_MASK (0x1U)
24381 #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_SHIFT (0U)
24382 /*! MtestPgmInfo - The value of this csr may be driven onto the Digital Observation Pin. */
24383 #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_MASK)
24384 /*! @} */
24385 
24386 /*! @name DYNPWRDNUP - Dynaimc Power Up/Down control */
24387 /*! @{ */
24388 
24389 #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_MASK (0x1U)
24390 #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_SHIFT (0U)
24391 /*! DynPowerDown - 1 - analog circuitry (voltage dacs, bias gen) is turned off. */
24392 #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_SHIFT)) & DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_MASK)
24393 /*! @} */
24394 
24395 /*! @name PHYTID - PHY Technology ID Register */
24396 /*! @{ */
24397 
24398 #define DWC_DDRPHYA_MASTER_PHYTID_PHYTID_MASK    (0xFFFFU)
24399 #define DWC_DDRPHYA_MASTER_PHYTID_PHYTID_SHIFT   (0U)
24400 /*! PhyTID - This register is a placeholder to store technology-specific information */
24401 #define DWC_DDRPHYA_MASTER_PHYTID_PHYTID(x)      (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYTID_PHYTID_SHIFT)) & DWC_DDRPHYA_MASTER_PHYTID_PHYTID_MASK)
24402 /*! @} */
24403 
24404 /*! @name HWTMRL_P0 - HWT MaxReadLatency. */
24405 /*! @{ */
24406 
24407 #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_MASK (0x1FU)
24408 #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_SHIFT (0U)
24409 /*! HwtMRL_p0 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
24410  *    until after all dbytes have their read data valid.
24411  */
24412 #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_MASK)
24413 /*! @} */
24414 
24415 /*! @name DFIPHYUPD - DFI PhyUpdate Request time counter (in MEMCLKs) */
24416 /*! @{ */
24417 
24418 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK (0xFU)
24419 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT (0U)
24420 /*! DFIPHYUPDCNT - This controls the interval between the end of a phyupdate transaction and a subsequent request. */
24421 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK)
24422 
24423 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK (0x70U)
24424 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT (4U)
24425 /*! DFIPHYUPDRESP - Enforces the t_phyupd_resp time, the maximum time that is allowed to controller
24426  *    to respond to the request for a PHY update.
24427  */
24428 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK)
24429 
24430 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK (0x80U)
24431 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT (7U)
24432 /*! DFIPHYUPDMODE - 1'b0 [Default] deterministic timer-based Phy Update Requests; enables multi-channel/multi-phy lockstep operation. */
24433 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK)
24434 
24435 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK (0xF00U)
24436 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT (8U)
24437 /*! DFIPHYUPDTHRESHOLD - 4'h0 Disable Threshold-based Phy Update Requests when DFIPHYUPDMODE==1'b1
24438  *    Nonzero codes are the threshold value for the change in the master LCDL 1UI phase code since
24439  *    the last Phy Update Request that will trigger a new Phy Update Request; If (current_1UI_phase -
24440  *    last_1UI_phase) > DFIPHYUPDTHRESHOLD, then a Phy Update will be requested.
24441  */
24442 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK)
24443 
24444 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK (0xF000U)
24445 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT (12U)
24446 /*! DFIPHYUPDINTTHRESHOLD - This subfield is similar to DFIPHYUPDTHRESHOLD except that rather than
24447  *    affecting the Phy Update request, it affects only the threshold used to generate the VT Drift
24448  *    Alarm Interrupt.
24449  */
24450 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK)
24451 /*! @} */
24452 
24453 /*! @name PDAMRSWRITEMODE - Controls the write DQ generation for Per-Dram-Addressing of MRS */
24454 /*! @{ */
24455 
24456 #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_MASK (0x1U)
24457 #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_SHIFT (0U)
24458 /*! PdaMrsWriteMode - Controls the write DQ generation per the timing requirements on the DQ signals
24459  *    used for Per-Dram-Addressing mode of MRS commands.
24460  */
24461 #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_SHIFT)) & DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_MASK)
24462 /*! @} */
24463 
24464 /*! @name DFIGEARDOWNCTL - Controls whether dfi_geardown_en will cause CS and CKE timing to change. */
24465 /*! @{ */
24466 
24467 #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK (0x3U)
24468 #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT (0U)
24469 /*! DFIGEARDOWNCTL - DFIGEARDOWNCTL[0] controls whether dfi_geardown_en will cause chip-select (CS) timing to change. */
24470 #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT)) & DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK)
24471 /*! @} */
24472 
24473 /*! @name DQSPREAMBLECONTROL_P0 - Control the PHY logic related to the read and write DQS preamble */
24474 /*! @{ */
24475 
24476 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_MASK (0x1U)
24477 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_SHIFT (0U)
24478 /*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
24479  *    take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
24480  *    configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
24481  */
24482 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_MASK)
24483 
24484 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_MASK (0x2U)
24485 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_SHIFT (1U)
24486 /*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
24487  *    DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
24488  */
24489 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_MASK)
24490 
24491 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_MASK (0x1CU)
24492 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_SHIFT (2U)
24493 /*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled. */
24494 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_MASK)
24495 
24496 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
24497 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
24498 /*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
24499  *    TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
24500  */
24501 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_MASK)
24502 
24503 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_MASK (0x40U)
24504 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_SHIFT (6U)
24505 /*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble. */
24506 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_MASK)
24507 
24508 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_MASK (0x80U)
24509 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_SHIFT (7U)
24510 /*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
24511  *    to the same timing group when the bubble is 1 memclk.
24512  */
24513 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_MASK)
24514 
24515 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK (0x100U)
24516 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT (8U)
24517 /*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
24518  *    respectively, before and after a write burst, except during a memory read transaction.
24519  */
24520 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK)
24521 /*! @} */
24522 
24523 /*! @name MASTERX4CONFIG - DBYTE module controls to select X4 Dram device mode */
24524 /*! @{ */
24525 
24526 #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK (0xFU)
24527 #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT (0U)
24528 /*! X4TG - Set to 1 if this Timing Group/Rank is x4 (as opposed to x8) memory. */
24529 #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT)) & DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK)
24530 /*! @} */
24531 
24532 /*! @name WRLEVBITS - Write level feedback DQ observability select. */
24533 /*! @{ */
24534 
24535 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_MASK (0xFU)
24536 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_SHIFT (0U)
24537 /*! WrLevForDQSL - Indicates which DQ bit is used for Write Levelization. */
24538 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_SHIFT)) & DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_MASK)
24539 
24540 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_MASK (0xF0U)
24541 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_SHIFT (4U)
24542 /*! WrLevForDQSU - Indicates which DQ bit is used for Write Levelization. */
24543 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_SHIFT)) & DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_MASK)
24544 /*! @} */
24545 
24546 /*! @name ENABLECSMULTICAST - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0] */
24547 /*! @{ */
24548 
24549 #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_MASK (0x1U)
24550 #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_SHIFT (0U)
24551 /*! EnableCsMulticast - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on
24552  *    CID[1:0] 0 - Do not override pins corresponding to cid[1:0] (dfi_cid[1:0] will connect to the pads)
24553  *    1 - Overrirde pins corresponding to cid[1:0] with dfi_cs[3:2].
24554  */
24555 #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_SHIFT)) & DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_MASK)
24556 /*! @} */
24557 
24558 /*! @name HWTLPCSMULTICAST - Drives cs_n[0] onto cs_n[1] during training */
24559 /*! @{ */
24560 
24561 #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_MASK (0x1U)
24562 #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_SHIFT (0U)
24563 /*! HwtLpCsMultiCast - When set, drives cs_n[0] onto cs_n[1] during training */
24564 #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_SHIFT)) & DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_MASK)
24565 /*! @} */
24566 
24567 /*! @name ACX4ANIBDIS - Disable for unused ACX Nibbles */
24568 /*! @{ */
24569 
24570 #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_MASK (0xFFFU)
24571 #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_SHIFT (0U)
24572 /*! Acx4AnibDis - When a bit is set, the corresponding ACX nibble is disabled (specifically, the I/O
24573  *    OE is disabled, as is the Dfi-side FIFO clock
24574  */
24575 #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_SHIFT)) & DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_MASK)
24576 /*! @} */
24577 
24578 /*! @name DMIPINPRESENT_P0 - This Register is used to enable the Read-DBI function in each DBYTE */
24579 /*! @{ */
24580 
24581 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_MASK (0x1U)
24582 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_SHIFT (0U)
24583 /*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device. */
24584 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_MASK)
24585 /*! @} */
24586 
24587 /*! @name ARDPTRINITVAL_P0 - Address/Command FIFO ReadPointer Initial Value */
24588 /*! @{ */
24589 
24590 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_MASK (0xFU)
24591 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_SHIFT (0U)
24592 /*! ARdPtrInitVal_p0 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips. */
24593 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_MASK)
24594 /*! @} */
24595 
24596 /*! @name DBYTEDLLMODECNTRL - DLL Mode control CSR for DBYTEs */
24597 /*! @{ */
24598 
24599 #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_MASK (0x2U)
24600 #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_SHIFT (1U)
24601 /*! DllRxPreambleMode - Must be set to 1 if read DQS preamble contains a toggle, for example DDR4 or LPDDR4 read toggling preambe mode */
24602 #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_MASK)
24603 /*! @} */
24604 
24605 /*! @name CALOFFSETS - Impedance Calibration offsets control */
24606 /*! @{ */
24607 
24608 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_MASK (0x3FU)
24609 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_SHIFT (0U)
24610 /*! CalCmpr5Offset - This value adjusts the offset-compensated DAC code for the cmpana circuit at VRef == 0. */
24611 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_MASK)
24612 
24613 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_MASK (0x3C0U)
24614 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_SHIFT (6U)
24615 /*! CalDrvPdThOffset - This value adjusts the driver pulldown calibration code */
24616 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_MASK)
24617 
24618 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_MASK (0x3C00U)
24619 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_SHIFT (10U)
24620 /*! CalDrvPuThOffset - This value adjusts the driver pullup calibration code */
24621 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_MASK)
24622 /*! @} */
24623 
24624 /*! @name SARINITVALS - Sar Init Vals */
24625 /*! @{ */
24626 
24627 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_MASK (0x7U)
24628 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_SHIFT (0U)
24629 /*! SarInitOFFSET05 - Specify the SAR starting value for OFFSET05 calibration. */
24630 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_MASK)
24631 
24632 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_MASK (0x38U)
24633 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_SHIFT (3U)
24634 /*! SarInitNINT - Specify the SAR starting value for NINT calibration. */
24635 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_MASK)
24636 
24637 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_MASK (0x1C0U)
24638 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_SHIFT (6U)
24639 /*! SarInitPEXT - Specify the SAR starting value for PEXT calibration. */
24640 #define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_MASK)
24641 /*! @} */
24642 
24643 /*! @name CALPEXTOVR - Impedance Calibration PExt Override control */
24644 /*! @{ */
24645 
24646 #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_MASK (0x1FU)
24647 #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_SHIFT (0U)
24648 /*! CalPExtOvr - If the CSR CalPExtDis is set then the value provided here by software will be used
24649  *    instead of the automatically generated value which is visible via CSR CalPExt This CSR may
24650  *    only be written when the calibrator is not running.
24651  */
24652 #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_SHIFT)) & DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_MASK)
24653 /*! @} */
24654 
24655 /*! @name CALCMPR5OVR - Impedance Calibration Cmpr 50 control */
24656 /*! @{ */
24657 
24658 #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_MASK (0xFFU)
24659 #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_SHIFT (0U)
24660 /*! CalCmpr5Ovr - If the CSR CalCmpr5Dis is set then the value provided here by software will be
24661  *    used instead of the automatically generated value which is visible via CSR CalCmpr5 This CSR may
24662  *    only be written when the calibrator is not running.
24663  */
24664 #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_MASK)
24665 /*! @} */
24666 
24667 /*! @name CALNINTOVR - Impedance Calibration NInt Override control */
24668 /*! @{ */
24669 
24670 #define DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_MASK (0x1FU)
24671 #define DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_SHIFT (0U)
24672 /*! CalNIntOvr - If the CSR CalNIntDis is set then the value provided here by software will be used
24673  *    instead of the automatically generated value which is visible via CSR CalNInt.
24674  */
24675 #define DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_SHIFT)) & DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_MASK)
24676 /*! @} */
24677 
24678 /*! @name CALDRVSTR0 - Impedance Calibration driver strength control */
24679 /*! @{ */
24680 
24681 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_MASK (0xFU)
24682 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_SHIFT (0U)
24683 /*! CalDrvStrPd50 - 3. */
24684 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_SHIFT)) & DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_MASK)
24685 
24686 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_MASK (0xF0U)
24687 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_SHIFT (4U)
24688 /*! CalDrvStrPu50 - 3. */
24689 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_SHIFT)) & DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_MASK)
24690 /*! @} */
24691 
24692 /*! @name PROCODTTIMECTL_P0 - READ DATA On-Die Termination Timing Control (by PHY) */
24693 /*! @{ */
24694 
24695 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_MASK (0x3U)
24696 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_SHIFT (0U)
24697 /*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
24698  *    Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
24699  *    1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
24700  *    to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
24701  */
24702 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_MASK)
24703 
24704 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_MASK (0xCU)
24705 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_SHIFT (2U)
24706 /*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
24707  *    start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
24708  *    from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
24709  */
24710 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_MASK)
24711 /*! @} */
24712 
24713 /*! @name MEMALERTCONTROL - This Register is used to configure the MemAlert Receiver */
24714 /*! @{ */
24715 
24716 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_MASK (0x7FU)
24717 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_SHIFT (0U)
24718 /*! MALERTVrefLevel - Sets the vref level of internal VREF DAC. */
24719 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_MASK)
24720 
24721 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_MASK (0x80U)
24722 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_SHIFT (7U)
24723 /*! MALERTVrefExtEn - When set for test/debug, selects external Vref source, This should not be set in mission mode. */
24724 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_MASK)
24725 
24726 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_MASK (0xF00U)
24727 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_SHIFT (8U)
24728 /*! MALERTPuStren - Controls the Pull-up termination on MALERT
24729  *    ========================================== bit[8] - controls a 240 Ohm Pull-up leg bit[9] - controls a 240 Ohm Pull-up leg bit[10]
24730  *    - controls a 120 Ohm Pull-up leg bit[11] - controls a 120 Ohm Pull-up leg
24731  *    ========================================== 0000 - No PullUp Strength 0001 - 240 Ohm PullUp Strength 0010 - 240 Ohm
24732  *    PullUp Strength 0011 - 120 Ohm PullUp Strength 0100 - 120 Ohm PullUp Strength 0101 - 80 Ohm
24733  *    PullUp Strength 0110 - 80 Ohm PullUp Strength 0111 - 60 Ohm PullUp Strength 1000 - 120 Ohm
24734  *    PullUp Strength 1001 - 80 Ohm PullUp Strength 1010 - 80 Ohm PullUp Strength 1011 - 60 Ohm PullUp
24735  *    Strength 1100 - 60 Ohm PullUp Strength 1101 - 48 Ohm PullUp Strength 1110 - 48 Ohm PullUp
24736  *    Strength 1111 - 40 Ohm PullUp Strength
24737  */
24738 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_MASK)
24739 
24740 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_MASK (0x1000U)
24741 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_SHIFT (12U)
24742 /*! MALERTPuEn - When set, enables the Pull-up termination on MALERT */
24743 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_MASK)
24744 
24745 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_MASK (0x2000U)
24746 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_SHIFT (13U)
24747 /*! MALERTRxEn - 1 - Enables receiver and received data is forwared to dfi_alert_n. */
24748 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_MASK)
24749 
24750 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_MASK (0x4000U)
24751 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_SHIFT (14U)
24752 /*! MALERTDisableVal - When MALERTRxEn is not set, this CSR state is used to drive dfi_alert_n. */
24753 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_MASK)
24754 
24755 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_MASK (0x8000U)
24756 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_SHIFT (15U)
24757 /*! MALERTForceError - When MALERTForceError is set, this CSR state is used to force parity error to memory. */
24758 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_MASK)
24759 /*! @} */
24760 
24761 /*! @name MEMALERTCONTROL2 - This Register is used to configure the MemAlert Receiver */
24762 /*! @{ */
24763 
24764 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_MASK (0x1U)
24765 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_SHIFT (0U)
24766 /*! MALERTSyncBypass - MALERTSyncBypass==[0], the phy will drive dfi_alert_n with a synchronized value of the ALERT_N receiver. */
24767 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_MASK)
24768 /*! @} */
24769 
24770 /*! @name MEMRESETL - Protection and control of BP_MemReset_L */
24771 /*! @{ */
24772 
24773 #define DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_MASK (0x1U)
24774 #define DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_SHIFT (0U)
24775 /*! MemResetLValue - Control the MemResetL output of the PHY. */
24776 #define DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_SHIFT)) & DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_MASK)
24777 
24778 #define DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_MASK (0x2U)
24779 #define DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_SHIFT (1U)
24780 /*! ProtectMemReset - Control the MemResetL output of the PHY. */
24781 #define DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_SHIFT)) & DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_MASK)
24782 /*! @} */
24783 
24784 /*! @name DRIVECSLOWONTOHIGH - Drive CS_N 3:0 onto CS_N 7:4 */
24785 /*! @{ */
24786 
24787 #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_MASK (0x1U)
24788 #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_SHIFT (0U)
24789 /*! CsLowOntoHigh - When this is set to a 1, CS[3:0] from the ACSM are driven to CS[7:4] pins and CS[3:0] are deasserted. */
24790 #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_SHIFT)) & DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_MASK)
24791 /*! @} */
24792 
24793 /*! @name PUBMODE - PUBMODE - HWT Mux Select */
24794 /*! @{ */
24795 
24796 #define DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_MASK (0x1U)
24797 #define DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_SHIFT (0U)
24798 /*! HwtMemSrc - When this is set to a 1, the mux that switches between DCT and HWT for the source of
24799  *    memory transactions is switched to HWT.
24800  */
24801 #define DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_SHIFT)) & DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_MASK)
24802 /*! @} */
24803 
24804 /*! @name MISCPHYSTATUS - Misc PHY status bits */
24805 /*! @{ */
24806 
24807 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_MASK (0x1U)
24808 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_SHIFT (0U)
24809 /*! DctSane - Returns the status of the custom circuit which protects the MemResetL output of the PHY on initial power-on or reset. */
24810 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_SHIFT)) & DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_MASK)
24811 
24812 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_MASK (0x2U)
24813 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_SHIFT (1U)
24814 /*! PORMemReset - Returns the active-high value used by the custom circuit which drives the memory RESET signal. */
24815 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_SHIFT)) & DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_MASK)
24816 /*! @} */
24817 
24818 /*! @name CORELOOPBACKSEL - Controls whether the loopback path bypasses the final PAD node. */
24819 /*! @{ */
24820 
24821 #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_MASK (0x1U)
24822 #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_SHIFT (0U)
24823 /*! CoreLoopbackSel - This register is controlled by the PHY test firmware This register enables Core-Side loopback operation of the PHY. */
24824 #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_SHIFT)) & DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_MASK)
24825 /*! @} */
24826 
24827 /*! @name DLLTRAINPARAM - DLL Various Training Parameters */
24828 /*! @{ */
24829 
24830 #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_MASK (0x3U)
24831 #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_SHIFT (0U)
24832 /*! ExtendPhdTime - Used by the PHY firmware locking the LCDL delay cells. */
24833 #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_SHIFT)) & DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_MASK)
24834 /*! @} */
24835 
24836 /*! @name HWTLPCSENBYPASS - CSn Disable Bypass for LPDDR3/4 */
24837 /*! @{ */
24838 
24839 #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_MASK (0x1U)
24840 #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_SHIFT (0U)
24841 /*! HwtLpCsEnBypass - When set, these bits disable LpCsEn function for LPDDR3/4 */
24842 #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_SHIFT)) & DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_MASK)
24843 /*! @} */
24844 
24845 /*! @name DFICAMODE - Dfi Command/Address Mode */
24846 /*! @{ */
24847 
24848 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_MASK (0x1U)
24849 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_SHIFT (0U)
24850 /*! DfiLp3CAMode - Controls the output data-rate of the AC module Command/Address pins 0: LP3 DDR
24851  *    address mode disabled 1: LP3 DDR address mode enabled
24852  */
24853 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_MASK)
24854 
24855 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_MASK (0x2U)
24856 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_SHIFT (1U)
24857 /*! DfiD4CAMode - Enable D4 Mode 0: D4 mode disabled 1: D4 mode enabled */
24858 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_MASK)
24859 
24860 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_MASK (0x4U)
24861 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_SHIFT (2U)
24862 /*! DfiLp4CAMode - Enable LP4 Mode 0: LP4 mode disabled 1: LP4 mode enabled */
24863 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_MASK)
24864 
24865 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_MASK (0x8U)
24866 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_SHIFT (3U)
24867 /*! DfiD4AltCAMode - Enable D4-Alt Mode 0: D4-Altmode disabled 1: D4-Altmode enabled */
24868 #define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_MASK)
24869 /*! @} */
24870 
24871 /*! @name DLLCONTROL - DLL Lock State machine control register */
24872 /*! @{ */
24873 
24874 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_MASK (0x1U)
24875 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_SHIFT (0U)
24876 /*! DllResetRelock - Used to reset the DDL/LCDL lock state machine Deasserting starts locking sequence. */
24877 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_MASK)
24878 
24879 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_MASK (0x2U)
24880 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_SHIFT (1U)
24881 /*! DllResetSlave - Reserved. */
24882 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_MASK)
24883 
24884 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_MASK (0x4U)
24885 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_SHIFT (2U)
24886 /*! DllResetRSVD - RSVD for future use */
24887 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_MASK)
24888 /*! @} */
24889 
24890 /*! @name PULSEDLLUPDATEPHASE - DLL update phase control */
24891 /*! @{ */
24892 
24893 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_MASK (0x1U)
24894 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_SHIFT (0U)
24895 /*! PulseDbyteDllUpdatePhase - Causes a LongBubble to the DBYTE modules, which causes a update of the DBYTE module DLLs (tx,rxen,rxclk). */
24896 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_MASK)
24897 
24898 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_MASK (0x2U)
24899 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_SHIFT (1U)
24900 /*! PulseACkDllUpdatePhase - Causes an AC module CK (memck) DLL phase update. */
24901 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_MASK)
24902 
24903 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_MASK (0x4U)
24904 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_SHIFT (2U)
24905 /*! PulseACaDllUpdatePhase - Causes an AC module CA (command/address/cke/odt) DLL phase update. */
24906 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_MASK)
24907 
24908 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_MASK (0x38U)
24909 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_SHIFT (3U)
24910 /*! UpdatePhaseDestReserved - reserved, not used */
24911 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_MASK)
24912 
24913 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_MASK (0x40U)
24914 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_SHIFT (6U)
24915 /*! TrainUpdatePhaseOnLongBubble - Causes LongBubble to update the dbyte & anib LDCL Phase. */
24916 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_MASK)
24917 
24918 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_MASK (0x80U)
24919 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_SHIFT (7U)
24920 /*! AlwaysUpdateLcdlPhase - Causes each new operation to reload the LcdlPhase; will increase bubbles. */
24921 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_MASK)
24922 /*! @} */
24923 
24924 /*! @name DLLGAINCTL_P0 - DLL gain control */
24925 /*! @{ */
24926 
24927 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_MASK (0xFU)
24928 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_SHIFT (0U)
24929 /*! DllGainIV - Initial value of DllGain. */
24930 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_MASK)
24931 
24932 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_MASK (0xF0U)
24933 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_SHIFT (4U)
24934 /*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
24935  *    used for maintaining lock, ie tracking pclk variation.
24936  */
24937 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_MASK)
24938 
24939 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_MASK (0xF00U)
24940 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_SHIFT (8U)
24941 /*! DllSeedSel - Reserved, must be configured to be 0. */
24942 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_MASK)
24943 /*! @} */
24944 
24945 /*! @name CALRATE - Impedance Calibration Control */
24946 /*! @{ */
24947 
24948 #define DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_MASK (0xFU)
24949 #define DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_SHIFT (0U)
24950 /*! CalInterval - This CSR specifies the interval between successive calibrations, in mS. */
24951 #define DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_MASK)
24952 
24953 #define DWC_DDRPHYA_MASTER_CALRATE_CALRUN_MASK   (0x10U)
24954 #define DWC_DDRPHYA_MASTER_CALRATE_CALRUN_SHIFT  (4U)
24955 /*! CalRun - 1: A calibration sequence will be triggered by the 0->1 transition of this bit, as determined by CSR CalOnce. */
24956 #define DWC_DDRPHYA_MASTER_CALRATE_CALRUN(x)     (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CALRUN_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CALRUN_MASK)
24957 
24958 #define DWC_DDRPHYA_MASTER_CALRATE_CALONCE_MASK  (0x20U)
24959 #define DWC_DDRPHYA_MASTER_CALRATE_CALONCE_SHIFT (5U)
24960 /*! CalOnce - The setting of this CSR changes the behaviour of CSR CalRun. */
24961 #define DWC_DDRPHYA_MASTER_CALRATE_CALONCE(x)    (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CALONCE_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CALONCE_MASK)
24962 
24963 #define DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_MASK (0x40U)
24964 #define DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_SHIFT (6U)
24965 /*! DisableBackgroundZQUpdates - 1: Instead of having the driver compensation codes go
24966  *    asynchronously out to all IO, hold until for any of PHYUPD ACK, CTRLUPD ACK, PHYMSTR ACK) 0: Calibrated ZQ
24967  *    Updates to IO aren't gated.
24968  */
24969 #define DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_MASK)
24970 /*! @} */
24971 
24972 /*! @name CALZAP - Impedance Calibration Zap/Reset */
24973 /*! @{ */
24974 
24975 #define DWC_DDRPHYA_MASTER_CALZAP_CALZAP_MASK    (0x1U)
24976 #define DWC_DDRPHYA_MASTER_CALZAP_CALZAP_SHIFT   (0U)
24977 /*! CalZap - NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten. */
24978 #define DWC_DDRPHYA_MASTER_CALZAP_CALZAP(x)      (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALZAP_CALZAP_SHIFT)) & DWC_DDRPHYA_MASTER_CALZAP_CALZAP_MASK)
24979 /*! @} */
24980 
24981 /*! @name PSTATE - PSTATE Selection */
24982 /*! @{ */
24983 
24984 #define DWC_DDRPHYA_MASTER_PSTATE_PSTATE_MASK    (0xFU)
24985 #define DWC_DDRPHYA_MASTER_PSTATE_PSTATE_SHIFT   (0U)
24986 /*! PState - NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten. */
24987 #define DWC_DDRPHYA_MASTER_PSTATE_PSTATE(x)      (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PSTATE_PSTATE_SHIFT)) & DWC_DDRPHYA_MASTER_PSTATE_PSTATE_MASK)
24988 /*! @} */
24989 
24990 /*! @name PLLOUTGATECONTROL - PLL Output Control */
24991 /*! @{ */
24992 
24993 #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_MASK (0x1U)
24994 #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_SHIFT (0U)
24995 /*! PclkGateEn - Reserved. */
24996 #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_MASK)
24997 /*! @} */
24998 
24999 /*! @name PORCONTROL - PMU Power-on Reset Control (PLL/DLL Lock Done) */
25000 /*! @{ */
25001 
25002 #define DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_MASK (0x1U)
25003 #define DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_SHIFT (0U)
25004 /*! PllDllLockDone - Set by the PIE to 1 after it has finished the PLL/DLL lock sequence. */
25005 #define DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_SHIFT)) & DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_MASK)
25006 /*! @} */
25007 
25008 /*! @name CALBUSY - Impedance Calibration Busy Status */
25009 /*! @{ */
25010 
25011 #define DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_MASK  (0x1U)
25012 #define DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_SHIFT (0U)
25013 /*! CalBusy - Read 1 if the calibrator is actively calibrating. */
25014 #define DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY(x)    (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_SHIFT)) & DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_MASK)
25015 /*! @} */
25016 
25017 /*! @name CALMISC2 - Miscellaneous impedance calibration controls. */
25018 /*! @{ */
25019 
25020 #define DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_MASK (0x7U)
25021 #define DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_SHIFT (0U)
25022 /*! CalNumVotes - This CSR controls the number of consecutive comparator output bits over which majority voting is done. */
25023 #define DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_MASK)
25024 
25025 #define DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_MASK (0x1000U)
25026 #define DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_SHIFT (12U)
25027 /*! CalCmptrResTrim - Reserved for future use. */
25028 #define DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_MASK)
25029 
25030 #define DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_MASK (0x2000U)
25031 #define DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_SHIFT (13U)
25032 /*! CalCancelRoundErrDis - The PEXT calibration result and NINT calibration results naturally
25033  *    include a rounding error which manifests as a change of impedance at the pad.
25034  */
25035 #define DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_MASK)
25036 
25037 #define DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_MASK (0x4000U)
25038 #define DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_SHIFT (14U)
25039 /*! CalSlowCmpana - When set, this CSR increases the time allowed for the cmpana cell to settle, by 50%. */
25040 #define DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_MASK)
25041 /*! @} */
25042 
25043 /*! @name CALMISC - Controls for disabling the impedance calibration of certain targets. */
25044 /*! @{ */
25045 
25046 #define DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_MASK (0x1U)
25047 #define DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_SHIFT (0U)
25048 /*! CalCmpr5Dis - Setting this CSR prevents the calibration engine from using the result from the CalCmpr5 stage of calibration. */
25049 #define DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_MASK)
25050 
25051 #define DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_MASK (0x2U)
25052 #define DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_SHIFT (1U)
25053 /*! CalNIntDis - Setting this CSR prevents the calibration engine from overwriting the CSRs
25054  *    TxCalBinN and TxCalThN with an automatically generated value, in which case a value must be supplied
25055  *    by software.
25056  */
25057 #define DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_MASK)
25058 
25059 #define DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_MASK (0x4U)
25060 #define DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_SHIFT (2U)
25061 /*! CalPExtDis - Setting this CSR prevents the calibration engine from overwriting the CSRs
25062  *    TxCalBinP and TxCalThP with an automatically generated value, in which case a value must be supplied
25063  *    by software.
25064  */
25065 #define DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_MASK)
25066 /*! @} */
25067 
25068 /*! @name CALVREFS -  */
25069 /*! @{ */
25070 
25071 #define DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_MASK (0x3U)
25072 #define DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_SHIFT (0U)
25073 /*! CalVRefs - This CSR drives the Cmpdig_CalRef pin of the cmpana cell at various stages of calibration. */
25074 #define DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_SHIFT)) & DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_MASK)
25075 /*! @} */
25076 
25077 /*! @name CALCMPR5 - Impedance Calibration Cmpr control */
25078 /*! @{ */
25079 
25080 #define DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_MASK (0xFFU)
25081 #define DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_SHIFT (0U)
25082 /*! CalCmpr5 - Returns the offset-compensated DAC code for the cmpana circuit at VRef == 0. */
25083 #define DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_MASK)
25084 /*! @} */
25085 
25086 /*! @name CALNINT - Impedance Calibration NInt control */
25087 /*! @{ */
25088 
25089 #define DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_MASK (0x1FU)
25090 #define DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_SHIFT (0U)
25091 /*! CalNIntThB - The value here is the number of thermometer bits which are set. */
25092 #define DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_SHIFT)) & DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_MASK)
25093 /*! @} */
25094 
25095 /*! @name CALPEXT - Impedance Calibration PExt control */
25096 /*! @{ */
25097 
25098 #define DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_MASK (0x1FU)
25099 #define DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_SHIFT (0U)
25100 /*! CalPExtThB - The value here is the number of thermometer bits which are set. */
25101 #define DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_SHIFT)) & DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_MASK)
25102 /*! @} */
25103 
25104 /*! @name CALCMPINVERT - Impedance Calibration Cmp Invert control */
25105 /*! @{ */
25106 
25107 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_MASK (0x1U)
25108 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_SHIFT (0U)
25109 /*! CmpInvertCalDac50 - Impedance Calibration Cmp Invert control */
25110 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_MASK)
25111 
25112 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_MASK (0x2U)
25113 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_SHIFT (1U)
25114 /*! CmpInvertCalDrvPd50 - Impedance Calibration Cmp Invert control */
25115 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_MASK)
25116 
25117 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_MASK (0x4U)
25118 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_SHIFT (2U)
25119 /*! CmpInvertCalDrvPu50 - Impedance Calibration Cmp Invert control */
25120 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_MASK)
25121 
25122 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_MASK (0x8U)
25123 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_SHIFT (3U)
25124 /*! CmpInvertCalOdtPd - Impedance Calibration Cmp Invert control */
25125 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_MASK)
25126 
25127 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_MASK (0x10U)
25128 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_SHIFT (4U)
25129 /*! CmpInvertCalOdtPu - Impedance Calibration Cmp Invert control */
25130 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_MASK)
25131 /*! @} */
25132 
25133 /*! @name CALCMPANACNTRL - Impedance Calibration Cmpana control */
25134 /*! @{ */
25135 
25136 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_MASK (0xFFU)
25137 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_SHIFT (0U)
25138 /*! CmprGainCurrAdj - Impedance Calibration Cmpana control */
25139 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_MASK)
25140 
25141 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_MASK (0x100U)
25142 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_SHIFT (8U)
25143 /*! CmprGainResAdj - Impedance Calibration Cmpana control */
25144 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_MASK)
25145 
25146 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_MASK (0x200U)
25147 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_SHIFT (9U)
25148 /*! CmprBiasBypassEn - Impedance Calibration Cmpana control */
25149 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_MASK)
25150 /*! @} */
25151 
25152 /*! @name DFIRDDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
25153 /*! @{ */
25154 
25155 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_MASK (0x3U)
25156 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_SHIFT (0U)
25157 /*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
25158  *    dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
25159  */
25160 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_MASK)
25161 
25162 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_MASK (0xCU)
25163 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_SHIFT (2U)
25164 /*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
25165  *    dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
25166  */
25167 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_MASK)
25168 
25169 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_MASK (0x30U)
25170 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_SHIFT (4U)
25171 /*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
25172  *    dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
25173  */
25174 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_MASK)
25175 
25176 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_MASK (0xC0U)
25177 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_SHIFT (6U)
25178 /*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
25179  *    dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
25180  */
25181 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_MASK)
25182 /*! @} */
25183 
25184 /*! @name VREFINGLOBAL_P0 - PHY Global Vref Controls */
25185 /*! @{ */
25186 
25187 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_MASK (0x7U)
25188 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_SHIFT (0U)
25189 /*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
25190  *    ========================================================== 2'b00 - PHY Vref DAC Range0 --
25191  *    BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
25192  *    Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
25193  *    ========================================================== GlobalVrefInSel[2] shall be set according to Dram
25194  *    Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
25195  *    1'b0 LPDDR3 1'b0 LPDDR4 1'b1
25196  */
25197 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_MASK)
25198 
25199 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_MASK (0x3F8U)
25200 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_SHIFT (3U)
25201 /*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
25202  *    by GlobalVrefInSel[2] ========================================================== RANGE0 :
25203  *    DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
25204  *    0.
25205  */
25206 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_MASK)
25207 
25208 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_MASK (0x3C00U)
25209 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_SHIFT (10U)
25210 /*! GlobalVrefInTrim - RSVD */
25211 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_MASK)
25212 
25213 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_MASK (0x4000U)
25214 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_SHIFT (14U)
25215 /*! GlobalVrefInMode - RSVD */
25216 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_MASK)
25217 /*! @} */
25218 
25219 /*! @name DFIWRDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
25220 /*! @{ */
25221 
25222 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_MASK (0x3U)
25223 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_SHIFT (0U)
25224 /*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
25225  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
25226  */
25227 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_MASK)
25228 
25229 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_MASK (0xCU)
25230 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_SHIFT (2U)
25231 /*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
25232  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
25233  */
25234 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_MASK)
25235 
25236 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_MASK (0x30U)
25237 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_SHIFT (4U)
25238 /*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
25239  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
25240  */
25241 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_MASK)
25242 
25243 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_MASK (0xC0U)
25244 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_SHIFT (6U)
25245 /*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
25246  *    TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
25247  */
25248 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_MASK)
25249 /*! @} */
25250 
25251 /*! @name MASUPDGOODCTR - Counts successful PHY Master Interface Updates (PPTs) */
25252 /*! @{ */
25253 
25254 #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_MASK (0xFFFFU)
25255 #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_SHIFT (0U)
25256 /*! MasUpdGoodCtr - This register increments whenever the Memory Controller acknowledges a PHY Master Interface request (i. */
25257 #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_MASK)
25258 /*! @} */
25259 
25260 /*! @name PHYUPD0GOODCTR - Counts successful PHY-initiated DFI0 Interface Updates */
25261 /*! @{ */
25262 
25263 #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_MASK (0xFFFFU)
25264 #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_SHIFT (0U)
25265 /*! PhyUpd0GoodCtr - This register increments whenever the Memory Controller acknowledges a PHY-initiated DFI0 interface update request. */
25266 #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_MASK)
25267 /*! @} */
25268 
25269 /*! @name PHYUPD1GOODCTR - Counts successful PHY-initiated DFI1 Interface Updates */
25270 /*! @{ */
25271 
25272 #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_MASK (0xFFFFU)
25273 #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_SHIFT (0U)
25274 /*! PhyUpd1GoodCtr - This register increments whenever the Memory Controller acknowledges a PHY-initiated DFI1 interface update request. */
25275 #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_MASK)
25276 /*! @} */
25277 
25278 /*! @name CTLUPD0GOODCTR - Counts successful Memory Controller DFI0 Interface Updates */
25279 /*! @{ */
25280 
25281 #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_MASK (0xFFFFU)
25282 #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_SHIFT (0U)
25283 /*! CtlUpd0GoodCtr - This register increments whenever the PHY acknowledges a Memory Controller-initiated DFI0 interface update request. */
25284 #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_MASK)
25285 /*! @} */
25286 
25287 /*! @name CTLUPD1GOODCTR - Counts successful Memory Controller DFI1 Interface Updates */
25288 /*! @{ */
25289 
25290 #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_MASK (0xFFFFU)
25291 #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_SHIFT (0U)
25292 /*! CtlUpd1GoodCtr - This register increments whenever the PHY acknowledges a Memory Controller-initiated DFI1 interface update request. */
25293 #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_MASK)
25294 /*! @} */
25295 
25296 /*! @name MASUPDFAILCTR - Counts unsuccessful PHY Master Interface Updates */
25297 /*! @{ */
25298 
25299 #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_MASK (0xFFFFU)
25300 #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_SHIFT (0U)
25301 /*! MasUpdFailCtr - This register increments whenever the PHY asserts a PHY Master Interface
25302  *    request, but the Memory Controller doesn't acknowledge the request within the allowed interval.
25303  */
25304 #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_MASK)
25305 /*! @} */
25306 
25307 /*! @name PHYUPD0FAILCTR - Counts unsuccessful PHY-initiated DFI0 Interface Updates */
25308 /*! @{ */
25309 
25310 #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_MASK (0xFFFFU)
25311 #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_SHIFT (0U)
25312 /*! PhyUpd0FailCtr - This register increments whenever the PHY asserts a DFI0 Interface update
25313  *    request, but the Memory Controller doesn't acknowledge the request within the allowed interval.
25314  */
25315 #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_MASK)
25316 /*! @} */
25317 
25318 /*! @name PHYUPD1FAILCTR - Counts unsuccessful PHY-initiated DFI1 Interface Updates */
25319 /*! @{ */
25320 
25321 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU)
25322 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT (0U)
25323 /*! PhyUpd1FailCtr - This register increments whenever the PHY asserts a DFI1 Interface update
25324  *    request, but the Memory Controller doesn't acknowledge the request within the allowed interval.
25325  */
25326 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK)
25327 /*! @} */
25328 
25329 /*! @name PHYPERFCTRENABLE - Enables for Performance Counters */
25330 /*! @{ */
25331 
25332 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_MASK (0x1U)
25333 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_SHIFT (0U)
25334 /*! MasUpdGoodCtl - Enables MasUpdGoodCtr */
25335 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_MASK)
25336 
25337 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_MASK (0x2U)
25338 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_SHIFT (1U)
25339 /*! PhyUpd0GoodCtl - Enables PhyUpd0GoodCtr */
25340 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_MASK)
25341 
25342 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_MASK (0x4U)
25343 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_SHIFT (2U)
25344 /*! PhyUpd1GoodCtl - Enables PhyUpd1GoodCtr */
25345 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_MASK)
25346 
25347 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_MASK (0x8U)
25348 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_SHIFT (3U)
25349 /*! CtlUpd0GoodCtl - Enables CtlUpd0GoodCtr */
25350 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_MASK)
25351 
25352 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_MASK (0x10U)
25353 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_SHIFT (4U)
25354 /*! CtlUpd1GoodCtl - Enables CtlUpd1GoodCtr */
25355 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_MASK)
25356 
25357 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_MASK (0x20U)
25358 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_SHIFT (5U)
25359 /*! MasUpdFailCtl - Enables MasUpdFailCtr */
25360 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_MASK)
25361 
25362 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_MASK (0x40U)
25363 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_SHIFT (6U)
25364 /*! PhyUpd0FailCtl - Enables PhyUpd0FailCtr */
25365 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_MASK)
25366 
25367 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_MASK (0x80U)
25368 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_SHIFT (7U)
25369 /*! PhyUpd1FailCtl - Enables PhyUpd1FailCtr */
25370 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_MASK)
25371 /*! @} */
25372 
25373 /*! @name PLLPWRDN - PLL Power Down */
25374 /*! @{ */
25375 
25376 #define DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_MASK (0x1U)
25377 #define DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_SHIFT (0U)
25378 /*! PllPwrDn - NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten. */
25379 #define DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_MASK)
25380 /*! @} */
25381 
25382 /*! @name PLLRESET - PLL Reset */
25383 /*! @{ */
25384 
25385 #define DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_MASK (0x1U)
25386 #define DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_SHIFT (0U)
25387 /*! PllReset - Reserved */
25388 #define DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_SHIFT)) & DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_MASK)
25389 /*! @} */
25390 
25391 /*! @name PLLCTRL2_P0 - PState dependent PLL Control Register 2 */
25392 /*! @{ */
25393 
25394 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_MASK (0x1FU)
25395 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_SHIFT (0U)
25396 /*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios. */
25397 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_MASK)
25398 /*! @} */
25399 
25400 /*! @name PLLCTRL0 - PLL Control Register 0 */
25401 /*! @{ */
25402 
25403 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_MASK (0x1U)
25404 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_SHIFT (0U)
25405 /*! PllStandby - Connects directly to standby pin of PLL. */
25406 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_MASK)
25407 
25408 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_MASK (0x2U)
25409 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_SHIFT (1U)
25410 /*! PllBypSel - Reserved. */
25411 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_MASK)
25412 
25413 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_MASK (0x4U)
25414 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_SHIFT (2U)
25415 /*! PllX2Mode - conects to x2_mode pins of PLL. */
25416 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_MASK)
25417 
25418 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_MASK (0x8U)
25419 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_SHIFT (3U)
25420 /*! PllOutBypEn - Controls the antiglitch mux on the pllout_x1x2x4 path 1: pllout_x1x2x4 =
25421  *    byp_pllin_x1 0: pllout_x1x2x4 = VCO (SCD) (selected by x2_mode)
25422  */
25423 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_MASK)
25424 
25425 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_MASK (0x10U)
25426 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_SHIFT (4U)
25427 /*! PllPreset - Put PLL in preset mode. */
25428 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_MASK)
25429 
25430 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_MASK (0x20U)
25431 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_SHIFT (5U)
25432 /*! PllBypassMode - PLL Bypass clock mux control. */
25433 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_MASK)
25434 
25435 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_MASK (0x40U)
25436 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_SHIFT (6U)
25437 /*! PllSelDfiFreqRatio - reserved. */
25438 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_MASK)
25439 
25440 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_MASK (0x80U)
25441 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_SHIFT (7U)
25442 /*! PllSyncBusFlush - Used to flush the syncbus logic of the PLL during PHY initialization or LP3 Exit sequence. */
25443 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_MASK)
25444 
25445 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_MASK (0x100U)
25446 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_SHIFT (8U)
25447 /*! PllSyncBusByp - When asserted bypasses the Pll SyncPulse and uses a synchronizer of the same latency. */
25448 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_MASK)
25449 
25450 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_MASK (0x600U)
25451 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_SHIFT (9U)
25452 /*! PllReserved10x9 - for future use. */
25453 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_MASK)
25454 
25455 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_MASK (0x800U)
25456 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_SHIFT (11U)
25457 /*! PllGearShift - Puts PLL in fast re-locking mode 0: default, normal mode 1: fast relock gear */
25458 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_MASK)
25459 
25460 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_MASK (0x1000U)
25461 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_SHIFT (12U)
25462 /*! PllLockCntSel - Lock detect counter selection. */
25463 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_MASK)
25464 
25465 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_MASK (0x6000U)
25466 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_SHIFT (13U)
25467 /*! PllLockPhSel - Lock detect phase selection. */
25468 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_MASK)
25469 
25470 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_MASK (0x8000U)
25471 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_SHIFT (15U)
25472 /*! PllSpareCtrl0 - Spare bits for PLL control. */
25473 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_MASK)
25474 /*! @} */
25475 
25476 /*! @name PLLCTRL1_P0 - PState dependent PLL Control Register 1 */
25477 /*! @{ */
25478 
25479 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_MASK (0x1FU)
25480 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_SHIFT (0U)
25481 /*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL. */
25482 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_MASK)
25483 
25484 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_MASK (0x1E0U)
25485 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_SHIFT (5U)
25486 /*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL. */
25487 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_MASK)
25488 /*! @} */
25489 
25490 /*! @name PLLTST - PLL Testing Control Register */
25491 /*! @{ */
25492 
25493 #define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_MASK (0x1U)
25494 #define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_SHIFT (0U)
25495 /*! PllAnaTstEn - Connects directly to pll_ana_test_en of PLL. */
25496 #define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_MASK)
25497 
25498 #define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_MASK (0x1EU)
25499 #define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_SHIFT (1U)
25500 /*! PllAnaTstSel - Connects directly to pll_ana_test_sel<3:0> of PLL. */
25501 #define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_MASK)
25502 
25503 #define DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_MASK (0x1E0U)
25504 #define DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_SHIFT (5U)
25505 /*! PllDigTstSel - Connects directly to pll_dig_test_sel<2:0> of PLL. */
25506 #define DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_MASK)
25507 /*! @} */
25508 
25509 /*! @name PLLLOCKSTATUS - PLL's pll_lock pin output */
25510 /*! @{ */
25511 
25512 #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_MASK (0x1U)
25513 #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_SHIFT (0U)
25514 /*! PllLockStatus - Directly connected to the pll_Lock output. */
25515 #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_SHIFT)) & DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_MASK)
25516 /*! @} */
25517 
25518 /*! @name PLLTESTMODE_P0 - Additional controls for PLL CP/VCO modes of operation */
25519 /*! @{ */
25520 
25521 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_MASK (0xFFFFU)
25522 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_SHIFT (0U)
25523 /*! PllTestMode_p0 - It is required to use default values for this CSR unless directed otherwise by Synopsys. */
25524 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_MASK)
25525 /*! @} */
25526 
25527 /*! @name PLLCTRL3 - PLL Control Register 3 */
25528 /*! @{ */
25529 
25530 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_MASK (0xFU)
25531 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_SHIFT (0U)
25532 /*! PllSpare - Spare bits for future PLL control modes */
25533 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_MASK)
25534 
25535 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_MASK (0x1F0U)
25536 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_SHIFT (4U)
25537 /*! PllMaxRange - connects directly to maxrange of PLL. */
25538 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_MASK)
25539 
25540 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_MASK (0x3E00U)
25541 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_SHIFT (9U)
25542 /*! PllDacValIn - connects directly to dacval_in<4:0> of PLL. */
25543 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_MASK)
25544 
25545 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_MASK (0x4000U)
25546 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_SHIFT (14U)
25547 /*! PllForceCal - connects directly to force_cal of PLL. */
25548 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_MASK)
25549 
25550 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_MASK (0x8000U)
25551 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_SHIFT (15U)
25552 /*! PllEnCal - Calibration will run at standby rising edge if en_cal=1 if en_cal=0 calibration will not run */
25553 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL(x)  (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_MASK)
25554 /*! @} */
25555 
25556 /*! @name PLLCTRL4_P0 - PState dependent PLL Control Register 4 */
25557 /*! @{ */
25558 
25559 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_MASK (0x1FU)
25560 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_SHIFT (0U)
25561 /*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL. */
25562 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_MASK)
25563 
25564 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_MASK (0x1E0U)
25565 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_SHIFT (5U)
25566 /*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL. */
25567 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_MASK)
25568 /*! @} */
25569 
25570 /*! @name PLLENDOFCAL - PLL's eoc (end of calibration) output */
25571 /*! @{ */
25572 
25573 #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_MASK (0x1U)
25574 #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_SHIFT (0U)
25575 /*! PllEndofCal - Directly connected to the pll's eoc output. */
25576 #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_MASK)
25577 /*! @} */
25578 
25579 /*! @name PLLSTANDBYEFF - PLL's standby_eff (effective standby) output */
25580 /*! @{ */
25581 
25582 #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_MASK (0x1U)
25583 #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_SHIFT (0U)
25584 /*! PllStandbyEff - Returns state off PLL standby. */
25585 #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_SHIFT)) & DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_MASK)
25586 /*! @} */
25587 
25588 /*! @name PLLDACVALOUT - PLL's Dacval_out output */
25589 /*! @{ */
25590 
25591 #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_MASK (0x1FU)
25592 #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_SHIFT (0U)
25593 /*! PllDacValOut - Directly connected to the pll's dacval_out output. */
25594 #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_SHIFT)) & DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_MASK)
25595 /*! @} */
25596 
25597 /*! @name LCDLDBGCNTL - Controls for use in observing and testing the LCDLs. */
25598 /*! @{ */
25599 
25600 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_MASK (0x1FFU)
25601 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_SHIFT (0U)
25602 /*! LcdlFineOvrVal - Value forced as the initial value while LcdlTstEnable=1 and LcdlFineOvr. */
25603 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_MASK)
25604 
25605 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_MASK (0x200U)
25606 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_SHIFT (9U)
25607 /*! LcdlFineOvr - Forces the value of the present LCDL 1UI estimate code to be LcdlFineOvrVal for all LCDLs. */
25608 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_MASK)
25609 
25610 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_MASK (0x400U)
25611 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_SHIFT (10U)
25612 /*! LcdlFineSnap - Latch enable for reading the present LCDL 1UI estimate code in LcdlFineSnapVal
25613  *    and the present phase-detector value in LcdlPhdSnapVal
25614  */
25615 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_MASK)
25616 
25617 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_MASK (0x800U)
25618 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_SHIFT (11U)
25619 /*! LcdlTstEnable - Enables the debug/test operations and status Ovr,Snap,StickyLock,StickyUnlock, and LiveLock. */
25620 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_MASK)
25621 
25622 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_MASK (0xF000U)
25623 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_SHIFT (12U)
25624 /*! LcdlStatusSel - Selects the LCDL status, from among the status for the 16 LCDLs in the DBYTE,
25625  *    for reading via Register DxLcdlStatus and an LCDL from among the LCDLs in the ANIB for reading
25626  *    via Register AcLcdlStatus LcdlStatusSel source for DxLcdlStatus source for AcLcdlStatus 15
25627  *    lcdl_rxclk1t reserved 14 lcdl_rxclk0t reserved 13 lcdl_rxclk1c reserved 12 lcdl_rxclk0c reserved
25628  *    11 lcdl_rxen1 anib11-tx 10 lcdl_rxen0 anib10-tx 9 lcdl_txln9 (dqs-lower) anib9-tx 8 lcdl_txln8
25629  *    (dm/dqs-upper) anib8-tx 7 lcdl_txln7 (dq7) anib7-tx 6 lcdl_txln6 (dq6) anib6-tx 5 lcdl_txln5
25630  *    (dq5) anib5-tx 4 lcdl_txln4 (dq4) anib4-tx 3 lcdl_txln3 (dq3) anib3-tx 2 lcdl_txln2 (dq2)
25631  *    anib2-tx 1 lcdl_txln1 (dq1) anib1-tx 0 lcdl_txln0 (dq0) anib0-tx
25632  */
25633 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_MASK)
25634 /*! @} */
25635 
25636 /*! @name ACLCDLSTATUS - Debug status of the DBYTE LCDL */
25637 /*! @{ */
25638 
25639 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_MASK (0x3FFU)
25640 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_SHIFT (0U)
25641 /*! AcLcdlFineSnapVal - Value of the LCDL 1UI estimate code, latched by pulse on csrLcdlFineSnap while csr LcdlTstEnable=1. */
25642 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_MASK)
25643 
25644 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_MASK (0x400U)
25645 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_SHIFT (10U)
25646 /*! AcLcdlPhdSnapVal - Value of the LCDL phase-detector output, latched by pulse on LcdlFineSnap while csr LcdlTstEnable=1. */
25647 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_MASK)
25648 
25649 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_MASK (0x800U)
25650 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_SHIFT (11U)
25651 /*! AcLcdlStickyLock - latched value of whether the LCDL ever achieved lock after the assertion of LcdlTstEnable. */
25652 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_MASK)
25653 
25654 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_MASK (0x1000U)
25655 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_SHIFT (12U)
25656 /*! AcLcdlStickyUnlock - latched value of whether the LCDL ever lost lock after the assertion of LcdlTstEnable. */
25657 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_MASK)
25658 
25659 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_MASK (0x2000U)
25660 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_SHIFT (13U)
25661 /*! AcLcdlLiveLock - present value of whether the LCDL is locked, valid when LcdlTstEnable=1. */
25662 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_MASK)
25663 /*! @} */
25664 
25665 /*! @name CUSTPHYREV - Customer settable by the customer */
25666 /*! @{ */
25667 
25668 #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK (0x3FU)
25669 #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT (0U)
25670 /*! CUSTPHYREV - The customer settable PHY version number. */
25671 #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT)) & DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK)
25672 /*! @} */
25673 
25674 /*! @name PHYREV - The hardware version of this PHY, excluding the PUB */
25675 /*! @{ */
25676 
25677 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK    (0xFU)
25678 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT   (0U)
25679 /*! PHYMNR - Indicates minor update of the PHY. */
25680 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x)      (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK)
25681 
25682 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK    (0xF0U)
25683 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT   (4U)
25684 /*! PHYMDR - Indicates moderate revision of the PHY. */
25685 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x)      (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK)
25686 
25687 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK    (0xFF00U)
25688 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT   (8U)
25689 /*! PHYMJR - Indicates major revision of the PHY. */
25690 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x)      (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK)
25691 /*! @} */
25692 
25693 /*! @name LP3EXITSEQ0BSTARTVECTOR - Start vector value to be used for LP3-exit or Init PIE Sequence */
25694 /*! @{ */
25695 
25696 #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK (0xFU)
25697 #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_SHIFT (0U)
25698 /*! LP3ExitSeq0BStartVecPllEnabled - PIE Start Vector value to be used for LP3-exit or Init and target P-state has PLL enabled */
25699 #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK)
25700 
25701 #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK (0xF0U)
25702 #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_SHIFT (4U)
25703 /*! LP3ExitSeq0BStartVecPllBypassed - PIE Start Vector value to be used for LP3-exit or Init and target P-state has PLL bypassed */
25704 #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_SHIFT)) & DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK)
25705 /*! @} */
25706 
25707 /*! @name DFIFREQXLAT0 - DFI Frequency Translation Register 0 */
25708 /*! @{ */
25709 
25710 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_MASK (0xFU)
25711 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_SHIFT (0U)
25712 /*! DfiFreqXlatVal0 - The sequencer start vector used when dfi_freq value is 0. */
25713 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_MASK)
25714 
25715 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_MASK (0xF0U)
25716 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_SHIFT (4U)
25717 /*! DfiFreqXlatVal1 - The sequencer start vector used when dfi_freq value is 1. */
25718 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_MASK)
25719 
25720 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_MASK (0xF00U)
25721 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_SHIFT (8U)
25722 /*! DfiFreqXlatVal2 - The sequencer start vector used when dfi_freq value is 2. */
25723 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_MASK)
25724 
25725 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_MASK (0xF000U)
25726 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_SHIFT (12U)
25727 /*! DfiFreqXlatVal3 - The sequencer start vector used when dfi_freq value is 3. */
25728 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_MASK)
25729 /*! @} */
25730 
25731 /*! @name DFIFREQXLAT1 - DFI Frequency Translation Register 1 */
25732 /*! @{ */
25733 
25734 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_MASK (0xFU)
25735 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_SHIFT (0U)
25736 /*! DfiFreqXlatVal4 - The sequencer start vector used when dfi_freq value is 4. */
25737 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_MASK)
25738 
25739 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_MASK (0xF0U)
25740 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_SHIFT (4U)
25741 /*! DfiFreqXlatVal5 - The sequencer start vector used when dfi_freq value is 5. */
25742 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_MASK)
25743 
25744 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_MASK (0xF00U)
25745 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_SHIFT (8U)
25746 /*! DfiFreqXlatVal6 - The sequencer start vector used when dfi_freq value is 6. */
25747 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_MASK)
25748 
25749 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_MASK (0xF000U)
25750 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_SHIFT (12U)
25751 /*! DfiFreqXlatVal7 - The sequencer start vector used when dfi_freq value is 7. */
25752 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_MASK)
25753 /*! @} */
25754 
25755 /*! @name DFIFREQXLAT2 - DFI Frequency Translation Register 2 */
25756 /*! @{ */
25757 
25758 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_MASK (0xFU)
25759 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_SHIFT (0U)
25760 /*! DfiFreqXlatVal8 - The sequencer start vector used when dfi_freq value is 8. */
25761 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_MASK)
25762 
25763 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_MASK (0xF0U)
25764 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_SHIFT (4U)
25765 /*! DfiFreqXlatVal9 - The sequencer start vector used when dfi_freq value is 9. */
25766 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_MASK)
25767 
25768 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_MASK (0xF00U)
25769 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_SHIFT (8U)
25770 /*! DfiFreqXlatVal10 - The sequencer start vector used when dfi_freq value is 10. */
25771 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_MASK)
25772 
25773 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_MASK (0xF000U)
25774 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_SHIFT (12U)
25775 /*! DfiFreqXlatVal11 - The sequencer start vector used when dfi_freq value is 11. */
25776 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_MASK)
25777 /*! @} */
25778 
25779 /*! @name DFIFREQXLAT3 - DFI Frequency Translation Register 3 */
25780 /*! @{ */
25781 
25782 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_MASK (0xFU)
25783 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_SHIFT (0U)
25784 /*! DfiFreqXlatVal12 - The sequencer start vector used when dfi_freq value is 12. */
25785 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_MASK)
25786 
25787 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_MASK (0xF0U)
25788 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_SHIFT (4U)
25789 /*! DfiFreqXlatVal13 - The sequencer start vector used when dfi_freq value is 13. */
25790 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_MASK)
25791 
25792 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_MASK (0xF00U)
25793 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_SHIFT (8U)
25794 /*! DfiFreqXlatVal14 - The sequencer start vector used when dfi_freq value is 14. */
25795 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_MASK)
25796 
25797 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_MASK (0xF000U)
25798 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_SHIFT (12U)
25799 /*! DfiFreqXlatVal15 - The sequencer start vector used when dfi_freq value is 15. */
25800 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_MASK)
25801 /*! @} */
25802 
25803 /*! @name DFIFREQXLAT4 - DFI Frequency Translation Register 4 */
25804 /*! @{ */
25805 
25806 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_MASK (0xFU)
25807 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_SHIFT (0U)
25808 /*! DfiFreqXlatVal16 - The sequencer start vector used when dfi_freq value is 16. */
25809 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_MASK)
25810 
25811 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_MASK (0xF0U)
25812 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_SHIFT (4U)
25813 /*! DfiFreqXlatVal17 - The sequencer start vector used when dfi_freq value is 17. */
25814 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_MASK)
25815 
25816 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_MASK (0xF00U)
25817 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_SHIFT (8U)
25818 /*! DfiFreqXlatVal18 - The sequencer start vector used when dfi_freq value is 18. */
25819 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_MASK)
25820 
25821 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_MASK (0xF000U)
25822 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_SHIFT (12U)
25823 /*! DfiFreqXlatVal19 - The sequencer start vector used when dfi_freq value is 19. */
25824 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_MASK)
25825 /*! @} */
25826 
25827 /*! @name DFIFREQXLAT5 - DFI Frequency Translation Register 5 */
25828 /*! @{ */
25829 
25830 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_MASK (0xFU)
25831 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_SHIFT (0U)
25832 /*! DfiFreqXlatVal20 - The sequencer start vector used when dfi_freq value is 20. */
25833 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_MASK)
25834 
25835 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_MASK (0xF0U)
25836 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_SHIFT (4U)
25837 /*! DfiFreqXlatVal21 - The sequencer start vector used when dfi_freq value is 21. */
25838 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_MASK)
25839 
25840 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_MASK (0xF00U)
25841 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_SHIFT (8U)
25842 /*! DfiFreqXlatVal22 - The sequencer start vector used when dfi_freq value is 22. */
25843 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_MASK)
25844 
25845 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_MASK (0xF000U)
25846 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_SHIFT (12U)
25847 /*! DfiFreqXlatVal23 - The sequencer start vector used when dfi_freq value is 23. */
25848 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_MASK)
25849 /*! @} */
25850 
25851 /*! @name DFIFREQXLAT6 - DFI Frequency Translation Register 6 */
25852 /*! @{ */
25853 
25854 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_MASK (0xFU)
25855 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_SHIFT (0U)
25856 /*! DfiFreqXlatVal24 - The sequencer start vector used when dfi_freq value is 24. */
25857 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_MASK)
25858 
25859 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_MASK (0xF0U)
25860 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_SHIFT (4U)
25861 /*! DfiFreqXlatVal25 - The sequencer start vector used when dfi_freq value is 25. */
25862 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_MASK)
25863 
25864 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_MASK (0xF00U)
25865 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_SHIFT (8U)
25866 /*! DfiFreqXlatVal26 - The sequencer start vector used when dfi_freq value is 26. */
25867 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_MASK)
25868 
25869 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_MASK (0xF000U)
25870 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_SHIFT (12U)
25871 /*! DfiFreqXlatVal27 - The sequencer start vector used when dfi_freq value is 27. */
25872 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_MASK)
25873 /*! @} */
25874 
25875 /*! @name DFIFREQXLAT7 - DFI Frequency Translation Register 7 */
25876 /*! @{ */
25877 
25878 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_MASK (0xFU)
25879 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_SHIFT (0U)
25880 /*! DfiFreqXlatVal28 - The sequencer start vector used when dfi_freq value is 28. */
25881 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_MASK)
25882 
25883 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_MASK (0xF0U)
25884 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_SHIFT (4U)
25885 /*! DfiFreqXlatVal29 - The sequencer start vector used when dfi_freq value is 29. */
25886 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_MASK)
25887 
25888 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_MASK (0xF00U)
25889 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_SHIFT (8U)
25890 /*! DfiFreqXlatVal30 - The sequencer start vector used when dfi_freq value is 30. */
25891 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_MASK)
25892 
25893 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_MASK (0xF000U)
25894 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_SHIFT (12U)
25895 /*! DfiFreqXlatVal31 - The sequencer start vector used when dfi_freq value is 31. */
25896 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_MASK)
25897 /*! @} */
25898 
25899 /*! @name TXRDPTRINIT - TxRdPtrInit control register */
25900 /*! @{ */
25901 
25902 #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_MASK (0x1U)
25903 #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_SHIFT (0U)
25904 /*! TxRdPtrInit - This register directly controls TxRdPtrInit, and is meant to be written by the
25905  *    PState sequencer as part of the power state switching sequence.
25906  */
25907 #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_SHIFT)) & DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_MASK)
25908 /*! @} */
25909 
25910 /*! @name DFIINITCOMPLETE - DFI Init Complete control */
25911 /*! @{ */
25912 
25913 #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_MASK (0x1U)
25914 #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_SHIFT (0U)
25915 /*! DfiInitComplete - This register directly controls DfiInitComplete, and is meant to be written by
25916  *    the PState sequencer as part of the power state switching sequence.
25917  */
25918 #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_MASK)
25919 /*! @} */
25920 
25921 /*! @name DFIFREQRATIO_P0 - DFI Frequency Ratio */
25922 /*! @{ */
25923 
25924 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_MASK (0x3U)
25925 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_SHIFT (0U)
25926 /*! DfiFreqRatio_p0 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
25927  *    1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
25928  */
25929 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_MASK)
25930 /*! @} */
25931 
25932 /*! @name RXFIFOCHECKS - Enable more frequent consistency checks of the RX FIFOs */
25933 /*! @{ */
25934 
25935 #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_MASK (0x1U)
25936 #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_SHIFT (0U)
25937 /*! DoFrequentRxFifoChecks - When 0, read data FIFO pointer consistency checks are performed only during sideband transactions (i. */
25938 #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_MASK)
25939 /*! @} */
25940 
25941 /*! @name MTESTDTOCTRL -  */
25942 /*! @{ */
25943 
25944 #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_MASK (0x1U)
25945 #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_SHIFT (0U)
25946 /*! MTestDtoCtrl - MTESTdtoEn==[0], dwc_ddrphy_dto will be squelched (0) MTESTdtoEn==[1],
25947  *    dwc_ddrphy_dto will reflect the observability signal multiplexed on MTestCombo
25948  */
25949 #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_MASK)
25950 /*! @} */
25951 
25952 /*! @name MAPCAA0TODFI - Maps PHY CAA lane 0 from dfi0_address of the index of the register contents */
25953 /*! @{ */
25954 
25955 #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_MASK (0xFU)
25956 #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_SHIFT (0U)
25957 /*! MapCAA0toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 0. */
25958 #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_MASK)
25959 /*! @} */
25960 
25961 /*! @name MAPCAA1TODFI - Maps PHY CAA lane 1 from dfi0_address of the index of the register contents */
25962 /*! @{ */
25963 
25964 #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_MASK (0xFU)
25965 #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_SHIFT (0U)
25966 /*! MapCAA1toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 1. */
25967 #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_MASK)
25968 /*! @} */
25969 
25970 /*! @name MAPCAA2TODFI - Maps PHY CAA lane 2 from dfi0_address of the index of the register contents */
25971 /*! @{ */
25972 
25973 #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_MASK (0xFU)
25974 #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_SHIFT (0U)
25975 /*! MapCAA2toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 2. */
25976 #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_MASK)
25977 /*! @} */
25978 
25979 /*! @name MAPCAA3TODFI - Maps PHY CAA lane 3 from dfi0_address of the index of the register contents */
25980 /*! @{ */
25981 
25982 #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_MASK (0xFU)
25983 #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_SHIFT (0U)
25984 /*! MapCAA3toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 3. */
25985 #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_MASK)
25986 /*! @} */
25987 
25988 /*! @name MAPCAA4TODFI - Maps PHY CAA lane 4 from dfi0_address of the index of the register contents */
25989 /*! @{ */
25990 
25991 #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_MASK (0xFU)
25992 #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_SHIFT (0U)
25993 /*! MapCAA4toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 4. */
25994 #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_MASK)
25995 /*! @} */
25996 
25997 /*! @name MAPCAA5TODFI - Maps PHY CAA lane 5 from dfi0_address of the index of the register contents */
25998 /*! @{ */
25999 
26000 #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_MASK (0xFU)
26001 #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_SHIFT (0U)
26002 /*! MapCAA5toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 5. */
26003 #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_MASK)
26004 /*! @} */
26005 
26006 /*! @name MAPCAA6TODFI - Maps PHY CAA lane 6 from dfi0_address of the index of the register contents */
26007 /*! @{ */
26008 
26009 #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_MASK (0xFU)
26010 #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_SHIFT (0U)
26011 /*! MapCAA6toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 6. */
26012 #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_MASK)
26013 /*! @} */
26014 
26015 /*! @name MAPCAA7TODFI - Maps PHY CAA lane 7 from dfi0_address of the index of the register contents */
26016 /*! @{ */
26017 
26018 #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_MASK (0xFU)
26019 #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_SHIFT (0U)
26020 /*! MapCAA7toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 7. */
26021 #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_MASK)
26022 /*! @} */
26023 
26024 /*! @name MAPCAA8TODFI - Maps PHY CAA lane 8 from dfi0_address of the index of the register contents */
26025 /*! @{ */
26026 
26027 #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_MASK (0xFU)
26028 #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_SHIFT (0U)
26029 /*! MapCAA8toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 8. */
26030 #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_MASK)
26031 /*! @} */
26032 
26033 /*! @name MAPCAA9TODFI - Maps PHY CAA lane 9 from dfi0_address of the index of the register contents */
26034 /*! @{ */
26035 
26036 #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_MASK (0xFU)
26037 #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_SHIFT (0U)
26038 /*! MapCAA9toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 9. */
26039 #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_MASK)
26040 /*! @} */
26041 
26042 /*! @name MAPCAB0TODFI - Maps PHY CAB lane 0 from dfi1_address of the index of the register contents */
26043 /*! @{ */
26044 
26045 #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_MASK (0xFU)
26046 #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_SHIFT (0U)
26047 /*! MapCAB0toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 0. */
26048 #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_MASK)
26049 /*! @} */
26050 
26051 /*! @name MAPCAB1TODFI - Maps PHY CAB lane 1 from dfi1_address of the index of the register contents */
26052 /*! @{ */
26053 
26054 #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_MASK (0xFU)
26055 #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_SHIFT (0U)
26056 /*! MapCAB1toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 1. */
26057 #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_MASK)
26058 /*! @} */
26059 
26060 /*! @name MAPCAB2TODFI - Maps PHY CAB lane 2 from dfi1_address of the index of the register contents */
26061 /*! @{ */
26062 
26063 #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_MASK (0xFU)
26064 #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_SHIFT (0U)
26065 /*! MapCAB2toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 2. */
26066 #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_MASK)
26067 /*! @} */
26068 
26069 /*! @name MAPCAB3TODFI - Maps PHY CAB lane 3 from dfi1_address of the index of the register contents */
26070 /*! @{ */
26071 
26072 #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_MASK (0xFU)
26073 #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_SHIFT (0U)
26074 /*! MapCAB3toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 3. */
26075 #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_MASK)
26076 /*! @} */
26077 
26078 /*! @name MAPCAB4TODFI - Maps PHY CAB lane 4 from dfi1_address of the index of the register contents */
26079 /*! @{ */
26080 
26081 #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_MASK (0xFU)
26082 #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_SHIFT (0U)
26083 /*! MapCAB4toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 4. */
26084 #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_MASK)
26085 /*! @} */
26086 
26087 /*! @name MAPCAB5TODFI - Maps PHY CAB lane 5 from dfi1_address of the index of the register contents */
26088 /*! @{ */
26089 
26090 #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_MASK (0xFU)
26091 #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_SHIFT (0U)
26092 /*! MapCAB5toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 5. */
26093 #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_MASK)
26094 /*! @} */
26095 
26096 /*! @name MAPCAB6TODFI - Maps PHY CAB lane 6 from dfi1_address of the index of the register contents */
26097 /*! @{ */
26098 
26099 #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_MASK (0xFU)
26100 #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_SHIFT (0U)
26101 /*! MapCAB6toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 6. */
26102 #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_MASK)
26103 /*! @} */
26104 
26105 /*! @name MAPCAB7TODFI - Maps PHY CAB lane 7 from dfi1_address of the index of the register contents */
26106 /*! @{ */
26107 
26108 #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_MASK (0xFU)
26109 #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_SHIFT (0U)
26110 /*! MapCAB7toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 7. */
26111 #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_MASK)
26112 /*! @} */
26113 
26114 /*! @name MAPCAB8TODFI - Maps PHY CAB lane 8 from dfi1_address of the index of the register contents */
26115 /*! @{ */
26116 
26117 #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_MASK (0xFU)
26118 #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_SHIFT (0U)
26119 /*! MapCAB8toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 8. */
26120 #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_MASK)
26121 /*! @} */
26122 
26123 /*! @name MAPCAB9TODFI - Maps PHY CAB lane 9 from dfi1_address of the index of the register contents */
26124 /*! @{ */
26125 
26126 #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_MASK (0xFU)
26127 #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_SHIFT (0U)
26128 /*! MapCAB9toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 9. */
26129 #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_MASK)
26130 /*! @} */
26131 
26132 /*! @name PHYINTERRUPTENABLE - Interrupt Enable Bits */
26133 /*! @{ */
26134 
26135 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_MASK (0x1U)
26136 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_SHIFT (0U)
26137 /*! PhyTrngCmpltEn - Enable for the PHY Training Complete interrupt. */
26138 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_MASK)
26139 
26140 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_MASK (0x2U)
26141 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_SHIFT (1U)
26142 /*! PhyInitCmpltEn - Enable for the PHY Initialization Complete interrupt. */
26143 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_MASK)
26144 
26145 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_MASK (0x4U)
26146 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_SHIFT (2U)
26147 /*! PhyTrngFailEn - Enable for the PHY Training Failure interrupt. */
26148 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_MASK)
26149 
26150 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_MASK (0xF8U)
26151 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_SHIFT (3U)
26152 /*! PhyFWReservedEn - Reserved */
26153 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_MASK)
26154 
26155 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_MASK (0x300U)
26156 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_SHIFT (8U)
26157 /*! PhyVTDriftAlarmEn - Enable for the PHY VT Drift Alarm interrupts. */
26158 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_MASK)
26159 
26160 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_MASK (0x400U)
26161 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_SHIFT (10U)
26162 /*! PhyRxFifoCheckEn - Enable for the RxFifo Pointers Check Interrupt 0 : Interrupt not enabled 1 : Interrupt enabled */
26163 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_MASK)
26164 
26165 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_MASK (0xF800U)
26166 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_SHIFT (11U)
26167 /*! PhyHWReservedEn - Reserved */
26168 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_MASK)
26169 /*! @} */
26170 
26171 /*! @name PHYINTERRUPTFWCONTROL - Interrupt Firmware Control Bits */
26172 /*! @{ */
26173 
26174 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_MASK (0x1U)
26175 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_SHIFT (0U)
26176 /*! PhyTrngCmpltFW - PHY Training Complete Firmware interrupt. */
26177 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_MASK)
26178 
26179 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_MASK (0x2U)
26180 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_SHIFT (1U)
26181 /*! PhyInitCmpltFW - PHY Initialization Complete Firmware interrupt. */
26182 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_MASK)
26183 
26184 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_MASK (0x4U)
26185 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_SHIFT (2U)
26186 /*! PhyTrngFailFW - PHY Training Failure Firmware interrupt. */
26187 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_MASK)
26188 
26189 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_MASK (0xF8U)
26190 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_SHIFT (3U)
26191 /*! PhyFWReservedFW - Reserved */
26192 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_MASK)
26193 /*! @} */
26194 
26195 /*! @name PHYINTERRUPTMASK - Interrupt Mask Bits */
26196 /*! @{ */
26197 
26198 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_MASK (0x1U)
26199 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_SHIFT (0U)
26200 /*! PhyTrngCmpltMsk - Mask for the PHY Training Complete interrupt. */
26201 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_MASK)
26202 
26203 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_MASK (0x2U)
26204 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_SHIFT (1U)
26205 /*! PhyInitCmpltMsk - Mask for the PHY Initialization Complete interrupt. */
26206 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_MASK)
26207 
26208 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_MASK (0x4U)
26209 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_SHIFT (2U)
26210 /*! PhyTrngFailMsk - Mask for the PHY Training Failure interrupt. */
26211 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_MASK)
26212 
26213 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_MASK (0xF8U)
26214 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_SHIFT (3U)
26215 /*! PhyFWReservedMsk - Reserved */
26216 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_MASK)
26217 
26218 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_MASK (0x300U)
26219 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_SHIFT (8U)
26220 /*! PhyVTDriftAlarmMsk - Mask for the PHY VT Drift Alarm interrupts. */
26221 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_MASK)
26222 
26223 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_MASK (0x400U)
26224 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_SHIFT (10U)
26225 /*! PhyRxFifoCheckMsk - Mask for the RxFifo Pointers Check Interrupt 0 : Interrupt not masked 1 : Interrupt masked */
26226 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_MASK)
26227 
26228 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_MASK (0xF800U)
26229 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_SHIFT (11U)
26230 /*! PhyHWReservedMsk - Reserved */
26231 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_MASK)
26232 /*! @} */
26233 
26234 /*! @name PHYINTERRUPTCLEAR - Interrupt Clear Bits */
26235 /*! @{ */
26236 
26237 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_MASK (0x1U)
26238 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_SHIFT (0U)
26239 /*! PhyTrngCmpltClr - Clear for the PHY Training Complete interrupt. */
26240 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_MASK)
26241 
26242 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_MASK (0x2U)
26243 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_SHIFT (1U)
26244 /*! PhyInitCmpltClr - Clear for the PHY Initialization Complete interrupt. */
26245 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_MASK)
26246 
26247 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_MASK (0x4U)
26248 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_SHIFT (2U)
26249 /*! PhyTrngFailClr - Clear for the PHY Training Failure interrupt. */
26250 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_MASK)
26251 
26252 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_MASK (0xF8U)
26253 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_SHIFT (3U)
26254 /*! PhyFWReservedClr - Reserved */
26255 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_MASK)
26256 
26257 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_MASK (0x300U)
26258 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_SHIFT (8U)
26259 /*! PhyVTDriftAlarmClr - Clear for the PHY VT Drift Alarm interrupt. */
26260 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_MASK)
26261 
26262 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_MASK (0x400U)
26263 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_SHIFT (10U)
26264 /*! PhyRxFifoCheckClr - Clear for the RxFifo Pointers Check Interrupt 0 : Interrupt not affected 1 : Interrupt cleared */
26265 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_MASK)
26266 
26267 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_MASK (0xF800U)
26268 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_SHIFT (11U)
26269 /*! PhyHWReservedClr - Reserved */
26270 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_MASK)
26271 /*! @} */
26272 
26273 /*! @name PHYINTERRUPTSTATUS - Interrupt Status Bits */
26274 /*! @{ */
26275 
26276 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_MASK (0x1U)
26277 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_SHIFT (0U)
26278 /*! PhyTrngCmplt - PHY Training Complete interrupt. */
26279 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_MASK)
26280 
26281 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_MASK (0x2U)
26282 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_SHIFT (1U)
26283 /*! PhyInitCmplt - PHY Initialization Complete interrupt. */
26284 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_MASK)
26285 
26286 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_MASK (0x4U)
26287 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_SHIFT (2U)
26288 /*! PhyTrngFail - PHY Training Failure interrupt. */
26289 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_MASK)
26290 
26291 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_MASK (0xF8U)
26292 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_SHIFT (3U)
26293 /*! PhyFWReserved - Reserved */
26294 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_MASK)
26295 
26296 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_MASK (0x300U)
26297 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_SHIFT (8U)
26298 /*! VTDriftAlarm - PHY VT Drift Alarm interrupt. */
26299 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_MASK)
26300 
26301 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_MASK (0x400U)
26302 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_SHIFT (10U)
26303 /*! PhyRxFifoCheck - A mechanism in the PHY checks the Read Fifo pointers for consistency at times they are idle. */
26304 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_MASK)
26305 
26306 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_MASK (0xF800U)
26307 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_SHIFT (11U)
26308 /*! PhyHWReserved - Reserved */
26309 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_MASK)
26310 /*! @} */
26311 
26312 /*! @name HWTSWIZZLEHWTADDRESS0 - Signal swizzle selection for HWT swizzle */
26313 /*! @{ */
26314 
26315 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_MASK (0x1FU)
26316 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_SHIFT (0U)
26317 /*! HwtSwizzleHwtAddress0 - This set of registers is used in DDR3/DDR4 mode where a user has re-mapped the DFI inputs to the PHY. */
26318 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_MASK)
26319 /*! @} */
26320 
26321 /*! @name HWTSWIZZLEHWTADDRESS1 - Signal swizzle selection for HWT swizzle */
26322 /*! @{ */
26323 
26324 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_MASK (0x1FU)
26325 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_SHIFT (0U)
26326 /*! HwtSwizzleHwtAddress1 - See Description of HwtSwizzleHwtAddress0 for details. */
26327 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_MASK)
26328 /*! @} */
26329 
26330 /*! @name HWTSWIZZLEHWTADDRESS2 - Signal swizzle selection for HWT swizzle */
26331 /*! @{ */
26332 
26333 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_MASK (0x1FU)
26334 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_SHIFT (0U)
26335 /*! HwtSwizzleHwtAddress2 - See Description of HwtSwizzleHwtAddress0 for details. */
26336 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_MASK)
26337 /*! @} */
26338 
26339 /*! @name HWTSWIZZLEHWTADDRESS3 - Signal swizzle selection for HWT swizzle */
26340 /*! @{ */
26341 
26342 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_MASK (0x1FU)
26343 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_SHIFT (0U)
26344 /*! HwtSwizzleHwtAddress3 - See Description of HwtSwizzleHwtAddress0 for details. */
26345 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_MASK)
26346 /*! @} */
26347 
26348 /*! @name HWTSWIZZLEHWTADDRESS4 - Signal swizzle selection for HWT swizzle */
26349 /*! @{ */
26350 
26351 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_MASK (0x1FU)
26352 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_SHIFT (0U)
26353 /*! HwtSwizzleHwtAddress4 - See Description of HwtSwizzleHwtAddress0 for details. */
26354 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_MASK)
26355 /*! @} */
26356 
26357 /*! @name HWTSWIZZLEHWTADDRESS5 - Signal swizzle selection for HWT swizzle */
26358 /*! @{ */
26359 
26360 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_MASK (0x1FU)
26361 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_SHIFT (0U)
26362 /*! HwtSwizzleHwtAddress5 - See Description of HwtSwizzleHwtAddress0 for details. */
26363 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_MASK)
26364 /*! @} */
26365 
26366 /*! @name HWTSWIZZLEHWTADDRESS6 - Signal swizzle selection for HWT swizzle */
26367 /*! @{ */
26368 
26369 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_MASK (0x1FU)
26370 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_SHIFT (0U)
26371 /*! HwtSwizzleHwtAddress6 - See Description of HwtSwizzleHwtAddress0 for details. */
26372 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_MASK)
26373 /*! @} */
26374 
26375 /*! @name HWTSWIZZLEHWTADDRESS7 - Signal swizzle selection for HWT swizzle */
26376 /*! @{ */
26377 
26378 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_MASK (0x1FU)
26379 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_SHIFT (0U)
26380 /*! HwtSwizzleHwtAddress7 - See Description of HwtSwizzleHwtAddress0 for details. */
26381 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_MASK)
26382 /*! @} */
26383 
26384 /*! @name HWTSWIZZLEHWTADDRESS8 - Signal swizzle selection for HWT swizzle */
26385 /*! @{ */
26386 
26387 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_MASK (0x1FU)
26388 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_SHIFT (0U)
26389 /*! HwtSwizzleHwtAddress8 - See Description of HwtSwizzleHwtAddress0 for details. */
26390 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_MASK)
26391 /*! @} */
26392 
26393 /*! @name HWTSWIZZLEHWTADDRESS9 - Signal swizzle selection for HWT swizzle */
26394 /*! @{ */
26395 
26396 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_MASK (0x1FU)
26397 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_SHIFT (0U)
26398 /*! HwtSwizzleHwtAddress9 - See Description of HwtSwizzleHwtAddress0 for details. */
26399 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_MASK)
26400 /*! @} */
26401 
26402 /*! @name HWTSWIZZLEHWTADDRESS10 - Signal swizzle selection for HWT swizzle */
26403 /*! @{ */
26404 
26405 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_MASK (0x1FU)
26406 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_SHIFT (0U)
26407 /*! HwtSwizzleHwtAddress10 - See Description of HwtSwizzleHwtAddress0 for details. */
26408 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_MASK)
26409 /*! @} */
26410 
26411 /*! @name HWTSWIZZLEHWTADDRESS11 - Signal swizzle selection for HWT swizzle */
26412 /*! @{ */
26413 
26414 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_MASK (0x1FU)
26415 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_SHIFT (0U)
26416 /*! HwtSwizzleHwtAddress11 - See Description of HwtSwizzleHwtAddress0 for details. */
26417 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_MASK)
26418 /*! @} */
26419 
26420 /*! @name HWTSWIZZLEHWTADDRESS12 - Signal swizzle selection for HWT swizzle */
26421 /*! @{ */
26422 
26423 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_MASK (0x1FU)
26424 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_SHIFT (0U)
26425 /*! HwtSwizzleHwtAddress12 - See Description of HwtSwizzleHwtAddress0 for details. */
26426 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_MASK)
26427 /*! @} */
26428 
26429 /*! @name HWTSWIZZLEHWTADDRESS13 - Signal swizzle selection for HWT swizzle */
26430 /*! @{ */
26431 
26432 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_MASK (0x1FU)
26433 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_SHIFT (0U)
26434 /*! HwtSwizzleHwtAddress13 - See Description of HwtSwizzleHwtAddress0 for details. */
26435 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_MASK)
26436 /*! @} */
26437 
26438 /*! @name HWTSWIZZLEHWTADDRESS14 - Signal swizzle selection for HWT swizzle */
26439 /*! @{ */
26440 
26441 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_MASK (0x1FU)
26442 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_SHIFT (0U)
26443 /*! HwtSwizzleHwtAddress14 - See Description of HwtSwizzleHwtAddress0 for details. */
26444 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_MASK)
26445 /*! @} */
26446 
26447 /*! @name HWTSWIZZLEHWTADDRESS15 - Signal swizzle selection for HWT swizzle */
26448 /*! @{ */
26449 
26450 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_MASK (0x1FU)
26451 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_SHIFT (0U)
26452 /*! HwtSwizzleHwtAddress15 - See Description of HwtSwizzleHwtAddress0 for details. */
26453 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_MASK)
26454 /*! @} */
26455 
26456 /*! @name HWTSWIZZLEHWTADDRESS17 - Signal swizzle selection for HWT swizzle */
26457 /*! @{ */
26458 
26459 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_MASK (0x1FU)
26460 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_SHIFT (0U)
26461 /*! HwtSwizzleHwtAddress17 - See Description of HwtSwizzleHwtAddress0 for details. */
26462 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_MASK)
26463 /*! @} */
26464 
26465 /*! @name HWTSWIZZLEHWTACTN - Signal swizzle selection for HWT swizzle */
26466 /*! @{ */
26467 
26468 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_MASK (0x1FU)
26469 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_SHIFT (0U)
26470 /*! HwtSwizzleHwtActN - See Description of HwtSwizzleHwtAddress0 for details. */
26471 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_MASK)
26472 /*! @} */
26473 
26474 /*! @name HWTSWIZZLEHWTBANK0 - Signal swizzle selection for HWT swizzle */
26475 /*! @{ */
26476 
26477 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_MASK (0x1FU)
26478 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_SHIFT (0U)
26479 /*! HwtSwizzleHwtBank0 - See Description of HwtSwizzleHwtAddress0 for details. */
26480 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_MASK)
26481 /*! @} */
26482 
26483 /*! @name HWTSWIZZLEHWTBANK1 - Signal swizzle selection for HWT swizzle */
26484 /*! @{ */
26485 
26486 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_MASK (0x1FU)
26487 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_SHIFT (0U)
26488 /*! HwtSwizzleHwtBank1 - See Description of HwtSwizzleHwtAddress0 for details. */
26489 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_MASK)
26490 /*! @} */
26491 
26492 /*! @name HWTSWIZZLEHWTBANK2 - Signal swizzle selection for HWT swizzle */
26493 /*! @{ */
26494 
26495 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_MASK (0x1FU)
26496 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_SHIFT (0U)
26497 /*! HwtSwizzleHwtBank2 - See Description of HwtSwizzleHwtAddress0 for details. */
26498 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_MASK)
26499 /*! @} */
26500 
26501 /*! @name HWTSWIZZLEHWTBG0 - Signal swizzle selection for HWT swizzle */
26502 /*! @{ */
26503 
26504 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_MASK (0x1FU)
26505 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_SHIFT (0U)
26506 /*! HwtSwizzleHwtBg0 - See Description of HwtSwizzleHwtAddress0 for details. */
26507 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_MASK)
26508 /*! @} */
26509 
26510 /*! @name HWTSWIZZLEHWTBG1 - Signal swizzle selection for HWT swizzle */
26511 /*! @{ */
26512 
26513 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_MASK (0x1FU)
26514 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_SHIFT (0U)
26515 /*! HwtSwizzleHwtBg1 - See Description of HwtSwizzleHwtAddress0 for details. */
26516 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_MASK)
26517 /*! @} */
26518 
26519 /*! @name HWTSWIZZLEHWTCASN - Signal swizzle selection for HWT swizzle */
26520 /*! @{ */
26521 
26522 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_MASK (0x1FU)
26523 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_SHIFT (0U)
26524 /*! HwtSwizzleHwtCasN - See Description of HwtSwizzleHwtAddress0 for details. */
26525 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_MASK)
26526 /*! @} */
26527 
26528 /*! @name HWTSWIZZLEHWTRASN - Signal swizzle selection for HWT swizzle */
26529 /*! @{ */
26530 
26531 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_MASK (0x1FU)
26532 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_SHIFT (0U)
26533 /*! HwtSwizzleHwtRasN - See Description of HwtSwizzleHwtAddress0 for details. */
26534 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_MASK)
26535 /*! @} */
26536 
26537 /*! @name HWTSWIZZLEHWTWEN - Signal swizzle selection for HWT swizzle */
26538 /*! @{ */
26539 
26540 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_MASK (0x1FU)
26541 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_SHIFT (0U)
26542 /*! HwtSwizzleHwtWeN - See Description of HwtSwizzleHwtAddress0 for details. */
26543 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_MASK)
26544 /*! @} */
26545 
26546 /*! @name HWTSWIZZLEHWTPARITYIN - Signal swizzle selection for HWT swizzle */
26547 /*! @{ */
26548 
26549 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_MASK (0x1FU)
26550 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_SHIFT (0U)
26551 /*! HwtSwizzleHwtParityIn - See Description of HwtSwizzleHwtAddress0 for details. */
26552 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_MASK)
26553 /*! @} */
26554 
26555 /*! @name DFIHANDSHAKEDELAYS0 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays */
26556 /*! @{ */
26557 
26558 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_MASK (0xFU)
26559 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_SHIFT (0U)
26560 /*! PhyUpdAckDelay0 - Adds 0-15 DfiClks of delay after dfi0_phyupd_ack asserts, before the PHY takes
26561  *    any action (such as starting DDL calibration).
26562  */
26563 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_MASK)
26564 
26565 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_MASK (0xF0U)
26566 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_SHIFT (4U)
26567 /*! PhyUpdReqDelay0 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi0_phyupd_req. */
26568 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_MASK)
26569 
26570 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_MASK (0xF00U)
26571 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_SHIFT (8U)
26572 /*! CtrlUpdAckDelay0 - Adds 0-15 DfiClks of delay after dfi0_ctrlupd_req asserts, before the PHY takes any action. */
26573 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_MASK)
26574 
26575 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_MASK (0xF000U)
26576 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_SHIFT (12U)
26577 /*! CtrlUpdReqDelay0 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi0_ctrlupd_ack. */
26578 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_MASK)
26579 /*! @} */
26580 
26581 /*! @name DFIHANDSHAKEDELAYS1 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays */
26582 /*! @{ */
26583 
26584 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_MASK (0xFU)
26585 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_SHIFT (0U)
26586 /*! PhyUpdAckDelay1 - Adds 0-15 DfiClks of delay after dfi1_phyupd_ack asserts, before the PHY takes
26587  *    any action (such as starting DDL calibration).
26588  */
26589 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_MASK)
26590 
26591 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_MASK (0xF0U)
26592 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_SHIFT (4U)
26593 /*! PhyUpdReqDelay1 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi1_phyupd_req. */
26594 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_MASK)
26595 
26596 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_MASK (0xF00U)
26597 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_SHIFT (8U)
26598 /*! CtrlUpdAckDelay1 - Adds 0-15 DfiClks of delay after dfi1_ctrlupd_req asserts, before the PHY takes any action. */
26599 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_MASK)
26600 
26601 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_MASK (0xF000U)
26602 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_SHIFT (12U)
26603 /*! CtrlUpdReqDelay1 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi1_ctrlupd_ack. */
26604 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_MASK)
26605 /*! @} */
26606 
26607 /*! @name CALUCLKINFO_P1 - Impedance Calibration Clock Ratio */
26608 /*! @{ */
26609 
26610 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_MASK (0x3FFU)
26611 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_SHIFT (0U)
26612 /*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24. */
26613 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_MASK)
26614 /*! @} */
26615 
26616 /*! @name SEQ0BDLY0_P1 - PHY Initialization Engine (PIE) Delay Register 0 */
26617 /*! @{ */
26618 
26619 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_MASK (0xFFFFU)
26620 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_SHIFT (0U)
26621 /*! Seq0BDLY0_p1 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
26622  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
26623  */
26624 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_MASK)
26625 /*! @} */
26626 
26627 /*! @name SEQ0BDLY1_P1 - PHY Initialization Engine (PIE) Delay Register 1 */
26628 /*! @{ */
26629 
26630 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_MASK (0xFFFFU)
26631 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_SHIFT (0U)
26632 /*! Seq0BDLY1_p1 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
26633  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
26634  */
26635 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_MASK)
26636 /*! @} */
26637 
26638 /*! @name SEQ0BDLY2_P1 - PHY Initialization Engine (PIE) Delay Register 2 */
26639 /*! @{ */
26640 
26641 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_MASK (0xFFFFU)
26642 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_SHIFT (0U)
26643 /*! Seq0BDLY2_p1 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
26644  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
26645  */
26646 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_MASK)
26647 /*! @} */
26648 
26649 /*! @name SEQ0BDLY3_P1 - PHY Initialization Engine (PIE) Delay Register 3 */
26650 /*! @{ */
26651 
26652 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_MASK (0xFFFFU)
26653 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_SHIFT (0U)
26654 /*! Seq0BDLY3_p1 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
26655  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
26656  */
26657 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_MASK)
26658 /*! @} */
26659 
26660 /*! @name PPTTRAINSETUP_P1 - Setup Intervals for DFI PHY Master operations */
26661 /*! @{ */
26662 
26663 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_MASK (0xFU)
26664 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_SHIFT (0U)
26665 /*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next. */
26666 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_MASK)
26667 
26668 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_MASK (0x70U)
26669 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_SHIFT (4U)
26670 /*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted. */
26671 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_MASK)
26672 /*! @} */
26673 
26674 /*! @name TRISTATEMODECA_P1 - Mode select register for MEMCLK/Address/Command Tristates */
26675 /*! @{ */
26676 
26677 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_MASK (0x1U)
26678 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_SHIFT (0U)
26679 /*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled. */
26680 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_MASK)
26681 
26682 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_MASK (0x2U)
26683 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_SHIFT (1U)
26684 /*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode. */
26685 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_MASK)
26686 
26687 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_MASK (0xCU)
26688 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_SHIFT (2U)
26689 /*! CkDisVal - The PHY provides 4 memory clocks, n=0. */
26690 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_MASK)
26691 /*! @} */
26692 
26693 /*! @name HWTMRL_P1 - HWT MaxReadLatency. */
26694 /*! @{ */
26695 
26696 #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_MASK (0x1FU)
26697 #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_SHIFT (0U)
26698 /*! HwtMRL_p1 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
26699  *    until after all dbytes have their read data valid.
26700  */
26701 #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_MASK)
26702 /*! @} */
26703 
26704 /*! @name DQSPREAMBLECONTROL_P1 - Control the PHY logic related to the read and write DQS preamble */
26705 /*! @{ */
26706 
26707 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_MASK (0x1U)
26708 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_SHIFT (0U)
26709 /*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
26710  *    take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
26711  *    configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
26712  */
26713 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_MASK)
26714 
26715 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_MASK (0x2U)
26716 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_SHIFT (1U)
26717 /*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
26718  *    DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
26719  */
26720 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_MASK)
26721 
26722 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_MASK (0x1CU)
26723 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_SHIFT (2U)
26724 /*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled. */
26725 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_MASK)
26726 
26727 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
26728 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
26729 /*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
26730  *    TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
26731  */
26732 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_MASK)
26733 
26734 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_MASK (0x40U)
26735 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_SHIFT (6U)
26736 /*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble. */
26737 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_MASK)
26738 
26739 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_MASK (0x80U)
26740 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_SHIFT (7U)
26741 /*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
26742  *    to the same timing group when the bubble is 1 memclk.
26743  */
26744 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_MASK)
26745 
26746 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK (0x100U)
26747 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT (8U)
26748 /*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
26749  *    respectively, before and after a write burst, except during a memory read transaction.
26750  */
26751 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK)
26752 /*! @} */
26753 
26754 /*! @name DMIPINPRESENT_P1 - This Register is used to enable the Read-DBI function in each DBYTE */
26755 /*! @{ */
26756 
26757 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_MASK (0x1U)
26758 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_SHIFT (0U)
26759 /*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device. */
26760 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_MASK)
26761 /*! @} */
26762 
26763 /*! @name ARDPTRINITVAL_P1 - Address/Command FIFO ReadPointer Initial Value */
26764 /*! @{ */
26765 
26766 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_MASK (0xFU)
26767 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_SHIFT (0U)
26768 /*! ARdPtrInitVal_p1 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips. */
26769 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_MASK)
26770 /*! @} */
26771 
26772 /*! @name PROCODTTIMECTL_P1 - READ DATA On-Die Termination Timing Control (by PHY) */
26773 /*! @{ */
26774 
26775 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_MASK (0x3U)
26776 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_SHIFT (0U)
26777 /*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
26778  *    Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
26779  *    1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
26780  *    to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
26781  */
26782 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_MASK)
26783 
26784 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_MASK (0xCU)
26785 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_SHIFT (2U)
26786 /*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
26787  *    start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
26788  *    from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
26789  */
26790 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_MASK)
26791 /*! @} */
26792 
26793 /*! @name DLLGAINCTL_P1 - DLL gain control */
26794 /*! @{ */
26795 
26796 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_MASK (0xFU)
26797 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_SHIFT (0U)
26798 /*! DllGainIV - Initial value of DllGain. */
26799 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_MASK)
26800 
26801 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_MASK (0xF0U)
26802 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_SHIFT (4U)
26803 /*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
26804  *    used for maintaining lock, ie tracking pclk variation.
26805  */
26806 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_MASK)
26807 
26808 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_MASK (0xF00U)
26809 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_SHIFT (8U)
26810 /*! DllSeedSel - Reserved, must be configured to be 0. */
26811 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_MASK)
26812 /*! @} */
26813 
26814 /*! @name DFIRDDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
26815 /*! @{ */
26816 
26817 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_MASK (0x3U)
26818 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_SHIFT (0U)
26819 /*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
26820  *    dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
26821  */
26822 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_MASK)
26823 
26824 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_MASK (0xCU)
26825 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_SHIFT (2U)
26826 /*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
26827  *    dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
26828  */
26829 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_MASK)
26830 
26831 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_MASK (0x30U)
26832 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_SHIFT (4U)
26833 /*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
26834  *    dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
26835  */
26836 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_MASK)
26837 
26838 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_MASK (0xC0U)
26839 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_SHIFT (6U)
26840 /*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
26841  *    dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
26842  */
26843 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_MASK)
26844 /*! @} */
26845 
26846 /*! @name VREFINGLOBAL_P1 - PHY Global Vref Controls */
26847 /*! @{ */
26848 
26849 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_MASK (0x7U)
26850 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_SHIFT (0U)
26851 /*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
26852  *    ========================================================== 2'b00 - PHY Vref DAC Range0 --
26853  *    BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
26854  *    Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
26855  *    ========================================================== GlobalVrefInSel[2] shall be set according to Dram
26856  *    Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
26857  *    1'b0 LPDDR3 1'b0 LPDDR4 1'b1
26858  */
26859 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_MASK)
26860 
26861 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_MASK (0x3F8U)
26862 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_SHIFT (3U)
26863 /*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
26864  *    by GlobalVrefInSel[2] ========================================================== RANGE0 :
26865  *    DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
26866  *    0.
26867  */
26868 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_MASK)
26869 
26870 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_MASK (0x3C00U)
26871 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_SHIFT (10U)
26872 /*! GlobalVrefInTrim - RSVD */
26873 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_MASK)
26874 
26875 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_MASK (0x4000U)
26876 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_SHIFT (14U)
26877 /*! GlobalVrefInMode - RSVD */
26878 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_MASK)
26879 /*! @} */
26880 
26881 /*! @name DFIWRDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
26882 /*! @{ */
26883 
26884 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_MASK (0x3U)
26885 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_SHIFT (0U)
26886 /*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
26887  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
26888  */
26889 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_MASK)
26890 
26891 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_MASK (0xCU)
26892 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_SHIFT (2U)
26893 /*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
26894  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
26895  */
26896 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_MASK)
26897 
26898 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_MASK (0x30U)
26899 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_SHIFT (4U)
26900 /*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
26901  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
26902  */
26903 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_MASK)
26904 
26905 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_MASK (0xC0U)
26906 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_SHIFT (6U)
26907 /*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
26908  *    TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
26909  */
26910 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_MASK)
26911 /*! @} */
26912 
26913 /*! @name PLLCTRL2_P1 - PState dependent PLL Control Register 2 */
26914 /*! @{ */
26915 
26916 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_MASK (0x1FU)
26917 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_SHIFT (0U)
26918 /*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios. */
26919 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_MASK)
26920 /*! @} */
26921 
26922 /*! @name PLLCTRL1_P1 - PState dependent PLL Control Register 1 */
26923 /*! @{ */
26924 
26925 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_MASK (0x1FU)
26926 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_SHIFT (0U)
26927 /*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL. */
26928 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_MASK)
26929 
26930 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_MASK (0x1E0U)
26931 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_SHIFT (5U)
26932 /*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL. */
26933 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_MASK)
26934 /*! @} */
26935 
26936 /*! @name PLLTESTMODE_P1 - Additional controls for PLL CP/VCO modes of operation */
26937 /*! @{ */
26938 
26939 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_MASK (0xFFFFU)
26940 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_SHIFT (0U)
26941 /*! PllTestMode_p1 - It is required to use default values for this CSR unless directed otherwise by Synopsys. */
26942 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_MASK)
26943 /*! @} */
26944 
26945 /*! @name PLLCTRL4_P1 - PState dependent PLL Control Register 4 */
26946 /*! @{ */
26947 
26948 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_MASK (0x1FU)
26949 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_SHIFT (0U)
26950 /*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL. */
26951 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_MASK)
26952 
26953 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_MASK (0x1E0U)
26954 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_SHIFT (5U)
26955 /*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL. */
26956 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_MASK)
26957 /*! @} */
26958 
26959 /*! @name DFIFREQRATIO_P1 - DFI Frequency Ratio */
26960 /*! @{ */
26961 
26962 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_MASK (0x3U)
26963 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_SHIFT (0U)
26964 /*! DfiFreqRatio_p1 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
26965  *    1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
26966  */
26967 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_MASK)
26968 /*! @} */
26969 
26970 /*! @name CALUCLKINFO_P2 - Impedance Calibration Clock Ratio */
26971 /*! @{ */
26972 
26973 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_MASK (0x3FFU)
26974 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_SHIFT (0U)
26975 /*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24. */
26976 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_MASK)
26977 /*! @} */
26978 
26979 /*! @name SEQ0BDLY0_P2 - PHY Initialization Engine (PIE) Delay Register 0 */
26980 /*! @{ */
26981 
26982 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_MASK (0xFFFFU)
26983 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_SHIFT (0U)
26984 /*! Seq0BDLY0_p2 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
26985  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
26986  */
26987 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_MASK)
26988 /*! @} */
26989 
26990 /*! @name SEQ0BDLY1_P2 - PHY Initialization Engine (PIE) Delay Register 1 */
26991 /*! @{ */
26992 
26993 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_MASK (0xFFFFU)
26994 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_SHIFT (0U)
26995 /*! Seq0BDLY1_p2 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
26996  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
26997  */
26998 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_MASK)
26999 /*! @} */
27000 
27001 /*! @name SEQ0BDLY2_P2 - PHY Initialization Engine (PIE) Delay Register 2 */
27002 /*! @{ */
27003 
27004 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_MASK (0xFFFFU)
27005 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_SHIFT (0U)
27006 /*! Seq0BDLY2_p2 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
27007  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
27008  */
27009 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_MASK)
27010 /*! @} */
27011 
27012 /*! @name SEQ0BDLY3_P2 - PHY Initialization Engine (PIE) Delay Register 3 */
27013 /*! @{ */
27014 
27015 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_MASK (0xFFFFU)
27016 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_SHIFT (0U)
27017 /*! Seq0BDLY3_p2 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
27018  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
27019  */
27020 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_MASK)
27021 /*! @} */
27022 
27023 /*! @name PPTTRAINSETUP_P2 - Setup Intervals for DFI PHY Master operations */
27024 /*! @{ */
27025 
27026 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_MASK (0xFU)
27027 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_SHIFT (0U)
27028 /*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next. */
27029 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_MASK)
27030 
27031 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_MASK (0x70U)
27032 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_SHIFT (4U)
27033 /*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted. */
27034 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_MASK)
27035 /*! @} */
27036 
27037 /*! @name TRISTATEMODECA_P2 - Mode select register for MEMCLK/Address/Command Tristates */
27038 /*! @{ */
27039 
27040 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_MASK (0x1U)
27041 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_SHIFT (0U)
27042 /*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled. */
27043 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_MASK)
27044 
27045 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_MASK (0x2U)
27046 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_SHIFT (1U)
27047 /*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode. */
27048 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_MASK)
27049 
27050 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_MASK (0xCU)
27051 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_SHIFT (2U)
27052 /*! CkDisVal - The PHY provides 4 memory clocks, n=0. */
27053 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_MASK)
27054 /*! @} */
27055 
27056 /*! @name HWTMRL_P2 - HWT MaxReadLatency. */
27057 /*! @{ */
27058 
27059 #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_MASK (0x1FU)
27060 #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_SHIFT (0U)
27061 /*! HwtMRL_p2 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
27062  *    until after all dbytes have their read data valid.
27063  */
27064 #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_MASK)
27065 /*! @} */
27066 
27067 /*! @name DQSPREAMBLECONTROL_P2 - Control the PHY logic related to the read and write DQS preamble */
27068 /*! @{ */
27069 
27070 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_MASK (0x1U)
27071 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_SHIFT (0U)
27072 /*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
27073  *    take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
27074  *    configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
27075  */
27076 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_MASK)
27077 
27078 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_MASK (0x2U)
27079 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_SHIFT (1U)
27080 /*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
27081  *    DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
27082  */
27083 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_MASK)
27084 
27085 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_MASK (0x1CU)
27086 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_SHIFT (2U)
27087 /*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled. */
27088 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_MASK)
27089 
27090 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
27091 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
27092 /*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
27093  *    TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
27094  */
27095 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_MASK)
27096 
27097 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_MASK (0x40U)
27098 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_SHIFT (6U)
27099 /*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble. */
27100 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_MASK)
27101 
27102 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_MASK (0x80U)
27103 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_SHIFT (7U)
27104 /*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
27105  *    to the same timing group when the bubble is 1 memclk.
27106  */
27107 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_MASK)
27108 
27109 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK (0x100U)
27110 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT (8U)
27111 /*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
27112  *    respectively, before and after a write burst, except during a memory read transaction.
27113  */
27114 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK)
27115 /*! @} */
27116 
27117 /*! @name DMIPINPRESENT_P2 - This Register is used to enable the Read-DBI function in each DBYTE */
27118 /*! @{ */
27119 
27120 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_MASK (0x1U)
27121 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_SHIFT (0U)
27122 /*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device. */
27123 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_MASK)
27124 /*! @} */
27125 
27126 /*! @name ARDPTRINITVAL_P2 - Address/Command FIFO ReadPointer Initial Value */
27127 /*! @{ */
27128 
27129 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_MASK (0xFU)
27130 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_SHIFT (0U)
27131 /*! ARdPtrInitVal_p2 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips. */
27132 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_MASK)
27133 /*! @} */
27134 
27135 /*! @name PROCODTTIMECTL_P2 - READ DATA On-Die Termination Timing Control (by PHY) */
27136 /*! @{ */
27137 
27138 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_MASK (0x3U)
27139 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_SHIFT (0U)
27140 /*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
27141  *    Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
27142  *    1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
27143  *    to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
27144  */
27145 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_MASK)
27146 
27147 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_MASK (0xCU)
27148 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_SHIFT (2U)
27149 /*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
27150  *    start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
27151  *    from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
27152  */
27153 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_MASK)
27154 /*! @} */
27155 
27156 /*! @name DLLGAINCTL_P2 - DLL gain control */
27157 /*! @{ */
27158 
27159 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_MASK (0xFU)
27160 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_SHIFT (0U)
27161 /*! DllGainIV - Initial value of DllGain. */
27162 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_MASK)
27163 
27164 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_MASK (0xF0U)
27165 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_SHIFT (4U)
27166 /*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
27167  *    used for maintaining lock, ie tracking pclk variation.
27168  */
27169 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_MASK)
27170 
27171 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_MASK (0xF00U)
27172 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_SHIFT (8U)
27173 /*! DllSeedSel - Reserved, must be configured to be 0. */
27174 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_MASK)
27175 /*! @} */
27176 
27177 /*! @name DFIRDDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
27178 /*! @{ */
27179 
27180 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_MASK (0x3U)
27181 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_SHIFT (0U)
27182 /*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
27183  *    dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
27184  */
27185 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_MASK)
27186 
27187 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_MASK (0xCU)
27188 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_SHIFT (2U)
27189 /*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
27190  *    dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
27191  */
27192 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_MASK)
27193 
27194 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_MASK (0x30U)
27195 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_SHIFT (4U)
27196 /*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
27197  *    dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
27198  */
27199 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_MASK)
27200 
27201 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_MASK (0xC0U)
27202 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_SHIFT (6U)
27203 /*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
27204  *    dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
27205  */
27206 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_MASK)
27207 /*! @} */
27208 
27209 /*! @name VREFINGLOBAL_P2 - PHY Global Vref Controls */
27210 /*! @{ */
27211 
27212 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_MASK (0x7U)
27213 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_SHIFT (0U)
27214 /*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
27215  *    ========================================================== 2'b00 - PHY Vref DAC Range0 --
27216  *    BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
27217  *    Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
27218  *    ========================================================== GlobalVrefInSel[2] shall be set according to Dram
27219  *    Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
27220  *    1'b0 LPDDR3 1'b0 LPDDR4 1'b1
27221  */
27222 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_MASK)
27223 
27224 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_MASK (0x3F8U)
27225 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_SHIFT (3U)
27226 /*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
27227  *    by GlobalVrefInSel[2] ========================================================== RANGE0 :
27228  *    DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
27229  *    0.
27230  */
27231 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_MASK)
27232 
27233 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_MASK (0x3C00U)
27234 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_SHIFT (10U)
27235 /*! GlobalVrefInTrim - RSVD */
27236 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_MASK)
27237 
27238 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_MASK (0x4000U)
27239 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_SHIFT (14U)
27240 /*! GlobalVrefInMode - RSVD */
27241 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_MASK)
27242 /*! @} */
27243 
27244 /*! @name DFIWRDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
27245 /*! @{ */
27246 
27247 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_MASK (0x3U)
27248 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_SHIFT (0U)
27249 /*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
27250  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
27251  */
27252 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_MASK)
27253 
27254 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_MASK (0xCU)
27255 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_SHIFT (2U)
27256 /*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
27257  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
27258  */
27259 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_MASK)
27260 
27261 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_MASK (0x30U)
27262 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_SHIFT (4U)
27263 /*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
27264  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
27265  */
27266 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_MASK)
27267 
27268 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_MASK (0xC0U)
27269 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_SHIFT (6U)
27270 /*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
27271  *    TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
27272  */
27273 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_MASK)
27274 /*! @} */
27275 
27276 /*! @name PLLCTRL2_P2 - PState dependent PLL Control Register 2 */
27277 /*! @{ */
27278 
27279 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_MASK (0x1FU)
27280 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_SHIFT (0U)
27281 /*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios. */
27282 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_MASK)
27283 /*! @} */
27284 
27285 /*! @name PLLCTRL1_P2 - PState dependent PLL Control Register 1 */
27286 /*! @{ */
27287 
27288 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_MASK (0x1FU)
27289 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_SHIFT (0U)
27290 /*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL. */
27291 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_MASK)
27292 
27293 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_MASK (0x1E0U)
27294 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_SHIFT (5U)
27295 /*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL. */
27296 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_MASK)
27297 /*! @} */
27298 
27299 /*! @name PLLTESTMODE_P2 - Additional controls for PLL CP/VCO modes of operation */
27300 /*! @{ */
27301 
27302 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_MASK (0xFFFFU)
27303 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_SHIFT (0U)
27304 /*! PllTestMode_p2 - It is required to use default values for this CSR unless directed otherwise by Synopsys. */
27305 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_MASK)
27306 /*! @} */
27307 
27308 /*! @name PLLCTRL4_P2 - PState dependent PLL Control Register 4 */
27309 /*! @{ */
27310 
27311 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_MASK (0x1FU)
27312 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_SHIFT (0U)
27313 /*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL. */
27314 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_MASK)
27315 
27316 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_MASK (0x1E0U)
27317 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_SHIFT (5U)
27318 /*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL. */
27319 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_MASK)
27320 /*! @} */
27321 
27322 /*! @name DFIFREQRATIO_P2 - DFI Frequency Ratio */
27323 /*! @{ */
27324 
27325 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_MASK (0x3U)
27326 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_SHIFT (0U)
27327 /*! DfiFreqRatio_p2 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
27328  *    1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
27329  */
27330 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_MASK)
27331 /*! @} */
27332 
27333 /*! @name CALUCLKINFO_P3 - Impedance Calibration Clock Ratio */
27334 /*! @{ */
27335 
27336 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_MASK (0x3FFU)
27337 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_SHIFT (0U)
27338 /*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24. */
27339 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_MASK)
27340 /*! @} */
27341 
27342 /*! @name SEQ0BDLY0_P3 - PHY Initialization Engine (PIE) Delay Register 0 */
27343 /*! @{ */
27344 
27345 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_MASK (0xFFFFU)
27346 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_SHIFT (0U)
27347 /*! Seq0BDLY0_p3 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
27348  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
27349  */
27350 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_MASK)
27351 /*! @} */
27352 
27353 /*! @name SEQ0BDLY1_P3 - PHY Initialization Engine (PIE) Delay Register 1 */
27354 /*! @{ */
27355 
27356 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_MASK (0xFFFFU)
27357 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_SHIFT (0U)
27358 /*! Seq0BDLY1_p3 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
27359  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
27360  */
27361 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_MASK)
27362 /*! @} */
27363 
27364 /*! @name SEQ0BDLY2_P3 - PHY Initialization Engine (PIE) Delay Register 2 */
27365 /*! @{ */
27366 
27367 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_MASK (0xFFFFU)
27368 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_SHIFT (0U)
27369 /*! Seq0BDLY2_p3 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
27370  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
27371  */
27372 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_MASK)
27373 /*! @} */
27374 
27375 /*! @name SEQ0BDLY3_P3 - PHY Initialization Engine (PIE) Delay Register 3 */
27376 /*! @{ */
27377 
27378 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_MASK (0xFFFFU)
27379 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_SHIFT (0U)
27380 /*! Seq0BDLY3_p3 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
27381  *    selection by the NOP and WAIT instructions in the PIE for the delay value.
27382  */
27383 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_MASK)
27384 /*! @} */
27385 
27386 /*! @name PPTTRAINSETUP_P3 - Setup Intervals for DFI PHY Master operations */
27387 /*! @{ */
27388 
27389 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_MASK (0xFU)
27390 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_SHIFT (0U)
27391 /*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next. */
27392 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_MASK)
27393 
27394 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_MASK (0x70U)
27395 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_SHIFT (4U)
27396 /*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted. */
27397 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_MASK)
27398 /*! @} */
27399 
27400 /*! @name TRISTATEMODECA_P3 - Mode select register for MEMCLK/Address/Command Tristates */
27401 /*! @{ */
27402 
27403 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_MASK (0x1U)
27404 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_SHIFT (0U)
27405 /*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled. */
27406 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_MASK)
27407 
27408 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_MASK (0x2U)
27409 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_SHIFT (1U)
27410 /*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode. */
27411 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_MASK)
27412 
27413 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_MASK (0xCU)
27414 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_SHIFT (2U)
27415 /*! CkDisVal - The PHY provides 4 memory clocks, n=0. */
27416 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_MASK)
27417 /*! @} */
27418 
27419 /*! @name HWTMRL_P3 - HWT MaxReadLatency. */
27420 /*! @{ */
27421 
27422 #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_MASK (0x1FU)
27423 #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_SHIFT (0U)
27424 /*! HwtMRL_p3 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
27425  *    until after all dbytes have their read data valid.
27426  */
27427 #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_MASK)
27428 /*! @} */
27429 
27430 /*! @name DQSPREAMBLECONTROL_P3 - Control the PHY logic related to the read and write DQS preamble */
27431 /*! @{ */
27432 
27433 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_MASK (0x1U)
27434 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_SHIFT (0U)
27435 /*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
27436  *    take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
27437  *    configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
27438  */
27439 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_MASK)
27440 
27441 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_MASK (0x2U)
27442 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_SHIFT (1U)
27443 /*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
27444  *    DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
27445  */
27446 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_MASK)
27447 
27448 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_MASK (0x1CU)
27449 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_SHIFT (2U)
27450 /*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled. */
27451 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_MASK)
27452 
27453 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
27454 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
27455 /*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
27456  *    TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
27457  */
27458 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_MASK)
27459 
27460 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_MASK (0x40U)
27461 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_SHIFT (6U)
27462 /*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble. */
27463 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_MASK)
27464 
27465 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_MASK (0x80U)
27466 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_SHIFT (7U)
27467 /*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
27468  *    to the same timing group when the bubble is 1 memclk.
27469  */
27470 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_MASK)
27471 
27472 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK (0x100U)
27473 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT (8U)
27474 /*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
27475  *    respectively, before and after a write burst, except during a memory read transaction.
27476  */
27477 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK)
27478 /*! @} */
27479 
27480 /*! @name DMIPINPRESENT_P3 - This Register is used to enable the Read-DBI function in each DBYTE */
27481 /*! @{ */
27482 
27483 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_MASK (0x1U)
27484 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_SHIFT (0U)
27485 /*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device. */
27486 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_MASK)
27487 /*! @} */
27488 
27489 /*! @name ARDPTRINITVAL_P3 - Address/Command FIFO ReadPointer Initial Value */
27490 /*! @{ */
27491 
27492 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_MASK (0xFU)
27493 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_SHIFT (0U)
27494 /*! ARdPtrInitVal_p3 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips. */
27495 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_MASK)
27496 /*! @} */
27497 
27498 /*! @name PROCODTTIMECTL_P3 - READ DATA On-Die Termination Timing Control (by PHY) */
27499 /*! @{ */
27500 
27501 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_MASK (0x3U)
27502 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_SHIFT (0U)
27503 /*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
27504  *    Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
27505  *    1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
27506  *    to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
27507  */
27508 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_MASK)
27509 
27510 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_MASK (0xCU)
27511 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_SHIFT (2U)
27512 /*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
27513  *    start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
27514  *    from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
27515  */
27516 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_MASK)
27517 /*! @} */
27518 
27519 /*! @name DLLGAINCTL_P3 - DLL gain control */
27520 /*! @{ */
27521 
27522 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_MASK (0xFU)
27523 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_SHIFT (0U)
27524 /*! DllGainIV - Initial value of DllGain. */
27525 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_MASK)
27526 
27527 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_MASK (0xF0U)
27528 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_SHIFT (4U)
27529 /*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
27530  *    used for maintaining lock, ie tracking pclk variation.
27531  */
27532 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_MASK)
27533 
27534 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_MASK (0xF00U)
27535 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_SHIFT (8U)
27536 /*! DllSeedSel - Reserved, must be configured to be 0. */
27537 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_MASK)
27538 /*! @} */
27539 
27540 /*! @name DFIRDDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
27541 /*! @{ */
27542 
27543 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_MASK (0x3U)
27544 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_SHIFT (0U)
27545 /*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
27546  *    dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
27547  */
27548 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_MASK)
27549 
27550 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_MASK (0xCU)
27551 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_SHIFT (2U)
27552 /*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
27553  *    dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
27554  */
27555 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_MASK)
27556 
27557 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_MASK (0x30U)
27558 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_SHIFT (4U)
27559 /*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
27560  *    dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
27561  */
27562 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_MASK)
27563 
27564 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_MASK (0xC0U)
27565 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_SHIFT (6U)
27566 /*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
27567  *    dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
27568  */
27569 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_MASK)
27570 /*! @} */
27571 
27572 /*! @name VREFINGLOBAL_P3 - PHY Global Vref Controls */
27573 /*! @{ */
27574 
27575 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_MASK (0x7U)
27576 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_SHIFT (0U)
27577 /*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
27578  *    ========================================================== 2'b00 - PHY Vref DAC Range0 --
27579  *    BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
27580  *    Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
27581  *    ========================================================== GlobalVrefInSel[2] shall be set according to Dram
27582  *    Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
27583  *    1'b0 LPDDR3 1'b0 LPDDR4 1'b1
27584  */
27585 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_MASK)
27586 
27587 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_MASK (0x3F8U)
27588 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_SHIFT (3U)
27589 /*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
27590  *    by GlobalVrefInSel[2] ========================================================== RANGE0 :
27591  *    DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
27592  *    0.
27593  */
27594 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_MASK)
27595 
27596 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_MASK (0x3C00U)
27597 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_SHIFT (10U)
27598 /*! GlobalVrefInTrim - RSVD */
27599 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_MASK)
27600 
27601 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_MASK (0x4000U)
27602 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_SHIFT (14U)
27603 /*! GlobalVrefInMode - RSVD */
27604 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_MASK)
27605 /*! @} */
27606 
27607 /*! @name DFIWRDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
27608 /*! @{ */
27609 
27610 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_MASK (0x3U)
27611 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_SHIFT (0U)
27612 /*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
27613  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
27614  */
27615 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_MASK)
27616 
27617 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_MASK (0xCU)
27618 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_SHIFT (2U)
27619 /*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
27620  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
27621  */
27622 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_MASK)
27623 
27624 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_MASK (0x30U)
27625 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_SHIFT (4U)
27626 /*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
27627  *    dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
27628  */
27629 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_MASK)
27630 
27631 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_MASK (0xC0U)
27632 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_SHIFT (6U)
27633 /*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
27634  *    TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
27635  */
27636 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_MASK)
27637 /*! @} */
27638 
27639 /*! @name PLLCTRL2_P3 - PState dependent PLL Control Register 2 */
27640 /*! @{ */
27641 
27642 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_MASK (0x1FU)
27643 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_SHIFT (0U)
27644 /*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios. */
27645 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_MASK)
27646 /*! @} */
27647 
27648 /*! @name PLLCTRL1_P3 - PState dependent PLL Control Register 1 */
27649 /*! @{ */
27650 
27651 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_MASK (0x1FU)
27652 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_SHIFT (0U)
27653 /*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL. */
27654 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_MASK)
27655 
27656 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_MASK (0x1E0U)
27657 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_SHIFT (5U)
27658 /*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL. */
27659 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_MASK)
27660 /*! @} */
27661 
27662 /*! @name PLLTESTMODE_P3 - Additional controls for PLL CP/VCO modes of operation */
27663 /*! @{ */
27664 
27665 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_MASK (0xFFFFU)
27666 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_SHIFT (0U)
27667 /*! PllTestMode_p3 - It is required to use default values for this CSR unless directed otherwise by Synopsys. */
27668 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_MASK)
27669 /*! @} */
27670 
27671 /*! @name PLLCTRL4_P3 - PState dependent PLL Control Register 4 */
27672 /*! @{ */
27673 
27674 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_MASK (0x1FU)
27675 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_SHIFT (0U)
27676 /*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL. */
27677 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_MASK)
27678 
27679 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_MASK (0x1E0U)
27680 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_SHIFT (5U)
27681 /*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL. */
27682 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_MASK)
27683 /*! @} */
27684 
27685 /*! @name DFIFREQRATIO_P3 - DFI Frequency Ratio */
27686 /*! @{ */
27687 
27688 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_MASK (0x3U)
27689 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_SHIFT (0U)
27690 /*! DfiFreqRatio_p3 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
27691  *    1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
27692  */
27693 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_MASK)
27694 /*! @} */
27695 
27696 
27697 /*!
27698  * @}
27699  */ /* end of group DWC_DDRPHYA_MASTER_Register_Masks */
27700 
27701 
27702 /* DWC_DDRPHYA_MASTER - Peripheral instance base addresses */
27703 /** Peripheral DWC_DDRPHYA_MASTER0 base address */
27704 #define DWC_DDRPHYA_MASTER0_BASE                 (0x3C020000u)
27705 /** Peripheral DWC_DDRPHYA_MASTER0 base pointer */
27706 #define DWC_DDRPHYA_MASTER0                      ((DWC_DDRPHYA_MASTER_Type *)DWC_DDRPHYA_MASTER0_BASE)
27707 /** Array initializer of DWC_DDRPHYA_MASTER peripheral base addresses */
27708 #define DWC_DDRPHYA_MASTER_BASE_ADDRS            { DWC_DDRPHYA_MASTER0_BASE }
27709 /** Array initializer of DWC_DDRPHYA_MASTER peripheral base pointers */
27710 #define DWC_DDRPHYA_MASTER_BASE_PTRS             { DWC_DDRPHYA_MASTER0 }
27711 
27712 /*!
27713  * @}
27714  */ /* end of group DWC_DDRPHYA_MASTER_Peripheral_Access_Layer */
27715 
27716 
27717 /* ----------------------------------------------------------------------------
27718    -- EARC Peripheral Access Layer
27719    ---------------------------------------------------------------------------- */
27720 
27721 /*!
27722  * @addtogroup EARC_Peripheral_Access_Layer EARC Peripheral Access Layer
27723  * @{
27724  */
27725 
27726 /** EARC - Register Layout Typedef */
27727 typedef struct {
27728   __IO uint32_t VERSION;                           /**< Version control register, offset: 0x0 */
27729        uint8_t RESERVED_0[12];
27730   struct {                                         /* offset: 0x10 */
27731     __IO uint32_t RW;                                /**< External control register, offset: 0x10 */
27732     __IO uint32_t SET;                               /**< External control register, offset: 0x14 */
27733     __IO uint32_t CLR;                               /**< External control register, offset: 0x18 */
27734     __IO uint32_t TOG;                               /**< External control register, offset: 0x1C */
27735   } EXT_CTRL;
27736   struct {                                         /* offset: 0x20 */
27737     __IO uint32_t RW;                                /**< External Status register, offset: 0x20 */
27738     __IO uint32_t SET;                               /**< External Status register, offset: 0x24 */
27739     __IO uint32_t CLR;                               /**< External Status register, offset: 0x28 */
27740     __IO uint32_t TOG;                               /**< External Status register, offset: 0x2C */
27741   } EXT_STATUS;
27742   struct {                                         /* offset: 0x30 */
27743     __IO uint32_t RW;                                /**< Interrupt enables for interrupt 0, offset: 0x30 */
27744     __IO uint32_t SET;                               /**< Interrupt enables for interrupt 0, offset: 0x34 */
27745     __IO uint32_t CLR;                               /**< Interrupt enables for interrupt 0, offset: 0x38 */
27746     __IO uint32_t TOG;                               /**< Interrupt enables for interrupt 0, offset: 0x3C */
27747   } EXT_IER0;
27748   struct {                                         /* offset: 0x40 */
27749     __IO uint32_t RW;                                /**< Interrupt enables for interrupt 1, offset: 0x40 */
27750     __IO uint32_t SET;                               /**< Interrupt enables for interrupt 1, offset: 0x44 */
27751     __IO uint32_t CLR;                               /**< Interrupt enables for interrupt 1, offset: 0x48 */
27752     __IO uint32_t TOG;                               /**< Interrupt enables for interrupt 1, offset: 0x4C */
27753   } EXT_IER1;
27754   struct {                                         /* offset: 0x50 */
27755     __IO uint32_t RW;                                /**< External Interrupt Status register, offset: 0x50 */
27756     __IO uint32_t SET;                               /**< External Interrupt Status register, offset: 0x54 */
27757     __IO uint32_t CLR;                               /**< External Interrupt Status register, offset: 0x58 */
27758     __IO uint32_t TOG;                               /**< External Interrupt Status register, offset: 0x5C */
27759   } EXT_ISR;
27760        uint8_t RESERVED_1[16];
27761   struct {                                         /* offset: 0x70 */
27762     __IO uint32_t RW;                                /**< Interrupt enable register for M0+, offset: 0x70 */
27763     __IO uint32_t SET;                               /**< Interrupt enable register for M0+, offset: 0x74 */
27764     __IO uint32_t CLR;                               /**< Interrupt enable register for M0+, offset: 0x78 */
27765     __IO uint32_t TOG;                               /**< Interrupt enable register for M0+, offset: 0x7C */
27766   } IER;
27767   struct {                                         /* offset: 0x80 */
27768     __IO uint32_t RW;                                /**< Interrupt status register, offset: 0x80 */
27769     __IO uint32_t SET;                               /**< Interrupt status register, offset: 0x84 */
27770     __IO uint32_t CLR;                               /**< Interrupt status register, offset: 0x88 */
27771     __IO uint32_t TOG;                               /**< Interrupt status register, offset: 0x8C */
27772   } ISR;
27773   struct {                                         /* offset: 0x90 */
27774     __IO uint32_t RW;                                /**< AI interface control register, offset: 0x90 */
27775     __IO uint32_t SET;                               /**< AI interface control register, offset: 0x94 */
27776     __IO uint32_t CLR;                               /**< AI interface control register, offset: 0x98 */
27777     __IO uint32_t TOG;                               /**< AI interface control register, offset: 0x9C */
27778   } PHY_AI_CTRL;
27779   __IO uint32_t PHY_AI_WDATA;                      /**< AI interface WDATA register, offset: 0xA0 */
27780   __I  uint32_t PHY_AI_RDATA;                      /**< AI interface RDATA register, offset: 0xA4 */
27781   __I  uint32_t DPATH_STATUS;                      /**< Audio XCVR datapath status, offset: 0xA8 */
27782        uint8_t RESERVED_2[20];
27783   struct {                                         /* offset: 0xC0 */
27784     __IO uint32_t RW;                                /**< CMDC receiver control register, offset: 0xC0 */
27785     __IO uint32_t SET;                               /**< CMDC receiver control register, offset: 0xC4 */
27786     __IO uint32_t CLR;                               /**< CMDC receiver control register, offset: 0xC8 */
27787     __IO uint32_t TOG;                               /**< CMDC receiver control register, offset: 0xCC */
27788   } RX_CMDC_CTRL;
27789   __I  uint32_t RX_CMDC_STATUS;                    /**< eARC receiver CMDC status, offset: 0xD0 */
27790        uint8_t RESERVED_3[12];
27791   __IO uint32_t RX_CMDC_TX_DATA;                   /**< CMDC transmit data register, offset: 0xE0 */
27792        uint8_t RESERVED_4[12];
27793   __I  uint32_t RX_CMDC_RX_DATA;                   /**< CMDC receive data register, offset: 0xF0 */
27794        uint8_t RESERVED_5[140];
27795   struct {                                         /* offset: 0x180 */
27796     __IO uint32_t RW;                                /**< Data path control register, offset: 0x180 */
27797     __IO uint32_t SET;                               /**< Data path control register, offset: 0x184 */
27798     __IO uint32_t CLR;                               /**< Data path control register, offset: 0x188 */
27799     __IO uint32_t TOG;                               /**< Data path control register, offset: 0x18C */
27800   } RX_DATAPATH_CTRL;
27801   __I  uint32_t RX_CS_DATA_BITS[6];                /**< Channel staus bits, array offset: 0x190, array step: 0x4 */
27802   __I  uint32_t RX_USER_DATA_BITS[6];              /**< User data bits, array offset: 0x1A8, array step: 0x4 */
27803   struct {                                         /* offset: 0x1C0 */
27804     __IO uint32_t RW;                                /**< DMAC counter control register, offset: 0x1C0 */
27805     __IO uint32_t SET;                               /**< DMAC counter control register, offset: 0x1C4 */
27806     __IO uint32_t CLR;                               /**< DMAC counter control register, offset: 0x1C8 */
27807     __IO uint32_t TOG;                               /**< DMAC counter control register, offset: 0x1CC */
27808   } RX_DPATH_CNTR_CTRL;
27809   __I  uint32_t RX_DPATH_TSCR;                     /**< Receive Datapath Timestamp Counter Register, offset: 0x1D0 */
27810   __I  uint32_t RX_DPATH_BCR;                      /**< Receive Datapath Bit counter register, offset: 0x1D4 */
27811   __I  uint32_t RX_DPATH_BCTR;                     /**< Receive datapath Bit count timestamp register., offset: 0x1D8 */
27812   __I  uint32_t RX_DPATH_BCRR;                     /**< Receive datapath Bit read timestamp register., offset: 0x1DC */
27813   struct {                                         /* offset: 0x1E0 */
27814     __IO uint32_t RW;                                /**< Preamble match value register, offset: 0x1E0 */
27815     __IO uint32_t SET;                               /**< Preamble match value register, offset: 0x1E4 */
27816     __IO uint32_t CLR;                               /**< Preamble match value register, offset: 0x1E8 */
27817     __IO uint32_t TOG;                               /**< Preamble match value register, offset: 0x1EC */
27818   } DMAC_PRE_MATCH_VAL;
27819   struct {                                         /* offset: 0x1F0 */
27820     __IO uint32_t RW;                                /**< Preamble match value register, offset: 0x1F0 */
27821     __IO uint32_t SET;                               /**< Preamble match value register, offset: 0x1F4 */
27822     __IO uint32_t CLR;                               /**< Preamble match value register, offset: 0x1F8 */
27823     __IO uint32_t TOG;                               /**< Preamble match value register, offset: 0x1FC */
27824   } DMAC_DTS_PRE_MATCH_VAL;
27825   __IO uint32_t RX_DPATH_PRE_ERR;                  /**< Error count for IEC60958-1 Block Synchronization., offset: 0x200 */
27826   __IO uint32_t RX_DPATH_PARITY_ERR;               /**< Parity Error count for IEC60958-1 Blocks., offset: 0x204 */
27827        uint8_t RESERVED_6[8];
27828   __I  uint32_t RX_DPATH_PKT_CNT;                  /**< Receive Data packet count., offset: 0x210 */
27829   __I  uint32_t RX_DPATH_ONE_BIT_ERR_CNT;          /**< Receive Data packet Corrected error count., offset: 0x214 */
27830   __I  uint32_t DMAC_PRE_MATCH_OFFSET;             /**< Preamble match offset value register, offset: 0x218 */
27831        uint8_t RESERVED_7[4];
27832   struct {                                         /* offset: 0x220 */
27833     __IO uint32_t RW;                                /**< Transmit Data path control register, offset: 0x220 */
27834     __IO uint32_t SET;                               /**< Transmit Data path control register, offset: 0x224 */
27835     __IO uint32_t CLR;                               /**< Transmit Data path control register, offset: 0x228 */
27836     __IO uint32_t TOG;                               /**< Transmit Data path control register, offset: 0x22C */
27837   } TX_DATAPATH_CTRL;
27838   __IO uint32_t TX_CS_DATA_BITS[6];                /**< Channel staus bits, array offset: 0x230, array step: 0x4 */
27839   __IO uint32_t TX_USER_DATA_BITS[6];              /**< User data bits, array offset: 0x248, array step: 0x4 */
27840   struct {                                         /* offset: 0x260 */
27841     __IO uint32_t RW;                                /**< DMAC counter control register, offset: 0x260 */
27842     __IO uint32_t SET;                               /**< DMAC counter control register, offset: 0x264 */
27843     __IO uint32_t CLR;                               /**< DMAC counter control register, offset: 0x268 */
27844     __IO uint32_t TOG;                               /**< DMAC counter control register, offset: 0x26C */
27845   } TX_DPATH_CNTR_CTRL;
27846   __I  uint32_t TX_DPATH_TSCR;                     /**< Transmit Datapath Timestamp Counter Register, offset: 0x270 */
27847   __I  uint32_t TX_DPATH_BCR;                      /**< Transmit Datapath Bit counter register, offset: 0x274 */
27848   __I  uint32_t TX_DPATH_BCTR;                     /**< Transmit datapath Bit count timestamp register., offset: 0x278 */
27849   __I  uint32_t TX_DPATH_BCRR;                     /**< Transmmit datapath Bit read timestamp register., offset: 0x27C */
27850        uint8_t RESERVED_8[32];
27851   struct {                                         /* offset: 0x2A0 */
27852     __IO uint32_t RW;                                /**< HPD Debounce Control Register, offset: 0x2A0 */
27853     __IO uint32_t SET;                               /**< HPD Debounce Control Register, offset: 0x2A4 */
27854     __IO uint32_t CLR;                               /**< HPD Debounce Control Register, offset: 0x2A8 */
27855     __IO uint32_t TOG;                               /**< HPD Debounce Control Register, offset: 0x2AC */
27856   } HPD_DBNC_CTRL;
27857        uint8_t RESERVED_9[32];
27858   __IO uint32_t TEMPERATURE;                       /**< Chip Temperature for eARC PHY, offset: 0x2D0 */
27859 } EARC_Type;
27860 
27861 /* ----------------------------------------------------------------------------
27862    -- EARC Register Masks
27863    ---------------------------------------------------------------------------- */
27864 
27865 /*!
27866  * @addtogroup EARC_Register_Masks EARC Register Masks
27867  * @{
27868  */
27869 
27870 /*! @name VERSION - Version control register */
27871 /*! @{ */
27872 
27873 #define EARC_VERSION_VERID_MASK                  (0xFFFFFFFFU)
27874 #define EARC_VERSION_VERID_SHIFT                 (0U)
27875 /*! VERID - Version ID */
27876 #define EARC_VERSION_VERID(x)                    (((uint32_t)(((uint32_t)(x)) << EARC_VERSION_VERID_SHIFT)) & EARC_VERSION_VERID_MASK)
27877 /*! @} */
27878 
27879 /*! @name EXT_CTRL - External control register */
27880 /*! @{ */
27881 
27882 #define EARC_EXT_CTRL_TX_FIFO_WMARK_MASK         (0x7FU)
27883 #define EARC_EXT_CTRL_TX_FIFO_WMARK_SHIFT        (0U)
27884 /*! TX_FIFO_WMARK - Audio Transmit FIFO Watermark Level */
27885 #define EARC_EXT_CTRL_TX_FIFO_WMARK(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_TX_FIFO_WMARK_SHIFT)) & EARC_EXT_CTRL_TX_FIFO_WMARK_MASK)
27886 
27887 #define EARC_EXT_CTRL_RX_FIFO_WMARK_MASK         (0x7F00U)
27888 #define EARC_EXT_CTRL_RX_FIFO_WMARK_SHIFT        (8U)
27889 /*! RX_FIFO_WMARK - Audio Receive FIFO Watermark Level */
27890 #define EARC_EXT_CTRL_RX_FIFO_WMARK(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_RX_FIFO_WMARK_SHIFT)) & EARC_EXT_CTRL_RX_FIFO_WMARK_MASK)
27891 
27892 #define EARC_EXT_CTRL_FABRIC_RR_SEL_MASK         (0x8000U)
27893 #define EARC_EXT_CTRL_FABRIC_RR_SEL_SHIFT        (15U)
27894 /*! FABRIC_RR_SEL - Selects Arbitration mode of crossbar switch. */
27895 #define EARC_EXT_CTRL_FABRIC_RR_SEL(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_FABRIC_RR_SEL_SHIFT)) & EARC_EXT_CTRL_FABRIC_RR_SEL_MASK)
27896 
27897 #define EARC_EXT_CTRL_PAGE_MASK                  (0xF0000U)
27898 #define EARC_EXT_CTRL_PAGE_SHIFT                 (16U)
27899 /*! PAGE - Page Select. */
27900 #define EARC_EXT_CTRL_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_PAGE_SHIFT)) & EARC_EXT_CTRL_PAGE_MASK)
27901 
27902 #define EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_MASK (0x200000U)
27903 #define EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_SHIFT (21U)
27904 /*! CORE_SLEEP_HOLD_REQ_B - Hold core from going to sleep mode when 0. */
27905 #define EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_SHIFT)) & EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_MASK)
27906 
27907 #define EARC_EXT_CTRL_CORE_WAIT_MASK             (0x400000U)
27908 #define EARC_EXT_CTRL_CORE_WAIT_SHIFT            (22U)
27909 /*! CORE_WAIT - Stop executing code */
27910 #define EARC_EXT_CTRL_CORE_WAIT(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_CORE_WAIT_SHIFT)) & EARC_EXT_CTRL_CORE_WAIT_MASK)
27911 
27912 #define EARC_EXT_CTRL_SPDIF_MODE_MASK            (0x800000U)
27913 #define EARC_EXT_CTRL_SPDIF_MODE_SHIFT           (23U)
27914 /*! SPDIF_MODE - Indicates SPDIF output mode. */
27915 #define EARC_EXT_CTRL_SPDIF_MODE(x)              (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_SPDIF_MODE_SHIFT)) & EARC_EXT_CTRL_SPDIF_MODE_MASK)
27916 
27917 #define EARC_EXT_CTRL_SDMA_WR_REQ_DIS_MASK       (0x1000000U)
27918 #define EARC_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT      (24U)
27919 /*! SDMA_WR_REQ_DIS - SDMA WR REQ disable */
27920 #define EARC_EXT_CTRL_SDMA_WR_REQ_DIS(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT)) & EARC_EXT_CTRL_SDMA_WR_REQ_DIS_MASK)
27921 
27922 #define EARC_EXT_CTRL_SDMA_RD_REQ_DIS_MASK       (0x2000000U)
27923 #define EARC_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT      (25U)
27924 /*! SDMA_RD_REQ_DIS - SDMA RD REQ disable */
27925 #define EARC_EXT_CTRL_SDMA_RD_REQ_DIS(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT)) & EARC_EXT_CTRL_SDMA_RD_REQ_DIS_MASK)
27926 
27927 #define EARC_EXT_CTRL_TX_DPATH_RESET_MASK        (0x8000000U)
27928 #define EARC_EXT_CTRL_TX_DPATH_RESET_SHIFT       (27U)
27929 /*! TX_DPATH_RESET - Soft reset to the Datapath for Transmit */
27930 #define EARC_EXT_CTRL_TX_DPATH_RESET(x)          (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_TX_DPATH_RESET_SHIFT)) & EARC_EXT_CTRL_TX_DPATH_RESET_MASK)
27931 
27932 #define EARC_EXT_CTRL_RX_DPATH_RESET_MASK        (0x10000000U)
27933 #define EARC_EXT_CTRL_RX_DPATH_RESET_SHIFT       (28U)
27934 /*! RX_DPATH_RESET - Soft reset to the eARC Differential data Receiver */
27935 #define EARC_EXT_CTRL_RX_DPATH_RESET(x)          (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_RX_DPATH_RESET_SHIFT)) & EARC_EXT_CTRL_RX_DPATH_RESET_MASK)
27936 
27937 #define EARC_EXT_CTRL_TX_CMDC_RESET_MASK         (0x20000000U)
27938 #define EARC_EXT_CTRL_TX_CMDC_RESET_SHIFT        (29U)
27939 /*! TX_CMDC_RESET - Soft reset to the eARC Common mode Transmitter */
27940 #define EARC_EXT_CTRL_TX_CMDC_RESET(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_TX_CMDC_RESET_SHIFT)) & EARC_EXT_CTRL_TX_CMDC_RESET_MASK)
27941 
27942 #define EARC_EXT_CTRL_RX_CMDC_RESET_MASK         (0x40000000U)
27943 #define EARC_EXT_CTRL_RX_CMDC_RESET_SHIFT        (30U)
27944 /*! RX_CMDC_RESET - Soft reset to the eARC Common mode Receiver */
27945 #define EARC_EXT_CTRL_RX_CMDC_RESET(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_RX_CMDC_RESET_SHIFT)) & EARC_EXT_CTRL_RX_CMDC_RESET_MASK)
27946 
27947 #define EARC_EXT_CTRL_CORE_RESET_MASK            (0x80000000U)
27948 #define EARC_EXT_CTRL_CORE_RESET_SHIFT           (31U)
27949 /*! CORE_RESET - M0+ Reset */
27950 #define EARC_EXT_CTRL_CORE_RESET(x)              (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_CORE_RESET_SHIFT)) & EARC_EXT_CTRL_CORE_RESET_MASK)
27951 /*! @} */
27952 
27953 /*! @name EXT_STATUS - External Status register */
27954 /*! @{ */
27955 
27956 #define EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK  (0xFFU)
27957 #define EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT (0U)
27958 /*! NO_TX_FIFO_ENTRIES - TX FIFO entries */
27959 #define EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT)) & EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK)
27960 
27961 #define EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK  (0xFF00U)
27962 #define EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT (8U)
27963 /*! NO_RX_FIFO_ENTRIES - RX FIFO entries */
27964 #define EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT)) & EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK)
27965 
27966 #define EARC_EXT_STATUS_CM0_SLEEPING_MASK        (0x10000U)
27967 #define EARC_EXT_STATUS_CM0_SLEEPING_SHIFT       (16U)
27968 /*! CM0_SLEEPING - CM0 is in Sleep mode. */
27969 #define EARC_EXT_STATUS_CM0_SLEEPING(x)          (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_CM0_SLEEPING_SHIFT)) & EARC_EXT_STATUS_CM0_SLEEPING_MASK)
27970 
27971 #define EARC_EXT_STATUS_CM0_DEEP_SLEEP_MASK      (0x20000U)
27972 #define EARC_EXT_STATUS_CM0_DEEP_SLEEP_SHIFT     (17U)
27973 /*! CM0_DEEP_SLEEP - CM0 is in deep sleep mode. */
27974 #define EARC_EXT_STATUS_CM0_DEEP_SLEEP(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_CM0_DEEP_SLEEP_SHIFT)) & EARC_EXT_STATUS_CM0_DEEP_SLEEP_MASK)
27975 
27976 #define EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_MASK (0x40000U)
27977 #define EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_SHIFT (18U)
27978 /*! CM0_SLEEP_HOLD_ACK_B - Sleep extension acknowledge. */
27979 #define EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B(x)  (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_SHIFT)) & EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_MASK)
27980 
27981 #define EARC_EXT_STATUS_TX_PIPE_EMPTY_MASK       (0x200000U)
27982 #define EARC_EXT_STATUS_TX_PIPE_EMPTY_SHIFT      (21U)
27983 /*! TX_PIPE_EMPTY - Indicates TX pipe status. */
27984 #define EARC_EXT_STATUS_TX_PIPE_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_TX_PIPE_EMPTY_SHIFT)) & EARC_EXT_STATUS_TX_PIPE_EMPTY_MASK)
27985 
27986 #define EARC_EXT_STATUS_RX_CMDC_RESP_TO_MASK     (0x800000U)
27987 #define EARC_EXT_STATUS_RX_CMDC_RESP_TO_SHIFT    (23U)
27988 /*! RX_CMDC_RESP_TO - CMDC Response not sent in programmed time */
27989 #define EARC_EXT_STATUS_RX_CMDC_RESP_TO(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_RX_CMDC_RESP_TO_SHIFT)) & EARC_EXT_STATUS_RX_CMDC_RESP_TO_MASK)
27990 
27991 #define EARC_EXT_STATUS_RX_CMDC_COMMA_TO_MASK    (0x2000000U)
27992 #define EARC_EXT_STATUS_RX_CMDC_COMMA_TO_SHIFT   (25U)
27993 /*! RX_CMDC_COMMA_TO - Receiver CMDC comma timeout Interrupt */
27994 #define EARC_EXT_STATUS_RX_CMDC_COMMA_TO(x)      (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_RX_CMDC_COMMA_TO_SHIFT)) & EARC_EXT_STATUS_RX_CMDC_COMMA_TO_MASK)
27995 
27996 #define EARC_EXT_STATUS_HEARTBEAT_STATUS_MASK    (0x8000000U)
27997 #define EARC_EXT_STATUS_HEARTBEAT_STATUS_SHIFT   (27U)
27998 /*! HEARTBEAT_STATUS - Earc Connection Status */
27999 #define EARC_EXT_STATUS_HEARTBEAT_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_HEARTBEAT_STATUS_SHIFT)) & EARC_EXT_STATUS_HEARTBEAT_STATUS_MASK)
28000 
28001 #define EARC_EXT_STATUS_NEW_UD4_REC_MASK         (0x10000000U)
28002 #define EARC_EXT_STATUS_NEW_UD4_REC_SHIFT        (28U)
28003 /*! NEW_UD4_REC - New user data */
28004 #define EARC_EXT_STATUS_NEW_UD4_REC(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NEW_UD4_REC_SHIFT)) & EARC_EXT_STATUS_NEW_UD4_REC_MASK)
28005 
28006 #define EARC_EXT_STATUS_NEW_UD5_REC_MASK         (0x20000000U)
28007 #define EARC_EXT_STATUS_NEW_UD5_REC_SHIFT        (29U)
28008 /*! NEW_UD5_REC - New user data */
28009 #define EARC_EXT_STATUS_NEW_UD5_REC(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NEW_UD5_REC_SHIFT)) & EARC_EXT_STATUS_NEW_UD5_REC_MASK)
28010 
28011 #define EARC_EXT_STATUS_NEW_UD6_REC_MASK         (0x40000000U)
28012 #define EARC_EXT_STATUS_NEW_UD6_REC_SHIFT        (30U)
28013 /*! NEW_UD6_REC - New user data */
28014 #define EARC_EXT_STATUS_NEW_UD6_REC(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NEW_UD6_REC_SHIFT)) & EARC_EXT_STATUS_NEW_UD6_REC_MASK)
28015 
28016 #define EARC_EXT_STATUS_HPD_I_MASK               (0x80000000U)
28017 #define EARC_EXT_STATUS_HPD_I_SHIFT              (31U)
28018 /*! HPD_I - HPD Input status */
28019 #define EARC_EXT_STATUS_HPD_I(x)                 (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_HPD_I_SHIFT)) & EARC_EXT_STATUS_HPD_I_MASK)
28020 /*! @} */
28021 
28022 /*! @name EXT_IER0 - Interrupt enables for interrupt 0 */
28023 /*! @{ */
28024 
28025 #define EARC_EXT_IER0_NEW_CS_IE_0_MASK           (0x1U)
28026 #define EARC_EXT_IER0_NEW_CS_IE_0_SHIFT          (0U)
28027 /*! NEW_CS_IE_0 - Enable for New channel status block received interrupt */
28028 #define EARC_EXT_IER0_NEW_CS_IE_0(x)             (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_NEW_CS_IE_0_SHIFT)) & EARC_EXT_IER0_NEW_CS_IE_0_MASK)
28029 
28030 #define EARC_EXT_IER0_NEW_UD_IE_0_MASK           (0x2U)
28031 #define EARC_EXT_IER0_NEW_UD_IE_0_SHIFT          (1U)
28032 /*! NEW_UD_IE_0 - Enable for new user data received interrupt */
28033 #define EARC_EXT_IER0_NEW_UD_IE_0(x)             (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_NEW_UD_IE_0_SHIFT)) & EARC_EXT_IER0_NEW_UD_IE_0_MASK)
28034 
28035 #define EARC_EXT_IER0_MUTE_IE_0_MASK             (0x4U)
28036 #define EARC_EXT_IER0_MUTE_IE_0_SHIFT            (2U)
28037 /*! MUTE_IE_0 - Enable for Mute detected interrupt */
28038 #define EARC_EXT_IER0_MUTE_IE_0(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_MUTE_IE_0_SHIFT)) & EARC_EXT_IER0_MUTE_IE_0_MASK)
28039 
28040 #define EARC_EXT_IER0_CMDC_RESP_TO_IE_0_MASK     (0x8U)
28041 #define EARC_EXT_IER0_CMDC_RESP_TO_IE_0_SHIFT    (3U)
28042 /*! CMDC_RESP_TO_IE_0 - Receiver CMDC data response timeout interrupt enable */
28043 #define EARC_EXT_IER0_CMDC_RESP_TO_IE_0(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_CMDC_RESP_TO_IE_0_SHIFT)) & EARC_EXT_IER0_CMDC_RESP_TO_IE_0_MASK)
28044 
28045 #define EARC_EXT_IER0_ECC_ERR_IE_0_MASK          (0x10U)
28046 #define EARC_EXT_IER0_ECC_ERR_IE_0_SHIFT         (4U)
28047 /*! ECC_ERR_IE_0 - 60958 Compressed data uncorrectable error interrupt enable */
28048 #define EARC_EXT_IER0_ECC_ERR_IE_0(x)            (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_ECC_ERR_IE_0_SHIFT)) & EARC_EXT_IER0_ECC_ERR_IE_0_MASK)
28049 
28050 #define EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK (0x20U)
28051 #define EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT (5U)
28052 /*! PREAMBLE_MISMATCH_IE_0 - Preamble mismatch interrupt enable. */
28053 #define EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0(x)  (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT)) & EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK)
28054 
28055 #define EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK (0x40U)
28056 #define EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT (6U)
28057 /*! FIFO_OFLOW_UFLOW_ERR_IE_0 - Receive FIFO overflow error interrupt enable. */
28058 #define EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT)) & EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK)
28059 
28060 #define EARC_EXT_IER0_HOST_WAKEUP_IE_0_MASK      (0x80U)
28061 #define EARC_EXT_IER0_HOST_WAKEUP_IE_0_SHIFT     (7U)
28062 /*! HOST_WAKEUP_IE_0 - Host wakeup on CEC match interrupt enable. */
28063 #define EARC_EXT_IER0_HOST_WAKEUP_IE_0(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_HOST_WAKEUP_IE_0_SHIFT)) & EARC_EXT_IER0_HOST_WAKEUP_IE_0_MASK)
28064 
28065 #define EARC_EXT_IER0_OHPD_IE_0_MASK             (0x100U)
28066 #define EARC_EXT_IER0_OHPD_IE_0_SHIFT            (8U)
28067 /*! OHPD_IE_0 - Output HPD interrupt enable. */
28068 #define EARC_EXT_IER0_OHPD_IE_0(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_OHPD_IE_0_SHIFT)) & EARC_EXT_IER0_OHPD_IE_0_MASK)
28069 
28070 #define EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_MASK (0x200U)
28071 #define EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_SHIFT (9U)
28072 /*! DMAC_NO_DATA_REC_IE_0 - Indicates no DMAC data is received. */
28073 #define EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_SHIFT)) & EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_MASK)
28074 
28075 #define EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_MASK (0x400U)
28076 #define EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_SHIFT (10U)
28077 /*! DMAC_FMT_CHG_DET_IE_0 - Indicates DMAC format change was detected */
28078 #define EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_SHIFT)) & EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_MASK)
28079 
28080 #define EARC_EXT_IER0_HB_STATE_CHG_IE_0_MASK     (0x800U)
28081 #define EARC_EXT_IER0_HB_STATE_CHG_IE_0_SHIFT    (11U)
28082 /*! HB_STATE_CHG_IE_0 - Interrupt enable for Heartbeat status change */
28083 #define EARC_EXT_IER0_HB_STATE_CHG_IE_0(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_HB_STATE_CHG_IE_0_SHIFT)) & EARC_EXT_IER0_HB_STATE_CHG_IE_0_MASK)
28084 
28085 #define EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_MASK (0x1000U)
28086 #define EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_SHIFT (12U)
28087 /*! CMDC_STATUS_UPDATE_IE_0 - Interrupt enable for CMDC status register update. */
28088 #define EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_SHIFT)) & EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_MASK)
28089 
28090 #define EARC_EXT_IER0_TEMP_UPDATE_IE_0_MASK      (0x2000U)
28091 #define EARC_EXT_IER0_TEMP_UPDATE_IE_0_SHIFT     (13U)
28092 /*! TEMP_UPDATE_IE_0 - Update request for chip temperature value. */
28093 #define EARC_EXT_IER0_TEMP_UPDATE_IE_0(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_TEMP_UPDATE_IE_0_SHIFT)) & EARC_EXT_IER0_TEMP_UPDATE_IE_0_MASK)
28094 
28095 #define EARC_EXT_IER0_DMA_RD_REQ_IE_0_MASK       (0x4000U)
28096 #define EARC_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT      (14U)
28097 /*! DMA_RD_REQ_IE_0 - Request to read data from FIFO. */
28098 #define EARC_EXT_IER0_DMA_RD_REQ_IE_0(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT)) & EARC_EXT_IER0_DMA_RD_REQ_IE_0_MASK)
28099 
28100 #define EARC_EXT_IER0_DMA_WR_REQ_IE_0_MASK       (0x8000U)
28101 #define EARC_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT      (15U)
28102 /*! DMA_WR_REQ_IE_0 - Request to write data to FIFO. */
28103 #define EARC_EXT_IER0_DMA_WR_REQ_IE_0(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT)) & EARC_EXT_IER0_DMA_WR_REQ_IE_0_MASK)
28104 
28105 #define EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_MASK  (0x10000U)
28106 #define EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_SHIFT (16U)
28107 /*! DMAC_RX_BME_ERR_IE_0 - Bi-phase mark encoding error */
28108 #define EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0(x)    (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_SHIFT)) & EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_MASK)
28109 
28110 #define EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK   (0x20000U)
28111 #define EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT  (17U)
28112 /*! PREAMBLE_MATCH_IE_0 - Interrupt enable for preamble match received. */
28113 #define EARC_EXT_IER0_PREAMBLE_MATCH_IE_0(x)     (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT)) & EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK)
28114 
28115 #define EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK (0x40000U)
28116 #define EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT (18U)
28117 /*! M_W_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame M/W preamble mismatch received. */
28118 #define EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT)) & EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK)
28119 
28120 #define EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK   (0x80000U)
28121 #define EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT  (19U)
28122 /*! B_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame B preamble mismatch received. */
28123 #define EARC_EXT_IER0_B_PRE_MISMATCH_IE_0(x)     (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT)) & EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK)
28124 
28125 #define EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK    (0x100000U)
28126 #define EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT   (20U)
28127 /*! UNEXP_PRE_REC_IE_0 - Interrupt enable for Unexpected preamble received. */
28128 #define EARC_EXT_IER0_UNEXP_PRE_REC_IE_0(x)      (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT)) & EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK)
28129 
28130 #define EARC_EXT_IER0_ARC_MODE_IE_0_MASK         (0x200000U)
28131 #define EARC_EXT_IER0_ARC_MODE_IE_0_SHIFT        (21U)
28132 /*! ARC_MODE_IE_0 - Interrupt to indicate ARC mode setup. */
28133 #define EARC_EXT_IER0_ARC_MODE_IE_0(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_ARC_MODE_IE_0_SHIFT)) & EARC_EXT_IER0_ARC_MODE_IE_0_MASK)
28134 
28135 #define EARC_EXT_IER0_CH_UD_OFLOW_IE_0_MASK      (0x400000U)
28136 #define EARC_EXT_IER0_CH_UD_OFLOW_IE_0_SHIFT     (22U)
28137 /*! CH_UD_OFLOW_IE_0 - Channel status or used data could not be stored. */
28138 #define EARC_EXT_IER0_CH_UD_OFLOW_IE_0(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_CH_UD_OFLOW_IE_0_SHIFT)) & EARC_EXT_IER0_CH_UD_OFLOW_IE_0_MASK)
28139 
28140 #define EARC_EXT_IER0_SPARE_IE_0_MASK            (0xFF800000U)
28141 #define EARC_EXT_IER0_SPARE_IE_0_SHIFT           (23U)
28142 /*! SPARE_IE_0 - Spare interrupts */
28143 #define EARC_EXT_IER0_SPARE_IE_0(x)              (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_SPARE_IE_0_SHIFT)) & EARC_EXT_IER0_SPARE_IE_0_MASK)
28144 /*! @} */
28145 
28146 /*! @name EXT_IER1 - Interrupt enables for interrupt 1 */
28147 /*! @{ */
28148 
28149 #define EARC_EXT_IER1_NEW_CS_IE_1_MASK           (0x1U)
28150 #define EARC_EXT_IER1_NEW_CS_IE_1_SHIFT          (0U)
28151 /*! NEW_CS_IE_1 - Enable for New channel status block received interrupt */
28152 #define EARC_EXT_IER1_NEW_CS_IE_1(x)             (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_NEW_CS_IE_1_SHIFT)) & EARC_EXT_IER1_NEW_CS_IE_1_MASK)
28153 
28154 #define EARC_EXT_IER1_NEW_UD_IE_1_MASK           (0x2U)
28155 #define EARC_EXT_IER1_NEW_UD_IE_1_SHIFT          (1U)
28156 /*! NEW_UD_IE_1 - Enable for new user data received interrupt */
28157 #define EARC_EXT_IER1_NEW_UD_IE_1(x)             (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_NEW_UD_IE_1_SHIFT)) & EARC_EXT_IER1_NEW_UD_IE_1_MASK)
28158 
28159 #define EARC_EXT_IER1_MUTE_IE_1_MASK             (0x4U)
28160 #define EARC_EXT_IER1_MUTE_IE_1_SHIFT            (2U)
28161 /*! MUTE_IE_1 - Enable for Mute detected interrupt */
28162 #define EARC_EXT_IER1_MUTE_IE_1(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_MUTE_IE_1_SHIFT)) & EARC_EXT_IER1_MUTE_IE_1_MASK)
28163 
28164 #define EARC_EXT_IER1_CMDC_RESP_TO_IE_1_MASK     (0x8U)
28165 #define EARC_EXT_IER1_CMDC_RESP_TO_IE_1_SHIFT    (3U)
28166 /*! CMDC_RESP_TO_IE_1 - Receiver CMDC data response timeout interrupt enable */
28167 #define EARC_EXT_IER1_CMDC_RESP_TO_IE_1(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_CMDC_RESP_TO_IE_1_SHIFT)) & EARC_EXT_IER1_CMDC_RESP_TO_IE_1_MASK)
28168 
28169 #define EARC_EXT_IER1_ECC_ERR_IE_1_MASK          (0x10U)
28170 #define EARC_EXT_IER1_ECC_ERR_IE_1_SHIFT         (4U)
28171 /*! ECC_ERR_IE_1 - 60958 Compressed data uncorrectable error interrupt enable */
28172 #define EARC_EXT_IER1_ECC_ERR_IE_1(x)            (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_ECC_ERR_IE_1_SHIFT)) & EARC_EXT_IER1_ECC_ERR_IE_1_MASK)
28173 
28174 #define EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK (0x20U)
28175 #define EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT (5U)
28176 /*! PREAMBLE_MISMATCH_IE_1 - Preamble mismatch interrupt enable. */
28177 #define EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1(x)  (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT)) & EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK)
28178 
28179 #define EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK (0x40U)
28180 #define EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT (6U)
28181 /*! FIFO_OFLOW_UFLOW_ERR_IE_1 - Receive FIFO overflow error interrupt enable. */
28182 #define EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT)) & EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK)
28183 
28184 #define EARC_EXT_IER1_HOST_WAKEUP_IE_1_MASK      (0x80U)
28185 #define EARC_EXT_IER1_HOST_WAKEUP_IE_1_SHIFT     (7U)
28186 /*! HOST_WAKEUP_IE_1 - Host wakeup on CEC match interrupt enable. */
28187 #define EARC_EXT_IER1_HOST_WAKEUP_IE_1(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_HOST_WAKEUP_IE_1_SHIFT)) & EARC_EXT_IER1_HOST_WAKEUP_IE_1_MASK)
28188 
28189 #define EARC_EXT_IER1_OHPD_IE_1_MASK             (0x100U)
28190 #define EARC_EXT_IER1_OHPD_IE_1_SHIFT            (8U)
28191 /*! OHPD_IE_1 - Output HPD interrupt enable. */
28192 #define EARC_EXT_IER1_OHPD_IE_1(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_OHPD_IE_1_SHIFT)) & EARC_EXT_IER1_OHPD_IE_1_MASK)
28193 
28194 #define EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_MASK (0x200U)
28195 #define EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_SHIFT (9U)
28196 /*! DMAC_NO_DATA_REC_IE_1 - Indicates no DMAC data is received. */
28197 #define EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_SHIFT)) & EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_MASK)
28198 
28199 #define EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_MASK (0x400U)
28200 #define EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_SHIFT (10U)
28201 /*! DMAC_FMT_CHG_DET_IE_1 - Indicates DMAC format change was detected */
28202 #define EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_SHIFT)) & EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_MASK)
28203 
28204 #define EARC_EXT_IER1_HB_STATE_CHG_IE_1_MASK     (0x800U)
28205 #define EARC_EXT_IER1_HB_STATE_CHG_IE_1_SHIFT    (11U)
28206 /*! HB_STATE_CHG_IE_1 - Interrupt enable for Heartbeat status change */
28207 #define EARC_EXT_IER1_HB_STATE_CHG_IE_1(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_HB_STATE_CHG_IE_1_SHIFT)) & EARC_EXT_IER1_HB_STATE_CHG_IE_1_MASK)
28208 
28209 #define EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_MASK (0x1000U)
28210 #define EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_SHIFT (12U)
28211 /*! CMDC_STATUS_UPDATE_IE_1 - Interrupt enable for CMDC status register update. */
28212 #define EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_SHIFT)) & EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_MASK)
28213 
28214 #define EARC_EXT_IER1_TEMP_UPDATE_IE_1_MASK      (0x2000U)
28215 #define EARC_EXT_IER1_TEMP_UPDATE_IE_1_SHIFT     (13U)
28216 /*! TEMP_UPDATE_IE_1 - Update request for chip temperature value. */
28217 #define EARC_EXT_IER1_TEMP_UPDATE_IE_1(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_TEMP_UPDATE_IE_1_SHIFT)) & EARC_EXT_IER1_TEMP_UPDATE_IE_1_MASK)
28218 
28219 #define EARC_EXT_IER1_DMA_RD_REQ_IE_1_MASK       (0x4000U)
28220 #define EARC_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT      (14U)
28221 /*! DMA_RD_REQ_IE_1 - Request to read data from FIFO. */
28222 #define EARC_EXT_IER1_DMA_RD_REQ_IE_1(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT)) & EARC_EXT_IER1_DMA_RD_REQ_IE_1_MASK)
28223 
28224 #define EARC_EXT_IER1_DMA_WR_REQ_IE_1_MASK       (0x8000U)
28225 #define EARC_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT      (15U)
28226 /*! DMA_WR_REQ_IE_1 - Request to write data to FIFO. */
28227 #define EARC_EXT_IER1_DMA_WR_REQ_IE_1(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT)) & EARC_EXT_IER1_DMA_WR_REQ_IE_1_MASK)
28228 
28229 #define EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_MASK  (0x10000U)
28230 #define EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_SHIFT (16U)
28231 /*! DMAC_RX_BME_ERR_IE_1 - Bi-phase mark encoding error */
28232 #define EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1(x)    (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_SHIFT)) & EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_MASK)
28233 
28234 #define EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK   (0x20000U)
28235 #define EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT  (17U)
28236 /*! PREAMBLE_MATCH_IE_1 - Interrupt enable for preamble match received. */
28237 #define EARC_EXT_IER1_PREAMBLE_MATCH_IE_1(x)     (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT)) & EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK)
28238 
28239 #define EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK (0x40000U)
28240 #define EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT (18U)
28241 /*! M_W_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame M/W preamble mismatch received. */
28242 #define EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1(x)   (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT)) & EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK)
28243 
28244 #define EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK   (0x80000U)
28245 #define EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT  (19U)
28246 /*! B_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame B preamble mismatch received. */
28247 #define EARC_EXT_IER1_B_PRE_MISMATCH_IE_1(x)     (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT)) & EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK)
28248 
28249 #define EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK    (0x100000U)
28250 #define EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT   (20U)
28251 /*! UNEXP_PRE_REC_IE_1 - Interrupt enable for Unexpected preamble received. */
28252 #define EARC_EXT_IER1_UNEXP_PRE_REC_IE_1(x)      (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT)) & EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK)
28253 
28254 #define EARC_EXT_IER1_ARC_MODE_IE_1_MASK         (0x200000U)
28255 #define EARC_EXT_IER1_ARC_MODE_IE_1_SHIFT        (21U)
28256 /*! ARC_MODE_IE_1 - Interrupt to indicate ARC mode setup. */
28257 #define EARC_EXT_IER1_ARC_MODE_IE_1(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_ARC_MODE_IE_1_SHIFT)) & EARC_EXT_IER1_ARC_MODE_IE_1_MASK)
28258 
28259 #define EARC_EXT_IER1_CH_UD_OFLOW_IE_1_MASK      (0x400000U)
28260 #define EARC_EXT_IER1_CH_UD_OFLOW_IE_1_SHIFT     (22U)
28261 /*! CH_UD_OFLOW_IE_1 - Channel status or used data could not be stored. */
28262 #define EARC_EXT_IER1_CH_UD_OFLOW_IE_1(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_CH_UD_OFLOW_IE_1_SHIFT)) & EARC_EXT_IER1_CH_UD_OFLOW_IE_1_MASK)
28263 
28264 #define EARC_EXT_IER1_SPARE_IE_1_MASK            (0xFF800000U)
28265 #define EARC_EXT_IER1_SPARE_IE_1_SHIFT           (23U)
28266 /*! SPARE_IE_1 - Spare interrupt enables. */
28267 #define EARC_EXT_IER1_SPARE_IE_1(x)              (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_SPARE_IE_1_SHIFT)) & EARC_EXT_IER1_SPARE_IE_1_MASK)
28268 /*! @} */
28269 
28270 /*! @name EXT_ISR - External Interrupt Status register */
28271 /*! @{ */
28272 
28273 #define EARC_EXT_ISR_RX_NEW_CH_STAT_MASK         (0x1U)
28274 #define EARC_EXT_ISR_RX_NEW_CH_STAT_SHIFT        (0U)
28275 /*! RX_NEW_CH_STAT - Received new channel status block */
28276 #define EARC_EXT_ISR_RX_NEW_CH_STAT(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_RX_NEW_CH_STAT_SHIFT)) & EARC_EXT_ISR_RX_NEW_CH_STAT_MASK)
28277 
28278 #define EARC_EXT_ISR_RX_NEW_USR_DATA_MASK        (0x2U)
28279 #define EARC_EXT_ISR_RX_NEW_USR_DATA_SHIFT       (1U)
28280 /*! RX_NEW_USR_DATA - Received new User data Information */
28281 #define EARC_EXT_ISR_RX_NEW_USR_DATA(x)          (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_RX_NEW_USR_DATA_SHIFT)) & EARC_EXT_ISR_RX_NEW_USR_DATA_MASK)
28282 
28283 #define EARC_EXT_ISR_MUTE_DET_MASK               (0x4U)
28284 #define EARC_EXT_ISR_MUTE_DET_SHIFT              (2U)
28285 /*! MUTE_DET - Interrupt to indicate HW mute bit was detected. */
28286 #define EARC_EXT_ISR_MUTE_DET(x)                 (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_MUTE_DET_SHIFT)) & EARC_EXT_ISR_MUTE_DET_MASK)
28287 
28288 #define EARC_EXT_ISR_CMDC_RESP_TO_ERR_MASK       (0x8U)
28289 #define EARC_EXT_ISR_CMDC_RESP_TO_ERR_SHIFT      (3U)
28290 /*! CMDC_RESP_TO_ERR - CMDC response timeout interrupt */
28291 #define EARC_EXT_ISR_CMDC_RESP_TO_ERR(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_CMDC_RESP_TO_ERR_SHIFT)) & EARC_EXT_ISR_CMDC_RESP_TO_ERR_MASK)
28292 
28293 #define EARC_EXT_ISR_ECC_ERR_MASK                (0x10U)
28294 #define EARC_EXT_ISR_ECC_ERR_SHIFT               (4U)
28295 /*! ECC_ERR - 60958 Compressed data uncorrectable error interrupt */
28296 #define EARC_EXT_ISR_ECC_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_ECC_ERR_SHIFT)) & EARC_EXT_ISR_ECC_ERR_MASK)
28297 
28298 #define EARC_EXT_ISR_PREAMBLE_MISMATCH_MASK      (0x20U)
28299 #define EARC_EXT_ISR_PREAMBLE_MISMATCH_SHIFT     (5U)
28300 /*! PREAMBLE_MISMATCH - Preamble mismatch interrupt */
28301 #define EARC_EXT_ISR_PREAMBLE_MISMATCH(x)        (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_PREAMBLE_MISMATCH_SHIFT)) & EARC_EXT_ISR_PREAMBLE_MISMATCH_MASK)
28302 
28303 #define EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK   (0x40U)
28304 #define EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT  (6U)
28305 /*! FIFO_OFLOW_UFLOW_ERR - Receive FIFO overflow error interrupt */
28306 #define EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR(x)     (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT)) & EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK)
28307 
28308 #define EARC_EXT_ISR_HOST_WAKEUP_MASK            (0x80U)
28309 #define EARC_EXT_ISR_HOST_WAKEUP_SHIFT           (7U)
28310 /*! HOST_WAKEUP - Host wakeup on CEC OPCODE match interrupt. */
28311 #define EARC_EXT_ISR_HOST_WAKEUP(x)              (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_HOST_WAKEUP_SHIFT)) & EARC_EXT_ISR_HOST_WAKEUP_MASK)
28312 
28313 #define EARC_EXT_ISR_OHPD_MASK                   (0x100U)
28314 #define EARC_EXT_ISR_OHPD_SHIFT                  (8U)
28315 /*! OHPD - HPD output driver */
28316 #define EARC_EXT_ISR_OHPD(x)                     (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_OHPD_SHIFT)) & EARC_EXT_ISR_OHPD_MASK)
28317 
28318 #define EARC_EXT_ISR_DMAC_NO_DATA_REC_MASK       (0x200U)
28319 #define EARC_EXT_ISR_DMAC_NO_DATA_REC_SHIFT      (9U)
28320 /*! DMAC_NO_DATA_REC - No DMAC data is received for 1us. */
28321 #define EARC_EXT_ISR_DMAC_NO_DATA_REC(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMAC_NO_DATA_REC_SHIFT)) & EARC_EXT_ISR_DMAC_NO_DATA_REC_MASK)
28322 
28323 #define EARC_EXT_ISR_FMT_CHG_DET_MASK            (0x400U)
28324 #define EARC_EXT_ISR_FMT_CHG_DET_SHIFT           (10U)
28325 /*! FMT_CHG_DET - Format change detect interrupt */
28326 #define EARC_EXT_ISR_FMT_CHG_DET(x)              (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_FMT_CHG_DET_SHIFT)) & EARC_EXT_ISR_FMT_CHG_DET_MASK)
28327 
28328 #define EARC_EXT_ISR_HB_STATE_CHG_MASK           (0x800U)
28329 #define EARC_EXT_ISR_HB_STATE_CHG_SHIFT          (11U)
28330 /*! HB_STATE_CHG - Interrupt enable for Heartbeat status change */
28331 #define EARC_EXT_ISR_HB_STATE_CHG(x)             (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_HB_STATE_CHG_SHIFT)) & EARC_EXT_ISR_HB_STATE_CHG_MASK)
28332 
28333 #define EARC_EXT_ISR_CMDC_STATUS_UPDATE_MASK     (0x1000U)
28334 #define EARC_EXT_ISR_CMDC_STATUS_UPDATE_SHIFT    (12U)
28335 /*! CMDC_STATUS_UPDATE - Interrupt enable for CMDC status register update. */
28336 #define EARC_EXT_ISR_CMDC_STATUS_UPDATE(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_CMDC_STATUS_UPDATE_SHIFT)) & EARC_EXT_ISR_CMDC_STATUS_UPDATE_MASK)
28337 
28338 #define EARC_EXT_ISR_TEMP_UPDATE_INT_MASK        (0x2000U)
28339 #define EARC_EXT_ISR_TEMP_UPDATE_INT_SHIFT       (13U)
28340 /*! TEMP_UPDATE_INT - Interrupt to get the new temperature value. */
28341 #define EARC_EXT_ISR_TEMP_UPDATE_INT(x)          (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_TEMP_UPDATE_INT_SHIFT)) & EARC_EXT_ISR_TEMP_UPDATE_INT_MASK)
28342 
28343 #define EARC_EXT_ISR_DMA_RD_REQ_MASK             (0x4000U)
28344 #define EARC_EXT_ISR_DMA_RD_REQ_SHIFT            (14U)
28345 /*! DMA_RD_REQ - Set when DMA read request is asserted. */
28346 #define EARC_EXT_ISR_DMA_RD_REQ(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMA_RD_REQ_SHIFT)) & EARC_EXT_ISR_DMA_RD_REQ_MASK)
28347 
28348 #define EARC_EXT_ISR_DMA_WR_REQ_MASK             (0x8000U)
28349 #define EARC_EXT_ISR_DMA_WR_REQ_SHIFT            (15U)
28350 /*! DMA_WR_REQ - Set when DMA write request is asserted. */
28351 #define EARC_EXT_ISR_DMA_WR_REQ(x)               (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMA_WR_REQ_SHIFT)) & EARC_EXT_ISR_DMA_WR_REQ_MASK)
28352 
28353 #define EARC_EXT_ISR_DMAC_BME_BIT_ERR_MASK       (0x10000U)
28354 #define EARC_EXT_ISR_DMAC_BME_BIT_ERR_SHIFT      (16U)
28355 /*! DMAC_BME_BIT_ERR - Set when DMAC BME data has an error. */
28356 #define EARC_EXT_ISR_DMAC_BME_BIT_ERR(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMAC_BME_BIT_ERR_SHIFT)) & EARC_EXT_ISR_DMAC_BME_BIT_ERR_MASK)
28357 
28358 #define EARC_EXT_ISR_PREAMBLE_MATCH_INT_MASK     (0x20000U)
28359 #define EARC_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT    (17U)
28360 /*! PREAMBLE_MATCH_INT - Interrupt to indicate PA PB / DTC CD preamble match was detected. */
28361 #define EARC_EXT_ISR_PREAMBLE_MATCH_INT(x)       (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT)) & EARC_EXT_ISR_PREAMBLE_MATCH_INT_MASK)
28362 
28363 #define EARC_EXT_ISR_M_W_PRE_MISMATCH_MASK       (0x40000U)
28364 #define EARC_EXT_ISR_M_W_PRE_MISMATCH_SHIFT      (18U)
28365 /*! M_W_PRE_MISMATCH - Set when DMAC preamble of M/W has an error. */
28366 #define EARC_EXT_ISR_M_W_PRE_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_M_W_PRE_MISMATCH_SHIFT)) & EARC_EXT_ISR_M_W_PRE_MISMATCH_MASK)
28367 
28368 #define EARC_EXT_ISR_B_PRE_MISMATCH_MASK         (0x80000U)
28369 #define EARC_EXT_ISR_B_PRE_MISMATCH_SHIFT        (19U)
28370 /*! B_PRE_MISMATCH - Set when DMAC preamble of B has an error. */
28371 #define EARC_EXT_ISR_B_PRE_MISMATCH(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_B_PRE_MISMATCH_SHIFT)) & EARC_EXT_ISR_B_PRE_MISMATCH_MASK)
28372 
28373 #define EARC_EXT_ISR_UNEXP_PRE_REC_MASK          (0x100000U)
28374 #define EARC_EXT_ISR_UNEXP_PRE_REC_SHIFT         (20U)
28375 /*! UNEXP_PRE_REC - Set when DMAC preamble was received after unexpected number of input bits. */
28376 #define EARC_EXT_ISR_UNEXP_PRE_REC(x)            (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_UNEXP_PRE_REC_SHIFT)) & EARC_EXT_ISR_UNEXP_PRE_REC_MASK)
28377 
28378 #define EARC_EXT_ISR_SEL_ARC_MODE_MASK           (0x200000U)
28379 #define EARC_EXT_ISR_SEL_ARC_MODE_SHIFT          (21U)
28380 /*! SEL_ARC_MODE - Set when CMDC SM falls out of eARC mode. */
28381 #define EARC_EXT_ISR_SEL_ARC_MODE(x)             (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_SEL_ARC_MODE_SHIFT)) & EARC_EXT_ISR_SEL_ARC_MODE_MASK)
28382 
28383 #define EARC_EXT_ISR_CS_OR_UD_OFLOW_MASK         (0x400000U)
28384 #define EARC_EXT_ISR_CS_OR_UD_OFLOW_SHIFT        (22U)
28385 /*! CS_OR_UD_OFLOW - Channel status or used data could not be stored. */
28386 #define EARC_EXT_ISR_CS_OR_UD_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_CS_OR_UD_OFLOW_SHIFT)) & EARC_EXT_ISR_CS_OR_UD_OFLOW_MASK)
28387 
28388 #define EARC_EXT_ISR_SPARE_INT_MASK              (0xFF800000U)
28389 #define EARC_EXT_ISR_SPARE_INT_SHIFT             (23U)
28390 /*! SPARE_INT - Extra interrupt. Currently not driven. Can be set by M0 */
28391 #define EARC_EXT_ISR_SPARE_INT(x)                (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_SPARE_INT_SHIFT)) & EARC_EXT_ISR_SPARE_INT_MASK)
28392 /*! @} */
28393 
28394 /*! @name IER - Interrupt enable register for M0+ */
28395 /*! @{ */
28396 
28397 #define EARC_IER_RX_CMDC_RX_DATA_IE_MASK         (0x1U)
28398 #define EARC_IER_RX_CMDC_RX_DATA_IE_SHIFT        (0U)
28399 /*! RX_CMDC_RX_DATA_IE - RX mode CMDC Receive data interrupt enable */
28400 #define EARC_IER_RX_CMDC_RX_DATA_IE(x)           (((uint32_t)(((uint32_t)(x)) << EARC_IER_RX_CMDC_RX_DATA_IE_SHIFT)) & EARC_IER_RX_CMDC_RX_DATA_IE_MASK)
28401 
28402 #define EARC_IER_RX_CMDC_RESP_TO_ERR_IE_MASK     (0x4U)
28403 #define EARC_IER_RX_CMDC_RESP_TO_ERR_IE_SHIFT    (2U)
28404 /*! RX_CMDC_RESP_TO_ERR_IE - Recevier mode Response timeout error interrupt enable */
28405 #define EARC_IER_RX_CMDC_RESP_TO_ERR_IE(x)       (((uint32_t)(((uint32_t)(x)) << EARC_IER_RX_CMDC_RESP_TO_ERR_IE_SHIFT)) & EARC_IER_RX_CMDC_RESP_TO_ERR_IE_MASK)
28406 
28407 #define EARC_IER_CMDC_SPARE_IE_MASK              (0x100U)
28408 #define EARC_IER_CMDC_SPARE_IE_SHIFT             (8U)
28409 /*! CMDC_SPARE_IE - Spare Interrupt. Could be used for Loopback */
28410 #define EARC_IER_CMDC_SPARE_IE(x)                (((uint32_t)(((uint32_t)(x)) << EARC_IER_CMDC_SPARE_IE_SHIFT)) & EARC_IER_CMDC_SPARE_IE_MASK)
28411 
28412 #define EARC_IER_HPD_TGL_IE_MASK                 (0x8000U)
28413 #define EARC_IER_HPD_TGL_IE_SHIFT                (15U)
28414 /*! HPD_TGL_IE - HPD pin level change interrupt enable */
28415 #define EARC_IER_HPD_TGL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << EARC_IER_HPD_TGL_IE_SHIFT)) & EARC_IER_HPD_TGL_IE_MASK)
28416 
28417 #define EARC_IER_PA_PB_DET_IE_MASK               (0x10000U)
28418 #define EARC_IER_PA_PB_DET_IE_SHIFT              (16U)
28419 /*! PA_PB_DET_IE - PA PB detected in Compressed mode interrupt enable */
28420 #define EARC_IER_PA_PB_DET_IE(x)                 (((uint32_t)(((uint32_t)(x)) << EARC_IER_PA_PB_DET_IE_SHIFT)) & EARC_IER_PA_PB_DET_IE_MASK)
28421 
28422 #define EARC_IER_DATA_BLK_REC_IE_MASK            (0x20000U)
28423 #define EARC_IER_DATA_BLK_REC_IE_SHIFT           (17U)
28424 /*! DATA_BLK_REC_IE - 60958 block of data received interrupt enable. */
28425 #define EARC_IER_DATA_BLK_REC_IE(x)              (((uint32_t)(((uint32_t)(x)) << EARC_IER_DATA_BLK_REC_IE_SHIFT)) & EARC_IER_DATA_BLK_REC_IE_MASK)
28426 
28427 #define EARC_IER_FMT_CHG_IE_MASK                 (0x40000U)
28428 #define EARC_IER_FMT_CHG_IE_SHIFT                (18U)
28429 /*! FMT_CHG_IE - Format Chnage interrupt. */
28430 #define EARC_IER_FMT_CHG_IE(x)                   (((uint32_t)(((uint32_t)(x)) << EARC_IER_FMT_CHG_IE_SHIFT)) & EARC_IER_FMT_CHG_IE_MASK)
28431 
28432 #define EARC_IER_DMAC_SPARE_IE_MASK              (0x80000U)
28433 #define EARC_IER_DMAC_SPARE_IE_SHIFT             (19U)
28434 /*! DMAC_SPARE_IE - Spare Interrupt. Could be used for Loopback */
28435 #define EARC_IER_DMAC_SPARE_IE(x)                (((uint32_t)(((uint32_t)(x)) << EARC_IER_DMAC_SPARE_IE_SHIFT)) & EARC_IER_DMAC_SPARE_IE_MASK)
28436 
28437 #define EARC_IER_SET_SPDIF_RX_IE_MASK            (0x100000U)
28438 #define EARC_IER_SET_SPDIF_RX_IE_SHIFT           (20U)
28439 /*! SET_SPDIF_RX_IE - Interrupt enable to set up SPDIF RX mode */
28440 #define EARC_IER_SET_SPDIF_RX_IE(x)              (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_SPDIF_RX_IE_SHIFT)) & EARC_IER_SET_SPDIF_RX_IE_MASK)
28441 
28442 #define EARC_IER_SET_SPDIF_TX_IE_MASK            (0x200000U)
28443 #define EARC_IER_SET_SPDIF_TX_IE_SHIFT           (21U)
28444 /*! SET_SPDIF_TX_IE - Interrupt enable to set up SPDIF TX mode */
28445 #define EARC_IER_SET_SPDIF_TX_IE(x)              (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_SPDIF_TX_IE_SHIFT)) & EARC_IER_SET_SPDIF_TX_IE_MASK)
28446 
28447 #define EARC_IER_SET_ARC_CM_IE_MASK              (0x400000U)
28448 #define EARC_IER_SET_ARC_CM_IE_SHIFT             (22U)
28449 /*! SET_ARC_CM_IE - Interrupt enable to set up PHY as Common mode ARC receiver */
28450 #define EARC_IER_SET_ARC_CM_IE(x)                (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_ARC_CM_IE_SHIFT)) & EARC_IER_SET_ARC_CM_IE_MASK)
28451 
28452 #define EARC_IER_SET_ARC_SE_IE_MASK              (0x800000U)
28453 #define EARC_IER_SET_ARC_SE_IE_SHIFT             (23U)
28454 /*! SET_ARC_SE_IE - Interrupt enable to set up PHY as Single ended mode ARC receiver */
28455 #define EARC_IER_SET_ARC_SE_IE(x)                (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_ARC_SE_IE_SHIFT)) & EARC_IER_SET_ARC_SE_IE_MASK)
28456 
28457 #define EARC_IER_SW_HPD_TGL_IE_MASK              (0x1000000U)
28458 #define EARC_IER_SW_HPD_TGL_IE_SHIFT             (24U)
28459 /*! SW_HPD_TGL_IE - Interrupt enable to allow SW to assert HPD. */
28460 #define EARC_IER_SW_HPD_TGL_IE(x)                (((uint32_t)(((uint32_t)(x)) << EARC_IER_SW_HPD_TGL_IE_SHIFT)) & EARC_IER_SW_HPD_TGL_IE_MASK)
28461 
28462 #define EARC_IER_TEMP_UPDATED_IE_MASK            (0x2000000U)
28463 #define EARC_IER_TEMP_UPDATED_IE_SHIFT           (25U)
28464 /*! TEMP_UPDATED_IE - Interrupt enable to allow SW to indicate new temperature value is available. */
28465 #define EARC_IER_TEMP_UPDATED_IE(x)              (((uint32_t)(((uint32_t)(x)) << EARC_IER_TEMP_UPDATED_IE_SHIFT)) & EARC_IER_TEMP_UPDATED_IE_MASK)
28466 /*! @} */
28467 
28468 /*! @name ISR - Interrupt status register */
28469 /*! @{ */
28470 
28471 #define EARC_ISR_RX_CMDC_RX_DATA_MASK            (0x1U)
28472 #define EARC_ISR_RX_CMDC_RX_DATA_SHIFT           (0U)
28473 /*! RX_CMDC_RX_DATA - Receiver mode CMDC Receive data */
28474 #define EARC_ISR_RX_CMDC_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EARC_ISR_RX_CMDC_RX_DATA_SHIFT)) & EARC_ISR_RX_CMDC_RX_DATA_MASK)
28475 
28476 #define EARC_ISR_RX_CMDC_RESP_TO_ERR_MASK        (0x4U)
28477 #define EARC_ISR_RX_CMDC_RESP_TO_ERR_SHIFT       (2U)
28478 /*! RX_CMDC_RESP_TO_ERR - Recevier mode CMDC Response timeout error */
28479 #define EARC_ISR_RX_CMDC_RESP_TO_ERR(x)          (((uint32_t)(((uint32_t)(x)) << EARC_ISR_RX_CMDC_RESP_TO_ERR_SHIFT)) & EARC_ISR_RX_CMDC_RESP_TO_ERR_MASK)
28480 
28481 #define EARC_ISR_CMDC_SPARE_INT_MASK             (0x100U)
28482 #define EARC_ISR_CMDC_SPARE_INT_SHIFT            (8U)
28483 /*! CMDC_SPARE_INT - Spare Interrupt */
28484 #define EARC_ISR_CMDC_SPARE_INT(x)               (((uint32_t)(((uint32_t)(x)) << EARC_ISR_CMDC_SPARE_INT_SHIFT)) & EARC_ISR_CMDC_SPARE_INT_MASK)
28485 
28486 #define EARC_ISR_HPD_TGL_MASK                    (0x8000U)
28487 #define EARC_ISR_HPD_TGL_SHIFT                   (15U)
28488 /*! HPD_TGL - HPD pin level change interrupt */
28489 #define EARC_ISR_HPD_TGL(x)                      (((uint32_t)(((uint32_t)(x)) << EARC_ISR_HPD_TGL_SHIFT)) & EARC_ISR_HPD_TGL_MASK)
28490 
28491 #define EARC_ISR_PA_PB_DET_MASK                  (0x10000U)
28492 #define EARC_ISR_PA_PB_DET_SHIFT                 (16U)
28493 /*! PA_PB_DET - PA PB detected in Compressed mode */
28494 #define EARC_ISR_PA_PB_DET(x)                    (((uint32_t)(((uint32_t)(x)) << EARC_ISR_PA_PB_DET_SHIFT)) & EARC_ISR_PA_PB_DET_MASK)
28495 
28496 #define EARC_ISR_DATA_BLK_REC_MASK               (0x20000U)
28497 #define EARC_ISR_DATA_BLK_REC_SHIFT              (17U)
28498 /*! DATA_BLK_REC - 60958 block of data received interrupt. */
28499 #define EARC_ISR_DATA_BLK_REC(x)                 (((uint32_t)(((uint32_t)(x)) << EARC_ISR_DATA_BLK_REC_SHIFT)) & EARC_ISR_DATA_BLK_REC_MASK)
28500 
28501 #define EARC_ISR_FMT_CHG_INT_MASK                (0x40000U)
28502 #define EARC_ISR_FMT_CHG_INT_SHIFT               (18U)
28503 /*! FMT_CHG_INT - Format Change interrupt. */
28504 #define EARC_ISR_FMT_CHG_INT(x)                  (((uint32_t)(((uint32_t)(x)) << EARC_ISR_FMT_CHG_INT_SHIFT)) & EARC_ISR_FMT_CHG_INT_MASK)
28505 
28506 #define EARC_ISR_DMAC_SPARE_INT_MASK             (0x80000U)
28507 #define EARC_ISR_DMAC_SPARE_INT_SHIFT            (19U)
28508 /*! DMAC_SPARE_INT - Spare Interrupt */
28509 #define EARC_ISR_DMAC_SPARE_INT(x)               (((uint32_t)(((uint32_t)(x)) << EARC_ISR_DMAC_SPARE_INT_SHIFT)) & EARC_ISR_DMAC_SPARE_INT_MASK)
28510 
28511 #define EARC_ISR_SET_SPDIF_RX_MODE_MASK          (0x100000U)
28512 #define EARC_ISR_SET_SPDIF_RX_MODE_SHIFT         (20U)
28513 /*! SET_SPDIF_RX_MODE - Interrupt to set up PHY and controller in SPDIF RX mode. */
28514 #define EARC_ISR_SET_SPDIF_RX_MODE(x)            (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_SPDIF_RX_MODE_SHIFT)) & EARC_ISR_SET_SPDIF_RX_MODE_MASK)
28515 
28516 #define EARC_ISR_SET_SPDIF_TX_MODE_MASK          (0x200000U)
28517 #define EARC_ISR_SET_SPDIF_TX_MODE_SHIFT         (21U)
28518 /*! SET_SPDIF_TX_MODE - Interrupt to set up PHY and controller in SPDIF TX mode. */
28519 #define EARC_ISR_SET_SPDIF_TX_MODE(x)            (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_SPDIF_TX_MODE_SHIFT)) & EARC_ISR_SET_SPDIF_TX_MODE_MASK)
28520 
28521 #define EARC_ISR_SET_ARC_CM_INT_MASK             (0x400000U)
28522 #define EARC_ISR_SET_ARC_CM_INT_SHIFT            (22U)
28523 /*! SET_ARC_CM_INT - Interrupt enable to set up PHY as Common mode ARC receiver */
28524 #define EARC_ISR_SET_ARC_CM_INT(x)               (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_ARC_CM_INT_SHIFT)) & EARC_ISR_SET_ARC_CM_INT_MASK)
28525 
28526 #define EARC_ISR_SET_ARC_SE_INT_MASK             (0x800000U)
28527 #define EARC_ISR_SET_ARC_SE_INT_SHIFT            (23U)
28528 /*! SET_ARC_SE_INT - Interrupt enable to set up PHY as Single ended mode ARC receiver */
28529 #define EARC_ISR_SET_ARC_SE_INT(x)               (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_ARC_SE_INT_SHIFT)) & EARC_ISR_SET_ARC_SE_INT_MASK)
28530 
28531 #define EARC_ISR_SW_HPD_TGL_INT_MASK             (0x1000000U)
28532 #define EARC_ISR_SW_HPD_TGL_INT_SHIFT            (24U)
28533 /*! SW_HPD_TGL_INT - Interrupt enable to set up PHY as Single ended mode ARC receiver */
28534 #define EARC_ISR_SW_HPD_TGL_INT(x)               (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SW_HPD_TGL_INT_SHIFT)) & EARC_ISR_SW_HPD_TGL_INT_MASK)
28535 
28536 #define EARC_ISR_TEMP_UPDATED_MASK               (0x2000000U)
28537 #define EARC_ISR_TEMP_UPDATED_SHIFT              (25U)
28538 /*! TEMP_UPDATED - Interrupt to indicate new temperature value is available. */
28539 #define EARC_ISR_TEMP_UPDATED(x)                 (((uint32_t)(((uint32_t)(x)) << EARC_ISR_TEMP_UPDATED_SHIFT)) & EARC_ISR_TEMP_UPDATED_MASK)
28540 /*! @} */
28541 
28542 /*! @name PHY_AI_CTRL - AI interface control register */
28543 /*! @{ */
28544 
28545 #define EARC_PHY_AI_CTRL_AI_ADDR_MASK            (0xFFU)
28546 #define EARC_PHY_AI_CTRL_AI_ADDR_SHIFT           (0U)
28547 /*! AI_ADDR - AI ADDR value */
28548 #define EARC_PHY_AI_CTRL_AI_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_AI_ADDR_SHIFT)) & EARC_PHY_AI_CTRL_AI_ADDR_MASK)
28549 
28550 #define EARC_PHY_AI_CTRL_AI_RESETN_MASK          (0x8000U)
28551 #define EARC_PHY_AI_CTRL_AI_RESETN_SHIFT         (15U)
28552 /*! AI_RESETN - AI reset bit */
28553 #define EARC_PHY_AI_CTRL_AI_RESETN(x)            (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_AI_RESETN_SHIFT)) & EARC_PHY_AI_CTRL_AI_RESETN_MASK)
28554 
28555 #define EARC_PHY_AI_CTRL_TOG_0_MASK              (0x1000000U)
28556 #define EARC_PHY_AI_CTRL_TOG_0_SHIFT             (24U)
28557 /*! TOG_0 - AI toggle bit */
28558 #define EARC_PHY_AI_CTRL_TOG_0(x)                (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_0_SHIFT)) & EARC_PHY_AI_CTRL_TOG_0_MASK)
28559 
28560 #define EARC_PHY_AI_CTRL_TOG_DONE_0_MASK         (0x2000000U)
28561 #define EARC_PHY_AI_CTRL_TOG_DONE_0_SHIFT        (25U)
28562 /*! TOG_DONE_0 - AI toggle done bit */
28563 #define EARC_PHY_AI_CTRL_TOG_DONE_0(x)           (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_DONE_0_SHIFT)) & EARC_PHY_AI_CTRL_TOG_DONE_0_MASK)
28564 
28565 #define EARC_PHY_AI_CTRL_TOG_1_MASK              (0x4000000U)
28566 #define EARC_PHY_AI_CTRL_TOG_1_SHIFT             (26U)
28567 /*! TOG_1 - AI toggle bit */
28568 #define EARC_PHY_AI_CTRL_TOG_1(x)                (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_1_SHIFT)) & EARC_PHY_AI_CTRL_TOG_1_MASK)
28569 
28570 #define EARC_PHY_AI_CTRL_TOG_DONE_1_MASK         (0x8000000U)
28571 #define EARC_PHY_AI_CTRL_TOG_DONE_1_SHIFT        (27U)
28572 /*! TOG_DONE_1 - AI toggle done bit */
28573 #define EARC_PHY_AI_CTRL_TOG_DONE_1(x)           (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_DONE_1_SHIFT)) & EARC_PHY_AI_CTRL_TOG_DONE_1_MASK)
28574 
28575 #define EARC_PHY_AI_CTRL_AI_RWB_MASK             (0x80000000U)
28576 #define EARC_PHY_AI_CTRL_AI_RWB_SHIFT            (31U)
28577 /*! AI_RWB - AI Read / write control bit */
28578 #define EARC_PHY_AI_CTRL_AI_RWB(x)               (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_AI_RWB_SHIFT)) & EARC_PHY_AI_CTRL_AI_RWB_MASK)
28579 /*! @} */
28580 
28581 /*! @name PHY_AI_WDATA - AI interface WDATA register */
28582 /*! @{ */
28583 
28584 #define EARC_PHY_AI_WDATA_WDATA_MASK             (0xFFFFFFFFU)
28585 #define EARC_PHY_AI_WDATA_WDATA_SHIFT            (0U)
28586 /*! WDATA - Write data */
28587 #define EARC_PHY_AI_WDATA_WDATA(x)               (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_WDATA_WDATA_SHIFT)) & EARC_PHY_AI_WDATA_WDATA_MASK)
28588 /*! @} */
28589 
28590 /*! @name PHY_AI_RDATA - AI interface RDATA register */
28591 /*! @{ */
28592 
28593 #define EARC_PHY_AI_RDATA_RDATA_MASK             (0xFFFFFFFFU)
28594 #define EARC_PHY_AI_RDATA_RDATA_SHIFT            (0U)
28595 /*! RDATA - Read data */
28596 #define EARC_PHY_AI_RDATA_RDATA(x)               (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_RDATA_RDATA_SHIFT)) & EARC_PHY_AI_RDATA_RDATA_MASK)
28597 /*! @} */
28598 
28599 /*! @name DPATH_STATUS - Audio XCVR datapath status */
28600 /*! @{ */
28601 
28602 #define EARC_DPATH_STATUS_RX_FRM_CNT_MASK        (0xFFU)
28603 #define EARC_DPATH_STATUS_RX_FRM_CNT_SHIFT       (0U)
28604 /*! RX_FRM_CNT - Count of received frames in a block */
28605 #define EARC_DPATH_STATUS_RX_FRM_CNT(x)          (((uint32_t)(((uint32_t)(x)) << EARC_DPATH_STATUS_RX_FRM_CNT_SHIFT)) & EARC_DPATH_STATUS_RX_FRM_CNT_MASK)
28606 
28607 #define EARC_DPATH_STATUS_TX_FRM_CNT_MASK        (0xFF00U)
28608 #define EARC_DPATH_STATUS_TX_FRM_CNT_SHIFT       (8U)
28609 /*! TX_FRM_CNT - Count of transmitted frames in a block */
28610 #define EARC_DPATH_STATUS_TX_FRM_CNT(x)          (((uint32_t)(((uint32_t)(x)) << EARC_DPATH_STATUS_TX_FRM_CNT_SHIFT)) & EARC_DPATH_STATUS_TX_FRM_CNT_MASK)
28611 /*! @} */
28612 
28613 /*! @name RX_CMDC_CTRL - CMDC receiver control register */
28614 /*! @{ */
28615 
28616 #define EARC_RX_CMDC_CTRL_COMMA_BITS_MASK        (0x1FU)
28617 #define EARC_RX_CMDC_CTRL_COMMA_BITS_SHIFT       (0U)
28618 /*! COMMA_BITS - Number of repeating bits in COMMA pattern */
28619 #define EARC_RX_CMDC_CTRL_COMMA_BITS(x)          (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_COMMA_BITS_SHIFT)) & EARC_RX_CMDC_CTRL_COMMA_BITS_MASK)
28620 
28621 #define EARC_RX_CMDC_CTRL_COMMA_EN_MASK          (0x80U)
28622 #define EARC_RX_CMDC_CTRL_COMMA_EN_SHIFT         (7U)
28623 /*! COMMA_EN - Enables COMMA pattern generation */
28624 #define EARC_RX_CMDC_CTRL_COMMA_EN(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_COMMA_EN_SHIFT)) & EARC_RX_CMDC_CTRL_COMMA_EN_MASK)
28625 
28626 #define EARC_RX_CMDC_CTRL_RESPONSE_TIME_MASK     (0x1F00U)
28627 #define EARC_RX_CMDC_CTRL_RESPONSE_TIME_SHIFT    (8U)
28628 /*! RESPONSE_TIME - Transmitter response timeout to a received message */
28629 #define EARC_RX_CMDC_CTRL_RESPONSE_TIME(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_RESPONSE_TIME_SHIFT)) & EARC_RX_CMDC_CTRL_RESPONSE_TIME_MASK)
28630 
28631 #define EARC_RX_CMDC_CTRL_TURNOVER_TIME_MASK     (0xF0000U)
28632 #define EARC_RX_CMDC_CTRL_TURNOVER_TIME_SHIFT    (16U)
28633 /*! TURNOVER_TIME - Minimum time before a response is generated */
28634 #define EARC_RX_CMDC_CTRL_TURNOVER_TIME(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_TURNOVER_TIME_SHIFT)) & EARC_RX_CMDC_CTRL_TURNOVER_TIME_MASK)
28635 
28636 #define EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_MASK     (0x700000U)
28637 #define EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_SHIFT    (20U)
28638 /*! TX_DRIVE_STOP - Transmitter bus release time */
28639 #define EARC_RX_CMDC_CTRL_TX_DRIVE_STOP(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_SHIFT)) & EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_MASK)
28640 
28641 #define EARC_RX_CMDC_CTRL_LBACK_EN_MASK          (0x80000000U)
28642 #define EARC_RX_CMDC_CTRL_LBACK_EN_SHIFT         (31U)
28643 /*! LBACK_EN - Loopback enable */
28644 #define EARC_RX_CMDC_CTRL_LBACK_EN(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_LBACK_EN_SHIFT)) & EARC_RX_CMDC_CTRL_LBACK_EN_MASK)
28645 /*! @} */
28646 
28647 /*! @name RX_CMDC_STATUS - eARC receiver CMDC status */
28648 /*! @{ */
28649 
28650 #define EARC_RX_CMDC_STATUS_CMDC_STATE_MASK      (0xF0000U)
28651 #define EARC_RX_CMDC_STATUS_CMDC_STATE_SHIFT     (16U)
28652 /*! CMDC_STATE - Current state of the RX CDMC control state machine */
28653 #define EARC_RX_CMDC_STATUS_CMDC_STATE(x)        (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_STATUS_CMDC_STATE_SHIFT)) & EARC_RX_CMDC_STATUS_CMDC_STATE_MASK)
28654 /*! @} */
28655 
28656 /*! @name RX_CMDC_TX_DATA - CMDC transmit data register */
28657 /*! @{ */
28658 
28659 #define EARC_RX_CMDC_TX_DATA_TX_DATA_MASK        (0x3FFFFFFU)
28660 #define EARC_RX_CMDC_TX_DATA_TX_DATA_SHIFT       (0U)
28661 /*! TX_DATA - Transmit data */
28662 #define EARC_RX_CMDC_TX_DATA_TX_DATA(x)          (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_TX_DATA_TX_DATA_SHIFT)) & EARC_RX_CMDC_TX_DATA_TX_DATA_MASK)
28663 
28664 #define EARC_RX_CMDC_TX_DATA_DATA_VALID_MASK     (0x80000000U)
28665 #define EARC_RX_CMDC_TX_DATA_DATA_VALID_SHIFT    (31U)
28666 /*! DATA_VALID - Transmit Data Valid */
28667 #define EARC_RX_CMDC_TX_DATA_DATA_VALID(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_TX_DATA_DATA_VALID_SHIFT)) & EARC_RX_CMDC_TX_DATA_DATA_VALID_MASK)
28668 /*! @} */
28669 
28670 /*! @name RX_CMDC_RX_DATA - CMDC receive data register */
28671 /*! @{ */
28672 
28673 #define EARC_RX_CMDC_RX_DATA_RX_DATA_MASK        (0x3FFFFFFU)
28674 #define EARC_RX_CMDC_RX_DATA_RX_DATA_SHIFT       (0U)
28675 /*! RX_DATA - Receive data */
28676 #define EARC_RX_CMDC_RX_DATA_RX_DATA(x)          (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_RX_DATA_RX_DATA_SHIFT)) & EARC_RX_CMDC_RX_DATA_RX_DATA_MASK)
28677 /*! @} */
28678 
28679 /*! @name RX_DATAPATH_CTRL - Data path control register */
28680 /*! @{ */
28681 
28682 #define EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK (0x1U)
28683 #define EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT (0U)
28684 #define EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT)) & EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK)
28685 
28686 #define EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_MASK (0x8U)
28687 #define EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_SHIFT (3U)
28688 /*! ECC_VUC_BITS_EN - RX_DATAPATH: Enable VUC bit replacement after ECC correction. */
28689 #define EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_SHIFT)) & EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_MASK)
28690 
28691 #define EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_MASK (0x10U)
28692 #define EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_SHIFT (4U)
28693 /*! EN_COMP_PARITY_CALC - RX_DATAPATH: Enable Compressed mode Parity calculation. */
28694 #define EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_SHIFT)) & EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_MASK)
28695 
28696 #define EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK (0x20U)
28697 #define EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT (5U)
28698 /*! RST_PKT_CNT_FIFO - Resets the packet count fifo. */
28699 #define EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT)) & EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK)
28700 
28701 #define EARC_RX_DATAPATH_CTRL_STORE_FMT_MASK     (0x40U)
28702 #define EARC_RX_DATAPATH_CTRL_STORE_FMT_SHIFT    (6U)
28703 /*! STORE_FMT - Receive Data store format. */
28704 #define EARC_RX_DATAPATH_CTRL_STORE_FMT(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_STORE_FMT_SHIFT)) & EARC_RX_DATAPATH_CTRL_STORE_FMT_MASK)
28705 
28706 #define EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK (0x80U)
28707 #define EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT (7U)
28708 /*! EN_PARITY_CALC - Enable Parity calculation. */
28709 #define EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC(x)  (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT)) & EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK)
28710 
28711 #define EARC_RX_DATAPATH_CTRL_UDR_MASK           (0x100U)
28712 #define EARC_RX_DATAPATH_CTRL_UDR_SHIFT          (8U)
28713 /*! UDR - User data reset */
28714 #define EARC_RX_DATAPATH_CTRL_UDR(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_UDR_SHIFT)) & EARC_RX_DATAPATH_CTRL_UDR_MASK)
28715 
28716 #define EARC_RX_DATAPATH_CTRL_CSR_MASK           (0x200U)
28717 #define EARC_RX_DATAPATH_CTRL_CSR_SHIFT          (9U)
28718 /*! CSR - Channel Status reset */
28719 #define EARC_RX_DATAPATH_CTRL_CSR(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_CSR_SHIFT)) & EARC_RX_DATAPATH_CTRL_CSR_MASK)
28720 
28721 #define EARC_RX_DATAPATH_CTRL_UDA_MASK           (0x400U)
28722 #define EARC_RX_DATAPATH_CTRL_UDA_SHIFT          (10U)
28723 /*! UDA - User Data Acknowledge */
28724 #define EARC_RX_DATAPATH_CTRL_UDA(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_UDA_SHIFT)) & EARC_RX_DATAPATH_CTRL_UDA_MASK)
28725 
28726 #define EARC_RX_DATAPATH_CTRL_CSA_MASK           (0x800U)
28727 #define EARC_RX_DATAPATH_CTRL_CSA_SHIFT          (11U)
28728 /*! CSA - Channel Status Acknowledge */
28729 #define EARC_RX_DATAPATH_CTRL_CSA(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_CSA_SHIFT)) & EARC_RX_DATAPATH_CTRL_CSA_MASK)
28730 
28731 #define EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK   (0x1000U)
28732 #define EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT  (12U)
28733 /*! CLR_RX_FIFO - Clear Receive FIFO */
28734 #define EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO(x)     (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT)) & EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK)
28735 
28736 #define EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK   (0xC000U)
28737 #define EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT  (14U)
28738 /*! RX_DATA_FMT - Indicates format of data stored in memory. */
28739 #define EARC_RX_DATAPATH_CTRL_RX_DATA_FMT(x)     (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT)) & EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK)
28740 
28741 #define EARC_RX_DATAPATH_CTRL_PABS_MASK          (0x80000U)
28742 #define EARC_RX_DATAPATH_CTRL_PABS_SHIFT         (19U)
28743 /*! PABS - Enable preamble search */
28744 #define EARC_RX_DATAPATH_CTRL_PABS(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_PABS_SHIFT)) & EARC_RX_DATAPATH_CTRL_PABS_MASK)
28745 
28746 #define EARC_RX_DATAPATH_CTRL_DTS_CDS_MASK       (0x100000U)
28747 #define EARC_RX_DATAPATH_CTRL_DTS_CDS_SHIFT      (20U)
28748 /*! DTS_CDS - Enable DTS CD 14 preamble search */
28749 #define EARC_RX_DATAPATH_CTRL_DTS_CDS(x)         (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_DTS_CDS_SHIFT)) & EARC_RX_DATAPATH_CTRL_DTS_CDS_MASK)
28750 
28751 #define EARC_RX_DATAPATH_CTRL_BLKC_MASK          (0x200000U)
28752 #define EARC_RX_DATAPATH_CTRL_BLKC_SHIFT         (21U)
28753 /*! BLKC - Block Compressed data */
28754 #define EARC_RX_DATAPATH_CTRL_BLKC(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_BLKC_SHIFT)) & EARC_RX_DATAPATH_CTRL_BLKC_MASK)
28755 
28756 #define EARC_RX_DATAPATH_CTRL_MUTE_CTRL_MASK     (0x400000U)
28757 #define EARC_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT    (22U)
28758 /*! MUTE_CTRL - M0+ mute request */
28759 #define EARC_RX_DATAPATH_CTRL_MUTE_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT)) & EARC_RX_DATAPATH_CTRL_MUTE_CTRL_MASK)
28760 
28761 #define EARC_RX_DATAPATH_CTRL_MUTE_MODE_MASK     (0x800000U)
28762 #define EARC_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT    (23U)
28763 /*! MUTE_MODE - Mute mode control */
28764 #define EARC_RX_DATAPATH_CTRL_MUTE_MODE(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT)) & EARC_RX_DATAPATH_CTRL_MUTE_MODE_MASK)
28765 
28766 #define EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_MASK  (0x1000000U)
28767 #define EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_SHIFT (24U)
28768 /*! FMT_CHG_CTRL - Format Change detection control. */
28769 #define EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_SHIFT)) & EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_MASK)
28770 
28771 #define EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_MASK  (0x2000000U)
28772 #define EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_SHIFT (25U)
28773 /*! FMT_CHG_MODE - Format change detected. Reset HW for next frame */
28774 #define EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE(x)    (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_SHIFT)) & EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_MASK)
28775 
28776 #define EARC_RX_DATAPATH_CTRL_LAYB_CTRL_MASK     (0x4000000U)
28777 #define EARC_RX_DATAPATH_CTRL_LAYB_CTRL_SHIFT    (26U)
28778 /*! LAYB_CTRL - Layout B mode control */
28779 #define EARC_RX_DATAPATH_CTRL_LAYB_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_LAYB_CTRL_SHIFT)) & EARC_RX_DATAPATH_CTRL_LAYB_CTRL_MASK)
28780 
28781 #define EARC_RX_DATAPATH_CTRL_LAYB_MODE_MASK     (0x8000000U)
28782 #define EARC_RX_DATAPATH_CTRL_LAYB_MODE_SHIFT    (27U)
28783 /*! LAYB_MODE - Layout B */
28784 #define EARC_RX_DATAPATH_CTRL_LAYB_MODE(x)       (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_LAYB_MODE_SHIFT)) & EARC_RX_DATAPATH_CTRL_LAYB_MODE_MASK)
28785 
28786 #define EARC_RX_DATAPATH_CTRL_PRC_MASK           (0x10000000U)
28787 #define EARC_RX_DATAPATH_CTRL_PRC_SHIFT          (28U)
28788 /*! PRC - Process Compressed */
28789 #define EARC_RX_DATAPATH_CTRL_PRC(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_PRC_SHIFT)) & EARC_RX_DATAPATH_CTRL_PRC_MASK)
28790 
28791 #define EARC_RX_DATAPATH_CTRL_COMP_MASK          (0x20000000U)
28792 #define EARC_RX_DATAPATH_CTRL_COMP_SHIFT         (29U)
28793 /*! COMP - Compressed data search mode */
28794 #define EARC_RX_DATAPATH_CTRL_COMP(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_COMP_SHIFT)) & EARC_RX_DATAPATH_CTRL_COMP_MASK)
28795 
28796 #define EARC_RX_DATAPATH_CTRL_FSM_MASK           (0xC0000000U)
28797 #define EARC_RX_DATAPATH_CTRL_FSM_SHIFT          (30U)
28798 /*! FSM - IEC60958-1 Frame Synchronization Mode */
28799 #define EARC_RX_DATAPATH_CTRL_FSM(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_FSM_SHIFT)) & EARC_RX_DATAPATH_CTRL_FSM_MASK)
28800 /*! @} */
28801 
28802 /*! @name RX_CS_DATA_BITS - Channel staus bits */
28803 /*! @{ */
28804 
28805 #define EARC_RX_CS_DATA_BITS_CS_DATA_MASK        (0xFFFFFFFFU)
28806 #define EARC_RX_CS_DATA_BITS_CS_DATA_SHIFT       (0U)
28807 /*! CS_DATA - Channel Status bits */
28808 #define EARC_RX_CS_DATA_BITS_CS_DATA(x)          (((uint32_t)(((uint32_t)(x)) << EARC_RX_CS_DATA_BITS_CS_DATA_SHIFT)) & EARC_RX_CS_DATA_BITS_CS_DATA_MASK)
28809 /*! @} */
28810 
28811 /* The count of EARC_RX_CS_DATA_BITS */
28812 #define EARC_RX_CS_DATA_BITS_COUNT               (6U)
28813 
28814 /*! @name RX_USER_DATA_BITS - User data bits */
28815 /*! @{ */
28816 
28817 #define EARC_RX_USER_DATA_BITS_U_DATA_MASK       (0xFFFFFFFFU)
28818 #define EARC_RX_USER_DATA_BITS_U_DATA_SHIFT      (0U)
28819 /*! U_DATA - User data bits */
28820 #define EARC_RX_USER_DATA_BITS_U_DATA(x)         (((uint32_t)(((uint32_t)(x)) << EARC_RX_USER_DATA_BITS_U_DATA_SHIFT)) & EARC_RX_USER_DATA_BITS_U_DATA_MASK)
28821 /*! @} */
28822 
28823 /* The count of EARC_RX_USER_DATA_BITS */
28824 #define EARC_RX_USER_DATA_BITS_COUNT             (6U)
28825 
28826 /*! @name RX_DPATH_CNTR_CTRL - DMAC counter control register */
28827 /*! @{ */
28828 
28829 #define EARC_RX_DPATH_CNTR_CTRL_TS_EN_MASK       (0x1U)
28830 #define EARC_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT      (0U)
28831 /*! TS_EN - Timestamp counter enable */
28832 #define EARC_RX_DPATH_CNTR_CTRL_TS_EN(x)         (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_TS_EN_MASK)
28833 
28834 #define EARC_RX_DPATH_CNTR_CTRL_TS_INC_MASK      (0x2U)
28835 #define EARC_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT     (1U)
28836 /*! TS_INC - Timestamp Increment */
28837 #define EARC_RX_DPATH_CNTR_CTRL_TS_INC(x)        (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_TS_INC_MASK)
28838 
28839 #define EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U)
28840 #define EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U)
28841 /*! RST_BIT_CNTR - Reset bit counter. */
28842 #define EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK)
28843 
28844 #define EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U)
28845 #define EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U)
28846 /*! RST_TS_CNTR - Reset timestamp counter. */
28847 #define EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR(x)   (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK)
28848 /*! @} */
28849 
28850 /*! @name RX_DPATH_TSCR - Receive Datapath Timestamp Counter Register */
28851 /*! @{ */
28852 
28853 #define EARC_RX_DPATH_TSCR_CVAL_MASK             (0xFFFFFFFFU)
28854 #define EARC_RX_DPATH_TSCR_CVAL_SHIFT            (0U)
28855 /*! CVAL - Timestamp counter value */
28856 #define EARC_RX_DPATH_TSCR_CVAL(x)               (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_TSCR_CVAL_SHIFT)) & EARC_RX_DPATH_TSCR_CVAL_MASK)
28857 /*! @} */
28858 
28859 /*! @name RX_DPATH_BCR - Receive Datapath Bit counter register */
28860 /*! @{ */
28861 
28862 #define EARC_RX_DPATH_BCR_CVAL_MASK              (0xFFFFFFFFU)
28863 #define EARC_RX_DPATH_BCR_CVAL_SHIFT             (0U)
28864 /*! CVAL - Bit count value */
28865 #define EARC_RX_DPATH_BCR_CVAL(x)                (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_BCR_CVAL_SHIFT)) & EARC_RX_DPATH_BCR_CVAL_MASK)
28866 /*! @} */
28867 
28868 /*! @name RX_DPATH_BCTR - Receive datapath Bit count timestamp register. */
28869 /*! @{ */
28870 
28871 #define EARC_RX_DPATH_BCTR_BCT_VAL_MASK          (0xFFFFFFFFU)
28872 #define EARC_RX_DPATH_BCTR_BCT_VAL_SHIFT         (0U)
28873 /*! BCT_VAL - Bit count timestamp value */
28874 #define EARC_RX_DPATH_BCTR_BCT_VAL(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_BCTR_BCT_VAL_SHIFT)) & EARC_RX_DPATH_BCTR_BCT_VAL_MASK)
28875 /*! @} */
28876 
28877 /*! @name RX_DPATH_BCRR - Receive datapath Bit read timestamp register. */
28878 /*! @{ */
28879 
28880 #define EARC_RX_DPATH_BCRR_BCT_VAL_MASK          (0xFFFFFFFFU)
28881 #define EARC_RX_DPATH_BCRR_BCT_VAL_SHIFT         (0U)
28882 /*! BCT_VAL - Bit count timestamp value */
28883 #define EARC_RX_DPATH_BCRR_BCT_VAL(x)            (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_BCRR_BCT_VAL_SHIFT)) & EARC_RX_DPATH_BCRR_BCT_VAL_MASK)
28884 /*! @} */
28885 
28886 /*! @name DMAC_PRE_MATCH_VAL - Preamble match value register */
28887 /*! @{ */
28888 
28889 #define EARC_DMAC_PRE_MATCH_VAL_PB_VAL_MASK      (0xFFFFU)
28890 #define EARC_DMAC_PRE_MATCH_VAL_PB_VAL_SHIFT     (0U)
28891 /*! PB_VAL - Preamble PB value */
28892 #define EARC_DMAC_PRE_MATCH_VAL_PB_VAL(x)        (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_PRE_MATCH_VAL_PB_VAL_SHIFT)) & EARC_DMAC_PRE_MATCH_VAL_PB_VAL_MASK)
28893 
28894 #define EARC_DMAC_PRE_MATCH_VAL_PA_VAL_MASK      (0xFFFF0000U)
28895 #define EARC_DMAC_PRE_MATCH_VAL_PA_VAL_SHIFT     (16U)
28896 /*! PA_VAL - Preamble PA value */
28897 #define EARC_DMAC_PRE_MATCH_VAL_PA_VAL(x)        (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_PRE_MATCH_VAL_PA_VAL_SHIFT)) & EARC_DMAC_PRE_MATCH_VAL_PA_VAL_MASK)
28898 /*! @} */
28899 
28900 /*! @name DMAC_DTS_PRE_MATCH_VAL - Preamble match value register */
28901 /*! @{ */
28902 
28903 #define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK (0xFFFFU)
28904 #define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT (0U)
28905 /*! DTS_PB_VAL - Preamble PB value */
28906 #define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT)) & EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK)
28907 
28908 #define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK (0xFFFF0000U)
28909 #define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT (16U)
28910 /*! DTS_PA_VAL - Preamble PA value */
28911 #define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT)) & EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK)
28912 /*! @} */
28913 
28914 /*! @name RX_DPATH_PRE_ERR - Error count for IEC60958-1 Block Synchronization. */
28915 /*! @{ */
28916 
28917 #define EARC_RX_DPATH_PRE_ERR_PRE_ERRS_MASK      (0xFFFFU)
28918 #define EARC_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT     (0U)
28919 /*! PRE_ERRS - Preamble Error counter */
28920 #define EARC_RX_DPATH_PRE_ERR_PRE_ERRS(x)        (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT)) & EARC_RX_DPATH_PRE_ERR_PRE_ERRS_MASK)
28921 
28922 #define EARC_RX_DPATH_PRE_ERR_CLEAR_MASK         (0x80000000U)
28923 #define EARC_RX_DPATH_PRE_ERR_CLEAR_SHIFT        (31U)
28924 /*! CLEAR - Clear bit for error counter. */
28925 #define EARC_RX_DPATH_PRE_ERR_CLEAR(x)           (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PRE_ERR_CLEAR_SHIFT)) & EARC_RX_DPATH_PRE_ERR_CLEAR_MASK)
28926 /*! @} */
28927 
28928 /*! @name RX_DPATH_PARITY_ERR - Parity Error count for IEC60958-1 Blocks. */
28929 /*! @{ */
28930 
28931 #define EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK   (0xFFFFU)
28932 #define EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT  (0U)
28933 /*! PRE_ERRS - Preamble Error counter */
28934 #define EARC_RX_DPATH_PARITY_ERR_PRE_ERRS(x)     (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT)) & EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK)
28935 
28936 #define EARC_RX_DPATH_PARITY_ERR_CLEAR_MASK      (0x80000000U)
28937 #define EARC_RX_DPATH_PARITY_ERR_CLEAR_SHIFT     (31U)
28938 /*! CLEAR - Clear bit for error counter. */
28939 #define EARC_RX_DPATH_PARITY_ERR_CLEAR(x)        (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PARITY_ERR_CLEAR_SHIFT)) & EARC_RX_DPATH_PARITY_ERR_CLEAR_MASK)
28940 /*! @} */
28941 
28942 /*! @name RX_DPATH_PKT_CNT - Receive Data packet count. */
28943 /*! @{ */
28944 
28945 #define EARC_RX_DPATH_PKT_CNT_VAL_MASK           (0x7FFFFFFFU)
28946 #define EARC_RX_DPATH_PKT_CNT_VAL_SHIFT          (0U)
28947 /*! VAL - Data packet counter */
28948 #define EARC_RX_DPATH_PKT_CNT_VAL(x)             (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PKT_CNT_VAL_SHIFT)) & EARC_RX_DPATH_PKT_CNT_VAL_MASK)
28949 /*! @} */
28950 
28951 /*! @name RX_DPATH_ONE_BIT_ERR_CNT - Receive Data packet Corrected error count. */
28952 /*! @{ */
28953 
28954 #define EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_MASK   (0xFFFFU)
28955 #define EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_SHIFT  (0U)
28956 #define EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL(x)     (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_SHIFT)) & EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_MASK)
28957 /*! @} */
28958 
28959 /*! @name DMAC_PRE_MATCH_OFFSET - Preamble match offset value register */
28960 /*! @{ */
28961 
28962 #define EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_MASK (0xFFFFFFFFU)
28963 #define EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT (0U)
28964 /*! PA_OFFSET - Sample count value for PA offset match */
28965 #define EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT)) & EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_MASK)
28966 /*! @} */
28967 
28968 /*! @name TX_DATAPATH_CTRL - Transmit Data path control register */
28969 /*! @{ */
28970 
28971 #define EARC_TX_DATAPATH_CTRL_CS_ACK_MASK        (0x1U)
28972 #define EARC_TX_DATAPATH_CTRL_CS_ACK_SHIFT       (0U)
28973 /*! CS_ACK - Channel Status ACK */
28974 #define EARC_TX_DATAPATH_CTRL_CS_ACK(x)          (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_CS_ACK_SHIFT)) & EARC_TX_DATAPATH_CTRL_CS_ACK_MASK)
28975 
28976 #define EARC_TX_DATAPATH_CTRL_UD_ACK_MASK        (0x2U)
28977 #define EARC_TX_DATAPATH_CTRL_UD_ACK_SHIFT       (1U)
28978 /*! UD_ACK - User Data ACK */
28979 #define EARC_TX_DATAPATH_CTRL_UD_ACK(x)          (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_UD_ACK_SHIFT)) & EARC_TX_DATAPATH_CTRL_UD_ACK_MASK)
28980 
28981 #define EARC_TX_DATAPATH_CTRL_CS_MOD_MASK        (0x4U)
28982 #define EARC_TX_DATAPATH_CTRL_CS_MOD_SHIFT       (2U)
28983 /*! CS_MOD - Enable Channel Status insertion */
28984 #define EARC_TX_DATAPATH_CTRL_CS_MOD(x)          (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_CS_MOD_SHIFT)) & EARC_TX_DATAPATH_CTRL_CS_MOD_MASK)
28985 
28986 #define EARC_TX_DATAPATH_CTRL_UD_MOD_MASK        (0x8U)
28987 #define EARC_TX_DATAPATH_CTRL_UD_MOD_SHIFT       (3U)
28988 /*! UD_MOD - Enable User Data insertion */
28989 #define EARC_TX_DATAPATH_CTRL_UD_MOD(x)          (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_UD_MOD_SHIFT)) & EARC_TX_DATAPATH_CTRL_UD_MOD_MASK)
28990 
28991 #define EARC_TX_DATAPATH_CTRL_VLD_MOD_MASK       (0x10U)
28992 #define EARC_TX_DATAPATH_CTRL_VLD_MOD_SHIFT      (4U)
28993 /*! VLD_MOD - Enable Valid bit insertion */
28994 #define EARC_TX_DATAPATH_CTRL_VLD_MOD(x)         (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_VLD_MOD_SHIFT)) & EARC_TX_DATAPATH_CTRL_VLD_MOD_MASK)
28995 
28996 #define EARC_TX_DATAPATH_CTRL_FRM_VLD_MASK       (0x20U)
28997 #define EARC_TX_DATAPATH_CTRL_FRM_VLD_SHIFT      (5U)
28998 /*! FRM_VLD - Valid bit value */
28999 #define EARC_TX_DATAPATH_CTRL_FRM_VLD(x)         (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_FRM_VLD_SHIFT)) & EARC_TX_DATAPATH_CTRL_FRM_VLD_MASK)
29000 
29001 #define EARC_TX_DATAPATH_CTRL_EN_PARITY_MASK     (0x40U)
29002 #define EARC_TX_DATAPATH_CTRL_EN_PARITY_SHIFT    (6U)
29003 /*! EN_PARITY - Enable parity insertion */
29004 #define EARC_TX_DATAPATH_CTRL_EN_PARITY(x)       (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_EN_PARITY_SHIFT)) & EARC_TX_DATAPATH_CTRL_EN_PARITY_MASK)
29005 
29006 #define EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK   (0x80U)
29007 #define EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT  (7U)
29008 /*! EN_PREAMBLE - Enable preamble insertion */
29009 #define EARC_TX_DATAPATH_CTRL_EN_PREAMBLE(x)     (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT)) & EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK)
29010 
29011 #define EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_MASK   (0x400U)
29012 #define EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_SHIFT  (10U)
29013 /*! TX_CLK_RATE - This bit controls the TX clock rate. */
29014 #define EARC_TX_DATAPATH_CTRL_TX_CLK_RATE(x)     (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_SHIFT)) & EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_MASK)
29015 
29016 #define EARC_TX_DATAPATH_CTRL_FRM_FMT_MASK       (0x800U)
29017 #define EARC_TX_DATAPATH_CTRL_FRM_FMT_SHIFT      (11U)
29018 /*! FRM_FMT - Frame format of input data */
29019 #define EARC_TX_DATAPATH_CTRL_FRM_FMT(x)         (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_FRM_FMT_SHIFT)) & EARC_TX_DATAPATH_CTRL_FRM_FMT_MASK)
29020 
29021 #define EARC_TX_DATAPATH_CTRL_TX_FORMAT_MASK     (0x3000U)
29022 #define EARC_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT    (12U)
29023 /*! TX_FORMAT - Transmit data format */
29024 #define EARC_TX_DATAPATH_CTRL_TX_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT)) & EARC_TX_DATAPATH_CTRL_TX_FORMAT_MASK)
29025 
29026 #define EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK  (0x4000U)
29027 #define EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT (14U)
29028 /*! STRT_DATA_TX - Once Comma pattern is successively received, and heartbeat is detected, start TX of DMAC data. */
29029 #define EARC_TX_DATAPATH_CTRL_STRT_DATA_TX(x)    (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT)) & EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK)
29030 /*! @} */
29031 
29032 /*! @name TX_CS_DATA_BITS - Channel staus bits */
29033 /*! @{ */
29034 
29035 #define EARC_TX_CS_DATA_BITS_CS_DATA_MASK        (0xFFFFFFFFU)
29036 #define EARC_TX_CS_DATA_BITS_CS_DATA_SHIFT       (0U)
29037 /*! CS_DATA - Channel Status bits / block */
29038 #define EARC_TX_CS_DATA_BITS_CS_DATA(x)          (((uint32_t)(((uint32_t)(x)) << EARC_TX_CS_DATA_BITS_CS_DATA_SHIFT)) & EARC_TX_CS_DATA_BITS_CS_DATA_MASK)
29039 /*! @} */
29040 
29041 /* The count of EARC_TX_CS_DATA_BITS */
29042 #define EARC_TX_CS_DATA_BITS_COUNT               (6U)
29043 
29044 /*! @name TX_USER_DATA_BITS - User data bits */
29045 /*! @{ */
29046 
29047 #define EARC_TX_USER_DATA_BITS_U_DATA_MASK       (0xFFFFFFFFU)
29048 #define EARC_TX_USER_DATA_BITS_U_DATA_SHIFT      (0U)
29049 /*! U_DATA - User data bits/block */
29050 #define EARC_TX_USER_DATA_BITS_U_DATA(x)         (((uint32_t)(((uint32_t)(x)) << EARC_TX_USER_DATA_BITS_U_DATA_SHIFT)) & EARC_TX_USER_DATA_BITS_U_DATA_MASK)
29051 /*! @} */
29052 
29053 /* The count of EARC_TX_USER_DATA_BITS */
29054 #define EARC_TX_USER_DATA_BITS_COUNT             (6U)
29055 
29056 /*! @name TX_DPATH_CNTR_CTRL - DMAC counter control register */
29057 /*! @{ */
29058 
29059 #define EARC_TX_DPATH_CNTR_CTRL_TS_EN_MASK       (0x1U)
29060 #define EARC_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT      (0U)
29061 /*! TS_EN - Timestamp counter enable */
29062 #define EARC_TX_DPATH_CNTR_CTRL_TS_EN(x)         (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_TS_EN_MASK)
29063 
29064 #define EARC_TX_DPATH_CNTR_CTRL_TS_INC_MASK      (0x2U)
29065 #define EARC_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT     (1U)
29066 /*! TS_INC - Timestamp Increment */
29067 #define EARC_TX_DPATH_CNTR_CTRL_TS_INC(x)        (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_TS_INC_MASK)
29068 
29069 #define EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U)
29070 #define EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U)
29071 /*! RST_BIT_CNTR - Reset bit counter. */
29072 #define EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK)
29073 
29074 #define EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U)
29075 #define EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U)
29076 /*! RST_TS_CNTR - Reset timestamp counter. */
29077 #define EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR(x)   (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK)
29078 /*! @} */
29079 
29080 /*! @name TX_DPATH_TSCR - Transmit Datapath Timestamp Counter Register */
29081 /*! @{ */
29082 
29083 #define EARC_TX_DPATH_TSCR_CVAL_MASK             (0xFFFFFFFFU)
29084 #define EARC_TX_DPATH_TSCR_CVAL_SHIFT            (0U)
29085 /*! CVAL - Timestamp counter value */
29086 #define EARC_TX_DPATH_TSCR_CVAL(x)               (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_TSCR_CVAL_SHIFT)) & EARC_TX_DPATH_TSCR_CVAL_MASK)
29087 /*! @} */
29088 
29089 /*! @name TX_DPATH_BCR - Transmit Datapath Bit counter register */
29090 /*! @{ */
29091 
29092 #define EARC_TX_DPATH_BCR_CVAL_MASK              (0xFFFFFFFFU)
29093 #define EARC_TX_DPATH_BCR_CVAL_SHIFT             (0U)
29094 /*! CVAL - Bit count value */
29095 #define EARC_TX_DPATH_BCR_CVAL(x)                (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_BCR_CVAL_SHIFT)) & EARC_TX_DPATH_BCR_CVAL_MASK)
29096 /*! @} */
29097 
29098 /*! @name TX_DPATH_BCTR - Transmit datapath Bit count timestamp register. */
29099 /*! @{ */
29100 
29101 #define EARC_TX_DPATH_BCTR_BCT_VAL_MASK          (0xFFFFFFFFU)
29102 #define EARC_TX_DPATH_BCTR_BCT_VAL_SHIFT         (0U)
29103 /*! BCT_VAL - Bit count timestamp value */
29104 #define EARC_TX_DPATH_BCTR_BCT_VAL(x)            (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_BCTR_BCT_VAL_SHIFT)) & EARC_TX_DPATH_BCTR_BCT_VAL_MASK)
29105 /*! @} */
29106 
29107 /*! @name TX_DPATH_BCRR - Transmmit datapath Bit read timestamp register. */
29108 /*! @{ */
29109 
29110 #define EARC_TX_DPATH_BCRR_BCT_VAL_MASK          (0xFFFFFFFFU)
29111 #define EARC_TX_DPATH_BCRR_BCT_VAL_SHIFT         (0U)
29112 /*! BCT_VAL - Bit count timestamp value */
29113 #define EARC_TX_DPATH_BCRR_BCT_VAL(x)            (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_BCRR_BCT_VAL_SHIFT)) & EARC_TX_DPATH_BCRR_BCT_VAL_MASK)
29114 /*! @} */
29115 
29116 /*! @name HPD_DBNC_CTRL - HPD Debounce Control Register */
29117 /*! @{ */
29118 
29119 #define EARC_HPD_DBNC_CTRL_VAL_MASK              (0xFFFFFFFFU)
29120 #define EARC_HPD_DBNC_CTRL_VAL_SHIFT             (0U)
29121 /*! VAL - HDP pin debounce interval */
29122 #define EARC_HPD_DBNC_CTRL_VAL(x)                (((uint32_t)(((uint32_t)(x)) << EARC_HPD_DBNC_CTRL_VAL_SHIFT)) & EARC_HPD_DBNC_CTRL_VAL_MASK)
29123 /*! @} */
29124 
29125 /*! @name TEMPERATURE - Chip Temperature for eARC PHY */
29126 /*! @{ */
29127 
29128 #define EARC_TEMPERATURE_VAL_MASK                (0xFFFFFFFFU)
29129 #define EARC_TEMPERATURE_VAL_SHIFT               (0U)
29130 /*! VAL - Temperature */
29131 #define EARC_TEMPERATURE_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << EARC_TEMPERATURE_VAL_SHIFT)) & EARC_TEMPERATURE_VAL_MASK)
29132 /*! @} */
29133 
29134 
29135 /*!
29136  * @}
29137  */ /* end of group EARC_Register_Masks */
29138 
29139 
29140 /* EARC - Peripheral instance base addresses */
29141 /** Peripheral AUDIO_XCVR base address */
29142 #define AUDIO_XCVR_BASE                          (0x30CC0000u)
29143 /** Peripheral AUDIO_XCVR base pointer */
29144 #define AUDIO_XCVR                               ((EARC_Type *)AUDIO_XCVR_BASE)
29145 /** Array initializer of EARC peripheral base addresses */
29146 #define EARC_BASE_ADDRS                          { AUDIO_XCVR_BASE }
29147 /** Array initializer of EARC peripheral base pointers */
29148 #define EARC_BASE_PTRS                           { AUDIO_XCVR }
29149 
29150 /*!
29151  * @}
29152  */ /* end of group EARC_Peripheral_Access_Layer */
29153 
29154 
29155 /* ----------------------------------------------------------------------------
29156    -- ECSPI Peripheral Access Layer
29157    ---------------------------------------------------------------------------- */
29158 
29159 /*!
29160  * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
29161  * @{
29162  */
29163 
29164 /** ECSPI - Register Layout Typedef */
29165 typedef struct {
29166   __I  uint32_t RXDATA;                            /**< Receive Data Register, offset: 0x0 */
29167   __O  uint32_t TXDATA;                            /**< Transmit Data Register, offset: 0x4 */
29168   __IO uint32_t CONREG;                            /**< Control Register, offset: 0x8 */
29169   __IO uint32_t CONFIGREG;                         /**< Config Register, offset: 0xC */
29170   __IO uint32_t INTREG;                            /**< Interrupt Control Register, offset: 0x10 */
29171   __IO uint32_t DMAREG;                            /**< DMA Control Register, offset: 0x14 */
29172   __IO uint32_t STATREG;                           /**< Status Register, offset: 0x18 */
29173   __IO uint32_t PERIODREG;                         /**< Sample Period Control Register, offset: 0x1C */
29174   __IO uint32_t TESTREG;                           /**< Test Control Register, offset: 0x20 */
29175        uint8_t RESERVED_0[28];
29176   __O  uint32_t MSGDATA;                           /**< Message Data Register, offset: 0x40 */
29177 } ECSPI_Type;
29178 
29179 /* ----------------------------------------------------------------------------
29180    -- ECSPI Register Masks
29181    ---------------------------------------------------------------------------- */
29182 
29183 /*!
29184  * @addtogroup ECSPI_Register_Masks ECSPI Register Masks
29185  * @{
29186  */
29187 
29188 /*! @name RXDATA - Receive Data Register */
29189 /*! @{ */
29190 
29191 #define ECSPI_RXDATA_ECSPI_RXDATA_MASK           (0xFFFFFFFFU)
29192 #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT          (0U)
29193 #define ECSPI_RXDATA_ECSPI_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK)
29194 /*! @} */
29195 
29196 /*! @name TXDATA - Transmit Data Register */
29197 /*! @{ */
29198 
29199 #define ECSPI_TXDATA_ECSPI_TXDATA_MASK           (0xFFFFFFFFU)
29200 #define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT          (0U)
29201 #define ECSPI_TXDATA_ECSPI_TXDATA(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK)
29202 /*! @} */
29203 
29204 /*! @name CONREG - Control Register */
29205 /*! @{ */
29206 
29207 #define ECSPI_CONREG_EN_MASK                     (0x1U)
29208 #define ECSPI_CONREG_EN_SHIFT                    (0U)
29209 /*! EN
29210  *  0b0..Disable the block.
29211  *  0b1..Enable the block.
29212  */
29213 #define ECSPI_CONREG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK)
29214 
29215 #define ECSPI_CONREG_HT_MASK                     (0x2U)
29216 #define ECSPI_CONREG_HT_SHIFT                    (1U)
29217 /*! HT
29218  *  0b0..Disable HT mode.
29219  *  0b1..Enable HT mode.
29220  */
29221 #define ECSPI_CONREG_HT(x)                       (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK)
29222 
29223 #define ECSPI_CONREG_XCH_MASK                    (0x4U)
29224 #define ECSPI_CONREG_XCH_SHIFT                   (2U)
29225 /*! XCH
29226  *  0b0..Idle.
29227  *  0b1..Initiates exchange (write) or busy (read).
29228  */
29229 #define ECSPI_CONREG_XCH(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK)
29230 
29231 #define ECSPI_CONREG_SMC_MASK                    (0x8U)
29232 #define ECSPI_CONREG_SMC_SHIFT                   (3U)
29233 /*! SMC
29234  *  0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or
29235  *       multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL
29236  *       descriptions.
29237  *  0b1..Immediately starts a SPI burst when data is written in TXFIFO.
29238  */
29239 #define ECSPI_CONREG_SMC(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK)
29240 
29241 #define ECSPI_CONREG_CHANNEL_MODE_MASK           (0xF0U)
29242 #define ECSPI_CONREG_CHANNEL_MODE_SHIFT          (4U)
29243 /*! CHANNEL_MODE
29244  *  0b0000..Slave mode.
29245  *  0b0001..Master mode.
29246  */
29247 #define ECSPI_CONREG_CHANNEL_MODE(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK)
29248 
29249 #define ECSPI_CONREG_POST_DIVIDER_MASK           (0xF00U)
29250 #define ECSPI_CONREG_POST_DIVIDER_SHIFT          (8U)
29251 /*! POST_DIVIDER
29252  *  0b0000..Divide by 1.
29253  *  0b0001..Divide by 2.
29254  *  0b0010..Divide by 4.
29255  *  0b1110..Divide by 2 14 .
29256  *  0b1111..Divide by 2 15 .
29257  */
29258 #define ECSPI_CONREG_POST_DIVIDER(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK)
29259 
29260 #define ECSPI_CONREG_PRE_DIVIDER_MASK            (0xF000U)
29261 #define ECSPI_CONREG_PRE_DIVIDER_SHIFT           (12U)
29262 /*! PRE_DIVIDER
29263  *  0b0000..Divide by 1.
29264  *  0b0001..Divide by 2.
29265  *  0b0010..Divide by 3.
29266  *  0b1101..Divide by 14.
29267  *  0b1110..Divide by 15.
29268  *  0b1111..Divide by 16.
29269  */
29270 #define ECSPI_CONREG_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK)
29271 
29272 #define ECSPI_CONREG_DRCTL_MASK                  (0x30000U)
29273 #define ECSPI_CONREG_DRCTL_SHIFT                 (16U)
29274 /*! DRCTL
29275  *  0b00..The SPI_RDY signal is a don't care.
29276  *  0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
29277  *  0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
29278  *  0b11..Reserved.
29279  */
29280 #define ECSPI_CONREG_DRCTL(x)                    (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK)
29281 
29282 #define ECSPI_CONREG_CHANNEL_SELECT_MASK         (0xC0000U)
29283 #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT        (18U)
29284 /*! CHANNEL_SELECT
29285  *  0b00..Channel 0 is selected. Chip Select (SS) will be asserted.
29286  *  0b01..Reserved.
29287  *  0b10..Reserved.
29288  *  0b11..Reserved.
29289  */
29290 #define ECSPI_CONREG_CHANNEL_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK)
29291 
29292 #define ECSPI_CONREG_BURST_LENGTH_MASK           (0xFFF00000U)
29293 #define ECSPI_CONREG_BURST_LENGTH_SHIFT          (20U)
29294 /*! BURST_LENGTH
29295  *  0b000000000000..A SPI burst contains the 1 LSB in a word.
29296  *  0b000000000001..A SPI burst contains the 2 LSB in a word.
29297  *  0b000000000010..A SPI burst contains the 3 LSB in a word.
29298  *  0b000000011111..A SPI burst contains all 32 bits in a word.
29299  *  0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
29300  *  0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
29301  *  0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
29302  *  0b111111111111..A SPI burst contains 2^7 words.
29303  */
29304 #define ECSPI_CONREG_BURST_LENGTH(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK)
29305 /*! @} */
29306 
29307 /*! @name CONFIGREG - Config Register */
29308 /*! @{ */
29309 
29310 #define ECSPI_CONFIGREG_SCLK_PHA_MASK            (0xFU)
29311 #define ECSPI_CONFIGREG_SCLK_PHA_SHIFT           (0U)
29312 /*! SCLK_PHA
29313  *  0b0000..Phase 0 operation.
29314  *  0b0001..Phase 1 operation.
29315  */
29316 #define ECSPI_CONFIGREG_SCLK_PHA(x)              (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK)
29317 
29318 #define ECSPI_CONFIGREG_SCLK_POL_MASK            (0xF0U)
29319 #define ECSPI_CONFIGREG_SCLK_POL_SHIFT           (4U)
29320 /*! SCLK_POL
29321  *  0b0000..Active high polarity (0 = Idle).
29322  *  0b0001..Active low polarity (1 = Idle).
29323  */
29324 #define ECSPI_CONFIGREG_SCLK_POL(x)              (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK)
29325 
29326 #define ECSPI_CONFIGREG_SS_CTL_MASK              (0xF00U)
29327 #define ECSPI_CONFIGREG_SS_CTL_SHIFT             (8U)
29328 /*! SS_CTL
29329  *  0b0000..In master mode - only one SPI burst will be transmitted.
29330  *  0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be
29331  *          transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
29332  *  0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is
29333  *          equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first
29334  *          received word are valid. All bits subsequent to the first received word in RXFIFO are valid.
29335  *  0b0001..Reserved
29336  */
29337 #define ECSPI_CONFIGREG_SS_CTL(x)                (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK)
29338 
29339 #define ECSPI_CONFIGREG_SS_POL_MASK              (0xF000U)
29340 #define ECSPI_CONFIGREG_SS_POL_SHIFT             (12U)
29341 /*! SS_POL
29342  *  0b0000..Active low.
29343  *  0b0001..Active high.
29344  */
29345 #define ECSPI_CONFIGREG_SS_POL(x)                (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK)
29346 
29347 #define ECSPI_CONFIGREG_DATA_CTL_MASK            (0xF0000U)
29348 #define ECSPI_CONFIGREG_DATA_CTL_SHIFT           (16U)
29349 /*! DATA_CTL
29350  *  0b0000..Stay high.
29351  *  0b0001..Stay low.
29352  */
29353 #define ECSPI_CONFIGREG_DATA_CTL(x)              (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK)
29354 
29355 #define ECSPI_CONFIGREG_SCLK_CTL_MASK            (0xF00000U)
29356 #define ECSPI_CONFIGREG_SCLK_CTL_SHIFT           (20U)
29357 /*! SCLK_CTL
29358  *  0b0000..Stay low.
29359  *  0b0001..Stay high.
29360  */
29361 #define ECSPI_CONFIGREG_SCLK_CTL(x)              (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK)
29362 
29363 #define ECSPI_CONFIGREG_HT_LENGTH_MASK           (0x1F000000U)
29364 #define ECSPI_CONFIGREG_HT_LENGTH_SHIFT          (24U)
29365 #define ECSPI_CONFIGREG_HT_LENGTH(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK)
29366 /*! @} */
29367 
29368 /*! @name INTREG - Interrupt Control Register */
29369 /*! @{ */
29370 
29371 #define ECSPI_INTREG_TEEN_MASK                   (0x1U)
29372 #define ECSPI_INTREG_TEEN_SHIFT                  (0U)
29373 /*! TEEN
29374  *  0b0..Disable
29375  *  0b1..Enable
29376  */
29377 #define ECSPI_INTREG_TEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK)
29378 
29379 #define ECSPI_INTREG_TDREN_MASK                  (0x2U)
29380 #define ECSPI_INTREG_TDREN_SHIFT                 (1U)
29381 /*! TDREN
29382  *  0b0..Disable
29383  *  0b1..Enable
29384  */
29385 #define ECSPI_INTREG_TDREN(x)                    (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK)
29386 
29387 #define ECSPI_INTREG_TFEN_MASK                   (0x4U)
29388 #define ECSPI_INTREG_TFEN_SHIFT                  (2U)
29389 /*! TFEN
29390  *  0b0..Disable
29391  *  0b1..Enable
29392  */
29393 #define ECSPI_INTREG_TFEN(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK)
29394 
29395 #define ECSPI_INTREG_RREN_MASK                   (0x8U)
29396 #define ECSPI_INTREG_RREN_SHIFT                  (3U)
29397 /*! RREN
29398  *  0b0..Disable
29399  *  0b1..Enable
29400  */
29401 #define ECSPI_INTREG_RREN(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK)
29402 
29403 #define ECSPI_INTREG_RDREN_MASK                  (0x10U)
29404 #define ECSPI_INTREG_RDREN_SHIFT                 (4U)
29405 /*! RDREN
29406  *  0b0..Disable
29407  *  0b1..Enable
29408  */
29409 #define ECSPI_INTREG_RDREN(x)                    (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK)
29410 
29411 #define ECSPI_INTREG_RFEN_MASK                   (0x20U)
29412 #define ECSPI_INTREG_RFEN_SHIFT                  (5U)
29413 /*! RFEN
29414  *  0b0..Disable
29415  *  0b1..Enable
29416  */
29417 #define ECSPI_INTREG_RFEN(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK)
29418 
29419 #define ECSPI_INTREG_ROEN_MASK                   (0x40U)
29420 #define ECSPI_INTREG_ROEN_SHIFT                  (6U)
29421 /*! ROEN
29422  *  0b0..Disable
29423  *  0b1..Enable
29424  */
29425 #define ECSPI_INTREG_ROEN(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK)
29426 
29427 #define ECSPI_INTREG_TCEN_MASK                   (0x80U)
29428 #define ECSPI_INTREG_TCEN_SHIFT                  (7U)
29429 /*! TCEN
29430  *  0b0..Disable
29431  *  0b1..Enable
29432  */
29433 #define ECSPI_INTREG_TCEN(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK)
29434 /*! @} */
29435 
29436 /*! @name DMAREG - DMA Control Register */
29437 /*! @{ */
29438 
29439 #define ECSPI_DMAREG_TX_THRESHOLD_MASK           (0x3FU)
29440 #define ECSPI_DMAREG_TX_THRESHOLD_SHIFT          (0U)
29441 #define ECSPI_DMAREG_TX_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK)
29442 
29443 #define ECSPI_DMAREG_TEDEN_MASK                  (0x80U)
29444 #define ECSPI_DMAREG_TEDEN_SHIFT                 (7U)
29445 /*! TEDEN
29446  *  0b0..Disable
29447  *  0b1..Enable
29448  */
29449 #define ECSPI_DMAREG_TEDEN(x)                    (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK)
29450 
29451 #define ECSPI_DMAREG_RX_THRESHOLD_MASK           (0x3F0000U)
29452 #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT          (16U)
29453 #define ECSPI_DMAREG_RX_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK)
29454 
29455 #define ECSPI_DMAREG_RXDEN_MASK                  (0x800000U)
29456 #define ECSPI_DMAREG_RXDEN_SHIFT                 (23U)
29457 /*! RXDEN
29458  *  0b0..Disable
29459  *  0b1..Enable
29460  */
29461 #define ECSPI_DMAREG_RXDEN(x)                    (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK)
29462 
29463 #define ECSPI_DMAREG_RX_DMA_LENGTH_MASK          (0x3F000000U)
29464 #define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT         (24U)
29465 #define ECSPI_DMAREG_RX_DMA_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
29466 
29467 #define ECSPI_DMAREG_RXTDEN_MASK                 (0x80000000U)
29468 #define ECSPI_DMAREG_RXTDEN_SHIFT                (31U)
29469 /*! RXTDEN
29470  *  0b0..Disable
29471  *  0b1..Enable
29472  */
29473 #define ECSPI_DMAREG_RXTDEN(x)                   (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK)
29474 /*! @} */
29475 
29476 /*! @name STATREG - Status Register */
29477 /*! @{ */
29478 
29479 #define ECSPI_STATREG_TE_MASK                    (0x1U)
29480 #define ECSPI_STATREG_TE_SHIFT                   (0U)
29481 /*! TE
29482  *  0b0..TXFIFO contains one or more words.
29483  *  0b1..TXFIFO is empty.
29484  */
29485 #define ECSPI_STATREG_TE(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK)
29486 
29487 #define ECSPI_STATREG_TDR_MASK                   (0x2U)
29488 #define ECSPI_STATREG_TDR_SHIFT                  (1U)
29489 /*! TDR
29490  *  0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
29491  *  0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
29492  */
29493 #define ECSPI_STATREG_TDR(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK)
29494 
29495 #define ECSPI_STATREG_TF_MASK                    (0x4U)
29496 #define ECSPI_STATREG_TF_SHIFT                   (2U)
29497 /*! TF
29498  *  0b0..TXFIFO is not Full.
29499  *  0b1..TXFIFO is Full.
29500  */
29501 #define ECSPI_STATREG_TF(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK)
29502 
29503 #define ECSPI_STATREG_RR_MASK                    (0x8U)
29504 #define ECSPI_STATREG_RR_SHIFT                   (3U)
29505 /*! RR
29506  *  0b0..No valid data in RXFIFO.
29507  *  0b1..More than 1 word in RXFIFO.
29508  */
29509 #define ECSPI_STATREG_RR(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK)
29510 
29511 #define ECSPI_STATREG_RDR_MASK                   (0x10U)
29512 #define ECSPI_STATREG_RDR_SHIFT                  (4U)
29513 /*! RDR
29514  *  0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
29515  *  0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists.
29516  *  0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
29517  *  0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD.
29518  */
29519 #define ECSPI_STATREG_RDR(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK)
29520 
29521 #define ECSPI_STATREG_RF_MASK                    (0x20U)
29522 #define ECSPI_STATREG_RF_SHIFT                   (5U)
29523 /*! RF
29524  *  0b0..Not Full.
29525  *  0b1..Full.
29526  */
29527 #define ECSPI_STATREG_RF(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK)
29528 
29529 #define ECSPI_STATREG_RO_MASK                    (0x40U)
29530 #define ECSPI_STATREG_RO_SHIFT                   (6U)
29531 /*! RO
29532  *  0b0..RXFIFO has no overflow.
29533  *  0b1..RXFIFO has overflowed.
29534  */
29535 #define ECSPI_STATREG_RO(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK)
29536 
29537 #define ECSPI_STATREG_TC_MASK                    (0x80U)
29538 #define ECSPI_STATREG_TC_SHIFT                   (7U)
29539 /*! TC
29540  *  0b0..Transfer in progress.
29541  *  0b1..Transfer completed.
29542  */
29543 #define ECSPI_STATREG_TC(x)                      (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK)
29544 /*! @} */
29545 
29546 /*! @name PERIODREG - Sample Period Control Register */
29547 /*! @{ */
29548 
29549 #define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK       (0x7FFFU)
29550 #define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT      (0U)
29551 /*! SAMPLE_PERIOD
29552  *  0b000000000000000..0 wait states inserted
29553  *  0b000000000000001..1 wait state inserted
29554  *  0b111111111111110..32766 wait states inserted
29555  *  0b111111111111111..32767 wait states inserted
29556  */
29557 #define ECSPI_PERIODREG_SAMPLE_PERIOD(x)         (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
29558 
29559 #define ECSPI_PERIODREG_CSRC_MASK                (0x8000U)
29560 #define ECSPI_PERIODREG_CSRC_SHIFT               (15U)
29561 /*! CSRC
29562  *  0b0..SPI Clock (SCLK)
29563  *  0b1..Low-Frequency Reference Clock (32.768 KHz)
29564  */
29565 #define ECSPI_PERIODREG_CSRC(x)                  (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK)
29566 
29567 #define ECSPI_PERIODREG_CSD_CTL_MASK             (0x3F0000U)
29568 #define ECSPI_PERIODREG_CSD_CTL_SHIFT            (16U)
29569 #define ECSPI_PERIODREG_CSD_CTL(x)               (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK)
29570 /*! @} */
29571 
29572 /*! @name TESTREG - Test Control Register */
29573 /*! @{ */
29574 
29575 #define ECSPI_TESTREG_TXCNT_MASK                 (0x7FU)
29576 #define ECSPI_TESTREG_TXCNT_SHIFT                (0U)
29577 #define ECSPI_TESTREG_TXCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK)
29578 
29579 #define ECSPI_TESTREG_RXCNT_MASK                 (0x7F00U)
29580 #define ECSPI_TESTREG_RXCNT_SHIFT                (8U)
29581 #define ECSPI_TESTREG_RXCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK)
29582 
29583 #define ECSPI_TESTREG_LBC_MASK                   (0x80000000U)
29584 #define ECSPI_TESTREG_LBC_SHIFT                  (31U)
29585 /*! LBC
29586  *  0b0..Not connected.
29587  *  0b1..Transmitter and receiver sections internally connected for Loopback.
29588  */
29589 #define ECSPI_TESTREG_LBC(x)                     (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK)
29590 /*! @} */
29591 
29592 /*! @name MSGDATA - Message Data Register */
29593 /*! @{ */
29594 
29595 #define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK         (0xFFFFFFFFU)
29596 #define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT        (0U)
29597 #define ECSPI_MSGDATA_ECSPI_MSGDATA(x)           (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
29598 /*! @} */
29599 
29600 
29601 /*!
29602  * @}
29603  */ /* end of group ECSPI_Register_Masks */
29604 
29605 
29606 /* ECSPI - Peripheral instance base addresses */
29607 /** Peripheral ECSPI1 base address */
29608 #define ECSPI1_BASE                              (0x30820000u)
29609 /** Peripheral ECSPI1 base pointer */
29610 #define ECSPI1                                   ((ECSPI_Type *)ECSPI1_BASE)
29611 /** Peripheral ECSPI2 base address */
29612 #define ECSPI2_BASE                              (0x30830000u)
29613 /** Peripheral ECSPI2 base pointer */
29614 #define ECSPI2                                   ((ECSPI_Type *)ECSPI2_BASE)
29615 /** Peripheral ECSPI3 base address */
29616 #define ECSPI3_BASE                              (0x30840000u)
29617 /** Peripheral ECSPI3 base pointer */
29618 #define ECSPI3                                   ((ECSPI_Type *)ECSPI3_BASE)
29619 /** Array initializer of ECSPI peripheral base addresses */
29620 #define ECSPI_BASE_ADDRS                         { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE }
29621 /** Array initializer of ECSPI peripheral base pointers */
29622 #define ECSPI_BASE_PTRS                          { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 }
29623 /** Interrupt vectors for the ECSPI peripheral type */
29624 #define ECSPI_IRQS                               { NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn }
29625 
29626 /*!
29627  * @}
29628  */ /* end of group ECSPI_Peripheral_Access_Layer */
29629 
29630 
29631 /* ----------------------------------------------------------------------------
29632    -- EDDC Peripheral Access Layer
29633    ---------------------------------------------------------------------------- */
29634 
29635 /*!
29636  * @addtogroup EDDC_Peripheral_Access_Layer EDDC Peripheral Access Layer
29637  * @{
29638  */
29639 
29640 /** EDDC - Register Layout Typedef */
29641 typedef struct {
29642   __IO uint8_t I2CM_SLAVE;                         /**< I2C DDC Slave address Configuration Register, offset: 0x0 */
29643   __IO uint8_t I2CM_ADDRESS;                       /**< I2C DDC Address Configuration Register, offset: 0x1 */
29644   __IO uint8_t I2CM_DATAO;                         /**< I2C DDC Data Write Register, offset: 0x2 */
29645   __I  uint8_t I2CM_DATAI;                         /**< I2C DDC Data read Register, offset: 0x3 */
29646   __O  uint8_t I2CM_OPERATION;                     /**< I2C DDC RD/RD_EXT/WR Operation Register Read and write operation request., offset: 0x4 */
29647   __IO uint8_t I2CM_INT;                           /**< I2C DDC Done Interrupt Register This register configures the I2C master interrupts., offset: 0x5 */
29648   __IO uint8_t I2CM_CTLINT;                        /**< I2C DDC error Interrupt Register This register configures the I2C master arbitration lost and not acknowledge error interrupts., offset: 0x6 */
29649   __IO uint8_t I2CM_DIV;                           /**< I2C DDC Speed Control Register This register configures the division relation between master and scl clock., offset: 0x7 */
29650   __IO uint8_t I2CM_SEGADDR;                       /**< I2C DDC Segment Address Configuration Register This register configures the segment address for extended R/W destination and is used for EDID reading operations, particularly for the Extended Data Read Operation for Enhanced DDC., offset: 0x8 */
29651   __IO uint8_t I2CM_SOFTRSTZ;                      /**< I2C DDC Software Reset Control Register This register resets the I2C master., offset: 0x9 */
29652   __IO uint8_t I2CM_SEGPTR;                        /**< I2C DDC Segment Pointer Register This register configures the segment pointer for extended RD/WR request., offset: 0xA */
29653   __IO uint8_t I2CM_SS_SCL_HCNT_1_ADDR;            /**< I2C DDC Slow Speed SCL High Level Control Register 1, offset: 0xB */
29654   __IO uint8_t I2CM_SS_SCL_HCNT_0_ADDR;            /**< I2C DDC Slow Speed SCL High Level Control Register 0, offset: 0xC */
29655   __IO uint8_t I2CM_SS_SCL_LCNT_1_ADDR;            /**< I2C DDC Slow Speed SCL Low Level Control Register 1, offset: 0xD */
29656   __IO uint8_t I2CM_SS_SCL_LCNT_0_ADDR;            /**< I2C DDC Slow Speed SCL Low Level Control Register 0, offset: 0xE */
29657   __IO uint8_t I2CM_FS_SCL_HCNT_1_ADDR;            /**< I2C DDC Fast Speed SCL High Level Control Register 1, offset: 0xF */
29658   __IO uint8_t I2CM_FS_SCL_HCNT_0_ADDR;            /**< I2C DDC Fast Speed SCL High Level Control Register 0, offset: 0x10 */
29659   __IO uint8_t I2CM_FS_SCL_LCNT_1_ADDR;            /**< I2C DDC Fast Speed SCL Low Level Control Register 1, offset: 0x11 */
29660   __IO uint8_t I2CM_FS_SCL_LCNT_0_ADDR;            /**< I2C DDC Fast Speed SCL Low Level Control Register 0, offset: 0x12 */
29661   __IO uint8_t I2CM_SDA_HOLD;                      /**< I2C DDC SDA Hold Register, offset: 0x13 */
29662   __IO uint8_t I2CM_SCDC_READ_UPDATE;              /**< SCDC Control Register This register configures the SCDC update status read through the I2C master interface., offset: 0x14 */
29663        uint8_t RESERVED_0[11];
29664   __I  uint8_t I2CM_READ_BUFF0;                    /**< I2C Master Sequential Read Buffer Register 0, offset: 0x20 */
29665   __I  uint8_t I2CM_READ_BUFF1;                    /**< I2C Master Sequential Read Buffer Register 1, offset: 0x21 */
29666   __I  uint8_t I2CM_READ_BUFF2;                    /**< I2C Master Sequential Read Buffer Register 2, offset: 0x22 */
29667   __I  uint8_t I2CM_READ_BUFF3;                    /**< I2C Master Sequential Read Buffer Register 3, offset: 0x23 */
29668   __I  uint8_t I2CM_READ_BUFF4;                    /**< I2C Master Sequential Read Buffer Register 4, offset: 0x24 */
29669   __I  uint8_t I2CM_READ_BUFF5;                    /**< I2C Master Sequential Read Buffer Register 5, offset: 0x25 */
29670   __I  uint8_t I2CM_READ_BUFF6;                    /**< I2C Master Sequential Read Buffer Register 6, offset: 0x26 */
29671   __I  uint8_t I2CM_READ_BUFF7;                    /**< I2C Master Sequential Read Buffer Register 7, offset: 0x27 */
29672        uint8_t RESERVED_1[8];
29673   __I  uint8_t I2CM_SCDC_UPDATE0;                  /**< I2C SCDC Read Update Register 0, offset: 0x30 */
29674   __I  uint8_t I2CM_SCDC_UPDATE1;                  /**< I2C SCDC Read Update Register 1, offset: 0x31 */
29675 } EDDC_Type;
29676 
29677 /* ----------------------------------------------------------------------------
29678    -- EDDC Register Masks
29679    ---------------------------------------------------------------------------- */
29680 
29681 /*!
29682  * @addtogroup EDDC_Register_Masks EDDC Register Masks
29683  * @{
29684  */
29685 
29686 /*! @name I2CM_SLAVE - I2C DDC Slave address Configuration Register */
29687 /*! @{ */
29688 
29689 #define EDDC_I2CM_SLAVE_SLAVEADDR_MASK           (0x7FU)
29690 #define EDDC_I2CM_SLAVE_SLAVEADDR_SHIFT          (0U)
29691 /*! slaveaddr - Slave address to be sent during read and write normal operations. */
29692 #define EDDC_I2CM_SLAVE_SLAVEADDR(x)             (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SLAVE_SLAVEADDR_SHIFT)) & EDDC_I2CM_SLAVE_SLAVEADDR_MASK)
29693 /*! @} */
29694 
29695 /*! @name I2CM_ADDRESS - I2C DDC Address Configuration Register */
29696 /*! @{ */
29697 
29698 #define EDDC_I2CM_ADDRESS_ADDRESS_MASK           (0xFFU)
29699 #define EDDC_I2CM_ADDRESS_ADDRESS_SHIFT          (0U)
29700 /*! address - Register address for read and write operations */
29701 #define EDDC_I2CM_ADDRESS_ADDRESS(x)             (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_ADDRESS_ADDRESS_SHIFT)) & EDDC_I2CM_ADDRESS_ADDRESS_MASK)
29702 /*! @} */
29703 
29704 /*! @name I2CM_DATAO - I2C DDC Data Write Register */
29705 /*! @{ */
29706 
29707 #define EDDC_I2CM_DATAO_DATAO_MASK               (0xFFU)
29708 #define EDDC_I2CM_DATAO_DATAO_SHIFT              (0U)
29709 /*! datao - Data to be written on register pointed by address[7:0]. */
29710 #define EDDC_I2CM_DATAO_DATAO(x)                 (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DATAO_DATAO_SHIFT)) & EDDC_I2CM_DATAO_DATAO_MASK)
29711 /*! @} */
29712 
29713 /*! @name I2CM_DATAI - I2C DDC Data read Register */
29714 /*! @{ */
29715 
29716 #define EDDC_I2CM_DATAI_DATAI_MASK               (0xFFU)
29717 #define EDDC_I2CM_DATAI_DATAI_SHIFT              (0U)
29718 /*! datai - Data read from register pointed by address[7:0]. */
29719 #define EDDC_I2CM_DATAI_DATAI(x)                 (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DATAI_DATAI_SHIFT)) & EDDC_I2CM_DATAI_DATAI_MASK)
29720 /*! @} */
29721 
29722 /*! @name I2CM_OPERATION - I2C DDC RD/RD_EXT/WR Operation Register Read and write operation request. */
29723 /*! @{ */
29724 
29725 #define EDDC_I2CM_OPERATION_RD_MASK              (0x1U)
29726 #define EDDC_I2CM_OPERATION_RD_SHIFT             (0U)
29727 /*! rd - Single byte read operation request */
29728 #define EDDC_I2CM_OPERATION_RD(x)                (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD_SHIFT)) & EDDC_I2CM_OPERATION_RD_MASK)
29729 
29730 #define EDDC_I2CM_OPERATION_RD_EXT_MASK          (0x2U)
29731 #define EDDC_I2CM_OPERATION_RD_EXT_SHIFT         (1U)
29732 /*! rd_ext - After writing 1'b1 to rd_ext bit a extended data read operation is started (E-DDC read operation). */
29733 #define EDDC_I2CM_OPERATION_RD_EXT(x)            (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD_EXT_SHIFT)) & EDDC_I2CM_OPERATION_RD_EXT_MASK)
29734 
29735 #define EDDC_I2CM_OPERATION_RD8_MASK             (0x4U)
29736 #define EDDC_I2CM_OPERATION_RD8_SHIFT            (2U)
29737 /*! rd8 - Sequential read operation request. */
29738 #define EDDC_I2CM_OPERATION_RD8(x)               (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD8_SHIFT)) & EDDC_I2CM_OPERATION_RD8_MASK)
29739 
29740 #define EDDC_I2CM_OPERATION_RD8_EXT_MASK         (0x8U)
29741 #define EDDC_I2CM_OPERATION_RD8_EXT_SHIFT        (3U)
29742 /*! rd8_ext - Extended sequential read operation request. */
29743 #define EDDC_I2CM_OPERATION_RD8_EXT(x)           (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD8_EXT_SHIFT)) & EDDC_I2CM_OPERATION_RD8_EXT_MASK)
29744 
29745 #define EDDC_I2CM_OPERATION_WR_MASK              (0x10U)
29746 #define EDDC_I2CM_OPERATION_WR_SHIFT             (4U)
29747 /*! wr - Single byte write operation request. */
29748 #define EDDC_I2CM_OPERATION_WR(x)                (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_WR_SHIFT)) & EDDC_I2CM_OPERATION_WR_MASK)
29749 
29750 #define EDDC_I2CM_OPERATION_BUSCLEAR_MASK        (0x20U)
29751 #define EDDC_I2CM_OPERATION_BUSCLEAR_SHIFT       (5U)
29752 /*! busclear - bus clear operation request. */
29753 #define EDDC_I2CM_OPERATION_BUSCLEAR(x)          (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_BUSCLEAR_SHIFT)) & EDDC_I2CM_OPERATION_BUSCLEAR_MASK)
29754 /*! @} */
29755 
29756 /*! @name I2CM_INT - I2C DDC Done Interrupt Register This register configures the I2C master interrupts. */
29757 /*! @{ */
29758 
29759 #define EDDC_I2CM_INT_DONE_MASK_MASK             (0x4U)
29760 #define EDDC_I2CM_INT_DONE_MASK_SHIFT            (2U)
29761 /*! done_mask - Done interrupt mask signal. */
29762 #define EDDC_I2CM_INT_DONE_MASK(x)               (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_INT_DONE_MASK_SHIFT)) & EDDC_I2CM_INT_DONE_MASK_MASK)
29763 
29764 #define EDDC_I2CM_INT_READ_REQ_MASK_MASK         (0x40U)
29765 #define EDDC_I2CM_INT_READ_REQ_MASK_SHIFT        (6U)
29766 /*! read_req_mask - Read request interruption mask signal. */
29767 #define EDDC_I2CM_INT_READ_REQ_MASK(x)           (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_INT_READ_REQ_MASK_SHIFT)) & EDDC_I2CM_INT_READ_REQ_MASK_MASK)
29768 /*! @} */
29769 
29770 /*! @name I2CM_CTLINT - I2C DDC error Interrupt Register This register configures the I2C master arbitration lost and not acknowledge error interrupts. */
29771 /*! @{ */
29772 
29773 #define EDDC_I2CM_CTLINT_ARBITRATION_MASK_MASK   (0x4U)
29774 #define EDDC_I2CM_CTLINT_ARBITRATION_MASK_SHIFT  (2U)
29775 /*! arbitration_mask - Arbitration error interrupt mask signal. */
29776 #define EDDC_I2CM_CTLINT_ARBITRATION_MASK(x)     (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_CTLINT_ARBITRATION_MASK_SHIFT)) & EDDC_I2CM_CTLINT_ARBITRATION_MASK_MASK)
29777 
29778 #define EDDC_I2CM_CTLINT_NACK_MASK_MASK          (0x40U)
29779 #define EDDC_I2CM_CTLINT_NACK_MASK_SHIFT         (6U)
29780 /*! nack_mask - Not acknowledge error interrupt mask signal. */
29781 #define EDDC_I2CM_CTLINT_NACK_MASK(x)            (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_CTLINT_NACK_MASK_SHIFT)) & EDDC_I2CM_CTLINT_NACK_MASK_MASK)
29782 /*! @} */
29783 
29784 /*! @name I2CM_DIV - I2C DDC Speed Control Register This register configures the division relation between master and scl clock. */
29785 /*! @{ */
29786 
29787 #define EDDC_I2CM_DIV_SPARE_MASK                 (0x7U)
29788 #define EDDC_I2CM_DIV_SPARE_SHIFT                (0U)
29789 /*! spare - Reserved as "spare" bit with no associated functionality. */
29790 #define EDDC_I2CM_DIV_SPARE(x)                   (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DIV_SPARE_SHIFT)) & EDDC_I2CM_DIV_SPARE_MASK)
29791 
29792 #define EDDC_I2CM_DIV_FAST_STD_MODE_MASK         (0x8U)
29793 #define EDDC_I2CM_DIV_FAST_STD_MODE_SHIFT        (3U)
29794 /*! fast_std_mode - Sets the I2C Master to work in Fast Mode or Standard Mode: 1: Fast Mode 0: Standard Mode */
29795 #define EDDC_I2CM_DIV_FAST_STD_MODE(x)           (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DIV_FAST_STD_MODE_SHIFT)) & EDDC_I2CM_DIV_FAST_STD_MODE_MASK)
29796 /*! @} */
29797 
29798 /*! @name I2CM_SEGADDR - I2C DDC Segment Address Configuration Register This register configures the segment address for extended R/W destination and is used for EDID reading operations, particularly for the Extended Data Read Operation for Enhanced DDC. */
29799 /*! @{ */
29800 
29801 #define EDDC_I2CM_SEGADDR_SEG_ADDR_MASK          (0x7FU)
29802 #define EDDC_I2CM_SEGADDR_SEG_ADDR_SHIFT         (0U)
29803 /*! seg_addr - I2C DDC Segment Address Configuration Register */
29804 #define EDDC_I2CM_SEGADDR_SEG_ADDR(x)            (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SEGADDR_SEG_ADDR_SHIFT)) & EDDC_I2CM_SEGADDR_SEG_ADDR_MASK)
29805 /*! @} */
29806 
29807 /*! @name I2CM_SOFTRSTZ - I2C DDC Software Reset Control Register This register resets the I2C master. */
29808 /*! @{ */
29809 
29810 #define EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK     (0x1U)
29811 #define EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT    (0U)
29812 /*! i2c_softrstz - I2C Master Software Reset. */
29813 #define EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ(x)       (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT)) & EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK)
29814 /*! @} */
29815 
29816 /*! @name I2CM_SEGPTR - I2C DDC Segment Pointer Register This register configures the segment pointer for extended RD/WR request. */
29817 /*! @{ */
29818 
29819 #define EDDC_I2CM_SEGPTR_SEGPTR_MASK             (0xFFU)
29820 #define EDDC_I2CM_SEGPTR_SEGPTR_SHIFT            (0U)
29821 /*! segptr - I2C DDC Segment Pointer Register */
29822 #define EDDC_I2CM_SEGPTR_SEGPTR(x)               (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SEGPTR_SEGPTR_SHIFT)) & EDDC_I2CM_SEGPTR_SEGPTR_MASK)
29823 /*! @} */
29824 
29825 /*! @name I2CM_SS_SCL_HCNT_1_ADDR - I2C DDC Slow Speed SCL High Level Control Register 1 */
29826 /*! @{ */
29827 
29828 #define EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK (0xFFU)
29829 #define EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT (0U)
29830 /*! i2cmp_ss_scl_hcnt1 - I2C DDC Slow Speed SCL High Level Control Register 1 */
29831 #define EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT)) & EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK)
29832 /*! @} */
29833 
29834 /*! @name I2CM_SS_SCL_HCNT_0_ADDR - I2C DDC Slow Speed SCL High Level Control Register 0 */
29835 /*! @{ */
29836 
29837 #define EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK (0xFFU)
29838 #define EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT (0U)
29839 /*! i2cmp_ss_scl_hcnt0 - I2C DDC Slow Speed SCL High Level Control Register 0 */
29840 #define EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT)) & EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK)
29841 /*! @} */
29842 
29843 /*! @name I2CM_SS_SCL_LCNT_1_ADDR - I2C DDC Slow Speed SCL Low Level Control Register 1 */
29844 /*! @{ */
29845 
29846 #define EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK (0xFFU)
29847 #define EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT (0U)
29848 /*! i2cmp_ss_scl_lcnt1 - I2C DDC Slow Speed SCL Low Level Control Register 1 */
29849 #define EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT)) & EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK)
29850 /*! @} */
29851 
29852 /*! @name I2CM_SS_SCL_LCNT_0_ADDR - I2C DDC Slow Speed SCL Low Level Control Register 0 */
29853 /*! @{ */
29854 
29855 #define EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK (0xFFU)
29856 #define EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT (0U)
29857 /*! i2cmp_ss_scl_lcnt0 - I2C DDC Slow Speed SCL Low Level Control Register 0 */
29858 #define EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT)) & EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK)
29859 /*! @} */
29860 
29861 /*! @name I2CM_FS_SCL_HCNT_1_ADDR - I2C DDC Fast Speed SCL High Level Control Register 1 */
29862 /*! @{ */
29863 
29864 #define EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK (0xFFU)
29865 #define EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT (0U)
29866 /*! i2cmp_fs_scl_hcnt1 - I2C DDC Fast Speed SCL High Level Control Register 1 */
29867 #define EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT)) & EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK)
29868 /*! @} */
29869 
29870 /*! @name I2CM_FS_SCL_HCNT_0_ADDR - I2C DDC Fast Speed SCL High Level Control Register 0 */
29871 /*! @{ */
29872 
29873 #define EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK (0xFFU)
29874 #define EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT (0U)
29875 /*! i2cmp_fs_scl_hcnt0 - I2C DDC Fast Speed SCL High Level Control Register 0 */
29876 #define EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT)) & EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK)
29877 /*! @} */
29878 
29879 /*! @name I2CM_FS_SCL_LCNT_1_ADDR - I2C DDC Fast Speed SCL Low Level Control Register 1 */
29880 /*! @{ */
29881 
29882 #define EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK (0xFFU)
29883 #define EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT (0U)
29884 /*! i2cmp_fs_scl_lcnt1 - I2C DDC Fast Speed SCL Low Level Control Register 1 */
29885 #define EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT)) & EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK)
29886 /*! @} */
29887 
29888 /*! @name I2CM_FS_SCL_LCNT_0_ADDR - I2C DDC Fast Speed SCL Low Level Control Register 0 */
29889 /*! @{ */
29890 
29891 #define EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK (0xFFU)
29892 #define EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT (0U)
29893 /*! i2cmp_fs_scl_lcnt0 - I2C DDC Fast Speed SCL Low Level Control Register 0 */
29894 #define EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT)) & EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK)
29895 /*! @} */
29896 
29897 /*! @name I2CM_SDA_HOLD - I2C DDC SDA Hold Register */
29898 /*! @{ */
29899 
29900 #define EDDC_I2CM_SDA_HOLD_OSDA_HOLD_MASK        (0xFFU)
29901 #define EDDC_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT       (0U)
29902 /*! osda_hold - Defines the number of SFR clock cycles to meet tHD;DAT (300 ns) osda_hold =
29903  *    round_to_high_integer (300 ns / (1 / isfrclk_frequency))
29904  */
29905 #define EDDC_I2CM_SDA_HOLD_OSDA_HOLD(x)          (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT)) & EDDC_I2CM_SDA_HOLD_OSDA_HOLD_MASK)
29906 /*! @} */
29907 
29908 /*! @name I2CM_SCDC_READ_UPDATE - SCDC Control Register This register configures the SCDC update status read through the I2C master interface. */
29909 /*! @{ */
29910 
29911 #define EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_MASK (0x1U)
29912 #define EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_SHIFT (0U)
29913 /*! read_update - When set to 1'b1, a SCDC Update Read is performed and the read data loaded into
29914  *    registers i2cm_scdc_update0 and i2cm_scdc_update1.
29915  */
29916 #define EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_SHIFT)) & EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_MASK)
29917 
29918 #define EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_MASK (0x10U)
29919 #define EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_SHIFT (4U)
29920 /*! read_request_en - Read request enabled. */
29921 #define EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_SHIFT)) & EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_MASK)
29922 
29923 #define EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_MASK (0x20U)
29924 #define EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_SHIFT (5U)
29925 /*! updtrd_vsyncpoll_en - Update read polling enabled. */
29926 #define EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_SHIFT)) & EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_MASK)
29927 /*! @} */
29928 
29929 /*! @name I2CM_READ_BUFF0 - I2C Master Sequential Read Buffer Register 0 */
29930 /*! @{ */
29931 
29932 #define EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_MASK (0xFFU)
29933 #define EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_SHIFT (0U)
29934 /*! i2cm_read_buff0 - Byte 0 of a I2C read buffer sequential read (from address i2cm_address) */
29935 #define EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_SHIFT)) & EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_MASK)
29936 /*! @} */
29937 
29938 /*! @name I2CM_READ_BUFF1 - I2C Master Sequential Read Buffer Register 1 */
29939 /*! @{ */
29940 
29941 #define EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_MASK (0xFFU)
29942 #define EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_SHIFT (0U)
29943 /*! i2cm_read_buff1 - Byte 1 of a I2C read buffer sequential read (from address i2cm_address+1) */
29944 #define EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_SHIFT)) & EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_MASK)
29945 /*! @} */
29946 
29947 /*! @name I2CM_READ_BUFF2 - I2C Master Sequential Read Buffer Register 2 */
29948 /*! @{ */
29949 
29950 #define EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_MASK (0xFFU)
29951 #define EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_SHIFT (0U)
29952 /*! i2cm_read_buff2 - Byte 2 of a I2C read buffer sequential read (from address i2cm_address+2) */
29953 #define EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_SHIFT)) & EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_MASK)
29954 /*! @} */
29955 
29956 /*! @name I2CM_READ_BUFF3 - I2C Master Sequential Read Buffer Register 3 */
29957 /*! @{ */
29958 
29959 #define EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_MASK (0xFFU)
29960 #define EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_SHIFT (0U)
29961 /*! i2cm_read_buff3 - Byte 3 of a I2C read buffer sequential read (from address i2cm_address+3) */
29962 #define EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_SHIFT)) & EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_MASK)
29963 /*! @} */
29964 
29965 /*! @name I2CM_READ_BUFF4 - I2C Master Sequential Read Buffer Register 4 */
29966 /*! @{ */
29967 
29968 #define EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_MASK (0xFFU)
29969 #define EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_SHIFT (0U)
29970 /*! i2cm_read_buff4 - Byte 4 of a I2C read buffer sequential read (from address i2cm_address+4) */
29971 #define EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_SHIFT)) & EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_MASK)
29972 /*! @} */
29973 
29974 /*! @name I2CM_READ_BUFF5 - I2C Master Sequential Read Buffer Register 5 */
29975 /*! @{ */
29976 
29977 #define EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_MASK (0xFFU)
29978 #define EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_SHIFT (0U)
29979 /*! i2cm_read_buff5 - Byte 5 of a I2C read buffer sequential read (from address i2cm_address+5) */
29980 #define EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_SHIFT)) & EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_MASK)
29981 /*! @} */
29982 
29983 /*! @name I2CM_READ_BUFF6 - I2C Master Sequential Read Buffer Register 6 */
29984 /*! @{ */
29985 
29986 #define EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_MASK (0xFFU)
29987 #define EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_SHIFT (0U)
29988 /*! i2cm_read_buff6 - Byte 6 of a I2C read buffer sequential read (from address i2cm_address+6) */
29989 #define EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_SHIFT)) & EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_MASK)
29990 /*! @} */
29991 
29992 /*! @name I2CM_READ_BUFF7 - I2C Master Sequential Read Buffer Register 7 */
29993 /*! @{ */
29994 
29995 #define EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_MASK (0xFFU)
29996 #define EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_SHIFT (0U)
29997 /*! i2cm_read_buff7 - Byte 7 of a I2C read buffer sequential read (from address i2cm_address+7) */
29998 #define EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7(x)  (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_SHIFT)) & EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_MASK)
29999 /*! @} */
30000 
30001 /*! @name I2CM_SCDC_UPDATE0 - I2C SCDC Read Update Register 0 */
30002 /*! @{ */
30003 
30004 #define EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_MASK (0xFFU)
30005 #define EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_SHIFT (0U)
30006 /*! i2cm_scdc_update0 - Byte 0 of a SCDC I2C update sequential read */
30007 #define EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_SHIFT)) & EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_MASK)
30008 /*! @} */
30009 
30010 /*! @name I2CM_SCDC_UPDATE1 - I2C SCDC Read Update Register 1 */
30011 /*! @{ */
30012 
30013 #define EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_MASK (0xFFU)
30014 #define EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_SHIFT (0U)
30015 /*! i2cm_scdc_update1 - Byte 1 of a SCDC I2C update sequential read */
30016 #define EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_SHIFT)) & EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_MASK)
30017 /*! @} */
30018 
30019 
30020 /*!
30021  * @}
30022  */ /* end of group EDDC_Register_Masks */
30023 
30024 
30025 /* EDDC - Peripheral instance base addresses */
30026 /** Peripheral EDDC base address */
30027 #define EDDC_BASE                                (0x32FDFE00u)
30028 /** Peripheral EDDC base pointer */
30029 #define EDDC                                     ((EDDC_Type *)EDDC_BASE)
30030 /** Array initializer of EDDC peripheral base addresses */
30031 #define EDDC_BASE_ADDRS                          { EDDC_BASE }
30032 /** Array initializer of EDDC peripheral base pointers */
30033 #define EDDC_BASE_PTRS                           { EDDC }
30034 
30035 /*!
30036  * @}
30037  */ /* end of group EDDC_Peripheral_Access_Layer */
30038 
30039 
30040 /* ----------------------------------------------------------------------------
30041    -- ENET Peripheral Access Layer
30042    ---------------------------------------------------------------------------- */
30043 
30044 /*!
30045  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
30046  * @{
30047  */
30048 
30049 /** ENET - Register Layout Typedef */
30050 typedef struct {
30051        uint8_t RESERVED_0[4];
30052   __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
30053   __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
30054        uint8_t RESERVED_1[4];
30055   __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
30056   __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
30057        uint8_t RESERVED_2[12];
30058   __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
30059        uint8_t RESERVED_3[24];
30060   __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
30061   __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
30062        uint8_t RESERVED_4[28];
30063   __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
30064        uint8_t RESERVED_5[28];
30065   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
30066        uint8_t RESERVED_6[60];
30067   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
30068        uint8_t RESERVED_7[28];
30069   __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
30070   __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
30071   __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
30072   __IO uint32_t TXIC[3];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
30073        uint8_t RESERVED_8[4];
30074   __IO uint32_t RXIC[3];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
30075        uint8_t RESERVED_9[12];
30076   __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
30077   __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
30078   __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
30079   __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
30080        uint8_t RESERVED_10[28];
30081   __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
30082        uint8_t RESERVED_11[24];
30083   __IO uint32_t RDSR1;                             /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
30084   __IO uint32_t TDSR1;                             /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
30085   __IO uint32_t MRBR1;                             /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
30086   __IO uint32_t RDSR2;                             /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
30087   __IO uint32_t TDSR2;                             /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
30088   __IO uint32_t MRBR2;                             /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
30089        uint8_t RESERVED_12[8];
30090   __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
30091   __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
30092   __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
30093        uint8_t RESERVED_13[4];
30094   __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
30095   __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
30096   __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
30097   __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
30098   __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
30099   __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
30100   __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
30101   __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
30102   __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
30103        uint8_t RESERVED_14[12];
30104   __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
30105   __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
30106   __IO uint32_t RCMR[2];                           /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
30107        uint8_t RESERVED_15[8];
30108   __IO uint32_t DMACFG[2];                         /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
30109   __IO uint32_t RDAR1;                             /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
30110   __IO uint32_t TDAR1;                             /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
30111   __IO uint32_t RDAR2;                             /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
30112   __IO uint32_t TDAR2;                             /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
30113   __IO uint32_t QOS;                               /**< QOS Scheme, offset: 0x1F0 */
30114        uint8_t RESERVED_16[12];
30115        uint32_t RMON_T_DROP;                       /**< Reserved Statistic Register, offset: 0x200 */
30116   __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
30117   __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
30118   __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
30119   __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
30120   __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
30121   __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
30122   __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
30123   __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
30124   __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
30125   __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
30126   __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
30127   __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
30128   __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
30129   __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
30130   __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
30131   __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
30132   __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
30133        uint32_t IEEE_T_DROP;                       /**< Reserved Statistic Register, offset: 0x248 */
30134   __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
30135   __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
30136   __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
30137   __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
30138   __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
30139   __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
30140   __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
30141   __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
30142   __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
30143   __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
30144   __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
30145        uint8_t RESERVED_17[12];
30146   __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
30147   __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
30148   __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
30149   __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
30150   __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
30151   __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
30152   __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
30153   __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
30154        uint32_t RMON_R_RESVD_0;                    /**< Reserved Statistic Register, offset: 0x2A4 */
30155   __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
30156   __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
30157   __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
30158   __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
30159   __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
30160   __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
30161   __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
30162   __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
30163   __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
30164   __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
30165   __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
30166   __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
30167   __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
30168   __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
30169   __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
30170        uint8_t RESERVED_18[284];
30171   __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
30172   __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
30173   __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
30174   __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
30175   __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
30176   __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
30177   __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
30178        uint8_t RESERVED_19[488];
30179   __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
30180   struct {                                         /* offset: 0x608, array step: 0x8 */
30181     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
30182     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
30183   } CHANNEL[4];
30184 } ENET_Type;
30185 
30186 /* ----------------------------------------------------------------------------
30187    -- ENET Register Masks
30188    ---------------------------------------------------------------------------- */
30189 
30190 /*!
30191  * @addtogroup ENET_Register_Masks ENET Register Masks
30192  * @{
30193  */
30194 
30195 /*! @name EIR - Interrupt Event Register */
30196 /*! @{ */
30197 
30198 #define ENET_EIR_RXB1_MASK                       (0x1U)
30199 #define ENET_EIR_RXB1_SHIFT                      (0U)
30200 /*! RXB1 - Receive buffer interrupt, class 1 */
30201 #define ENET_EIR_RXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
30202 
30203 #define ENET_EIR_RXF1_MASK                       (0x2U)
30204 #define ENET_EIR_RXF1_SHIFT                      (1U)
30205 /*! RXF1 - Receive frame interrupt, class 1 */
30206 #define ENET_EIR_RXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
30207 
30208 #define ENET_EIR_TXB1_MASK                       (0x4U)
30209 #define ENET_EIR_TXB1_SHIFT                      (2U)
30210 /*! TXB1 - Transmit buffer interrupt, class 1 */
30211 #define ENET_EIR_TXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
30212 
30213 #define ENET_EIR_TXF1_MASK                       (0x8U)
30214 #define ENET_EIR_TXF1_SHIFT                      (3U)
30215 /*! TXF1 - Transmit frame interrupt, class 1 */
30216 #define ENET_EIR_TXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
30217 
30218 #define ENET_EIR_RXB2_MASK                       (0x10U)
30219 #define ENET_EIR_RXB2_SHIFT                      (4U)
30220 /*! RXB2 - Receive buffer interrupt, class 2 */
30221 #define ENET_EIR_RXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
30222 
30223 #define ENET_EIR_RXF2_MASK                       (0x20U)
30224 #define ENET_EIR_RXF2_SHIFT                      (5U)
30225 /*! RXF2 - Receive frame interrupt, class 2 */
30226 #define ENET_EIR_RXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
30227 
30228 #define ENET_EIR_TXB2_MASK                       (0x40U)
30229 #define ENET_EIR_TXB2_SHIFT                      (6U)
30230 /*! TXB2 - Transmit buffer interrupt, class 2 */
30231 #define ENET_EIR_TXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
30232 
30233 #define ENET_EIR_TXF2_MASK                       (0x80U)
30234 #define ENET_EIR_TXF2_SHIFT                      (7U)
30235 /*! TXF2 - Transmit frame interrupt, class 2 */
30236 #define ENET_EIR_TXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
30237 
30238 #define ENET_EIR_RXFLUSH_0_MASK                  (0x1000U)
30239 #define ENET_EIR_RXFLUSH_0_SHIFT                 (12U)
30240 #define ENET_EIR_RXFLUSH_0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
30241 
30242 #define ENET_EIR_RXFLUSH_1_MASK                  (0x2000U)
30243 #define ENET_EIR_RXFLUSH_1_SHIFT                 (13U)
30244 #define ENET_EIR_RXFLUSH_1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
30245 
30246 #define ENET_EIR_RXFLUSH_2_MASK                  (0x4000U)
30247 #define ENET_EIR_RXFLUSH_2_SHIFT                 (14U)
30248 #define ENET_EIR_RXFLUSH_2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
30249 
30250 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
30251 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
30252 /*! TS_TIMER - Timestamp Timer */
30253 #define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
30254 
30255 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
30256 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
30257 /*! TS_AVAIL - Transmit Timestamp Available */
30258 #define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
30259 
30260 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
30261 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
30262 /*! WAKEUP - Node Wakeup Request Indication */
30263 #define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
30264 
30265 #define ENET_EIR_PLR_MASK                        (0x40000U)
30266 #define ENET_EIR_PLR_SHIFT                       (18U)
30267 /*! PLR - Payload Receive Error */
30268 #define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
30269 
30270 #define ENET_EIR_UN_MASK                         (0x80000U)
30271 #define ENET_EIR_UN_SHIFT                        (19U)
30272 /*! UN - Transmit FIFO Underrun */
30273 #define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
30274 
30275 #define ENET_EIR_RL_MASK                         (0x100000U)
30276 #define ENET_EIR_RL_SHIFT                        (20U)
30277 /*! RL - Collision Retry Limit */
30278 #define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
30279 
30280 #define ENET_EIR_LC_MASK                         (0x200000U)
30281 #define ENET_EIR_LC_SHIFT                        (21U)
30282 /*! LC - Late Collision */
30283 #define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
30284 
30285 #define ENET_EIR_EBERR_MASK                      (0x400000U)
30286 #define ENET_EIR_EBERR_SHIFT                     (22U)
30287 /*! EBERR - Ethernet Bus Error */
30288 #define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
30289 
30290 #define ENET_EIR_MII_MASK                        (0x800000U)
30291 #define ENET_EIR_MII_SHIFT                       (23U)
30292 /*! MII - MII Interrupt. */
30293 #define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
30294 
30295 #define ENET_EIR_RXB_MASK                        (0x1000000U)
30296 #define ENET_EIR_RXB_SHIFT                       (24U)
30297 /*! RXB - Receive Buffer Interrupt */
30298 #define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
30299 
30300 #define ENET_EIR_RXF_MASK                        (0x2000000U)
30301 #define ENET_EIR_RXF_SHIFT                       (25U)
30302 /*! RXF - Receive Frame Interrupt */
30303 #define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
30304 
30305 #define ENET_EIR_TXB_MASK                        (0x4000000U)
30306 #define ENET_EIR_TXB_SHIFT                       (26U)
30307 /*! TXB - Transmit Buffer Interrupt */
30308 #define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
30309 
30310 #define ENET_EIR_TXF_MASK                        (0x8000000U)
30311 #define ENET_EIR_TXF_SHIFT                       (27U)
30312 /*! TXF - Transmit Frame Interrupt */
30313 #define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
30314 
30315 #define ENET_EIR_GRA_MASK                        (0x10000000U)
30316 #define ENET_EIR_GRA_SHIFT                       (28U)
30317 /*! GRA - Graceful Stop Complete */
30318 #define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
30319 
30320 #define ENET_EIR_BABT_MASK                       (0x20000000U)
30321 #define ENET_EIR_BABT_SHIFT                      (29U)
30322 /*! BABT - Babbling Transmit Error */
30323 #define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
30324 
30325 #define ENET_EIR_BABR_MASK                       (0x40000000U)
30326 #define ENET_EIR_BABR_SHIFT                      (30U)
30327 /*! BABR - Babbling Receive Error */
30328 #define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
30329 /*! @} */
30330 
30331 /*! @name EIMR - Interrupt Mask Register */
30332 /*! @{ */
30333 
30334 #define ENET_EIMR_RXB1_MASK                      (0x1U)
30335 #define ENET_EIMR_RXB1_SHIFT                     (0U)
30336 /*! RXB1 - Receive buffer interrupt, class 1 */
30337 #define ENET_EIMR_RXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
30338 
30339 #define ENET_EIMR_RXF1_MASK                      (0x2U)
30340 #define ENET_EIMR_RXF1_SHIFT                     (1U)
30341 /*! RXF1 - Receive frame interrupt, class 1 */
30342 #define ENET_EIMR_RXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
30343 
30344 #define ENET_EIMR_TXB1_MASK                      (0x4U)
30345 #define ENET_EIMR_TXB1_SHIFT                     (2U)
30346 /*! TXB1 - Transmit buffer interrupt, class 1 */
30347 #define ENET_EIMR_TXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
30348 
30349 #define ENET_EIMR_TXF1_MASK                      (0x8U)
30350 #define ENET_EIMR_TXF1_SHIFT                     (3U)
30351 /*! TXF1 - Transmit frame interrupt, class 1 */
30352 #define ENET_EIMR_TXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
30353 
30354 #define ENET_EIMR_RXB2_MASK                      (0x10U)
30355 #define ENET_EIMR_RXB2_SHIFT                     (4U)
30356 /*! RXB2 - Receive buffer interrupt, class 2 */
30357 #define ENET_EIMR_RXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
30358 
30359 #define ENET_EIMR_RXF2_MASK                      (0x20U)
30360 #define ENET_EIMR_RXF2_SHIFT                     (5U)
30361 /*! RXF2 - Receive frame interrupt, class 2 */
30362 #define ENET_EIMR_RXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
30363 
30364 #define ENET_EIMR_TXB2_MASK                      (0x40U)
30365 #define ENET_EIMR_TXB2_SHIFT                     (6U)
30366 /*! TXB2 - Transmit buffer interrupt, class 2 */
30367 #define ENET_EIMR_TXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
30368 
30369 #define ENET_EIMR_TXF2_MASK                      (0x80U)
30370 #define ENET_EIMR_TXF2_SHIFT                     (7U)
30371 /*! TXF2 - Transmit frame interrupt, class 2 */
30372 #define ENET_EIMR_TXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
30373 
30374 #define ENET_EIMR_RXFLUSH_0_MASK                 (0x1000U)
30375 #define ENET_EIMR_RXFLUSH_0_SHIFT                (12U)
30376 #define ENET_EIMR_RXFLUSH_0(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
30377 
30378 #define ENET_EIMR_RXFLUSH_1_MASK                 (0x2000U)
30379 #define ENET_EIMR_RXFLUSH_1_SHIFT                (13U)
30380 #define ENET_EIMR_RXFLUSH_1(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
30381 
30382 #define ENET_EIMR_RXFLUSH_2_MASK                 (0x4000U)
30383 #define ENET_EIMR_RXFLUSH_2_SHIFT                (14U)
30384 #define ENET_EIMR_RXFLUSH_2(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
30385 
30386 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
30387 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
30388 /*! TS_TIMER - TS_TIMER Interrupt Mask */
30389 #define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
30390 
30391 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
30392 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
30393 /*! TS_AVAIL - TS_AVAIL Interrupt Mask */
30394 #define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
30395 
30396 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
30397 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
30398 /*! WAKEUP - WAKEUP Interrupt Mask */
30399 #define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
30400 
30401 #define ENET_EIMR_PLR_MASK                       (0x40000U)
30402 #define ENET_EIMR_PLR_SHIFT                      (18U)
30403 /*! PLR - PLR Interrupt Mask */
30404 #define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
30405 
30406 #define ENET_EIMR_UN_MASK                        (0x80000U)
30407 #define ENET_EIMR_UN_SHIFT                       (19U)
30408 /*! UN - UN Interrupt Mask */
30409 #define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
30410 
30411 #define ENET_EIMR_RL_MASK                        (0x100000U)
30412 #define ENET_EIMR_RL_SHIFT                       (20U)
30413 /*! RL - RL Interrupt Mask */
30414 #define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
30415 
30416 #define ENET_EIMR_LC_MASK                        (0x200000U)
30417 #define ENET_EIMR_LC_SHIFT                       (21U)
30418 /*! LC - LC Interrupt Mask */
30419 #define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
30420 
30421 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
30422 #define ENET_EIMR_EBERR_SHIFT                    (22U)
30423 /*! EBERR - EBERR Interrupt Mask */
30424 #define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
30425 
30426 #define ENET_EIMR_MII_MASK                       (0x800000U)
30427 #define ENET_EIMR_MII_SHIFT                      (23U)
30428 /*! MII - MII Interrupt Mask */
30429 #define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
30430 
30431 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
30432 #define ENET_EIMR_RXB_SHIFT                      (24U)
30433 /*! RXB - RXB Interrupt Mask */
30434 #define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
30435 
30436 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
30437 #define ENET_EIMR_RXF_SHIFT                      (25U)
30438 /*! RXF - RXF Interrupt Mask */
30439 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
30440 
30441 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
30442 #define ENET_EIMR_TXB_SHIFT                      (26U)
30443 /*! TXB - TXB Interrupt Mask
30444  *  0b0..The corresponding interrupt source is masked.
30445  *  0b1..The corresponding interrupt source is not masked.
30446  */
30447 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
30448 
30449 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
30450 #define ENET_EIMR_TXF_SHIFT                      (27U)
30451 /*! TXF - TXF Interrupt Mask
30452  *  0b0..The corresponding interrupt source is masked.
30453  *  0b1..The corresponding interrupt source is not masked.
30454  */
30455 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
30456 
30457 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
30458 #define ENET_EIMR_GRA_SHIFT                      (28U)
30459 /*! GRA - GRA Interrupt Mask
30460  *  0b0..The corresponding interrupt source is masked.
30461  *  0b1..The corresponding interrupt source is not masked.
30462  */
30463 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
30464 
30465 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
30466 #define ENET_EIMR_BABT_SHIFT                     (29U)
30467 /*! BABT - BABT Interrupt Mask
30468  *  0b0..The corresponding interrupt source is masked.
30469  *  0b1..The corresponding interrupt source is not masked.
30470  */
30471 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
30472 
30473 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
30474 #define ENET_EIMR_BABR_SHIFT                     (30U)
30475 /*! BABR - BABR Interrupt Mask
30476  *  0b0..The corresponding interrupt source is masked.
30477  *  0b1..The corresponding interrupt source is not masked.
30478  */
30479 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
30480 /*! @} */
30481 
30482 /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
30483 /*! @{ */
30484 
30485 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
30486 #define ENET_RDAR_RDAR_SHIFT                     (24U)
30487 /*! RDAR - Receive Descriptor Active */
30488 #define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
30489 /*! @} */
30490 
30491 /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
30492 /*! @{ */
30493 
30494 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
30495 #define ENET_TDAR_TDAR_SHIFT                     (24U)
30496 /*! TDAR - Transmit Descriptor Active */
30497 #define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
30498 /*! @} */
30499 
30500 /*! @name ECR - Ethernet Control Register */
30501 /*! @{ */
30502 
30503 #define ENET_ECR_RESET_MASK                      (0x1U)
30504 #define ENET_ECR_RESET_SHIFT                     (0U)
30505 /*! RESET - Ethernet MAC Reset */
30506 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
30507 
30508 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
30509 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
30510 /*! ETHEREN - Ethernet Enable
30511  *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
30512  *  0b1..MAC is enabled, and reception and transmission are possible.
30513  */
30514 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
30515 
30516 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
30517 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
30518 /*! MAGICEN - Magic Packet Detection Enable
30519  *  0b0..Magic detection logic disabled.
30520  *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
30521  */
30522 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
30523 
30524 #define ENET_ECR_SLEEP_MASK                      (0x8U)
30525 #define ENET_ECR_SLEEP_SHIFT                     (3U)
30526 /*! SLEEP - Sleep Mode Enable
30527  *  0b0..Normal operating mode.
30528  *  0b1..Sleep mode.
30529  */
30530 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
30531 
30532 #define ENET_ECR_EN1588_MASK                     (0x10U)
30533 #define ENET_ECR_EN1588_SHIFT                    (4U)
30534 /*! EN1588 - EN1588 Enable
30535  *  0b0..Legacy FEC buffer descriptors and functions enabled.
30536  *  0b1..Enhanced frame time-stamping functions enabled.
30537  */
30538 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
30539 
30540 #define ENET_ECR_SPEED_MASK                      (0x20U)
30541 #define ENET_ECR_SPEED_SHIFT                     (5U)
30542 /*! SPEED
30543  *  0b0..10/100-Mbit/s mode
30544  *  0b1..1000-Mbit/s mode
30545  */
30546 #define ENET_ECR_SPEED(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
30547 
30548 #define ENET_ECR_DBGEN_MASK                      (0x40U)
30549 #define ENET_ECR_DBGEN_SHIFT                     (6U)
30550 /*! DBGEN - Debug Enable
30551  *  0b0..MAC continues operation in debug mode.
30552  *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
30553  */
30554 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
30555 
30556 #define ENET_ECR_DBSWP_MASK                      (0x100U)
30557 #define ENET_ECR_DBSWP_SHIFT                     (8U)
30558 /*! DBSWP - Descriptor Byte Swapping Enable
30559  *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
30560  *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
30561  */
30562 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
30563 
30564 #define ENET_ECR_SVLANEN_MASK                    (0x200U)
30565 #define ENET_ECR_SVLANEN_SHIFT                   (9U)
30566 /*! SVLANEN - S-VLAN enable
30567  *  0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
30568  *  0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
30569  *       receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
30570  *       classification match comparators, RCMRn.
30571  */
30572 #define ENET_ECR_SVLANEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
30573 
30574 #define ENET_ECR_VLANUSE2ND_MASK                 (0x400U)
30575 #define ENET_ECR_VLANUSE2ND_SHIFT                (10U)
30576 /*! VLANUSE2ND - VLAN use second tag
30577  *  0b0..Always extract data from the first VLAN tag if it exists.
30578  *  0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
30579  *       double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
30580  *       second tag must be a C-VLAN
30581  */
30582 #define ENET_ECR_VLANUSE2ND(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
30583 
30584 #define ENET_ECR_SVLANDBL_MASK                   (0x800U)
30585 #define ENET_ECR_SVLANDBL_SHIFT                  (11U)
30586 /*! SVLANDBL - S-VLAN double tag */
30587 #define ENET_ECR_SVLANDBL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
30588 
30589 #define ENET_ECR_TXC_DLY_MASK                    (0x10000U)
30590 #define ENET_ECR_TXC_DLY_SHIFT                   (16U)
30591 /*! TXC_DLY - Transmit clock delay
30592  *  0b0..RGMII_TXC is not delayed.
30593  *  0b1..Generate delayed version of RGMII_TXC.
30594  */
30595 #define ENET_ECR_TXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
30596 
30597 #define ENET_ECR_RXC_DLY_MASK                    (0x20000U)
30598 #define ENET_ECR_RXC_DLY_SHIFT                   (17U)
30599 /*! RXC_DLY - Receive clock delay
30600  *  0b0..Use non-delayed version of RGMII_RXC.
30601  *  0b1..Use delayed version of RGMII_RXC.
30602  */
30603 #define ENET_ECR_RXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK)
30604 /*! @} */
30605 
30606 /*! @name MMFR - MII Management Frame Register */
30607 /*! @{ */
30608 
30609 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
30610 #define ENET_MMFR_DATA_SHIFT                     (0U)
30611 /*! DATA - Management Frame Data */
30612 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
30613 
30614 #define ENET_MMFR_TA_MASK                        (0x30000U)
30615 #define ENET_MMFR_TA_SHIFT                       (16U)
30616 /*! TA - Turn Around */
30617 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
30618 
30619 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
30620 #define ENET_MMFR_RA_SHIFT                       (18U)
30621 /*! RA - Register Address */
30622 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
30623 
30624 #define ENET_MMFR_PA_MASK                        (0xF800000U)
30625 #define ENET_MMFR_PA_SHIFT                       (23U)
30626 /*! PA - PHY Address */
30627 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
30628 
30629 #define ENET_MMFR_OP_MASK                        (0x30000000U)
30630 #define ENET_MMFR_OP_SHIFT                       (28U)
30631 /*! OP - Operation Code */
30632 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
30633 
30634 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
30635 #define ENET_MMFR_ST_SHIFT                       (30U)
30636 /*! ST - Start Of Frame Delimiter */
30637 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
30638 /*! @} */
30639 
30640 /*! @name MSCR - MII Speed Control Register */
30641 /*! @{ */
30642 
30643 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
30644 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
30645 /*! MII_SPEED - MII Speed */
30646 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
30647 
30648 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
30649 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
30650 /*! DIS_PRE - Disable Preamble
30651  *  0b0..Preamble enabled.
30652  *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
30653  */
30654 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
30655 
30656 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
30657 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
30658 /*! HOLDTIME - Hold time On MDIO Output
30659  *  0b000..1 internal module clock cycle
30660  *  0b001..2 internal module clock cycles
30661  *  0b010..3 internal module clock cycles
30662  *  0b111..8 internal module clock cycles
30663  */
30664 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
30665 /*! @} */
30666 
30667 /*! @name MIBC - MIB Control Register */
30668 /*! @{ */
30669 
30670 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
30671 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
30672 /*! MIB_CLEAR - MIB Clear
30673  *  0b0..See note above.
30674  *  0b1..All statistics counters are reset to 0.
30675  */
30676 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
30677 
30678 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
30679 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
30680 /*! MIB_IDLE - MIB Idle
30681  *  0b0..The MIB block is updating MIB counters.
30682  *  0b1..The MIB block is not currently updating any MIB counters.
30683  */
30684 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
30685 
30686 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
30687 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
30688 /*! MIB_DIS - Disable MIB Logic
30689  *  0b0..MIB logic is enabled.
30690  *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
30691  */
30692 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
30693 /*! @} */
30694 
30695 /*! @name RCR - Receive Control Register */
30696 /*! @{ */
30697 
30698 #define ENET_RCR_LOOP_MASK                       (0x1U)
30699 #define ENET_RCR_LOOP_SHIFT                      (0U)
30700 /*! LOOP - Internal Loopback
30701  *  0b0..Loopback disabled.
30702  *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
30703  */
30704 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
30705 
30706 #define ENET_RCR_DRT_MASK                        (0x2U)
30707 #define ENET_RCR_DRT_SHIFT                       (1U)
30708 /*! DRT - Disable Receive On Transmit
30709  *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
30710  *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
30711  */
30712 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
30713 
30714 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
30715 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
30716 /*! MII_MODE - Media Independent Interface Mode
30717  *  0b0..Reserved.
30718  *  0b1..RMII mode, as indicated by the RMII_MODE field.
30719  */
30720 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
30721 
30722 #define ENET_RCR_PROM_MASK                       (0x8U)
30723 #define ENET_RCR_PROM_SHIFT                      (3U)
30724 /*! PROM - Promiscuous Mode
30725  *  0b0..Disabled.
30726  *  0b1..Enabled.
30727  */
30728 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
30729 
30730 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
30731 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
30732 /*! BC_REJ - Broadcast Frame Reject */
30733 #define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
30734 
30735 #define ENET_RCR_FCE_MASK                        (0x20U)
30736 #define ENET_RCR_FCE_SHIFT                       (5U)
30737 /*! FCE - Flow Control Enable */
30738 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
30739 
30740 #define ENET_RCR_RGMII_EN_MASK                   (0x40U)
30741 #define ENET_RCR_RGMII_EN_SHIFT                  (6U)
30742 /*! RGMII_EN - RGMII Mode Enable
30743  *  0b0..MAC configured for non-RGMII operation
30744  *  0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
30745  *       ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
30746  */
30747 #define ENET_RCR_RGMII_EN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
30748 
30749 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
30750 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
30751 /*! RMII_MODE - RMII Mode Enable
30752  *  0b0..MAC configured for MII mode.
30753  *  0b1..MAC configured for RMII operation.
30754  */
30755 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
30756 
30757 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
30758 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
30759 /*! RMII_10T
30760  *  0b0..100-Mbit/s operation.
30761  *  0b1..10-Mbit/s operation.
30762  */
30763 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
30764 
30765 #define ENET_RCR_PADEN_MASK                      (0x1000U)
30766 #define ENET_RCR_PADEN_SHIFT                     (12U)
30767 /*! PADEN - Enable Frame Padding Remove On Receive
30768  *  0b0..No padding is removed on receive by the MAC.
30769  *  0b1..Padding is removed from received frames.
30770  */
30771 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
30772 
30773 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
30774 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
30775 /*! PAUFWD - Terminate/Forward Pause Frames
30776  *  0b0..Pause frames are terminated and discarded in the MAC.
30777  *  0b1..Pause frames are forwarded to the user application.
30778  */
30779 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
30780 
30781 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
30782 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
30783 /*! CRCFWD - Terminate/Forward Received CRC
30784  *  0b0..The CRC field of received frames is transmitted to the user application.
30785  *  0b1..The CRC field is stripped from the frame.
30786  */
30787 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
30788 
30789 #define ENET_RCR_CFEN_MASK                       (0x8000U)
30790 #define ENET_RCR_CFEN_SHIFT                      (15U)
30791 /*! CFEN - MAC Control Frame Enable
30792  *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
30793  *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
30794  */
30795 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
30796 
30797 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
30798 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
30799 /*! MAX_FL - Maximum Frame Length */
30800 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
30801 
30802 #define ENET_RCR_NLC_MASK                        (0x40000000U)
30803 #define ENET_RCR_NLC_SHIFT                       (30U)
30804 /*! NLC - Payload Length Check Disable
30805  *  0b0..The payload length check is disabled.
30806  *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
30807  */
30808 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
30809 
30810 #define ENET_RCR_GRS_MASK                        (0x80000000U)
30811 #define ENET_RCR_GRS_SHIFT                       (31U)
30812 /*! GRS - Graceful Receive Stopped */
30813 #define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
30814 /*! @} */
30815 
30816 /*! @name TCR - Transmit Control Register */
30817 /*! @{ */
30818 
30819 #define ENET_TCR_GTS_MASK                        (0x1U)
30820 #define ENET_TCR_GTS_SHIFT                       (0U)
30821 /*! GTS - Graceful Transmit Stop */
30822 #define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
30823 
30824 #define ENET_TCR_FDEN_MASK                       (0x4U)
30825 #define ENET_TCR_FDEN_SHIFT                      (2U)
30826 /*! FDEN - Full-Duplex Enable */
30827 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
30828 
30829 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
30830 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
30831 /*! TFC_PAUSE - Transmit Frame Control Pause
30832  *  0b0..No PAUSE frame transmitted.
30833  *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
30834  */
30835 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
30836 
30837 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
30838 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
30839 /*! RFC_PAUSE - Receive Frame Control Pause */
30840 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
30841 
30842 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
30843 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
30844 /*! ADDSEL - Source MAC Address Select On Transmit
30845  *  0b000..Node MAC address programmed on PADDR1/2 registers.
30846  *  0b100..Reserved.
30847  *  0b101..Reserved.
30848  *  0b110..Reserved.
30849  */
30850 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
30851 
30852 #define ENET_TCR_ADDINS_MASK                     (0x100U)
30853 #define ENET_TCR_ADDINS_SHIFT                    (8U)
30854 /*! ADDINS - Set MAC Address On Transmit
30855  *  0b0..The source MAC address is not modified by the MAC.
30856  *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
30857  */
30858 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
30859 
30860 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
30861 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
30862 /*! CRCFWD - Forward Frame From Application With CRC
30863  *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
30864  *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
30865  */
30866 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
30867 /*! @} */
30868 
30869 /*! @name PALR - Physical Address Lower Register */
30870 /*! @{ */
30871 
30872 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
30873 #define ENET_PALR_PADDR1_SHIFT                   (0U)
30874 /*! PADDR1 - Pause Address */
30875 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
30876 /*! @} */
30877 
30878 /*! @name PAUR - Physical Address Upper Register */
30879 /*! @{ */
30880 
30881 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
30882 #define ENET_PAUR_TYPE_SHIFT                     (0U)
30883 /*! TYPE - Type Field In PAUSE Frames */
30884 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
30885 
30886 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
30887 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
30888 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
30889 /*! @} */
30890 
30891 /*! @name OPD - Opcode/Pause Duration Register */
30892 /*! @{ */
30893 
30894 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
30895 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
30896 /*! PAUSE_DUR - Pause Duration */
30897 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
30898 
30899 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
30900 #define ENET_OPD_OPCODE_SHIFT                    (16U)
30901 /*! OPCODE - Opcode Field In PAUSE Frames */
30902 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
30903 /*! @} */
30904 
30905 /*! @name TXIC - Transmit Interrupt Coalescing Register */
30906 /*! @{ */
30907 
30908 #define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
30909 #define ENET_TXIC_ICTT_SHIFT                     (0U)
30910 /*! ICTT - Interrupt coalescing timer threshold */
30911 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
30912 
30913 #define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
30914 #define ENET_TXIC_ICFT_SHIFT                     (20U)
30915 /*! ICFT - Interrupt coalescing frame count threshold */
30916 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
30917 
30918 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
30919 #define ENET_TXIC_ICCS_SHIFT                     (30U)
30920 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
30921  *  0b0..Use GMII TX clocks.
30922  *  0b1..Use ENET system clock.
30923  */
30924 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
30925 
30926 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
30927 #define ENET_TXIC_ICEN_SHIFT                     (31U)
30928 /*! ICEN - Interrupt Coalescing Enable
30929  *  0b0..Disable Interrupt coalescing.
30930  *  0b1..Enable Interrupt coalescing.
30931  */
30932 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
30933 /*! @} */
30934 
30935 /* The count of ENET_TXIC */
30936 #define ENET_TXIC_COUNT                          (3U)
30937 
30938 /*! @name RXIC - Receive Interrupt Coalescing Register */
30939 /*! @{ */
30940 
30941 #define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
30942 #define ENET_RXIC_ICTT_SHIFT                     (0U)
30943 /*! ICTT - Interrupt coalescing timer threshold */
30944 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
30945 
30946 #define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
30947 #define ENET_RXIC_ICFT_SHIFT                     (20U)
30948 /*! ICFT - Interrupt coalescing frame count threshold */
30949 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
30950 
30951 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
30952 #define ENET_RXIC_ICCS_SHIFT                     (30U)
30953 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
30954  *  0b0..Use MII/GMII TX clocks.
30955  *  0b1..Use ENET system clock.
30956  */
30957 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
30958 
30959 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
30960 #define ENET_RXIC_ICEN_SHIFT                     (31U)
30961 /*! ICEN - Interrupt Coalescing Enable
30962  *  0b0..Disable Interrupt coalescing.
30963  *  0b1..Enable Interrupt coalescing.
30964  */
30965 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
30966 /*! @} */
30967 
30968 /* The count of ENET_RXIC */
30969 #define ENET_RXIC_COUNT                          (3U)
30970 
30971 /*! @name IAUR - Descriptor Individual Upper Address Register */
30972 /*! @{ */
30973 
30974 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
30975 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
30976 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
30977 /*! @} */
30978 
30979 /*! @name IALR - Descriptor Individual Lower Address Register */
30980 /*! @{ */
30981 
30982 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
30983 #define ENET_IALR_IADDR2_SHIFT                   (0U)
30984 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
30985 /*! @} */
30986 
30987 /*! @name GAUR - Descriptor Group Upper Address Register */
30988 /*! @{ */
30989 
30990 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
30991 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
30992 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
30993 /*! @} */
30994 
30995 /*! @name GALR - Descriptor Group Lower Address Register */
30996 /*! @{ */
30997 
30998 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
30999 #define ENET_GALR_GADDR2_SHIFT                   (0U)
31000 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
31001 /*! @} */
31002 
31003 /*! @name TFWR - Transmit FIFO Watermark Register */
31004 /*! @{ */
31005 
31006 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
31007 #define ENET_TFWR_TFWR_SHIFT                     (0U)
31008 /*! TFWR - Transmit FIFO Write
31009  *  0b000000..64 bytes written.
31010  *  0b000001..64 bytes written.
31011  *  0b000010..128 bytes written.
31012  *  0b000011..192 bytes written.
31013  *  0b111111..4032 bytes written.
31014  */
31015 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
31016 
31017 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
31018 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
31019 /*! STRFWD - Store And Forward Enable
31020  *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
31021  *  0b1..Enabled.
31022  */
31023 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
31024 /*! @} */
31025 
31026 /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
31027 /*! @{ */
31028 
31029 #define ENET_RDSR1_R_DES_START_MASK              (0xFFFFFFF8U)
31030 #define ENET_RDSR1_R_DES_START_SHIFT             (3U)
31031 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
31032 /*! @} */
31033 
31034 /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
31035 /*! @{ */
31036 
31037 #define ENET_TDSR1_X_DES_START_MASK              (0xFFFFFFF8U)
31038 #define ENET_TDSR1_X_DES_START_SHIFT             (3U)
31039 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
31040 /*! @} */
31041 
31042 /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
31043 /*! @{ */
31044 
31045 #define ENET_MRBR1_R_BUF_SIZE_MASK               (0x7F0U)
31046 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              (4U)
31047 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
31048 /*! @} */
31049 
31050 /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
31051 /*! @{ */
31052 
31053 #define ENET_RDSR2_R_DES_START_MASK              (0xFFFFFFF8U)
31054 #define ENET_RDSR2_R_DES_START_SHIFT             (3U)
31055 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
31056 /*! @} */
31057 
31058 /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
31059 /*! @{ */
31060 
31061 #define ENET_TDSR2_X_DES_START_MASK              (0xFFFFFFF8U)
31062 #define ENET_TDSR2_X_DES_START_SHIFT             (3U)
31063 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
31064 /*! @} */
31065 
31066 /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
31067 /*! @{ */
31068 
31069 #define ENET_MRBR2_R_BUF_SIZE_MASK               (0x7F0U)
31070 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              (4U)
31071 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
31072 /*! @} */
31073 
31074 /*! @name RDSR - Receive Descriptor Ring 0 Start Register */
31075 /*! @{ */
31076 
31077 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
31078 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
31079 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
31080 /*! @} */
31081 
31082 /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
31083 /*! @{ */
31084 
31085 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
31086 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
31087 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
31088 /*! @} */
31089 
31090 /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
31091 /*! @{ */
31092 
31093 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x7F0U)
31094 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
31095 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
31096 /*! @} */
31097 
31098 /*! @name RSFL - Receive FIFO Section Full Threshold */
31099 /*! @{ */
31100 
31101 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0x3FFU)
31102 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
31103 /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */
31104 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
31105 /*! @} */
31106 
31107 /*! @name RSEM - Receive FIFO Section Empty Threshold */
31108 /*! @{ */
31109 
31110 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0x3FFU)
31111 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
31112 /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */
31113 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
31114 
31115 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
31116 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
31117 /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */
31118 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
31119 /*! @} */
31120 
31121 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
31122 /*! @{ */
31123 
31124 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0x3FFU)
31125 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
31126 /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */
31127 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
31128 /*! @} */
31129 
31130 /*! @name RAFL - Receive FIFO Almost Full Threshold */
31131 /*! @{ */
31132 
31133 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0x3FFU)
31134 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
31135 /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */
31136 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
31137 /*! @} */
31138 
31139 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
31140 /*! @{ */
31141 
31142 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0x3FFU)
31143 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
31144 /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */
31145 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
31146 /*! @} */
31147 
31148 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
31149 /*! @{ */
31150 
31151 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0x3FFU)
31152 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
31153 /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */
31154 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
31155 /*! @} */
31156 
31157 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
31158 /*! @{ */
31159 
31160 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0x3FFU)
31161 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
31162 /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */
31163 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
31164 /*! @} */
31165 
31166 /*! @name TIPG - Transmit Inter-Packet Gap */
31167 /*! @{ */
31168 
31169 #define ENET_TIPG_IPG_MASK                       (0x1FU)
31170 #define ENET_TIPG_IPG_SHIFT                      (0U)
31171 /*! IPG - Transmit Inter-Packet Gap */
31172 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
31173 /*! @} */
31174 
31175 /*! @name FTRL - Frame Truncation Length */
31176 /*! @{ */
31177 
31178 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
31179 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
31180 /*! TRUNC_FL - Frame Truncation Length */
31181 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
31182 /*! @} */
31183 
31184 /*! @name TACC - Transmit Accelerator Function Configuration */
31185 /*! @{ */
31186 
31187 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
31188 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
31189 /*! SHIFT16 - TX FIFO Shift-16
31190  *  0b0..Disabled.
31191  *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
31192  *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
31193  *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
31194  *       extended to a 16-byte header.
31195  */
31196 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
31197 
31198 #define ENET_TACC_IPCHK_MASK                     (0x8U)
31199 #define ENET_TACC_IPCHK_SHIFT                    (3U)
31200 /*! IPCHK
31201  *  0b0..Checksum is not inserted.
31202  *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
31203  *       be cleared. If a non-IP frame is transmitted the frame is not modified.
31204  */
31205 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
31206 
31207 #define ENET_TACC_PROCHK_MASK                    (0x10U)
31208 #define ENET_TACC_PROCHK_SHIFT                   (4U)
31209 /*! PROCHK
31210  *  0b0..Checksum not inserted.
31211  *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
31212  *       frame. The checksum field must be cleared. The other frames are not modified.
31213  */
31214 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
31215 /*! @} */
31216 
31217 /*! @name RACC - Receive Accelerator Function Configuration */
31218 /*! @{ */
31219 
31220 #define ENET_RACC_PADREM_MASK                    (0x1U)
31221 #define ENET_RACC_PADREM_SHIFT                   (0U)
31222 /*! PADREM - Enable Padding Removal For Short IP Frames
31223  *  0b0..Padding not removed.
31224  *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
31225  */
31226 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
31227 
31228 #define ENET_RACC_IPDIS_MASK                     (0x2U)
31229 #define ENET_RACC_IPDIS_SHIFT                    (1U)
31230 /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
31231  *  0b0..Frames with wrong IPv4 header checksum are not discarded.
31232  *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
31233  *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
31234  *       store and forward mode (RSFL cleared).
31235  */
31236 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
31237 
31238 #define ENET_RACC_PRODIS_MASK                    (0x4U)
31239 #define ENET_RACC_PRODIS_SHIFT                   (2U)
31240 /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
31241  *  0b0..Frames with wrong checksum are not discarded.
31242  *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
31243  *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
31244  *       cleared).
31245  */
31246 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
31247 
31248 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
31249 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
31250 /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
31251  *  0b0..Frames with errors are not discarded.
31252  *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
31253  */
31254 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
31255 
31256 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
31257 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
31258 /*! SHIFT16 - RX FIFO Shift-16
31259  *  0b0..Disabled.
31260  *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
31261  */
31262 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
31263 /*! @} */
31264 
31265 /*! @name RCMR - Receive Classification Match Register for Class n */
31266 /*! @{ */
31267 
31268 #define ENET_RCMR_CMP0_MASK                      (0x7U)
31269 #define ENET_RCMR_CMP0_SHIFT                     (0U)
31270 /*! CMP0 - Compare 0 */
31271 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
31272 
31273 #define ENET_RCMR_CMP1_MASK                      (0x70U)
31274 #define ENET_RCMR_CMP1_SHIFT                     (4U)
31275 /*! CMP1 - Compare 1 */
31276 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
31277 
31278 #define ENET_RCMR_CMP2_MASK                      (0x700U)
31279 #define ENET_RCMR_CMP2_SHIFT                     (8U)
31280 /*! CMP2 - Compare 2 */
31281 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
31282 
31283 #define ENET_RCMR_CMP3_MASK                      (0x7000U)
31284 #define ENET_RCMR_CMP3_SHIFT                     (12U)
31285 /*! CMP3 - Compare 3 */
31286 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
31287 
31288 #define ENET_RCMR_MATCHEN_MASK                   (0x10000U)
31289 #define ENET_RCMR_MATCHEN_SHIFT                  (16U)
31290 /*! MATCHEN - Match Enable
31291  *  0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
31292  *  0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
31293  */
31294 #define ENET_RCMR_MATCHEN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
31295 /*! @} */
31296 
31297 /* The count of ENET_RCMR */
31298 #define ENET_RCMR_COUNT                          (2U)
31299 
31300 /*! @name DMACFG - DMA Class Based Configuration */
31301 /*! @{ */
31302 
31303 #define ENET_DMACFG_IDLE_SLOPE_MASK              (0xFFFFU)
31304 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             (0U)
31305 /*! IDLE_SLOPE - Idle slope */
31306 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
31307 
31308 #define ENET_DMACFG_DMA_CLASS_EN_MASK            (0x10000U)
31309 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           (16U)
31310 /*! DMA_CLASS_EN - DMA class enable
31311  *  0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
31312  *       requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
31313  *       queues are disabled then their frames will be placed in queue 0.
31314  *  0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
31315  */
31316 #define ENET_DMACFG_DMA_CLASS_EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
31317 
31318 #define ENET_DMACFG_CALC_NOIPG_MASK              (0x20000U)
31319 #define ENET_DMACFG_CALC_NOIPG_SHIFT             (17U)
31320 /*! CALC_NOIPG - Calculate no IPG
31321  *  0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
31322  *       for a frame when doing bandwidth calculations. This is the default.
31323  *  0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
31324  *       when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
31325  *       frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
31326  *       will become more bandwidth than large frames due to the relation of data to IPG overhead).
31327  */
31328 #define ENET_DMACFG_CALC_NOIPG(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
31329 /*! @} */
31330 
31331 /* The count of ENET_DMACFG */
31332 #define ENET_DMACFG_COUNT                        (2U)
31333 
31334 /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
31335 /*! @{ */
31336 
31337 #define ENET_RDAR1_RDAR_MASK                     (0x1000000U)
31338 #define ENET_RDAR1_RDAR_SHIFT                    (24U)
31339 /*! RDAR - Receive Descriptor Active */
31340 #define ENET_RDAR1_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
31341 /*! @} */
31342 
31343 /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
31344 /*! @{ */
31345 
31346 #define ENET_TDAR1_TDAR_MASK                     (0x1000000U)
31347 #define ENET_TDAR1_TDAR_SHIFT                    (24U)
31348 /*! TDAR - Transmit Descriptor Active */
31349 #define ENET_TDAR1_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
31350 /*! @} */
31351 
31352 /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
31353 /*! @{ */
31354 
31355 #define ENET_RDAR2_RDAR_MASK                     (0x1000000U)
31356 #define ENET_RDAR2_RDAR_SHIFT                    (24U)
31357 /*! RDAR - Receive Descriptor Active */
31358 #define ENET_RDAR2_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
31359 /*! @} */
31360 
31361 /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
31362 /*! @{ */
31363 
31364 #define ENET_TDAR2_TDAR_MASK                     (0x1000000U)
31365 #define ENET_TDAR2_TDAR_SHIFT                    (24U)
31366 /*! TDAR - Transmit Descriptor Active */
31367 #define ENET_TDAR2_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
31368 /*! @} */
31369 
31370 /*! @name QOS - QOS Scheme */
31371 /*! @{ */
31372 
31373 #define ENET_QOS_TX_SCHEME_MASK                  (0x7U)
31374 #define ENET_QOS_TX_SCHEME_SHIFT                 (0U)
31375 /*! TX_SCHEME - TX scheme configuration
31376  *  0b000..Credit-based scheme
31377  *  0b001..Round-robin scheme
31378  *  0b010-0b111..Reserved
31379  */
31380 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
31381 
31382 #define ENET_QOS_RX_FLUSH0_MASK                  (0x8U)
31383 #define ENET_QOS_RX_FLUSH0_SHIFT                 (3U)
31384 /*! RX_FLUSH0 - RX Flush Ring 0
31385  *  0b0..Disable
31386  *  0b1..Enable
31387  */
31388 #define ENET_QOS_RX_FLUSH0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
31389 
31390 #define ENET_QOS_RX_FLUSH1_MASK                  (0x10U)
31391 #define ENET_QOS_RX_FLUSH1_SHIFT                 (4U)
31392 /*! RX_FLUSH1 - RX Flush Ring 1
31393  *  0b0..Disable
31394  *  0b1..Enable
31395  */
31396 #define ENET_QOS_RX_FLUSH1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
31397 
31398 #define ENET_QOS_RX_FLUSH2_MASK                  (0x20U)
31399 #define ENET_QOS_RX_FLUSH2_SHIFT                 (5U)
31400 /*! RX_FLUSH2 - RX Flush Ring 2
31401  *  0b0..Disable
31402  *  0b1..Enable
31403  */
31404 #define ENET_QOS_RX_FLUSH2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
31405 /*! @} */
31406 
31407 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
31408 /*! @{ */
31409 
31410 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
31411 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
31412 /*! TXPKTS - Packet count */
31413 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
31414 /*! @} */
31415 
31416 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
31417 /*! @{ */
31418 
31419 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
31420 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
31421 /*! TXPKTS - Broadcast packets */
31422 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
31423 /*! @} */
31424 
31425 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
31426 /*! @{ */
31427 
31428 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
31429 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
31430 /*! TXPKTS - Multicast packets */
31431 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
31432 /*! @} */
31433 
31434 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
31435 /*! @{ */
31436 
31437 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
31438 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
31439 /*! TXPKTS - Packets with CRC/align error */
31440 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
31441 /*! @} */
31442 
31443 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
31444 /*! @{ */
31445 
31446 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
31447 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
31448 /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */
31449 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
31450 /*! @} */
31451 
31452 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
31453 /*! @{ */
31454 
31455 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
31456 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
31457 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */
31458 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
31459 /*! @} */
31460 
31461 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
31462 /*! @{ */
31463 
31464 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
31465 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
31466 /*! TXPKTS - Number of packets less than 64 bytes with bad CRC */
31467 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
31468 /*! @} */
31469 
31470 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
31471 /*! @{ */
31472 
31473 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
31474 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
31475 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */
31476 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
31477 /*! @} */
31478 
31479 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
31480 /*! @{ */
31481 
31482 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
31483 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
31484 /*! TXPKTS - Number of transmit collisions */
31485 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
31486 /*! @} */
31487 
31488 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
31489 /*! @{ */
31490 
31491 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
31492 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
31493 /*! TXPKTS - Number of 64-byte transmit packets */
31494 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
31495 /*! @} */
31496 
31497 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
31498 /*! @{ */
31499 
31500 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
31501 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
31502 /*! TXPKTS - Number of 65- to 127-byte transmit packets */
31503 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
31504 /*! @} */
31505 
31506 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
31507 /*! @{ */
31508 
31509 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
31510 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
31511 /*! TXPKTS - Number of 128- to 255-byte transmit packets */
31512 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
31513 /*! @} */
31514 
31515 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
31516 /*! @{ */
31517 
31518 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
31519 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
31520 /*! TXPKTS - Number of 256- to 511-byte transmit packets */
31521 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
31522 /*! @} */
31523 
31524 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
31525 /*! @{ */
31526 
31527 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
31528 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
31529 /*! TXPKTS - Number of 512- to 1023-byte transmit packets */
31530 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
31531 /*! @} */
31532 
31533 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
31534 /*! @{ */
31535 
31536 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
31537 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
31538 /*! TXPKTS - Number of 1024- to 2047-byte transmit packets */
31539 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
31540 /*! @} */
31541 
31542 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
31543 /*! @{ */
31544 
31545 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
31546 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
31547 /*! TXPKTS - Number of transmit packets greater than 2048 bytes */
31548 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
31549 /*! @} */
31550 
31551 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
31552 /*! @{ */
31553 
31554 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
31555 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
31556 /*! TXOCTS - Number of transmit octets */
31557 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
31558 /*! @} */
31559 
31560 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
31561 /*! @{ */
31562 
31563 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
31564 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
31565 /*! COUNT - Number of frames transmitted OK */
31566 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
31567 /*! @} */
31568 
31569 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
31570 /*! @{ */
31571 
31572 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
31573 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
31574 /*! COUNT - Number of frames transmitted with one collision */
31575 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
31576 /*! @} */
31577 
31578 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
31579 /*! @{ */
31580 
31581 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
31582 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
31583 /*! COUNT - Number of frames transmitted with multiple collisions */
31584 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
31585 /*! @} */
31586 
31587 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
31588 /*! @{ */
31589 
31590 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
31591 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
31592 /*! COUNT - Number of frames transmitted with deferral delay */
31593 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
31594 /*! @} */
31595 
31596 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
31597 /*! @{ */
31598 
31599 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
31600 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
31601 /*! COUNT - Number of frames transmitted with late collision */
31602 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
31603 /*! @} */
31604 
31605 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
31606 /*! @{ */
31607 
31608 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
31609 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
31610 /*! COUNT - Number of frames transmitted with excessive collisions */
31611 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
31612 /*! @} */
31613 
31614 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
31615 /*! @{ */
31616 
31617 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
31618 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
31619 /*! COUNT - Number of frames transmitted with transmit FIFO underrun */
31620 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
31621 /*! @} */
31622 
31623 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
31624 /*! @{ */
31625 
31626 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
31627 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
31628 /*! COUNT - Number of frames transmitted with carrier sense error */
31629 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
31630 /*! @} */
31631 
31632 /*! @name IEEE_T_SQE - Reserved Statistic Register */
31633 /*! @{ */
31634 
31635 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
31636 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
31637 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
31638 /*! @} */
31639 
31640 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
31641 /*! @{ */
31642 
31643 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
31644 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
31645 /*! COUNT - Number of flow-control pause frames transmitted */
31646 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
31647 /*! @} */
31648 
31649 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
31650 /*! @{ */
31651 
31652 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
31653 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
31654 /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */
31655 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
31656 /*! @} */
31657 
31658 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
31659 /*! @{ */
31660 
31661 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
31662 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
31663 /*! COUNT - Number of packets received */
31664 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
31665 /*! @} */
31666 
31667 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
31668 /*! @{ */
31669 
31670 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
31671 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
31672 /*! COUNT - Number of receive broadcast packets */
31673 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
31674 /*! @} */
31675 
31676 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
31677 /*! @{ */
31678 
31679 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
31680 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
31681 /*! COUNT - Number of receive multicast packets */
31682 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
31683 /*! @} */
31684 
31685 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
31686 /*! @{ */
31687 
31688 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
31689 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
31690 /*! COUNT - Number of receive packets with CRC or align error */
31691 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
31692 /*! @} */
31693 
31694 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
31695 /*! @{ */
31696 
31697 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
31698 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
31699 /*! COUNT - Number of receive packets with less than 64 bytes and good CRC */
31700 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
31701 /*! @} */
31702 
31703 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
31704 /*! @{ */
31705 
31706 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
31707 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
31708 /*! COUNT - Number of receive packets greater than MAX_FL and good CRC */
31709 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
31710 /*! @} */
31711 
31712 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
31713 /*! @{ */
31714 
31715 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
31716 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
31717 /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */
31718 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
31719 /*! @} */
31720 
31721 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
31722 /*! @{ */
31723 
31724 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
31725 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
31726 /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */
31727 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
31728 /*! @} */
31729 
31730 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
31731 /*! @{ */
31732 
31733 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
31734 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
31735 /*! COUNT - Number of 64-byte receive packets */
31736 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
31737 /*! @} */
31738 
31739 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
31740 /*! @{ */
31741 
31742 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
31743 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
31744 /*! COUNT - Number of 65- to 127-byte recieve packets */
31745 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
31746 /*! @} */
31747 
31748 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
31749 /*! @{ */
31750 
31751 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
31752 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
31753 /*! COUNT - Number of 128- to 255-byte recieve packets */
31754 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
31755 /*! @} */
31756 
31757 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
31758 /*! @{ */
31759 
31760 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
31761 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
31762 /*! COUNT - Number of 256- to 511-byte recieve packets */
31763 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
31764 /*! @} */
31765 
31766 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
31767 /*! @{ */
31768 
31769 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
31770 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
31771 /*! COUNT - Number of 512- to 1023-byte recieve packets */
31772 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
31773 /*! @} */
31774 
31775 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
31776 /*! @{ */
31777 
31778 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
31779 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
31780 /*! COUNT - Number of 1024- to 2047-byte recieve packets */
31781 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
31782 /*! @} */
31783 
31784 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
31785 /*! @{ */
31786 
31787 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
31788 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
31789 /*! COUNT - Number of greater-than-2048-byte recieve packets */
31790 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
31791 /*! @} */
31792 
31793 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
31794 /*! @{ */
31795 
31796 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
31797 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
31798 /*! COUNT - Number of receive octets */
31799 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
31800 /*! @} */
31801 
31802 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
31803 /*! @{ */
31804 
31805 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
31806 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
31807 /*! COUNT - Frame count */
31808 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
31809 /*! @} */
31810 
31811 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
31812 /*! @{ */
31813 
31814 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
31815 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
31816 /*! COUNT - Number of frames received OK */
31817 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
31818 /*! @} */
31819 
31820 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
31821 /*! @{ */
31822 
31823 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
31824 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
31825 /*! COUNT - Number of frames received with CRC error */
31826 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
31827 /*! @} */
31828 
31829 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
31830 /*! @{ */
31831 
31832 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
31833 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
31834 /*! COUNT - Number of frames received with alignment error */
31835 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
31836 /*! @} */
31837 
31838 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
31839 /*! @{ */
31840 
31841 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
31842 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
31843 /*! COUNT - Receive FIFO overflow count */
31844 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
31845 /*! @} */
31846 
31847 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
31848 /*! @{ */
31849 
31850 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
31851 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
31852 /*! COUNT - Number of flow-control pause frames received */
31853 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
31854 /*! @} */
31855 
31856 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
31857 /*! @{ */
31858 
31859 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
31860 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
31861 /*! COUNT - Number of octets for frames received without error */
31862 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
31863 /*! @} */
31864 
31865 /*! @name ATCR - Adjustable Timer Control Register */
31866 /*! @{ */
31867 
31868 #define ENET_ATCR_EN_MASK                        (0x1U)
31869 #define ENET_ATCR_EN_SHIFT                       (0U)
31870 /*! EN - Enable Timer
31871  *  0b0..The timer stops at the current value.
31872  *  0b1..The timer starts incrementing.
31873  */
31874 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
31875 
31876 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
31877 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
31878 /*! OFFEN - Enable One-Shot Offset Event
31879  *  0b0..Disable.
31880  *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
31881  *       when the offset event is reached, so no further event occurs until the field is set again. The timer
31882  *       offset value must be set before setting this field.
31883  */
31884 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
31885 
31886 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
31887 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
31888 /*! OFFRST - Reset Timer On Offset Event
31889  *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
31890  *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
31891  */
31892 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
31893 
31894 #define ENET_ATCR_PEREN_MASK                     (0x10U)
31895 #define ENET_ATCR_PEREN_SHIFT                    (4U)
31896 /*! PEREN - Enable Periodical Event
31897  *  0b0..Disable.
31898  *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
31899  *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
31900  *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
31901  */
31902 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
31903 
31904 #define ENET_ATCR_PINPER_MASK                    (0x80U)
31905 #define ENET_ATCR_PINPER_SHIFT                   (7U)
31906 /*! PINPER
31907  *  0b0..Disable.
31908  *  0b1..Enable.
31909  */
31910 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
31911 
31912 #define ENET_ATCR_RESTART_MASK                   (0x200U)
31913 #define ENET_ATCR_RESTART_SHIFT                  (9U)
31914 /*! RESTART - Reset Timer */
31915 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
31916 
31917 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
31918 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
31919 /*! CAPTURE - Capture Timer Value
31920  *  0b0..No effect.
31921  *  0b1..The current time is captured and can be read from the ATVR register.
31922  */
31923 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
31924 
31925 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
31926 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
31927 /*! SLAVE - Enable Timer Slave Mode
31928  *  0b0..The timer is active and all configuration fields in this register are relevant.
31929  *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
31930  *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
31931  */
31932 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
31933 /*! @} */
31934 
31935 /*! @name ATVR - Timer Value Register */
31936 /*! @{ */
31937 
31938 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
31939 #define ENET_ATVR_ATIME_SHIFT                    (0U)
31940 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
31941 /*! @} */
31942 
31943 /*! @name ATOFF - Timer Offset Register */
31944 /*! @{ */
31945 
31946 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
31947 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
31948 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
31949 /*! @} */
31950 
31951 /*! @name ATPER - Timer Period Register */
31952 /*! @{ */
31953 
31954 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
31955 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
31956 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
31957 /*! @} */
31958 
31959 /*! @name ATCOR - Timer Correction Register */
31960 /*! @{ */
31961 
31962 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
31963 #define ENET_ATCOR_COR_SHIFT                     (0U)
31964 /*! COR - Correction Counter Wrap-Around Value */
31965 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
31966 /*! @} */
31967 
31968 /*! @name ATINC - Time-Stamping Clock Period Register */
31969 /*! @{ */
31970 
31971 #define ENET_ATINC_INC_MASK                      (0x7FU)
31972 #define ENET_ATINC_INC_SHIFT                     (0U)
31973 /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */
31974 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
31975 
31976 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
31977 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
31978 /*! INC_CORR - Correction Increment Value */
31979 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
31980 /*! @} */
31981 
31982 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
31983 /*! @{ */
31984 
31985 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
31986 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
31987 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
31988 /*! @} */
31989 
31990 /*! @name TGSR - Timer Global Status Register */
31991 /*! @{ */
31992 
31993 #define ENET_TGSR_TF0_MASK                       (0x1U)
31994 #define ENET_TGSR_TF0_SHIFT                      (0U)
31995 /*! TF0 - Copy Of Timer Flag For Channel 0
31996  *  0b0..Timer Flag for Channel 0 is clear
31997  *  0b1..Timer Flag for Channel 0 is set
31998  */
31999 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
32000 
32001 #define ENET_TGSR_TF1_MASK                       (0x2U)
32002 #define ENET_TGSR_TF1_SHIFT                      (1U)
32003 /*! TF1 - Copy Of Timer Flag For Channel 1
32004  *  0b0..Timer Flag for Channel 1 is clear
32005  *  0b1..Timer Flag for Channel 1 is set
32006  */
32007 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
32008 
32009 #define ENET_TGSR_TF2_MASK                       (0x4U)
32010 #define ENET_TGSR_TF2_SHIFT                      (2U)
32011 /*! TF2 - Copy Of Timer Flag For Channel 2
32012  *  0b0..Timer Flag for Channel 2 is clear
32013  *  0b1..Timer Flag for Channel 2 is set
32014  */
32015 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
32016 
32017 #define ENET_TGSR_TF3_MASK                       (0x8U)
32018 #define ENET_TGSR_TF3_SHIFT                      (3U)
32019 /*! TF3 - Copy Of Timer Flag For Channel 3
32020  *  0b0..Timer Flag for Channel 3 is clear
32021  *  0b1..Timer Flag for Channel 3 is set
32022  */
32023 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
32024 /*! @} */
32025 
32026 /*! @name TCSR - Timer Control Status Register */
32027 /*! @{ */
32028 
32029 #define ENET_TCSR_TDRE_MASK                      (0x1U)
32030 #define ENET_TCSR_TDRE_SHIFT                     (0U)
32031 /*! TDRE - Timer DMA Request Enable
32032  *  0b0..DMA request is disabled
32033  *  0b1..DMA request is enabled
32034  */
32035 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
32036 
32037 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
32038 #define ENET_TCSR_TMODE_SHIFT                    (2U)
32039 /*! TMODE - Timer Mode
32040  *  0b0000..Timer Channel is disabled.
32041  *  0b0001..Timer Channel is configured for Input Capture on rising edge.
32042  *  0b0010..Timer Channel is configured for Input Capture on falling edge.
32043  *  0b0011..Timer Channel is configured for Input Capture on both edges.
32044  *  0b0100..Timer Channel is configured for Output Compare - software only.
32045  *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
32046  *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
32047  *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
32048  *  0b1000..Reserved
32049  *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
32050  *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
32051  *  0b110x..Reserved
32052  *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle.
32053  *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
32054  */
32055 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
32056 
32057 #define ENET_TCSR_TIE_MASK                       (0x40U)
32058 #define ENET_TCSR_TIE_SHIFT                      (6U)
32059 /*! TIE - Timer Interrupt Enable
32060  *  0b0..Interrupt is disabled
32061  *  0b1..Interrupt is enabled
32062  */
32063 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
32064 
32065 #define ENET_TCSR_TF_MASK                        (0x80U)
32066 #define ENET_TCSR_TF_SHIFT                       (7U)
32067 /*! TF - Timer Flag
32068  *  0b0..Input Capture or Output Compare has not occurred.
32069  *  0b1..Input Capture or Output Compare has occurred.
32070  */
32071 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
32072 /*! @} */
32073 
32074 /* The count of ENET_TCSR */
32075 #define ENET_TCSR_COUNT                          (4U)
32076 
32077 /*! @name TCCR - Timer Compare Capture Register */
32078 /*! @{ */
32079 
32080 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
32081 #define ENET_TCCR_TCC_SHIFT                      (0U)
32082 /*! TCC - Timer Capture Compare */
32083 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
32084 /*! @} */
32085 
32086 /* The count of ENET_TCCR */
32087 #define ENET_TCCR_COUNT                          (4U)
32088 
32089 
32090 /*!
32091  * @}
32092  */ /* end of group ENET_Register_Masks */
32093 
32094 
32095 /* ENET - Peripheral instance base addresses */
32096 /** Peripheral ENET1 base address */
32097 #define ENET1_BASE                               (0x30BE0000u)
32098 /** Peripheral ENET1 base pointer */
32099 #define ENET1                                    ((ENET_Type *)ENET1_BASE)
32100 /** Array initializer of ENET peripheral base addresses */
32101 #define ENET_BASE_ADDRS                          { ENET1_BASE }
32102 /** Array initializer of ENET peripheral base pointers */
32103 #define ENET_BASE_PTRS                           { ENET1 }
32104 /** Interrupt vectors for the ENET peripheral type */
32105 #define ENET_Transmit_IRQS                       { ENET1_IRQn }
32106 #define ENET_Receive_IRQS                        { ENET1_IRQn }
32107 #define ENET_Error_IRQS                          { ENET1_IRQn }
32108 #define ENET_1588_Timer_IRQS                     { ENET1_1588_Timer_IRQn }
32109 #define ENET_Ts_IRQS                             { ENET1_1588_Timer_IRQn }
32110 /* ENET Buffer Descriptor and Buffer Address Alignment. */
32111 #define ENET_BUFF_ALIGNMENT                      (64U)
32112 
32113 
32114 /*!
32115  * @}
32116  */ /* end of group ENET_Peripheral_Access_Layer */
32117 
32118 
32119 /* ----------------------------------------------------------------------------
32120    -- ENET_QOS Peripheral Access Layer
32121    ---------------------------------------------------------------------------- */
32122 
32123 /*!
32124  * @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer
32125  * @{
32126  */
32127 
32128 /** ENET_QOS - Register Layout Typedef */
32129 typedef struct {
32130   __IO uint32_t MAC_CONFIGURATION;                 /**< MAC Configuration Register, offset: 0x0 */
32131   __IO uint32_t MAC_EXT_CONFIGURATION;             /**< MAC Extended Configuration Register, offset: 0x4 */
32132   __IO uint32_t MAC_PACKET_FILTER;                 /**< MAC Packet Filter, offset: 0x8 */
32133   __IO uint32_t MAC_WATCHDOG_TIMEOUT;              /**< Watchdog Timeout, offset: 0xC */
32134   __IO uint32_t MAC_HASH_TABLE_REG0;               /**< MAC Hash Table Register 0, offset: 0x10 */
32135   __IO uint32_t MAC_HASH_TABLE_REG1;               /**< MAC Hash Table Register 1, offset: 0x14 */
32136        uint8_t RESERVED_0[56];
32137   __IO uint32_t MAC_VLAN_TAG_CTRL;                 /**< MAC VLAN Tag Control, offset: 0x50 */
32138   __IO uint32_t MAC_VLAN_TAG_DATA;                 /**< MAC VLAN Tag Data, offset: 0x54 */
32139   __IO uint32_t MAC_VLAN_HASH_TABLE;               /**< MAC VLAN Hash Table, offset: 0x58 */
32140        uint8_t RESERVED_1[4];
32141   __IO uint32_t MAC_VLAN_INCL;                     /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
32142   __IO uint32_t MAC_INNER_VLAN_INCL;               /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
32143        uint8_t RESERVED_2[8];
32144   __IO uint32_t MAC_TX_FLOW_CTRL_Q[5];             /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */
32145        uint8_t RESERVED_3[12];
32146   __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< MAC Rx Flow Control, offset: 0x90 */
32147   __IO uint32_t MAC_RXQ_CTRL4;                     /**< Receive Queue Control 4, offset: 0x94 */
32148   __IO uint32_t MAC_TXQ_PRTY_MAP0;                 /**< Transmit Queue Priority Mapping 0, offset: 0x98 */
32149   __IO uint32_t MAC_TXQ_PRTY_MAP1;                 /**< Transmit Queue Priority Mapping 1, offset: 0x9C */
32150   __IO uint32_t MAC_RXQ_CTRL[4];                   /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */
32151   __I  uint32_t MAC_INTERRUPT_STATUS;              /**< Interrupt Status, offset: 0xB0 */
32152   __IO uint32_t MAC_INTERRUPT_ENABLE;              /**< Interrupt Enable, offset: 0xB4 */
32153   __I  uint32_t MAC_RX_TX_STATUS;                  /**< Receive Transmit Status, offset: 0xB8 */
32154        uint8_t RESERVED_4[4];
32155   __IO uint32_t MAC_PMT_CONTROL_STATUS;            /**< PMT Control and Status, offset: 0xC0 */
32156   __IO uint32_t MAC_RWK_PACKET_FILTER;             /**< Remote Wakeup Filter, offset: 0xC4 */
32157        uint8_t RESERVED_5[8];
32158   __IO uint32_t MAC_LPI_CONTROL_STATUS;            /**< LPI Control and Status, offset: 0xD0 */
32159   __IO uint32_t MAC_LPI_TIMERS_CONTROL;            /**< LPI Timers Control, offset: 0xD4 */
32160   __IO uint32_t MAC_LPI_ENTRY_TIMER;               /**< Tx LPI Entry Timer Control, offset: 0xD8 */
32161   __IO uint32_t MAC_ONEUS_TIC_COUNTER;             /**< One-microsecond Reference Timer, offset: 0xDC */
32162        uint8_t RESERVED_6[24];
32163   __IO uint32_t MAC_PHYIF_CONTROL_STATUS;          /**< PHY Interface Control and Status, offset: 0xF8 */
32164        uint8_t RESERVED_7[20];
32165   __I  uint32_t MAC_VERSION;                       /**< MAC Version, offset: 0x110 */
32166   __I  uint32_t MAC_DEBUG;                         /**< MAC Debug, offset: 0x114 */
32167        uint8_t RESERVED_8[4];
32168   __I  uint32_t MAC_HW_FEAT[4];                    /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */
32169        uint8_t RESERVED_9[212];
32170   __IO uint32_t MAC_MDIO_ADDRESS;                  /**< MDIO Address, offset: 0x200 */
32171   __IO uint32_t MAC_MDIO_DATA;                     /**< MAC MDIO Data, offset: 0x204 */
32172        uint8_t RESERVED_10[40];
32173   __IO uint32_t MAC_CSR_SW_CTRL;                   /**< CSR Software Control, offset: 0x230 */
32174   __IO uint32_t MAC_FPE_CTRL_STS;                  /**< Frame Preemption Control, offset: 0x234 */
32175        uint8_t RESERVED_11[8];
32176   __I  uint32_t MAC_PRESN_TIME_NS;                 /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */
32177   __IO uint32_t MAC_PRESN_TIME_UPDT;               /**< MAC 1722 Presentation Time, offset: 0x244 */
32178        uint8_t RESERVED_12[184];
32179   struct {                                         /* offset: 0x300, array step: 0x8 */
32180     __IO uint32_t HIGH;                              /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */
32181     __IO uint32_t LOW;                               /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */
32182   } MAC_ADDRESS[64];
32183        uint8_t RESERVED_13[512];
32184   __IO uint32_t MAC_MMC_CONTROL;                   /**< MMC Control, offset: 0x700 */
32185   __I  uint32_t MAC_MMC_RX_INTERRUPT;              /**< MMC Rx Interrupt, offset: 0x704 */
32186   __I  uint32_t MAC_MMC_TX_INTERRUPT;              /**< MMC Tx Interrupt, offset: 0x708 */
32187   __IO uint32_t MAC_MMC_RX_INTERRUPT_MASK;         /**< MMC Rx Interrupt Mask, offset: 0x70C */
32188   __IO uint32_t MAC_MMC_TX_INTERRUPT_MASK;         /**< MMC Tx Interrupt Mask, offset: 0x710 */
32189   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD;       /**< Tx Octet Count Good and Bad, offset: 0x714 */
32190   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD;      /**< Tx Packet Count Good and Bad, offset: 0x718 */
32191   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD;     /**< Tx Broadcast Packets Good, offset: 0x71C */
32192   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD;     /**< Tx Multicast Packets Good, offset: 0x720 */
32193   __I  uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD;  /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */
32194   __I  uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */
32195   __I  uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */
32196   __I  uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */
32197   __I  uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */
32198   __I  uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */
32199   __I  uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD;   /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */
32200   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */
32201   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */
32202   __I  uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS;    /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */
32203   __I  uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */
32204   __I  uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */
32205   __I  uint32_t MAC_TX_DEFERRED_PACKETS;           /**< Deferred Packets Transmitted, offset: 0x754 */
32206   __I  uint32_t MAC_TX_LATE_COLLISION_PACKETS;     /**< Late Collision Packets Transmitted, offset: 0x758 */
32207   __I  uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */
32208   __I  uint32_t MAC_TX_CARRIER_ERROR_PACKETS;      /**< Carrier Error Packets Transmitted, offset: 0x760 */
32209   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD;           /**< Bytes Transmitted in Good Packets, offset: 0x764 */
32210   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD;          /**< Good Packets Transmitted, offset: 0x768 */
32211   __I  uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR;   /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */
32212   __I  uint32_t MAC_TX_PAUSE_PACKETS;              /**< Pause Packets Transmitted, offset: 0x770 */
32213   __I  uint32_t MAC_TX_VLAN_PACKETS_GOOD;          /**< Good VLAN Packets Transmitted, offset: 0x774 */
32214   __I  uint32_t MAC_TX_OSIZE_PACKETS_GOOD;         /**< Good Oversize Packets Transmitted, offset: 0x778 */
32215        uint8_t RESERVED_14[4];
32216   __I  uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD;     /**< Good and Bad Packets Received, offset: 0x780 */
32217   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD;       /**< Bytes in Good and Bad Packets Received, offset: 0x784 */
32218   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD;           /**< Bytes in Good Packets Received, offset: 0x788 */
32219   __I  uint32_t MAC_RX_BROADCAST_PACKETS_GOOD;     /**< Good Broadcast Packets Received, offset: 0x78C */
32220   __I  uint32_t MAC_RX_MULTICAST_PACKETS_GOOD;     /**< Good Multicast Packets Received, offset: 0x790 */
32221   __I  uint32_t MAC_RX_CRC_ERROR_PACKETS;          /**< CRC Error Packets Received, offset: 0x794 */
32222   __I  uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS;    /**< Alignment Error Packets Received, offset: 0x798 */
32223   __I  uint32_t MAC_RX_RUNT_ERROR_PACKETS;         /**< Runt Error Packets Received, offset: 0x79C */
32224   __I  uint32_t MAC_RX_JABBER_ERROR_PACKETS;       /**< Jabber Error Packets Received, offset: 0x7A0 */
32225   __I  uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD;     /**< Good Undersize Packets Received, offset: 0x7A4 */
32226   __I  uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD;      /**< Good Oversize Packets Received, offset: 0x7A8 */
32227   __I  uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD;  /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */
32228   __I  uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */
32229   __I  uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */
32230   __I  uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */
32231   __I  uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */
32232   __I  uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */
32233   __I  uint32_t MAC_RX_UNICAST_PACKETS_GOOD;       /**< Good Unicast Packets Received, offset: 0x7C4 */
32234   __I  uint32_t MAC_RX_LENGTH_ERROR_PACKETS;       /**< Length Error Packets Received, offset: 0x7C8 */
32235   __I  uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS;  /**< Out-of-range Type Packets Received, offset: 0x7CC */
32236   __I  uint32_t MAC_RX_PAUSE_PACKETS;              /**< Pause Packets Received, offset: 0x7D0 */
32237   __I  uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS;      /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */
32238   __I  uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD;      /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */
32239   __I  uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS;     /**< Watchdog Error Packets Received, offset: 0x7DC */
32240   __I  uint32_t MAC_RX_RECEIVE_ERROR_PACKETS;      /**< Receive Error Packets Received, offset: 0x7E0 */
32241   __I  uint32_t MAC_RX_CONTROL_PACKETS_GOOD;       /**< Good Control Packets Received, offset: 0x7E4 */
32242        uint8_t RESERVED_15[4];
32243   __I  uint32_t MAC_TX_LPI_USEC_CNTR;              /**< Microseconds Tx LPI Asserted, offset: 0x7EC */
32244   __I  uint32_t MAC_TX_LPI_TRAN_CNTR;              /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */
32245   __I  uint32_t MAC_RX_LPI_USEC_CNTR;              /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */
32246   __I  uint32_t MAC_RX_LPI_TRAN_CNTR;              /**< Number of Times Rx LPI Entered, offset: 0x7F8 */
32247        uint8_t RESERVED_16[4];
32248   __IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK;     /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */
32249        uint8_t RESERVED_17[4];
32250   __I  uint32_t MAC_MMC_IPC_RX_INTERRUPT;          /**< MMC IPC Receive Interrupt, offset: 0x808 */
32251        uint8_t RESERVED_18[4];
32252   __I  uint32_t MAC_RXIPV4_GOOD_PACKETS;           /**< Good IPv4 Datagrams Received, offset: 0x810 */
32253   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS;   /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */
32254   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS;     /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */
32255   __I  uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS;     /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */
32256   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */
32257   __I  uint32_t MAC_RXIPV6_GOOD_PACKETS;           /**< Good IPv6 Datagrams Received, offset: 0x824 */
32258   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS;   /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */
32259   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS;     /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */
32260   __I  uint32_t MAC_RXUDP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */
32261   __I  uint32_t MAC_RXUDP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */
32262   __I  uint32_t MAC_RXTCP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */
32263   __I  uint32_t MAC_RXTCP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */
32264   __I  uint32_t MAC_RXICMP_GOOD_PACKETS;           /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */
32265   __I  uint32_t MAC_RXICMP_ERROR_PACKETS;          /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */
32266        uint8_t RESERVED_19[8];
32267   __I  uint32_t MAC_RXIPV4_GOOD_OCTETS;            /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */
32268   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */
32269   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */
32270   __I  uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS;      /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */
32271   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */
32272   __I  uint32_t MAC_RXIPV6_GOOD_OCTETS;            /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */
32273   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */
32274   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */
32275   __I  uint32_t MAC_RXUDP_GOOD_OCTETS;             /**< Bytes Received in Good UDP Segment, offset: 0x870 */
32276   __I  uint32_t MAC_RXUDP_ERROR_OCTETS;            /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */
32277   __I  uint32_t MAC_RXTCP_GOOD_OCTETS;             /**< Bytes Received in Good TCP Segment, offset: 0x878 */
32278   __I  uint32_t MAC_RXTCP_ERROR_OCTETS;            /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */
32279   __I  uint32_t MAC_RXICMP_GOOD_OCTETS;            /**< Bytes Received in Good ICMP Segment, offset: 0x880 */
32280   __I  uint32_t MAC_RXICMP_ERROR_OCTETS;           /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */
32281        uint8_t RESERVED_20[24];
32282   __I  uint32_t MAC_MMC_FPE_TX_INTERRUPT;          /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */
32283   __IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK;     /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */
32284   __I  uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */
32285   __I  uint32_t MAC_MMC_TX_HOLD_REQ_CNTR;          /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */
32286        uint8_t RESERVED_21[16];
32287   __I  uint32_t MAC_MMC_FPE_RX_INTERRUPT;          /**< MMC FPE Receive Interrupt, offset: 0x8C0 */
32288   __IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK;     /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */
32289   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */
32290   __I  uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR;    /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */
32291   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */
32292   __I  uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */
32293        uint8_t RESERVED_22[40];
32294   __IO uint32_t MAC_L3_L4_CONTROL0;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */
32295   __IO uint32_t MAC_LAYER4_ADDRESS0;               /**< Layer 4 Address 0, offset: 0x904 */
32296        uint8_t RESERVED_23[8];
32297   __IO uint32_t MAC_LAYER3_ADDR0_REG0;             /**< Layer 3 Address 0 Register 0, offset: 0x910 */
32298   __IO uint32_t MAC_LAYER3_ADDR1_REG0;             /**< Layer 3 Address 1 Register 0, offset: 0x914 */
32299   __IO uint32_t MAC_LAYER3_ADDR2_REG0;             /**< Layer 3 Address 2 Register 0, offset: 0x918 */
32300   __IO uint32_t MAC_LAYER3_ADDR3_REG0;             /**< Layer 3 Address 3 Register 0, offset: 0x91C */
32301        uint8_t RESERVED_24[16];
32302   __IO uint32_t MAC_L3_L4_CONTROL1;                /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */
32303   __IO uint32_t MAC_LAYER4_ADDRESS1;               /**< Layer 4 Address 0, offset: 0x934 */
32304        uint8_t RESERVED_25[8];
32305   __IO uint32_t MAC_LAYER3_ADDR0_REG1;             /**< Layer 3 Address 0 Register 1, offset: 0x940 */
32306   __IO uint32_t MAC_LAYER3_ADDR1_REG1;             /**< Layer 3 Address 1 Register 1, offset: 0x944 */
32307   __IO uint32_t MAC_LAYER3_ADDR2_REG1;             /**< Layer 3 Address 2 Register 1, offset: 0x948 */
32308   __IO uint32_t MAC_LAYER3_ADDR3_REG1;             /**< Layer 3 Address 3 Register 1, offset: 0x94C */
32309        uint8_t RESERVED_26[16];
32310   __IO uint32_t MAC_L3_L4_CONTROL2;                /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */
32311   __IO uint32_t MAC_LAYER4_ADDRESS2;               /**< Layer 4 Address 2, offset: 0x964 */
32312        uint8_t RESERVED_27[8];
32313   __IO uint32_t MAC_LAYER3_ADDR0_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x970 */
32314   __IO uint32_t MAC_LAYER3_ADDR1_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x974 */
32315   __IO uint32_t MAC_LAYER3_ADDR2_REG2;             /**< Layer 3 Address 2 Register 2, offset: 0x978 */
32316   __IO uint32_t MAC_LAYER3_ADDR3_REG2;             /**< Layer 3 Address 3 Register 2, offset: 0x97C */
32317        uint8_t RESERVED_28[16];
32318   __IO uint32_t MAC_L3_L4_CONTROL3;                /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */
32319   __IO uint32_t MAC_LAYER4_ADDRESS3;               /**< Layer 4 Address 3, offset: 0x994 */
32320        uint8_t RESERVED_29[8];
32321   __IO uint32_t MAC_LAYER3_ADDR0_REG3;             /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */
32322   __IO uint32_t MAC_LAYER3_ADDR1_REG3;             /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */
32323   __IO uint32_t MAC_LAYER3_ADDR2_REG3;             /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */
32324   __IO uint32_t MAC_LAYER3_ADDR3_REG3;             /**< Layer 3 Address 3 Register 3, offset: 0x9AC */
32325        uint8_t RESERVED_30[16];
32326   __IO uint32_t MAC_L3_L4_CONTROL4;                /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */
32327   __IO uint32_t MAC_LAYER4_ADDRESS4;               /**< Layer 4 Address 4, offset: 0x9C4 */
32328        uint8_t RESERVED_31[8];
32329   __IO uint32_t MAC_LAYER3_ADDR0_REG4;             /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */
32330   __IO uint32_t MAC_LAYER3_ADDR1_REG4;             /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */
32331   __IO uint32_t MAC_LAYER3_ADDR2_REG4;             /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */
32332   __IO uint32_t MAC_LAYER3_ADDR3_REG4;             /**< Layer 3 Address 3 Register 4, offset: 0x9DC */
32333        uint8_t RESERVED_32[16];
32334   __IO uint32_t MAC_L3_L4_CONTROL5;                /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */
32335   __IO uint32_t MAC_LAYER4_ADDRESS5;               /**< Layer 4 Address 5, offset: 0x9F4 */
32336        uint8_t RESERVED_33[8];
32337   __IO uint32_t MAC_LAYER3_ADDR0_REG5;             /**< Layer 3 Address 0 Register 5, offset: 0xA00 */
32338   __IO uint32_t MAC_LAYER3_ADDR1_REG5;             /**< Layer 3 Address 1 Register 5, offset: 0xA04 */
32339   __IO uint32_t MAC_LAYER3_ADDR2_REG5;             /**< Layer 3 Address 2 Register 5, offset: 0xA08 */
32340   __IO uint32_t MAC_LAYER3_ADDR3_REG5;             /**< Layer 3 Address 3 Register 5, offset: 0xA0C */
32341        uint8_t RESERVED_34[16];
32342   __IO uint32_t MAC_L3_L4_CONTROL6;                /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */
32343   __IO uint32_t MAC_LAYER4_ADDRESS6;               /**< Layer 4 Address 6, offset: 0xA24 */
32344        uint8_t RESERVED_35[8];
32345   __IO uint32_t MAC_LAYER3_ADDR0_REG6;             /**< Layer 3 Address 0 Register 6, offset: 0xA30 */
32346   __IO uint32_t MAC_LAYER3_ADDR1_REG6;             /**< Layer 3 Address 1 Register 6, offset: 0xA34 */
32347   __IO uint32_t MAC_LAYER3_ADDR2_REG6;             /**< Layer 3 Address 2 Register 6, offset: 0xA38 */
32348   __IO uint32_t MAC_LAYER3_ADDR3_REG6;             /**< Layer 3 Address 3 Register 6, offset: 0xA3C */
32349        uint8_t RESERVED_36[16];
32350   __IO uint32_t MAC_L3_L4_CONTROL7;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */
32351   __IO uint32_t MAC_LAYER4_ADDRESS7;               /**< Layer 4 Address 7, offset: 0xA54 */
32352        uint8_t RESERVED_37[8];
32353   __IO uint32_t MAC_LAYER3_ADDR0_REG7;             /**< Layer 3 Address 0 Register 7, offset: 0xA60 */
32354   __IO uint32_t MAC_LAYER3_ADDR1_REG7;             /**< Layer 3 Address 1 Register 7, offset: 0xA64 */
32355   __IO uint32_t MAC_LAYER3_ADDR2_REG7;             /**< Layer 3 Address 2 Register 7, offset: 0xA68 */
32356   __IO uint32_t MAC_LAYER3_ADDR3_REG7;             /**< Layer 3 Address 3 Register 7, offset: 0xA6C */
32357        uint8_t RESERVED_38[144];
32358   __IO uint32_t MAC_TIMESTAMP_CONTROL;             /**< Timestamp Control, offset: 0xB00 */
32359   __IO uint32_t MAC_SUB_SECOND_INCREMENT;          /**< Subsecond Increment, offset: 0xB04 */
32360   __I  uint32_t MAC_SYSTEM_TIME_SECONDS;           /**< System Time Seconds, offset: 0xB08 */
32361   __I  uint32_t MAC_SYSTEM_TIME_NANOSECONDS;       /**< System Time Nanoseconds, offset: 0xB0C */
32362   __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE;    /**< System Time Seconds Update, offset: 0xB10 */
32363   __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
32364   __IO uint32_t MAC_TIMESTAMP_ADDEND;              /**< Timestamp Addend, offset: 0xB18 */
32365   __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */
32366   __I  uint32_t MAC_TIMESTAMP_STATUS;              /**< Timestamp Status, offset: 0xB20 */
32367        uint8_t RESERVED_39[12];
32368   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
32369   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
32370        uint8_t RESERVED_40[8];
32371   __IO uint32_t MAC_AUXILIARY_CONTROL;             /**< Auxiliary Timestamp Control, offset: 0xB40 */
32372        uint8_t RESERVED_41[4];
32373   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */
32374   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS;   /**< Auxiliary Timestamp Seconds, offset: 0xB4C */
32375   __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR;   /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */
32376   __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR;    /**< imestamp Egress Asymmetry Correction, offset: 0xB54 */
32377   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
32378   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
32379   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */
32380   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */
32381   __I  uint32_t MAC_TIMESTAMP_INGRESS_LATENCY;     /**< Timestamp Ingress Latency, offset: 0xB68 */
32382   __I  uint32_t MAC_TIMESTAMP_EGRESS_LATENCY;      /**< Timestamp Egress Latency, offset: 0xB6C */
32383   __IO uint32_t MAC_PPS_CONTROL;                   /**< PPS Control, offset: 0xB70 */
32384        uint8_t RESERVED_42[12];
32385   __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS;      /**< PPS0 Target Time Seconds, offset: 0xB80 */
32386   __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS;  /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
32387   __IO uint32_t MAC_PPS0_INTERVAL;                 /**< PPS0 Interval, offset: 0xB88 */
32388   __IO uint32_t MAC_PPS0_WIDTH;                    /**< PPS0 Width, offset: 0xB8C */
32389   __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS;      /**< PPS1 Target Time Seconds, offset: 0xB90 */
32390   __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS;  /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */
32391   __IO uint32_t MAC_PPS1_INTERVAL;                 /**< PPS1 Interval, offset: 0xB98 */
32392   __IO uint32_t MAC_PPS1_WIDTH;                    /**< PPS1 Width, offset: 0xB9C */
32393   __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS;      /**< PPS2 Target Time Seconds, offset: 0xBA0 */
32394   __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS;  /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */
32395   __IO uint32_t MAC_PPS2_INTERVAL;                 /**< PPS2 Interval, offset: 0xBA8 */
32396   __IO uint32_t MAC_PPS2_WIDTH;                    /**< PPS2 Width, offset: 0xBAC */
32397   __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS;      /**< PPS3 Target Time Seconds, offset: 0xBB0 */
32398   __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS;  /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */
32399   __IO uint32_t MAC_PPS3_INTERVAL;                 /**< PPS3 Interval, offset: 0xBB8 */
32400   __IO uint32_t MAC_PPS3_WIDTH;                    /**< PPS3 Width, offset: 0xBBC */
32401   __IO uint32_t MAC_PTO_CONTROL;                   /**< PTP Offload Engine Control, offset: 0xBC0 */
32402   __IO uint32_t MAC_SOURCE_PORT_IDENTITY0;         /**< Source Port Identity 0, offset: 0xBC4 */
32403   __IO uint32_t MAC_SOURCE_PORT_IDENTITY1;         /**< Source Port Identity 1, offset: 0xBC8 */
32404   __IO uint32_t MAC_SOURCE_PORT_IDENTITY2;         /**< Source Port Identity 2, offset: 0xBCC */
32405   __IO uint32_t MAC_LOG_MESSAGE_INTERVAL;          /**< Log Message Interval, offset: 0xBD0 */
32406        uint8_t RESERVED_43[44];
32407   __IO uint32_t MTL_OPERATION_MODE;                /**< MTL Operation Mode, offset: 0xC00 */
32408        uint8_t RESERVED_44[4];
32409   __IO uint32_t MTL_DBG_CTL;                       /**< FIFO Debug Access Control and Status, offset: 0xC08 */
32410   __IO uint32_t MTL_DBG_STS;                       /**< FIFO Debug Status, offset: 0xC0C */
32411   __IO uint32_t MTL_FIFO_DEBUG_DATA;               /**< FIFO Debug Data, offset: 0xC10 */
32412        uint8_t RESERVED_45[12];
32413   __I  uint32_t MTL_INTERRUPT_STATUS;              /**< MTL Interrupt Status, offset: 0xC20 */
32414        uint8_t RESERVED_46[12];
32415   __IO uint32_t MTL_RXQ_DMA_MAP0;                  /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
32416   __IO uint32_t MTL_RXQ_DMA_MAP1;                  /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */
32417        uint8_t RESERVED_47[8];
32418   __IO uint32_t MTL_TBS_CTRL;                      /**< Time Based Scheduling Control, offset: 0xC40 */
32419        uint8_t RESERVED_48[12];
32420   __IO uint32_t MTL_EST_CONTROL;                   /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */
32421        uint8_t RESERVED_49[4];
32422   __IO uint32_t MTL_EST_STATUS;                    /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */
32423        uint8_t RESERVED_50[4];
32424   __IO uint32_t MTL_EST_SCH_ERROR;                 /**< EST Scheduling Error, offset: 0xC60 */
32425   __IO uint32_t MTL_EST_FRM_SIZE_ERROR;            /**< EST Frame Size Error, offset: 0xC64 */
32426   __I  uint32_t MTL_EST_FRM_SIZE_CAPTURE;          /**< EST Frame Size Capture, offset: 0xC68 */
32427        uint8_t RESERVED_51[4];
32428   __IO uint32_t MTL_EST_INTR_ENABLE;               /**< EST Interrupt Enable, offset: 0xC70 */
32429        uint8_t RESERVED_52[12];
32430   __IO uint32_t MTL_EST_GCL_CONTROL;               /**< EST GCL Control, offset: 0xC80 */
32431   __IO uint32_t MTL_EST_GCL_DATA;                  /**< EST GCL Data, offset: 0xC84 */
32432        uint8_t RESERVED_53[8];
32433   __IO uint32_t MTL_FPE_CTRL_STS;                  /**< Frame Preemption Control and Status, offset: 0xC90 */
32434   __IO uint32_t MTL_FPE_ADVANCE;                   /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */
32435        uint8_t RESERVED_54[8];
32436   __IO uint32_t MTL_RXP_CONTROL_STATUS;            /**< RXP Control Status, offset: 0xCA0 */
32437   __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS;  /**< RXP Interrupt Control Status, offset: 0xCA4 */
32438   __I  uint32_t MTL_RXP_DROP_CNT;                  /**< RXP Drop Count, offset: 0xCA8 */
32439   __I  uint32_t MTL_RXP_ERROR_CNT;                 /**< RXP Error Count, offset: 0xCAC */
32440   __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */
32441   __IO uint32_t MTL_RXP_INDIRECT_ACC_DATA;         /**< RXP Indirect Access Data, offset: 0xCB4 */
32442        uint8_t RESERVED_55[72];
32443   struct {                                         /* offset: 0xD00, array step: 0x40 */
32444     __IO uint32_t MTL_TXQX_OP_MODE;                  /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
32445     __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */
32446     __I  uint32_t MTL_TXQX_DBG;                      /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */
32447          uint8_t RESERVED_0[4];
32448     __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1-4] */
32449     __I  uint32_t MTL_TXQX_ETS_STAT;                 /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */
32450     __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
32451     __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40, valid indices: [1-4] */
32452     __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1-4] */
32453     __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40, valid indices: [1-4] */
32454          uint8_t RESERVED_1[4];
32455     __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
32456     __IO uint32_t MTL_RXQX_OP_MODE;                  /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
32457     __I  uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
32458     __I  uint32_t MTL_RXQX_DBG;                      /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */
32459     __IO uint32_t MTL_RXQX_CTRL;                     /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */
32460   } MTL_QUEUE[5];
32461        uint8_t RESERVED_56[448];
32462   __IO uint32_t DMA_MODE;                          /**< DMA Bus Mode, offset: 0x1000 */
32463   __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus Mode, offset: 0x1004 */
32464   __I  uint32_t DMA_INTERRUPT_STATUS;              /**< DMA Interrupt Status, offset: 0x1008 */
32465   __I  uint32_t DMA_DEBUG_STATUS0;                 /**< DMA Debug Status 0, offset: 0x100C */
32466   __I  uint32_t DMA_DEBUG_STATUS1;                 /**< DMA Debug Status 1, offset: 0x1010 */
32467        uint8_t RESERVED_57[44];
32468   __IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL;        /**< AXI LPI Entry Interval Control, offset: 0x1040 */
32469        uint8_t RESERVED_58[12];
32470   __IO uint32_t DMA_TBS_CTRL;                      /**< TBS Control, offset: 0x1050 */
32471        uint8_t RESERVED_59[172];
32472   struct {                                         /* offset: 0x1100, array step: 0x80 */
32473     __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channel 0 Control..DMA Channel 4 Control, array offset: 0x1100, array step: 0x80 */
32474     __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */
32475     __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */
32476          uint8_t RESERVED_0[8];
32477     __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
32478          uint8_t RESERVED_1[4];
32479     __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
32480     __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
32481          uint8_t RESERVED_2[4];
32482     __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
32483     __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
32484     __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
32485     __IO uint32_t DMA_CHX_INT_EN;                    /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
32486     __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
32487     __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
32488          uint8_t RESERVED_3[4];
32489     __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
32490          uint8_t RESERVED_4[4];
32491     __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
32492          uint8_t RESERVED_5[4];
32493     __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
32494          uint8_t RESERVED_6[4];
32495     __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
32496     __IO uint32_t DMA_CHX_STAT;                      /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */
32497     __I  uint32_t DMA_CHX_MISS_FRAME_CNT;            /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
32498     __I  uint32_t DMA_CHX_RXP_ACCEPT_CNT;            /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */
32499     __I  uint32_t DMA_CHX_RX_ERI_CNT;                /**< Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
32500          uint8_t RESERVED_7[16];
32501   } DMA_CH[5];
32502 } ENET_QOS_Type;
32503 
32504 /* ----------------------------------------------------------------------------
32505    -- ENET_QOS Register Masks
32506    ---------------------------------------------------------------------------- */
32507 
32508 /*!
32509  * @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks
32510  * @{
32511  */
32512 
32513 /*! @name MAC_CONFIGURATION - MAC Configuration Register */
32514 /*! @{ */
32515 
32516 #define ENET_QOS_MAC_CONFIGURATION_RE_MASK       (0x1U)
32517 #define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT      (0U)
32518 /*! RE - Receiver Enable
32519  *  0b0..Receiver is disabled
32520  *  0b1..Receiver is enabled
32521  */
32522 #define ENET_QOS_MAC_CONFIGURATION_RE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK)
32523 
32524 #define ENET_QOS_MAC_CONFIGURATION_TE_MASK       (0x2U)
32525 #define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT      (1U)
32526 /*! TE - Transmitter Enable
32527  *  0b0..Transmitter is disabled
32528  *  0b1..Transmitter is enabled
32529  */
32530 #define ENET_QOS_MAC_CONFIGURATION_TE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK)
32531 
32532 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK   (0xCU)
32533 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT  (2U)
32534 /*! PRELEN - Preamble Length for Transmit packets
32535  *  0b10..3 bytes of preamble
32536  *  0b01..5 bytes of preamble
32537  *  0b00..7 bytes of preamble
32538  *  0b11..Reserved
32539  */
32540 #define ENET_QOS_MAC_CONFIGURATION_PRELEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK)
32541 
32542 #define ENET_QOS_MAC_CONFIGURATION_DC_MASK       (0x10U)
32543 #define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT      (4U)
32544 /*! DC - Deferral Check
32545  *  0b0..Deferral check function is disabled
32546  *  0b1..Deferral check function is enabled
32547  */
32548 #define ENET_QOS_MAC_CONFIGURATION_DC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK)
32549 
32550 #define ENET_QOS_MAC_CONFIGURATION_BL_MASK       (0x60U)
32551 #define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT      (5U)
32552 /*! BL - Back-Off Limit
32553  *  0b11..k = min(n,1)
32554  *  0b00..k = min(n,10)
32555  *  0b10..k = min(n,4)
32556  *  0b01..k = min(n,8)
32557  */
32558 #define ENET_QOS_MAC_CONFIGURATION_BL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK)
32559 
32560 #define ENET_QOS_MAC_CONFIGURATION_DR_MASK       (0x100U)
32561 #define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT      (8U)
32562 /*! DR - Disable Retry
32563  *  0b1..Disable Retry
32564  *  0b0..Enable Retry
32565  */
32566 #define ENET_QOS_MAC_CONFIGURATION_DR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK)
32567 
32568 #define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK     (0x200U)
32569 #define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT    (9U)
32570 /*! DCRS - Disable Carrier Sense During Transmission
32571  *  0b1..Disable Carrier Sense During Transmission
32572  *  0b0..Enable Carrier Sense During Transmission
32573  */
32574 #define ENET_QOS_MAC_CONFIGURATION_DCRS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK)
32575 
32576 #define ENET_QOS_MAC_CONFIGURATION_DO_MASK       (0x400U)
32577 #define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT      (10U)
32578 /*! DO - Disable Receive Own
32579  *  0b1..Disable Receive Own
32580  *  0b0..Enable Receive Own
32581  */
32582 #define ENET_QOS_MAC_CONFIGURATION_DO(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK)
32583 
32584 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK   (0x800U)
32585 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT  (11U)
32586 /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
32587  *  0b0..ECRSFD is disabled
32588  *  0b1..ECRSFD is enabled
32589  */
32590 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK)
32591 
32592 #define ENET_QOS_MAC_CONFIGURATION_LM_MASK       (0x1000U)
32593 #define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT      (12U)
32594 /*! LM - Loopback Mode
32595  *  0b0..Loopback is disabled
32596  *  0b1..Loopback is enabled
32597  */
32598 #define ENET_QOS_MAC_CONFIGURATION_LM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK)
32599 
32600 #define ENET_QOS_MAC_CONFIGURATION_DM_MASK       (0x2000U)
32601 #define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT      (13U)
32602 /*! DM - Duplex Mode
32603  *  0b1..Full-duplex mode
32604  *  0b0..Half-duplex mode
32605  */
32606 #define ENET_QOS_MAC_CONFIGURATION_DM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK)
32607 
32608 #define ENET_QOS_MAC_CONFIGURATION_FES_MASK      (0x4000U)
32609 #define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT     (14U)
32610 /*! FES - Speed
32611  *  0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
32612  *  0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
32613  */
32614 #define ENET_QOS_MAC_CONFIGURATION_FES(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK)
32615 
32616 #define ENET_QOS_MAC_CONFIGURATION_PS_MASK       (0x8000U)
32617 #define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT      (15U)
32618 /*! PS - Port Select
32619  *  0b0..For 1000 or 2500 Mbps operations
32620  *  0b1..For 10 or 100 Mbps operations
32621  */
32622 #define ENET_QOS_MAC_CONFIGURATION_PS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK)
32623 
32624 #define ENET_QOS_MAC_CONFIGURATION_JE_MASK       (0x10000U)
32625 #define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT      (16U)
32626 /*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes
32627  *    (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet
32628  *    status.
32629  *  0b0..Jumbo packet is disabled
32630  *  0b1..Jumbo packet is enabled
32631  */
32632 #define ENET_QOS_MAC_CONFIGURATION_JE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK)
32633 
32634 #define ENET_QOS_MAC_CONFIGURATION_JD_MASK       (0x20000U)
32635 #define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT      (17U)
32636 /*! JD - Jabber Disable
32637  *  0b1..Jabber is disabled
32638  *  0b0..Jabber is enabled
32639  */
32640 #define ENET_QOS_MAC_CONFIGURATION_JD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK)
32641 
32642 #define ENET_QOS_MAC_CONFIGURATION_BE_MASK       (0x40000U)
32643 #define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT      (18U)
32644 /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
32645  *    transmission in the GMII half-duplex mode.
32646  *  0b0..Packet Burst is disabled
32647  *  0b1..Packet Burst is enabled
32648  */
32649 #define ENET_QOS_MAC_CONFIGURATION_BE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK)
32650 
32651 #define ENET_QOS_MAC_CONFIGURATION_WD_MASK       (0x80000U)
32652 #define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT      (19U)
32653 /*! WD - Watchdog Disable
32654  *  0b1..Watchdog is disabled
32655  *  0b0..Watchdog is enabled
32656  */
32657 #define ENET_QOS_MAC_CONFIGURATION_WD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK)
32658 
32659 #define ENET_QOS_MAC_CONFIGURATION_ACS_MASK      (0x100000U)
32660 #define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT     (20U)
32661 /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
32662  *    on the incoming packets only if the value of the length field is less than 1,536 bytes.
32663  *  0b0..Automatic Pad or CRC Stripping is disabled
32664  *  0b1..Automatic Pad or CRC Stripping is enabled
32665  */
32666 #define ENET_QOS_MAC_CONFIGURATION_ACS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK)
32667 
32668 #define ENET_QOS_MAC_CONFIGURATION_CST_MASK      (0x200000U)
32669 #define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT     (21U)
32670 /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
32671  *    packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
32672  *    the packet to the application.
32673  *  0b0..CRC stripping for Type packets is disabled
32674  *  0b1..CRC stripping for Type packets is enabled
32675  */
32676 #define ENET_QOS_MAC_CONFIGURATION_CST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK)
32677 
32678 #define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK     (0x400000U)
32679 #define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT    (22U)
32680 /*! S2KP - IEEE 802.
32681  *  0b0..Support upto 2K packet is disabled
32682  *  0b1..Support upto 2K packet is Enabled
32683  */
32684 #define ENET_QOS_MAC_CONFIGURATION_S2KP(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK)
32685 
32686 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK   (0x800000U)
32687 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT  (23U)
32688 /*! GPSLCE - Giant Packet Size Limit Control Enable
32689  *  0b0..Giant Packet Size Limit Control is disabled
32690  *  0b1..Giant Packet Size Limit Control is enabled
32691  */
32692 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK)
32693 
32694 #define ENET_QOS_MAC_CONFIGURATION_IPG_MASK      (0x7000000U)
32695 #define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT     (24U)
32696 /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
32697  *  0b111..40 bit times IPG
32698  *  0b110..48 bit times IPG
32699  *  0b101..56 bit times IPG
32700  *  0b100..64 bit times IPG
32701  *  0b011..72 bit times IPG
32702  *  0b010..80 bit times IPG
32703  *  0b001..88 bit times IPG
32704  *  0b000..96 bit times IPG
32705  */
32706 #define ENET_QOS_MAC_CONFIGURATION_IPG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK)
32707 
32708 #define ENET_QOS_MAC_CONFIGURATION_IPC_MASK      (0x8000000U)
32709 #define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT     (27U)
32710 /*! IPC - Checksum Offload
32711  *  0b0..IP header/payload checksum checking is disabled
32712  *  0b1..IP header/payload checksum checking is enabled
32713  */
32714 #define ENET_QOS_MAC_CONFIGURATION_IPC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK)
32715 
32716 #define ENET_QOS_MAC_CONFIGURATION_SARC_MASK     (0x70000000U)
32717 #define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT    (28U)
32718 /*! SARC - Source Address Insertion or Replacement Control
32719  *  0b010..Contents of MAC Addr-0 inserted in SA field
32720  *  0b011..Contents of MAC Addr-0 replaces SA field
32721  *  0b110..Contents of MAC Addr-1 inserted in SA field
32722  *  0b111..Contents of MAC Addr-1 replaces SA field
32723  *  0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
32724  */
32725 #define ENET_QOS_MAC_CONFIGURATION_SARC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK)
32726 /*! @} */
32727 
32728 /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
32729 /*! @{ */
32730 
32731 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU)
32732 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
32733 /*! GPSL - Giant Packet Size Limit */
32734 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK)
32735 
32736 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U)
32737 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
32738 /*! DCRCC - Disable CRC Checking for Received Packets
32739  *  0b1..CRC Checking is disabled
32740  *  0b0..CRC Checking is enabled
32741  */
32742 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK)
32743 
32744 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U)
32745 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
32746 /*! SPEN - Slow Protocol Detection Enable
32747  *  0b0..Slow Protocol Detection is disabled
32748  *  0b1..Slow Protocol Detection is enabled
32749  */
32750 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK)
32751 
32752 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK  (0x40000U)
32753 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
32754 /*! USP - Unicast Slow Protocol Packet Detect
32755  *  0b0..Unicast Slow Protocol Packet Detection is disabled
32756  *  0b1..Unicast Slow Protocol Packet Detection is enabled
32757  */
32758 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK)
32759 
32760 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK  (0x80000U)
32761 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U)
32762 /*! PDC - Packet Duplication Control
32763  *  0b0..Packet Duplication Control is disabled
32764  *  0b1..Packet Duplication Control is enabled
32765  */
32766 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK)
32767 
32768 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U)
32769 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
32770 /*! EIPGEN - Extended Inter-Packet Gap Enable
32771  *  0b0..Extended Inter-Packet Gap is disabled
32772  *  0b1..Extended Inter-Packet Gap is enabled
32773  */
32774 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
32775 
32776 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U)
32777 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
32778 /*! EIPG - Extended Inter-Packet Gap */
32779 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK)
32780 /*! @} */
32781 
32782 /*! @name MAC_PACKET_FILTER - MAC Packet Filter */
32783 /*! @{ */
32784 
32785 #define ENET_QOS_MAC_PACKET_FILTER_PR_MASK       (0x1U)
32786 #define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT      (0U)
32787 /*! PR - Promiscuous Mode
32788  *  0b0..Promiscuous Mode is disabled
32789  *  0b1..Promiscuous Mode is enabled
32790  */
32791 #define ENET_QOS_MAC_PACKET_FILTER_PR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK)
32792 
32793 #define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK      (0x2U)
32794 #define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT     (1U)
32795 /*! HUC - Hash Unicast
32796  *  0b0..Hash Unicast is disabled
32797  *  0b1..Hash Unicast is enabled
32798  */
32799 #define ENET_QOS_MAC_PACKET_FILTER_HUC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK)
32800 
32801 #define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK      (0x4U)
32802 #define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT     (2U)
32803 /*! HMC - Hash Multicast
32804  *  0b0..Hash Multicast is disabled
32805  *  0b1..Hash Multicast is enabled
32806  */
32807 #define ENET_QOS_MAC_PACKET_FILTER_HMC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK)
32808 
32809 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK     (0x8U)
32810 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT    (3U)
32811 /*! DAIF - DA Inverse Filtering
32812  *  0b0..DA Inverse Filtering is disabled
32813  *  0b1..DA Inverse Filtering is enabled
32814  */
32815 #define ENET_QOS_MAC_PACKET_FILTER_DAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK)
32816 
32817 #define ENET_QOS_MAC_PACKET_FILTER_PM_MASK       (0x10U)
32818 #define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT      (4U)
32819 /*! PM - Pass All Multicast
32820  *  0b0..Pass All Multicast is disabled
32821  *  0b1..Pass All Multicast is enabled
32822  */
32823 #define ENET_QOS_MAC_PACKET_FILTER_PM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK)
32824 
32825 #define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK      (0x20U)
32826 #define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT     (5U)
32827 /*! DBF - Disable Broadcast Packets
32828  *  0b1..Disable Broadcast Packets
32829  *  0b0..Enable Broadcast Packets
32830  */
32831 #define ENET_QOS_MAC_PACKET_FILTER_DBF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK)
32832 
32833 #define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK      (0xC0U)
32834 #define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT     (6U)
32835 /*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including
32836  *    unicast and multicast Pause packets).
32837  *  0b00..MAC filters all control packets from reaching the application
32838  *  0b10..MAC forwards all control packets to the application even if they fail the Address filter
32839  *  0b11..MAC forwards the control packets that pass the Address filter
32840  *  0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
32841  */
32842 #define ENET_QOS_MAC_PACKET_FILTER_PCF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK)
32843 
32844 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK     (0x100U)
32845 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT    (8U)
32846 /*! SAIF - SA Inverse Filtering
32847  *  0b0..SA Inverse Filtering is disabled
32848  *  0b1..SA Inverse Filtering is enabled
32849  */
32850 #define ENET_QOS_MAC_PACKET_FILTER_SAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK)
32851 
32852 #define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK      (0x200U)
32853 #define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT     (9U)
32854 /*! SAF - Source Address Filter Enable
32855  *  0b0..SA Filtering is disabled
32856  *  0b1..SA Filtering is enabled
32857  */
32858 #define ENET_QOS_MAC_PACKET_FILTER_SAF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK)
32859 
32860 #define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK      (0x400U)
32861 #define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT     (10U)
32862 /*! HPF - Hash or Perfect Filter
32863  *  0b0..Hash or Perfect Filter is disabled
32864  *  0b1..Hash or Perfect Filter is enabled
32865  */
32866 #define ENET_QOS_MAC_PACKET_FILTER_HPF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK)
32867 
32868 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK     (0x10000U)
32869 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT    (16U)
32870 /*! VTFE - VLAN Tag Filter Enable
32871  *  0b0..VLAN Tag Filter is disabled
32872  *  0b1..VLAN Tag Filter is enabled
32873  */
32874 #define ENET_QOS_MAC_PACKET_FILTER_VTFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK)
32875 
32876 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK     (0x100000U)
32877 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT    (20U)
32878 /*! IPFE - Layer 3 and Layer 4 Filter Enable
32879  *  0b0..Layer 3 and Layer 4 Filters are disabled
32880  *  0b1..Layer 3 and Layer 4 Filters are enabled
32881  */
32882 #define ENET_QOS_MAC_PACKET_FILTER_IPFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK)
32883 
32884 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK     (0x200000U)
32885 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT    (21U)
32886 /*! DNTU - Drop Non-TCP/UDP over IP Packets
32887  *  0b1..Drop Non-TCP/UDP over IP Packets
32888  *  0b0..Forward Non-TCP/UDP over IP Packets
32889  */
32890 #define ENET_QOS_MAC_PACKET_FILTER_DNTU(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK)
32891 
32892 #define ENET_QOS_MAC_PACKET_FILTER_RA_MASK       (0x80000000U)
32893 #define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT      (31U)
32894 /*! RA - Receive All
32895  *  0b0..Receive All is disabled
32896  *  0b1..Receive All is enabled
32897  */
32898 #define ENET_QOS_MAC_PACKET_FILTER_RA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK)
32899 /*! @} */
32900 
32901 /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
32902 /*! @{ */
32903 
32904 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK   (0xFU)
32905 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT  (0U)
32906 /*! WTO - Watchdog Timeout
32907  *  0b1000..10 KB
32908  *  0b1001..11 KB
32909  *  0b1010..12 KB
32910  *  0b1011..13 KB
32911  *  0b1100..14 KB
32912  *  0b1101..15 KB
32913  *  0b1110..16383 Bytes
32914  *  0b0000..2 KB
32915  *  0b0001..3 KB
32916  *  0b0010..4 KB
32917  *  0b0011..5 KB
32918  *  0b0100..6 KB
32919  *  0b0101..7 KB
32920  *  0b0110..8 KB
32921  *  0b0111..9 KB
32922  *  0b1111..Reserved
32923  */
32924 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
32925 
32926 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK   (0x100U)
32927 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT  (8U)
32928 /*! PWE - Programmable Watchdog Enable
32929  *  0b0..Programmable Watchdog is disabled
32930  *  0b1..Programmable Watchdog is enabled
32931  */
32932 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
32933 /*! @} */
32934 
32935 /*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */
32936 /*! @{ */
32937 
32938 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU)
32939 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
32940 /*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. */
32941 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK)
32942 /*! @} */
32943 
32944 /*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */
32945 /*! @{ */
32946 
32947 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU)
32948 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
32949 /*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. */
32950 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK)
32951 /*! @} */
32952 
32953 /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
32954 /*! @{ */
32955 
32956 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK       (0x1U)
32957 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT      (0U)
32958 /*! OB - Operation Busy
32959  *  0b0..Operation Busy is disabled
32960  *  0b1..Operation Busy is enabled
32961  */
32962 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK)
32963 
32964 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK       (0x2U)
32965 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT      (1U)
32966 /*! CT - Command Type
32967  *  0b1..Read operation
32968  *  0b0..Write operation
32969  */
32970 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK)
32971 
32972 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK      (0x7CU)
32973 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT     (2U)
32974 /*! OFS - Offset */
32975 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK)
32976 
32977 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK     (0x20000U)
32978 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT    (17U)
32979 /*! VTIM - VLAN Tag Inverse Match Enable
32980  *  0b0..VLAN Tag Inverse Match is disabled
32981  *  0b1..VLAN Tag Inverse Match is enabled
32982  */
32983 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK)
32984 
32985 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK     (0x40000U)
32986 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT    (18U)
32987 /*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN
32988  *    packets (Type = 0x88A8) as valid VLAN tagged packets.
32989  *  0b0..S-VLAN is disabled
32990  *  0b1..S-VLAN is enabled
32991  */
32992 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK)
32993 
32994 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK     (0x600000U)
32995 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT    (21U)
32996 /*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the
32997  *    outer VLAN Tag in received packet.
32998  *  0b11..Always strip
32999  *  0b00..Do not strip
33000  *  0b10..Strip if VLAN filter fails
33001  *  0b01..Strip if VLAN filter passes
33002  */
33003 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK)
33004 
33005 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK   (0x1000000U)
33006 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT  (24U)
33007 /*! EVLRXS - Enable VLAN Tag in Rx status
33008  *  0b0..VLAN Tag in Rx status is disabled
33009  *  0b1..VLAN Tag in Rx status is enabled
33010  */
33011 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
33012 
33013 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK     (0x2000000U)
33014 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT    (25U)
33015 /*! VTHM - VLAN Tag Hash Table Match Enable
33016  *  0b0..VLAN Tag Hash Table Match is disabled
33017  *  0b1..VLAN Tag Hash Table Match is enabled
33018  */
33019 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK)
33020 
33021 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK    (0x4000000U)
33022 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT   (26U)
33023 /*! EDVLP - Enable Double VLAN Processing
33024  *  0b0..Double VLAN Processing is disabled
33025  *  0b1..Double VLAN Processing is enabled
33026  */
33027 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
33028 
33029 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK   (0x8000000U)
33030 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT  (27U)
33031 /*! ERIVLT - ERIVLT
33032  *  0b0..Inner VLAN tag is disabled
33033  *  0b1..Inner VLAN tag is enabled
33034  */
33035 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
33036 
33037 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK    (0x30000000U)
33038 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT   (28U)
33039 /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation
33040  *    on inner VLAN Tag in received packet.
33041  *  0b11..Always strip
33042  *  0b00..Do not strip
33043  *  0b10..Strip if VLAN filter fails
33044  *  0b01..Strip if VLAN filter passes
33045  */
33046 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
33047 
33048 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK  (0x80000000U)
33049 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U)
33050 /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
33051  *  0b0..Inner VLAN Tag in Rx status is disabled
33052  *  0b1..Inner VLAN Tag in Rx status is enabled
33053  */
33054 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
33055 /*! @} */
33056 
33057 /*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */
33058 /*! @{ */
33059 
33060 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK      (0xFFFFU)
33061 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT     (0U)
33062 /*! VID - VLAN Tag ID */
33063 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK)
33064 
33065 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK      (0x10000U)
33066 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT     (16U)
33067 /*! VEN - VLAN Tag Enable
33068  *  0b0..VLAN Tag is disabled
33069  *  0b1..VLAN Tag is enabled
33070  */
33071 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK)
33072 
33073 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK      (0x20000U)
33074 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT     (17U)
33075 /*! ETV - 12bits or 16bits VLAN comparison
33076  *  0b1..12 bit VLAN comparison
33077  *  0b0..16 bit VLAN comparison
33078  */
33079 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK)
33080 
33081 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK   (0x40000U)
33082 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT  (18U)
33083 /*! DOVLTC - Disable VLAN Type Comparison
33084  *  0b1..VLAN type comparison is disabled
33085  *  0b0..VLAN type comparison is enabled
33086  */
33087 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK)
33088 
33089 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK   (0x80000U)
33090 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT  (19U)
33091 /*! ERSVLM - Enable S-VLAN Match for received Frames
33092  *  0b0..Receive S-VLAN Match is disabled
33093  *  0b1..Receive S-VLAN Match is enabled
33094  */
33095 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK)
33096 
33097 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK   (0x100000U)
33098 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT  (20U)
33099 /*! ERIVLT - Enable Inner VLAN Tag Comparison
33100  *  0b0..Inner VLAN tag comparison is disabled
33101  *  0b1..Inner VLAN tag comparison is enabled
33102  */
33103 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK)
33104 
33105 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK  (0x1000000U)
33106 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U)
33107 /*! DMACHEN - DMA Channel Number Enable
33108  *  0b0..DMA Channel Number is disabled
33109  *  0b1..DMA Channel Number is enabled
33110  */
33111 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK)
33112 
33113 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK   (0xE000000U)
33114 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT  (25U)
33115 /*! DMACHN - DMA Channel Number */
33116 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK)
33117 /*! @} */
33118 
33119 /*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */
33120 /*! @{ */
33121 
33122 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK   (0xFFFFU)
33123 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT  (0U)
33124 /*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table. */
33125 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK)
33126 /*! @} */
33127 
33128 /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
33129 /*! @{ */
33130 
33131 #define ENET_QOS_MAC_VLAN_INCL_VLT_MASK          (0xFFFFU)
33132 #define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT         (0U)
33133 /*! VLT - VLAN Tag for Transmit Packets */
33134 #define ENET_QOS_MAC_VLAN_INCL_VLT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK)
33135 
33136 #define ENET_QOS_MAC_VLAN_INCL_VLC_MASK          (0x30000U)
33137 #define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT         (16U)
33138 /*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or
33139  *    replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag
33140  *    (bytes 15 and 16) of all transmitted packets with VLAN tags.
33141  *  0b01..VLAN tag deletion
33142  *  0b10..VLAN tag insertion
33143  *  0b00..No VLAN tag deletion, insertion, or replacement
33144  *  0b11..VLAN tag replacement
33145  */
33146 #define ENET_QOS_MAC_VLAN_INCL_VLC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK)
33147 
33148 #define ENET_QOS_MAC_VLAN_INCL_VLP_MASK          (0x40000U)
33149 #define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT         (18U)
33150 /*! VLP - VLAN Priority Control
33151  *  0b0..VLAN Priority Control is disabled
33152  *  0b1..VLAN Priority Control is enabled
33153  */
33154 #define ENET_QOS_MAC_VLAN_INCL_VLP(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK)
33155 
33156 #define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK         (0x80000U)
33157 #define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT        (19U)
33158 /*! CSVL - C-VLAN or S-VLAN
33159  *  0b0..C-VLAN type (0x8100) is inserted or replaced
33160  *  0b1..S-VLAN type (0x88A8) is inserted or replaced
33161  */
33162 #define ENET_QOS_MAC_VLAN_INCL_CSVL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK)
33163 
33164 #define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK         (0x100000U)
33165 #define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT        (20U)
33166 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
33167  *    replaced in Tx packet should be taken from: - The Tx descriptor
33168  *  0b0..VLAN Tag Input is disabled
33169  *  0b1..VLAN Tag Input is enabled
33170  */
33171 #define ENET_QOS_MAC_VLAN_INCL_VLTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK)
33172 
33173 #define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK         (0x200000U)
33174 #define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT        (21U)
33175 /*! CBTI - Channel based tag insertion
33176  *  0b0..Channel based tag insertion is disabled
33177  *  0b1..Channel based tag insertion is enabled
33178  */
33179 #define ENET_QOS_MAC_VLAN_INCL_CBTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK)
33180 
33181 #define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK         (0x7000000U)
33182 #define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT        (24U)
33183 /*! ADDR - Address */
33184 #define ENET_QOS_MAC_VLAN_INCL_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK)
33185 
33186 #define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK         (0x40000000U)
33187 #define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT        (30U)
33188 /*! RDWR - Read write control
33189  *  0b0..Read operation of indirect access
33190  *  0b1..Write operation of indirect access
33191  */
33192 #define ENET_QOS_MAC_VLAN_INCL_RDWR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK)
33193 
33194 #define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK         (0x80000000U)
33195 #define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT        (31U)
33196 /*! BUSY - Busy
33197  *  0b1..Busy status detected
33198  *  0b0..Busy status not detected
33199  */
33200 #define ENET_QOS_MAC_VLAN_INCL_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK)
33201 /*! @} */
33202 
33203 /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
33204 /*! @{ */
33205 
33206 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK    (0xFFFFU)
33207 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT   (0U)
33208 /*! VLT - VLAN Tag for Transmit Packets */
33209 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK)
33210 
33211 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK    (0x30000U)
33212 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT   (16U)
33213 /*! VLC - VLAN Tag Control in Transmit Packets
33214  *  0b01..VLAN tag deletion
33215  *  0b10..VLAN tag insertion
33216  *  0b00..No VLAN tag deletion, insertion, or replacement
33217  *  0b11..VLAN tag replacement
33218  */
33219 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK)
33220 
33221 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK    (0x40000U)
33222 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT   (18U)
33223 /*! VLP - VLAN Priority Control
33224  *  0b0..VLAN Priority Control is disabled
33225  *  0b1..VLAN Priority Control is enabled
33226  */
33227 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK)
33228 
33229 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK   (0x80000U)
33230 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT  (19U)
33231 /*! CSVL - C-VLAN or S-VLAN
33232  *  0b0..C-VLAN type (0x8100) is inserted
33233  *  0b1..S-VLAN type (0x88A8) is inserted
33234  */
33235 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK)
33236 
33237 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK   (0x100000U)
33238 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT  (20U)
33239 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
33240  *    replaced in Tx packet should be taken from: - The Tx descriptor
33241  *  0b0..VLAN Tag Input is disabled
33242  *  0b1..VLAN Tag Input is enabled
33243  */
33244 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK)
33245 /*! @} */
33246 
33247 /*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */
33248 /*! @{ */
33249 
33250 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U)
33251 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U)
33252 /*! FCB_BPA - Flow Control Busy or Backpressure Activate
33253  *  0b0..Flow Control Busy or Backpressure Activate is disabled
33254  *  0b1..Flow Control Busy or Backpressure Activate is enabled
33255  */
33256 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
33257 
33258 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK     (0x2U)
33259 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT    (1U)
33260 /*! TFE - Transmit Flow Control Enable
33261  *  0b0..Transmit Flow Control is disabled
33262  *  0b1..Transmit Flow Control is enabled
33263  */
33264 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
33265 
33266 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK     (0x70U)
33267 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT    (4U)
33268 /*! PLT - Pause Low Threshold
33269  *  0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
33270  *  0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
33271  *  0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
33272  *  0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
33273  *  0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
33274  *  0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
33275  *  0b110..Reserved
33276  */
33277 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
33278 
33279 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK    (0x80U)
33280 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT   (7U)
33281 /*! DZPQ - Disable Zero-Quanta Pause
33282  *  0b1..Zero-Quanta Pause packet generation is disabled
33283  *  0b0..Zero-Quanta Pause packet generation is enabled
33284  */
33285 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
33286 
33287 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK      (0xFFFF0000U)
33288 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT     (16U)
33289 /*! PT - Pause Time */
33290 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK)
33291 /*! @} */
33292 
33293 /* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */
33294 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT        (5U)
33295 
33296 /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
33297 /*! @{ */
33298 
33299 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK       (0x1U)
33300 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT      (0U)
33301 /*! RFE - Receive Flow Control Enable
33302  *  0b0..Receive Flow Control is disabled
33303  *  0b1..Receive Flow Control is enabled
33304  */
33305 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK)
33306 
33307 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK        (0x2U)
33308 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT       (1U)
33309 /*! UP - Unicast Pause Packet Detect
33310  *  0b0..Unicast Pause Packet Detect disabled
33311  *  0b1..Unicast Pause Packet Detect enabled
33312  */
33313 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK)
33314 
33315 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK      (0x100U)
33316 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT     (8U)
33317 /*! PFCE - Priority Based Flow Control Enable
33318  *  0b0..Priority Based Flow Control is disabled
33319  *  0b1..Priority Based Flow Control is enabled
33320  */
33321 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK)
33322 /*! @} */
33323 
33324 /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
33325 /*! @{ */
33326 
33327 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK        (0x1U)
33328 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT       (0U)
33329 /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
33330  *  0b0..Unicast Address Filter Fail Packets Queuing is disabled
33331  *  0b1..Unicast Address Filter Fail Packets Queuing is enabled
33332  */
33333 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK)
33334 
33335 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK         (0xEU)
33336 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT        (1U)
33337 /*! UFFQ - Unicast Address Filter Fail Packets Queue. */
33338 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK)
33339 
33340 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK        (0x100U)
33341 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT       (8U)
33342 /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
33343  *  0b0..Multicast Address Filter Fail Packets Queuing is disabled
33344  *  0b1..Multicast Address Filter Fail Packets Queuing is enabled
33345  */
33346 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK)
33347 
33348 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK         (0xE00U)
33349 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT        (9U)
33350 /*! MFFQ - Multicast Address Filter Fail Packets Queue. */
33351 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK)
33352 
33353 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK        (0x10000U)
33354 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT       (16U)
33355 /*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
33356  *  0b0..VLAN tag Filter Fail Packets Queuing is disabled
33357  *  0b1..VLAN tag Filter Fail Packets Queuing is enabled
33358  */
33359 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK)
33360 
33361 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK         (0xE0000U)
33362 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT        (17U)
33363 /*! VFFQ - VLAN Tag Filter Fail Packets Queue */
33364 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK)
33365 /*! @} */
33366 
33367 /*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */
33368 /*! @{ */
33369 
33370 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK    (0xFFU)
33371 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT   (0U)
33372 /*! PSTQ0 - Priorities Selected in Transmit Queue 0 */
33373 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK)
33374 
33375 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK    (0xFF00U)
33376 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT   (8U)
33377 /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. */
33378 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK)
33379 
33380 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK    (0xFF0000U)
33381 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT   (16U)
33382 /*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit. */
33383 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK)
33384 
33385 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK    (0xFF000000U)
33386 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT   (24U)
33387 /*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit. */
33388 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK)
33389 /*! @} */
33390 
33391 /*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */
33392 /*! @{ */
33393 
33394 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK    (0xFFU)
33395 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT   (0U)
33396 /*! PSTQ4 - Priorities Selected in Transmit Queue 4 */
33397 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK)
33398 /*! @} */
33399 
33400 /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */
33401 /*! @{ */
33402 
33403 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK         (0x7U)
33404 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT        (0U)
33405 /*! AVCPQ - AV Untagged Control Packets Queue
33406  *  0b000..Receive Queue 0
33407  *  0b001..Receive Queue 1
33408  *  0b010..Receive Queue 2
33409  *  0b011..Receive Queue 3
33410  *  0b100..Receive Queue 4
33411  *  0b101..Reserved
33412  *  0b110..Reserved
33413  *  0b111..Reserved
33414  */
33415 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK)
33416 
33417 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK         (0xFFU)
33418 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT        (0U)
33419 /*! PSRQ0 - Priorities Selected in the Receive Queue 0 */
33420 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK)
33421 
33422 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK         (0xFFU)
33423 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT        (0U)
33424 /*! PSRQ4 - Priorities Selected in the Receive Queue 4 */
33425 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK)
33426 
33427 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK        (0x3U)
33428 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT       (0U)
33429 /*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB.
33430  *  0b00..Queue not enabled
33431  *  0b01..Queue enabled for AV
33432  *  0b10..Queue enabled for DCB/Generic
33433  *  0b11..Reserved
33434  */
33435 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK)
33436 
33437 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK        (0xCU)
33438 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT       (2U)
33439 /*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field.
33440  *  0b00..Queue not enabled
33441  *  0b01..Queue enabled for AV
33442  *  0b10..Queue enabled for DCB/Generic
33443  *  0b11..Reserved
33444  */
33445 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK)
33446 
33447 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK          (0x70U)
33448 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT         (4U)
33449 /*! PTPQ - PTP Packets Queue
33450  *  0b000..Receive Queue 0
33451  *  0b001..Receive Queue 1
33452  *  0b010..Receive Queue 2
33453  *  0b011..Receive Queue 3
33454  *  0b100..Receive Queue 4
33455  *  0b101..Reserved
33456  *  0b110..Reserved
33457  *  0b111..Reserved
33458  */
33459 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK)
33460 
33461 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK        (0x30U)
33462 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT       (4U)
33463 /*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field.
33464  *  0b00..Queue not enabled
33465  *  0b01..Queue enabled for AV
33466  *  0b10..Queue enabled for DCB/Generic
33467  *  0b11..Reserved
33468  */
33469 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK)
33470 
33471 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK        (0xC0U)
33472 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT       (6U)
33473 /*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field.
33474  *  0b00..Queue not enabled
33475  *  0b01..Queue enabled for AV
33476  *  0b10..Queue enabled for DCB/Generic
33477  *  0b11..Reserved
33478  */
33479 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK)
33480 
33481 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK        (0x700U)
33482 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT       (8U)
33483 /*! DCBCPQ - DCB Control Packets Queue
33484  *  0b000..Receive Queue 0
33485  *  0b001..Receive Queue 1
33486  *  0b010..Receive Queue 2
33487  *  0b011..Receive Queue 3
33488  *  0b100..Receive Queue 4
33489  *  0b101..Reserved
33490  *  0b110..Reserved
33491  *  0b111..Reserved
33492  */
33493 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK)
33494 
33495 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK         (0xFF00U)
33496 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT        (8U)
33497 /*! PSRQ1 - Priorities Selected in the Receive Queue 1 */
33498 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK)
33499 
33500 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK        (0x300U)
33501 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT       (8U)
33502 /*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field.
33503  *  0b00..Queue not enabled
33504  *  0b01..Queue enabled for AV
33505  *  0b10..Queue enabled for DCB/Generic
33506  *  0b11..Reserved
33507  */
33508 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK)
33509 
33510 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK           (0x7000U)
33511 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT          (12U)
33512 /*! UPQ - Untagged Packet Queue
33513  *  0b000..Receive Queue 0
33514  *  0b001..Receive Queue 1
33515  *  0b010..Receive Queue 2
33516  *  0b011..Receive Queue 3
33517  *  0b100..Receive Queue 4
33518  *  0b101..Reserved
33519  *  0b110..Reserved
33520  *  0b111..Reserved
33521  */
33522 #define ENET_QOS_MAC_RXQ_CTRL_UPQ(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK)
33523 
33524 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK         (0x70000U)
33525 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT        (16U)
33526 /*! MCBCQ - Multicast and Broadcast Queue
33527  *  0b000..Receive Queue 0
33528  *  0b001..Receive Queue 1
33529  *  0b010..Receive Queue 2
33530  *  0b011..Receive Queue 3
33531  *  0b100..Receive Queue 4
33532  *  0b101..Reserved
33533  *  0b110..Reserved
33534  *  0b111..Reserved
33535  */
33536 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK)
33537 
33538 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK         (0xFF0000U)
33539 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT        (16U)
33540 /*! PSRQ2 - Priorities Selected in the Receive Queue 2 */
33541 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK)
33542 
33543 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK       (0x100000U)
33544 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT      (20U)
33545 /*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast
33546  *    packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed
33547  *    to Rx Queue specified in MCBCQ field.
33548  *  0b0..Multicast and Broadcast Queue is disabled
33549  *  0b1..Multicast and Broadcast Queue is enabled
33550  */
33551 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK)
33552 
33553 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK        (0x200000U)
33554 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT       (21U)
33555 /*! TACPQE - Tagged AV Control Packets Queuing Enable.
33556  *  0b0..Tagged AV Control Packets Queuing is disabled
33557  *  0b1..Tagged AV Control Packets Queuing is enabled
33558  */
33559 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK)
33560 
33561 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK          (0xC00000U)
33562 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT         (22U)
33563 /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */
33564 #define ENET_QOS_MAC_RXQ_CTRL_TPQC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK)
33565 
33566 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK          (0x7000000U)
33567 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT         (24U)
33568 /*! FPRQ - Frame Preemption Residue Queue */
33569 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK)
33570 
33571 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK         (0xFF000000U)
33572 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT        (24U)
33573 /*! PSRQ3 - Priorities Selected in the Receive Queue 3 */
33574 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK)
33575 /*! @} */
33576 
33577 /* The count of ENET_QOS_MAC_RXQ_CTRL */
33578 #define ENET_QOS_MAC_RXQ_CTRL_COUNT              (4U)
33579 
33580 /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
33581 /*! @{ */
33582 
33583 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U)
33584 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
33585 /*! RGSMIIIS - RGMII or SMII Interrupt Status
33586  *  0b1..RGMII or SMII Interrupt Status is active
33587  *  0b0..RGMII or SMII Interrupt Status is not active
33588  */
33589 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK)
33590 
33591 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U)
33592 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
33593 /*! PHYIS - PHY Interrupt
33594  *  0b1..PHY Interrupt detected
33595  *  0b0..PHY Interrupt not detected
33596  */
33597 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK)
33598 
33599 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U)
33600 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
33601 /*! PMTIS - PMT Interrupt Status
33602  *  0b1..PMT Interrupt status active
33603  *  0b0..PMT Interrupt status not active
33604  */
33605 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK)
33606 
33607 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U)
33608 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
33609 /*! LPIIS - LPI Interrupt Status
33610  *  0b1..LPI Interrupt status active
33611  *  0b0..LPI Interrupt status not active
33612  */
33613 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK)
33614 
33615 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U)
33616 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
33617 /*! MMCIS - MMC Interrupt Status
33618  *  0b1..MMC Interrupt status active
33619  *  0b0..MMC Interrupt status not active
33620  */
33621 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK)
33622 
33623 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U)
33624 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
33625 /*! MMCRXIS - MMC Receive Interrupt Status
33626  *  0b1..MMC Receive Interrupt status active
33627  *  0b0..MMC Receive Interrupt status not active
33628  */
33629 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK)
33630 
33631 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U)
33632 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
33633 /*! MMCTXIS - MMC Transmit Interrupt Status
33634  *  0b1..MMC Transmit Interrupt status active
33635  *  0b0..MMC Transmit Interrupt status not active
33636  */
33637 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK)
33638 
33639 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U)
33640 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
33641 /*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status
33642  *  0b1..MMC Receive Checksum Offload Interrupt status active
33643  *  0b0..MMC Receive Checksum Offload Interrupt status not active
33644  */
33645 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK)
33646 
33647 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK  (0x1000U)
33648 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
33649 /*! TSIS - Timestamp Interrupt Status
33650  *  0b1..Timestamp Interrupt status active
33651  *  0b0..Timestamp Interrupt status not active
33652  */
33653 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK)
33654 
33655 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U)
33656 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
33657 /*! TXSTSIS - Transmit Status Interrupt
33658  *  0b1..Transmit Interrupt status active
33659  *  0b0..Transmit Interrupt status not active
33660  */
33661 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
33662 
33663 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U)
33664 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
33665 /*! RXSTSIS - Receive Status Interrupt
33666  *  0b1..Receive Interrupt status active
33667  *  0b0..Receive Interrupt status not active
33668  */
33669 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
33670 
33671 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U)
33672 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U)
33673 /*! FPEIS - Frame Preemption Interrupt Status
33674  *  0b1..Frame Preemption Interrupt status active
33675  *  0b0..Frame Preemption Interrupt status not active
33676  */
33677 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK)
33678 
33679 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U)
33680 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
33681 /*! MDIOIS - MDIO Interrupt Status
33682  *  0b1..MDIO Interrupt status active
33683  *  0b0..MDIO Interrupt status not active
33684  */
33685 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
33686 
33687 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U)
33688 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U)
33689 /*! MFTIS - MMC FPE Transmit Interrupt Status
33690  *  0b1..MMC FPE Transmit Interrupt status active
33691  *  0b0..MMC FPE Transmit Interrupt status not active
33692  */
33693 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK)
33694 
33695 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U)
33696 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U)
33697 /*! MFRIS - MMC FPE Receive Interrupt Status
33698  *  0b1..MMC FPE Receive Interrupt status active
33699  *  0b0..MMC FPE Receive Interrupt status not active
33700  */
33701 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK)
33702 /*! @} */
33703 
33704 /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
33705 /*! @{ */
33706 
33707 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U)
33708 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
33709 /*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the
33710  *    interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register.
33711  *  0b0..RGMII or SMII Interrupt is disabled
33712  *  0b1..RGMII or SMII Interrupt is enabled
33713  */
33714 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK)
33715 
33716 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U)
33717 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
33718 /*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
33719  *    signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS].
33720  *  0b0..PHY Interrupt is disabled
33721  *  0b1..PHY Interrupt is enabled
33722  */
33723 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
33724 
33725 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U)
33726 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
33727 /*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt
33728  *    signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS].
33729  *  0b0..PMT Interrupt is disabled
33730  *  0b1..PMT Interrupt is enabled
33731  */
33732 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
33733 
33734 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U)
33735 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
33736 /*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt
33737  *    signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS].
33738  *  0b0..LPI Interrupt is disabled
33739  *  0b1..LPI Interrupt is enabled
33740  */
33741 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
33742 
33743 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK  (0x1000U)
33744 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
33745 /*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the
33746  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS].
33747  *  0b0..Timestamp Interrupt is disabled
33748  *  0b1..Timestamp Interrupt is enabled
33749  */
33750 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK)
33751 
33752 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U)
33753 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
33754 /*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the
33755  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS].
33756  *  0b0..Timestamp Status Interrupt is disabled
33757  *  0b1..Timestamp Status Interrupt is enabled
33758  */
33759 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
33760 
33761 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U)
33762 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
33763 /*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the
33764  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS].
33765  *  0b0..Receive Status Interrupt is disabled
33766  *  0b1..Receive Status Interrupt is enabled
33767  */
33768 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
33769 
33770 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U)
33771 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U)
33772 /*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the
33773  *    interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS.
33774  *  0b0..Frame Preemption Interrupt is disabled
33775  *  0b1..Frame Preemption Interrupt is enabled
33776  */
33777 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK)
33778 
33779 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U)
33780 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
33781 /*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt
33782  *    when MDIOIS field is set in the MAC_INTERRUPT_STATUS register.
33783  *  0b0..MDIO Interrupt is disabled
33784  *  0b1..MDIO Interrupt is enabled
33785  */
33786 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
33787 /*! @} */
33788 
33789 /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
33790 /*! @{ */
33791 
33792 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK       (0x1U)
33793 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT      (0U)
33794 /*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which
33795  *    happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled)
33796  *    and JD bit is reset in the MAC_CONFIGURATION register.
33797  *  0b1..Transmit Jabber Timeout occurred
33798  *  0b0..No Transmit Jabber Timeout
33799  */
33800 #define ENET_QOS_MAC_RX_TX_STATUS_TJT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK)
33801 
33802 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK     (0x2U)
33803 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT    (1U)
33804 /*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
33805  *    indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
33806  *  0b1..No carrier
33807  *  0b0..Carrier is present
33808  */
33809 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK)
33810 
33811 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK     (0x4U)
33812 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT    (2U)
33813 /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
33814  *    indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i
33815  *    signal was inactive for one or more transmission clock periods during packet transmission.
33816  *  0b1..Loss of carrier
33817  *  0b0..Carrier is present
33818  */
33819 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK)
33820 
33821 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK     (0x8U)
33822 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT    (3U)
33823 /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the
33824  *    DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission
33825  *    ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or
33826  *    when Jumbo packet is enabled).
33827  *  0b1..Excessive deferral
33828  *  0b0..No Excessive deferral
33829  */
33830 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK)
33831 
33832 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK      (0x10U)
33833 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT     (4U)
33834 /*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
33835  *    indicates that the packet transmission aborted because a collision occurred after the collision
33836  *    window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier
33837  *    Extension in GMII mode).
33838  *  0b1..Late collision is sensed
33839  *  0b0..No collision
33840  */
33841 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK)
33842 
33843 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK     (0x20U)
33844 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT    (5U)
33845 /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this
33846  *    bit indicates that the transmission aborted after 16 successive collisions while attempting
33847  *    to transmit the current packet.
33848  *  0b1..Excessive collision is sensed
33849  *  0b0..No collision
33850  */
33851 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK)
33852 
33853 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK       (0x100U)
33854 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT      (8U)
33855 /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
33856  *    bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
33857  *    MAC_CONFIGURATION register.
33858  *  0b1..Receive watchdog timed out
33859  *  0b0..No receive watchdog timeout
33860  */
33861 #define ENET_QOS_MAC_RX_TX_STATUS_RWT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK)
33862 /*! @} */
33863 
33864 /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
33865 /*! @{ */
33866 
33867 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U)
33868 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
33869 /*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it
33870  *    receives the expected magic packet or remote wake-up packet.
33871  *  0b0..Power down is disabled
33872  *  0b1..Power down is enabled
33873  */
33874 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
33875 
33876 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
33877 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
33878 /*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet.
33879  *  0b0..Magic Packet is disabled
33880  *  0b1..Magic Packet is enabled
33881  */
33882 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
33883 
33884 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
33885 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
33886 /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
33887  *    generated when the MAC receives a remote wake-up packet.
33888  *  0b0..Remote wake-up packet is disabled
33889  *  0b1..Remote wake-up packet is enabled
33890  */
33891 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
33892 
33893 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
33894 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
33895 /*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management
33896  *    event is generated because of the reception of a magic packet.
33897  *  0b1..Magic packet is received
33898  *  0b0..No Magic packet is received
33899  */
33900 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
33901 
33902 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
33903 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
33904 /*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power
33905  *    management event is generated because of the reception of a remote wake-up packet.
33906  *  0b1..Remote wake-up packet is received
33907  *  0b0..Remote wake-up packet is received
33908  */
33909 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
33910 
33911 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
33912 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
33913 /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
33914  *    address recognition is detected as a remote wake-up packet.
33915  *  0b0..Global unicast is disabled
33916  *  0b1..Global unicast is enabled
33917  */
33918 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
33919 
33920 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U)
33921 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
33922 /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
33923  *    MAC receiver drops all received frames until it receives the expected Wake-up frame.
33924  *  0b0..Remote Wake-up Packet Forwarding is disabled
33925  *  0b1..Remote Wake-up Packet Forwarding is enabled
33926  */
33927 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
33928 
33929 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U)
33930 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
33931 /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when
33932  *    4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter
33933  *    register pointer.
33934  */
33935 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
33936 
33937 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
33938 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
33939 /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
33940  *    remote wake-up packet filter register pointer is reset to 3'b000.
33941  *  0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
33942  *  0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
33943  */
33944 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
33945 /*! @} */
33946 
33947 /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
33948 /*! @{ */
33949 
33950 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
33951 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
33952 /*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter. */
33953 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
33954 /*! @} */
33955 
33956 /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
33957 /*! @{ */
33958 
33959 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U)
33960 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
33961 /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
33962  *    entered the LPI state because of the setting of the LPIEN bit.
33963  *  0b1..Transmit LPI entry detected
33964  *  0b0..Transmit LPI entry not detected
33965  */
33966 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
33967 
33968 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U)
33969 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
33970 /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
33971  *    the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
33972  *  0b1..Transmit LPI exit detected
33973  *  0b0..Transmit LPI exit not detected
33974  */
33975 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
33976 
33977 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U)
33978 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
33979 /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
33980  *    an LPI pattern and entered the LPI state.
33981  *  0b1..Receive LPI entry detected
33982  *  0b0..Receive LPI entry not detected
33983  */
33984 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
33985 
33986 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U)
33987 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
33988 /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
33989  *    receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the
33990  *    normal reception.
33991  *  0b1..Receive LPI exit detected
33992  *  0b0..Receive LPI exit not detected
33993  */
33994 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
33995 
33996 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U)
33997 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
33998 /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the
33999  *    LPI pattern on the GMII or MII interface.
34000  *  0b1..Transmit LPI state detected
34001  *  0b0..Transmit LPI state not detected
34002  */
34003 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
34004 
34005 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U)
34006 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
34007 /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI
34008  *    pattern on the GMII or MII interface.
34009  *  0b1..Receive LPI state detected
34010  *  0b0..Receive LPI state not detected
34011  */
34012 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
34013 
34014 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U)
34015 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
34016 /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
34017  *  0b0..LPI state is disabled
34018  *  0b1..LPI state is enabled
34019  */
34020 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
34021 
34022 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U)
34023 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
34024 /*! PLS - PHY Link Status This bit indicates the link status of the PHY.
34025  *  0b0..link is down
34026  *  0b1..link is okay (UP)
34027  */
34028 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK)
34029 
34030 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U)
34031 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
34032 /*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or
34033  *    SMII Receive paths to be used for activating the LPI LS TIMER.
34034  *  0b0..PHY Link Status is disabled
34035  *  0b1..PHY Link Status is enabled
34036  */
34037 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK)
34038 
34039 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U)
34040 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
34041 /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
34042  *    out of the LPI mode on the Transmit side.
34043  *  0b0..LPI Tx Automate is disabled
34044  *  0b1..LPI Tx Automate is enabled
34045  */
34046 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
34047 
34048 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U)
34049 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
34050 /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
34051  *  0b0..LPI Timer is disabled
34052  *  0b1..LPI Timer is enabled
34053  */
34054 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
34055 
34056 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
34057 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
34058 /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts
34059  *    sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
34060  *  0b0..LPI Tx Clock Stop is disabled
34061  *  0b1..LPI Tx Clock Stop is enabled
34062  */
34063 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
34064 /*! @} */
34065 
34066 /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
34067 /*! @{ */
34068 
34069 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU)
34070 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
34071 /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
34072  *    waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
34073  *    transmission.
34074  */
34075 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
34076 
34077 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U)
34078 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
34079 /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
34080  *    status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
34081  */
34082 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK)
34083 /*! @} */
34084 
34085 /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
34086 /*! @{ */
34087 
34088 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK  (0xFFFF8U)
34089 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
34090 /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI
34091  *    mode, after it has transmitted all the frames.
34092  */
34093 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
34094 /*! @} */
34095 
34096 /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
34097 /*! @{ */
34098 
34099 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
34100 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
34101 /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. */
34102 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
34103 /*! @} */
34104 
34105 /*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */
34106 /*! @{ */
34107 
34108 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U)
34109 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
34110 /*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission
34111  *    of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or
34112  *    SGMII port.
34113  *  0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII
34114  *  0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII
34115  */
34116 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK)
34117 
34118 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U)
34119 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
34120 /*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of
34121  *    configuration in the RGMII, SGMII, or SMII interface.
34122  *  0b0..Link down
34123  *  0b1..Link up
34124  */
34125 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK)
34126 
34127 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U)
34128 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
34129 /*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link.
34130  *  0b1..Full-duplex mode
34131  *  0b0..Half-duplex mode
34132  */
34133 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK)
34134 
34135 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U)
34136 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
34137 /*! LNKSPEED - Link Speed This bit indicates the current speed of the link.
34138  *  0b10..125 MHz
34139  *  0b00..2.5 MHz
34140  *  0b01..25 MHz
34141  *  0b11..Reserved
34142  */
34143 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK)
34144 
34145 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U)
34146 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
34147 /*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0).
34148  *  0b1..Link up
34149  *  0b0..Link down
34150  */
34151 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK)
34152 /*! @} */
34153 
34154 /*! @name MAC_VERSION - MAC Version */
34155 /*! @{ */
34156 
34157 #define ENET_QOS_MAC_VERSION_SNPSVER_MASK        (0xFFU)
34158 #define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT       (0U)
34159 /*! SNPSVER - Synopsys-defined Version */
34160 #define ENET_QOS_MAC_VERSION_SNPSVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK)
34161 
34162 #define ENET_QOS_MAC_VERSION_USERVER_MASK        (0xFF00U)
34163 #define ENET_QOS_MAC_VERSION_USERVER_SHIFT       (8U)
34164 /*! USERVER - User-defined Version (8'h10) */
34165 #define ENET_QOS_MAC_VERSION_USERVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK)
34166 /*! @} */
34167 
34168 /*! @name MAC_DEBUG - MAC Debug */
34169 /*! @{ */
34170 
34171 #define ENET_QOS_MAC_DEBUG_RPESTS_MASK           (0x1U)
34172 #define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT          (0U)
34173 /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that
34174  *    the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the
34175  *    Idle state.
34176  *  0b1..MAC GMII or MII Receive Protocol Engine Status detected
34177  *  0b0..MAC GMII or MII Receive Protocol Engine Status not detected
34178  */
34179 #define ENET_QOS_MAC_DEBUG_RPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK)
34180 
34181 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK         (0x6U)
34182 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT        (1U)
34183 /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
34184  *    the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
34185  *    Controller module.
34186  */
34187 #define ENET_QOS_MAC_DEBUG_RFCFCSTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK)
34188 
34189 #define ENET_QOS_MAC_DEBUG_TPESTS_MASK           (0x10000U)
34190 #define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT          (16U)
34191 /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that
34192  *    the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in
34193  *    the Idle state.
34194  *  0b1..MAC GMII or MII Transmit Protocol Engine Status detected
34195  *  0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
34196  */
34197 #define ENET_QOS_MAC_DEBUG_TPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK)
34198 
34199 #define ENET_QOS_MAC_DEBUG_TFCSTS_MASK           (0x60000U)
34200 #define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT          (17U)
34201 /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
34202  *  0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
34203  *  0b00..Idle state
34204  *  0b11..Transferring input packet for transmission
34205  *  0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
34206  */
34207 #define ENET_QOS_MAC_DEBUG_TFCSTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK)
34208 /*! @} */
34209 
34210 /*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */
34211 /*! @{ */
34212 
34213 #define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK         (0x1U)
34214 #define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT        (0U)
34215 /*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
34216  *  0b1..10 or 100 Mbps support
34217  *  0b0..No 10 or 100 Mbps support
34218  */
34219 #define ENET_QOS_MAC_HW_FEAT_MIISEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK)
34220 
34221 #define ENET_QOS_MAC_HW_FEAT_NRVF_MASK           (0x7U)
34222 #define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT          (0U)
34223 /*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:
34224  *  0b011..16 Extended Rx VLAN Filters
34225  *  0b100..24 Extended Rx VLAN Filters
34226  *  0b101..32 Extended Rx VLAN Filters
34227  *  0b001..4 Extended Rx VLAN Filters
34228  *  0b010..8 Extended Rx VLAN Filters
34229  *  0b000..No Extended Rx VLAN Filters
34230  *  0b110..Reserved
34231  */
34232 #define ENET_QOS_MAC_HW_FEAT_NRVF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK)
34233 
34234 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK     (0x1FU)
34235 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT    (0U)
34236 /*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in
34237  *    bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
34238  *  0b00011..1024 bytes
34239  *  0b00000..128 bytes
34240  *  0b01010..128 KB
34241  *  0b00111..16384 bytes
34242  *  0b00100..2048 bytes
34243  *  0b00001..256 bytes
34244  *  0b01011..256 KB
34245  *  0b01000..32 KB
34246  *  0b00101..4096 bytes
34247  *  0b00010..512 bytes
34248  *  0b01001..64 KB
34249  *  0b00110..8192 bytes
34250  *  0b01100..Reserved
34251  */
34252 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK)
34253 
34254 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK         (0xFU)
34255 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT        (0U)
34256 /*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues:
34257  *  0b0000..1 MTL Rx Queue
34258  *  0b0001..2 MTL Rx Queues
34259  *  0b0010..3 MTL Rx Queues
34260  *  0b0011..4 MTL Rx Queues
34261  *  0b0100..5 MTL Rx Queues
34262  *  0b0101..Reserved
34263  *  0b0110..Reserved
34264  *  0b0111..Reserved
34265  */
34266 #define ENET_QOS_MAC_HW_FEAT_RXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK)
34267 
34268 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK        (0x2U)
34269 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT       (1U)
34270 /*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
34271  *  0b1..1000 Mbps support
34272  *  0b0..No 1000 Mbps support
34273  */
34274 #define ENET_QOS_MAC_HW_FEAT_GMIISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK)
34275 
34276 #define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK          (0x4U)
34277 #define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT         (2U)
34278 /*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected
34279  *  0b1..Half-duplex support
34280  *  0b0..No Half-duplex support
34281  */
34282 #define ENET_QOS_MAC_HW_FEAT_HDSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK)
34283 
34284 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK         (0x8U)
34285 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT        (3U)
34286 /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI,
34287  *    SGMII, or RTBI PHY interface option is selected
34288  *  0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
34289  *  0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
34290  */
34291 #define ENET_QOS_MAC_HW_FEAT_PCSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK)
34292 
34293 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK        (0x10U)
34294 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT       (4U)
34295 /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the
34296  *    Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
34297  *  0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
34298  *  0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
34299  */
34300 #define ENET_QOS_MAC_HW_FEAT_CBTISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK)
34301 
34302 #define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK         (0x10U)
34303 #define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT        (4U)
34304 /*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
34305  *  0b1..VLAN Hash Filter selected
34306  *  0b0..VLAN Hash Filter not selected
34307  */
34308 #define ENET_QOS_MAC_HW_FEAT_VLHASH(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK)
34309 
34310 #define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK          (0x20U)
34311 #define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT         (5U)
34312 /*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.
34313  *  0b1..Double VLAN option is selected
34314  *  0b0..Double VLAN option is not selected
34315  */
34316 #define ENET_QOS_MAC_HW_FEAT_DVLAN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK)
34317 
34318 #define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK         (0x20U)
34319 #define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT        (5U)
34320 /*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
34321  *  0b1..SMA (MDIO) Interface selected
34322  *  0b0..SMA (MDIO) Interface not selected
34323  */
34324 #define ENET_QOS_MAC_HW_FEAT_SMASEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK)
34325 
34326 #define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK          (0x20U)
34327 #define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT         (5U)
34328 /*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected.
34329  *  0b1..Single Port RAM feature is selected
34330  *  0b0..Single Port RAM feature is not selected
34331  */
34332 #define ENET_QOS_MAC_HW_FEAT_SPRAM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK)
34333 
34334 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK         (0x40U)
34335 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT        (6U)
34336 /*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
34337  *  0b1..PMT Remote Wake-up Packet Enable option is selected
34338  *  0b0..PMT Remote Wake-up Packet Enable option is not selected
34339  */
34340 #define ENET_QOS_MAC_HW_FEAT_RWKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK)
34341 
34342 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK     (0x7C0U)
34343 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT    (6U)
34344 /*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in
34345  *    bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
34346  *  0b00011..1024 bytes
34347  *  0b00000..128 bytes
34348  *  0b01010..128 KB
34349  *  0b00111..16384 bytes
34350  *  0b00100..2048 bytes
34351  *  0b00001..256 bytes
34352  *  0b01000..32 KB
34353  *  0b00101..4096 bytes
34354  *  0b00010..512 bytes
34355  *  0b01001..64 KB
34356  *  0b00110..8192 bytes
34357  *  0b01011..Reserved
34358  */
34359 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK)
34360 
34361 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK         (0x3C0U)
34362 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT        (6U)
34363 /*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:
34364  *  0b0000..1 MTL Tx Queue
34365  *  0b0001..2 MTL Tx Queues
34366  *  0b0010..3 MTL Tx Queues
34367  *  0b0011..4 MTL Tx Queues
34368  *  0b0100..5 MTL Tx Queues
34369  *  0b0101..Reserved
34370  *  0b0110..Reserved
34371  *  0b0111..Reserved
34372  */
34373 #define ENET_QOS_MAC_HW_FEAT_TXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK)
34374 
34375 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK         (0x80U)
34376 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT        (7U)
34377 /*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected
34378  *  0b1..PMT Magic Packet Enable option is selected
34379  *  0b0..PMT Magic Packet Enable option is not selected
34380  */
34381 #define ENET_QOS_MAC_HW_FEAT_MGKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK)
34382 
34383 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK         (0x100U)
34384 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT        (8U)
34385 /*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
34386  *  0b1..RMON Module Enable option is selected
34387  *  0b0..RMON Module Enable option is not selected
34388  */
34389 #define ENET_QOS_MAC_HW_FEAT_MMCSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK)
34390 
34391 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK      (0x200U)
34392 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT     (9U)
34393 /*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
34394  *  0b1..ARP Offload Enable option is selected
34395  *  0b0..ARP Offload Enable option is not selected
34396  */
34397 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK)
34398 
34399 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK        (0x200U)
34400 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT       (9U)
34401 /*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the
34402  *    Broadcast/Multicast Packet Duplication feature is selected.
34403  *  0b1..Broadcast/Multicast Packet Duplication feature is selected
34404  *  0b0..Broadcast/Multicast Packet Duplication feature is not selected
34405  */
34406 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK)
34407 
34408 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK         (0x400U)
34409 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT        (10U)
34410 /*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible
34411  *    Programmable Receive Parser option is selected.
34412  *  0b1..Flexible Receive Parser feature is selected
34413  *  0b0..Flexible Receive Parser feature is not selected
34414  */
34415 #define ENET_QOS_MAC_HW_FEAT_FRPSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK)
34416 
34417 #define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK          (0x1800U)
34418 #define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT         (11U)
34419 /*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of
34420  *    bytes of the packet data to be Parsed by Flexible Receive Parser.
34421  *  0b01..128 Bytes
34422  *  0b10..256 Bytes
34423  *  0b00..64 Bytes
34424  *  0b11..Reserved
34425  */
34426 #define ENET_QOS_MAC_HW_FEAT_FRPBS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK)
34427 
34428 #define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK          (0x800U)
34429 #define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT         (11U)
34430 /*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
34431  *  0b1..One-Step Timestamping feature is selected
34432  *  0b0..One-Step Timestamping feature is not selected
34433  */
34434 #define ENET_QOS_MAC_HW_FEAT_OSTEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK)
34435 
34436 #define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK          (0x1000U)
34437 #define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT         (12U)
34438 /*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
34439  *  0b1..PTP Offload feature is selected
34440  *  0b0..PTP Offload feature is not selected
34441  */
34442 #define ENET_QOS_MAC_HW_FEAT_PTOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK)
34443 
34444 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK        (0xF000U)
34445 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT       (12U)
34446 /*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels:
34447  *  0b0000..1 MTL Rx Channel
34448  *  0b0001..2 MTL Rx Channels
34449  *  0b0010..3 MTL Rx Channels
34450  *  0b0011..4 MTL Rx Channels
34451  *  0b0100..5 MTL Rx Channels
34452  *  0b0101..Reserved
34453  *  0b0110..Reserved
34454  *  0b0111..Reserved
34455  */
34456 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK)
34457 
34458 #define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK          (0x1000U)
34459 #define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT         (12U)
34460 /*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
34461  *  0b1..IEEE 1588-2008 Timestamp Enable option is selected
34462  *  0b0..IEEE 1588-2008 Timestamp Enable option is not selected
34463  */
34464 #define ENET_QOS_MAC_HW_FEAT_TSSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK)
34465 
34466 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK      (0x2000U)
34467 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT     (13U)
34468 /*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
34469  *  0b1..IEEE 1588 High Word Register option is selected
34470  *  0b0..IEEE 1588 High Word Register option is not selected
34471  */
34472 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK)
34473 
34474 #define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK         (0x2000U)
34475 #define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT        (13U)
34476 /*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient
34477  *    Ethernet (EEE) option is selected
34478  *  0b1..Energy Efficient Ethernet Enable option is selected
34479  *  0b0..Energy Efficient Ethernet Enable option is not selected
34480  */
34481 #define ENET_QOS_MAC_HW_FEAT_EEESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK)
34482 
34483 #define ENET_QOS_MAC_HW_FEAT_FRPES_MASK          (0x6000U)
34484 #define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT         (13U)
34485 /*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser
34486  *    Entries supported by Flexible Receive Parser.
34487  *  0b01..128 Entries
34488  *  0b10..256 Entries
34489  *  0b00..64 Entries
34490  *  0b11..Reserved
34491  */
34492 #define ENET_QOS_MAC_HW_FEAT_FRPES(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK)
34493 
34494 #define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK         (0xC000U)
34495 #define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT        (14U)
34496 /*! ADDR64 - Address Width.
34497  *  0b00..32
34498  *  0b01..40
34499  *  0b10..48
34500  *  0b11..Reserved
34501  */
34502 #define ENET_QOS_MAC_HW_FEAT_ADDR64(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK)
34503 
34504 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK       (0x4000U)
34505 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT      (14U)
34506 /*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit
34507  *    TCP/IP Checksum Insertion option is selected
34508  *  0b1..Transmit Checksum Offload Enable option is selected
34509  *  0b0..Transmit Checksum Offload Enable option is not selected
34510  */
34511 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK)
34512 
34513 #define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK          (0x10000U)
34514 #define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT         (16U)
34515 /*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected
34516  *  0b1..DCB Feature is selected
34517  *  0b0..DCB Feature is not selected
34518  */
34519 #define ENET_QOS_MAC_HW_FEAT_DCBEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK)
34520 
34521 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK         (0x10000U)
34522 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT        (16U)
34523 /*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable
34524  *    Enhancements to Scheduling Traffic feature is selected.
34525  *  0b1..Enable Enhancements to Scheduling Traffic feature is selected
34526  *  0b0..Enable Enhancements to Scheduling Traffic feature is not selected
34527  */
34528 #define ENET_QOS_MAC_HW_FEAT_ESTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK)
34529 
34530 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK       (0x10000U)
34531 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT      (16U)
34532 /*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
34533  *  0b1..Receive Checksum Offload Enable option is selected
34534  *  0b0..Receive Checksum Offload Enable option is not selected
34535  */
34536 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK)
34537 
34538 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK         (0xE0000U)
34539 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT        (17U)
34540 /*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
34541  *  0b101..1024
34542  *  0b010..128
34543  *  0b011..256
34544  *  0b100..512
34545  *  0b001..64
34546  *  0b000..No Depth configured
34547  *  0b110..Reserved
34548  */
34549 #define ENET_QOS_MAC_HW_FEAT_ESTDEP(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK)
34550 
34551 #define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK          (0x20000U)
34552 #define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT         (17U)
34553 /*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected
34554  *  0b1..Split Header Feature is selected
34555  *  0b0..Split Header Feature is not selected
34556  */
34557 #define ENET_QOS_MAC_HW_FEAT_SPHEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK)
34558 
34559 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK   (0x7C0000U)
34560 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT  (18U)
34561 /*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is
34562  *    selected for Enable Additional 1-31 MAC Address Registers option
34563  */
34564 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK)
34565 
34566 #define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK          (0x40000U)
34567 #define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT         (18U)
34568 /*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation
34569  *    Offloading for TCP/IP Packets option is selected
34570  *  0b1..TCP Segmentation Offload Feature is selected
34571  *  0b0..TCP Segmentation Offload Feature is not selected
34572  */
34573 #define ENET_QOS_MAC_HW_FEAT_TSOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK)
34574 
34575 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK        (0x3C0000U)
34576 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT       (18U)
34577 /*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:
34578  *  0b0000..1 MTL Tx Channel
34579  *  0b0001..2 MTL Tx Channels
34580  *  0b0010..3 MTL Tx Channels
34581  *  0b0011..4 MTL Tx Channels
34582  *  0b0100..5 MTL Tx Channels
34583  *  0b0101..Reserved
34584  *  0b0110..Reserved
34585  *  0b0111..Reserved
34586  */
34587 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK)
34588 
34589 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK        (0x80000U)
34590 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT       (19U)
34591 /*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected
34592  *  0b1..DMA Debug Registers option is selected
34593  *  0b0..DMA Debug Registers option is not selected
34594  */
34595 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK)
34596 
34597 #define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK          (0x100000U)
34598 #define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT         (20U)
34599 /*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected.
34600  *  0b1..AV Feature is selected
34601  *  0b0..AV Feature is not selected
34602  */
34603 #define ENET_QOS_MAC_HW_FEAT_AVSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK)
34604 
34605 #define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK         (0x300000U)
34606 #define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT        (20U)
34607 /*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the
34608  *    width of the Configured Time Interval Field
34609  *  0b00..Width not configured
34610  *  0b01..16
34611  *  0b10..20
34612  *  0b11..24
34613  */
34614 #define ENET_QOS_MAC_HW_FEAT_ESTWID(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK)
34615 
34616 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK         (0x200000U)
34617 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT        (21U)
34618 /*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video
34619  *    Bridging option on Rx Side Only is selected.
34620  *  0b1..Rx Side Only AV Feature is selected
34621  *  0b0..Rx Side Only AV Feature is not selected
34622  */
34623 #define ENET_QOS_MAC_HW_FEAT_RAVSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK)
34624 
34625 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK    (0x800000U)
34626 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT   (23U)
34627 /*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32
34628  *    MAC Address Registers (32-63) option is selected
34629  *  0b1..MAC Addresses 32-63 Select option is selected
34630  *  0b0..MAC Addresses 32-63 Select option is not selected
34631  */
34632 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK)
34633 
34634 #define ENET_QOS_MAC_HW_FEAT_POUOST_MASK         (0x800000U)
34635 #define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT        (23U)
34636 /*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One
34637  *    step timestamp for PTP over UDP/IP feature is selected.
34638  *  0b1..One Step for PTP over UDP/IP Feature is selected
34639  *  0b0..One Step for PTP over UDP/IP Feature is not selected
34640  */
34641 #define ENET_QOS_MAC_HW_FEAT_POUOST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK)
34642 
34643 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK      (0x3000000U)
34644 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT     (24U)
34645 /*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table:
34646  *  0b10..128
34647  *  0b11..256
34648  *  0b01..64
34649  *  0b00..No hash table
34650  */
34651 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK)
34652 
34653 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK    (0x1000000U)
34654 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT   (24U)
34655 /*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64
34656  *    MAC Address Registers (64-127) option is selected
34657  *  0b1..MAC Addresses 64-127 Select option is selected
34658  *  0b0..MAC Addresses 64-127 Select option is not selected
34659  */
34660 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK)
34661 
34662 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK      (0x7000000U)
34663 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT     (24U)
34664 /*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs:
34665  *  0b001..1 PPS output
34666  *  0b010..2 PPS output
34667  *  0b011..3 PPS output
34668  *  0b100..4 PPS output
34669  *  0b000..No PPS output
34670  *  0b101..Reserved
34671  */
34672 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK)
34673 
34674 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK       (0x6000000U)
34675 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT      (25U)
34676 /*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system
34677  *    time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
34678  *  0b10..Both
34679  *  0b01..External
34680  *  0b00..Internal
34681  *  0b11..Reserved
34682  */
34683 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK)
34684 
34685 #define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK         (0x4000000U)
34686 #define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT        (26U)
34687 /*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected.
34688  *  0b1..Frame Preemption Enable feature is selected
34689  *  0b0..Frame Preemption Enable feature is not selected
34690  */
34691 #define ENET_QOS_MAC_HW_FEAT_FPESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK)
34692 
34693 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK       (0x78000000U)
34694 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT      (27U)
34695 /*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:
34696  *  0b0001..1 L3 or L4 Filter
34697  *  0b0010..2 L3 or L4 Filters
34698  *  0b0011..3 L3 or L4 Filters
34699  *  0b0100..4 L3 or L4 Filters
34700  *  0b0101..5 L3 or L4 Filters
34701  *  0b0110..6 L3 or L4 Filters
34702  *  0b0111..7 L3 or L4 Filters
34703  *  0b1000..8 L3 or L4 Filters
34704  *  0b0000..No L3 or L4 Filter
34705  */
34706 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK)
34707 
34708 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK      (0x8000000U)
34709 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT     (27U)
34710 /*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and
34711  *    VLAN Insertion on Tx option is selected
34712  *  0b1..Source Address or VLAN Insertion Enable option is selected
34713  *  0b0..Source Address or VLAN Insertion Enable option is not selected
34714  */
34715 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK)
34716 
34717 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK         (0x8000000U)
34718 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT        (27U)
34719 /*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected.
34720  *  0b1..Time Based Scheduling Enable feature is selected
34721  *  0b0..Time Based Scheduling Enable feature is not selected
34722  */
34723 #define ENET_QOS_MAC_HW_FEAT_TBSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK)
34724 
34725 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK      (0x70000000U)
34726 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT     (28U)
34727 /*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration,
34728  *    this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
34729  *  0b000..GMII or MII
34730  *  0b111..RevMII
34731  *  0b001..RGMII
34732  *  0b100..RMII
34733  *  0b101..RTBI
34734  *  0b010..SGMII
34735  *  0b110..SMII
34736  *  0b011..TBI
34737  */
34738 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK)
34739 
34740 #define ENET_QOS_MAC_HW_FEAT_ASP_MASK            (0x30000000U)
34741 #define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT           (28U)
34742 /*! ASP - Automotive Safety Package Following are the encoding for the different Safety features
34743  *  0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
34744  *  0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
34745  *  0b01..Only "ECC protection for external memory" feature is selected
34746  *  0b00..No Safety features selected
34747  */
34748 #define ENET_QOS_MAC_HW_FEAT_ASP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK)
34749 
34750 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK     (0x70000000U)
34751 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT    (28U)
34752 /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:
34753  *  0b001..1 auxiliary input
34754  *  0b010..2 auxiliary input
34755  *  0b011..3 auxiliary input
34756  *  0b100..4 auxiliary input
34757  *  0b000..No auxiliary input
34758  *  0b101..Reserved
34759  */
34760 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK)
34761 /*! @} */
34762 
34763 /* The count of ENET_QOS_MAC_HW_FEAT */
34764 #define ENET_QOS_MAC_HW_FEAT_COUNT               (4U)
34765 
34766 /*! @name MAC_MDIO_ADDRESS - MDIO Address */
34767 /*! @{ */
34768 
34769 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK        (0x1U)
34770 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT       (0U)
34771 /*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave.
34772  *  0b0..GMII Busy is disabled
34773  *  0b1..GMII Busy is enabled
34774  */
34775 #define ENET_QOS_MAC_MDIO_ADDRESS_GB(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK)
34776 
34777 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK      (0x2U)
34778 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT     (1U)
34779 /*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO.
34780  *  0b0..Clause 45 PHY is disabled
34781  *  0b1..Clause 45 PHY is enabled
34782  */
34783 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK)
34784 
34785 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK     (0x4U)
34786 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT    (2U)
34787 /*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII.
34788  *  0b0..GMII Operation Command 0 is disabled
34789  *  0b1..GMII Operation Command 0 is enabled
34790  */
34791 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK)
34792 
34793 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK     (0x8U)
34794 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT    (3U)
34795 /*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or
34796  *    RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read
34797  *    Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write
34798  *    and Read commands are valid.
34799  *  0b0..GMII Operation Command 1 is disabled
34800  *  0b1..GMII Operation Command 1 is enabled
34801  */
34802 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK)
34803 
34804 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK      (0x10U)
34805 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT     (4U)
34806 /*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets
34807  *    before read, write, or post-read increment address packets.
34808  *  0b0..Skip Address Packet is disabled
34809  *  0b1..Skip Address Packet is enabled
34810  */
34811 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK)
34812 
34813 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK        (0xF00U)
34814 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT       (8U)
34815 /*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock
34816  *    according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC
34817  *    clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock
34818  *    = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
34819  *    - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz;
34820  *    MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR
34821  *    clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency
34822  *    applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.
34823  */
34824 #define ENET_QOS_MAC_MDIO_ADDRESS_CR(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK)
34825 
34826 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK       (0x7000U)
34827 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT      (12U)
34828 /*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles
34829  *    generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame.
34830  */
34831 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK)
34832 
34833 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK       (0x1F0000U)
34834 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT      (16U)
34835 /*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. */
34836 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK)
34837 
34838 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK        (0x3E00000U)
34839 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT       (21U)
34840 /*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. */
34841 #define ENET_QOS_MAC_MDIO_ADDRESS_PA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK)
34842 
34843 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK       (0x4000000U)
34844 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT      (26U)
34845 /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
34846  *    the MAC informs the completion of a read or write command at the end of frame transfer (before
34847  *    the trailing clocks are transmitted).
34848  *  0b0..Back to Back transactions disabled
34849  *  0b1..Back to Back transactions enabled
34850  */
34851 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK)
34852 
34853 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK       (0x8000000U)
34854 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT      (27U)
34855 /*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble
34856  *    and transmits MDIO frames with only 1 preamble bit.
34857  *  0b0..Preamble Suppression disabled
34858  *  0b1..Preamble Suppression enabled
34859  */
34860 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK)
34861 /*! @} */
34862 
34863 /*! @name MAC_MDIO_DATA - MAC MDIO Data */
34864 /*! @{ */
34865 
34866 #define ENET_QOS_MAC_MDIO_DATA_GD_MASK           (0xFFFFU)
34867 #define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT          (0U)
34868 /*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a
34869  *    Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a
34870  *    Management Write operation.
34871  */
34872 #define ENET_QOS_MAC_MDIO_DATA_GD(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK)
34873 
34874 #define ENET_QOS_MAC_MDIO_DATA_RA_MASK           (0xFFFF0000U)
34875 #define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT          (16U)
34876 /*! RA - Register Address This field is valid only when C45E is set. */
34877 #define ENET_QOS_MAC_MDIO_DATA_RA(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK)
34878 /*! @} */
34879 
34880 /*! @name MAC_CSR_SW_CTRL - CSR Software Control */
34881 /*! @{ */
34882 
34883 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK       (0x1U)
34884 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT      (0U)
34885 /*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register
34886  *    fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to
34887  *    clear it.
34888  *  0b0..Register Clear on Write 1 is disabled
34889  *  0b1..Register Clear on Write 1 is enabled
34890  */
34891 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK)
34892 /*! @} */
34893 
34894 /*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */
34895 /*! @{ */
34896 
34897 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK      (0x1U)
34898 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT     (0U)
34899 /*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled.
34900  *  0b0..Tx Frame Preemption is disabled
34901  *  0b1..Tx Frame Preemption is enabled
34902  */
34903 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK)
34904 
34905 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK      (0x2U)
34906 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT     (1U)
34907 /*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket.
34908  *  0b0..Send Verify mPacket is disabled
34909  *  0b1..Send Verify mPacket is enabled
34910  */
34911 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK)
34912 
34913 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK      (0x4U)
34914 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT     (2U)
34915 /*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket.
34916  *  0b0..Send Respond mPacket is disabled
34917  *  0b1..Send Respond mPacket is enabled
34918  */
34919 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK)
34920 
34921 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK  (0x8U)
34922 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U)
34923 /*! S1_SET_0 - Synopsys Reserved, Must be set to "0". */
34924 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK)
34925 
34926 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK      (0x10000U)
34927 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT     (16U)
34928 /*! RVER - Received Verify Frame Set when a Verify mPacket is received.
34929  *  0b1..Received Verify Frame
34930  *  0b0..Not received Verify Frame
34931  */
34932 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK)
34933 
34934 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK      (0x20000U)
34935 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT     (17U)
34936 /*! RRSP - Received Respond Frame Set when a Respond mPacket is received.
34937  *  0b1..Received Respond Frame
34938  *  0b0..Not received Respond Frame
34939  */
34940 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK)
34941 
34942 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK      (0x40000U)
34943 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT     (18U)
34944 /*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field).
34945  *  0b1..transmitted Verify Frame
34946  *  0b0..Not transmitted Verify Frame
34947  */
34948 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK)
34949 
34950 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK      (0x80000U)
34951 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT     (19U)
34952 /*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field).
34953  *  0b1..transmitted Respond Frame
34954  *  0b0..Not transmitted Respond Frame
34955  */
34956 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK)
34957 /*! @} */
34958 
34959 /*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */
34960 /*! @{ */
34961 
34962 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK     (0xFFFFFFFFU)
34963 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT    (0U)
34964 /*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary
34965  *    rollover equivalent time of the PTP System Time in ns
34966  */
34967 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK)
34968 /*! @} */
34969 
34970 /*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */
34971 /*! @{ */
34972 
34973 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK   (0xFFFFFFFFU)
34974 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT  (0U)
34975 /*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. */
34976 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK)
34977 /*! @} */
34978 
34979 /*! @name HIGH - MAC Address0 High..MAC Address63 High */
34980 /*! @{ */
34981 
34982 #define ENET_QOS_HIGH_ADDRHI_MASK                (0xFFFFU)
34983 #define ENET_QOS_HIGH_ADDRHI_SHIFT               (0U)
34984 /*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. */
34985 #define ENET_QOS_HIGH_ADDRHI(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK)
34986 
34987 #define ENET_QOS_HIGH_DCS_MASK                   (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
34988 #define ENET_QOS_HIGH_DCS_SHIFT                  (16U)
34989 /*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field
34990  *    contains the binary representation of the DMA Channel number to which an Rx packet whose DA
34991  *    matches the MAC Address(#i) content is routed.
34992  */
34993 #define ENET_QOS_HIGH_DCS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
34994 
34995 #define ENET_QOS_HIGH_MBC_MASK                   (0x3F000000U)
34996 #define ENET_QOS_HIGH_MBC_SHIFT                  (24U)
34997 /*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. */
34998 #define ENET_QOS_HIGH_MBC(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK)
34999 
35000 #define ENET_QOS_HIGH_SA_MASK                    (0x40000000U)
35001 #define ENET_QOS_HIGH_SA_SHIFT                   (30U)
35002 /*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA
35003  *    fields of the received packet.
35004  *  0b0..Compare with Destination Address
35005  *  0b1..Compare with Source Address
35006  */
35007 #define ENET_QOS_HIGH_SA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK)
35008 
35009 #define ENET_QOS_HIGH_AE_MASK                    (0x80000000U)
35010 #define ENET_QOS_HIGH_AE_SHIFT                   (31U)
35011 /*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering.
35012  *  0b0..INVALID : This bit must be always set to 1
35013  *  0b1..This bit is always set to 1
35014  */
35015 #define ENET_QOS_HIGH_AE(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK)
35016 /*! @} */
35017 
35018 /* The count of ENET_QOS_HIGH */
35019 #define ENET_QOS_HIGH_COUNT                      (64U)
35020 
35021 /*! @name LOW - MAC Address0 Low..MAC Address63 Low */
35022 /*! @{ */
35023 
35024 #define ENET_QOS_LOW_ADDRLO_MASK                 (0xFFFFFFFFU)
35025 #define ENET_QOS_LOW_ADDRLO_SHIFT                (0U)
35026 /*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. */
35027 #define ENET_QOS_LOW_ADDRLO(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK)
35028 /*! @} */
35029 
35030 /* The count of ENET_QOS_LOW */
35031 #define ENET_QOS_LOW_COUNT                       (64U)
35032 
35033 /*! @name MAC_MMC_CONTROL - MMC Control */
35034 /*! @{ */
35035 
35036 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK     (0x1U)
35037 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT    (0U)
35038 /*! CNTRST - Counters Reset When this bit is set, all counters are reset.
35039  *  0b0..Counters are not reset
35040  *  0b1..All counters are reset
35041  */
35042 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK)
35043 
35044 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK  (0x2U)
35045 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
35046 /*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value.
35047  *  0b0..Counter Stop Rollover is disabled
35048  *  0b1..Counter Stop Rollover is enabled
35049  */
35050 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK)
35051 
35052 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK    (0x4U)
35053 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT   (2U)
35054 /*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset).
35055  *  0b0..Reset on Read is disabled
35056  *  0b1..Reset on Read is enabled
35057  */
35058 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK)
35059 
35060 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK   (0x8U)
35061 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT  (3U)
35062 /*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value.
35063  *  0b0..MMC Counter Freeze is disabled
35064  *  0b1..MMC Counter Freeze is enabled
35065  */
35066 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK)
35067 
35068 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK    (0x10U)
35069 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT   (4U)
35070 /*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost
35071  *    full or almost half according to the CNTPRSTLVL bit.
35072  *  0b0..Counters Preset is disabled
35073  *  0b1..Counters Preset is enabled
35074  */
35075 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK)
35076 
35077 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U)
35078 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
35079 /*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value.
35080  *  0b0..Full-Half Preset is disabled
35081  *  0b1..Full-Half Preset is enabled
35082  */
35083 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK)
35084 
35085 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK      (0x100U)
35086 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT     (8U)
35087 /*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit.
35088  *  0b0..Update MMC Counters for Dropped Broadcast Packets is disabled
35089  *  0b1..Update MMC Counters for Dropped Broadcast Packets is enabled
35090  */
35091 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK)
35092 /*! @} */
35093 
35094 /*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */
35095 /*! @{ */
35096 
35097 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U)
35098 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
35099 /*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the
35100  *    rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
35101  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected
35102  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected
35103  */
35104 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK)
35105 
35106 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U)
35107 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
35108 /*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the
35109  *    rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
35110  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected
35111  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected
35112  */
35113 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK)
35114 
35115 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U)
35116 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
35117 /*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the
35118  *    rxoctetcount_g counter reaches half of the maximum value or the maximum value.
35119  *  0b1..MMC Receive Good Octet Counter Interrupt Status detected
35120  *  0b0..MMC Receive Good Octet Counter Interrupt Status not detected
35121  */
35122 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK)
35123 
35124 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U)
35125 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U)
35126 /*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the
35127  *    rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
35128  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected
35129  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
35130  */
35131 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK)
35132 
35133 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U)
35134 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
35135 /*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the
35136  *    rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
35137  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected
35138  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected
35139  */
35140 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK)
35141 
35142 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U)
35143 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
35144 /*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the
35145  *    rxcrcerror counter reaches half of the maximum value or the maximum value.
35146  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected
35147  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected
35148  */
35149 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK)
35150 
35151 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U)
35152 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U)
35153 /*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when
35154  *    the rxalignmenterror counter reaches half of the maximum value or the maximum value.
35155  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected
35156  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected
35157  */
35158 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK)
35159 
35160 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U)
35161 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U)
35162 /*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the
35163  *    rxrunterror counter reaches half of the maximum value or the maximum value.
35164  *  0b1..MMC Receive Runt Packet Counter Interrupt Status detected
35165  *  0b0..MMC Receive Runt Packet Counter Interrupt Status not detected
35166  */
35167 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK)
35168 
35169 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U)
35170 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U)
35171 /*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the
35172  *    rxjabbererror counter reaches half of the maximum value or the maximum value.
35173  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected
35174  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected
35175  */
35176 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK)
35177 
35178 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U)
35179 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U)
35180 /*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when
35181  *    the rxundersize_g counter reaches half of the maximum value or the maximum value.
35182  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected
35183  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected
35184  */
35185 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK)
35186 
35187 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U)
35188 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U)
35189 /*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the
35190  *    rxoversize_g counter reaches half of the maximum value or the maximum value.
35191  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected
35192  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected
35193  */
35194 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK)
35195 
35196 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U)
35197 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U)
35198 /*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
35199  *    when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
35200  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected
35201  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
35202  */
35203 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK)
35204 
35205 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U)
35206 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U)
35207 /*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit
35208  *    is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum
35209  *    value.
35210  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
35211  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
35212  */
35213 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK)
35214 
35215 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U)
35216 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U)
35217 /*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
35218  *    bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the
35219  *    maximum value.
35220  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
35221  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
35222  */
35223 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK)
35224 
35225 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U)
35226 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U)
35227 /*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
35228  *    bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the
35229  *    maximum value.
35230  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
35231  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
35232  */
35233 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK)
35234 
35235 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U)
35236 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U)
35237 /*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This
35238  *    bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the
35239  *    maximum value.
35240  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
35241  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
35242  */
35243 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK)
35244 
35245 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U)
35246 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U)
35247 /*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
35248  *    This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the
35249  *    maximum value.
35250  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
35251  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
35252  */
35253 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK)
35254 
35255 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U)
35256 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U)
35257 /*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the
35258  *    rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
35259  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected
35260  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected
35261  */
35262 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK)
35263 
35264 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U)
35265 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
35266 /*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the
35267  *    rxlengtherror counter reaches half of the maximum value or the maximum value.
35268  *  0b1..MMC Receive Length Error Packet Counter Interrupt Status detected
35269  *  0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected
35270  */
35271 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK)
35272 
35273 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U)
35274 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U)
35275 /*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status.
35276  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected
35277  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
35278  */
35279 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK)
35280 
35281 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U)
35282 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U)
35283 /*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the
35284  *    rxpausepackets counter reaches half of the maximum value or the maximum value.
35285  *  0b1..MMC Receive Pause Packet Counter Interrupt Status detected
35286  *  0b0..MMC Receive Pause Packet Counter Interrupt Status not detected
35287  */
35288 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK)
35289 
35290 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U)
35291 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
35292 /*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the
35293  *    rxfifooverflow counter reaches half of the maximum value or the maximum value.
35294  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected
35295  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
35296  */
35297 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK)
35298 
35299 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U)
35300 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U)
35301 /*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the
35302  *    rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
35303  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected
35304  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
35305  */
35306 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK)
35307 
35308 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U)
35309 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U)
35310 /*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the
35311  *    rxwatchdog error counter reaches half of the maximum value or the maximum value.
35312  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected
35313  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
35314  */
35315 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK)
35316 
35317 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U)
35318 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U)
35319 /*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the
35320  *    rxrcverror counter reaches half of the maximum value or the maximum value.
35321  *  0b1..MMC Receive Error Packet Counter Interrupt Status detected
35322  *  0b0..MMC Receive Error Packet Counter Interrupt Status not detected
35323  */
35324 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK)
35325 
35326 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U)
35327 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U)
35328 /*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the
35329  *    rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
35330  *  0b1..MMC Receive Control Packet Counter Interrupt Status detected
35331  *  0b0..MMC Receive Control Packet Counter Interrupt Status not detected
35332  */
35333 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK)
35334 
35335 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U)
35336 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U)
35337 /*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the
35338  *    Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
35339  *  0b1..MMC Receive LPI microsecond Counter Interrupt Status detected
35340  *  0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected
35341  */
35342 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK)
35343 
35344 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U)
35345 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U)
35346 /*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the
35347  *    Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
35348  *  0b1..MMC Receive LPI transition Counter Interrupt Status detected
35349  *  0b0..MMC Receive LPI transition Counter Interrupt Status not detected
35350  */
35351 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK)
35352 /*! @} */
35353 
35354 /*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */
35355 /*! @{ */
35356 
35357 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U)
35358 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
35359 /*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the
35360  *    txoctetcount_gb counter reaches half of the maximum value or the maximum value.
35361  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected
35362  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected
35363  */
35364 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK)
35365 
35366 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U)
35367 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
35368 /*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the
35369  *    txpacketcount_gb counter reaches half of the maximum value or the maximum value.
35370  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected
35371  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected
35372  */
35373 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK)
35374 
35375 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U)
35376 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U)
35377 /*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the
35378  *    txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
35379  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected
35380  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
35381  */
35382 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK)
35383 
35384 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U)
35385 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U)
35386 /*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the
35387  *    txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
35388  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected
35389  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
35390  */
35391 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK)
35392 
35393 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U)
35394 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U)
35395 /*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
35396  *    when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
35397  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected
35398  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
35399  */
35400 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK)
35401 
35402 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U)
35403 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U)
35404 /*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This
35405  *    bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it
35406  *    reaches the maximum value.
35407  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
35408  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
35409  */
35410 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK)
35411 
35412 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U)
35413 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U)
35414 /*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
35415  *    bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the
35416  *    maximum value.
35417  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
35418  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
35419  */
35420 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK)
35421 
35422 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U)
35423 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U)
35424 /*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
35425  *    bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the
35426  *    maximum value.
35427  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
35428  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
35429  */
35430 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK)
35431 
35432 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U)
35433 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U)
35434 /*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
35435  *    This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the
35436  *    maximum value.
35437  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
35438  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
35439  */
35440 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK)
35441 
35442 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U)
35443 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U)
35444 /*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
35445  *    This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or
35446  *    the maximum value.
35447  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
35448  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
35449  */
35450 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK)
35451 
35452 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U)
35453 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U)
35454 /*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when
35455  *    the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
35456  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected
35457  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
35458  */
35459 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK)
35460 
35461 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U)
35462 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U)
35463 /*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when
35464  *    the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
35465  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected
35466  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
35467  */
35468 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK)
35469 
35470 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U)
35471 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U)
35472 /*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when
35473  *    the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
35474  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected
35475  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
35476  */
35477 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK)
35478 
35479 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U)
35480 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
35481 /*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when
35482  *    the txunderflowerror counter reaches half of the maximum value or the maximum value.
35483  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected
35484  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
35485  */
35486 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK)
35487 
35488 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U)
35489 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U)
35490 /*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set
35491  *    when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
35492  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected
35493  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
35494  */
35495 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK)
35496 
35497 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U)
35498 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U)
35499 /*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is
35500  *    set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
35501  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected
35502  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
35503  */
35504 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK)
35505 
35506 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U)
35507 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U)
35508 /*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the
35509  *    txdeferred counter reaches half of the maximum value or the maximum value.
35510  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected
35511  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected
35512  */
35513 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK)
35514 
35515 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U)
35516 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U)
35517 /*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when
35518  *    the txlatecol counter reaches half of the maximum value or the maximum value.
35519  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected
35520  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected
35521  */
35522 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK)
35523 
35524 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U)
35525 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U)
35526 /*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set
35527  *    when the txexesscol counter reaches half of the maximum value or the maximum value.
35528  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected
35529  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
35530  */
35531 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK)
35532 
35533 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U)
35534 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
35535 /*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the
35536  *    txcarriererror counter reaches half of the maximum value or the maximum value.
35537  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected
35538  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
35539  */
35540 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK)
35541 
35542 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U)
35543 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
35544 /*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the
35545  *    txoctetcount_g counter reaches half of the maximum value or the maximum value.
35546  *  0b1..MMC Transmit Good Octet Counter Interrupt Status detected
35547  *  0b0..MMC Transmit Good Octet Counter Interrupt Status not detected
35548  */
35549 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK)
35550 
35551 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U)
35552 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
35553 /*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the
35554  *    txpacketcount_g counter reaches half of the maximum value or the maximum value.
35555  *  0b1..MMC Transmit Good Packet Counter Interrupt Status detected
35556  *  0b0..MMC Transmit Good Packet Counter Interrupt Status not detected
35557  */
35558 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK)
35559 
35560 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U)
35561 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U)
35562 /*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set
35563  *    when the txexcessdef counter reaches half of the maximum value or the maximum value.
35564  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected
35565  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
35566  */
35567 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK)
35568 
35569 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U)
35570 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U)
35571 /*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the
35572  *    txpausepacketserror counter reaches half of the maximum value or the maximum value.
35573  *  0b1..MMC Transmit Pause Packet Counter Interrupt Status detected
35574  *  0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected
35575  */
35576 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK)
35577 
35578 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U)
35579 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U)
35580 /*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the
35581  *    txvlanpackets_g counter reaches half of the maximum value or the maximum value.
35582  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected
35583  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
35584  */
35585 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK)
35586 
35587 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U)
35588 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U)
35589 /*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when
35590  *    the txoversize_g counter reaches half of the maximum value or the maximum value.
35591  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected
35592  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
35593  */
35594 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK)
35595 
35596 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U)
35597 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U)
35598 /*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the
35599  *    Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
35600  *  0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected
35601  *  0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected
35602  */
35603 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK)
35604 
35605 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U)
35606 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U)
35607 /*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the
35608  *    Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
35609  *  0b1..MMC Transmit LPI transition Counter Interrupt Status detected
35610  *  0b0..MMC Transmit LPI transition Counter Interrupt Status not detected
35611  */
35612 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK)
35613 /*! @} */
35614 
35615 /*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */
35616 /*! @{ */
35617 
35618 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U)
35619 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
35620 /*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the
35621  *    interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
35622  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
35623  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled
35624  */
35625 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK)
35626 
35627 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U)
35628 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
35629 /*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the
35630  *    interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
35631  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
35632  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled
35633  */
35634 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK)
35635 
35636 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U)
35637 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
35638 /*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
35639  *    when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
35640  *  0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled
35641  *  0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled
35642  */
35643 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK)
35644 
35645 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U)
35646 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U)
35647 /*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
35648  *    interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the
35649  *    maximum value.
35650  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
35651  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled
35652  */
35653 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK)
35654 
35655 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U)
35656 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
35657 /*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
35658  *    interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the
35659  *    maximum value.
35660  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
35661  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled
35662  */
35663 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK)
35664 
35665 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U)
35666 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
35667 /*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the
35668  *    interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
35669  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
35670  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled
35671  */
35672 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK)
35673 
35674 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U)
35675 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U)
35676 /*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks
35677  *    the interrupt when the rxalignmenterror counter reaches half of the maximum value or the
35678  *    maximum value.
35679  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
35680  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled
35681  */
35682 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK)
35683 
35684 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U)
35685 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U)
35686 /*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt
35687  *    when the rxrunterror counter reaches half of the maximum value or the maximum value.
35688  *  0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled
35689  *  0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled
35690  */
35691 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK)
35692 
35693 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U)
35694 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U)
35695 /*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the
35696  *    interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
35697  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
35698  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled
35699  */
35700 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK)
35701 
35702 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U)
35703 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U)
35704 /*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks
35705  *    the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum
35706  *    value.
35707  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
35708  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled
35709  */
35710 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK)
35711 
35712 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U)
35713 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U)
35714 /*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the
35715  *    interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum
35716  *    value.
35717  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
35718  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled
35719  */
35720 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK)
35721 
35722 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U)
35723 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U)
35724 /*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
35725  *    masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the
35726  *    maximum value.
35727  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
35728  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
35729  */
35730 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK)
35731 
35732 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U)
35733 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U)
35734 /*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
35735  *    this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum
35736  *    value or the maximum value.
35737  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
35738  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
35739  */
35740 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK)
35741 
35742 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U)
35743 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U)
35744 /*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
35745  *    this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum
35746  *    value or the maximum value.
35747  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
35748  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
35749  */
35750 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK)
35751 
35752 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U)
35753 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U)
35754 /*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
35755  *    this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum
35756  *    value or the maximum value.
35757  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
35758  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
35759  */
35760 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK)
35761 
35762 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U)
35763 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U)
35764 /*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
35765  *    Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the
35766  *    maximum value or the maximum value.
35767  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
35768  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
35769  */
35770 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK)
35771 
35772 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U)
35773 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U)
35774 /*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
35775  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
35776  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
35777  */
35778 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK)
35779 
35780 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U)
35781 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U)
35782 /*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the
35783  *    interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum
35784  *    value.
35785  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
35786  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled
35787  */
35788 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK)
35789 
35790 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U)
35791 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
35792 /*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the
35793  *    interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
35794  *  0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled
35795  *  0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled
35796  */
35797 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK)
35798 
35799 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U)
35800 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U)
35801 /*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit
35802  *    masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the
35803  *    maximum value.
35804  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
35805  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled
35806  */
35807 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK)
35808 
35809 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U)
35810 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U)
35811 /*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt
35812  *    when the rxpausepackets counter reaches half of the maximum value or the maximum value.
35813  *  0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled
35814  *  0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled
35815  */
35816 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK)
35817 
35818 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U)
35819 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
35820 /*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the
35821  *    interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
35822  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
35823  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled
35824  */
35825 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK)
35826 
35827 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U)
35828 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U)
35829 /*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the
35830  *    interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum
35831  *    value.
35832  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
35833  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled
35834  */
35835 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK)
35836 
35837 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U)
35838 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U)
35839 /*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the
35840  *    interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
35841  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
35842  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled
35843  */
35844 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK)
35845 
35846 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U)
35847 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U)
35848 /*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the
35849  *    interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.
35850  *  0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled
35851  *  0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled
35852  */
35853 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK)
35854 
35855 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U)
35856 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U)
35857 /*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the
35858  *    interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
35859  *  0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled
35860  *  0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled
35861  */
35862 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK)
35863 
35864 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U)
35865 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U)
35866 /*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the
35867  *    interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
35868  *  0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled
35869  *  0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled
35870  */
35871 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK)
35872 
35873 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U)
35874 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U)
35875 /*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the
35876  *    interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
35877  *  0b0..MMC Receive LPI transition counter interrupt Mask is disabled
35878  *  0b1..MMC Receive LPI transition counter interrupt Mask is enabled
35879  */
35880 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK)
35881 /*! @} */
35882 
35883 /*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */
35884 /*! @{ */
35885 
35886 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U)
35887 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
35888 /*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the
35889  *    interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
35890  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled
35891  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled
35892  */
35893 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK)
35894 
35895 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U)
35896 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
35897 /*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the
35898  *    interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
35899  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled
35900  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled
35901  */
35902 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK)
35903 
35904 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U)
35905 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U)
35906 /*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
35907  *    interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the
35908  *    maximum value.
35909  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled
35910  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled
35911  */
35912 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK)
35913 
35914 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U)
35915 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U)
35916 /*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
35917  *    interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the
35918  *    maximum value.
35919  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled
35920  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled
35921  */
35922 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK)
35923 
35924 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U)
35925 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U)
35926 /*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
35927  *    masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the
35928  *    maximum value.
35929  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
35930  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
35931  */
35932 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK)
35933 
35934 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U)
35935 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U)
35936 /*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
35937  *    this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum
35938  *    value or the maximum value.
35939  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
35940  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
35941  */
35942 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK)
35943 
35944 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U)
35945 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U)
35946 /*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
35947  *    this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum
35948  *    value or the maximum value.
35949  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
35950  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
35951  */
35952 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK)
35953 
35954 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U)
35955 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U)
35956 /*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
35957  *    this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum
35958  *    value or the maximum value.
35959  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
35960  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
35961  */
35962 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK)
35963 
35964 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U)
35965 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U)
35966 /*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
35967  *    Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the
35968  *    maximum value or the maximum value.
35969  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
35970  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
35971  */
35972 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK)
35973 
35974 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U)
35975 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U)
35976 /*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
35977  *    Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the
35978  *    maximum value or the maximum value.
35979  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
35980  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
35981  */
35982 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK)
35983 
35984 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U)
35985 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U)
35986 /*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
35987  *    the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the
35988  *    maximum value.
35989  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled
35990  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled
35991  */
35992 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK)
35993 
35994 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U)
35995 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U)
35996 /*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
35997  *    the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the
35998  *    maximum value.
35999  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled
36000  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled
36001  */
36002 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK)
36003 
36004 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U)
36005 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U)
36006 /*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks
36007  *    the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the
36008  *    maximum value.
36009  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled
36010  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled
36011  */
36012 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK)
36013 
36014 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U)
36015 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
36016 /*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks
36017  *    the interrupt when the txunderflowerror counter reaches half of the maximum value or the
36018  *    maximum value.
36019  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled
36020  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled
36021  */
36022 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK)
36023 
36024 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U)
36025 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U)
36026 /*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit
36027  *    masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the
36028  *    maximum value.
36029  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled
36030  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled
36031  */
36032 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK)
36033 
36034 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U)
36035 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U)
36036 /*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit
36037  *    masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the
36038  *    maximum value.
36039  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled
36040  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled
36041  */
36042 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK)
36043 
36044 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U)
36045 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U)
36046 /*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the
36047  *    interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
36048  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled
36049  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled
36050  */
36051 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK)
36052 
36053 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U)
36054 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U)
36055 /*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks
36056  *    the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
36057  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled
36058  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled
36059  */
36060 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK)
36061 
36062 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U)
36063 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U)
36064 /*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit
36065  *    masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum
36066  *    value.
36067  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled
36068  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled
36069  */
36070 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK)
36071 
36072 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U)
36073 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
36074 /*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the
36075  *    interrupt when the txcarriererror counter reaches half of the maximum value or the maximum
36076  *    value.
36077  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled
36078  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled
36079  */
36080 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK)
36081 
36082 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U)
36083 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
36084 /*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
36085  *    when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
36086  *  0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled
36087  *  0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled
36088  */
36089 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK)
36090 
36091 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U)
36092 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
36093 /*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt
36094  *    when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
36095  *  0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled
36096  *  0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled
36097  */
36098 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK)
36099 
36100 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U)
36101 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U)
36102 /*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit
36103  *    masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum
36104  *    value.
36105  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
36106  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled
36107  */
36108 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK)
36109 
36110 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U)
36111 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U)
36112 /*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the
36113  *    interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.
36114  *  0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled
36115  *  0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled
36116  */
36117 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK)
36118 
36119 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U)
36120 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U)
36121 /*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the
36122  *    interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
36123  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
36124  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled
36125  */
36126 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK)
36127 
36128 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U)
36129 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U)
36130 /*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks
36131  *    the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum
36132  *    value.
36133  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
36134  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled
36135  */
36136 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK)
36137 
36138 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U)
36139 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U)
36140 /*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the
36141  *    interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
36142  *  0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled
36143  *  0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled
36144  */
36145 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK)
36146 
36147 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U)
36148 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U)
36149 /*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the
36150  *    interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
36151  *  0b0..MMC Transmit LPI transition counter interrupt Mask is disabled
36152  *  0b1..MMC Transmit LPI transition counter interrupt Mask is enabled
36153  */
36154 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK)
36155 /*! @} */
36156 
36157 /*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */
36158 /*! @{ */
36159 
36160 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU)
36161 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
36162 /*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted,
36163  *    exclusive of preamble and retried bytes, in good and bad packets.
36164  */
36165 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
36166 /*! @} */
36167 
36168 /*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */
36169 /*! @{ */
36170 
36171 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU)
36172 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
36173 /*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets
36174  *    transmitted, exclusive of retried packets.
36175  */
36176 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
36177 /*! @} */
36178 
36179 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */
36180 /*! @{ */
36181 
36182 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU)
36183 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U)
36184 /*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted. */
36185 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
36186 /*! @} */
36187 
36188 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */
36189 /*! @{ */
36190 
36191 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU)
36192 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U)
36193 /*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted. */
36194 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
36195 /*! @} */
36196 
36197 /*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */
36198 /*! @{ */
36199 
36200 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU)
36201 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U)
36202 /*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets
36203  *    transmitted with length 64 bytes, exclusive of preamble and retried packets.
36204  */
36205 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
36206 /*! @} */
36207 
36208 /*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */
36209 /*! @{ */
36210 
36211 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU)
36212 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U)
36213 /*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and
36214  *    bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble
36215  *    and retried packets.
36216  */
36217 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
36218 /*! @} */
36219 
36220 /*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */
36221 /*! @{ */
36222 
36223 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU)
36224 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U)
36225 /*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and
36226  *    bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of
36227  *    preamble and retried packets.
36228  */
36229 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
36230 /*! @} */
36231 
36232 /*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */
36233 /*! @{ */
36234 
36235 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU)
36236 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U)
36237 /*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and
36238  *    bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of
36239  *    preamble and retried packets.
36240  */
36241 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
36242 /*! @} */
36243 
36244 /*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */
36245 /*! @{ */
36246 
36247 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU)
36248 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U)
36249 /*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good
36250  *    and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of
36251  *    preamble and retried packets.
36252  */
36253 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
36254 /*! @} */
36255 
36256 /*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */
36257 /*! @{ */
36258 
36259 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
36260 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U)
36261 /*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good
36262  *    and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of
36263  *    preamble and retried packets.
36264  */
36265 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
36266 /*! @} */
36267 
36268 /*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */
36269 /*! @{ */
36270 
36271 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU)
36272 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U)
36273 /*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted. */
36274 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
36275 /*! @} */
36276 
36277 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */
36278 /*! @{ */
36279 
36280 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU)
36281 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U)
36282 /*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted. */
36283 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
36284 /*! @} */
36285 
36286 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */
36287 /*! @{ */
36288 
36289 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU)
36290 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U)
36291 /*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted. */
36292 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
36293 /*! @} */
36294 
36295 /*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */
36296 /*! @{ */
36297 
36298 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU)
36299 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
36300 /*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error. */
36301 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
36302 /*! @} */
36303 
36304 /*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */
36305 /*! @{ */
36306 
36307 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU)
36308 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U)
36309 /*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully
36310  *    transmitted packets after a single collision in the half-duplex mode.
36311  */
36312 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
36313 /*! @} */
36314 
36315 /*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */
36316 /*! @{ */
36317 
36318 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU)
36319 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U)
36320 /*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully
36321  *    transmitted packets after multiple collisions in the half-duplex mode.
36322  */
36323 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
36324 /*! @} */
36325 
36326 /*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */
36327 /*! @{ */
36328 
36329 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU)
36330 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U)
36331 /*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after
36332  *    a deferral in the half-duplex mode.
36333  */
36334 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
36335 /*! @} */
36336 
36337 /*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */
36338 /*! @{ */
36339 
36340 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU)
36341 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U)
36342 /*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error. */
36343 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
36344 /*! @} */
36345 
36346 /*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */
36347 /*! @{ */
36348 
36349 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU)
36350 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U)
36351 /*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted
36352  *    because of excessive (16) collision errors.
36353  */
36354 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
36355 /*! @} */
36356 
36357 /*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */
36358 /*! @{ */
36359 
36360 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU)
36361 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
36362 /*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of
36363  *    carrier sense error (no carrier or loss of carrier).
36364  */
36365 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
36366 /*! @} */
36367 
36368 /*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */
36369 /*! @{ */
36370 
36371 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU)
36372 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
36373 /*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets. */
36374 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
36375 /*! @} */
36376 
36377 /*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */
36378 /*! @{ */
36379 
36380 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU)
36381 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
36382 /*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted. */
36383 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
36384 /*! @} */
36385 
36386 /*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */
36387 /*! @{ */
36388 
36389 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU)
36390 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U)
36391 /*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted
36392  *    because of excessive deferral error (deferred for more than two max-sized packet times).
36393  */
36394 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
36395 /*! @} */
36396 
36397 /*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */
36398 /*! @{ */
36399 
36400 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU)
36401 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U)
36402 /*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted. */
36403 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
36404 /*! @} */
36405 
36406 /*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */
36407 /*! @{ */
36408 
36409 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU)
36410 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U)
36411 /*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted. */
36412 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
36413 /*! @} */
36414 
36415 /*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */
36416 /*! @{ */
36417 
36418 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU)
36419 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U)
36420 /*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without
36421  *    errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets;
36422  *    2000 bytes if enabled in S2KP bit of the CONFIGURATION register).
36423  */
36424 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
36425 /*! @} */
36426 
36427 /*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */
36428 /*! @{ */
36429 
36430 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU)
36431 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
36432 /*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received. */
36433 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
36434 /*! @} */
36435 
36436 /*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */
36437 /*! @{ */
36438 
36439 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU)
36440 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
36441 /*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive
36442  *    of preamble, in good and bad packets.
36443  */
36444 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
36445 /*! @} */
36446 
36447 /*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */
36448 /*! @{ */
36449 
36450 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU)
36451 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
36452 /*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets. */
36453 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
36454 /*! @} */
36455 
36456 /*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */
36457 /*! @{ */
36458 
36459 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU)
36460 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U)
36461 /*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received. */
36462 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
36463 /*! @} */
36464 
36465 /*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */
36466 /*! @{ */
36467 
36468 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU)
36469 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
36470 /*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received. */
36471 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
36472 /*! @} */
36473 
36474 /*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */
36475 /*! @{ */
36476 
36477 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU)
36478 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
36479 /*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error. */
36480 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
36481 /*! @} */
36482 
36483 /*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */
36484 /*! @{ */
36485 
36486 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU)
36487 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U)
36488 /*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. */
36489 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
36490 /*! @} */
36491 
36492 /*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */
36493 /*! @{ */
36494 
36495 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU)
36496 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U)
36497 /*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt
36498  *    (length less than 64 bytes and CRC error) error.
36499  */
36500 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
36501 /*! @} */
36502 
36503 /*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */
36504 /*! @{ */
36505 
36506 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU)
36507 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U)
36508 /*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received
36509  *    with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC
36510  *    error.
36511  */
36512 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
36513 /*! @} */
36514 
36515 /*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */
36516 /*! @{ */
36517 
36518 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU)
36519 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U)
36520 /*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with
36521  *    length less than 64 bytes, without any errors.
36522  */
36523 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
36524 /*! @} */
36525 
36526 /*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */
36527 /*! @{ */
36528 
36529 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU)
36530 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U)
36531 /*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without
36532  *    errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged
36533  *    packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register).
36534  */
36535 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
36536 /*! @} */
36537 
36538 /*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */
36539 /*! @{ */
36540 
36541 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU)
36542 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U)
36543 /*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad
36544  *    packets received with length 64 bytes, exclusive of the preamble.
36545  */
36546 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
36547 /*! @} */
36548 
36549 /*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */
36550 /*! @{ */
36551 
36552 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU)
36553 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U)
36554 /*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and
36555  *    bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.
36556  */
36557 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
36558 /*! @} */
36559 
36560 /*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */
36561 /*! @{ */
36562 
36563 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU)
36564 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U)
36565 /*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and
36566  *    bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the
36567  *    preamble.
36568  */
36569 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
36570 /*! @} */
36571 
36572 /*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */
36573 /*! @{ */
36574 
36575 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU)
36576 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U)
36577 /*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and
36578  *    bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the
36579  *    preamble.
36580  */
36581 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
36582 /*! @} */
36583 
36584 /*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */
36585 /*! @{ */
36586 
36587 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU)
36588 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U)
36589 /*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good
36590  *    and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the
36591  *    preamble.
36592  */
36593 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
36594 /*! @} */
36595 
36596 /*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */
36597 /*! @{ */
36598 
36599 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
36600 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U)
36601 /*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad
36602  *    packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the
36603  *    preamble.
36604  */
36605 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
36606 /*! @} */
36607 
36608 /*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */
36609 /*! @{ */
36610 
36611 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU)
36612 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U)
36613 /*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received. */
36614 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
36615 /*! @} */
36616 
36617 /*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */
36618 /*! @{ */
36619 
36620 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU)
36621 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
36622 /*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with
36623  *    length error (Length Type field not equal to packet size), for all packets with valid length field.
36624  */
36625 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
36626 /*! @} */
36627 
36628 /*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */
36629 /*! @{ */
36630 
36631 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU)
36632 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U)
36633 /*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received
36634  *    with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).
36635  */
36636 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
36637 /*! @} */
36638 
36639 /*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */
36640 /*! @{ */
36641 
36642 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU)
36643 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U)
36644 /*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received. */
36645 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
36646 /*! @} */
36647 
36648 /*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */
36649 /*! @{ */
36650 
36651 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU)
36652 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
36653 /*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow. */
36654 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
36655 /*! @} */
36656 
36657 /*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */
36658 /*! @{ */
36659 
36660 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU)
36661 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U)
36662 /*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received. */
36663 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
36664 /*! @} */
36665 
36666 /*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */
36667 /*! @{ */
36668 
36669 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU)
36670 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U)
36671 /*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with
36672  *    error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when
36673  *    JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and
36674  *    WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in
36675  *    MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register).
36676  */
36677 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
36678 /*! @} */
36679 
36680 /*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */
36681 /*! @{ */
36682 
36683 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU)
36684 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U)
36685 /*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with
36686  *    Receive error or Packet Extension error on the GMII or MII interface.
36687  */
36688 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
36689 /*! @} */
36690 
36691 /*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */
36692 /*! @{ */
36693 
36694 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU)
36695 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U)
36696 /*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received. */
36697 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
36698 /*! @} */
36699 
36700 /*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */
36701 /*! @{ */
36702 
36703 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU)
36704 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U)
36705 /*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. */
36706 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK)
36707 /*! @} */
36708 
36709 /*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */
36710 /*! @{ */
36711 
36712 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU)
36713 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U)
36714 /*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. */
36715 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK)
36716 /*! @} */
36717 
36718 /*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */
36719 /*! @{ */
36720 
36721 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU)
36722 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U)
36723 /*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. */
36724 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK)
36725 /*! @} */
36726 
36727 /*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */
36728 /*! @{ */
36729 
36730 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU)
36731 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U)
36732 /*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. */
36733 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK)
36734 /*! @} */
36735 
36736 /*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */
36737 /*! @{ */
36738 
36739 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U)
36740 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
36741 /*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the
36742  *    interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
36743  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled
36744  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled
36745  */
36746 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK)
36747 
36748 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U)
36749 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
36750 /*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit
36751  *    masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the
36752  *    maximum value.
36753  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled
36754  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled
36755  */
36756 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK)
36757 
36758 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U)
36759 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U)
36760 /*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit
36761  *    masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the
36762  *    maximum value.
36763  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled
36764  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled
36765  */
36766 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK)
36767 
36768 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U)
36769 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U)
36770 /*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks
36771  *    the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the
36772  *    maximum value.
36773  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled
36774  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled
36775  */
36776 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK)
36777 
36778 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U)
36779 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U)
36780 /*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting
36781  *    this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum
36782  *    value or the maximum value.
36783  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled
36784  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled
36785  */
36786 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK)
36787 
36788 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U)
36789 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
36790 /*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the
36791  *    interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
36792  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled
36793  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled
36794  */
36795 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK)
36796 
36797 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U)
36798 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
36799 /*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit
36800  *    masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the
36801  *    maximum value.
36802  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled
36803  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled
36804  */
36805 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK)
36806 
36807 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U)
36808 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U)
36809 /*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit
36810  *    masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the
36811  *    maximum value.
36812  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled
36813  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled
36814  */
36815 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK)
36816 
36817 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U)
36818 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U)
36819 /*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the
36820  *    interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
36821  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled
36822  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled
36823  */
36824 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK)
36825 
36826 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U)
36827 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
36828 /*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the
36829  *    interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
36830  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled
36831  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled
36832  */
36833 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK)
36834 
36835 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U)
36836 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U)
36837 /*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the
36838  *    interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
36839  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled
36840  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled
36841  */
36842 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK)
36843 
36844 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U)
36845 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
36846 /*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the
36847  *    interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
36848  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled
36849  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled
36850  */
36851 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK)
36852 
36853 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U)
36854 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U)
36855 /*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the
36856  *    interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
36857  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled
36858  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled
36859  */
36860 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK)
36861 
36862 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U)
36863 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
36864 /*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the
36865  *    interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum
36866  *    value.
36867  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled
36868  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled
36869  */
36870 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK)
36871 
36872 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U)
36873 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U)
36874 /*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the
36875  *    interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
36876  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled
36877  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled
36878  */
36879 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK)
36880 
36881 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U)
36882 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
36883 /*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks
36884  *    the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the
36885  *    maximum value.
36886  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled
36887  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled
36888  */
36889 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK)
36890 
36891 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U)
36892 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U)
36893 /*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks
36894  *    the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the
36895  *    maximum value.
36896  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled
36897  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled
36898  */
36899 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK)
36900 
36901 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U)
36902 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U)
36903 /*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks
36904  *    the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the
36905  *    maximum value.
36906  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled
36907  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled
36908  */
36909 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK)
36910 
36911 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U)
36912 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U)
36913 /*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting
36914  *    this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum
36915  *    value or the maximum value.
36916  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled
36917  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled
36918  */
36919 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK)
36920 
36921 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U)
36922 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U)
36923 /*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
36924  *    interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
36925  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
36926  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
36927  */
36928 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK)
36929 
36930 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U)
36931 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
36932 /*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
36933  *    interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum
36934  *    value.
36935  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
36936  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
36937  */
36938 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK)
36939 
36940 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U)
36941 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U)
36942 /*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit
36943  *    masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the
36944  *    maximum value.
36945  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled
36946  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled
36947  */
36948 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK)
36949 
36950 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U)
36951 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U)
36952 /*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the
36953  *    interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum
36954  *    value.
36955  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled
36956  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled
36957  */
36958 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK)
36959 
36960 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U)
36961 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
36962 /*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the
36963  *    interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
36964  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled
36965  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled
36966  */
36967 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK)
36968 
36969 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U)
36970 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U)
36971 /*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the
36972  *    interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
36973  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled
36974  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled
36975  */
36976 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK)
36977 
36978 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U)
36979 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
36980 /*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the
36981  *    interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
36982  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled
36983  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled
36984  */
36985 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK)
36986 
36987 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U)
36988 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U)
36989 /*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the
36990  *    interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
36991  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled
36992  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled
36993  */
36994 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK)
36995 
36996 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U)
36997 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
36998 /*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the
36999  *    interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum
37000  *    value.
37001  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled
37002  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled
37003  */
37004 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK)
37005 /*! @} */
37006 
37007 /*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */
37008 /*! @{ */
37009 
37010 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U)
37011 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
37012 /*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the
37013  *    rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
37014  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected
37015  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected
37016  */
37017 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK)
37018 
37019 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U)
37020 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
37021 /*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set
37022  *    when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
37023  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected
37024  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected
37025  */
37026 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK)
37027 
37028 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U)
37029 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U)
37030 /*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set
37031  *    when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
37032  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected
37033  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected
37034  */
37035 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK)
37036 
37037 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U)
37038 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U)
37039 /*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when
37040  *    the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
37041  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected
37042  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected
37043  */
37044 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK)
37045 
37046 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U)
37047 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U)
37048 /*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit
37049  *    is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum
37050  *    value.
37051  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected
37052  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected
37053  */
37054 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK)
37055 
37056 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U)
37057 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
37058 /*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the
37059  *    rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
37060  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected
37061  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected
37062  */
37063 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK)
37064 
37065 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U)
37066 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
37067 /*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set
37068  *    when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
37069  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected
37070  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected
37071  */
37072 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK)
37073 
37074 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U)
37075 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U)
37076 /*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set
37077  *    when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
37078  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected
37079  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected
37080  */
37081 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK)
37082 
37083 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U)
37084 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U)
37085 /*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the
37086  *    rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
37087  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected
37088  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected
37089  */
37090 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK)
37091 
37092 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U)
37093 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
37094 /*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the
37095  *    rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
37096  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected
37097  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected
37098  */
37099 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK)
37100 
37101 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U)
37102 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U)
37103 /*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the
37104  *    rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
37105  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected
37106  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected
37107  */
37108 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK)
37109 
37110 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U)
37111 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
37112 /*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the
37113  *    rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
37114  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected
37115  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected
37116  */
37117 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK)
37118 
37119 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U)
37120 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U)
37121 /*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the
37122  *    rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
37123  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected
37124  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected
37125  */
37126 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK)
37127 
37128 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U)
37129 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
37130 /*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the
37131  *    rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
37132  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected
37133  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected
37134  */
37135 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK)
37136 
37137 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U)
37138 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U)
37139 /*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the
37140  *    rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
37141  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected
37142  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected
37143  */
37144 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK)
37145 
37146 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U)
37147 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
37148 /*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when
37149  *    the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
37150  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected
37151  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected
37152  */
37153 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK)
37154 
37155 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U)
37156 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U)
37157 /*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when
37158  *    the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
37159  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected
37160  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected
37161  */
37162 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK)
37163 
37164 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U)
37165 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U)
37166 /*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when
37167  *    the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
37168  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected
37169  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected
37170  */
37171 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK)
37172 
37173 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U)
37174 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U)
37175 /*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit
37176  *    is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum
37177  *    value.
37178  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected
37179  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected
37180  */
37181 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK)
37182 
37183 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U)
37184 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U)
37185 /*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the
37186  *    rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
37187  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected
37188  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected
37189  */
37190 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK)
37191 
37192 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U)
37193 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
37194 /*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when
37195  *    the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
37196  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected
37197  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected
37198  */
37199 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK)
37200 
37201 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U)
37202 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U)
37203 /*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when
37204  *    the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
37205  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected
37206  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected
37207  */
37208 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK)
37209 
37210 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U)
37211 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U)
37212 /*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the
37213  *    rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
37214  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected
37215  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected
37216  */
37217 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK)
37218 
37219 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U)
37220 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
37221 /*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the
37222  *    rxudp_err_octets counter reaches half of the maximum value or the maximum value.
37223  *  0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected
37224  *  0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected
37225  */
37226 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK)
37227 
37228 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U)
37229 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U)
37230 /*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the
37231  *    rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
37232  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected
37233  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected
37234  */
37235 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK)
37236 
37237 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U)
37238 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
37239 /*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the
37240  *    rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
37241  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected
37242  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected
37243  */
37244 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK)
37245 
37246 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U)
37247 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U)
37248 /*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the
37249  *    rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
37250  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected
37251  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected
37252  */
37253 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK)
37254 
37255 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U)
37256 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
37257 /*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the
37258  *    rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
37259  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected
37260  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected
37261  */
37262 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK)
37263 /*! @} */
37264 
37265 /*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */
37266 /*! @{ */
37267 
37268 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU)
37269 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
37270 /*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. */
37271 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK)
37272 /*! @} */
37273 
37274 /*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */
37275 /*! @{ */
37276 
37277 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU)
37278 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
37279 /*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams
37280  *    received with header (checksum, length, or version mismatch) errors.
37281  */
37282 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK)
37283 /*! @} */
37284 
37285 /*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */
37286 /*! @{ */
37287 
37288 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU)
37289 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U)
37290 /*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets
37291  *    received that did not have a TCP, UDP, or ICMP payload.
37292  */
37293 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK)
37294 /*! @} */
37295 
37296 /*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */
37297 /*! @{ */
37298 
37299 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU)
37300 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U)
37301 /*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation. */
37302 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK)
37303 /*! @} */
37304 
37305 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */
37306 /*! @{ */
37307 
37308 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU)
37309 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U)
37310 /*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good
37311  *    IPv4 datagrams received that had a UDP payload with checksum disabled.
37312  */
37313 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK)
37314 /*! @} */
37315 
37316 /*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */
37317 /*! @{ */
37318 
37319 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU)
37320 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
37321 /*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload. */
37322 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK)
37323 /*! @} */
37324 
37325 /*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */
37326 /*! @{ */
37327 
37328 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU)
37329 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
37330 /*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams
37331  *    received with header (length or version mismatch) errors.
37332  */
37333 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK)
37334 /*! @} */
37335 
37336 /*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */
37337 /*! @{ */
37338 
37339 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU)
37340 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U)
37341 /*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets
37342  *    received that did not have a TCP, UDP, or ICMP payload.
37343  */
37344 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK)
37345 /*! @} */
37346 
37347 /*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */
37348 /*! @{ */
37349 
37350 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU)
37351 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U)
37352 /*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. */
37353 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK)
37354 /*! @} */
37355 
37356 /*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */
37357 /*! @{ */
37358 
37359 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU)
37360 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
37361 /*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received
37362  *    whose UDP payload has a checksum error.
37363  */
37364 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK)
37365 /*! @} */
37366 
37367 /*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */
37368 /*! @{ */
37369 
37370 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU)
37371 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U)
37372 /*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload. */
37373 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK)
37374 /*! @} */
37375 
37376 /*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */
37377 /*! @{ */
37378 
37379 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU)
37380 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
37381 /*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received
37382  *    whose TCP payload has a checksum error.
37383  */
37384 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK)
37385 /*! @} */
37386 
37387 /*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */
37388 /*! @{ */
37389 
37390 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU)
37391 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U)
37392 /*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload. */
37393 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK)
37394 /*! @} */
37395 
37396 /*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */
37397 /*! @{ */
37398 
37399 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU)
37400 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
37401 /*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams
37402  *    received whose ICMP payload has a checksum error.
37403  */
37404 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK)
37405 /*! @} */
37406 
37407 /*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */
37408 /*! @{ */
37409 
37410 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU)
37411 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U)
37412 /*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4
37413  *    datagrams encapsulating TCP, UDP, or ICMP data.
37414  */
37415 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK)
37416 /*! @} */
37417 
37418 /*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */
37419 /*! @{ */
37420 
37421 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU)
37422 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
37423 /*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received
37424  *    in IPv4 datagrams with header errors (checksum, length, version mismatch).
37425  */
37426 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK)
37427 /*! @} */
37428 
37429 /*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */
37430 /*! @{ */
37431 
37432 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU)
37433 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U)
37434 /*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4
37435  *    datagrams that did not have a TCP, UDP, or ICMP payload.
37436  */
37437 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK)
37438 /*! @} */
37439 
37440 /*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */
37441 /*! @{ */
37442 
37443 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU)
37444 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U)
37445 /*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. */
37446 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK)
37447 /*! @} */
37448 
37449 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */
37450 /*! @{ */
37451 
37452 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU)
37453 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U)
37454 /*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes
37455  *    received in a UDP segment that had the UDP checksum disabled.
37456  */
37457 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK)
37458 /*! @} */
37459 
37460 /*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */
37461 /*! @{ */
37462 
37463 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU)
37464 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U)
37465 /*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6
37466  *    datagrams encapsulating TCP, UDP, or ICMP data.
37467  */
37468 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK)
37469 /*! @} */
37470 
37471 /*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */
37472 /*! @{ */
37473 
37474 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU)
37475 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
37476 /*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received
37477  *    in IPv6 datagrams with header errors (length, version mismatch).
37478  */
37479 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK)
37480 /*! @} */
37481 
37482 /*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */
37483 /*! @{ */
37484 
37485 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU)
37486 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U)
37487 /*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6
37488  *    datagrams that did not have a TCP, UDP, or ICMP payload.
37489  */
37490 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK)
37491 /*! @} */
37492 
37493 /*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */
37494 /*! @{ */
37495 
37496 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU)
37497 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U)
37498 /*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. */
37499 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK)
37500 /*! @} */
37501 
37502 /*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */
37503 /*! @{ */
37504 
37505 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU)
37506 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
37507 /*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. */
37508 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK)
37509 /*! @} */
37510 
37511 /*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */
37512 /*! @{ */
37513 
37514 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU)
37515 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U)
37516 /*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. */
37517 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK)
37518 /*! @} */
37519 
37520 /*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */
37521 /*! @{ */
37522 
37523 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU)
37524 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
37525 /*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. */
37526 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK)
37527 /*! @} */
37528 
37529 /*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */
37530 /*! @{ */
37531 
37532 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU)
37533 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U)
37534 /*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. */
37535 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK)
37536 /*! @} */
37537 
37538 /*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */
37539 /*! @{ */
37540 
37541 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU)
37542 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
37543 /*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. */
37544 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK)
37545 /*! @} */
37546 
37547 /*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */
37548 /*! @{ */
37549 
37550 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U)
37551 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U)
37552 /*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the
37553  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
37554  *  0b1..MMC Tx FPE Fragment Counter Interrupt status detected
37555  *  0b0..MMC Tx FPE Fragment Counter Interrupt status not detected
37556  */
37557 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK)
37558 
37559 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U)
37560 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U)
37561 /*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr
37562  *    counter reaches half of the maximum value or the maximum value.
37563  *  0b1..MMC Tx Hold Request Counter Interrupt Status detected
37564  *  0b0..MMC Tx Hold Request Counter Interrupt Status not detected
37565  */
37566 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK)
37567 /*! @} */
37568 
37569 /*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */
37570 /*! @{ */
37571 
37572 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U)
37573 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U)
37574 /*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when
37575  *    the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
37576  *  0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled
37577  *  0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled
37578  */
37579 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK)
37580 
37581 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U)
37582 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U)
37583 /*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt
37584  *    when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value.
37585  *  0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled
37586  *  0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled
37587  */
37588 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK)
37589 /*! @} */
37590 
37591 /*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */
37592 /*! @{ */
37593 
37594 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU)
37595 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U)
37596 /*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has
37597  *    been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled
37598  *    during FPE Enabled configuration.
37599  */
37600 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
37601 /*! @} */
37602 
37603 /*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */
37604 /*! @{ */
37605 
37606 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU)
37607 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U)
37608 /*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. */
37609 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
37610 /*! @} */
37611 
37612 /*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */
37613 /*! @{ */
37614 
37615 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U)
37616 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U)
37617 /*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the
37618  *    Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value.
37619  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected
37620  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected
37621  */
37622 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK)
37623 
37624 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U)
37625 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U)
37626 /*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the
37627  *    Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
37628  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected
37629  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected
37630  */
37631 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK)
37632 
37633 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U)
37634 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U)
37635 /*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the
37636  *    Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value.
37637  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected
37638  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected
37639  */
37640 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK)
37641 
37642 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U)
37643 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U)
37644 /*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the
37645  *    Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
37646  *  0b1..MMC Rx FPE Fragment Counter Interrupt Status detected
37647  *  0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected
37648  */
37649 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK)
37650 /*! @} */
37651 
37652 /*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */
37653 /*! @{ */
37654 
37655 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U)
37656 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U)
37657 /*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the
37658  *    interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the
37659  *    maximum value.
37660  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled
37661  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled
37662  */
37663 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK)
37664 
37665 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U)
37666 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U)
37667 /*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt
37668  *    when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
37669  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled
37670  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled
37671  */
37672 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK)
37673 
37674 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U)
37675 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U)
37676 /*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt
37677  *    when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum
37678  *    value.
37679  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled
37680  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled
37681  */
37682 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK)
37683 
37684 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U)
37685 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U)
37686 /*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the
37687  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
37688  *  0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled
37689  *  0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled
37690  */
37691 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK)
37692 /*! @} */
37693 
37694 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */
37695 /*! @{ */
37696 
37697 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU)
37698 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U)
37699 /*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with
37700  *    reassembly errors on the Receiver, due to mismatch in the Fragment Count value.
37701  */
37702 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
37703 /*! @} */
37704 
37705 /*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */
37706 /*! @{ */
37707 
37708 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU)
37709 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U)
37710 /*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to
37711  *    unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there
37712  *    was no preceding preempted frame.
37713  */
37714 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
37715 /*! @} */
37716 
37717 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */
37718 /*! @{ */
37719 
37720 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU)
37721 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U)
37722 /*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were
37723  *    successfully reassembled and delivered to MAC.
37724  */
37725 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
37726 /*! @} */
37727 
37728 /*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */
37729 /*! @{ */
37730 
37731 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU)
37732 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U)
37733 /*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received
37734  *    due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE
37735  *    Enabled configuration.
37736  */
37737 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
37738 /*! @} */
37739 
37740 /*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */
37741 /*! @{ */
37742 
37743 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK  (0x1U)
37744 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U)
37745 /*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
37746  *    Address matching is enabled for IPv6 packets.
37747  *  0b0..Layer 3 Protocol is disabled
37748  *  0b1..Layer 3 Protocol is enabled
37749  */
37750 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK)
37751 
37752 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK  (0x4U)
37753 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U)
37754 /*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
37755  *  0b0..Layer 3 IP SA Match is disabled
37756  *  0b1..Layer 3 IP SA Match is enabled
37757  */
37758 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK)
37759 
37760 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U)
37761 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U)
37762 /*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
37763  *    field is enabled for inverse matching.
37764  *  0b0..Layer 3 IP SA Inverse Match is disabled
37765  *  0b1..Layer 3 IP SA Inverse Match is enabled
37766  */
37767 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK)
37768 
37769 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK  (0x10U)
37770 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U)
37771 /*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
37772  *  0b0..Layer 3 IP DA Match is disabled
37773  *  0b1..Layer 3 IP DA Match is enabled
37774  */
37775 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK)
37776 
37777 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U)
37778 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U)
37779 /*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
37780  *    Address field is enabled for inverse matching.
37781  *  0b0..Layer 3 IP DA Inverse Match is disabled
37782  *  0b1..Layer 3 IP DA Inverse Match is enabled
37783  */
37784 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK)
37785 
37786 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U)
37787 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U)
37788 /*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
37789  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
37790  */
37791 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
37792 
37793 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U)
37794 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U)
37795 /*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
37796  *    bits of IP Destination Address that are matched in the IPv4 packets.
37797  */
37798 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
37799 
37800 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK  (0x10000U)
37801 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U)
37802 /*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
37803  *    fields of UDP packets are used for matching.
37804  *  0b0..Layer 4 Protocol is disabled
37805  *  0b1..Layer 4 Protocol is enabled
37806  */
37807 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK)
37808 
37809 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK  (0x40000U)
37810 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U)
37811 /*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
37812  *  0b0..Layer 4 Source Port Match is disabled
37813  *  0b1..Layer 4 Source Port Match is enabled
37814  */
37815 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK)
37816 
37817 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U)
37818 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U)
37819 /*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
37820  *    number field is enabled for inverse matching.
37821  *  0b0..Layer 4 Source Port Inverse Match is disabled
37822  *  0b1..Layer 4 Source Port Inverse Match is enabled
37823  */
37824 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK)
37825 
37826 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK  (0x100000U)
37827 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U)
37828 /*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
37829  *    Port number field is enabled for matching.
37830  *  0b0..Layer 4 Destination Port Match is disabled
37831  *  0b1..Layer 4 Destination Port Match is enabled
37832  */
37833 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK)
37834 
37835 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U)
37836 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U)
37837 /*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
37838  *    Destination Port number field is enabled for inverse matching.
37839  *  0b0..Layer 4 Destination Port Inverse Match is disabled
37840  *  0b1..Layer 4 Destination Port Inverse Match is enabled
37841  */
37842 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK)
37843 
37844 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK  (0x7000000U)
37845 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U)
37846 /*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
37847  *    to which the packet passed by this filter is routed.
37848  */
37849 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK)
37850 
37851 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U)
37852 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U)
37853 /*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
37854  *    number for the packet that is passed by this L3_L4 filter.
37855  *  0b0..DMA Channel Select is disabled
37856  *  0b1..DMA Channel Select is enabled
37857  */
37858 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK)
37859 /*! @} */
37860 
37861 /*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */
37862 /*! @{ */
37863 
37864 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK  (0xFFFFU)
37865 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U)
37866 /*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
37867  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
37868  *    Source Port Number field in the IPv4 or IPv6 packets.
37869  */
37870 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
37871 
37872 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK  (0xFFFF0000U)
37873 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U)
37874 /*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
37875  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
37876  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
37877  */
37878 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
37879 /*! @} */
37880 
37881 /*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */
37882 /*! @{ */
37883 
37884 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU)
37885 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U)
37886 /*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
37887  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
37888  *    Address field in the IPv6 packets.
37889  */
37890 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
37891 /*! @} */
37892 
37893 /*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */
37894 /*! @{ */
37895 
37896 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU)
37897 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U)
37898 /*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
37899  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
37900  *    Address field in the IPv6 packets.
37901  */
37902 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
37903 /*! @} */
37904 
37905 /*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */
37906 /*! @{ */
37907 
37908 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU)
37909 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U)
37910 /*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
37911  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
37912  *    Address field in the IPv6 packets.
37913  */
37914 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
37915 /*! @} */
37916 
37917 /*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */
37918 /*! @{ */
37919 
37920 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU)
37921 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U)
37922 /*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
37923  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
37924  *    Address field in the IPv6 packets.
37925  */
37926 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
37927 /*! @} */
37928 
37929 /*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */
37930 /*! @{ */
37931 
37932 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK  (0x1U)
37933 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U)
37934 /*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
37935  *    Address matching is enabled for IPv6 packets.
37936  *  0b0..Layer 3 Protocol is disabled
37937  *  0b1..Layer 3 Protocol is enabled
37938  */
37939 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK)
37940 
37941 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK  (0x4U)
37942 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U)
37943 /*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
37944  *  0b0..Layer 3 IP SA Match is disabled
37945  *  0b1..Layer 3 IP SA Match is enabled
37946  */
37947 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK)
37948 
37949 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U)
37950 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U)
37951 /*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
37952  *    field is enabled for inverse matching.
37953  *  0b0..Layer 3 IP SA Inverse Match is disabled
37954  *  0b1..Layer 3 IP SA Inverse Match is enabled
37955  */
37956 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK)
37957 
37958 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK  (0x10U)
37959 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U)
37960 /*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
37961  *  0b0..Layer 3 IP DA Match is disabled
37962  *  0b1..Layer 3 IP DA Match is enabled
37963  */
37964 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK)
37965 
37966 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U)
37967 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U)
37968 /*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
37969  *    Address field is enabled for inverse matching.
37970  *  0b0..Layer 3 IP DA Inverse Match is disabled
37971  *  0b1..Layer 3 IP DA Inverse Match is enabled
37972  */
37973 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK)
37974 
37975 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U)
37976 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U)
37977 /*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
37978  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
37979  */
37980 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
37981 
37982 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U)
37983 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U)
37984 /*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
37985  *    bits of IP Destination Address that are matched in the IPv4 packets.
37986  */
37987 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
37988 
37989 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK  (0x10000U)
37990 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U)
37991 /*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
37992  *    fields of UDP packets are used for matching.
37993  *  0b0..Layer 4 Protocol is disabled
37994  *  0b1..Layer 4 Protocol is enabled
37995  */
37996 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK)
37997 
37998 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK  (0x40000U)
37999 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U)
38000 /*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
38001  *  0b0..Layer 4 Source Port Match is disabled
38002  *  0b1..Layer 4 Source Port Match is enabled
38003  */
38004 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK)
38005 
38006 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U)
38007 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U)
38008 /*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
38009  *    number field is enabled for inverse matching.
38010  *  0b0..Layer 4 Source Port Inverse Match is disabled
38011  *  0b1..Layer 4 Source Port Inverse Match is enabled
38012  */
38013 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK)
38014 
38015 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK  (0x100000U)
38016 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U)
38017 /*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
38018  *    Port number field is enabled for matching.
38019  *  0b0..Layer 4 Destination Port Match is disabled
38020  *  0b1..Layer 4 Destination Port Match is enabled
38021  */
38022 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK)
38023 
38024 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U)
38025 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U)
38026 /*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
38027  *    Destination Port number field is enabled for inverse matching.
38028  *  0b0..Layer 4 Destination Port Inverse Match is disabled
38029  *  0b1..Layer 4 Destination Port Inverse Match is enabled
38030  */
38031 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK)
38032 
38033 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK  (0x7000000U)
38034 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U)
38035 /*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
38036  *    to which the packet passed by this filter is routed.
38037  */
38038 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK)
38039 
38040 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U)
38041 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U)
38042 /*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
38043  *    number for the packet that is passed by this L3_L4 filter.
38044  *  0b0..DMA Channel Select is disabled
38045  *  0b1..DMA Channel Select is enabled
38046  */
38047 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK)
38048 /*! @} */
38049 
38050 /*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */
38051 /*! @{ */
38052 
38053 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK  (0xFFFFU)
38054 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U)
38055 /*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
38056  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
38057  *    Source Port Number field in the IPv4 or IPv6 packets.
38058  */
38059 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
38060 
38061 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK  (0xFFFF0000U)
38062 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U)
38063 /*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
38064  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
38065  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
38066  */
38067 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
38068 /*! @} */
38069 
38070 /*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */
38071 /*! @{ */
38072 
38073 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU)
38074 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U)
38075 /*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
38076  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
38077  *    Address field in the IPv6 packets.
38078  */
38079 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
38080 /*! @} */
38081 
38082 /*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */
38083 /*! @{ */
38084 
38085 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU)
38086 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U)
38087 /*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
38088  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
38089  *    Address field in the IPv6 packets.
38090  */
38091 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
38092 /*! @} */
38093 
38094 /*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */
38095 /*! @{ */
38096 
38097 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU)
38098 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U)
38099 /*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
38100  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
38101  *    Address field in the IPv6 packets.
38102  */
38103 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
38104 /*! @} */
38105 
38106 /*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */
38107 /*! @{ */
38108 
38109 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU)
38110 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U)
38111 /*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
38112  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
38113  *    Address field in the IPv6 packets.
38114  */
38115 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
38116 /*! @} */
38117 
38118 /*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */
38119 /*! @{ */
38120 
38121 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK  (0x1U)
38122 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U)
38123 /*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
38124  *    Address matching is enabled for IPv6 packets.
38125  *  0b0..Layer 3 Protocol is disabled
38126  *  0b1..Layer 3 Protocol is enabled
38127  */
38128 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK)
38129 
38130 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK  (0x4U)
38131 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U)
38132 /*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
38133  *  0b0..Layer 3 IP SA Match is disabled
38134  *  0b1..Layer 3 IP SA Match is enabled
38135  */
38136 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK)
38137 
38138 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U)
38139 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U)
38140 /*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
38141  *    field is enabled for inverse matching.
38142  *  0b0..Layer 3 IP SA Inverse Match is disabled
38143  *  0b1..Layer 3 IP SA Inverse Match is enabled
38144  */
38145 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK)
38146 
38147 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK  (0x10U)
38148 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U)
38149 /*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
38150  *  0b0..Layer 3 IP DA Match is disabled
38151  *  0b1..Layer 3 IP DA Match is enabled
38152  */
38153 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK)
38154 
38155 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U)
38156 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U)
38157 /*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
38158  *    Address field is enabled for inverse matching.
38159  *  0b0..Layer 3 IP DA Inverse Match is disabled
38160  *  0b1..Layer 3 IP DA Inverse Match is enabled
38161  */
38162 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK)
38163 
38164 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U)
38165 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U)
38166 /*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
38167  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
38168  */
38169 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
38170 
38171 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U)
38172 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U)
38173 /*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
38174  *    bits of IP Destination Address that are matched in the IPv4 packets.
38175  */
38176 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
38177 
38178 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK  (0x10000U)
38179 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U)
38180 /*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
38181  *    fields of UDP packets are used for matching.
38182  *  0b0..Layer 4 Protocol is disabled
38183  *  0b1..Layer 4 Protocol is enabled
38184  */
38185 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK)
38186 
38187 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK  (0x40000U)
38188 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U)
38189 /*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
38190  *  0b0..Layer 4 Source Port Match is disabled
38191  *  0b1..Layer 4 Source Port Match is enabled
38192  */
38193 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK)
38194 
38195 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U)
38196 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U)
38197 /*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
38198  *    number field is enabled for inverse matching.
38199  *  0b0..Layer 4 Source Port Inverse Match is disabled
38200  *  0b1..Layer 4 Source Port Inverse Match is enabled
38201  */
38202 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK)
38203 
38204 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK  (0x100000U)
38205 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U)
38206 /*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
38207  *    Port number field is enabled for matching.
38208  *  0b0..Layer 4 Destination Port Match is disabled
38209  *  0b1..Layer 4 Destination Port Match is enabled
38210  */
38211 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK)
38212 
38213 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U)
38214 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U)
38215 /*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
38216  *    Destination Port number field is enabled for inverse matching.
38217  *  0b0..Layer 4 Destination Port Inverse Match is disabled
38218  *  0b1..Layer 4 Destination Port Inverse Match is enabled
38219  */
38220 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK)
38221 
38222 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK  (0x7000000U)
38223 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U)
38224 /*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
38225  *    to which the packet passed by this filter is routed.
38226  */
38227 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK)
38228 
38229 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U)
38230 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U)
38231 /*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
38232  *    number for the packet that is passed by this L3_L4 filter.
38233  *  0b0..DMA Channel Select is disabled
38234  *  0b1..DMA Channel Select is enabled
38235  */
38236 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK)
38237 /*! @} */
38238 
38239 /*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */
38240 /*! @{ */
38241 
38242 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK  (0xFFFFU)
38243 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U)
38244 /*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
38245  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
38246  *    Source Port Number field in the IPv4 or IPv6 packets.
38247  */
38248 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
38249 
38250 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK  (0xFFFF0000U)
38251 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U)
38252 /*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
38253  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
38254  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
38255  */
38256 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
38257 /*! @} */
38258 
38259 /*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */
38260 /*! @{ */
38261 
38262 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU)
38263 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U)
38264 /*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
38265  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
38266  *    Address field in the IPv6 packets.
38267  */
38268 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
38269 /*! @} */
38270 
38271 /*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */
38272 /*! @{ */
38273 
38274 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU)
38275 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U)
38276 /*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
38277  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
38278  *    Address field in the IPv6 packets.
38279  */
38280 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
38281 /*! @} */
38282 
38283 /*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */
38284 /*! @{ */
38285 
38286 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU)
38287 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U)
38288 /*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
38289  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
38290  *    Address field in the IPv6 packets.
38291  */
38292 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
38293 /*! @} */
38294 
38295 /*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */
38296 /*! @{ */
38297 
38298 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU)
38299 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U)
38300 /*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
38301  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
38302  *    Address field in the IPv6 packets.
38303  */
38304 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
38305 /*! @} */
38306 
38307 /*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */
38308 /*! @{ */
38309 
38310 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK  (0x1U)
38311 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U)
38312 /*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
38313  *    Address matching is enabled for IPv6 packets.
38314  *  0b0..Layer 3 Protocol is disabled
38315  *  0b1..Layer 3 Protocol is enabled
38316  */
38317 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK)
38318 
38319 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK  (0x4U)
38320 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U)
38321 /*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
38322  *  0b0..Layer 3 IP SA Match is disabled
38323  *  0b1..Layer 3 IP SA Match is enabled
38324  */
38325 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK)
38326 
38327 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U)
38328 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U)
38329 /*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
38330  *    field is enabled for inverse matching.
38331  *  0b0..Layer 3 IP SA Inverse Match is disabled
38332  *  0b1..Layer 3 IP SA Inverse Match is enabled
38333  */
38334 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK)
38335 
38336 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK  (0x10U)
38337 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U)
38338 /*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
38339  *  0b0..Layer 3 IP DA Match is disabled
38340  *  0b1..Layer 3 IP DA Match is enabled
38341  */
38342 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK)
38343 
38344 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U)
38345 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U)
38346 /*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
38347  *    Address field is enabled for inverse matching.
38348  *  0b0..Layer 3 IP DA Inverse Match is disabled
38349  *  0b1..Layer 3 IP DA Inverse Match is enabled
38350  */
38351 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK)
38352 
38353 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U)
38354 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U)
38355 /*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
38356  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
38357  */
38358 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
38359 
38360 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U)
38361 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U)
38362 /*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
38363  *    bits of IP Destination Address that are matched in the IPv4 packets.
38364  */
38365 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
38366 
38367 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK  (0x10000U)
38368 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U)
38369 /*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
38370  *    fields of UDP packets are used for matching.
38371  *  0b0..Layer 4 Protocol is disabled
38372  *  0b1..Layer 4 Protocol is enabled
38373  */
38374 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK)
38375 
38376 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK  (0x40000U)
38377 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U)
38378 /*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
38379  *  0b0..Layer 4 Source Port Match is disabled
38380  *  0b1..Layer 4 Source Port Match is enabled
38381  */
38382 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK)
38383 
38384 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U)
38385 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U)
38386 /*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
38387  *    number field is enabled for inverse matching.
38388  *  0b0..Layer 4 Source Port Inverse Match is disabled
38389  *  0b1..Layer 4 Source Port Inverse Match is enabled
38390  */
38391 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK)
38392 
38393 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK  (0x100000U)
38394 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U)
38395 /*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
38396  *    Port number field is enabled for matching.
38397  *  0b0..Layer 4 Destination Port Match is disabled
38398  *  0b1..Layer 4 Destination Port Match is enabled
38399  */
38400 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK)
38401 
38402 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U)
38403 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U)
38404 /*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
38405  *    Destination Port number field is enabled for inverse matching.
38406  *  0b0..Layer 4 Destination Port Inverse Match is disabled
38407  *  0b1..Layer 4 Destination Port Inverse Match is enabled
38408  */
38409 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK)
38410 
38411 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK  (0x7000000U)
38412 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U)
38413 /*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
38414  *    to which the packet passed by this filter is routed.
38415  */
38416 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK)
38417 
38418 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U)
38419 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U)
38420 /*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
38421  *    number for the packet that is passed by this L3_L4 filter.
38422  *  0b0..DMA Channel Select is disabled
38423  *  0b1..DMA Channel Select is enabled
38424  */
38425 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK)
38426 /*! @} */
38427 
38428 /*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */
38429 /*! @{ */
38430 
38431 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK  (0xFFFFU)
38432 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U)
38433 /*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
38434  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
38435  *    Source Port Number field in the IPv4 or IPv6 packets.
38436  */
38437 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
38438 
38439 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK  (0xFFFF0000U)
38440 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U)
38441 /*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
38442  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
38443  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
38444  */
38445 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
38446 /*! @} */
38447 
38448 /*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */
38449 /*! @{ */
38450 
38451 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU)
38452 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U)
38453 /*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
38454  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
38455  *    Address field in the IPv6 packets.
38456  */
38457 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
38458 /*! @} */
38459 
38460 /*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */
38461 /*! @{ */
38462 
38463 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU)
38464 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U)
38465 /*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
38466  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
38467  *    Address field in the IPv6 packets.
38468  */
38469 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
38470 /*! @} */
38471 
38472 /*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */
38473 /*! @{ */
38474 
38475 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU)
38476 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U)
38477 /*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
38478  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
38479  *    Address field in the IPv6 packets.
38480  */
38481 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
38482 /*! @} */
38483 
38484 /*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */
38485 /*! @{ */
38486 
38487 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU)
38488 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U)
38489 /*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
38490  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
38491  *    Address field in the IPv6 packets.
38492  */
38493 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
38494 /*! @} */
38495 
38496 /*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */
38497 /*! @{ */
38498 
38499 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK  (0x1U)
38500 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U)
38501 /*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
38502  *    Address matching is enabled for IPv6 packets.
38503  *  0b0..Layer 3 Protocol is disabled
38504  *  0b1..Layer 3 Protocol is enabled
38505  */
38506 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK)
38507 
38508 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK  (0x4U)
38509 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U)
38510 /*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
38511  *  0b0..Layer 3 IP SA Match is disabled
38512  *  0b1..Layer 3 IP SA Match is enabled
38513  */
38514 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK)
38515 
38516 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U)
38517 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U)
38518 /*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
38519  *    field is enabled for inverse matching.
38520  *  0b0..Layer 3 IP SA Inverse Match is disabled
38521  *  0b1..Layer 3 IP SA Inverse Match is enabled
38522  */
38523 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK)
38524 
38525 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK  (0x10U)
38526 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U)
38527 /*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
38528  *  0b0..Layer 3 IP DA Match is disabled
38529  *  0b1..Layer 3 IP DA Match is enabled
38530  */
38531 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK)
38532 
38533 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U)
38534 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U)
38535 /*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
38536  *    Address field is enabled for inverse matching.
38537  *  0b0..Layer 3 IP DA Inverse Match is disabled
38538  *  0b1..Layer 3 IP DA Inverse Match is enabled
38539  */
38540 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK)
38541 
38542 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U)
38543 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U)
38544 /*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
38545  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
38546  */
38547 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK)
38548 
38549 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U)
38550 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U)
38551 /*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
38552  *    bits of IP Destination Address that are matched in the IPv4 packets.
38553  */
38554 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK)
38555 
38556 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK  (0x10000U)
38557 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U)
38558 /*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
38559  *    fields of UDP packets are used for matching.
38560  *  0b0..Layer 4 Protocol is disabled
38561  *  0b1..Layer 4 Protocol is enabled
38562  */
38563 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK)
38564 
38565 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK  (0x40000U)
38566 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U)
38567 /*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
38568  *  0b0..Layer 4 Source Port Match is disabled
38569  *  0b1..Layer 4 Source Port Match is enabled
38570  */
38571 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK)
38572 
38573 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U)
38574 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U)
38575 /*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
38576  *    number field is enabled for inverse matching.
38577  *  0b0..Layer 4 Source Port Inverse Match is disabled
38578  *  0b1..Layer 4 Source Port Inverse Match is enabled
38579  */
38580 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK)
38581 
38582 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK  (0x100000U)
38583 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U)
38584 /*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
38585  *    Port number field is enabled for matching.
38586  *  0b0..Layer 4 Destination Port Match is disabled
38587  *  0b1..Layer 4 Destination Port Match is enabled
38588  */
38589 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK)
38590 
38591 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U)
38592 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U)
38593 /*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
38594  *    Destination Port number field is enabled for inverse matching.
38595  *  0b0..Layer 4 Destination Port Inverse Match is disabled
38596  *  0b1..Layer 4 Destination Port Inverse Match is enabled
38597  */
38598 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK)
38599 
38600 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK  (0x7000000U)
38601 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U)
38602 /*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
38603  *    to which the packet passed by this filter is routed.
38604  */
38605 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK)
38606 
38607 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U)
38608 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U)
38609 /*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
38610  *    number for the packet that is passed by this L3_L4 filter.
38611  *  0b0..DMA Channel Select is disabled
38612  *  0b1..DMA Channel Select is enabled
38613  */
38614 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK)
38615 /*! @} */
38616 
38617 /*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */
38618 /*! @{ */
38619 
38620 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK  (0xFFFFU)
38621 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U)
38622 /*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
38623  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
38624  *    Source Port Number field in the IPv4 or IPv6 packets.
38625  */
38626 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK)
38627 
38628 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK  (0xFFFF0000U)
38629 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U)
38630 /*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
38631  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
38632  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
38633  */
38634 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK)
38635 /*! @} */
38636 
38637 /*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */
38638 /*! @{ */
38639 
38640 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU)
38641 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U)
38642 /*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
38643  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
38644  *    Address field in the IPv6 packets.
38645  */
38646 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK)
38647 /*! @} */
38648 
38649 /*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */
38650 /*! @{ */
38651 
38652 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU)
38653 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U)
38654 /*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
38655  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
38656  *    Address field in the IPv6 packets.
38657  */
38658 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK)
38659 /*! @} */
38660 
38661 /*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */
38662 /*! @{ */
38663 
38664 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU)
38665 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U)
38666 /*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
38667  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
38668  *    Address field in the IPv6 packets.
38669  */
38670 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK)
38671 /*! @} */
38672 
38673 /*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */
38674 /*! @{ */
38675 
38676 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU)
38677 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U)
38678 /*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
38679  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
38680  *    Address field in the IPv6 packets.
38681  */
38682 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK)
38683 /*! @} */
38684 
38685 /*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */
38686 /*! @{ */
38687 
38688 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK  (0x1U)
38689 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U)
38690 /*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
38691  *    Address matching is enabled for IPv6 packets.
38692  *  0b0..Layer 3 Protocol is disabled
38693  *  0b1..Layer 3 Protocol is enabled
38694  */
38695 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK)
38696 
38697 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK  (0x4U)
38698 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U)
38699 /*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
38700  *  0b0..Layer 3 IP SA Match is disabled
38701  *  0b1..Layer 3 IP SA Match is enabled
38702  */
38703 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK)
38704 
38705 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U)
38706 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U)
38707 /*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
38708  *    field is enabled for inverse matching.
38709  *  0b0..Layer 3 IP SA Inverse Match is disabled
38710  *  0b1..Layer 3 IP SA Inverse Match is enabled
38711  */
38712 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK)
38713 
38714 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK  (0x10U)
38715 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U)
38716 /*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
38717  *  0b0..Layer 3 IP DA Match is disabled
38718  *  0b1..Layer 3 IP DA Match is enabled
38719  */
38720 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK)
38721 
38722 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U)
38723 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U)
38724 /*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
38725  *    Address field is enabled for inverse matching.
38726  *  0b0..Layer 3 IP DA Inverse Match is disabled
38727  *  0b1..Layer 3 IP DA Inverse Match is enabled
38728  */
38729 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK)
38730 
38731 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U)
38732 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U)
38733 /*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
38734  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
38735  */
38736 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK)
38737 
38738 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U)
38739 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U)
38740 /*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
38741  *    bits of IP Destination Address that are matched in the IPv4 packets.
38742  */
38743 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK)
38744 
38745 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK  (0x10000U)
38746 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U)
38747 /*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
38748  *    fields of UDP packets are used for matching.
38749  *  0b0..Layer 4 Protocol is disabled
38750  *  0b1..Layer 4 Protocol is enabled
38751  */
38752 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK)
38753 
38754 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK  (0x40000U)
38755 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U)
38756 /*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
38757  *  0b0..Layer 4 Source Port Match is disabled
38758  *  0b1..Layer 4 Source Port Match is enabled
38759  */
38760 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK)
38761 
38762 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U)
38763 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U)
38764 /*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
38765  *    number field is enabled for inverse matching.
38766  *  0b0..Layer 4 Source Port Inverse Match is disabled
38767  *  0b1..Layer 4 Source Port Inverse Match is enabled
38768  */
38769 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK)
38770 
38771 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK  (0x100000U)
38772 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U)
38773 /*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
38774  *    Port number field is enabled for matching.
38775  *  0b0..Layer 4 Destination Port Match is disabled
38776  *  0b1..Layer 4 Destination Port Match is enabled
38777  */
38778 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK)
38779 
38780 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U)
38781 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U)
38782 /*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
38783  *    Destination Port number field is enabled for inverse matching.
38784  *  0b0..Layer 4 Destination Port Inverse Match is disabled
38785  *  0b1..Layer 4 Destination Port Inverse Match is enabled
38786  */
38787 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK)
38788 
38789 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK  (0x7000000U)
38790 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U)
38791 /*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
38792  *    to which the packet passed by this filter is routed.
38793  */
38794 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK)
38795 
38796 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U)
38797 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U)
38798 /*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
38799  *    number for the packet that is passed by this L3_L4 filter.
38800  *  0b0..DMA Channel Select is disabled
38801  *  0b1..DMA Channel Select is enabled
38802  */
38803 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK)
38804 /*! @} */
38805 
38806 /*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */
38807 /*! @{ */
38808 
38809 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK  (0xFFFFU)
38810 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U)
38811 /*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
38812  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
38813  *    Source Port Number field in the IPv4 or IPv6 packets.
38814  */
38815 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK)
38816 
38817 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK  (0xFFFF0000U)
38818 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U)
38819 /*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
38820  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
38821  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
38822  */
38823 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK)
38824 /*! @} */
38825 
38826 /*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */
38827 /*! @{ */
38828 
38829 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU)
38830 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U)
38831 /*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
38832  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
38833  *    Address field in the IPv6 packets.
38834  */
38835 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK)
38836 /*! @} */
38837 
38838 /*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */
38839 /*! @{ */
38840 
38841 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU)
38842 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U)
38843 /*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
38844  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
38845  *    Address field in the IPv6 packets.
38846  */
38847 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK)
38848 /*! @} */
38849 
38850 /*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */
38851 /*! @{ */
38852 
38853 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU)
38854 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U)
38855 /*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
38856  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
38857  *    Address field in the IPv6 packets.
38858  */
38859 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK)
38860 /*! @} */
38861 
38862 /*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */
38863 /*! @{ */
38864 
38865 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU)
38866 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U)
38867 /*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
38868  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
38869  *    Address field in the IPv6 packets.
38870  */
38871 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK)
38872 /*! @} */
38873 
38874 /*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */
38875 /*! @{ */
38876 
38877 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK  (0x1U)
38878 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U)
38879 /*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
38880  *    Address matching is enabled for IPv6 packets.
38881  *  0b0..Layer 3 Protocol is disabled
38882  *  0b1..Layer 3 Protocol is enabled
38883  */
38884 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK)
38885 
38886 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK  (0x4U)
38887 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U)
38888 /*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
38889  *  0b0..Layer 3 IP SA Match is disabled
38890  *  0b1..Layer 3 IP SA Match is enabled
38891  */
38892 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK)
38893 
38894 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U)
38895 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U)
38896 /*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
38897  *    field is enabled for inverse matching.
38898  *  0b0..Layer 3 IP SA Inverse Match is disabled
38899  *  0b1..Layer 3 IP SA Inverse Match is enabled
38900  */
38901 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK)
38902 
38903 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK  (0x10U)
38904 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U)
38905 /*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
38906  *  0b0..Layer 3 IP DA Match is disabled
38907  *  0b1..Layer 3 IP DA Match is enabled
38908  */
38909 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK)
38910 
38911 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U)
38912 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U)
38913 /*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
38914  *    Address field is enabled for inverse matching.
38915  *  0b0..Layer 3 IP DA Inverse Match is disabled
38916  *  0b1..Layer 3 IP DA Inverse Match is enabled
38917  */
38918 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK)
38919 
38920 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U)
38921 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U)
38922 /*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
38923  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
38924  */
38925 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK)
38926 
38927 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U)
38928 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U)
38929 /*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
38930  *    bits of IP Destination Address that are matched in the IPv4 packets.
38931  */
38932 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK)
38933 
38934 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK  (0x10000U)
38935 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U)
38936 /*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
38937  *    fields of UDP packets are used for matching.
38938  *  0b0..Layer 4 Protocol is disabled
38939  *  0b1..Layer 4 Protocol is enabled
38940  */
38941 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK)
38942 
38943 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK  (0x40000U)
38944 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U)
38945 /*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
38946  *  0b0..Layer 4 Source Port Match is disabled
38947  *  0b1..Layer 4 Source Port Match is enabled
38948  */
38949 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK)
38950 
38951 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U)
38952 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U)
38953 /*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
38954  *    number field is enabled for inverse matching.
38955  *  0b0..Layer 4 Source Port Inverse Match is disabled
38956  *  0b1..Layer 4 Source Port Inverse Match is enabled
38957  */
38958 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK)
38959 
38960 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK  (0x100000U)
38961 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U)
38962 /*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
38963  *    Port number field is enabled for matching.
38964  *  0b0..Layer 4 Destination Port Match is disabled
38965  *  0b1..Layer 4 Destination Port Match is enabled
38966  */
38967 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK)
38968 
38969 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U)
38970 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U)
38971 /*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
38972  *    Destination Port number field is enabled for inverse matching.
38973  *  0b0..Layer 4 Destination Port Inverse Match is disabled
38974  *  0b1..Layer 4 Destination Port Inverse Match is enabled
38975  */
38976 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK)
38977 
38978 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK  (0x7000000U)
38979 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U)
38980 /*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
38981  *    to which the packet passed by this filter is routed.
38982  */
38983 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK)
38984 
38985 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U)
38986 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U)
38987 /*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
38988  *    number for the packet that is passed by this L3_L4 filter.
38989  *  0b0..DMA Channel Select is disabled
38990  *  0b1..DMA Channel Select is enabled
38991  */
38992 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK)
38993 /*! @} */
38994 
38995 /*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */
38996 /*! @{ */
38997 
38998 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK  (0xFFFFU)
38999 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U)
39000 /*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
39001  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
39002  *    Source Port Number field in the IPv4 or IPv6 packets.
39003  */
39004 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK)
39005 
39006 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK  (0xFFFF0000U)
39007 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U)
39008 /*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
39009  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
39010  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
39011  */
39012 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK)
39013 /*! @} */
39014 
39015 /*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */
39016 /*! @{ */
39017 
39018 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU)
39019 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U)
39020 /*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
39021  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
39022  *    Address field in the IPv6 packets.
39023  */
39024 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK)
39025 /*! @} */
39026 
39027 /*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */
39028 /*! @{ */
39029 
39030 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU)
39031 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U)
39032 /*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
39033  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
39034  *    Address field in the IPv6 packets.
39035  */
39036 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK)
39037 /*! @} */
39038 
39039 /*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */
39040 /*! @{ */
39041 
39042 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU)
39043 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U)
39044 /*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
39045  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
39046  *    Address field in the IPv6 packets.
39047  */
39048 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK)
39049 /*! @} */
39050 
39051 /*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */
39052 /*! @{ */
39053 
39054 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU)
39055 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U)
39056 /*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
39057  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
39058  *    Address field in the IPv6 packets.
39059  */
39060 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK)
39061 /*! @} */
39062 
39063 /*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */
39064 /*! @{ */
39065 
39066 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK  (0x1U)
39067 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U)
39068 /*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
39069  *    Address matching is enabled for IPv6 packets.
39070  *  0b0..Layer 3 Protocol is disabled
39071  *  0b1..Layer 3 Protocol is enabled
39072  */
39073 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK)
39074 
39075 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK  (0x4U)
39076 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U)
39077 /*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
39078  *  0b0..Layer 3 IP SA Match is disabled
39079  *  0b1..Layer 3 IP SA Match is enabled
39080  */
39081 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK)
39082 
39083 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U)
39084 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U)
39085 /*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
39086  *    field is enabled for inverse matching.
39087  *  0b0..Layer 3 IP SA Inverse Match is disabled
39088  *  0b1..Layer 3 IP SA Inverse Match is enabled
39089  */
39090 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK)
39091 
39092 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK  (0x10U)
39093 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U)
39094 /*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
39095  *  0b0..Layer 3 IP DA Match is disabled
39096  *  0b1..Layer 3 IP DA Match is enabled
39097  */
39098 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK)
39099 
39100 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U)
39101 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U)
39102 /*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
39103  *    Address field is enabled for inverse matching.
39104  *  0b0..Layer 3 IP DA Inverse Match is disabled
39105  *  0b1..Layer 3 IP DA Inverse Match is enabled
39106  */
39107 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK)
39108 
39109 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U)
39110 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U)
39111 /*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
39112  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
39113  */
39114 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK)
39115 
39116 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U)
39117 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U)
39118 /*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
39119  *    bits of IP Destination Address that are matched in the IPv4 packets.
39120  */
39121 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK)
39122 
39123 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK  (0x10000U)
39124 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U)
39125 /*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
39126  *    fields of UDP packets are used for matching.
39127  *  0b0..Layer 4 Protocol is disabled
39128  *  0b1..Layer 4 Protocol is enabled
39129  */
39130 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK)
39131 
39132 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK  (0x40000U)
39133 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U)
39134 /*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
39135  *  0b0..Layer 4 Source Port Match is disabled
39136  *  0b1..Layer 4 Source Port Match is enabled
39137  */
39138 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK)
39139 
39140 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U)
39141 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U)
39142 /*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
39143  *    number field is enabled for inverse matching.
39144  *  0b0..Layer 4 Source Port Inverse Match is disabled
39145  *  0b1..Layer 4 Source Port Inverse Match is enabled
39146  */
39147 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK)
39148 
39149 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK  (0x100000U)
39150 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U)
39151 /*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
39152  *    Port number field is enabled for matching.
39153  *  0b0..Layer 4 Destination Port Match is disabled
39154  *  0b1..Layer 4 Destination Port Match is enabled
39155  */
39156 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK)
39157 
39158 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U)
39159 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U)
39160 /*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
39161  *    Destination Port number field is enabled for inverse matching.
39162  *  0b0..Layer 4 Destination Port Inverse Match is disabled
39163  *  0b1..Layer 4 Destination Port Inverse Match is enabled
39164  */
39165 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK)
39166 
39167 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK  (0x7000000U)
39168 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U)
39169 /*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
39170  *    to which the packet passed by this filter is routed.
39171  */
39172 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK)
39173 
39174 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U)
39175 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U)
39176 /*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
39177  *    number for the packet that is passed by this L3_L4 filter.
39178  *  0b0..DMA Channel Select is disabled
39179  *  0b1..DMA Channel Select is enabled
39180  */
39181 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK)
39182 /*! @} */
39183 
39184 /*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */
39185 /*! @{ */
39186 
39187 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK  (0xFFFFU)
39188 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U)
39189 /*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
39190  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
39191  *    Source Port Number field in the IPv4 or IPv6 packets.
39192  */
39193 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK)
39194 
39195 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK  (0xFFFF0000U)
39196 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U)
39197 /*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
39198  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
39199  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
39200  */
39201 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK)
39202 /*! @} */
39203 
39204 /*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */
39205 /*! @{ */
39206 
39207 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU)
39208 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U)
39209 /*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
39210  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
39211  *    Address field in the IPv6 packets.
39212  */
39213 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK)
39214 /*! @} */
39215 
39216 /*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */
39217 /*! @{ */
39218 
39219 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU)
39220 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U)
39221 /*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
39222  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
39223  *    Address field in the IPv6 packets.
39224  */
39225 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK)
39226 /*! @} */
39227 
39228 /*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */
39229 /*! @{ */
39230 
39231 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU)
39232 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U)
39233 /*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
39234  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
39235  *    Address field in the IPv6 packets.
39236  */
39237 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK)
39238 /*! @} */
39239 
39240 /*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */
39241 /*! @{ */
39242 
39243 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU)
39244 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U)
39245 /*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
39246  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
39247  *    Address field in the IPv6 packets.
39248  */
39249 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK)
39250 /*! @} */
39251 
39252 /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
39253 /*! @{ */
39254 
39255 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U)
39256 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
39257 /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
39258  *  0b0..Timestamp is disabled
39259  *  0b1..Timestamp is enabled
39260  */
39261 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
39262 
39263 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
39264 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
39265 /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
39266  *  0b0..Coarse method is used to update system timestamp
39267  *  0b1..Fine method is used to update system timestamp
39268  */
39269 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
39270 
39271 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U)
39272 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
39273 /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
39274  *    with the value specified in the MAC_System_Time_Seconds_Update and
39275  *    MAC_System_Time_Nanoseconds_Update registers.
39276  *  0b0..Timestamp is not initialized
39277  *  0b1..Timestamp is initialized
39278  */
39279 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
39280 
39281 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U)
39282 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
39283 /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
39284  *    with the value specified in MAC_System_Time_Seconds_Update and
39285  *    MAC_System_Time_Nanoseconds_Update registers.
39286  *  0b0..Timestamp is not updated
39287  *  0b1..Timestamp is updated
39288  */
39289 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
39290 
39291 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
39292 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
39293 /*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
39294  *    register is updated in the PTP block for fine correction.
39295  *  0b0..Addend Register is not updated
39296  *  0b1..Addend Register is updated
39297  */
39298 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
39299 
39300 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U)
39301 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U)
39302 /*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled.
39303  *  0b0..Presentation Time Generation is disabled
39304  *  0b1..Presentation Time Generation is enabled
39305  */
39306 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK)
39307 
39308 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U)
39309 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
39310 /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
39311  *    enabled for all packets received by the MAC.
39312  *  0b0..Timestamp for All Packets disabled
39313  *  0b1..Timestamp for All Packets enabled
39314  */
39315 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
39316 
39317 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
39318 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
39319 /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
39320  *    register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments
39321  *    the timestamp (High) seconds.
39322  *  0b0..Timestamp Digital or Binary Rollover Control is disabled
39323  *  0b1..Timestamp Digital or Binary Rollover Control is enabled
39324  */
39325 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
39326 
39327 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
39328 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
39329 /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
39330  *    1588 version 2 format is used to process the PTP packets.
39331  *  0b0..PTP Packet Processing for Version 2 Format is disabled
39332  *  0b1..PTP Packet Processing for Version 2 Format is enabled
39333  */
39334 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
39335 
39336 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U)
39337 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
39338 /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
39339  *    processes the PTP packets encapsulated directly in the Ethernet packets.
39340  *  0b0..Processing of PTP over Ethernet Packets is disabled
39341  *  0b1..Processing of PTP over Ethernet Packets is enabled
39342  */
39343 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
39344 
39345 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
39346 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
39347 /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC
39348  *    receiver processes the PTP packets encapsulated in IPv6-UDP packets.
39349  *  0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
39350  *  0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
39351  */
39352 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
39353 
39354 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
39355 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
39356 /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
39357  *    receiver processes the PTP packets encapsulated in IPv4-UDP packets.
39358  *  0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
39359  *  0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
39360  */
39361 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
39362 
39363 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
39364 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
39365 /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
39366  *    snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
39367  *  0b0..Timestamp Snapshot for Event Messages is disabled
39368  *  0b1..Timestamp Snapshot for Event Messages is enabled
39369  */
39370 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
39371 
39372 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
39373 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
39374 /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
39375  *    is taken only for the messages that are relevant to the master node.
39376  *  0b0..Snapshot for Messages Relevant to Master is disabled
39377  *  0b1..Snapshot for Messages Relevant to Master is enabled
39378  */
39379 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
39380 
39381 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
39382 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
39383 /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
39384  *    decide the set of PTP packet types for which snapshot needs to be taken.
39385  */
39386 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
39387 
39388 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
39389 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
39390 /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
39391  *    address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
39392  *    directly sent over Ethernet.
39393  *  0b0..MAC Address for PTP Packet Filtering is disabled
39394  *  0b1..MAC Address for PTP Packet Filtering is enabled
39395  */
39396 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
39397 
39398 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK  (0x80000U)
39399 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U)
39400 /*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set,
39401  *    the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum
39402  *    correct, for changes made to origin timestamp and/or correction field as part of one step timestamp
39403  *    operation.
39404  *  0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled
39405  *  0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled
39406  */
39407 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK)
39408 
39409 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U)
39410 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
39411 /*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit
39412  *    reference System Time input for the following: - To take the timestamp provided as status - To insert
39413  *    the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is
39414  *    enabled.
39415  *  0b0..External System Time Input is disabled
39416  *  0b1..External System Time Input is enabled
39417  */
39418 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
39419 
39420 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
39421 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
39422 /*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
39423  *    transmit timestamp status even if it is not read by the software.
39424  *  0b0..Transmit Timestamp Status Mode is disabled
39425  *  0b1..Transmit Timestamp Status Mode is enabled
39426  */
39427 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
39428 
39429 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
39430 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
39431 /*! AV8021ASMEN - AV 802.
39432  *  0b0..AV 802.1AS Mode is disabled
39433  *  0b1..AV 802.1AS Mode is enabled
39434  */
39435 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
39436 /*! @} */
39437 
39438 /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
39439 /*! @{ */
39440 
39441 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U)
39442 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U)
39443 /*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value,
39444  *    represented in nanoseconds multiplied by 2^8.
39445  */
39446 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
39447 
39448 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U)
39449 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
39450 /*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock
39451  *    cycle (of clk_ptp_i) with the contents of the sub-second register.
39452  */
39453 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
39454 /*! @} */
39455 
39456 /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
39457 /*! @{ */
39458 
39459 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU)
39460 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U)
39461 /*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the
39462  *    System Time maintained by the MAC.
39463  */
39464 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
39465 /*! @} */
39466 
39467 /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
39468 /*! @{ */
39469 
39470 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
39471 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
39472 /*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0. */
39473 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
39474 /*! @} */
39475 
39476 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
39477 /*! @{ */
39478 
39479 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
39480 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
39481 /*! TSS - Timestamp Seconds The value in this field is the seconds part of the update. */
39482 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
39483 /*! @} */
39484 
39485 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
39486 /*! @{ */
39487 
39488 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
39489 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
39490 /*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. */
39491 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
39492 
39493 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
39494 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
39495 /*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register.
39496  *  0b0..Add time
39497  *  0b1..Subtract time
39498  */
39499 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
39500 /*! @} */
39501 
39502 /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
39503 /*! @{ */
39504 
39505 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK  (0xFFFFFFFFU)
39506 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
39507 /*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the
39508  *    Accumulator register to achieve time synchronization.
39509  */
39510 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
39511 /*! @} */
39512 
39513 /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */
39514 /*! @{ */
39515 
39516 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU)
39517 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U)
39518 /*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. */
39519 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
39520 /*! @} */
39521 
39522 /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
39523 /*! @{ */
39524 
39525 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U)
39526 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
39527 /*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of
39528  *    the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
39529  *  0b1..Timestamp Seconds Overflow status detected
39530  *  0b0..Timestamp Seconds Overflow status not detected
39531  */
39532 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
39533 
39534 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U)
39535 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
39536 /*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system
39537  *    time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and
39538  *    MAC_PPS0_Target_Time_Nanoseconds registers.
39539  *  0b1..Timestamp Target Time Reached status detected
39540  *  0b0..Timestamp Target Time Reached status not detected
39541  */
39542 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
39543 
39544 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U)
39545 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
39546 /*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO.
39547  *  0b1..Auxiliary Timestamp Trigger Snapshot status detected
39548  *  0b0..Auxiliary Timestamp Trigger Snapshot status not detected
39549  */
39550 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK)
39551 
39552 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
39553 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
39554 /*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed
39555  *    in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses.
39556  *  0b1..Timestamp Target Time Error status detected
39557  *  0b0..Timestamp Target Time Error status not detected
39558  */
39559 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
39560 
39561 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U)
39562 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U)
39563 /*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that
39564  *    the value of system time is greater than or equal to the value specified in the
39565  *    MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers.
39566  *  0b1..Timestamp Target Time Reached for Target Time PPS1 status detected
39567  *  0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected
39568  */
39569 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK)
39570 
39571 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U)
39572 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U)
39573 /*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed
39574  *    in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses.
39575  *  0b1..Timestamp Target Time Error status detected
39576  *  0b0..Timestamp Target Time Error status not detected
39577  */
39578 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK)
39579 
39580 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U)
39581 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U)
39582 /*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that
39583  *    the value of system time is greater than or equal to the value specified in the
39584  *    MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers.
39585  *  0b1..Timestamp Target Time Reached for Target Time PPS2 status detected
39586  *  0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected
39587  */
39588 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK)
39589 
39590 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U)
39591 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U)
39592 /*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed
39593  *    in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses.
39594  *  0b1..Timestamp Target Time Error status detected
39595  *  0b0..Timestamp Target Time Error status not detected
39596  */
39597 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK)
39598 
39599 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U)
39600 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U)
39601 /*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates
39602  *    that the value of system time is greater than or equal to the value specified in the
39603  *    MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers.
39604  *  0b1..Timestamp Target Time Reached for Target Time PPS3 status detected
39605  *  0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected
39606  */
39607 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK)
39608 
39609 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U)
39610 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U)
39611 /*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed
39612  *    in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses.
39613  *  0b1..Timestamp Target Time Error status detected
39614  *  0b0..Timestamp Target Time Error status not detected
39615  */
39616 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK)
39617 
39618 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U)
39619 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
39620 /*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop
39621  *    transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in
39622  *    the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers.
39623  *  0b1..Tx Timestamp Status Interrupt status detected
39624  *  0b0..Tx Timestamp Status Interrupt status not detected
39625  */
39626 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
39627 
39628 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U)
39629 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U)
39630 /*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
39631  *    trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable.
39632  */
39633 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK)
39634 
39635 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U)
39636 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
39637 /*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary
39638  *    timestamp snapshot FIFO is full and external trigger was set.
39639  *  0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected
39640  *  0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected
39641  */
39642 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK)
39643 
39644 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U)
39645 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
39646 /*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. */
39647 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK)
39648 /*! @} */
39649 
39650 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
39651 /*! @{ */
39652 
39653 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
39654 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
39655 /*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field
39656  *    of the Transmit packet's captured timestamp.
39657  */
39658 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
39659 
39660 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
39661 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
39662 /*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the
39663  *    following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL
39664  *    register is reset - The timestamp of the previous packet is overwritten with timestamp of the
39665  *    current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set.
39666  *  0b1..Transmit Timestamp Status Missed status detected
39667  *  0b0..Transmit Timestamp Status Missed status not detected
39668  */
39669 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
39670 /*! @} */
39671 
39672 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
39673 /*! @{ */
39674 
39675 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
39676 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
39677 /*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds
39678  *    field of Transmit packet's captured timestamp.
39679  */
39680 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
39681 /*! @} */
39682 
39683 /*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */
39684 /*! @{ */
39685 
39686 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U)
39687 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
39688 /*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO.
39689  *  0b0..Auxiliary Snapshot FIFO Clear is disabled
39690  *  0b1..Auxiliary Snapshot FIFO Clear is enabled
39691  */
39692 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK)
39693 
39694 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U)
39695 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U)
39696 /*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0.
39697  *  0b0..Auxiliary Snapshot $i is disabled
39698  *  0b1..Auxiliary Snapshot $i is enabled
39699  */
39700 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK)
39701 
39702 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U)
39703 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U)
39704 /*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1.
39705  *  0b0..Auxiliary Snapshot $i is disabled
39706  *  0b1..Auxiliary Snapshot $i is enabled
39707  */
39708 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK)
39709 
39710 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U)
39711 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U)
39712 /*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2.
39713  *  0b0..Auxiliary Snapshot $i is disabled
39714  *  0b1..Auxiliary Snapshot $i is enabled
39715  */
39716 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK)
39717 
39718 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U)
39719 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U)
39720 /*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3.
39721  *  0b0..Auxiliary Snapshot $i is disabled
39722  *  0b1..Auxiliary Snapshot $i is enabled
39723  */
39724 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK)
39725 /*! @} */
39726 
39727 /*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */
39728 /*! @{ */
39729 
39730 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU)
39731 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U)
39732 /*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. */
39733 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK)
39734 /*! @} */
39735 
39736 /*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */
39737 /*! @{ */
39738 
39739 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU)
39740 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U)
39741 /*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */
39742 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK)
39743 /*! @} */
39744 
39745 /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */
39746 /*! @{ */
39747 
39748 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU)
39749 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U)
39750 /*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path
39751  *    asymmetry value to be added to correctionField of Pdelay_Resp PTP packet.
39752  */
39753 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
39754 /*! @} */
39755 
39756 /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */
39757 /*! @{ */
39758 
39759 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU)
39760 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U)
39761 /*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path
39762  *    asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet.
39763  */
39764 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
39765 /*! @} */
39766 
39767 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
39768 /*! @{ */
39769 
39770 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
39771 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
39772 /*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as
39773  *    defined by the Ingress Correction expression.
39774  */
39775 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
39776 /*! @} */
39777 
39778 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
39779 /*! @{ */
39780 
39781 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
39782 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
39783 /*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path
39784  *    correction value as defined by the Egress Correction expression.
39785  */
39786 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
39787 /*! @} */
39788 
39789 /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */
39790 /*! @{ */
39791 
39792 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U)
39793 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U)
39794 /*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds
39795  *    part of the ingress path correction value as defined by the "Ingress Correction" expression.
39796  */
39797 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
39798 /*! @} */
39799 
39800 /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */
39801 /*! @{ */
39802 
39803 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U)
39804 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U)
39805 /*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds
39806  *    part of the egress path correction value as defined by the "Egress Correction" expression.
39807  */
39808 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
39809 /*! @} */
39810 
39811 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
39812 /*! @{ */
39813 
39814 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
39815 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
39816 /*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in
39817  *    nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the
39818  *    ingress timestamp is taken.
39819  */
39820 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
39821 
39822 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
39823 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
39824 /*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
39825  *    sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII)
39826  *    where the ingress timestamp is taken.
39827  */
39828 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
39829 /*! @} */
39830 
39831 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
39832 /*! @{ */
39833 
39834 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
39835 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
39836 /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
39837  *    sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and
39838  *    the output ports (phy_txd_o) of the MAC.
39839  */
39840 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
39841 
39842 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
39843 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
39844 /*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in
39845  *    nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output
39846  *    ports (phy_txd_o) of the MAC.
39847  */
39848 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
39849 /*! @} */
39850 
39851 /*! @name MAC_PPS_CONTROL - PPS Control */
39852 /*! @{ */
39853 
39854 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
39855 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
39856 /*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. */
39857 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
39858 
39859 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK     (0x10U)
39860 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT    (4U)
39861 /*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD.
39862  *  0b0..Flexible PPS Output Mode is disabled
39863  *  0b1..Flexible PPS Output Mode is enabled
39864  */
39865 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK)
39866 
39867 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U)
39868 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U)
39869 /*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time
39870  *    registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0
39871  *    output signal:
39872  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
39873  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
39874  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
39875  *        ptp_pps_o output port
39876  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
39877  *  0b01..Reserved
39878  */
39879 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
39880 
39881 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK    (0x80U)
39882 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT   (7U)
39883 /*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode.
39884  *  0b1..0th PPS instance is enabled to operate in MCGR mode
39885  *  0b0..0th PPS instance is enabled to operate in PPS mode
39886  */
39887 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK)
39888 
39889 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK    (0xF00U)
39890 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT   (8U)
39891 /*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. */
39892 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK)
39893 
39894 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U)
39895 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U)
39896 /*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time
39897  *    registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1
39898  *    output signal.
39899  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
39900  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
39901  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
39902  *        ptp_pps_o output port
39903  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
39904  *  0b01..Reserved
39905  */
39906 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
39907 
39908 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK    (0x8000U)
39909 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT   (15U)
39910 /*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode.
39911  *  0b0..1st PPS instance is disabled to operate in PPS or MCGR mode
39912  *  0b1..1st PPS instance is enabled to operate in PPS or MCGR mode
39913  */
39914 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK)
39915 
39916 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK    (0xF0000U)
39917 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT   (16U)
39918 /*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. */
39919 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK)
39920 
39921 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U)
39922 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U)
39923 /*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time
39924  *    registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2
39925  *    output signal.
39926  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
39927  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
39928  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
39929  *        ptp_pps_o output port
39930  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
39931  *  0b01..Reserved
39932  */
39933 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
39934 
39935 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK    (0x800000U)
39936 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT   (23U)
39937 /*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode.
39938  *  0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode
39939  *  0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode
39940  */
39941 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK)
39942 
39943 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK    (0xF000000U)
39944 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT   (24U)
39945 /*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. */
39946 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK)
39947 
39948 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U)
39949 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U)
39950 /*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time
39951  *    registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3
39952  *    output signal.
39953  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
39954  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
39955  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
39956  *        ptp_pps_o output port
39957  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
39958  *  0b01..Reserved
39959  */
39960 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
39961 
39962 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK    (0x80000000U)
39963 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT   (31U)
39964 /*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. */
39965 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK)
39966 /*! @} */
39967 
39968 /*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
39969 /*! @{ */
39970 
39971 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
39972 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
39973 /*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds. */
39974 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
39975 /*! @} */
39976 
39977 /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
39978 /*! @{ */
39979 
39980 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
39981 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
39982 /*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
39983 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
39984 
39985 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U)
39986 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U)
39987 /*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
39988  *    PPS_CONTROL register is programmed to 010 or 011.
39989  *  0b1..PPS Target Time Register Busy is detected
39990  *  0b0..PPS Target Time Register Busy status is not detected
39991  */
39992 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK)
39993 /*! @} */
39994 
39995 /*! @name MAC_PPS0_INTERVAL - PPS0 Interval */
39996 /*! @{ */
39997 
39998 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK  (0xFFFFFFFFU)
39999 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U)
40000 /*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
40001 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK)
40002 /*! @} */
40003 
40004 /*! @name MAC_PPS0_WIDTH - PPS0 Width */
40005 /*! @{ */
40006 
40007 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK   (0xFFFFFFFFU)
40008 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT  (0U)
40009 /*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and
40010  *    corresponding falling edge of PPS0 signal output.
40011  */
40012 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
40013 /*! @} */
40014 
40015 /*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */
40016 /*! @{ */
40017 
40018 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU)
40019 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U)
40020 /*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds. */
40021 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
40022 /*! @} */
40023 
40024 /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */
40025 /*! @{ */
40026 
40027 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU)
40028 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U)
40029 /*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
40030 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
40031 
40032 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U)
40033 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U)
40034 /*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
40035  *    PPS_CONTROL register is programmed to 010 or 011.
40036  *  0b1..PPS Target Time Register Busy is detected
40037  *  0b0..PPS Target Time Register Busy status is not detected
40038  */
40039 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK)
40040 /*! @} */
40041 
40042 /*! @name MAC_PPS1_INTERVAL - PPS1 Interval */
40043 /*! @{ */
40044 
40045 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK  (0xFFFFFFFFU)
40046 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U)
40047 /*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
40048 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK)
40049 /*! @} */
40050 
40051 /*! @name MAC_PPS1_WIDTH - PPS1 Width */
40052 /*! @{ */
40053 
40054 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK   (0xFFFFFFFFU)
40055 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT  (0U)
40056 /*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and
40057  *    corresponding falling edge of PPS0 signal output.
40058  */
40059 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
40060 /*! @} */
40061 
40062 /*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */
40063 /*! @{ */
40064 
40065 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU)
40066 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U)
40067 /*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds. */
40068 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
40069 /*! @} */
40070 
40071 /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */
40072 /*! @{ */
40073 
40074 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU)
40075 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U)
40076 /*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
40077 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
40078 
40079 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U)
40080 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U)
40081 /*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
40082  *    PPS_CONTROL register is programmed to 010 or 011.
40083  *  0b1..PPS Target Time Register Busy is detected
40084  *  0b0..PPS Target Time Register Busy status is not detected
40085  */
40086 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK)
40087 /*! @} */
40088 
40089 /*! @name MAC_PPS2_INTERVAL - PPS2 Interval */
40090 /*! @{ */
40091 
40092 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK  (0xFFFFFFFFU)
40093 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U)
40094 /*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
40095 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK)
40096 /*! @} */
40097 
40098 /*! @name MAC_PPS2_WIDTH - PPS2 Width */
40099 /*! @{ */
40100 
40101 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK   (0xFFFFFFFFU)
40102 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT  (0U)
40103 /*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and
40104  *    corresponding falling edge of PPS0 signal output.
40105  */
40106 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
40107 /*! @} */
40108 
40109 /*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */
40110 /*! @{ */
40111 
40112 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU)
40113 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U)
40114 /*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds. */
40115 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
40116 /*! @} */
40117 
40118 /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */
40119 /*! @{ */
40120 
40121 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU)
40122 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U)
40123 /*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
40124 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
40125 
40126 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U)
40127 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U)
40128 /*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
40129  *    PPS_CONTROL register is programmed to 010 or 011.
40130  *  0b1..PPS Target Time Register Busy is detected
40131  *  0b0..PPS Target Time Register Busy status is not detected
40132  */
40133 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK)
40134 /*! @} */
40135 
40136 /*! @name MAC_PPS3_INTERVAL - PPS3 Interval */
40137 /*! @{ */
40138 
40139 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK  (0xFFFFFFFFU)
40140 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U)
40141 /*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
40142 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK)
40143 /*! @} */
40144 
40145 /*! @name MAC_PPS3_WIDTH - PPS3 Width */
40146 /*! @{ */
40147 
40148 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK   (0xFFFFFFFFU)
40149 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT  (0U)
40150 /*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and
40151  *    corresponding falling edge of PPS0 signal output.
40152  */
40153 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
40154 /*! @} */
40155 
40156 /*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */
40157 /*! @{ */
40158 
40159 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK      (0x1U)
40160 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT     (0U)
40161 /*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled.
40162  *  0b0..PTP Offload feature is disabled
40163  *  0b1..PTP Offload feature is enabled
40164  */
40165 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK)
40166 
40167 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK    (0x2U)
40168 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT   (1U)
40169 /*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated
40170  *    periodically based on interval programmed or trigger from application, when the MAC is
40171  *    programmed to be in Clock Master mode.
40172  *  0b0..Automatic PTP SYNC message is disabled
40173  *  0b1..Automatic PTP SYNC message is enabled
40174  */
40175 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK)
40176 
40177 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK   (0x4U)
40178 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT  (2U)
40179 /*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message
40180  *    is generated periodically based on interval programmed or trigger from application, when the
40181  *    MAC is programmed to be in Peer-to-Peer Transparent mode.
40182  *  0b0..Automatic PTP Pdelay_Req message is disabled
40183  *  0b1..Automatic PTP Pdelay_Req message is enabled
40184  */
40185 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK)
40186 
40187 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK  (0x10U)
40188 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U)
40189 /*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted.
40190  *  0b0..Automatic PTP SYNC message Trigger is disabled
40191  *  0b1..Automatic PTP SYNC message Trigger is enabled
40192  */
40193 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK)
40194 
40195 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U)
40196 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U)
40197 /*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted.
40198  *  0b0..Automatic PTP Pdelay_Req message Trigger is disabled
40199  *  0b1..Automatic PTP Pdelay_Req message Trigger is enabled
40200  */
40201 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK)
40202 
40203 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK     (0x40U)
40204 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT    (6U)
40205 /*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay
40206  *    Request and Delay response is not generated for received SYNC and Delay request packet
40207  *    respectively, as required by the programmed mode.
40208  *  0b1..PTO Delay Request/Response response generation is disabled
40209  *  0b0..PTO Delay Request/Response response generation is enabled
40210  */
40211 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK)
40212 
40213 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK     (0x80U)
40214 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT    (7U)
40215 /*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay
40216  *    Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req)
40217  *    request packet, as required by the programmed mode.
40218  *  0b1..Peer Delay Response response generation is disabled
40219  *  0b0..Peer Delay Response response generation is enabled
40220  */
40221 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK)
40222 
40223 #define ENET_QOS_MAC_PTO_CONTROL_DN_MASK         (0xFF00U)
40224 #define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT        (8U)
40225 /*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating. */
40226 #define ENET_QOS_MAC_PTO_CONTROL_DN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK)
40227 /*! @} */
40228 
40229 /*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */
40230 /*! @{ */
40231 
40232 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU)
40233 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U)
40234 /*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. */
40235 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK)
40236 /*! @} */
40237 
40238 /*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */
40239 /*! @{ */
40240 
40241 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU)
40242 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U)
40243 /*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. */
40244 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK)
40245 /*! @} */
40246 
40247 /*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */
40248 /*! @{ */
40249 
40250 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU)
40251 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U)
40252 /*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. */
40253 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK)
40254 /*! @} */
40255 
40256 /*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */
40257 /*! @{ */
40258 
40259 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU)
40260 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U)
40261 /*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC
40262  *    message when the PTP node is Master.
40263  */
40264 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK)
40265 
40266 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U)
40267 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U)
40268 /*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
40269  *  0b110..Reserved
40270  *  0b000..DelayReq generated for every received SYNC
40271  *  0b100..for every 16 SYNC messages
40272  *  0b001..DelayReq generated every alternate reception of SYNC
40273  *  0b101..for every 32 SYNC messages
40274  *  0b010..for every 4 SYNC messages
40275  *  0b011..for every 8 SYNC messages
40276  */
40277 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK)
40278 
40279 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U)
40280 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U)
40281 /*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. */
40282 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK)
40283 /*! @} */
40284 
40285 /*! @name MTL_OPERATION_MODE - MTL Operation Mode */
40286 /*! @{ */
40287 
40288 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK  (0x2U)
40289 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U)
40290 /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
40291  *  0b0..Drop Transmit Status is disabled
40292  *  0b1..Drop Transmit Status is enabled
40293  */
40294 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK)
40295 
40296 #define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK     (0x4U)
40297 #define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT    (2U)
40298 /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
40299  *  0b0..Strict priority (SP)
40300  *  0b1..Weighted Strict Priority (WSP)
40301  */
40302 #define ENET_QOS_MTL_OPERATION_MODE_RAA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK)
40303 
40304 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK  (0x60U)
40305 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U)
40306 /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:
40307  *  0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
40308  *  0b11..Strict priority algorithm
40309  *  0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
40310  *  0b00..WRR algorithm
40311  */
40312 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK)
40313 
40314 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U)
40315 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U)
40316 /*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
40317  *  0b0..Counters Preset is disabled
40318  *  0b1..Counters Preset is enabled
40319  */
40320 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK)
40321 
40322 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK  (0x200U)
40323 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U)
40324 /*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
40325  *  0b0..Counters are not reset
40326  *  0b1..All counters are reset
40327  */
40328 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK)
40329 
40330 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK    (0x8000U)
40331 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT   (15U)
40332 /*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled.
40333  *  0b0..Flexible Rx parser is disabled
40334  *  0b1..Flexible Rx parser is enabled
40335  */
40336 #define ENET_QOS_MTL_OPERATION_MODE_FRPE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK)
40337 /*! @} */
40338 
40339 /*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */
40340 /*! @{ */
40341 
40342 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK         (0x1U)
40343 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT        (0U)
40344 /*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled.
40345  *  0b0..FIFO Debug Access is disabled
40346  *  0b1..FIFO Debug Access is enabled
40347  */
40348 #define ENET_QOS_MTL_DBG_CTL_FDBGEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK)
40349 
40350 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK         (0x2U)
40351 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT        (1U)
40352 /*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to
40353  *    the FIFO is read, write, and debug access.
40354  *  0b0..Debug Mode Access to FIFO is disabled
40355  *  0b1..Debug Mode Access to FIFO is enabled
40356  */
40357 #define ENET_QOS_MTL_DBG_CTL_DBGMOD(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK)
40358 
40359 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK         (0xCU)
40360 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT        (2U)
40361 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation.
40362  *  0b11..All four bytes are valid
40363  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
40364  *  0b01..Byte 0 and Byte 1 are valid
40365  *  0b00..Byte 0 valid
40366  */
40367 #define ENET_QOS_MTL_DBG_CTL_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK)
40368 
40369 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK       (0x60U)
40370 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT      (5U)
40371 /*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO.
40372  *  0b01..Control Word/Normal Status
40373  *  0b11..EOP Data/EOP
40374  *  0b00..Packet Data
40375  *  0b10..SOP Data/Last Status
40376  */
40377 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK)
40378 
40379 #define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK         (0x100U)
40380 #define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT        (8U)
40381 /*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
40382  *  0b0..Reset All Pointers is disabled
40383  *  0b1..Reset All Pointers is enabled
40384  */
40385 #define ENET_QOS_MTL_DBG_CTL_RSTALL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK)
40386 
40387 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK         (0x200U)
40388 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT        (9U)
40389 /*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the
40390  *    currently-selected FIFO are reset when FIFO Debug Access is enabled.
40391  *  0b0..Reset Pointers of Selected FIFO is disabled
40392  *  0b1..Reset Pointers of Selected FIFO is enabled
40393  */
40394 #define ENET_QOS_MTL_DBG_CTL_RSTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK)
40395 
40396 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK       (0x400U)
40397 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT      (10U)
40398 /*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
40399  *  0b0..FIFO Read is disabled
40400  *  0b1..FIFO Read is enabled
40401  */
40402 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK)
40403 
40404 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK       (0x800U)
40405 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT      (11U)
40406 /*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected
40407  *    FIFO when FIFO Debug Access is enabled.
40408  *  0b0..FIFO Write is disabled
40409  *  0b1..FIFO Write is enabled
40410  */
40411 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK)
40412 
40413 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK        (0x3000U)
40414 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT       (12U)
40415 /*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access:
40416  *  0b11..Rx FIFO
40417  *  0b10..TSO FIFO (cannot be accessed when SLVMOD is set)
40418  *  0b00..Tx FIFO
40419  *  0b01..Tx Status FIFO (only read access when SLVMOD is set)
40420  */
40421 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK)
40422 
40423 #define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK          (0x4000U)
40424 #define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT         (14U)
40425 /*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is
40426  *    generated when EOP of received packet is written to the Rx FIFO.
40427  *  0b0..Receive Packet Available Interrupt Status is disabled
40428  *  0b1..Receive Packet Available Interrupt Status is enabled
40429  */
40430 #define ENET_QOS_MTL_DBG_CTL_PKTIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK)
40431 
40432 #define ENET_QOS_MTL_DBG_CTL_STSIE_MASK          (0x8000U)
40433 #define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT         (15U)
40434 /*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is
40435  *    generated when Transmit status is available in slave mode.
40436  *  0b0..Transmit Packet Available Interrupt Status is disabled
40437  *  0b1..Transmit Packet Available Interrupt Status is enabled
40438  */
40439 #define ENET_QOS_MTL_DBG_CTL_STSIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK)
40440 /*! @} */
40441 
40442 /*! @name MTL_DBG_STS - FIFO Debug Status */
40443 /*! @{ */
40444 
40445 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK       (0x1U)
40446 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT      (0U)
40447 /*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the
40448  *    MAC and content of the following fields is not valid: - All other fields of this register - All
40449  *    fields of the MTL_FIFO_DEBUG_DATA register
40450  *  0b1..FIFO Busy detected
40451  *  0b0..FIFO Busy not detected
40452  */
40453 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK)
40454 
40455 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK       (0x6U)
40456 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT      (1U)
40457 /*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO.
40458  *  0b01..Control Word/Normal Status
40459  *  0b11..EOP Data/EOP
40460  *  0b00..Packet Data
40461  *  0b10..SOP Data/Last Status
40462  */
40463 #define ENET_QOS_MTL_DBG_STS_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK)
40464 
40465 #define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK         (0x18U)
40466 #define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT        (3U)
40467 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation.
40468  *  0b11..All four bytes are valid
40469  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
40470  *  0b01..Byte 0 and Byte 1 are valid
40471  *  0b00..Byte 0 valid
40472  */
40473 #define ENET_QOS_MTL_DBG_STS_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK)
40474 
40475 #define ENET_QOS_MTL_DBG_STS_PKTI_MASK           (0x100U)
40476 #define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT          (8U)
40477 /*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has
40478  *    written the EOP of received packet to the Rx FIFO.
40479  *  0b1..Receive Packet Available Interrupt Status detected
40480  *  0b0..Receive Packet Available Interrupt Status not detected
40481  */
40482 #define ENET_QOS_MTL_DBG_STS_PKTI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK)
40483 
40484 #define ENET_QOS_MTL_DBG_STS_STSI_MASK           (0x200U)
40485 #define ENET_QOS_MTL_DBG_STS_STSI_SHIFT          (9U)
40486 /*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave
40487  *    mode Tx packet is transmitted, and the status is available in Tx Status FIFO.
40488  *  0b1..Transmit Status Available Interrupt Status detected
40489  *  0b0..Transmit Status Available Interrupt Status not detected
40490  */
40491 #define ENET_QOS_MTL_DBG_STS_STSI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK)
40492 
40493 #define ENET_QOS_MTL_DBG_STS_LOCR_MASK           (0xFFFF8000U)
40494 #define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT          (15U)
40495 /*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. */
40496 #define ENET_QOS_MTL_DBG_STS_LOCR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK)
40497 /*! @} */
40498 
40499 /*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */
40500 /*! @{ */
40501 
40502 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU)
40503 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
40504 /*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the
40505  *    data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO.
40506  */
40507 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
40508 /*! @} */
40509 
40510 /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
40511 /*! @{ */
40512 
40513 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK  (0x1U)
40514 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
40515 /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
40516  *  0b1..Queue 0 Interrupt status detected
40517  *  0b0..Queue 0 Interrupt status not detected
40518  */
40519 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK)
40520 
40521 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK  (0x2U)
40522 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U)
40523 /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
40524  *  0b1..Queue 1 Interrupt status detected
40525  *  0b0..Queue 1 Interrupt status not detected
40526  */
40527 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK)
40528 
40529 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK  (0x4U)
40530 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U)
40531 /*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2.
40532  *  0b1..Queue 2 Interrupt status detected
40533  *  0b0..Queue 2 Interrupt status not detected
40534  */
40535 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK)
40536 
40537 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK  (0x8U)
40538 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U)
40539 /*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3.
40540  *  0b1..Queue 3 Interrupt status detected
40541  *  0b0..Queue 3 Interrupt status not detected
40542  */
40543 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK)
40544 
40545 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK  (0x10U)
40546 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U)
40547 /*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4.
40548  *  0b1..Queue 4 Interrupt status detected
40549  *  0b0..Queue 4 Interrupt status not detected
40550  */
40551 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK)
40552 
40553 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U)
40554 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
40555 /*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access.
40556  *  0b1..Debug Interrupt status detected
40557  *  0b0..Debug Interrupt status not detected
40558  */
40559 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK)
40560 
40561 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U)
40562 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U)
40563 /*! ESTIS - EST (TAS- 802.
40564  *  0b1..EST (TAS- 802.1Qbv) Interrupt status detected
40565  *  0b0..EST (TAS- 802.1Qbv) Interrupt status not detected
40566  */
40567 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK)
40568 
40569 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U)
40570 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U)
40571 /*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block.
40572  *  0b1..MTL Rx Parser Interrupt status detected
40573  *  0b0..MTL Rx Parser Interrupt status not detected
40574  */
40575 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK)
40576 /*! @} */
40577 
40578 /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
40579 /*! @{ */
40580 
40581 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK  (0x7U)
40582 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U)
40583 /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
40584  *    in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
40585  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
40586  *    field is valid when the Q0DDMACH field is reset.
40587  */
40588 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
40589 
40590 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK  (0x10U)
40591 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U)
40592 /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
40593  *    the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
40594  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
40595  *    Ethernet DA address.
40596  *  0b0..Queue 0 disabled for DA-based DMA Channel Selection
40597  *  0b1..Queue 0 enabled for DA-based DMA Channel Selection
40598  */
40599 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
40600 
40601 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK  (0x700U)
40602 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U)
40603 /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
40604  *    in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
40605  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
40606  *    field is valid when the Q1DDMACH field is reset.
40607  */
40608 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
40609 
40610 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK  (0x1000U)
40611 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U)
40612 /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
40613  *    the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
40614  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
40615  *    Ethernet DA address.
40616  *  0b0..Queue 1 disabled for DA-based DMA Channel Selection
40617  *  0b1..Queue 1 enabled for DA-based DMA Channel Selection
40618  */
40619 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
40620 
40621 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK  (0x70000U)
40622 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U)
40623 /*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet
40624  *    in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
40625  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
40626  *    field is valid when the Q2DDMACH field is reset.
40627  */
40628 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK)
40629 
40630 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK  (0x100000U)
40631 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U)
40632 /*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
40633  *    the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC
40634  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
40635  *    Ethernet DA address.
40636  *  0b0..Queue 2 disabled for DA-based DMA Channel Selection
40637  *  0b1..Queue 2 enabled for DA-based DMA Channel Selection
40638  */
40639 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK)
40640 
40641 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK  (0x7000000U)
40642 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U)
40643 /*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet
40644  *    in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
40645  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
40646  *    field is valid when the Q3DDMACH field is reset.
40647  */
40648 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK)
40649 
40650 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK  (0x10000000U)
40651 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U)
40652 /*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit
40653  *    indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided
40654  *    in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers,
40655  *    or the Ethernet DA address.
40656  *  0b0..Queue 3 disabled for DA-based DMA Channel Selection
40657  *  0b1..Queue 3 enabled for DA-based DMA Channel Selection
40658  */
40659 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK)
40660 /*! @} */
40661 
40662 /*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */
40663 /*! @{ */
40664 
40665 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK  (0x7U)
40666 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U)
40667 /*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received
40668  *    in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
40669  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
40670  *    field is valid when the Q4DDMACH field is reset.
40671  */
40672 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK)
40673 
40674 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK  (0x10U)
40675 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U)
40676 /*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
40677  *    the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC
40678  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
40679  *    Ethernet DA address.
40680  *  0b0..Queue 4 disabled for DA-based DMA Channel Selection
40681  *  0b1..Queue 4 enabled for DA-based DMA Channel Selection
40682  */
40683 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK)
40684 /*! @} */
40685 
40686 /*! @name MTL_TBS_CTRL - Time Based Scheduling Control */
40687 /*! @{ */
40688 
40689 #define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK          (0x1U)
40690 #define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT         (0U)
40691 /*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling
40692  *    is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the
40693  *    current list.
40694  *  0b0..EST offset Mode is disabled
40695  *  0b1..EST offset Mode is enabled
40696  */
40697 #define ENET_QOS_MTL_TBS_CTRL_ESTM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK)
40698 
40699 #define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK          (0x2U)
40700 #define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT         (1U)
40701 /*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid.
40702  *  0b0..LEOS field is invalid
40703  *  0b1..LEOS field is valid
40704  */
40705 #define ENET_QOS_MTL_TBS_CTRL_LEOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK)
40706 
40707 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK         (0x70U)
40708 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT        (4U)
40709 /*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. */
40710 #define ENET_QOS_MTL_TBS_CTRL_LEGOS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK)
40711 
40712 #define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK          (0xFFFFFF00U)
40713 #define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT         (8U)
40714 /*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the
40715  *    Launch time to compute the Launch Expiry time.
40716  */
40717 #define ENET_QOS_MTL_TBS_CTRL_LEOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK)
40718 /*! @} */
40719 
40720 /*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */
40721 /*! @{ */
40722 
40723 #define ENET_QOS_MTL_EST_CONTROL_EEST_MASK       (0x1U)
40724 #define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT      (0U)
40725 /*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state.
40726  *  0b0..EST is disabled
40727  *  0b1..EST is enabled
40728  */
40729 #define ENET_QOS_MTL_EST_CONTROL_EEST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK)
40730 
40731 #define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK       (0x2U)
40732 #define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT      (1U)
40733 /*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list
40734  *    that it currently owns (SWOL) and the hardware should switch to the new list based on the new
40735  *    BTR.
40736  *  0b0..Switch to S/W owned list is disabled
40737  *  0b1..Switch to S/W owned list is enabled
40738  */
40739 #define ENET_QOS_MTL_EST_CONTROL_SSWL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK)
40740 
40741 #define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK       (0x10U)
40742 #define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT      (4U)
40743 /*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during
40744  *    Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register).
40745  *  0b1..Do not Drop frames during Frame Size Error
40746  *  0b0..Drop frames during Frame Size Error
40747  */
40748 #define ENET_QOS_MTL_EST_CONTROL_DDBF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK)
40749 
40750 #define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK       (0x20U)
40751 #define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT      (5U)
40752 /*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due
40753  *    to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE
40754  *    field of this register) GCL iterations are dropped.
40755  *  0b0..Do not Drop Frames causing Scheduling Error
40756  *  0b1..Drop Frames causing Scheduling Error
40757  */
40758 #define ENET_QOS_MTL_EST_CONTROL_DFBS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK)
40759 
40760 #define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK       (0xC0U)
40761 #define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT      (6U)
40762 /*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before
40763  *    reporting an HLBS error defined in EST_STATUS register.
40764  *  0b10..16 iterations
40765  *  0b11..32 iterations
40766  *  0b00..4 iterations
40767  *  0b01..8 iterations
40768  */
40769 #define ENET_QOS_MTL_EST_CONTROL_LCSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK)
40770 
40771 #define ENET_QOS_MTL_EST_CONTROL_TILS_MASK       (0x700U)
40772 #define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT      (8U)
40773 /*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the
40774  *    programmed Time Interval values used in the Gate Control Lists.
40775  */
40776 #define ENET_QOS_MTL_EST_CONTROL_TILS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK)
40777 
40778 #define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK       (0xFFF000U)
40779 #define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT      (12U)
40780 /*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is
40781  *    added to the current time to compensate for all the implementation pipeline delays such as the CDC
40782  *    sync delay, buffering delays, data path delays etc.
40783  */
40784 #define ENET_QOS_MTL_EST_CONTROL_CTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK)
40785 
40786 #define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK       (0xFF000000U)
40787 #define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT      (24U)
40788 /*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. */
40789 #define ENET_QOS_MTL_EST_CONTROL_PTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK)
40790 /*! @} */
40791 
40792 /*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */
40793 /*! @{ */
40794 
40795 #define ENET_QOS_MTL_EST_STATUS_SWLC_MASK        (0x1U)
40796 #define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT       (0U)
40797 /*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully
40798  *    switched to the SWOL, and the SWOL bit has been updated to that effect.
40799  *  0b1..Switch to S/W owned list Complete detected
40800  *  0b0..Switch to S/W owned list Complete not detected
40801  */
40802 #define ENET_QOS_MTL_EST_STATUS_SWLC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK)
40803 
40804 #define ENET_QOS_MTL_EST_STATUS_BTRE_MASK        (0x2U)
40805 #define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT       (1U)
40806 /*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed
40807  *    value is less than current time.
40808  *  0b1..BTR Error detected
40809  *  0b0..BTR Error not detected
40810  */
40811 #define ENET_QOS_MTL_EST_STATUS_BTRE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK)
40812 
40813 #define ENET_QOS_MTL_EST_STATUS_HLBF_MASK        (0x4U)
40814 #define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT       (2U)
40815 /*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more
40816  *    Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or
40817  *    equal to the duration needed for frame size (or frame fragment size when preemption is
40818  *    enabled) transmission.
40819  *  0b1..Head-Of-Line Blocking due to Frame Size detected
40820  *  0b0..Head-Of-Line Blocking due to Frame Size not detected
40821  */
40822 #define ENET_QOS_MTL_EST_STATUS_HLBF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK)
40823 
40824 #define ENET_QOS_MTL_EST_STATUS_HLBS_MASK        (0x8U)
40825 #define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT       (3U)
40826 /*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration
40827  *    and get scheduled even after 4 iterations of the GCL.
40828  *  0b1..Head-Of-Line Blocking due to Scheduling detected
40829  *  0b0..Head-Of-Line Blocking due to Scheduling not detected
40830  */
40831 #define ENET_QOS_MTL_EST_STATUS_HLBS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK)
40832 
40833 #define ENET_QOS_MTL_EST_STATUS_CGCE_MASK        (0x10U)
40834 #define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT       (4U)
40835 /*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the
40836  *    programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the
40837  *    Cycle Time (CTR).
40838  *  0b1..Constant Gate Control Error detected
40839  *  0b0..Constant Gate Control Error not detected
40840  */
40841 #define ENET_QOS_MTL_EST_STATUS_CGCE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK)
40842 
40843 #define ENET_QOS_MTL_EST_STATUS_SWOL_MASK        (0x80U)
40844 #define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT       (7U)
40845 /*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and
40846  *    when "1" indicates the Gate Control list "1" is owned by the software.
40847  *  0b1..Gate control list number "1" is owned by software
40848  *  0b0..Gate control list number "0" is owned by software
40849  */
40850 #define ENET_QOS_MTL_EST_STATUS_SWOL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK)
40851 
40852 #define ENET_QOS_MTL_EST_STATUS_BTRL_MASK        (0xF00U)
40853 #define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT       (8U)
40854 /*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time
40855  *    =< New BTR + (N * New Cycle Time) becomes true.
40856  */
40857 #define ENET_QOS_MTL_EST_STATUS_BTRL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK)
40858 
40859 #define ENET_QOS_MTL_EST_STATUS_CGSN_MASK        (0xF0000U)
40860 #define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT       (16U)
40861 /*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list. */
40862 #define ENET_QOS_MTL_EST_STATUS_CGSN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK)
40863 /*! @} */
40864 
40865 /*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */
40866 /*! @{ */
40867 
40868 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK     (0x1FU)
40869 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT    (0U)
40870 /*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced
40871  *    error/timeout described in HLBS field of status register.
40872  */
40873 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK)
40874 /*! @} */
40875 
40876 /*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */
40877 /*! @{ */
40878 
40879 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU)
40880 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U)
40881 /*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced
40882  *    error described in HLBF field of status register.
40883  */
40884 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
40885 /*! @} */
40886 
40887 /*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */
40888 /*! @{ */
40889 
40890 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU)
40891 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U)
40892 /*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number
40893  *    indicated in HBFQ field of this register.
40894  */
40895 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
40896 
40897 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U)
40898 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U)
40899 /*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number)
40900  *    experiencing HLBF error (see HLBF field of status register).
40901  */
40902 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK)
40903 /*! @} */
40904 
40905 /*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */
40906 /*! @{ */
40907 
40908 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK   (0x1U)
40909 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT  (0U)
40910 /*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration
40911  *    change is successful and the hardware has switched to the new list.
40912  *  0b0..Interrupt for Switch List is disabled
40913  *  0b1..Interrupt for Switch List is enabled
40914  */
40915 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK)
40916 
40917 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK   (0x2U)
40918 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT  (1U)
40919 /*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status.
40920  *  0b0..Interrupt for BTR Error is disabled
40921  *  0b1..Interrupt for BTR Error is enabled
40922  */
40923 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK)
40924 
40925 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK   (0x4U)
40926 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT  (2U)
40927 /*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking
40928  *    due to Frame Size error occurs and is indicated in the status.
40929  *  0b0..Interrupt for HLBF is disabled
40930  *  0b1..Interrupt for HLBF is enabled
40931  */
40932 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK)
40933 
40934 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK   (0x8U)
40935 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT  (3U)
40936 /*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking
40937  *    due to Scheduling issue and is indicated in the status.
40938  *  0b0..Interrupt for HLBS is disabled
40939  *  0b1..Interrupt for HLBS is enabled
40940  */
40941 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK)
40942 
40943 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK   (0x10U)
40944 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT  (4U)
40945 /*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control
40946  *    Error occurs and is indicated in the status.
40947  *  0b0..Interrupt for CGCE is disabled
40948  *  0b1..Interrupt for CGCE is enabled
40949  */
40950 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK)
40951 /*! @} */
40952 
40953 /*! @name MTL_EST_GCL_CONTROL - EST GCL Control */
40954 /*! @{ */
40955 
40956 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK   (0x1U)
40957 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT  (0U)
40958 /*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress.
40959  *  0b0..Start Read/Write Op disabled
40960  *  0b1..Start Read/Write Op enabled
40961  */
40962 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK)
40963 
40964 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK   (0x2U)
40965 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT  (1U)
40966 /*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation.
40967  *  0b1..Read Operation
40968  *  0b0..Write Operation
40969  */
40970 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK)
40971 
40972 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK   (0x4U)
40973 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT  (2U)
40974 /*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL
40975  *    related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA.
40976  *  0b0..Gate Control Related Registers are disabled
40977  *  0b1..Gate Control Related Registers are enabled
40978  */
40979 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK)
40980 
40981 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK   (0x10U)
40982 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT  (4U)
40983 /*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and
40984  *    Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is
40985  *    used to determine which bank to use.
40986  *  0b0..Debug Mode is disabled
40987  *  0b1..Debug Mode is enabled
40988  */
40989 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK)
40990 
40991 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK   (0x20U)
40992 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT  (5U)
40993 /*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to
40994  *    Bank 0 (GCL0 and corresponding Time related registers).
40995  *  0b0..R/W in debug mode should be directed to Bank 0
40996  *  0b1..R/W in debug mode should be directed to Bank 1
40997  */
40998 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK)
40999 
41000 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK   (0x1FF00U)
41001 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT  (8U)
41002 /*! ADDR - Gate Control List Address: (GCLA when GCRR is "0"). */
41003 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK)
41004 
41005 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK   (0x100000U)
41006 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT  (20U)
41007 /*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL
41008  *    registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set.
41009  *  0b0..ERR0 is disabled
41010  *  0b1..ERR1 is enabled
41011  */
41012 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK)
41013 
41014 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U)
41015 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U)
41016 /*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register,
41017  *    enables the ECC error injection feature.
41018  *  0b0..EST ECC Inject Error is disabled
41019  *  0b1..EST ECC Inject Error is enabled
41020  */
41021 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK)
41022 
41023 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U)
41024 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U)
41025 /*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set,
41026  *    following are the errors inserted based on the value encoded in this field.
41027  *  0b00..Insert 1 bit error
41028  *  0b11..Insert 1 bit error in address field
41029  *  0b01..Insert 2 bit errors
41030  *  0b10..Insert 3 bit errors
41031  */
41032 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
41033 /*! @} */
41034 
41035 /*! @name MTL_EST_GCL_DATA - EST GCL Data */
41036 /*! @{ */
41037 
41038 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK       (0xFFFFFFFFU)
41039 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT      (0U)
41040 /*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register. */
41041 #define ENET_QOS_MTL_EST_GCL_DATA_GCD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK)
41042 /*! @} */
41043 
41044 /*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */
41045 /*! @{ */
41046 
41047 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK      (0x3U)
41048 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT     (0U)
41049 /*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of
41050  *    bytes over 64 bytes required in non-final fragments of preempted frames.
41051  */
41052 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK)
41053 
41054 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK       (0x1F00U)
41055 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT      (8U)
41056 /*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as
41057  *    preemptable, when '0' Queue is classified as express.
41058  */
41059 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK)
41060 
41061 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK       (0x10000000U)
41062 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT      (28U)
41063 /*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
41064  *  0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State
41065  *  0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
41066  */
41067 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK)
41068 /*! @} */
41069 
41070 /*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */
41071 /*! @{ */
41072 
41073 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK       (0xFFFFU)
41074 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT      (0U)
41075 /*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to
41076  *    the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of
41077  *    transmission or any preemptable frames that are queued for transmission.
41078  */
41079 #define ENET_QOS_MTL_FPE_ADVANCE_HADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK)
41080 
41081 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK       (0xFFFF0000U)
41082 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT      (16U)
41083 /*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE
41084  *    to the MAC and the MAC being ready to resume transmission of preemptable frames, in the
41085  *    absence of there being any express frames available for transmission.
41086  */
41087 #define ENET_QOS_MTL_FPE_ADVANCE_RADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK)
41088 /*! @} */
41089 
41090 /*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */
41091 /*! @{ */
41092 
41093 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU)
41094 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U)
41095 /*! NVE - Number of valid entries in the Instruction table This control indicates the number of
41096  *    valid entries in the Instruction Memory.
41097  */
41098 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK)
41099 
41100 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U)
41101 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U)
41102 /*! NPE - Number of parsable entries in the Instruction table This control indicates the number of
41103  *    parsable entries in the Instruction Memory.
41104  */
41105 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK)
41106 
41107 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U)
41108 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U)
41109 /*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State
41110  *    and waiting for a new packet for processing.
41111  *  0b1..RX Parser in Idle state
41112  *  0b0..RX Parser not in Idle state
41113  */
41114 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK)
41115 /*! @} */
41116 
41117 /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */
41118 /*! @{ */
41119 
41120 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U)
41121 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U)
41122 /*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction
41123  *    address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then
41124  *    this bit is set to 1.
41125  *  0b1..Number of Valid Entries Overflow Interrupt Status detected
41126  *  0b0..Number of Valid Entries Overflow Interrupt Status not detected
41127  */
41128 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK)
41129 
41130 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U)
41131 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U)
41132 /*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the
41133  *    number of parsed entries found to be more than NPE[] (Number of Parseable Entries in
41134  *    MTL_RXP_CONTROL register),then this bit is set to 1.
41135  *  0b1..Number of Parsable Entries Overflow Interrupt Status detected
41136  *  0b0..Number of Parsable Entries Overflow Interrupt Status not detected
41137  */
41138 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK)
41139 
41140 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U)
41141 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U)
41142 /*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's
41143  *    'Frame Offset' found to be more than EOF offset, then then this bit is set.
41144  *  0b1..Frame Offset Overflow Interrupt Status detected
41145  *  0b0..Frame Offset Overflow Interrupt Status not detected
41146  */
41147 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK)
41148 
41149 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U)
41150 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U)
41151 /*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the
41152  *    packet by setting RF=1 in the instruction memory, then this bit is set to 1.
41153  *  0b1..Packet Dropped due to RF Interrupt Status detected
41154  *  0b0..Packet Dropped due to RF Interrupt Status not detected
41155  */
41156 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK)
41157 
41158 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U)
41159 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U)
41160 /*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled.
41161  *  0b0..Number of Valid Entries Overflow Interrupt is disabled
41162  *  0b1..Number of Valid Entries Overflow Interrupt is enabled
41163  */
41164 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK)
41165 
41166 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U)
41167 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U)
41168 /*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled.
41169  *  0b0..Number of Parsable Entries Overflow Interrupt is disabled
41170  *  0b1..Number of Parsable Entries Overflow Interrupt is enabled
41171  */
41172 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK)
41173 
41174 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U)
41175 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U)
41176 /*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled.
41177  *  0b0..Frame Offset Overflow Interrupt is disabled
41178  *  0b1..Frame Offset Overflow Interrupt is enabled
41179  */
41180 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK)
41181 
41182 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U)
41183 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U)
41184 /*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled.
41185  *  0b0..Packet Drop due to RF Interrupt is disabled
41186  *  0b1..Packet Drop due to RF Interrupt is enabled
41187  */
41188 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK)
41189 /*! @} */
41190 
41191 /*! @name MTL_RXP_DROP_CNT - RXP Drop Count */
41192 /*! @{ */
41193 
41194 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK     (0x7FFFFFFFU)
41195 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT    (0U)
41196 /*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. */
41197 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK)
41198 
41199 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK  (0x80000000U)
41200 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U)
41201 /*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the
41202  *    MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit.
41203  *  0b1..Rx Parser Drop count overflow occurred
41204  *  0b0..Rx Parser Drop count overflow not occurred
41205  */
41206 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK)
41207 /*! @} */
41208 
41209 /*! @name MTL_RXP_ERROR_CNT - RXP Error Count */
41210 /*! @{ */
41211 
41212 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK    (0x7FFFFFFFU)
41213 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT   (0U)
41214 /*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters
41215  *    following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry
41216  *    address > EOF data entry address The counter is cleared when the register is read.
41217  */
41218 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK)
41219 
41220 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U)
41221 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U)
41222 /*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the
41223  *    MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit.
41224  *  0b1..Rx Parser Error count overflow occurred
41225  *  0b0..Rx Parser Error count overflow not occurred
41226  */
41227 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK)
41228 /*! @} */
41229 
41230 /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */
41231 /*! @{ */
41232 
41233 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU)
41234 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U)
41235 /*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. */
41236 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
41237 
41238 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U)
41239 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U)
41240 /*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory.
41241  *  0b0..Read operation to the Rx Parser Memory
41242  *  0b1..Write operation to the Rx Parser Memory
41243  */
41244 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK)
41245 
41246 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U)
41247 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U)
41248 /*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it
41249  *    indicates to start the Read/Write operation from/to the Rx Parser Memory.
41250  *  0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory)
41251  *  0b0..hardware not busy
41252  */
41253 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK)
41254 /*! @} */
41255 
41256 /*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */
41257 /*! @{ */
41258 
41259 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU)
41260 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U)
41261 /*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. */
41262 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
41263 /*! @} */
41264 
41265 /*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */
41266 /*! @{ */
41267 
41268 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK       (0x1U)
41269 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT      (0U)
41270 /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
41271  *  0b0..Flush Transmit Queue is disabled
41272  *  0b1..Flush Transmit Queue is enabled
41273  */
41274 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK)
41275 
41276 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK       (0x2U)
41277 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT      (1U)
41278 /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
41279  *  0b0..Transmit Store and Forward is disabled
41280  *  0b1..Transmit Store and Forward is enabled
41281  */
41282 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK)
41283 
41284 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK     (0xCU)
41285 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT    (2U)
41286 /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
41287  *  0b00..Not enabled
41288  *  0b10..Enabled
41289  *  0b01..Enable in AV mode (Reserved in non-AV)
41290  *  0b11..Reserved
41291  */
41292 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK)
41293 
41294 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK       (0x70U)
41295 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT      (4U)
41296 /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
41297  *  0b011..128
41298  *  0b100..192
41299  *  0b101..256
41300  *  0b000..32
41301  *  0b110..384
41302  *  0b111..512
41303  *  0b001..64
41304  *  0b010..96
41305  */
41306 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK)
41307 
41308 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK       (0x1F0000U)
41309 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT      (16U)
41310 /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. */
41311 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK)
41312 /*! @} */
41313 
41314 /* The count of ENET_QOS_MTL_TXQX_OP_MODE */
41315 #define ENET_QOS_MTL_TXQX_OP_MODE_COUNT          (5U)
41316 
41317 /*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */
41318 /*! @{ */
41319 
41320 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK  (0x7FFU)
41321 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
41322 /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
41323  *    controller because of Tx Queue Underflow.
41324  */
41325 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
41326 
41327 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK  (0x800U)
41328 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
41329 /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
41330  *    Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
41331  *  0b1..Overflow detected for Underflow Packet Counter
41332  *  0b0..Overflow not detected for Underflow Packet Counter
41333  */
41334 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
41335 /*! @} */
41336 
41337 /* The count of ENET_QOS_MTL_TXQX_UNDRFLW */
41338 #define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT          (5U)
41339 
41340 /*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */
41341 /*! @{ */
41342 
41343 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK     (0x1U)
41344 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT    (0U)
41345 /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
41346  *    indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
41347  *    of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
41348  *    when PFC is enabled - Reception of 802.
41349  *  0b1..Transmit Queue in Pause status is detected
41350  *  0b0..Transmit Queue in Pause status is not detected
41351  */
41352 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK)
41353 
41354 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK        (0x6U)
41355 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT       (1U)
41356 /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:
41357  *  0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
41358  *  0b00..Idle state
41359  *  0b01..Read state (transferring data to the MAC transmitter)
41360  *  0b10..Waiting for pending Tx Status from the MAC transmitter
41361  */
41362 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK)
41363 
41364 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK        (0x8U)
41365 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT       (3U)
41366 /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
41367  *    Queue Write Controller is active, and it is transferring the data to the Tx Queue.
41368  *  0b1..MTL Tx Queue Write Controller status is detected
41369  *  0b0..MTL Tx Queue Write Controller status is not detected
41370  */
41371 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK)
41372 
41373 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK        (0x10U)
41374 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT       (4U)
41375 /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
41376  *    is not empty and some data is left for transmission.
41377  *  0b1..MTL Tx Queue Not Empty status is detected
41378  *  0b0..MTL Tx Queue Not Empty status is not detected
41379  */
41380 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK)
41381 
41382 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK     (0x20U)
41383 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT    (5U)
41384 /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
41385  *  0b1..MTL Tx Status FIFO Full status is detected
41386  *  0b0..MTL Tx Status FIFO Full status is not detected
41387  */
41388 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK)
41389 
41390 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK          (0x70000U)
41391 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT         (16U)
41392 /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. */
41393 #define ENET_QOS_MTL_TXQX_DBG_PTXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK)
41394 
41395 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK       (0x700000U)
41396 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT      (20U)
41397 /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
41398  *    number of status in the Tx Status FIFO of this queue.
41399  */
41400 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK)
41401 /*! @} */
41402 
41403 /* The count of ENET_QOS_MTL_TXQX_DBG */
41404 #define ENET_QOS_MTL_TXQX_DBG_COUNT              (5U)
41405 
41406 /*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */
41407 /*! @{ */
41408 
41409 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK    (0x4U)
41410 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT   (2U)
41411 /*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling
41412  *    algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is
41413  *    selected for Queue 1 traffic.
41414  *  0b0..CBS Algorithm is disabled
41415  *  0b1..CBS Algorithm is enabled
41416  */
41417 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK)
41418 
41419 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK       (0x8U)
41420 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT      (3U)
41421 /*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based
41422  *    shaper algorithm logic is not reset to zero when there is positive credit and no packet to
41423  *    transmit in Channel 1.
41424  *  0b0..Credit Control is disabled
41425  *  0b1..Credit Control is enabled
41426  */
41427 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK)
41428 
41429 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK      (0x70U)
41430 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT     (4U)
41431 /*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the
41432  *    number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the
41433  *    average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be
41434  *    computed for Queue.
41435  *  0b100..16 slots
41436  *  0b000..1 slot
41437  *  0b001..2 slots
41438  *  0b010..4 slots
41439  *  0b011..8 slots
41440  *  0b101..Reserved
41441  */
41442 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK)
41443 /*! @} */
41444 
41445 /* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */
41446 #define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT         (5U)
41447 
41448 /*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */
41449 /*! @{ */
41450 
41451 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK      (0xFFFFFFU)
41452 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT     (0U)
41453 /*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot. */
41454 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK)
41455 /*! @} */
41456 
41457 /* The count of ENET_QOS_MTL_TXQX_ETS_STAT */
41458 #define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT         (5U)
41459 
41460 /*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */
41461 /*! @{ */
41462 
41463 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK   (0x1FFFFFU)
41464 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT  (0U)
41465 /*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0
41466  *    traffic, this field contains the quantum value in bytes to be added to credit during every queue
41467  *    scanning cycle.
41468  */
41469 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
41470 /*! @} */
41471 
41472 /* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */
41473 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT        (5U)
41474 
41475 /*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */
41476 /*! @{ */
41477 
41478 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK   (0x3FFFU)
41479 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT  (0U)
41480 /*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the
41481  *    sendSlopeCredit value required for credit-based shaper algorithm for Queue 1.
41482  */
41483 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
41484 /*! @} */
41485 
41486 /* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */
41487 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT      (5U)
41488 
41489 /*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */
41490 /*! @{ */
41491 
41492 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK        (0x1FFFFFFFU)
41493 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT       (0U)
41494 /*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value
41495  *    required for the credit-based shaper algorithm.
41496  */
41497 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK)
41498 /*! @} */
41499 
41500 /* The count of ENET_QOS_MTL_TXQX_HI_CRDT */
41501 #define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT          (5U)
41502 
41503 /*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */
41504 /*! @{ */
41505 
41506 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK        (0x1FFFFFFFU)
41507 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT       (0U)
41508 /*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value
41509  *    required for the credit-based shaper algorithm.
41510  */
41511 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK)
41512 /*! @} */
41513 
41514 /* The count of ENET_QOS_MTL_TXQX_LO_CRDT */
41515 #define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT          (5U)
41516 
41517 /*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */
41518 /*! @{ */
41519 
41520 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
41521 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
41522 /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
41523  *    had an underflow while transmitting the packet.
41524  *  0b1..Transmit Queue Underflow Interrupt Status detected
41525  *  0b0..Transmit Queue Underflow Interrupt Status not detected
41526  */
41527 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
41528 
41529 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
41530 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
41531 /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
41532  *  0b1..Average Bits Per Slot Interrupt Status detected
41533  *  0b0..Average Bits Per Slot Interrupt Status not detected
41534  */
41535 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
41536 
41537 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
41538 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
41539 /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
41540  *  0b0..Transmit Queue Underflow Interrupt Status is disabled
41541  *  0b1..Transmit Queue Underflow Interrupt Status is enabled
41542  */
41543 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
41544 
41545 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
41546 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
41547 /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
41548  *    sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
41549  *  0b0..Average Bits Per Slot Interrupt is disabled
41550  *  0b1..Average Bits Per Slot Interrupt is enabled
41551  */
41552 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
41553 
41554 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
41555 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
41556 /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
41557  *    an overflow while receiving the packet.
41558  *  0b1..Receive Queue Overflow Interrupt Status detected
41559  *  0b0..Receive Queue Overflow Interrupt Status not detected
41560  */
41561 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
41562 
41563 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
41564 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
41565 /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
41566  *  0b0..Receive Queue Overflow Interrupt is disabled
41567  *  0b1..Receive Queue Overflow Interrupt is enabled
41568  */
41569 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
41570 /*! @} */
41571 
41572 /* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */
41573 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT     (5U)
41574 
41575 /*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */
41576 /*! @{ */
41577 
41578 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK       (0x3U)
41579 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT      (0U)
41580 /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
41581  *    (in bytes): The received packet is transferred to the application or DMA when the packet size
41582  *    within the MTL Rx queue is larger than the threshold.
41583  *  0b11..128
41584  *  0b01..32
41585  *  0b00..64
41586  *  0b10..96
41587  */
41588 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK)
41589 
41590 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK       (0x8U)
41591 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT      (3U)
41592 /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
41593  *    good packets (packets with no error and length less than 64 bytes), including pad-bytes and
41594  *    CRC.
41595  *  0b0..Forward Undersized Good Packets is disabled
41596  *  0b1..Forward Undersized Good Packets is enabled
41597  */
41598 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK)
41599 
41600 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK       (0x10U)
41601 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT      (4U)
41602 /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
41603  *    (CRC error, GMII_ER, watchdog timeout, or overflow).
41604  *  0b0..Forward Error Packets is disabled
41605  *  0b1..Forward Error Packets is enabled
41606  */
41607 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK)
41608 
41609 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK       (0x20U)
41610 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT      (5U)
41611 /*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet
41612  *    from the Rx queue only after the complete packet has been written to it, ignoring the RTC field
41613  *    of this register.
41614  *  0b0..Receive Queue Store and Forward is disabled
41615  *  0b1..Receive Queue Store and Forward is enabled
41616  */
41617 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK)
41618 
41619 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
41620 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
41621 /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
41622  *    does not drop the packets which only have the errors detected by the Receive Checksum Offload
41623  *    engine.
41624  *  0b1..Dropping of TCP/IP Checksum Error Packets is disabled
41625  *  0b0..Dropping of TCP/IP Checksum Error Packets is enabled
41626  */
41627 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
41628 
41629 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK      (0x80U)
41630 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT     (7U)
41631 /*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation,
41632  *    based on the fill-level of Rx queue, is enabled.
41633  *  0b0..Hardware Flow Control is disabled
41634  *  0b1..Hardware Flow Control is enabled
41635  */
41636 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK)
41637 
41638 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK       (0xF00U)
41639 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT      (8U)
41640 /*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control
41641  *    the threshold (fill-level of Rx queue) at which the flow control is activated: For more
41642  *    information on encoding for this field, see RFD.
41643  */
41644 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK)
41645 
41646 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK       (0x3C000U)
41647 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT      (14U)
41648 /*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits
41649  *    control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after
41650  *    activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1.
41651  */
41652 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK)
41653 
41654 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK       (0x1F00000U)
41655 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT      (20U)
41656 /*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. */
41657 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK)
41658 /*! @} */
41659 
41660 /* The count of ENET_QOS_MTL_RXQX_OP_MODE */
41661 #define ENET_QOS_MTL_RXQX_OP_MODE_COUNT          (5U)
41662 
41663 /*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */
41664 /*! @{ */
41665 
41666 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
41667 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
41668 /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
41669  *    DWC_ether_qos because of Receive queue overflow.
41670  */
41671 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
41672 
41673 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
41674 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
41675 /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
41676  *    Overflow Packet Counter field crossed the maximum limit.
41677  *  0b1..Overflow Counter overflow detected
41678  *  0b0..Overflow Counter overflow not detected
41679  */
41680 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
41681 
41682 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
41683 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
41684 /*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the
41685  *    DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue.
41686  */
41687 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
41688 
41689 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
41690 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
41691 /*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue
41692  *    Missed Packet Counter crossed the maximum limit.
41693  *  0b1..Missed Packet Counter overflow detected
41694  *  0b0..Missed Packet Counter overflow not detected
41695  */
41696 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
41697 /*! @} */
41698 
41699 /* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */
41700 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U)
41701 
41702 /*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */
41703 /*! @{ */
41704 
41705 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK        (0x1U)
41706 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT       (0U)
41707 /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
41708  *    Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
41709  *  0b1..MTL Rx Queue Write Controller Active Status detected
41710  *  0b0..MTL Rx Queue Write Controller Active Status not detected
41711  */
41712 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK)
41713 
41714 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK        (0x6U)
41715 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT       (1U)
41716 /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:
41717  *  0b11..Flushing the packet data and status
41718  *  0b00..Idle state
41719  *  0b01..Reading packet data
41720  *  0b10..Reading packet status (or timestamp)
41721  */
41722 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK)
41723 
41724 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK        (0x30U)
41725 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT       (4U)
41726 /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:
41727  *  0b10..Rx Queue fill-level above flow-control activate threshold
41728  *  0b01..Rx Queue fill-level below flow-control deactivate threshold
41729  *  0b00..Rx Queue empty
41730  *  0b11..Rx Queue full
41731  */
41732 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK)
41733 
41734 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK          (0x3FFF0000U)
41735 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT         (16U)
41736 /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. */
41737 #define ENET_QOS_MTL_RXQX_DBG_PRXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK)
41738 /*! @} */
41739 
41740 /* The count of ENET_QOS_MTL_RXQX_DBG */
41741 #define ENET_QOS_MTL_RXQX_DBG_COUNT              (5U)
41742 
41743 /*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */
41744 /*! @{ */
41745 
41746 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK     (0x7U)
41747 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT    (0U)
41748 /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. */
41749 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
41750 
41751 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
41752 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
41753 /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives
41754  *    the packet data to the ARI interface such that the entire packet data of currently-selected
41755  *    queue is transmitted before switching to other queue.
41756  *  0b0..Receive Queue Packet Arbitration is disabled
41757  *  0b1..Receive Queue Packet Arbitration is enabled
41758  */
41759 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
41760 /*! @} */
41761 
41762 /* The count of ENET_QOS_MTL_RXQX_CTRL */
41763 #define ENET_QOS_MTL_RXQX_CTRL_COUNT             (5U)
41764 
41765 /*! @name DMA_MODE - DMA Bus Mode */
41766 /*! @{ */
41767 
41768 #define ENET_QOS_DMA_MODE_SWR_MASK               (0x1U)
41769 #define ENET_QOS_DMA_MODE_SWR_SHIFT              (0U)
41770 /*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and
41771  *    all internal registers of the DMA, MTL, and MAC.
41772  *  0b0..Software Reset is disabled
41773  *  0b1..Software Reset is enabled
41774  */
41775 #define ENET_QOS_DMA_MODE_SWR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK)
41776 
41777 #define ENET_QOS_DMA_MODE_DSPW_MASK              (0x100U)
41778 #define ENET_QOS_DMA_MODE_DSPW_SHIFT             (8U)
41779 /*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted.
41780  *  0b0..Descriptor Posted Write is disabled
41781  *  0b1..Descriptor Posted Write is enabled
41782  */
41783 #define ENET_QOS_DMA_MODE_DSPW(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK)
41784 
41785 #define ENET_QOS_DMA_MODE_INTM_MASK              (0x30000U)
41786 #define ENET_QOS_DMA_MODE_INTM_SHIFT             (16U)
41787 /*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos.
41788  *  0b00..See above description
41789  *  0b01..See above description
41790  *  0b10..See above description
41791  *  0b11..Reserved
41792  */
41793 #define ENET_QOS_DMA_MODE_INTM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK)
41794 /*! @} */
41795 
41796 /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
41797 /*! @{ */
41798 
41799 #define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK         (0x1U)
41800 #define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT        (0U)
41801 /*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers
41802  *    of specified lengths as given below.
41803  *  0b0..Fixed Burst Length is disabled
41804  *  0b1..Fixed Burst Length is enabled
41805  */
41806 #define ENET_QOS_DMA_SYSBUS_MODE_FB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK)
41807 
41808 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK      (0x2U)
41809 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT     (1U)
41810 /*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
41811  *    master can select a burst length of 4 on the AXI interface.
41812  *  0b0..No effect
41813  *  0b1..AXI Burst Length 4
41814  */
41815 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK)
41816 
41817 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK      (0x4U)
41818 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT     (2U)
41819 /*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
41820  *    master can select a burst length of 8 on the AXI interface.
41821  *  0b0..No effect
41822  *  0b1..AXI Burst Length 8
41823  */
41824 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK)
41825 
41826 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK     (0x8U)
41827 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT    (3U)
41828 /*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
41829  *    master can select a burst length of 16 on the AXI interface.
41830  *  0b0..No effect
41831  *  0b1..AXI Burst Length 16
41832  */
41833 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK)
41834 
41835 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK       (0x400U)
41836 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT      (10U)
41837 /*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state
41838  *    when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in
41839  *    the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register.
41840  *  0b0..Automatic AXI LPI is disabled
41841  *  0b1..Automatic AXI LPI is enabled
41842  */
41843 #define ENET_QOS_DMA_SYSBUS_MODE_AALE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK)
41844 
41845 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK        (0x1000U)
41846 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT       (12U)
41847 /*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs
41848  *    address-aligned burst transfers on Read and Write channels.
41849  *  0b0..Address-Aligned Beats is disabled
41850  *  0b1..Address-Aligned Beats is enabled
41851  */
41852 #define ENET_QOS_DMA_SYSBUS_MODE_AAL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK)
41853 
41854 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK    (0x2000U)
41855 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT   (13U)
41856 /*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers
41857  *    performed by the EQOS-AXI master do not cross 1 KB boundary.
41858  *  0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
41859  *  0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
41860  */
41861 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK)
41862 
41863 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U)
41864 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
41865 /*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. */
41866 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK)
41867 
41868 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U)
41869 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
41870 /*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum
41871  *    outstanding request on the AXI write interface.
41872  */
41873 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK)
41874 
41875 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U)
41876 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
41877 /*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables
41878  *    the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet
41879  *    is received.
41880  *  0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled
41881  *  0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled
41882  */
41883 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK)
41884 
41885 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK     (0x80000000U)
41886 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT    (31U)
41887 /*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported
41888  *    by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock
41889  *    controller.
41890  *  0b0..Low Power Interface (LPI) is disabled
41891  *  0b1..Low Power Interface (LPI) is enabled
41892  */
41893 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK)
41894 /*! @} */
41895 
41896 /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
41897 /*! @{ */
41898 
41899 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U)
41900 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
41901 /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
41902  *  0b1..DMA Channel 0 Interrupt Status detected
41903  *  0b0..DMA Channel 0 Interrupt Status not detected
41904  */
41905 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK)
41906 
41907 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U)
41908 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U)
41909 /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
41910  *  0b1..DMA Channel 1 Interrupt Status detected
41911  *  0b0..DMA Channel 1 Interrupt Status not detected
41912  */
41913 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK)
41914 
41915 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U)
41916 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U)
41917 /*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2.
41918  *  0b1..DMA Channel 2 Interrupt Status detected
41919  *  0b0..DMA Channel 2 Interrupt Status not detected
41920  */
41921 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK)
41922 
41923 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U)
41924 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U)
41925 /*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3.
41926  *  0b1..DMA Channel 3 Interrupt Status detected
41927  *  0b0..DMA Channel 3 Interrupt Status not detected
41928  */
41929 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK)
41930 
41931 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U)
41932 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U)
41933 /*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4.
41934  *  0b1..DMA Channel 4 Interrupt Status detected
41935  *  0b0..DMA Channel 4 Interrupt Status not detected
41936  */
41937 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK)
41938 
41939 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U)
41940 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
41941 /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
41942  *  0b1..MTL Interrupt Status detected
41943  *  0b0..MTL Interrupt Status not detected
41944  */
41945 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK)
41946 
41947 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U)
41948 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
41949 /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
41950  *  0b1..MAC Interrupt Status detected
41951  *  0b0..MAC Interrupt Status not detected
41952  */
41953 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK)
41954 /*! @} */
41955 
41956 /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
41957 /*! @{ */
41958 
41959 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK  (0x1U)
41960 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
41961 /*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the
41962  *    AXI master is active, and it is transferring data.
41963  *  0b1..AXI Master Write Channel or AHB Master Status detected
41964  *  0b0..AXI Master Write Channel or AHB Master Status not detected
41965  */
41966 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
41967 
41968 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK  (0x2U)
41969 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
41970 /*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of
41971  *    the AXI master is active, and it is transferring the data.
41972  *  0b1..AXI Master Read Channel Status detected
41973  *  0b0..AXI Master Read Channel Status not detected
41974  */
41975 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK)
41976 
41977 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK     (0xF00U)
41978 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT    (8U)
41979 /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0.
41980  *  0b0010..Reserved for future use
41981  *  0b0101..Running (Closing the Rx Descriptor)
41982  *  0b0001..Running (Fetching Rx Transfer Descriptor)
41983  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
41984  *  0b0011..Running (Waiting for Rx packet)
41985  *  0b0000..Stopped (Reset or Stop Receive Command issued)
41986  *  0b0100..Suspended (Rx Descriptor Unavailable)
41987  *  0b0110..Timestamp write state
41988  */
41989 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK)
41990 
41991 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK     (0xF000U)
41992 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT    (12U)
41993 /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0.
41994  *  0b0101..Reserved for future use
41995  *  0b0111..Running (Closing Tx Descriptor)
41996  *  0b0001..Running (Fetching Tx Transfer Descriptor)
41997  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
41998  *  0b0010..Running (Waiting for status)
41999  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
42000  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
42001  *  0b0100..Timestamp write state
42002  */
42003 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK)
42004 
42005 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK     (0xF0000U)
42006 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT    (16U)
42007 /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
42008  *  0b0010..Reserved for future use
42009  *  0b0101..Running (Closing the Rx Descriptor)
42010  *  0b0001..Running (Fetching Rx Transfer Descriptor)
42011  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
42012  *  0b0011..Running (Waiting for Rx packet)
42013  *  0b0000..Stopped (Reset or Stop Receive Command issued)
42014  *  0b0100..Suspended (Rx Descriptor Unavailable)
42015  *  0b0110..Timestamp write state
42016  */
42017 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK)
42018 
42019 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK     (0xF00000U)
42020 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT    (20U)
42021 /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
42022  *  0b0101..Reserved for future use
42023  *  0b0111..Running (Closing Tx Descriptor)
42024  *  0b0001..Running (Fetching Tx Transfer Descriptor)
42025  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
42026  *  0b0010..Running (Waiting for status)
42027  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
42028  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
42029  *  0b0100..Timestamp write state
42030  */
42031 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK)
42032 
42033 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK     (0xF000000U)
42034 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT    (24U)
42035 /*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2.
42036  *  0b0010..Reserved for future use
42037  *  0b0101..Running (Closing the Rx Descriptor)
42038  *  0b0001..Running (Fetching Rx Transfer Descriptor)
42039  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
42040  *  0b0011..Running (Waiting for Rx packet)
42041  *  0b0000..Stopped (Reset or Stop Receive Command issued)
42042  *  0b0100..Suspended (Rx Descriptor Unavailable)
42043  *  0b0110..Timestamp write state
42044  */
42045 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK)
42046 
42047 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK     (0xF0000000U)
42048 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT    (28U)
42049 /*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2.
42050  *  0b0101..Reserved for future use
42051  *  0b0111..Running (Closing Tx Descriptor)
42052  *  0b0001..Running (Fetching Tx Transfer Descriptor)
42053  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
42054  *  0b0010..Running (Waiting for status)
42055  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
42056  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
42057  *  0b0100..Timestamp write state
42058  */
42059 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK)
42060 /*! @} */
42061 
42062 /*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */
42063 /*! @{ */
42064 
42065 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK     (0xFU)
42066 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT    (0U)
42067 /*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3.
42068  *  0b0010..Reserved for future use
42069  *  0b0101..Running (Closing the Rx Descriptor)
42070  *  0b0001..Running (Fetching Rx Transfer Descriptor)
42071  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
42072  *  0b0011..Running (Waiting for Rx packet)
42073  *  0b0000..Stopped (Reset or Stop Receive Command issued)
42074  *  0b0100..Suspended (Rx Descriptor Unavailable)
42075  *  0b0110..Timestamp write state
42076  */
42077 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK)
42078 
42079 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK     (0xF0U)
42080 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT    (4U)
42081 /*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3.
42082  *  0b0101..Reserved for future use
42083  *  0b0111..Running (Closing Tx Descriptor)
42084  *  0b0001..Running (Fetching Tx Transfer Descriptor)
42085  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
42086  *  0b0010..Running (Waiting for status)
42087  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
42088  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
42089  *  0b0100..Timestamp write state
42090  */
42091 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK)
42092 
42093 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK     (0xF00U)
42094 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT    (8U)
42095 /*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4.
42096  *  0b0010..Reserved for future use
42097  *  0b0101..Running (Closing the Rx Descriptor)
42098  *  0b0001..Running (Fetching Rx Transfer Descriptor)
42099  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
42100  *  0b0011..Running (Waiting for Rx packet)
42101  *  0b0000..Stopped (Reset or Stop Receive Command issued)
42102  *  0b0100..Suspended (Rx Descriptor Unavailable)
42103  *  0b0110..Timestamp write state
42104  */
42105 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK)
42106 
42107 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK     (0xF000U)
42108 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT    (12U)
42109 /*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4.
42110  *  0b0101..Reserved for future use
42111  *  0b0111..Running (Closing Tx Descriptor)
42112  *  0b0001..Running (Fetching Tx Transfer Descriptor)
42113  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
42114  *  0b0010..Running (Waiting for status)
42115  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
42116  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
42117  *  0b0100..Timestamp write state
42118  */
42119 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK)
42120 /*! @} */
42121 
42122 /*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */
42123 /*! @{ */
42124 
42125 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU)
42126 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
42127 /*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait
42128  *    for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64
42129  *    clock cycles
42130  */
42131 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK)
42132 /*! @} */
42133 
42134 /*! @name DMA_TBS_CTRL - TBS Control */
42135 /*! @{ */
42136 
42137 #define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK          (0x1U)
42138 #define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT         (0U)
42139 /*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid.
42140  *  0b0..Fetch Time Offset is invalid
42141  *  0b1..Fetch Time Offset is valid
42142  */
42143 #define ENET_QOS_DMA_TBS_CTRL_FTOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK)
42144 
42145 #define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK          (0x70U)
42146 #define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT         (4U)
42147 /*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. */
42148 #define ENET_QOS_DMA_TBS_CTRL_FGOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK)
42149 
42150 #define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK          (0xFFFFFF00U)
42151 #define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT         (8U)
42152 /*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the
42153  *    Launch time to compute the Fetch Time.
42154  */
42155 #define ENET_QOS_DMA_TBS_CTRL_FTOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOS_MASK)
42156 /*! @} */
42157 
42158 /*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */
42159 /*! @{ */
42160 
42161 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK         (0x10000U)
42162 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT        (16U)
42163 /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in
42164  *    DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times.
42165  *  0b0..8xPBL mode is disabled
42166  *  0b1..8xPBL mode is enabled
42167  */
42168 #define ENET_QOS_DMA_CHX_CTRL_PBLx8(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK)
42169 
42170 #define ENET_QOS_DMA_CHX_CTRL_DSL_MASK           (0x1C0000U)
42171 #define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT          (18U)
42172 /*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on
42173  *    the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors.
42174  */
42175 #define ENET_QOS_DMA_CHX_CTRL_DSL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK)
42176 /*! @} */
42177 
42178 /* The count of ENET_QOS_DMA_CHX_CTRL */
42179 #define ENET_QOS_DMA_CHX_CTRL_COUNT              (5U)
42180 
42181 /*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */
42182 /*! @{ */
42183 
42184 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK         (0x1U)
42185 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT        (0U)
42186 /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
42187  *  0b1..Start Transmission Command
42188  *  0b0..Stop Transmission Command
42189  */
42190 #define ENET_QOS_DMA_CHX_TX_CTRL_ST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK)
42191 
42192 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK        (0x10U)
42193 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT       (4U)
42194 /*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second
42195  *    packet of the Transmit data even before the status for the first packet is obtained.
42196  *  0b0..Operate on Second Packet disabled
42197  *  0b1..Operate on Second Packet enabled
42198  */
42199 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK)
42200 
42201 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK       (0x8000U)
42202 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT      (15U)
42203 /*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of
42204  *    locations in the MTL before initiating a transfer.
42205  *  0b0..Ignore PBL Requirement is disabled
42206  *  0b1..Ignore PBL Requirement is enabled
42207  */
42208 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK)
42209 
42210 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK      (0x3F0000U)
42211 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT     (16U)
42212 /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
42213  *    transferred in one DMA block data transfer.
42214  */
42215 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK)
42216 
42217 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK       (0x10000000U)
42218 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT      (28U)
42219 /*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced
42220  *    Descriptors that are 32 Bytes for both Normal and Context Descriptors.
42221  *  0b0..Enhanced Descriptor is disabled
42222  *  0b1..Enhanced Descriptor is enabled
42223  */
42224 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK)
42225 /*! @} */
42226 
42227 /* The count of ENET_QOS_DMA_CHX_TX_CTRL */
42228 #define ENET_QOS_DMA_CHX_TX_CTRL_COUNT           (5U)
42229 
42230 /*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */
42231 /*! @{ */
42232 
42233 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK         (0x1U)
42234 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT        (0U)
42235 /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from
42236  *    the Receive list and processes the incoming packets.
42237  *  0b1..Start Receive
42238  *  0b0..Stop Receive
42239  */
42240 #define ENET_QOS_DMA_CHX_RX_CTRL_SR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK)
42241 
42242 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK   (0xEU)
42243 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT  (1U)
42244 /*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. */
42245 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK)
42246 
42247 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK  (0x7FF0U)
42248 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U)
42249 /*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. */
42250 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK)
42251 
42252 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK      (0x3F0000U)
42253 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT     (16U)
42254 /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
42255  *    transferred in one DMA block data transfer.
42256  */
42257 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK)
42258 
42259 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK        (0x80000000U)
42260 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT       (31U)
42261 /*! RPF - Rx Packet Flush.
42262  *  0b0..Rx Packet Flush is disabled
42263  *  0b1..Rx Packet Flush is enabled
42264  */
42265 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK)
42266 /*! @} */
42267 
42268 /* The count of ENET_QOS_DMA_CHX_RX_CTRL */
42269 #define ENET_QOS_DMA_CHX_RX_CTRL_COUNT           (5U)
42270 
42271 /*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */
42272 /*! @{ */
42273 
42274 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U)
42275 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U)
42276 /*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. */
42277 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
42278 /*! @} */
42279 
42280 /* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */
42281 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT  (5U)
42282 
42283 /*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */
42284 /*! @{ */
42285 
42286 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U)
42287 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U)
42288 /*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. */
42289 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
42290 /*! @} */
42291 
42292 /* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */
42293 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT  (5U)
42294 
42295 /*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */
42296 /*! @{ */
42297 
42298 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U)
42299 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U)
42300 /*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. */
42301 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
42302 /*! @} */
42303 
42304 /* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */
42305 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT   (5U)
42306 
42307 /*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */
42308 /*! @{ */
42309 
42310 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U)
42311 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U)
42312 /*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. */
42313 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
42314 /*! @} */
42315 
42316 /* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */
42317 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT   (5U)
42318 
42319 /*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */
42320 /*! @{ */
42321 
42322 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
42323 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
42324 /*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. */
42325 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
42326 /*! @} */
42327 
42328 /* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */
42329 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U)
42330 
42331 /*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */
42332 /*! @{ */
42333 
42334 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
42335 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
42336 /*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. */
42337 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
42338 /*! @} */
42339 
42340 /* The count of ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH */
42341 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_COUNT (5U)
42342 
42343 /*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */
42344 /*! @{ */
42345 
42346 #define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK         (0x1U)
42347 #define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT        (0U)
42348 /*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled.
42349  *  0b0..Transmit Interrupt is disabled
42350  *  0b1..Transmit Interrupt is enabled
42351  */
42352 #define ENET_QOS_DMA_CHX_INT_EN_TIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK)
42353 
42354 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK        (0x2U)
42355 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT       (1U)
42356 /*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled.
42357  *  0b0..Transmit Stopped is disabled
42358  *  0b1..Transmit Stopped is enabled
42359  */
42360 #define ENET_QOS_DMA_CHX_INT_EN_TXSE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK)
42361 
42362 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK        (0x4U)
42363 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT       (2U)
42364 /*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the
42365  *    Transmit Buffer Unavailable interrupt is enabled.
42366  *  0b0..Transmit Buffer Unavailable is disabled
42367  *  0b1..Transmit Buffer Unavailable is enabled
42368  */
42369 #define ENET_QOS_DMA_CHX_INT_EN_TBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK)
42370 
42371 #define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK         (0x40U)
42372 #define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT        (6U)
42373 /*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled.
42374  *  0b0..Receive Interrupt is disabled
42375  *  0b1..Receive Interrupt is enabled
42376  */
42377 #define ENET_QOS_DMA_CHX_INT_EN_RIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK)
42378 
42379 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK        (0x80U)
42380 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT       (7U)
42381 /*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the
42382  *    Receive Buffer Unavailable interrupt is enabled.
42383  *  0b0..Receive Buffer Unavailable is disabled
42384  *  0b1..Receive Buffer Unavailable is enabled
42385  */
42386 #define ENET_QOS_DMA_CHX_INT_EN_RBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK)
42387 
42388 #define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK         (0x100U)
42389 #define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT        (8U)
42390 /*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled.
42391  *  0b0..Receive Stopped is disabled
42392  *  0b1..Receive Stopped is enabled
42393  */
42394 #define ENET_QOS_DMA_CHX_INT_EN_RSE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK)
42395 
42396 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK        (0x200U)
42397 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT       (9U)
42398 /*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive
42399  *    Watchdog Timeout interrupt is enabled.
42400  *  0b0..Receive Watchdog Timeout is disabled
42401  *  0b1..Receive Watchdog Timeout is enabled
42402  */
42403 #define ENET_QOS_DMA_CHX_INT_EN_RWTE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK)
42404 
42405 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK        (0x400U)
42406 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT       (10U)
42407 /*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled.
42408  *  0b0..Early Transmit Interrupt is disabled
42409  *  0b1..Early Transmit Interrupt is enabled
42410  */
42411 #define ENET_QOS_DMA_CHX_INT_EN_ETIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
42412 
42413 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK        (0x800U)
42414 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT       (11U)
42415 /*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled.
42416  *  0b0..Early Receive Interrupt is disabled
42417  *  0b1..Early Receive Interrupt is enabled
42418  */
42419 #define ENET_QOS_DMA_CHX_INT_EN_ERIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
42420 
42421 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK        (0x1000U)
42422 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT       (12U)
42423 /*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled.
42424  *  0b0..Fatal Bus Error is disabled
42425  *  0b1..Fatal Bus Error is enabled
42426  */
42427 #define ENET_QOS_DMA_CHX_INT_EN_FBEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK)
42428 
42429 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK        (0x2000U)
42430 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT       (13U)
42431 /*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled.
42432  *  0b0..Context Descriptor Error is disabled
42433  *  0b1..Context Descriptor Error is enabled
42434  */
42435 #define ENET_QOS_DMA_CHX_INT_EN_CDEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK)
42436 
42437 #define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK         (0x4000U)
42438 #define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT        (14U)
42439 /*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled.
42440  *  0b0..Abnormal Interrupt Summary is disabled
42441  *  0b1..Abnormal Interrupt Summary is enabled
42442  */
42443 #define ENET_QOS_DMA_CHX_INT_EN_AIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK)
42444 
42445 #define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK         (0x8000U)
42446 #define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT        (15U)
42447 /*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled.
42448  *  0b0..Normal Interrupt Summary is disabled
42449  *  0b1..Normal Interrupt Summary is enabled
42450  */
42451 #define ENET_QOS_DMA_CHX_INT_EN_NIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK)
42452 /*! @} */
42453 
42454 /* The count of ENET_QOS_DMA_CHX_INT_EN */
42455 #define ENET_QOS_DMA_CHX_INT_EN_COUNT            (5U)
42456 
42457 /*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */
42458 /*! @{ */
42459 
42460 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
42461 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
42462 /*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock
42463  *    cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
42464  */
42465 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
42466 
42467 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
42468 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
42469 /*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system
42470  *    clock cycles corresponding to one unit in RWT field.
42471  */
42472 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
42473 /*! @} */
42474 
42475 /* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */
42476 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT    (5U)
42477 
42478 /*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */
42479 /*! @{ */
42480 
42481 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
42482 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
42483 /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
42484  *    programmed in the Tx descriptor with the current reference given in the RSN field.
42485  *  0b0..Slot Comparison is disabled
42486  *  0b1..Slot Comparison is enabled
42487  */
42488 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
42489 
42490 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
42491 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
42492 /*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer
42493  *    when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot
42494  *    number given in the RSN field or - ahead of the reference slot number by up to two slots This
42495  *    bit is applicable only when the ESC bit is set.
42496  *  0b0..Advance Slot Check is disabled
42497  *  0b1..Advance Slot Check is enabled
42498  */
42499 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
42500 
42501 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
42502 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
42503 /*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA
42504  *    fetches the scheduled packets.
42505  */
42506 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
42507 
42508 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
42509 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
42510 /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA. */
42511 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
42512 /*! @} */
42513 
42514 /* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */
42515 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U)
42516 
42517 /*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */
42518 /*! @{ */
42519 
42520 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
42521 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
42522 /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. */
42523 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
42524 /*! @} */
42525 
42526 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */
42527 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT    (5U)
42528 
42529 /*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */
42530 /*! @{ */
42531 
42532 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
42533 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
42534 /*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. */
42535 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
42536 /*! @} */
42537 
42538 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */
42539 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT    (5U)
42540 
42541 /*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */
42542 /*! @{ */
42543 
42544 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
42545 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
42546 /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. */
42547 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
42548 /*! @} */
42549 
42550 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */
42551 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT     (5U)
42552 
42553 /*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */
42554 /*! @{ */
42555 
42556 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
42557 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
42558 /*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. */
42559 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
42560 /*! @} */
42561 
42562 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */
42563 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT     (5U)
42564 
42565 /*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */
42566 /*! @{ */
42567 
42568 #define ENET_QOS_DMA_CHX_STAT_TI_MASK            (0x1U)
42569 #define ENET_QOS_DMA_CHX_STAT_TI_SHIFT           (0U)
42570 /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
42571  *  0b1..Transmit Interrupt status detected
42572  *  0b0..Transmit Interrupt status not detected
42573  */
42574 #define ENET_QOS_DMA_CHX_STAT_TI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK)
42575 
42576 #define ENET_QOS_DMA_CHX_STAT_TPS_MASK           (0x2U)
42577 #define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT          (1U)
42578 /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
42579  *  0b1..Transmit Process Stopped status detected
42580  *  0b0..Transmit Process Stopped status not detected
42581  */
42582 #define ENET_QOS_DMA_CHX_STAT_TPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK)
42583 
42584 #define ENET_QOS_DMA_CHX_STAT_TBU_MASK           (0x4U)
42585 #define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT          (2U)
42586 /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
42587  *    descriptor in the Transmit list, and the DMA cannot acquire it.
42588  *  0b1..Transmit Buffer Unavailable status detected
42589  *  0b0..Transmit Buffer Unavailable status not detected
42590  */
42591 #define ENET_QOS_DMA_CHX_STAT_TBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK)
42592 
42593 #define ENET_QOS_DMA_CHX_STAT_RI_MASK            (0x40U)
42594 #define ENET_QOS_DMA_CHX_STAT_RI_SHIFT           (6U)
42595 /*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
42596  *  0b1..Receive Interrupt status detected
42597  *  0b0..Receive Interrupt status not detected
42598  */
42599 #define ENET_QOS_DMA_CHX_STAT_RI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK)
42600 
42601 #define ENET_QOS_DMA_CHX_STAT_RBU_MASK           (0x80U)
42602 #define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT          (7U)
42603 /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next
42604  *    descriptor in the Receive list, and the DMA cannot acquire it.
42605  *  0b1..Receive Buffer Unavailable status detected
42606  *  0b0..Receive Buffer Unavailable status not detected
42607  */
42608 #define ENET_QOS_DMA_CHX_STAT_RBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK)
42609 
42610 #define ENET_QOS_DMA_CHX_STAT_RPS_MASK           (0x100U)
42611 #define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT          (8U)
42612 /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
42613  *  0b1..Receive Process Stopped status detected
42614  *  0b0..Receive Process Stopped status not detected
42615  */
42616 #define ENET_QOS_DMA_CHX_STAT_RPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK)
42617 
42618 #define ENET_QOS_DMA_CHX_STAT_RWT_MASK           (0x200U)
42619 #define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT          (9U)
42620 /*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048
42621  *    bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
42622  *  0b1..Receive Watchdog Timeout status detected
42623  *  0b0..Receive Watchdog Timeout status not detected
42624  */
42625 #define ENET_QOS_DMA_CHX_STAT_RWT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK)
42626 
42627 #define ENET_QOS_DMA_CHX_STAT_ETI_MASK           (0x400U)
42628 #define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT          (10U)
42629 /*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the
42630  *    transfer of packet data to the MTL TXFIFO memory.
42631  *  0b1..Early Transmit Interrupt status detected
42632  *  0b0..Early Transmit Interrupt status not detected
42633  */
42634 #define ENET_QOS_DMA_CHX_STAT_ETI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK)
42635 
42636 #define ENET_QOS_DMA_CHX_STAT_ERI_MASK           (0x800U)
42637 #define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT          (11U)
42638 /*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the
42639  *    transfer of packet data to the memory.
42640  *  0b1..Early Receive Interrupt status detected
42641  *  0b0..Early Receive Interrupt status not detected
42642  */
42643 #define ENET_QOS_DMA_CHX_STAT_ERI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK)
42644 
42645 #define ENET_QOS_DMA_CHX_STAT_FBE_MASK           (0x1000U)
42646 #define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT          (12U)
42647 /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
42648  *  0b1..Fatal Bus Error status detected
42649  *  0b0..Fatal Bus Error status not detected
42650  */
42651 #define ENET_QOS_DMA_CHX_STAT_FBE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK)
42652 
42653 #define ENET_QOS_DMA_CHX_STAT_CDE_MASK           (0x2000U)
42654 #define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT          (13U)
42655 /*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a
42656  *    descriptor error, which indicates invalid context in the middle of packet flow ( intermediate
42657  *    descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor
42658  *    with either of the buffer address as ones which is considered to be invalid.
42659  *  0b1..Context Descriptor Error status detected
42660  *  0b0..Context Descriptor Error status not detected
42661  */
42662 #define ENET_QOS_DMA_CHX_STAT_CDE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK)
42663 
42664 #define ENET_QOS_DMA_CHX_STAT_AIS_MASK           (0x4000U)
42665 #define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT          (14U)
42666 /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
42667  *    following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
42668  *    register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive
42669  *    Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context
42670  *    Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
42671  *  0b1..Abnormal Interrupt Summary status detected
42672  *  0b0..Abnormal Interrupt Summary status not detected
42673  */
42674 #define ENET_QOS_DMA_CHX_STAT_AIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK)
42675 
42676 #define ENET_QOS_DMA_CHX_STAT_NIS_MASK           (0x8000U)
42677 #define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT          (15U)
42678 /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
42679  *    following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
42680  *    register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive
42681  *    Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt
42682  *    enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit.
42683  *  0b1..Normal Interrupt Summary status detected
42684  *  0b0..Normal Interrupt Summary status not detected
42685  */
42686 #define ENET_QOS_DMA_CHX_STAT_NIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK)
42687 
42688 #define ENET_QOS_DMA_CHX_STAT_TEB_MASK           (0x70000U)
42689 #define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT          (16U)
42690 /*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. */
42691 #define ENET_QOS_DMA_CHX_STAT_TEB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK)
42692 
42693 #define ENET_QOS_DMA_CHX_STAT_REB_MASK           (0x380000U)
42694 #define ENET_QOS_DMA_CHX_STAT_REB_SHIFT          (19U)
42695 /*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. */
42696 #define ENET_QOS_DMA_CHX_STAT_REB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK)
42697 /*! @} */
42698 
42699 /* The count of ENET_QOS_DMA_CHX_STAT */
42700 #define ENET_QOS_DMA_CHX_STAT_COUNT              (5U)
42701 
42702 /*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */
42703 /*! @{ */
42704 
42705 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
42706 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
42707 /*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are
42708  *    dropped by the DMA either because of bus error or because of programming RPF field in
42709  *    DMA_CH2_RX_CONTROL register.
42710  */
42711 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
42712 
42713 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
42714 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
42715 /*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further.
42716  *  0b1..Miss Frame Counter overflow occurred
42717  *  0b0..Miss Frame Counter overflow not occurred
42718  */
42719 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
42720 /*! @} */
42721 
42722 /* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */
42723 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT    (5U)
42724 
42725 /*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */
42726 /*! @{ */
42727 
42728 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU)
42729 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U)
42730 /*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. */
42731 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK)
42732 
42733 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U)
42734 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U)
42735 /*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC
42736  *    Counter field crossed the maximum limit.
42737  *  0b1..Rx Parser Accept Counter overflow occurred
42738  *  0b0..Rx Parser Accept Counter overflow not occurred
42739  */
42740 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK)
42741 /*! @} */
42742 
42743 /* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */
42744 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT    (5U)
42745 
42746 /*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */
42747 /*! @{ */
42748 
42749 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK    (0xFFFU)
42750 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT   (0U)
42751 /*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments
42752  *    for burst transfer completed by the Rx DMA from the start of packet transfer.
42753  */
42754 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
42755 /*! @} */
42756 
42757 /* The count of ENET_QOS_DMA_CHX_RX_ERI_CNT */
42758 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_COUNT        (5U)
42759 
42760 
42761 /*!
42762  * @}
42763  */ /* end of group ENET_QOS_Register_Masks */
42764 
42765 
42766 /* ENET_QOS - Peripheral instance base addresses */
42767 /** Peripheral ENET_QOS base address */
42768 #define ENET_QOS_BASE                            (0x30BF0000u)
42769 /** Peripheral ENET_QOS base pointer */
42770 #define ENET_QOS                                 ((ENET_QOS_Type *)ENET_QOS_BASE)
42771 /** Array initializer of ENET_QOS peripheral base addresses */
42772 #define ENET_QOS_BASE_ADDRS                      { ENET_QOS_BASE }
42773 /** Array initializer of ENET_QOS peripheral base pointers */
42774 #define ENET_QOS_BASE_PTRS                       { ENET_QOS }
42775 /** Interrupt vectors for the ENET_QOS peripheral type */
42776 #define ENET_QOS_IRQS                            { ENET_QOS_IRQn }
42777 #define ENET_QOS_PMT_IRQS                        { ENET_QOS_PMT_IRQn }
42778 
42779 /*!
42780  * @}
42781  */ /* end of group ENET_QOS_Peripheral_Access_Layer */
42782 
42783 
42784 /* ----------------------------------------------------------------------------
42785    -- FLEXSPI Peripheral Access Layer
42786    ---------------------------------------------------------------------------- */
42787 
42788 /*!
42789  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
42790  * @{
42791  */
42792 
42793 /** FLEXSPI - Register Layout Typedef */
42794 typedef struct {
42795   __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
42796   __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
42797   __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
42798   __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
42799   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
42800   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
42801   __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
42802   __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
42803   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
42804        uint8_t RESERVED_0[32];
42805   __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
42806   __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
42807   __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
42808        uint8_t RESERVED_1[4];
42809   __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
42810        uint8_t RESERVED_2[8];
42811   __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
42812   __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
42813        uint8_t RESERVED_3[8];
42814   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
42815   __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
42816   __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
42817   __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
42818   __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
42819        uint8_t RESERVED_4[24];
42820   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
42821   __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
42822   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
42823   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
42824   __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
42825   __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
42826        uint8_t RESERVED_5[8];
42827   __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
42828   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
42829   __IO uint32_t LUT[128];                          /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
42830 } FLEXSPI_Type;
42831 
42832 /* ----------------------------------------------------------------------------
42833    -- FLEXSPI Register Masks
42834    ---------------------------------------------------------------------------- */
42835 
42836 /*!
42837  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
42838  * @{
42839  */
42840 
42841 /*! @name MCR0 - Module Control Register 0 */
42842 /*! @{ */
42843 
42844 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
42845 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
42846 /*! SWRESET - Software Reset */
42847 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
42848 
42849 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
42850 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
42851 /*! MDIS - Module Disable */
42852 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
42853 
42854 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
42855 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
42856 /*! RXCLKSRC - Sample Clock source selection for Flash Reading
42857  *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
42858  *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
42859  *  0b10..Reserved
42860  *  0b11..Flash provided Read strobe and input from DQS pad
42861  */
42862 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
42863 
42864 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
42865 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
42866 /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
42867  *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
42868  *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
42869  */
42870 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
42871 
42872 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
42873 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
42874 /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
42875  *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
42876  *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
42877  */
42878 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
42879 
42880 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
42881 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
42882 /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
42883  *  0b000..Divided by 1
42884  *  0b001..Divided by 2
42885  *  0b010..Divided by 3
42886  *  0b011..Divided by 4
42887  *  0b100..Divided by 5
42888  *  0b101..Divided by 6
42889  *  0b110..Divided by 7
42890  *  0b111..Divided by 8
42891  */
42892 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
42893 
42894 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
42895 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
42896 /*! HSEN - Half Speed Serial Flash access Enable.
42897  *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
42898  *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
42899  */
42900 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
42901 
42902 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
42903 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
42904 /*! DOZEEN - Doze mode enable bit
42905  *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
42906  *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
42907  */
42908 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
42909 
42910 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
42911 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
42912 /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
42913  *  0b0..Disable.
42914  *  0b1..Enable.
42915  */
42916 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
42917 
42918 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
42919 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
42920 /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
42921  *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
42922  *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
42923  *  0b0..Disable.
42924  *  0b1..Enable.
42925  */
42926 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
42927 
42928 #define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
42929 #define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
42930 /*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
42931  *    disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
42932  *    is correctly executed.
42933  *  0b0..Disable.
42934  *  0b1..Enable.
42935  */
42936 #define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
42937 
42938 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
42939 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
42940 /*! IPGRANTWAIT - Time out wait cycle for IP command grant. */
42941 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
42942 
42943 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
42944 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
42945 /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. */
42946 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
42947 /*! @} */
42948 
42949 /*! @name MCR1 - Module Control Register 1 */
42950 /*! @{ */
42951 
42952 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
42953 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
42954 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
42955 
42956 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
42957 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
42958 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
42959 /*! @} */
42960 
42961 /*! @name MCR2 - Module Control Register 2 */
42962 /*! @{ */
42963 
42964 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
42965 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
42966 /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
42967  *    automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
42968  *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
42969  *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
42970  *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
42971  *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
42972  */
42973 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
42974 
42975 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
42976 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
42977 /*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
42978  *    written with 0x1. This bit will be auto-cleared immediately.
42979  */
42980 #define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
42981 
42982 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
42983 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
42984 /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
42985  *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
42986  *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
42987  *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
42988  *       ignored.
42989  *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
42990  */
42991 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
42992 
42993 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
42994 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
42995 /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
42996  *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
42997  *    field, MCR0[SWRESET] should be set.
42998  *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
42999  *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
43000  */
43001 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
43002 
43003 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
43004 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
43005 /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. */
43006 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
43007 /*! @} */
43008 
43009 /*! @name AHBCR - AHB Bus Control Register */
43010 /*! @{ */
43011 
43012 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
43013 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
43014 /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
43015  *  0b0..Flash will be accessed in Individual mode.
43016  *  0b1..Flash will be accessed in Parallel mode.
43017  */
43018 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
43019 
43020 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
43021 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
43022 /*! CACHABLEEN - Enable AHB bus cachable read access support.
43023  *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
43024  *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
43025  */
43026 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
43027 
43028 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
43029 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
43030 /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
43031  *    of AHB write access, refer for more details about AHB bufferable write.
43032  *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
43033  *       ready after all data is transmitted to External device and AHB command finished.
43034  *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
43035  *       granted by arbitrator and will not wait for AHB command finished.
43036  */
43037 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
43038 
43039 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
43040 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
43041 /*! PREFETCHEN - AHB Read Prefetch Enable. */
43042 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
43043 
43044 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
43045 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
43046 /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
43047  *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
43048  *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
43049  *       burst required to meet the alignment requirement.
43050  */
43051 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
43052 /*! @} */
43053 
43054 /*! @name INTEN - Interrupt Enable Register */
43055 /*! @{ */
43056 
43057 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
43058 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
43059 /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */
43060 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
43061 
43062 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
43063 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
43064 /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */
43065 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
43066 
43067 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
43068 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
43069 /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */
43070 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
43071 
43072 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
43073 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
43074 /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */
43075 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
43076 
43077 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
43078 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
43079 /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */
43080 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
43081 
43082 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
43083 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
43084 /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */
43085 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
43086 
43087 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
43088 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
43089 /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */
43090 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
43091 
43092 #define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
43093 #define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
43094 /*! DATALEARNFAILEN - Data Learning failed interrupt enable. */
43095 #define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
43096 
43097 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
43098 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
43099 /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */
43100 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
43101 
43102 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
43103 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
43104 /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */
43105 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
43106 
43107 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
43108 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
43109 /*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */
43110 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
43111 
43112 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
43113 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
43114 /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. */
43115 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
43116 /*! @} */
43117 
43118 /*! @name INTR - Interrupt Register */
43119 /*! @{ */
43120 
43121 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
43122 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
43123 /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
43124  *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
43125  */
43126 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
43127 
43128 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
43129 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
43130 /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */
43131 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
43132 
43133 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
43134 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
43135 /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */
43136 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
43137 
43138 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
43139 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
43140 /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
43141  *    IP command, this command will be ignored and not executed at all.
43142  */
43143 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
43144 
43145 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
43146 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
43147 /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
43148  *    AHB command, this command will be ignored and not executed at all.
43149  */
43150 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
43151 
43152 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
43153 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
43154 /*! IPRXWA - IP RX FIFO watermark available interrupt. */
43155 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
43156 
43157 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
43158 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
43159 /*! IPTXWE - IP TX FIFO watermark empty interrupt. */
43160 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
43161 
43162 #define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
43163 #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
43164 /*! DATALEARNFAIL - Data Learning failed interrupt. */
43165 #define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
43166 
43167 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
43168 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
43169 /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */
43170 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
43171 
43172 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
43173 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
43174 /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */
43175 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
43176 
43177 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
43178 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
43179 /*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */
43180 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
43181 
43182 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
43183 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
43184 /*! SEQTIMEOUT - Sequence execution timeout interrupt. */
43185 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
43186 /*! @} */
43187 
43188 /*! @name LUTKEY - LUT Key Register */
43189 /*! @{ */
43190 
43191 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
43192 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
43193 /*! KEY - The Key to lock or unlock LUT. */
43194 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
43195 /*! @} */
43196 
43197 /*! @name LUTCR - LUT Control Register */
43198 /*! @{ */
43199 
43200 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
43201 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
43202 /*! LOCK - Lock LUT */
43203 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
43204 
43205 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
43206 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
43207 /*! UNLOCK - Unlock LUT */
43208 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
43209 /*! @} */
43210 
43211 /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
43212 /*! @{ */
43213 
43214 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x1FFU)
43215 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
43216 /*! BUFSZ - AHB RX Buffer Size in 64 bits. */
43217 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
43218 
43219 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
43220 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
43221 /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */
43222 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
43223 
43224 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
43225 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
43226 /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. */
43227 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
43228 
43229 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
43230 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
43231 /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. */
43232 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
43233 /*! @} */
43234 
43235 /* The count of FLEXSPI_AHBRXBUFCR0 */
43236 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
43237 
43238 /*! @name FLSHCR0 - Flash Control Register 0 */
43239 /*! @{ */
43240 
43241 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
43242 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
43243 /*! FLSHSZ - Flash Size in KByte. */
43244 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
43245 /*! @} */
43246 
43247 /* The count of FLEXSPI_FLSHCR0 */
43248 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
43249 
43250 /*! @name FLSHCR1 - Flash Control Register 1 */
43251 /*! @{ */
43252 
43253 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
43254 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
43255 /*! TCSS - Serial Flash CS setup time. */
43256 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
43257 
43258 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
43259 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
43260 /*! TCSH - Serial Flash CS Hold time. */
43261 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
43262 
43263 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
43264 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
43265 /*! WA - Word Addressable. */
43266 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
43267 
43268 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
43269 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
43270 /*! CAS - Column Address Size. */
43271 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
43272 
43273 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
43274 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
43275 /*! CSINTERVALUNIT - CS interval unit
43276  *  0b0..The CS interval unit is 1 serial clock cycle
43277  *  0b1..The CS interval unit is 256 serial clock cycle
43278  */
43279 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
43280 
43281 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
43282 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
43283 /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
43284  *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
43285  *    the interval between command sequences, this field should be set accordingly. If there is no
43286  *    limitation, set this field with value 0x0.
43287  */
43288 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
43289 /*! @} */
43290 
43291 /* The count of FLEXSPI_FLSHCR1 */
43292 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
43293 
43294 /*! @name FLSHCR2 - Flash Control Register 2 */
43295 /*! @{ */
43296 
43297 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0x1FU)
43298 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
43299 /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */
43300 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
43301 
43302 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
43303 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
43304 /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */
43305 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
43306 
43307 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0x1F00U)
43308 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
43309 /*! AWRSEQID - Sequence Index for AHB Write triggered Command. */
43310 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
43311 
43312 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
43313 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
43314 /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */
43315 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
43316 
43317 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
43318 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
43319 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
43320 
43321 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
43322 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
43323 /*! AWRWAITUNIT - AWRWAIT unit
43324  *  0b000..The AWRWAIT unit is 2 ahb clock cycle
43325  *  0b001..The AWRWAIT unit is 8 ahb clock cycle
43326  *  0b010..The AWRWAIT unit is 32 ahb clock cycle
43327  *  0b011..The AWRWAIT unit is 128 ahb clock cycle
43328  *  0b100..The AWRWAIT unit is 512 ahb clock cycle
43329  *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
43330  *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
43331  *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
43332  */
43333 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
43334 
43335 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
43336 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
43337 /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
43338  *    Refer Programmable Sequence Engine for details.
43339  */
43340 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
43341 /*! @} */
43342 
43343 /* The count of FLEXSPI_FLSHCR2 */
43344 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
43345 
43346 /*! @name FLSHCR4 - Flash Control Register 4 */
43347 /*! @{ */
43348 
43349 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
43350 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
43351 /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
43352  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
43353  *       burst start address alignment when flash is accessed in individual mode.
43354  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
43355  *       burst start address alignment when flash is accessed in individual mode.
43356  */
43357 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
43358 
43359 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
43360 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
43361 /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
43362  *    memory device on port A, this bit must be set.
43363  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
43364  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
43365  */
43366 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
43367 
43368 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
43369 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
43370 /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
43371  *    memory device on port B, this bit must be set.
43372  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
43373  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
43374  */
43375 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
43376 /*! @} */
43377 
43378 /*! @name IPCR0 - IP Control Register 0 */
43379 /*! @{ */
43380 
43381 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
43382 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
43383 /*! SFAR - Serial Flash Address for IP command. */
43384 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
43385 /*! @} */
43386 
43387 /*! @name IPCR1 - IP Control Register 1 */
43388 /*! @{ */
43389 
43390 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
43391 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
43392 /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */
43393 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
43394 
43395 #define FLEXSPI_IPCR1_ISEQID_MASK                (0x1F0000U)
43396 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
43397 /*! ISEQID - Sequence Index in LUT for IP command. */
43398 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
43399 
43400 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
43401 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
43402 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */
43403 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
43404 
43405 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
43406 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
43407 /*! IPAREN - Parallel mode Enabled for IP command.
43408  *  0b0..Flash will be accessed in Individual mode.
43409  *  0b1..Flash will be accessed in Parallel mode.
43410  */
43411 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
43412 /*! @} */
43413 
43414 /*! @name IPCMD - IP Command Register */
43415 /*! @{ */
43416 
43417 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
43418 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
43419 /*! TRG - Setting this bit will trigger an IP Command. */
43420 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
43421 /*! @} */
43422 
43423 /*! @name DLPR - Data Learn Pattern Register */
43424 /*! @{ */
43425 
43426 #define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
43427 #define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
43428 /*! DLP - Data Learning Pattern. */
43429 #define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
43430 /*! @} */
43431 
43432 /*! @name IPRXFCR - IP RX FIFO Control Register */
43433 /*! @{ */
43434 
43435 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
43436 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
43437 /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */
43438 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
43439 
43440 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
43441 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
43442 /*! RXDMAEN - IP RX FIFO reading by DMA enabled.
43443  *  0b0..IP RX FIFO would be read by processor.
43444  *  0b1..IP RX FIFO would be read by DMA.
43445  */
43446 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
43447 
43448 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0xFCU)
43449 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
43450 /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. */
43451 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
43452 /*! @} */
43453 
43454 /*! @name IPTXFCR - IP TX FIFO Control Register */
43455 /*! @{ */
43456 
43457 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
43458 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
43459 /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */
43460 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
43461 
43462 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
43463 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
43464 /*! TXDMAEN - IP TX FIFO filling by DMA enabled.
43465  *  0b0..IP TX FIFO would be filled by processor.
43466  *  0b1..IP TX FIFO would be filled by DMA.
43467  */
43468 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
43469 
43470 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
43471 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
43472 /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. */
43473 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
43474 /*! @} */
43475 
43476 /*! @name DLLCR - DLL Control Register 0 */
43477 /*! @{ */
43478 
43479 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
43480 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
43481 /*! DLLEN - DLL calibration enable. */
43482 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
43483 
43484 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
43485 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
43486 /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
43487  *    DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
43488  *    action is edge triggered, so software need to clear this bit after set this bit (no delay
43489  *    limitation).
43490  */
43491 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
43492 
43493 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
43494 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
43495 /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). */
43496 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
43497 
43498 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
43499 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
43500 /*! OVRDEN - Slave clock delay line delay cell number selection override enable. */
43501 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
43502 
43503 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
43504 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
43505 /*! OVRDVAL - Slave clock delay line delay cell number selection override value. */
43506 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
43507 /*! @} */
43508 
43509 /* The count of FLEXSPI_DLLCR */
43510 #define FLEXSPI_DLLCR_COUNT                      (2U)
43511 
43512 /*! @name STS0 - Status Register 0 */
43513 /*! @{ */
43514 
43515 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
43516 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
43517 /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
43518  *    sequence executing on FlexSPI interface.
43519  */
43520 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
43521 
43522 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
43523 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
43524 /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
43525  *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
43526  *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
43527  *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
43528  */
43529 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
43530 
43531 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
43532 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
43533 /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
43534  *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
43535  *  0b00..Triggered by AHB read command (triggered by AHB read).
43536  *  0b01..Triggered by AHB write command (triggered by AHB Write).
43537  *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
43538  *  0b11..Triggered by suspended command (resumed).
43539  */
43540 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
43541 
43542 #define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
43543 #define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
43544 /*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. */
43545 #define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
43546 
43547 #define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
43548 #define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
43549 /*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning. */
43550 #define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
43551 /*! @} */
43552 
43553 /*! @name STS1 - Status Register 1 */
43554 /*! @{ */
43555 
43556 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0x1FU)
43557 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
43558 /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
43559  *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
43560  */
43561 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
43562 
43563 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
43564 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
43565 /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
43566  *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
43567  *  0b0000..No error.
43568  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
43569  *  0b0011..There is unknown instruction opcode in the sequence.
43570  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
43571  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
43572  *  0b1110..Sequence execution timeout.
43573  */
43574 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
43575 
43576 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0x1F0000U)
43577 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
43578 /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
43579  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
43580  */
43581 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
43582 
43583 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
43584 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
43585 /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
43586  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
43587  *  0b0000..No error.
43588  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
43589  *  0b0011..There is unknown instruction opcode in the sequence.
43590  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
43591  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
43592  *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
43593  *  0b1110..Sequence execution timeout.
43594  *  0b1111..Flash boundary crossed.
43595  */
43596 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
43597 /*! @} */
43598 
43599 /*! @name STS2 - Status Register 2 */
43600 /*! @{ */
43601 
43602 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
43603 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
43604 /*! ASLVLOCK - Flash A sample clock slave delay line locked. */
43605 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
43606 
43607 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
43608 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
43609 /*! AREFLOCK - Flash A sample clock reference delay line locked. */
43610 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
43611 
43612 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
43613 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
43614 /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */
43615 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
43616 
43617 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
43618 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
43619 /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */
43620 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
43621 
43622 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
43623 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
43624 /*! BSLVLOCK - Flash B sample clock slave delay line locked. */
43625 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
43626 
43627 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
43628 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
43629 /*! BREFLOCK - Flash B sample clock reference delay line locked. */
43630 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
43631 
43632 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
43633 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
43634 /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */
43635 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
43636 
43637 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
43638 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
43639 /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. */
43640 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
43641 /*! @} */
43642 
43643 /*! @name AHBSPNDSTS - AHB Suspend Status Register */
43644 /*! @{ */
43645 
43646 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
43647 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
43648 /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */
43649 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
43650 
43651 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
43652 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
43653 /*! BUFID - AHB RX BUF ID for suspended command sequence. */
43654 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
43655 
43656 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
43657 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
43658 /*! DATLFT - Left Data size for suspended command sequence (in byte). */
43659 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
43660 /*! @} */
43661 
43662 /*! @name IPRXFSTS - IP RX FIFO Status Register */
43663 /*! @{ */
43664 
43665 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
43666 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
43667 /*! FILL - Fill level of IP RX FIFO. */
43668 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
43669 
43670 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
43671 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
43672 /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. */
43673 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
43674 /*! @} */
43675 
43676 /*! @name IPTXFSTS - IP TX FIFO Status Register */
43677 /*! @{ */
43678 
43679 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
43680 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
43681 /*! FILL - Fill level of IP TX FIFO. */
43682 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
43683 
43684 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
43685 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
43686 /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. */
43687 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
43688 /*! @} */
43689 
43690 /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
43691 /*! @{ */
43692 
43693 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
43694 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
43695 /*! RXDATA - RX Data */
43696 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
43697 /*! @} */
43698 
43699 /* The count of FLEXSPI_RFDR */
43700 #define FLEXSPI_RFDR_COUNT                       (32U)
43701 
43702 /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
43703 /*! @{ */
43704 
43705 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
43706 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
43707 /*! TXDATA - TX Data */
43708 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
43709 /*! @} */
43710 
43711 /* The count of FLEXSPI_TFDR */
43712 #define FLEXSPI_TFDR_COUNT                       (32U)
43713 
43714 /*! @name LUT - LUT 0..LUT 127 */
43715 /*! @{ */
43716 
43717 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
43718 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
43719 /*! OPERAND0 - OPERAND0 */
43720 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
43721 
43722 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
43723 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
43724 /*! NUM_PADS0 - NUM_PADS0 */
43725 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
43726 
43727 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
43728 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
43729 /*! OPCODE0 - OPCODE */
43730 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
43731 
43732 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
43733 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
43734 /*! OPERAND1 - OPERAND1 */
43735 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
43736 
43737 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
43738 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
43739 /*! NUM_PADS1 - NUM_PADS1 */
43740 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
43741 
43742 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
43743 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
43744 /*! OPCODE1 - OPCODE1 */
43745 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
43746 /*! @} */
43747 
43748 /* The count of FLEXSPI_LUT */
43749 #define FLEXSPI_LUT_COUNT                        (128U)
43750 
43751 
43752 /*!
43753  * @}
43754  */ /* end of group FLEXSPI_Register_Masks */
43755 
43756 
43757 /* FLEXSPI - Peripheral instance base addresses */
43758 /** Peripheral FLEXSPI base address */
43759 #define FLEXSPI_BASE                             (0x30BB0000u)
43760 /** Peripheral FLEXSPI base pointer */
43761 #define FLEXSPI                                  ((FLEXSPI_Type *)FLEXSPI_BASE)
43762 /** Array initializer of FLEXSPI peripheral base addresses */
43763 #define FLEXSPI_BASE_ADDRS                       { FLEXSPI_BASE }
43764 /** Array initializer of FLEXSPI peripheral base pointers */
43765 #define FLEXSPI_BASE_PTRS                        { FLEXSPI }
43766 
43767 /*!
43768  * @}
43769  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
43770 
43771 
43772 /* ----------------------------------------------------------------------------
43773    -- FRAMECOMPOSER Peripheral Access Layer
43774    ---------------------------------------------------------------------------- */
43775 
43776 /*!
43777  * @addtogroup FRAMECOMPOSER_Peripheral_Access_Layer FRAMECOMPOSER Peripheral Access Layer
43778  * @{
43779  */
43780 
43781 /** FRAMECOMPOSER - Register Layout Typedef */
43782 typedef struct {
43783   __IO uint8_t FC_INVIDCONF;                       /**< Frame Composer Input Video Configuration and HDCP Keepout Register, offset: 0x0 */
43784   __IO uint8_t FC_INHACTIV0;                       /**< Frame Composer Input Video HActive Pixels Register 0, offset: 0x1 */
43785   __IO uint8_t FC_INHACTIV1;                       /**< Frame Composer Input Video HActive Pixels Register 1, offset: 0x2 */
43786   __IO uint8_t FC_INHBLANK0;                       /**< Frame Composer Input Video HBlank Pixels Register 0, offset: 0x3 */
43787   __IO uint8_t FC_INHBLANK1;                       /**< Frame Composer Input Video HBlank Pixels Register 1, offset: 0x4 */
43788   __IO uint8_t FC_INVACTIV0;                       /**< Frame Composer Input Video VActive Pixels Register 0, offset: 0x5 */
43789   __IO uint8_t FC_INVACTIV1;                       /**< Frame Composer Input Video VActive Pixels Register 1, offset: 0x6 */
43790   __IO uint8_t FC_INVBLANK;                        /**< Frame Composer Input Video VBlank Pixels Register, offset: 0x7 */
43791   __IO uint8_t FC_HSYNCINDELAY0;                   /**< Frame Composer Input Video HSync Front Porch Register 0, offset: 0x8 */
43792   __IO uint8_t FC_HSYNCINDELAY1;                   /**< Frame Composer Input Video HSync Front Porch Register 1, offset: 0x9 */
43793   __IO uint8_t FC_HSYNCINWIDTH0;                   /**< Frame Composer Input Video HSync Width Register 0, offset: 0xA */
43794   __IO uint8_t FC_HSYNCINWIDTH1;                   /**< Frame Composer Input Video HSync Width Register 1, offset: 0xB */
43795   __IO uint8_t FC_VSYNCINDELAY;                    /**< Frame Composer Input Video VSync Front Porch Register, offset: 0xC */
43796   __IO uint8_t FC_VSYNCINWIDTH;                    /**< Frame Composer Input Video VSync Width Register, offset: 0xD */
43797   __IO uint8_t FC_INFREQ0;                         /**< Frame Composer Input Video Refresh Rate Register 0, offset: 0xE */
43798   __IO uint8_t FC_INFREQ1;                         /**< Frame Composer Input Video Refresh Rate Register 1, offset: 0xF */
43799   __IO uint8_t FC_INFREQ2;                         /**< Frame Composer Input Video Refresh Rate Register 2, offset: 0x10 */
43800   __IO uint8_t FC_CTRLDUR;                         /**< Frame Composer Control Period Duration Register, offset: 0x11 */
43801   __IO uint8_t FC_EXCTRLDUR;                       /**< Frame Composer Extended Control Period Duration Register, offset: 0x12 */
43802   __IO uint8_t FC_EXCTRLSPAC;                      /**< Frame Composer Extended Control Period Maximum Spacing Register, offset: 0x13 */
43803   __IO uint8_t FC_CH0PREAM;                        /**< Frame Composer Channel 0 Non-Preamble Data Register, offset: 0x14 */
43804   __IO uint8_t FC_CH1PREAM;                        /**< Frame Composer Channel 1 Non-Preamble Data Register, offset: 0x15 */
43805   __IO uint8_t FC_CH2PREAM;                        /**< Frame Composer Channel 2 Non-Preamble Data Register, offset: 0x16 */
43806   __IO uint8_t FC_AVICONF3;                        /**< Frame Composer AVI Packet Configuration Register 3, offset: 0x17 */
43807   __IO uint8_t FC_GCP;                             /**< Frame Composer GCP Packet Configuration Register, offset: 0x18 */
43808   __IO uint8_t FC_AVICONF0;                        /**< Frame Composer AVI Packet Configuration Register 0, offset: 0x19 */
43809   __IO uint8_t FC_AVICONF1;                        /**< Frame Composer AVI Packet Configuration Register 1, offset: 0x1A */
43810   __IO uint8_t FC_AVICONF2;                        /**< Frame Composer AVI Packet Configuration Register 2, offset: 0x1B */
43811   __IO uint8_t FC_AVIVID;                          /**< Frame Composer AVI Packet VIC Register, offset: 0x1C */
43812        uint8_t RESERVED_0[8];
43813   __IO uint8_t FC_AUDICONF0;                       /**< Frame Composer AUD Packet Configuration Register 0, offset: 0x25 */
43814   __IO uint8_t FC_AUDICONF1;                       /**< Frame Composer AUD Packet Configuration Register 1, offset: 0x26 */
43815   __IO uint8_t FC_AUDICONF2;                       /**< Frame Composer AUD Packet Configuration Register 2, offset: 0x27 */
43816   __IO uint8_t FC_AUDICONF3;                       /**< Frame Composer AUD Packet Configuration Register 3, offset: 0x28 */
43817   __IO uint8_t FC_VSDIEEEID0;                      /**< Frame Composer VSI Packet Data IEEE Register 0, offset: 0x29 */
43818   __IO uint8_t FC_VSDSIZE;                         /**< Frame Composer VSI Packet Data Size Register, offset: 0x2A */
43819        uint8_t RESERVED_1[5];
43820   __IO uint8_t FC_VSDIEEEID1;                      /**< Frame Composer VSI Packet Data IEEE Register 1, offset: 0x30 */
43821   __IO uint8_t FC_VSDIEEEID2;                      /**< Frame Composer VSI Packet Data IEEE Register 2, offset: 0x31 */
43822        uint8_t RESERVED_2[48];
43823   __IO uint8_t FC_SPDDEVICEINF;                    /**< Frame Composer SPD Packet Data Source Product Descriptor Register, offset: 0x62 */
43824   __IO uint8_t FC_AUDSCONF;                        /**< Frame Composer Audio Sample Flat and Layout Configuration Register, offset: 0x63 */
43825   __I  uint8_t FC_AUDSSTAT;                        /**< Frame Composer Audio Sample Flat and Layout Status Register, offset: 0x64 */
43826   __IO uint8_t FC_AUDSV;                           /**< Frame Composer Audio Sample Validity Flag Register, offset: 0x65 */
43827   __IO uint8_t FC_AUDSU;                           /**< Frame Composer Audio Sample User Flag Register, offset: 0x66 */
43828   __IO uint8_t FC_AUDSCHNL0;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 0, offset: 0x67 */
43829   __IO uint8_t FC_AUDSCHNL1;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 1, offset: 0x68 */
43830   __IO uint8_t FC_AUDSCHNL2;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 2, offset: 0x69 */
43831   __IO uint8_t FC_AUDSCHNL3;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 3, offset: 0x6A */
43832   __IO uint8_t FC_AUDSCHNL4;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 4, offset: 0x6B */
43833   __IO uint8_t FC_AUDSCHNL5;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 5, offset: 0x6C */
43834   __IO uint8_t FC_AUDSCHNL6;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 6, offset: 0x6D */
43835   __IO uint8_t FC_AUDSCHNL7;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 7, offset: 0x6E */
43836   __IO uint8_t FC_AUDSCHNL8;                       /**< Frame Composer Audio Sample Channel Status Configuration Register 8, offset: 0x6F */
43837        uint8_t RESERVED_3[3];
43838   __IO uint8_t FC_CTRLQHIGH;                       /**< Frame Composer Number of High Priority Packets Attended Configuration Register, offset: 0x73 */
43839   __IO uint8_t FC_CTRLQLOW;                        /**< Frame Composer Number of Low Priority Packets Attended Configuration Register, offset: 0x74 */
43840   __IO uint8_t FC_ACP0;                            /**< Frame Composer ACP Packet Type Configuration Register 0, offset: 0x75 */
43841        uint8_t RESERVED_4[12];
43842   __IO uint8_t FC_ACP16;                           /**< Frame Composer ACP Packet Body Configuration Register 16, offset: 0x82 */
43843   __IO uint8_t FC_ACP15;                           /**< Frame Composer ACP Packet Body Configuration Register 15, offset: 0x83 */
43844   __IO uint8_t FC_ACP14;                           /**< Frame Composer ACP Packet Body Configuration Register 14, offset: 0x84 */
43845   __IO uint8_t FC_ACP13;                           /**< Frame Composer ACP Packet Body Configuration Register 13, offset: 0x85 */
43846   __IO uint8_t FC_ACP12;                           /**< Frame Composer ACP Packet Body Configuration Register 12, offset: 0x86 */
43847   __IO uint8_t FC_ACP11;                           /**< Frame Composer ACP Packet Body Configuration Register 11, offset: 0x87 */
43848   __IO uint8_t FC_ACP10;                           /**< Frame Composer ACP Packet Body Configuration Register 10, offset: 0x88 */
43849   __IO uint8_t FC_ACP9;                            /**< Frame Composer ACP Packet Body Configuration Register 9, offset: 0x89 */
43850   __IO uint8_t FC_ACP8;                            /**< Frame Composer ACP Packet Body Configuration Register 8, offset: 0x8A */
43851   __IO uint8_t FC_ACP7;                            /**< Frame Composer ACP Packet Body Configuration Register 7, offset: 0x8B */
43852   __IO uint8_t FC_ACP6;                            /**< Frame Composer ACP Packet Body Configuration Register 6, offset: 0x8C */
43853   __IO uint8_t FC_ACP5;                            /**< Frame Composer ACP Packet Body Configuration Register 5, offset: 0x8D */
43854   __IO uint8_t FC_ACP4;                            /**< Frame Composer ACP Packet Body Configuration Register 4, offset: 0x8E */
43855   __IO uint8_t FC_ACP3;                            /**< Frame Composer ACP Packet Body Configuration Register 3, offset: 0x8F */
43856   __IO uint8_t FC_ACP2;                            /**< Frame Composer ACP Packet Body Configuration Register 2, offset: 0x90 */
43857   __IO uint8_t FC_ACP1;                            /**< Frame Composer ACP Packet Body Configuration Register 1, offset: 0x91 */
43858   __IO uint8_t FC_ISCR1_0;                         /**< Frame Composer ISRC1 Packet Status, Valid, and Continue Configuration Register, offset: 0x92 */
43859   __IO uint8_t FC_ISCR1_16;                        /**< Frame Composer ISRC1 Packet Body Register 16, offset: 0x93 */
43860   __IO uint8_t FC_ISCR1_15;                        /**< Frame Composer ISRC1 Packet Body Register 15, offset: 0x94 */
43861   __IO uint8_t FC_ISCR1_14;                        /**< Frame Composer ISRC1 Packet Body Register 14, offset: 0x95 */
43862   __IO uint8_t FC_ISCR1_13;                        /**< Frame Composer ISRC1 Packet Body Register 13, offset: 0x96 */
43863   __IO uint8_t FC_ISCR1_12;                        /**< Frame Composer ISRC1 Packet Body Register 12, offset: 0x97 */
43864   __IO uint8_t FC_ISCR1_11;                        /**< Frame Composer ISRC1 Packet Body Register 11, offset: 0x98 */
43865   __IO uint8_t FC_ISCR1_10;                        /**< Frame Composer ISRC1 Packet Body Register 10, offset: 0x99 */
43866   __IO uint8_t FC_ISCR1_9;                         /**< Frame Composer ISRC1 Packet Body Register 9, offset: 0x9A */
43867   __IO uint8_t FC_ISCR1_8;                         /**< Frame Composer ISRC1 Packet Body Register 8, offset: 0x9B */
43868   __IO uint8_t FC_ISCR1_7;                         /**< Frame Composer ISRC1 Packet Body Register 7, offset: 0x9C */
43869   __IO uint8_t FC_ISCR1_6;                         /**< Frame Composer ISRC1 Packet Body Register 6, offset: 0x9D */
43870   __IO uint8_t FC_ISCR1_5;                         /**< Frame Composer ISRC1 Packet Body Register 5, offset: 0x9E */
43871   __IO uint8_t FC_ISCR1_4;                         /**< Frame Composer ISRC1 Packet Body Register 4, offset: 0x9F */
43872   __IO uint8_t FC_ISCR1_3;                         /**< Frame Composer ISRC1 Packet Body Register 3, offset: 0xA0 */
43873   __IO uint8_t FC_ISCR1_2;                         /**< Frame Composer ISRC1 Packet Body Register 2, offset: 0xA1 */
43874   __IO uint8_t FC_ISCR1_1;                         /**< Frame Composer ISRC1 Packet Body Register 1, offset: 0xA2 */
43875   __IO uint8_t FC_ISCR2_15;                        /**< Frame Composer ISRC2 Packet Body Register 15, offset: 0xA3 */
43876   __IO uint8_t FC_ISCR2_14;                        /**< Frame Composer ISRC2 Packet Body Register 14, offset: 0xA4 */
43877   __IO uint8_t FC_ISCR2_13;                        /**< Frame Composer ISRC2 Packet Body Register 13, offset: 0xA5 */
43878   __IO uint8_t FC_ISCR2_12;                        /**< Frame Composer ISRC2 Packet Body Register 12, offset: 0xA6 */
43879   __IO uint8_t FC_ISCR2_11;                        /**< Frame Composer ISRC2 Packet Body Register 11, offset: 0xA7 */
43880   __IO uint8_t FC_ISCR2_10;                        /**< Frame Composer ISRC2 Packet Body Register 10, offset: 0xA8 */
43881   __IO uint8_t FC_ISCR2_9;                         /**< Frame Composer ISRC2 Packet Body Register 9, offset: 0xA9 */
43882   __IO uint8_t FC_ISCR2_8;                         /**< Frame Composer ISRC2 Packet Body Register 8, offset: 0xAA */
43883   __IO uint8_t FC_ISCR2_7;                         /**< Frame Composer ISRC2 Packet Body Register 7, offset: 0xAB */
43884   __IO uint8_t FC_ISCR2_6;                         /**< Frame Composer ISRC2 Packet Body Register 6, offset: 0xAC */
43885   __IO uint8_t FC_ISCR2_5;                         /**< Frame Composer ISRC2 Packet Body Register 5, offset: 0xAD */
43886   __IO uint8_t FC_ISCR2_4;                         /**< Frame Composer ISRC2 Packet Body Register 4, offset: 0xAE */
43887   __IO uint8_t FC_ISCR2_3;                         /**< Frame Composer ISRC2 Packet Body Register 3, offset: 0xAF */
43888   __IO uint8_t FC_ISCR2_2;                         /**< Frame Composer ISRC2 Packet Body Register 2, offset: 0xB0 */
43889   __IO uint8_t FC_ISCR2_1;                         /**< Frame Composer ISRC2 Packet Body Register 1, offset: 0xB1 */
43890   __IO uint8_t FC_ISCR2_0;                         /**< Frame Composer ISRC2 Packet Body Register 0, offset: 0xB2 */
43891   __IO uint8_t FC_DATAUTO0;                        /**< Frame Composer Data Island Auto Packet Scheduling Register 0 Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD, VSD, ISRC2, ISRC1 and ACP packets., offset: 0xB3 */
43892   __IO uint8_t FC_DATAUTO1;                        /**< Frame Composer Data Island Auto Packet Scheduling Register 1 Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets., offset: 0xB4 */
43893   __IO uint8_t FC_DATAUTO2;                        /**< Frame Composer Data Island Auto packet scheduling Register 2 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets., offset: 0xB5 */
43894   __O  uint8_t FC_DATMAN;                          /**< Frame Composer Data Island Manual Packet Request Register Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD, ISRC2, ISRC1 and ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested., offset: 0xB6 */
43895   __IO uint8_t FC_DATAUTO3;                        /**< Frame Composer Data Island Auto Packet Scheduling Register 3 Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI, GCP, AUDI and ACR packets., offset: 0xB7 */
43896   __IO uint8_t FC_RDRB0;                           /**< Frame Composer Round Robin ACR Packet Insertion Register 0 Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xB8 */
43897   __IO uint8_t FC_RDRB1;                           /**< Frame Composer Round Robin ACR Packet Insertion Register 1 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the ACR packet insertion on data island when FC is on RDRB mode this packet., offset: 0xB9 */
43898   __IO uint8_t FC_RDRB2;                           /**< Frame Composer Round Robin AUDI Packet Insertion Register 2 Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xBA */
43899   __IO uint8_t FC_RDRB3;                           /**< Frame Composer Round Robin AUDI Packet Insertion Register 3 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AUDI packet insertion on data island when FC is on RDRB mode this packet., offset: 0xBB */
43900   __IO uint8_t FC_RDRB4;                           /**< Frame Composer Round Robin GCP Packet Insertion Register 4 Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xBC */
43901   __IO uint8_t FC_RDRB5;                           /**< Frame Composer Round Robin GCP Packet Insertion Register 5 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the GCP packet insertion on data island when FC is on RDRB mode this packet., offset: 0xBD */
43902   __IO uint8_t FC_RDRB6;                           /**< Frame Composer Round Robin AVI Packet Insertion Register 6 Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xBE */
43903   __IO uint8_t FC_RDRB7;                           /**< Frame Composer Round Robin AVI Packet Insertion Register 7 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AVI packet insertion on data island when FC is on RDRB mode this packet., offset: 0xBF */
43904   __IO uint8_t FC_RDRB8;                           /**< Frame Composer Round Robin AMP Packet Insertion Register 8, offset: 0xC0 */
43905   __IO uint8_t FC_RDRB9;                           /**< Frame Composer Round Robin AMP Packet Insertion Register 9, offset: 0xC1 */
43906   __IO uint8_t FC_RDRB10;                          /**< Frame Composer Round Robin NTSC VBI Packet Insertion Register 10, offset: 0xC2 */
43907   __IO uint8_t FC_RDRB11;                          /**< Frame Composer Round Robin NTSC VBI Packet Insertion Register 11, offset: 0xC3 */
43908   __IO uint8_t FC_RDRB12;                          /**< Frame Composer Round Robin DRM Packet Insertion Register 12, offset: 0xC4 */
43909   __IO uint8_t FC_RDRB13;                          /**< Frame Composer Round Robin DRM Packet Insertion Register 13, offset: 0xC5 */
43910        uint8_t RESERVED_5[12];
43911   __IO uint8_t FC_MASK0;                           /**< Frame Composer Packet Interrupt Mask Register 0, offset: 0xD2 */
43912        uint8_t RESERVED_6[3];
43913   __IO uint8_t FC_MASK1;                           /**< Frame Composer Packet Interrupt Mask Register 1, offset: 0xD6 */
43914        uint8_t RESERVED_7[3];
43915   __IO uint8_t FC_MASK2;                           /**< Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register 2, offset: 0xDA */
43916        uint8_t RESERVED_8[5];
43917   __IO uint8_t FC_PRCONF;                          /**< Frame Composer Pixel Repetition Configuration Register, offset: 0xE0 */
43918   __IO uint8_t FC_SCRAMBLER_CTRL;                  /**< Frame Composer Scrambler Control, offset: 0xE1 */
43919   __IO uint8_t FC_MULTISTREAM_CTRL;                /**< Frame Composer Multi-Stream Audio Control, offset: 0xE2 */
43920   __IO uint8_t FC_PACKET_TX_EN;                    /**< Frame Composer Packet Transmission Control, offset: 0xE3 */
43921        uint8_t RESERVED_9[4];
43922   __IO uint8_t FC_ACTSPC_HDLR_CFG;                 /**< Frame Composer Active Space Control, offset: 0xE8 */
43923   __IO uint8_t FC_INVACT_2D_0;                     /**< Frame Composer Input Video 2D VActive Pixels Register 0, offset: 0xE9 */
43924   __IO uint8_t FC_INVACT_2D_1;                     /**< Frame Composer Input Video VActive pixels Register 1, offset: 0xEA */
43925        uint8_t RESERVED_10[21];
43926   __I  uint8_t FC_GMD_STAT;                        /**< Frame Composer GMD Packet Status Register Gamut metadata packet status bit information for no_current_gmd, next_gmd_field, gmd_packet_sequence and current_gamut_seq_num., offset: 0x100 */
43927   __IO uint8_t FC_GMD_EN;                          /**< Frame Composer GMD Packet Enable Register This register enables Gamut metadata (GMD) packet transmission., offset: 0x101 */
43928   __O  uint8_t FC_GMD_UP;                          /**< Frame Composer GMD Packet Update Register This register performs an GMD packet content update according to the configured packet body (FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB)., offset: 0x102 */
43929   __IO uint8_t FC_GMD_CONF;                        /**< Frame Composer GMD Packet Schedule Configuration Register This register configures the number of GMD packets to be inserted per frame (starting always in the line where the active Vsync appears) and the line spacing between the transmitted GMD packets., offset: 0x103 */
43930   __IO uint8_t FC_GMD_HB;                          /**< Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits., offset: 0x104 */
43931        uint8_t RESERVED_11[35];
43932   __IO uint8_t FC_AMP_HB1;                         /**< Frame Composer AMP Packet Header Register 1, offset: 0x128 */
43933   __IO uint8_t FC_AMP_HB2;                         /**< Frame Composer AMP Packet Header Register 2, offset: 0x129 */
43934        uint8_t RESERVED_12[30];
43935   __IO uint8_t FC_NVBI_HB1;                        /**< Frame Composer NTSC VBI Packet Header Register 1, offset: 0x148 */
43936   __IO uint8_t FC_NVBI_HB2;                        /**< Frame Composer NTSC VBI Packet Header Register 2, offset: 0x149 */
43937        uint8_t RESERVED_13[29];
43938   __O  uint8_t FC_DRM_UP;                          /**< Frame Composer DRM Packet Update Register This register performs an DRM packet content update according to the configured packet body (FC_DRM_PB0 to FC_DRM_PB27) and packet header (FC_DRM_HB)., offset: 0x167 */
43939        uint8_t RESERVED_14[152];
43940   __IO uint8_t FC_DBGFORCE;                        /**< Frame Composer video/audio Force Enable Register This register allows to force the controller to output audio and video data the values configured in the FC_DBGAUD and FC_DBGTMDS registers., offset: 0x200 */
43941   __IO uint8_t FC_DBGAUD0CH0;                      /**< Frame Composer Audio Data Channel 0 Register 0 Configures the audio fixed data to be used in channel 0 when in fixed audio selection., offset: 0x201 */
43942   __IO uint8_t FC_DBGAUD1CH0;                      /**< Frame Composer Audio Data Channel 0 Register 1 Configures the audio fixed data to be used in channel 0 when in fixed audio selection., offset: 0x202 */
43943   __IO uint8_t FC_DBGAUD2CH0;                      /**< Frame Composer Audio Data Channel 0 Register 2 Configures the audio fixed data to be used in channel 0 when in fixed audio selection., offset: 0x203 */
43944   __IO uint8_t FC_DBGAUD0CH1;                      /**< Frame Composer Audio Data Channel 1 Register 0 Configures the audio fixed data to be used in channel 1 when in fixed audio selection., offset: 0x204 */
43945   __IO uint8_t FC_DBGAUD1CH1;                      /**< Frame Composer Audio Data Channel 1 Register 1 Configures the audio fixed data to be used in channel 1 when in fixed audio selection., offset: 0x205 */
43946   __IO uint8_t FC_DBGAUD2CH1;                      /**< Frame Composer Audio Data Channel 1 Register 2 Configures the audio fixed data to be used in channel 1 when in fixed audio selection., offset: 0x206 */
43947   __IO uint8_t FC_DBGAUD0CH2;                      /**< Frame Composer Audio Data Channel 2 Register 0 Configures the audio fixed data to be used in channel 2 when in fixed audio selection., offset: 0x207 */
43948   __IO uint8_t FC_DBGAUD1CH2;                      /**< Frame Composer Audio Data Channel 2 Register 1 Configures the audio fixed data to be used in channel 2 when in fixed audio selection., offset: 0x208 */
43949   __IO uint8_t FC_DBGAUD2CH2;                      /**< Frame Composer Audio Data Channel 2 Register 2 Configures the audio fixed data to be used in channel 2 when in fixed audio selection., offset: 0x209 */
43950   __IO uint8_t FC_DBGAUD0CH3;                      /**< Frame Composer Audio Data Channel 3 Register 0 Configures the audio fixed data to be used in channel 3 when in fixed audio selection., offset: 0x20A */
43951   __IO uint8_t FC_DBGAUD1CH3;                      /**< Frame Composer Audio Data Channel 3 Register 1 Configures the audio fixed data to be used in channel 3 when in fixed audio selection., offset: 0x20B */
43952   __IO uint8_t FC_DBGAUD2CH3;                      /**< Frame Composer Audio Data Channel 3 Register 2 Configures the audio fixed data to be used in channel 3 when in fixed audio selection., offset: 0x20C */
43953   __IO uint8_t FC_DBGAUD0CH4;                      /**< Frame Composer Audio Data Channel 4 Register 0 Configures the audio fixed data to be used in channel 4 when in fixed audio selection., offset: 0x20D */
43954   __IO uint8_t FC_DBGAUD1CH4;                      /**< Frame Composer Audio Data Channel 4 Register 1 Configures the audio fixed data to be used in channel 4 when in fixed audio selection., offset: 0x20E */
43955   __IO uint8_t FC_DBGAUD2CH4;                      /**< Frame Composer Audio Data Channel 4 Register 2 Configures the audio fixed data to be used in channel 4 when in fixed audio selection., offset: 0x20F */
43956   __IO uint8_t FC_DBGAUD0CH5;                      /**< Frame Composer Audio Data Channel 5 Register 0 Configures the audio fixed data to be used in channel 5 when in fixed audio selection., offset: 0x210 */
43957   __IO uint8_t FC_DBGAUD1CH5;                      /**< Frame Composer Audio Data Channel 5 Register 1 Configures the audio fixed data to be used in channel 5 when in fixed audio selection., offset: 0x211 */
43958   __IO uint8_t FC_DBGAUD2CH5;                      /**< Frame Composer Audio Data Channel 5 Register 2 Configures the audio fixed data to be used in channel 5 when in fixed audio selection., offset: 0x212 */
43959   __IO uint8_t FC_DBGAUD0CH6;                      /**< Frame Composer Audio Data Channel 6 Register 0 Configures the audio fixed data to be used in channel 6 when in fixed audio selection., offset: 0x213 */
43960   __IO uint8_t FC_DBGAUD1CH6;                      /**< Frame Composer Audio Data Channel 6 Register 1 Configures the audio fixed data to be used in channel 6 when in fixed audio selection., offset: 0x214 */
43961   __IO uint8_t FC_DBGAUD2CH6;                      /**< Frame Composer Audio Data Channel 6 Register 2 Configures the audio fixed data to be used in channel 6 when in fixed audio selection., offset: 0x215 */
43962   __IO uint8_t FC_DBGAUD0CH7;                      /**< Frame Composer Audio Data Channel 7 Register 0 Configures the audio fixed data to be used in channel 7 when in fixed audio selection., offset: 0x216 */
43963   __IO uint8_t FC_DBGAUD1CH7;                      /**< Frame Composer Audio Data Channel 7 Register 1 Configures the audio fixed data to be used in channel 7 when in fixed audio selection., offset: 0x217 */
43964   __IO uint8_t FC_DBGAUD2CH7;                      /**< Frame Composer Audio Data Channel 7 Register 2 Configures the audio fixed data to be used in channel 7 when in fixed audio selection., offset: 0x218 */
43965 } FRAMECOMPOSER_Type;
43966 
43967 /* ----------------------------------------------------------------------------
43968    -- FRAMECOMPOSER Register Masks
43969    ---------------------------------------------------------------------------- */
43970 
43971 /*!
43972  * @addtogroup FRAMECOMPOSER_Register_Masks FRAMECOMPOSER Register Masks
43973  * @{
43974  */
43975 
43976 /*! @name FC_INVIDCONF - Frame Composer Input Video Configuration and HDCP Keepout Register */
43977 /*! @{ */
43978 
43979 #define FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_MASK   (0x1U)
43980 #define FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_SHIFT  (0U)
43981 /*! in_I_P - Input video mode: 1b: Interlaced 0b: Progressive */
43982 #define FRAMECOMPOSER_FC_INVIDCONF_IN_I_P(x)     (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_MASK)
43983 
43984 #define FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK (0x2U)
43985 #define FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_SHIFT (1U)
43986 /*! r_v_blank_in_osc - Used for CEA861-D modes with fractional Vblank (for example, modes 5, 6, 7, 10, 11, 20, 21, and 22). */
43987 #define FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK)
43988 
43989 #define FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_MASK (0x8U)
43990 #define FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_SHIFT (3U)
43991 /*! DVI_modez - Active low 0b: DVI mode selected 1b: HDMI mode selected */
43992 #define FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_MASK)
43993 
43994 #define FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_MASK (0x10U)
43995 #define FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_SHIFT (4U)
43996 /*! de_in_polarity - Data enable input polarity 1b: Active high 0b: Active low */
43997 #define FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_MASK)
43998 
43999 #define FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK (0x20U)
44000 #define FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_SHIFT (5U)
44001 /*! hsync_in_polarity - Hsync input polarity 1b: Active high 0b: Active low */
44002 #define FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK)
44003 
44004 #define FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK (0x40U)
44005 #define FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_SHIFT (6U)
44006 /*! vsync_in_polarity - Vsync input polarity 1b: Active high 0b: Active low */
44007 #define FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK)
44008 
44009 #define FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_MASK (0x80U)
44010 #define FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_SHIFT (7U)
44011 /*! HDCP_keepout - Start/stop HDCP keepout window generation 1b: Active */
44012 #define FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_MASK)
44013 /*! @} */
44014 
44015 /*! @name FC_INHACTIV0 - Frame Composer Input Video HActive Pixels Register 0 */
44016 /*! @{ */
44017 
44018 #define FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_MASK (0xFFU)
44019 #define FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_SHIFT (0U)
44020 /*! H_in_activ - Input video Horizontal active pixel region width. */
44021 #define FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_MASK)
44022 /*! @} */
44023 
44024 /*! @name FC_INHACTIV1 - Frame Composer Input Video HActive Pixels Register 1 */
44025 /*! @{ */
44026 
44027 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_MASK (0xFU)
44028 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_SHIFT (0U)
44029 /*! H_in_activ - Input video Horizontal active pixel region width */
44030 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_MASK)
44031 
44032 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_MASK (0x10U)
44033 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_SHIFT (4U)
44034 /*! H_in_activ_12 - Input video Horizontal active pixel region width (0 . */
44035 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_MASK)
44036 
44037 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_MASK (0x20U)
44038 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_SHIFT (5U)
44039 /*! H_in_activ_13 - Input video Horizontal active pixel region width (0 . */
44040 #define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_MASK)
44041 /*! @} */
44042 
44043 /*! @name FC_INHBLANK0 - Frame Composer Input Video HBlank Pixels Register 0 */
44044 /*! @{ */
44045 
44046 #define FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_MASK (0xFFU)
44047 #define FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_SHIFT (0U)
44048 /*! H_in_blank - Input video Horizontal blanking pixel region width. */
44049 #define FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_SHIFT)) & FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_MASK)
44050 /*! @} */
44051 
44052 /*! @name FC_INHBLANK1 - Frame Composer Input Video HBlank Pixels Register 1 */
44053 /*! @{ */
44054 
44055 #define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_MASK (0x3U)
44056 #define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_SHIFT (0U)
44057 /*! H_in_blank - Input video Horizontal blanking pixel region width this bit field holds bits 9:8 of
44058  *    number of Horizontal blanking pixels.
44059  */
44060 #define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_SHIFT)) & FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_MASK)
44061 
44062 #define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_MASK (0x1CU)
44063 #define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_SHIFT (2U)
44064 /*! H_in_blank_12 - Input video Horizontal blanking pixel region width If configuration parameter
44065  *    DWC_HDMI_TX_14 = True (1), this bit field holds bit 12:10 of number of horizontal blanking
44066  *    pixels.
44067  */
44068 #define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_SHIFT)) & FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_MASK)
44069 /*! @} */
44070 
44071 /*! @name FC_INVACTIV0 - Frame Composer Input Video VActive Pixels Register 0 */
44072 /*! @{ */
44073 
44074 #define FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_MASK (0xFFU)
44075 #define FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_SHIFT (0U)
44076 /*! V_in_activ - Input video Vertical active pixel region width. */
44077 #define FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_MASK)
44078 /*! @} */
44079 
44080 /*! @name FC_INVACTIV1 - Frame Composer Input Video VActive Pixels Register 1 */
44081 /*! @{ */
44082 
44083 #define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_MASK (0x7U)
44084 #define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_SHIFT (0U)
44085 /*! V_in_activ - Input video Vertical active pixel region width. */
44086 #define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_MASK)
44087 
44088 #define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_MASK (0x18U)
44089 #define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_SHIFT (3U)
44090 /*! V_in_activ_12_11 - Input video Vertical active pixel region width. */
44091 #define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_SHIFT)) & FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_MASK)
44092 /*! @} */
44093 
44094 /*! @name FC_INVBLANK - Frame Composer Input Video VBlank Pixels Register */
44095 /*! @{ */
44096 
44097 #define FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_MASK (0xFFU)
44098 #define FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_SHIFT (0U)
44099 /*! V_in_blank - Input video Vertical blanking pixel region width. */
44100 #define FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_SHIFT)) & FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_MASK)
44101 /*! @} */
44102 
44103 /*! @name FC_HSYNCINDELAY0 - Frame Composer Input Video HSync Front Porch Register 0 */
44104 /*! @{ */
44105 
44106 #define FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_MASK (0xFFU)
44107 #define FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_SHIFT (0U)
44108 /*! H_in_delay - Input video Hsync active edge delay. */
44109 #define FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_MASK)
44110 /*! @} */
44111 
44112 /*! @name FC_HSYNCINDELAY1 - Frame Composer Input Video HSync Front Porch Register 1 */
44113 /*! @{ */
44114 
44115 #define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_MASK (0x7U)
44116 #define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_SHIFT (0U)
44117 /*! H_in_delay - Input video Horizontal active edge delay. */
44118 #define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_MASK)
44119 
44120 #define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_MASK (0x18U)
44121 #define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_SHIFT (3U)
44122 /*! H_in_delay_12 - Input video Horizontal active edge delay. */
44123 #define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_MASK)
44124 /*! @} */
44125 
44126 /*! @name FC_HSYNCINWIDTH0 - Frame Composer Input Video HSync Width Register 0 */
44127 /*! @{ */
44128 
44129 #define FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_MASK (0xFFU)
44130 #define FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_SHIFT (0U)
44131 /*! H_in_width - Input video Hsync active pulse width. */
44132 #define FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_MASK)
44133 /*! @} */
44134 
44135 /*! @name FC_HSYNCINWIDTH1 - Frame Composer Input Video HSync Width Register 1 */
44136 /*! @{ */
44137 
44138 #define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_MASK (0x1U)
44139 #define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_SHIFT (0U)
44140 /*! H_in_width - Input video Hsync active pulse width. */
44141 #define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_MASK)
44142 
44143 #define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_MASK (0x2U)
44144 #define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_SHIFT (1U)
44145 /*! H_in_width_9 - Input video Hsync active pulse width. */
44146 #define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_MASK)
44147 /*! @} */
44148 
44149 /*! @name FC_VSYNCINDELAY - Frame Composer Input Video VSync Front Porch Register */
44150 /*! @{ */
44151 
44152 #define FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_MASK (0xFFU)
44153 #define FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_SHIFT (0U)
44154 /*! V_in_delay - Input video Vsync active edge delay. */
44155 #define FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_SHIFT)) & FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_MASK)
44156 /*! @} */
44157 
44158 /*! @name FC_VSYNCINWIDTH - Frame Composer Input Video VSync Width Register */
44159 /*! @{ */
44160 
44161 #define FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_MASK (0x3FU)
44162 #define FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_SHIFT (0U)
44163 /*! V_in_width - Input video Vsync active pulse width. */
44164 #define FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_SHIFT)) & FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_MASK)
44165 /*! @} */
44166 
44167 /*! @name FC_INFREQ0 - Frame Composer Input Video Refresh Rate Register 0 */
44168 /*! @{ */
44169 
44170 #define FRAMECOMPOSER_FC_INFREQ0_INFREQ_MASK     (0xFFU)
44171 #define FRAMECOMPOSER_FC_INFREQ0_INFREQ_SHIFT    (0U)
44172 /*! infreq - Video refresh rate in Hz*1E3 format. */
44173 #define FRAMECOMPOSER_FC_INFREQ0_INFREQ(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INFREQ0_INFREQ_SHIFT)) & FRAMECOMPOSER_FC_INFREQ0_INFREQ_MASK)
44174 /*! @} */
44175 
44176 /*! @name FC_INFREQ1 - Frame Composer Input Video Refresh Rate Register 1 */
44177 /*! @{ */
44178 
44179 #define FRAMECOMPOSER_FC_INFREQ1_INFREQ_MASK     (0xFFU)
44180 #define FRAMECOMPOSER_FC_INFREQ1_INFREQ_SHIFT    (0U)
44181 /*! infreq - Video refresh rate in Hz*1E3 format. */
44182 #define FRAMECOMPOSER_FC_INFREQ1_INFREQ(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INFREQ1_INFREQ_SHIFT)) & FRAMECOMPOSER_FC_INFREQ1_INFREQ_MASK)
44183 /*! @} */
44184 
44185 /*! @name FC_INFREQ2 - Frame Composer Input Video Refresh Rate Register 2 */
44186 /*! @{ */
44187 
44188 #define FRAMECOMPOSER_FC_INFREQ2_INFREQ_MASK     (0xFU)
44189 #define FRAMECOMPOSER_FC_INFREQ2_INFREQ_SHIFT    (0U)
44190 /*! infreq - Video refresh rate in Hz*1E3 format. */
44191 #define FRAMECOMPOSER_FC_INFREQ2_INFREQ(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INFREQ2_INFREQ_SHIFT)) & FRAMECOMPOSER_FC_INFREQ2_INFREQ_MASK)
44192 /*! @} */
44193 
44194 /*! @name FC_CTRLDUR - Frame Composer Control Period Duration Register */
44195 /*! @{ */
44196 
44197 #define FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_MASK (0xFFU)
44198 #define FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_SHIFT (0U)
44199 /*! ctrlperiodduration - Configuration of the control period minimum duration (minimum of 12 pixel clock cycles; refer to HDMI 1. */
44200 #define FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_SHIFT)) & FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_MASK)
44201 /*! @} */
44202 
44203 /*! @name FC_EXCTRLDUR - Frame Composer Extended Control Period Duration Register */
44204 /*! @{ */
44205 
44206 #define FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_MASK (0xFFU)
44207 #define FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_SHIFT (0U)
44208 /*! exctrlperiodduration - Configuration of the extended control period minimum duration (minimum of 32 pixel clock cycles; refer to HDMI 1. */
44209 #define FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_SHIFT)) & FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_MASK)
44210 /*! @} */
44211 
44212 /*! @name FC_EXCTRLSPAC - Frame Composer Extended Control Period Maximum Spacing Register */
44213 /*! @{ */
44214 
44215 #define FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_MASK (0xFFU)
44216 #define FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_SHIFT (0U)
44217 /*! exctrlperiodspacing - Configuration of the maximum spacing between consecutive extended control
44218  *    periods (maximum of 50ms; refer to the applicable HDMI specification).
44219  */
44220 #define FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_SHIFT)) & FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_MASK)
44221 /*! @} */
44222 
44223 /*! @name FC_CH0PREAM - Frame Composer Channel 0 Non-Preamble Data Register */
44224 /*! @{ */
44225 
44226 #define FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_MASK (0xFFU)
44227 #define FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_SHIFT (0U)
44228 /*! ch0_preamble_filter - When in control mode, configures 8 bits that fill the channel 0 data lines
44229  *    not used to transmit the preamble (for more clarification, refer to the HDMI 1.
44230  */
44231 #define FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_SHIFT)) & FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_MASK)
44232 /*! @} */
44233 
44234 /*! @name FC_CH1PREAM - Frame Composer Channel 1 Non-Preamble Data Register */
44235 /*! @{ */
44236 
44237 #define FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_MASK (0x3FU)
44238 #define FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_SHIFT (0U)
44239 /*! ch1_preamble_filter - When in control mode, configures 6 bits that fill the channel 1 data lines
44240  *    not used to transmit the preamble (for more clarification, refer to the HDMI 1.
44241  */
44242 #define FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_SHIFT)) & FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_MASK)
44243 /*! @} */
44244 
44245 /*! @name FC_CH2PREAM - Frame Composer Channel 2 Non-Preamble Data Register */
44246 /*! @{ */
44247 
44248 #define FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_MASK (0x3FU)
44249 #define FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_SHIFT (0U)
44250 /*! ch2_preamble_filter - When in control mode, configures 6 bits that fill the channel 2 data lines
44251  *    not used to transmit the preamble (for more clarification, refer to the HDMI 1.
44252  */
44253 #define FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_SHIFT)) & FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_MASK)
44254 /*! @} */
44255 
44256 /*! @name FC_AVICONF3 - Frame Composer AVI Packet Configuration Register 3 */
44257 /*! @{ */
44258 
44259 #define FRAMECOMPOSER_FC_AVICONF3_CN_MASK        (0x3U)
44260 #define FRAMECOMPOSER_FC_AVICONF3_CN_SHIFT       (0U)
44261 /*! CN - IT content type according to CEA the specification */
44262 #define FRAMECOMPOSER_FC_AVICONF3_CN(x)          (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF3_CN_SHIFT)) & FRAMECOMPOSER_FC_AVICONF3_CN_MASK)
44263 
44264 #define FRAMECOMPOSER_FC_AVICONF3_YQ_MASK        (0xCU)
44265 #define FRAMECOMPOSER_FC_AVICONF3_YQ_SHIFT       (2U)
44266 /*! YQ - YCbCr Quantization range according to the CEA specification */
44267 #define FRAMECOMPOSER_FC_AVICONF3_YQ(x)          (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF3_YQ_SHIFT)) & FRAMECOMPOSER_FC_AVICONF3_YQ_MASK)
44268 /*! @} */
44269 
44270 /*! @name FC_GCP - Frame Composer GCP Packet Configuration Register */
44271 /*! @{ */
44272 
44273 #define FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_MASK   (0x1U)
44274 #define FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_SHIFT  (0U)
44275 /*! clear_avmute - Value of "clear_avmute" in the GCP packet */
44276 #define FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE(x)     (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_SHIFT)) & FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_MASK)
44277 
44278 #define FRAMECOMPOSER_FC_GCP_SET_AVMUTE_MASK     (0x2U)
44279 #define FRAMECOMPOSER_FC_GCP_SET_AVMUTE_SHIFT    (1U)
44280 /*! set_avmute - Value of "set_avmute" in the GCP packet Once the AVmute is set, the frame composer
44281  *    schedules the GCP packet with AVmute set in the packet scheduler to be sent once (may only be
44282  *    transmitted between the active edge of VSYNC and 384 pixels following this edge).
44283  */
44284 #define FRAMECOMPOSER_FC_GCP_SET_AVMUTE(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GCP_SET_AVMUTE_SHIFT)) & FRAMECOMPOSER_FC_GCP_SET_AVMUTE_MASK)
44285 
44286 #define FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_MASK  (0x4U)
44287 #define FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_SHIFT (2U)
44288 /*! default_phase - Value of "default_phase" in the GCP packet. */
44289 #define FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_SHIFT)) & FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_MASK)
44290 /*! @} */
44291 
44292 /*! @name FC_AVICONF0 - Frame Composer AVI Packet Configuration Register 0 */
44293 /*! @{ */
44294 
44295 #define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_MASK (0x3U)
44296 #define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_SHIFT (0U)
44297 /*! rgc_ycc_indication - Y1,Y0 RGB or YCbCr indicator */
44298 #define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_MASK)
44299 
44300 #define FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_MASK (0xCU)
44301 #define FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_SHIFT (2U)
44302 /*! bar_information - Bar information data valid */
44303 #define FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_MASK)
44304 
44305 #define FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_MASK (0x30U)
44306 #define FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_SHIFT (4U)
44307 /*! scan_information - Scan information */
44308 #define FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_MASK)
44309 
44310 #define FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_MASK (0x40U)
44311 #define FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_SHIFT (6U)
44312 /*! active_format_present - Active format present */
44313 #define FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_MASK)
44314 
44315 #define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_MASK (0x80U)
44316 #define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_SHIFT (7U)
44317 /*! rgc_ycc_indication_2 - Y2, Bit 2 of rgc_ycc_indication */
44318 #define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_MASK)
44319 /*! @} */
44320 
44321 /*! @name FC_AVICONF1 - Frame Composer AVI Packet Configuration Register 1 */
44322 /*! @{ */
44323 
44324 #define FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK (0xFU)
44325 #define FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_SHIFT (0U)
44326 /*! active_aspect_ratio - Active aspect ratio */
44327 #define FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_SHIFT)) & FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK)
44328 
44329 #define FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_MASK (0x30U)
44330 #define FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_SHIFT (4U)
44331 /*! picture_aspect_ratio - Picture aspect ratio */
44332 #define FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_SHIFT)) & FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_MASK)
44333 
44334 #define FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_MASK (0xC0U)
44335 #define FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_SHIFT (6U)
44336 /*! Colorimetry - Colorimetry */
44337 #define FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_SHIFT)) & FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_MASK)
44338 /*! @} */
44339 
44340 /*! @name FC_AVICONF2 - Frame Composer AVI Packet Configuration Register 2 */
44341 /*! @{ */
44342 
44343 #define FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_MASK (0x3U)
44344 #define FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_SHIFT (0U)
44345 /*! non_uniform_picture_scaling - Non-uniform picture scaling */
44346 #define FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_MASK)
44347 
44348 #define FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_MASK (0xCU)
44349 #define FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_SHIFT (2U)
44350 /*! quantization_range - Quantization range */
44351 #define FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_MASK)
44352 
44353 #define FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_MASK (0x70U)
44354 #define FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_SHIFT (4U)
44355 /*! extended_colorimetry - Extended colorimetry */
44356 #define FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_MASK)
44357 
44358 #define FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_MASK (0x80U)
44359 #define FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_SHIFT (7U)
44360 /*! it_content - IT content */
44361 #define FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_MASK)
44362 /*! @} */
44363 
44364 /*! @name FC_AVIVID - Frame Composer AVI Packet VIC Register */
44365 /*! @{ */
44366 
44367 #define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_MASK   (0x7FU)
44368 #define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_SHIFT  (0U)
44369 /*! fc_avivid - Configures the AVI InfoFrame Video Identification code. */
44370 #define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID(x)     (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_SHIFT)) & FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_MASK)
44371 
44372 #define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_MASK (0x80U)
44373 #define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_SHIFT (7U)
44374 /*! fc_avivid_7 - Bit 7 of fc_avivid register */
44375 #define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_SHIFT)) & FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_MASK)
44376 /*! @} */
44377 
44378 /*! @name FC_AUDICONF0 - Frame Composer AUD Packet Configuration Register 0 */
44379 /*! @{ */
44380 
44381 #define FRAMECOMPOSER_FC_AUDICONF0_CT_MASK       (0xFU)
44382 #define FRAMECOMPOSER_FC_AUDICONF0_CT_SHIFT      (0U)
44383 /*! CT - Coding Type */
44384 #define FRAMECOMPOSER_FC_AUDICONF0_CT(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF0_CT_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF0_CT_MASK)
44385 
44386 #define FRAMECOMPOSER_FC_AUDICONF0_CC_MASK       (0x70U)
44387 #define FRAMECOMPOSER_FC_AUDICONF0_CC_SHIFT      (4U)
44388 /*! CC - Channel count */
44389 #define FRAMECOMPOSER_FC_AUDICONF0_CC(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF0_CC_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF0_CC_MASK)
44390 /*! @} */
44391 
44392 /*! @name FC_AUDICONF1 - Frame Composer AUD Packet Configuration Register 1 */
44393 /*! @{ */
44394 
44395 #define FRAMECOMPOSER_FC_AUDICONF1_SF_MASK       (0x7U)
44396 #define FRAMECOMPOSER_FC_AUDICONF1_SF_SHIFT      (0U)
44397 /*! SF - Sampling frequency */
44398 #define FRAMECOMPOSER_FC_AUDICONF1_SF(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF1_SF_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF1_SF_MASK)
44399 
44400 #define FRAMECOMPOSER_FC_AUDICONF1_SS_MASK       (0x30U)
44401 #define FRAMECOMPOSER_FC_AUDICONF1_SS_SHIFT      (4U)
44402 /*! SS - Sampling size */
44403 #define FRAMECOMPOSER_FC_AUDICONF1_SS(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF1_SS_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF1_SS_MASK)
44404 /*! @} */
44405 
44406 /*! @name FC_AUDICONF2 - Frame Composer AUD Packet Configuration Register 2 */
44407 /*! @{ */
44408 
44409 #define FRAMECOMPOSER_FC_AUDICONF2_CA_MASK       (0xFFU)
44410 #define FRAMECOMPOSER_FC_AUDICONF2_CA_SHIFT      (0U)
44411 /*! CA - Channel allocation */
44412 #define FRAMECOMPOSER_FC_AUDICONF2_CA(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF2_CA_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF2_CA_MASK)
44413 /*! @} */
44414 
44415 /*! @name FC_AUDICONF3 - Frame Composer AUD Packet Configuration Register 3 */
44416 /*! @{ */
44417 
44418 #define FRAMECOMPOSER_FC_AUDICONF3_LSV_MASK      (0xFU)
44419 #define FRAMECOMPOSER_FC_AUDICONF3_LSV_SHIFT     (0U)
44420 /*! LSV - Level shift value (for down mixing) */
44421 #define FRAMECOMPOSER_FC_AUDICONF3_LSV(x)        (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF3_LSV_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF3_LSV_MASK)
44422 
44423 #define FRAMECOMPOSER_FC_AUDICONF3_DM_INH_MASK   (0x10U)
44424 #define FRAMECOMPOSER_FC_AUDICONF3_DM_INH_SHIFT  (4U)
44425 /*! DM_INH - Down mix enable */
44426 #define FRAMECOMPOSER_FC_AUDICONF3_DM_INH(x)     (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF3_DM_INH_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF3_DM_INH_MASK)
44427 
44428 #define FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_MASK   (0x60U)
44429 #define FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_SHIFT  (5U)
44430 /*! LFEPBL - LFE playback information LFEPBL1, LFEPBL0 LFE playback level as compared to the other channels. */
44431 #define FRAMECOMPOSER_FC_AUDICONF3_LFEPBL(x)     (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_MASK)
44432 /*! @} */
44433 
44434 /*! @name FC_VSDIEEEID0 - Frame Composer VSI Packet Data IEEE Register 0 */
44435 /*! @{ */
44436 
44437 #define FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_MASK    (0xFFU)
44438 #define FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_SHIFT   (0U)
44439 /*! IEEE - This register configures the Vendor Specific InfoFrame IEEE registration identifier. */
44440 #define FRAMECOMPOSER_FC_VSDIEEEID0_IEEE(x)      (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_SHIFT)) & FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_MASK)
44441 /*! @} */
44442 
44443 /*! @name FC_VSDSIZE - Frame Composer VSI Packet Data Size Register */
44444 /*! @{ */
44445 
44446 #define FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_MASK    (0x1FU)
44447 #define FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_SHIFT   (0U)
44448 /*! VSDSIZE - Packet size as described in the HDMI Vendor Specific InfoFrame (from the HDMI specification). */
44449 #define FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE(x)      (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_SHIFT)) & FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_MASK)
44450 /*! @} */
44451 
44452 /*! @name FC_VSDIEEEID1 - Frame Composer VSI Packet Data IEEE Register 1 */
44453 /*! @{ */
44454 
44455 #define FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_MASK    (0xFFU)
44456 #define FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_SHIFT   (0U)
44457 /*! IEEE - This register configures the Vendor Specific InfoFrame IEEE registration identifier. */
44458 #define FRAMECOMPOSER_FC_VSDIEEEID1_IEEE(x)      (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_SHIFT)) & FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_MASK)
44459 /*! @} */
44460 
44461 /*! @name FC_VSDIEEEID2 - Frame Composer VSI Packet Data IEEE Register 2 */
44462 /*! @{ */
44463 
44464 #define FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_MASK    (0xFFU)
44465 #define FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_SHIFT   (0U)
44466 /*! IEEE - This register configures the Vendor Specific InfoFrame IEEE registration identifier. */
44467 #define FRAMECOMPOSER_FC_VSDIEEEID2_IEEE(x)      (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_SHIFT)) & FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_MASK)
44468 /*! @} */
44469 
44470 /*! @name FC_SPDDEVICEINF - Frame Composer SPD Packet Data Source Product Descriptor Register */
44471 /*! @{ */
44472 
44473 #define FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_MASK (0xFFU)
44474 #define FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_SHIFT (0U)
44475 /*! fc_spddeviceinf - Frame Composer SPD Packet Data Source Product Descriptor Register */
44476 #define FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_SHIFT)) & FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_MASK)
44477 /*! @} */
44478 
44479 /*! @name FC_AUDSCONF - Frame Composer Audio Sample Flat and Layout Configuration Register */
44480 /*! @{ */
44481 
44482 #define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK (0x1U)
44483 #define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_SHIFT (0U)
44484 /*! aud_packet_layout - Set the audio packet layout to be sent in the packet: 1b: layout 1 0b:
44485  *    layout 0 If DWC_HDMI_TX_20 is defined and register field fc_multistream_ctrl.
44486  */
44487 #define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK)
44488 
44489 #define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_MASK (0xF0U)
44490 #define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_SHIFT (4U)
44491 /*! aud_packet_sampflt - Set the audio packet sample flat value to be sent on the packet. */
44492 #define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_MASK)
44493 /*! @} */
44494 
44495 /*! @name FC_AUDSSTAT - Frame Composer Audio Sample Flat and Layout Status Register */
44496 /*! @{ */
44497 
44498 #define FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_MASK (0xFU)
44499 #define FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_SHIFT (0U)
44500 /*! packet_sampprs - Shows the data sample present indication of the last Audio sample packet sent by the HDMI TX Controller. */
44501 #define FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_SHIFT)) & FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_MASK)
44502 /*! @} */
44503 
44504 /*! @name FC_AUDSV - Frame Composer Audio Sample Validity Flag Register */
44505 /*! @{ */
44506 
44507 #define FRAMECOMPOSER_FC_AUDSV_V0L_MASK          (0x1U)
44508 #define FRAMECOMPOSER_FC_AUDSV_V0L_SHIFT         (0U)
44509 /*! V0l - Set validity bit "V" for Channel 0, Left */
44510 #define FRAMECOMPOSER_FC_AUDSV_V0L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V0L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V0L_MASK)
44511 
44512 #define FRAMECOMPOSER_FC_AUDSV_V1L_MASK          (0x2U)
44513 #define FRAMECOMPOSER_FC_AUDSV_V1L_SHIFT         (1U)
44514 /*! V1l - Set validity bit "V" for Channel 1, Left */
44515 #define FRAMECOMPOSER_FC_AUDSV_V1L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V1L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V1L_MASK)
44516 
44517 #define FRAMECOMPOSER_FC_AUDSV_V2L_MASK          (0x4U)
44518 #define FRAMECOMPOSER_FC_AUDSV_V2L_SHIFT         (2U)
44519 /*! V2l - Set validity bit "V" for Channel 2, Left */
44520 #define FRAMECOMPOSER_FC_AUDSV_V2L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V2L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V2L_MASK)
44521 
44522 #define FRAMECOMPOSER_FC_AUDSV_V3L_MASK          (0x8U)
44523 #define FRAMECOMPOSER_FC_AUDSV_V3L_SHIFT         (3U)
44524 /*! V3l - Set validity bit "V" for Channel 3, Left */
44525 #define FRAMECOMPOSER_FC_AUDSV_V3L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V3L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V3L_MASK)
44526 
44527 #define FRAMECOMPOSER_FC_AUDSV_V0R_MASK          (0x10U)
44528 #define FRAMECOMPOSER_FC_AUDSV_V0R_SHIFT         (4U)
44529 /*! V0r - Set validity bit "V" for Channel 0, Right */
44530 #define FRAMECOMPOSER_FC_AUDSV_V0R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V0R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V0R_MASK)
44531 
44532 #define FRAMECOMPOSER_FC_AUDSV_V1R_MASK          (0x20U)
44533 #define FRAMECOMPOSER_FC_AUDSV_V1R_SHIFT         (5U)
44534 /*! V1r - Set validity bit "V" for Channel 1, Right */
44535 #define FRAMECOMPOSER_FC_AUDSV_V1R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V1R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V1R_MASK)
44536 
44537 #define FRAMECOMPOSER_FC_AUDSV_V2R_MASK          (0x40U)
44538 #define FRAMECOMPOSER_FC_AUDSV_V2R_SHIFT         (6U)
44539 /*! V2r - Set validity bit "V" for Channel 2, Right */
44540 #define FRAMECOMPOSER_FC_AUDSV_V2R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V2R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V2R_MASK)
44541 
44542 #define FRAMECOMPOSER_FC_AUDSV_V3R_MASK          (0x80U)
44543 #define FRAMECOMPOSER_FC_AUDSV_V3R_SHIFT         (7U)
44544 /*! V3r - Set validity bit "V" for Channel 3, Right */
44545 #define FRAMECOMPOSER_FC_AUDSV_V3R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V3R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V3R_MASK)
44546 /*! @} */
44547 
44548 /*! @name FC_AUDSU - Frame Composer Audio Sample User Flag Register */
44549 /*! @{ */
44550 
44551 #define FRAMECOMPOSER_FC_AUDSU_U0L_MASK          (0x1U)
44552 #define FRAMECOMPOSER_FC_AUDSU_U0L_SHIFT         (0U)
44553 /*! U0l - Set user bit "U" for Channel 0, Left */
44554 #define FRAMECOMPOSER_FC_AUDSU_U0L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U0L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U0L_MASK)
44555 
44556 #define FRAMECOMPOSER_FC_AUDSU_U1L_MASK          (0x2U)
44557 #define FRAMECOMPOSER_FC_AUDSU_U1L_SHIFT         (1U)
44558 /*! U1l - Set user bit "U" for Channel 1, Left */
44559 #define FRAMECOMPOSER_FC_AUDSU_U1L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U1L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U1L_MASK)
44560 
44561 #define FRAMECOMPOSER_FC_AUDSU_U2L_MASK          (0x4U)
44562 #define FRAMECOMPOSER_FC_AUDSU_U2L_SHIFT         (2U)
44563 /*! U2l - Set user bit "U" for Channel 2, Left */
44564 #define FRAMECOMPOSER_FC_AUDSU_U2L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U2L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U2L_MASK)
44565 
44566 #define FRAMECOMPOSER_FC_AUDSU_U3L_MASK          (0x8U)
44567 #define FRAMECOMPOSER_FC_AUDSU_U3L_SHIFT         (3U)
44568 /*! U3l - Set user bit "U" for Channel 3, Left */
44569 #define FRAMECOMPOSER_FC_AUDSU_U3L(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U3L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U3L_MASK)
44570 
44571 #define FRAMECOMPOSER_FC_AUDSU_U0R_MASK          (0x10U)
44572 #define FRAMECOMPOSER_FC_AUDSU_U0R_SHIFT         (4U)
44573 /*! U0r - Set user bit "U" for Channel 0, Right */
44574 #define FRAMECOMPOSER_FC_AUDSU_U0R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U0R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U0R_MASK)
44575 
44576 #define FRAMECOMPOSER_FC_AUDSU_U1R_MASK          (0x20U)
44577 #define FRAMECOMPOSER_FC_AUDSU_U1R_SHIFT         (5U)
44578 /*! U1r - Set user bit "U" for Channel 1, Right */
44579 #define FRAMECOMPOSER_FC_AUDSU_U1R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U1R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U1R_MASK)
44580 
44581 #define FRAMECOMPOSER_FC_AUDSU_U2R_MASK          (0x40U)
44582 #define FRAMECOMPOSER_FC_AUDSU_U2R_SHIFT         (6U)
44583 /*! U2r - Set user bit "U" for Channel 2, Right */
44584 #define FRAMECOMPOSER_FC_AUDSU_U2R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U2R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U2R_MASK)
44585 
44586 #define FRAMECOMPOSER_FC_AUDSU_U3R_MASK          (0x80U)
44587 #define FRAMECOMPOSER_FC_AUDSU_U3R_SHIFT         (7U)
44588 /*! U3r - Set user bit "U" for Channel 3, Right */
44589 #define FRAMECOMPOSER_FC_AUDSU_U3R(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U3R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U3R_MASK)
44590 /*! @} */
44591 
44592 /*! @name FC_AUDSCHNL0 - Frame Composer Audio Sample Channel Status Configuration Register 0 */
44593 /*! @{ */
44594 
44595 #define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_MASK (0x1U)
44596 #define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_SHIFT (0U)
44597 /*! oiec_copyright - IEC Copyright indication */
44598 #define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_MASK)
44599 
44600 #define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_MASK (0x30U)
44601 #define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_SHIFT (4U)
44602 /*! oiec_cgmsa - CGMS-A */
44603 #define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_MASK)
44604 /*! @} */
44605 
44606 /*! @name FC_AUDSCHNL1 - Frame Composer Audio Sample Channel Status Configuration Register 1 */
44607 /*! @{ */
44608 
44609 #define FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_MASK (0xFFU)
44610 #define FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_SHIFT (0U)
44611 /*! oiec_categorycode - Category code */
44612 #define FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_MASK)
44613 /*! @} */
44614 
44615 /*! @name FC_AUDSCHNL2 - Frame Composer Audio Sample Channel Status Configuration Register 2 */
44616 /*! @{ */
44617 
44618 #define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_MASK (0xFU)
44619 #define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_SHIFT (0U)
44620 /*! oiec_sourcenumber - Source number */
44621 #define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_MASK)
44622 
44623 #define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_MASK (0x70U)
44624 #define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_SHIFT (4U)
44625 /*! oiec_pcmaudiomode - PCM audio mode */
44626 #define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_MASK)
44627 /*! @} */
44628 
44629 /*! @name FC_AUDSCHNL3 - Frame Composer Audio Sample Channel Status Configuration Register 3 */
44630 /*! @{ */
44631 
44632 #define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_MASK (0xFU)
44633 #define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_SHIFT (0U)
44634 /*! oiec_channelnumcr0 - Channel number for first right sample */
44635 #define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_MASK)
44636 
44637 #define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_MASK (0xF0U)
44638 #define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_SHIFT (4U)
44639 /*! oiec_channelnumcr1 - Channel number for second right sample */
44640 #define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_MASK)
44641 /*! @} */
44642 
44643 /*! @name FC_AUDSCHNL4 - Frame Composer Audio Sample Channel Status Configuration Register 4 */
44644 /*! @{ */
44645 
44646 #define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_MASK (0xFU)
44647 #define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_SHIFT (0U)
44648 /*! oiec_channelnumcr2 - Channel number for third right sample */
44649 #define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_MASK)
44650 
44651 #define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_MASK (0xF0U)
44652 #define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_SHIFT (4U)
44653 /*! oiec_channelnumcr3 - Channel number for fourth right sample */
44654 #define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_MASK)
44655 /*! @} */
44656 
44657 /*! @name FC_AUDSCHNL5 - Frame Composer Audio Sample Channel Status Configuration Register 5 */
44658 /*! @{ */
44659 
44660 #define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_MASK (0xFU)
44661 #define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_SHIFT (0U)
44662 /*! oiec_channelnumcl0 - Channel number for first left sample */
44663 #define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_MASK)
44664 
44665 #define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_MASK (0xF0U)
44666 #define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_SHIFT (4U)
44667 /*! oiec_channelnumcl1 - Channel number for second left sample */
44668 #define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_MASK)
44669 /*! @} */
44670 
44671 /*! @name FC_AUDSCHNL6 - Frame Composer Audio Sample Channel Status Configuration Register 6 */
44672 /*! @{ */
44673 
44674 #define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_MASK (0xFU)
44675 #define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_SHIFT (0U)
44676 /*! oiec_channelnumcl2 - Channel number for third left sample */
44677 #define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_MASK)
44678 
44679 #define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_MASK (0xF0U)
44680 #define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_SHIFT (4U)
44681 /*! oiec_channelnumcl3 - Channel number for fourth left sample */
44682 #define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_MASK)
44683 /*! @} */
44684 
44685 /*! @name FC_AUDSCHNL7 - Frame Composer Audio Sample Channel Status Configuration Register 7 */
44686 /*! @{ */
44687 
44688 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_MASK (0xFU)
44689 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_SHIFT (0U)
44690 /*! oiec_sampfreq - Sampling frequency */
44691 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_MASK)
44692 
44693 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_MASK (0x30U)
44694 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_SHIFT (4U)
44695 /*! oiec_clkaccuracy - Clock accuracy */
44696 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_MASK)
44697 
44698 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_MASK (0xC0U)
44699 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_SHIFT (6U)
44700 /*! oiec_sampfreq_ext - Sampling frequency (channel status bits 31 and 30) */
44701 #define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_MASK)
44702 /*! @} */
44703 
44704 /*! @name FC_AUDSCHNL8 - Frame Composer Audio Sample Channel Status Configuration Register 8 */
44705 /*! @{ */
44706 
44707 #define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_MASK (0xFU)
44708 #define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_SHIFT (0U)
44709 /*! oiec_wordlength - Word length configuration */
44710 #define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_MASK)
44711 
44712 #define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_MASK (0xF0U)
44713 #define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_SHIFT (4U)
44714 /*! oiec_origsampfreq - Original sampling frequency */
44715 #define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_MASK)
44716 /*! @} */
44717 
44718 /*! @name FC_CTRLQHIGH - Frame Composer Number of High Priority Packets Attended Configuration Register */
44719 /*! @{ */
44720 
44721 #define FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_MASK (0x1FU)
44722 #define FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_SHIFT (0U)
44723 /*! onhighattended - Configures the number of high priority packets or audio sample packets
44724  *    consecutively attended before checking low priority queue status.
44725  */
44726 #define FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_SHIFT)) & FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_MASK)
44727 /*! @} */
44728 
44729 /*! @name FC_CTRLQLOW - Frame Composer Number of Low Priority Packets Attended Configuration Register */
44730 /*! @{ */
44731 
44732 #define FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_MASK (0x1FU)
44733 #define FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_SHIFT (0U)
44734 /*! onlowattended - Configures the number of low priority packets or null packets consecutively
44735  *    attended before checking high priority queue status or audio samples availability.
44736  */
44737 #define FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_SHIFT)) & FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_MASK)
44738 /*! @} */
44739 
44740 /*! @name FC_ACP0 - Frame Composer ACP Packet Type Configuration Register 0 */
44741 /*! @{ */
44742 
44743 #define FRAMECOMPOSER_FC_ACP0_ACPTYPE_MASK       (0xFFU)
44744 #define FRAMECOMPOSER_FC_ACP0_ACPTYPE_SHIFT      (0U)
44745 /*! acptype - Configures the ACP packet type. */
44746 #define FRAMECOMPOSER_FC_ACP0_ACPTYPE(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP0_ACPTYPE_SHIFT)) & FRAMECOMPOSER_FC_ACP0_ACPTYPE_MASK)
44747 /*! @} */
44748 
44749 /*! @name FC_ACP16 - Frame Composer ACP Packet Body Configuration Register 16 */
44750 /*! @{ */
44751 
44752 #define FRAMECOMPOSER_FC_ACP16_FC_ACP16_MASK     (0xFFU)
44753 #define FRAMECOMPOSER_FC_ACP16_FC_ACP16_SHIFT    (0U)
44754 /*! fc_acp16 - Frame Composer ACP Packet Body Configuration Register 16 */
44755 #define FRAMECOMPOSER_FC_ACP16_FC_ACP16(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP16_FC_ACP16_SHIFT)) & FRAMECOMPOSER_FC_ACP16_FC_ACP16_MASK)
44756 /*! @} */
44757 
44758 /*! @name FC_ACP15 - Frame Composer ACP Packet Body Configuration Register 15 */
44759 /*! @{ */
44760 
44761 #define FRAMECOMPOSER_FC_ACP15_FC_ACP15_MASK     (0xFFU)
44762 #define FRAMECOMPOSER_FC_ACP15_FC_ACP15_SHIFT    (0U)
44763 /*! fc_acp15 - Frame Composer ACP Packet Body Configuration Register 15 */
44764 #define FRAMECOMPOSER_FC_ACP15_FC_ACP15(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP15_FC_ACP15_SHIFT)) & FRAMECOMPOSER_FC_ACP15_FC_ACP15_MASK)
44765 /*! @} */
44766 
44767 /*! @name FC_ACP14 - Frame Composer ACP Packet Body Configuration Register 14 */
44768 /*! @{ */
44769 
44770 #define FRAMECOMPOSER_FC_ACP14_FC_ACP14_MASK     (0xFFU)
44771 #define FRAMECOMPOSER_FC_ACP14_FC_ACP14_SHIFT    (0U)
44772 /*! fc_acp14 - Frame Composer ACP Packet Body Configuration Register 14 */
44773 #define FRAMECOMPOSER_FC_ACP14_FC_ACP14(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP14_FC_ACP14_SHIFT)) & FRAMECOMPOSER_FC_ACP14_FC_ACP14_MASK)
44774 /*! @} */
44775 
44776 /*! @name FC_ACP13 - Frame Composer ACP Packet Body Configuration Register 13 */
44777 /*! @{ */
44778 
44779 #define FRAMECOMPOSER_FC_ACP13_FC_ACP13_MASK     (0xFFU)
44780 #define FRAMECOMPOSER_FC_ACP13_FC_ACP13_SHIFT    (0U)
44781 /*! fc_acp13 - Frame Composer ACP Packet Body Configuration Register 13 */
44782 #define FRAMECOMPOSER_FC_ACP13_FC_ACP13(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP13_FC_ACP13_SHIFT)) & FRAMECOMPOSER_FC_ACP13_FC_ACP13_MASK)
44783 /*! @} */
44784 
44785 /*! @name FC_ACP12 - Frame Composer ACP Packet Body Configuration Register 12 */
44786 /*! @{ */
44787 
44788 #define FRAMECOMPOSER_FC_ACP12_FC_ACP12_MASK     (0xFFU)
44789 #define FRAMECOMPOSER_FC_ACP12_FC_ACP12_SHIFT    (0U)
44790 /*! fc_acp12 - Frame Composer ACP Packet Body Configuration Register 12 */
44791 #define FRAMECOMPOSER_FC_ACP12_FC_ACP12(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP12_FC_ACP12_SHIFT)) & FRAMECOMPOSER_FC_ACP12_FC_ACP12_MASK)
44792 /*! @} */
44793 
44794 /*! @name FC_ACP11 - Frame Composer ACP Packet Body Configuration Register 11 */
44795 /*! @{ */
44796 
44797 #define FRAMECOMPOSER_FC_ACP11_FC_ACP11_MASK     (0xFFU)
44798 #define FRAMECOMPOSER_FC_ACP11_FC_ACP11_SHIFT    (0U)
44799 /*! fc_acp11 - Frame Composer ACP Packet Body Configuration Register 11 */
44800 #define FRAMECOMPOSER_FC_ACP11_FC_ACP11(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP11_FC_ACP11_SHIFT)) & FRAMECOMPOSER_FC_ACP11_FC_ACP11_MASK)
44801 /*! @} */
44802 
44803 /*! @name FC_ACP10 - Frame Composer ACP Packet Body Configuration Register 10 */
44804 /*! @{ */
44805 
44806 #define FRAMECOMPOSER_FC_ACP10_FC_ACP10_MASK     (0xFFU)
44807 #define FRAMECOMPOSER_FC_ACP10_FC_ACP10_SHIFT    (0U)
44808 /*! fc_acp10 - Frame Composer ACP Packet Body Configuration Register 10 */
44809 #define FRAMECOMPOSER_FC_ACP10_FC_ACP10(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP10_FC_ACP10_SHIFT)) & FRAMECOMPOSER_FC_ACP10_FC_ACP10_MASK)
44810 /*! @} */
44811 
44812 /*! @name FC_ACP9 - Frame Composer ACP Packet Body Configuration Register 9 */
44813 /*! @{ */
44814 
44815 #define FRAMECOMPOSER_FC_ACP9_FC_ACP9_MASK       (0xFFU)
44816 #define FRAMECOMPOSER_FC_ACP9_FC_ACP9_SHIFT      (0U)
44817 /*! fc_acp9 - Frame Composer ACP Packet Body Configuration Register 9 */
44818 #define FRAMECOMPOSER_FC_ACP9_FC_ACP9(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP9_FC_ACP9_SHIFT)) & FRAMECOMPOSER_FC_ACP9_FC_ACP9_MASK)
44819 /*! @} */
44820 
44821 /*! @name FC_ACP8 - Frame Composer ACP Packet Body Configuration Register 8 */
44822 /*! @{ */
44823 
44824 #define FRAMECOMPOSER_FC_ACP8_FC_ACP8_MASK       (0xFFU)
44825 #define FRAMECOMPOSER_FC_ACP8_FC_ACP8_SHIFT      (0U)
44826 /*! fc_acp8 - Frame Composer ACP Packet Body Configuration Register 8 */
44827 #define FRAMECOMPOSER_FC_ACP8_FC_ACP8(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP8_FC_ACP8_SHIFT)) & FRAMECOMPOSER_FC_ACP8_FC_ACP8_MASK)
44828 /*! @} */
44829 
44830 /*! @name FC_ACP7 - Frame Composer ACP Packet Body Configuration Register 7 */
44831 /*! @{ */
44832 
44833 #define FRAMECOMPOSER_FC_ACP7_FC_ACP7_MASK       (0xFFU)
44834 #define FRAMECOMPOSER_FC_ACP7_FC_ACP7_SHIFT      (0U)
44835 /*! fc_acp7 - Frame Composer ACP Packet Body Configuration Register 7 */
44836 #define FRAMECOMPOSER_FC_ACP7_FC_ACP7(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP7_FC_ACP7_SHIFT)) & FRAMECOMPOSER_FC_ACP7_FC_ACP7_MASK)
44837 /*! @} */
44838 
44839 /*! @name FC_ACP6 - Frame Composer ACP Packet Body Configuration Register 6 */
44840 /*! @{ */
44841 
44842 #define FRAMECOMPOSER_FC_ACP6_FC_ACP6_MASK       (0xFFU)
44843 #define FRAMECOMPOSER_FC_ACP6_FC_ACP6_SHIFT      (0U)
44844 /*! fc_acp6 - Frame Composer ACP Packet Body Configuration Register 6 */
44845 #define FRAMECOMPOSER_FC_ACP6_FC_ACP6(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP6_FC_ACP6_SHIFT)) & FRAMECOMPOSER_FC_ACP6_FC_ACP6_MASK)
44846 /*! @} */
44847 
44848 /*! @name FC_ACP5 - Frame Composer ACP Packet Body Configuration Register 5 */
44849 /*! @{ */
44850 
44851 #define FRAMECOMPOSER_FC_ACP5_FC_ACP5_MASK       (0xFFU)
44852 #define FRAMECOMPOSER_FC_ACP5_FC_ACP5_SHIFT      (0U)
44853 /*! fc_acp5 - Frame Composer ACP Packet Body Configuration Register 5 */
44854 #define FRAMECOMPOSER_FC_ACP5_FC_ACP5(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP5_FC_ACP5_SHIFT)) & FRAMECOMPOSER_FC_ACP5_FC_ACP5_MASK)
44855 /*! @} */
44856 
44857 /*! @name FC_ACP4 - Frame Composer ACP Packet Body Configuration Register 4 */
44858 /*! @{ */
44859 
44860 #define FRAMECOMPOSER_FC_ACP4_FC_ACP4_MASK       (0xFFU)
44861 #define FRAMECOMPOSER_FC_ACP4_FC_ACP4_SHIFT      (0U)
44862 /*! fc_acp4 - Frame Composer ACP Packet Body Configuration Register 4 */
44863 #define FRAMECOMPOSER_FC_ACP4_FC_ACP4(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP4_FC_ACP4_SHIFT)) & FRAMECOMPOSER_FC_ACP4_FC_ACP4_MASK)
44864 /*! @} */
44865 
44866 /*! @name FC_ACP3 - Frame Composer ACP Packet Body Configuration Register 3 */
44867 /*! @{ */
44868 
44869 #define FRAMECOMPOSER_FC_ACP3_FC_ACP3_MASK       (0xFFU)
44870 #define FRAMECOMPOSER_FC_ACP3_FC_ACP3_SHIFT      (0U)
44871 /*! fc_acp3 - Frame Composer ACP Packet Body Configuration Register 3 */
44872 #define FRAMECOMPOSER_FC_ACP3_FC_ACP3(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP3_FC_ACP3_SHIFT)) & FRAMECOMPOSER_FC_ACP3_FC_ACP3_MASK)
44873 /*! @} */
44874 
44875 /*! @name FC_ACP2 - Frame Composer ACP Packet Body Configuration Register 2 */
44876 /*! @{ */
44877 
44878 #define FRAMECOMPOSER_FC_ACP2_FC_ACP2_MASK       (0xFFU)
44879 #define FRAMECOMPOSER_FC_ACP2_FC_ACP2_SHIFT      (0U)
44880 /*! fc_acp2 - Frame Composer ACP Packet Body Configuration Register 2 */
44881 #define FRAMECOMPOSER_FC_ACP2_FC_ACP2(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP2_FC_ACP2_SHIFT)) & FRAMECOMPOSER_FC_ACP2_FC_ACP2_MASK)
44882 /*! @} */
44883 
44884 /*! @name FC_ACP1 - Frame Composer ACP Packet Body Configuration Register 1 */
44885 /*! @{ */
44886 
44887 #define FRAMECOMPOSER_FC_ACP1_FC_ACP1_MASK       (0xFFU)
44888 #define FRAMECOMPOSER_FC_ACP1_FC_ACP1_SHIFT      (0U)
44889 /*! fc_acp1 - Frame Composer ACP Packet Body Configuration Register 1 */
44890 #define FRAMECOMPOSER_FC_ACP1_FC_ACP1(x)         (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP1_FC_ACP1_SHIFT)) & FRAMECOMPOSER_FC_ACP1_FC_ACP1_MASK)
44891 /*! @} */
44892 
44893 /*! @name FC_ISCR1_0 - Frame Composer ISRC1 Packet Status, Valid, and Continue Configuration Register */
44894 /*! @{ */
44895 
44896 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_MASK  (0x1U)
44897 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_SHIFT (0U)
44898 /*! isrc_cont - ISRC1 Indication of packet continuation (ISRC2 will be transmitted) */
44899 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_MASK)
44900 
44901 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_MASK (0x2U)
44902 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_SHIFT (1U)
44903 /*! isrc_valid - ISRC1 Valid control signal */
44904 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_MASK)
44905 
44906 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_MASK (0x1CU)
44907 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_SHIFT (2U)
44908 /*! isrc_status - ISRC1 Status signal */
44909 #define FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_MASK)
44910 /*! @} */
44911 
44912 /*! @name FC_ISCR1_16 - Frame Composer ISRC1 Packet Body Register 16 */
44913 /*! @{ */
44914 
44915 #define FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_MASK (0xFFU)
44916 #define FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_SHIFT (0U)
44917 /*! fc_iscr1_16 - Frame Composer ISRC1 Packet Body Register 16; configures ISRC1 packet body of the ISRC1 packet */
44918 #define FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_MASK)
44919 /*! @} */
44920 
44921 /*! @name FC_ISCR1_15 - Frame Composer ISRC1 Packet Body Register 15 */
44922 /*! @{ */
44923 
44924 #define FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_MASK (0xFFU)
44925 #define FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_SHIFT (0U)
44926 /*! fc_iscr1_15 - Frame Composer ISRC1 Packet Body Register 15 */
44927 #define FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_MASK)
44928 /*! @} */
44929 
44930 /*! @name FC_ISCR1_14 - Frame Composer ISRC1 Packet Body Register 14 */
44931 /*! @{ */
44932 
44933 #define FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_MASK (0xFFU)
44934 #define FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_SHIFT (0U)
44935 /*! fc_iscr1_14 - Frame Composer ISRC1 Packet Body Register 14 */
44936 #define FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_MASK)
44937 /*! @} */
44938 
44939 /*! @name FC_ISCR1_13 - Frame Composer ISRC1 Packet Body Register 13 */
44940 /*! @{ */
44941 
44942 #define FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_MASK (0xFFU)
44943 #define FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_SHIFT (0U)
44944 /*! fc_iscr1_13 - Frame Composer ISRC1 Packet Body Register 13 */
44945 #define FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_MASK)
44946 /*! @} */
44947 
44948 /*! @name FC_ISCR1_12 - Frame Composer ISRC1 Packet Body Register 12 */
44949 /*! @{ */
44950 
44951 #define FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_MASK (0xFFU)
44952 #define FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_SHIFT (0U)
44953 /*! fc_iscr1_12 - Frame Composer ISRC1 Packet Body Register 12 */
44954 #define FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_MASK)
44955 /*! @} */
44956 
44957 /*! @name FC_ISCR1_11 - Frame Composer ISRC1 Packet Body Register 11 */
44958 /*! @{ */
44959 
44960 #define FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_MASK (0xFFU)
44961 #define FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_SHIFT (0U)
44962 /*! fc_iscr1_11 - Frame Composer ISRC1 Packet Body Register 11 */
44963 #define FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_MASK)
44964 /*! @} */
44965 
44966 /*! @name FC_ISCR1_10 - Frame Composer ISRC1 Packet Body Register 10 */
44967 /*! @{ */
44968 
44969 #define FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_MASK (0xFFU)
44970 #define FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_SHIFT (0U)
44971 /*! fc_iscr1_10 - Frame Composer ISRC1 Packet Body Register 10 */
44972 #define FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_MASK)
44973 /*! @} */
44974 
44975 /*! @name FC_ISCR1_9 - Frame Composer ISRC1 Packet Body Register 9 */
44976 /*! @{ */
44977 
44978 #define FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_MASK (0xFFU)
44979 #define FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_SHIFT (0U)
44980 /*! fc_iscr1_9 - Frame Composer ISRC1 Packet Body Register 9 */
44981 #define FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_MASK)
44982 /*! @} */
44983 
44984 /*! @name FC_ISCR1_8 - Frame Composer ISRC1 Packet Body Register 8 */
44985 /*! @{ */
44986 
44987 #define FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_MASK (0xFFU)
44988 #define FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_SHIFT (0U)
44989 /*! fc_iscr1_8 - Frame Composer ISRC1 Packet Body Register 8 */
44990 #define FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_MASK)
44991 /*! @} */
44992 
44993 /*! @name FC_ISCR1_7 - Frame Composer ISRC1 Packet Body Register 7 */
44994 /*! @{ */
44995 
44996 #define FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_MASK (0xFFU)
44997 #define FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_SHIFT (0U)
44998 /*! fc_iscr1_7 - Frame Composer ISRC1 Packet Body Register 7 */
44999 #define FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_MASK)
45000 /*! @} */
45001 
45002 /*! @name FC_ISCR1_6 - Frame Composer ISRC1 Packet Body Register 6 */
45003 /*! @{ */
45004 
45005 #define FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_MASK (0xFFU)
45006 #define FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_SHIFT (0U)
45007 /*! fc_iscr1_6 - Frame Composer ISRC1 Packet Body Register 6 */
45008 #define FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_MASK)
45009 /*! @} */
45010 
45011 /*! @name FC_ISCR1_5 - Frame Composer ISRC1 Packet Body Register 5 */
45012 /*! @{ */
45013 
45014 #define FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_MASK (0xFFU)
45015 #define FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_SHIFT (0U)
45016 /*! fc_iscr1_5 - Frame Composer ISRC1 Packet Body Register 5 */
45017 #define FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_MASK)
45018 /*! @} */
45019 
45020 /*! @name FC_ISCR1_4 - Frame Composer ISRC1 Packet Body Register 4 */
45021 /*! @{ */
45022 
45023 #define FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_MASK (0xFFU)
45024 #define FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_SHIFT (0U)
45025 /*! fc_iscr1_4 - Frame Composer ISRC1 Packet Body Register 4 */
45026 #define FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_MASK)
45027 /*! @} */
45028 
45029 /*! @name FC_ISCR1_3 - Frame Composer ISRC1 Packet Body Register 3 */
45030 /*! @{ */
45031 
45032 #define FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_MASK (0xFFU)
45033 #define FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_SHIFT (0U)
45034 /*! fc_iscr1_3 - Frame Composer ISRC1 Packet Body Register 3 */
45035 #define FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_MASK)
45036 /*! @} */
45037 
45038 /*! @name FC_ISCR1_2 - Frame Composer ISRC1 Packet Body Register 2 */
45039 /*! @{ */
45040 
45041 #define FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_MASK (0xFFU)
45042 #define FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_SHIFT (0U)
45043 /*! fc_iscr1_2 - Frame Composer ISRC1 Packet Body Register 2 */
45044 #define FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_MASK)
45045 /*! @} */
45046 
45047 /*! @name FC_ISCR1_1 - Frame Composer ISRC1 Packet Body Register 1 */
45048 /*! @{ */
45049 
45050 #define FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_MASK (0xFFU)
45051 #define FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_SHIFT (0U)
45052 /*! fc_iscr1_1 - Frame Composer ISRC1 Packet Body Register 1 */
45053 #define FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_MASK)
45054 /*! @} */
45055 
45056 /*! @name FC_ISCR2_15 - Frame Composer ISRC2 Packet Body Register 15 */
45057 /*! @{ */
45058 
45059 #define FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_MASK (0xFFU)
45060 #define FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_SHIFT (0U)
45061 /*! fc_iscr2_15 - Frame Composer ISRC2 Packet Body Register 15; configures the ISRC2 packet body of the ISRC2 packet */
45062 #define FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_MASK)
45063 /*! @} */
45064 
45065 /*! @name FC_ISCR2_14 - Frame Composer ISRC2 Packet Body Register 14 */
45066 /*! @{ */
45067 
45068 #define FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_MASK (0xFFU)
45069 #define FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_SHIFT (0U)
45070 /*! fc_iscr2_14 - Frame Composer ISRC2 Packet Body Register 14 */
45071 #define FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_MASK)
45072 /*! @} */
45073 
45074 /*! @name FC_ISCR2_13 - Frame Composer ISRC2 Packet Body Register 13 */
45075 /*! @{ */
45076 
45077 #define FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_MASK (0xFFU)
45078 #define FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_SHIFT (0U)
45079 /*! fc_iscr2_13 - Frame Composer ISRC2 Packet Body Register 13 */
45080 #define FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_MASK)
45081 /*! @} */
45082 
45083 /*! @name FC_ISCR2_12 - Frame Composer ISRC2 Packet Body Register 12 */
45084 /*! @{ */
45085 
45086 #define FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_MASK (0xFFU)
45087 #define FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_SHIFT (0U)
45088 /*! fc_iscr2_12 - Frame Composer ISRC2 Packet Body Register 12 */
45089 #define FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_MASK)
45090 /*! @} */
45091 
45092 /*! @name FC_ISCR2_11 - Frame Composer ISRC2 Packet Body Register 11 */
45093 /*! @{ */
45094 
45095 #define FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_MASK (0xFFU)
45096 #define FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_SHIFT (0U)
45097 /*! fc_iscr2_11 - Frame Composer ISRC2 Packet Body Register 11 */
45098 #define FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_MASK)
45099 /*! @} */
45100 
45101 /*! @name FC_ISCR2_10 - Frame Composer ISRC2 Packet Body Register 10 */
45102 /*! @{ */
45103 
45104 #define FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_MASK (0xFFU)
45105 #define FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_SHIFT (0U)
45106 /*! fc_iscr2_10 - Frame Composer ISRC2 Packet Body Register 10 */
45107 #define FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_MASK)
45108 /*! @} */
45109 
45110 /*! @name FC_ISCR2_9 - Frame Composer ISRC2 Packet Body Register 9 */
45111 /*! @{ */
45112 
45113 #define FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_MASK (0xFFU)
45114 #define FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_SHIFT (0U)
45115 /*! fc_iscr2_9 - Frame Composer ISRC2 Packet Body Register 9 */
45116 #define FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_MASK)
45117 /*! @} */
45118 
45119 /*! @name FC_ISCR2_8 - Frame Composer ISRC2 Packet Body Register 8 */
45120 /*! @{ */
45121 
45122 #define FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_MASK (0xFFU)
45123 #define FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_SHIFT (0U)
45124 /*! fc_iscr2_8 - Frame Composer ISRC2 Packet Body Register 8 */
45125 #define FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_MASK)
45126 /*! @} */
45127 
45128 /*! @name FC_ISCR2_7 - Frame Composer ISRC2 Packet Body Register 7 */
45129 /*! @{ */
45130 
45131 #define FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_MASK (0xFFU)
45132 #define FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_SHIFT (0U)
45133 /*! fc_iscr2_7 - Frame Composer ISRC2 Packet Body Register 7 */
45134 #define FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_MASK)
45135 /*! @} */
45136 
45137 /*! @name FC_ISCR2_6 - Frame Composer ISRC2 Packet Body Register 6 */
45138 /*! @{ */
45139 
45140 #define FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_MASK (0xFFU)
45141 #define FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_SHIFT (0U)
45142 /*! fc_iscr2_6 - Frame Composer ISRC2 Packet Body Register 6 */
45143 #define FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_MASK)
45144 /*! @} */
45145 
45146 /*! @name FC_ISCR2_5 - Frame Composer ISRC2 Packet Body Register 5 */
45147 /*! @{ */
45148 
45149 #define FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_MASK (0xFFU)
45150 #define FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_SHIFT (0U)
45151 /*! fc_iscr2_5 - Frame Composer ISRC2 Packet Body Register 5 */
45152 #define FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_MASK)
45153 /*! @} */
45154 
45155 /*! @name FC_ISCR2_4 - Frame Composer ISRC2 Packet Body Register 4 */
45156 /*! @{ */
45157 
45158 #define FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_MASK (0xFFU)
45159 #define FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_SHIFT (0U)
45160 /*! fc_iscr2_4 - Frame Composer ISRC2 Packet Body Register 4 */
45161 #define FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_MASK)
45162 /*! @} */
45163 
45164 /*! @name FC_ISCR2_3 - Frame Composer ISRC2 Packet Body Register 3 */
45165 /*! @{ */
45166 
45167 #define FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_MASK (0xFFU)
45168 #define FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_SHIFT (0U)
45169 /*! fc_iscr2_3 - Frame Composer ISRC2 Packet Body Register 3 */
45170 #define FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_MASK)
45171 /*! @} */
45172 
45173 /*! @name FC_ISCR2_2 - Frame Composer ISRC2 Packet Body Register 2 */
45174 /*! @{ */
45175 
45176 #define FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_MASK (0xFFU)
45177 #define FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_SHIFT (0U)
45178 /*! fc_iscr2_2 - Frame Composer ISRC2 Packet Body Register 2 */
45179 #define FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_MASK)
45180 /*! @} */
45181 
45182 /*! @name FC_ISCR2_1 - Frame Composer ISRC2 Packet Body Register 1 */
45183 /*! @{ */
45184 
45185 #define FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_MASK (0xFFU)
45186 #define FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_SHIFT (0U)
45187 /*! fc_iscr2_1 - Frame Composer ISRC2 Packet Body Register 1 */
45188 #define FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_MASK)
45189 /*! @} */
45190 
45191 /*! @name FC_ISCR2_0 - Frame Composer ISRC2 Packet Body Register 0 */
45192 /*! @{ */
45193 
45194 #define FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_MASK (0xFFU)
45195 #define FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_SHIFT (0U)
45196 /*! fc_iscr2_0 - Frame Composer ISRC2 Packet Body Register 0 */
45197 #define FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_MASK)
45198 /*! @} */
45199 
45200 /*! @name FC_DATAUTO0 - Frame Composer Data Island Auto Packet Scheduling Register 0 Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD, VSD, ISRC2, ISRC1 and ACP packets. */
45201 /*! @{ */
45202 
45203 #define FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_MASK  (0x1U)
45204 #define FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_SHIFT (0U)
45205 /*! acp_auto - Enables ACP automatic packet scheduling */
45206 #define FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_MASK)
45207 
45208 #define FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_MASK (0x2U)
45209 #define FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_SHIFT (1U)
45210 /*! iscr1_auto - Enables ISRC1 automatic packet scheduling */
45211 #define FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_MASK)
45212 
45213 #define FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_MASK (0x4U)
45214 #define FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_SHIFT (2U)
45215 /*! iscr2_auto - Enables ISRC2 automatic packet scheduling */
45216 #define FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_MASK)
45217 
45218 #define FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_MASK  (0x8U)
45219 #define FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_SHIFT (3U)
45220 /*! vsd_auto - Enables VSD automatic packet scheduling */
45221 #define FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_MASK)
45222 
45223 #define FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_MASK  (0x10U)
45224 #define FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_SHIFT (4U)
45225 /*! spd_auto - Enables SPD automatic packet scheduling */
45226 #define FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_MASK)
45227 /*! @} */
45228 
45229 /*! @name FC_DATAUTO1 - Frame Composer Data Island Auto Packet Scheduling Register 1 Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets. */
45230 /*! @{ */
45231 
45232 #define FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_MASK (0xFU)
45233 #define FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_SHIFT (0U)
45234 /*! auto_frame_interpolation - Packet frame interpolation for automatic packet scheduling */
45235 #define FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_MASK)
45236 /*! @} */
45237 
45238 /*! @name FC_DATAUTO2 - Frame Composer Data Island Auto packet scheduling Register 2 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets. */
45239 /*! @{ */
45240 
45241 #define FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_MASK (0xFU)
45242 #define FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_SHIFT (0U)
45243 /*! auto_line_spacing - Packets line spacing, for automatic packet scheduling */
45244 #define FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_MASK)
45245 
45246 #define FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_MASK (0xF0U)
45247 #define FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_SHIFT (4U)
45248 /*! auto_frame_packets - Packets per frame, for automatic packet scheduling */
45249 #define FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_MASK)
45250 /*! @} */
45251 
45252 /*! @name FC_DATMAN - Frame Composer Data Island Manual Packet Request Register Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD, ISRC2, ISRC1 and ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested. */
45253 /*! @{ */
45254 
45255 #define FRAMECOMPOSER_FC_DATMAN_ACP_TX_MASK      (0x1U)
45256 #define FRAMECOMPOSER_FC_DATMAN_ACP_TX_SHIFT     (0U)
45257 /*! acp_tx - ACP packet */
45258 #define FRAMECOMPOSER_FC_DATMAN_ACP_TX(x)        (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_ACP_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_ACP_TX_MASK)
45259 
45260 #define FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_MASK    (0x2U)
45261 #define FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_SHIFT   (1U)
45262 /*! iscr1_tx - ISRC1 packet */
45263 #define FRAMECOMPOSER_FC_DATMAN_ISCR1_TX(x)      (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_MASK)
45264 
45265 #define FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_MASK    (0x4U)
45266 #define FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_SHIFT   (2U)
45267 /*! iscr2_tx - ISRC2 packet */
45268 #define FRAMECOMPOSER_FC_DATMAN_ISCR2_TX(x)      (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_MASK)
45269 
45270 #define FRAMECOMPOSER_FC_DATMAN_VSD_TX_MASK      (0x8U)
45271 #define FRAMECOMPOSER_FC_DATMAN_VSD_TX_SHIFT     (3U)
45272 /*! vsd_tx - VSD packet */
45273 #define FRAMECOMPOSER_FC_DATMAN_VSD_TX(x)        (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_VSD_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_VSD_TX_MASK)
45274 
45275 #define FRAMECOMPOSER_FC_DATMAN_SPD_TX_MASK      (0x10U)
45276 #define FRAMECOMPOSER_FC_DATMAN_SPD_TX_SHIFT     (4U)
45277 /*! spd_tx - SPD packet */
45278 #define FRAMECOMPOSER_FC_DATMAN_SPD_TX(x)        (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_SPD_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_SPD_TX_MASK)
45279 
45280 #define FRAMECOMPOSER_FC_DATMAN_NULL_TX_MASK     (0x20U)
45281 #define FRAMECOMPOSER_FC_DATMAN_NULL_TX_SHIFT    (5U)
45282 /*! null_tx - Null packet */
45283 #define FRAMECOMPOSER_FC_DATMAN_NULL_TX(x)       (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_NULL_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_NULL_TX_MASK)
45284 /*! @} */
45285 
45286 /*! @name FC_DATAUTO3 - Frame Composer Data Island Auto Packet Scheduling Register 3 Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI, GCP, AUDI and ACR packets. */
45287 /*! @{ */
45288 
45289 #define FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_MASK  (0x1U)
45290 #define FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_SHIFT (0U)
45291 /*! acr_auto - Enables ACR packet insertion */
45292 #define FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_MASK)
45293 
45294 #define FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_MASK (0x2U)
45295 #define FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_SHIFT (1U)
45296 /*! audi_auto - Enables AUDI packet insertion */
45297 #define FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_MASK)
45298 
45299 #define FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_MASK  (0x4U)
45300 #define FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_SHIFT (2U)
45301 /*! gcp_auto - Enables GCP packet insertion */
45302 #define FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_MASK)
45303 
45304 #define FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_MASK  (0x8U)
45305 #define FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_SHIFT (3U)
45306 /*! avi_auto - Enables AVI packet insertion */
45307 #define FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_MASK)
45308 
45309 #define FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_MASK  (0x10U)
45310 #define FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_SHIFT (4U)
45311 /*! amp_auto - Enables AMP packet insertion */
45312 #define FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_MASK)
45313 
45314 #define FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_MASK (0x20U)
45315 #define FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_SHIFT (5U)
45316 /*! nvbi_auto - Enables NTSC VBI packet insertion */
45317 #define FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_MASK)
45318 
45319 #define FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_MASK  (0x40U)
45320 #define FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_SHIFT (6U)
45321 /*! drm_auto - Enables DRM packet insertion */
45322 #define FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO(x)    (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_MASK)
45323 /*! @} */
45324 
45325 /*! @name FC_RDRB0 - Frame Composer Round Robin ACR Packet Insertion Register 0 Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet insertion on data island when FC is on RDRB mode for this packet. */
45326 /*! @{ */
45327 
45328 #define FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_MASK (0xFU)
45329 #define FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_SHIFT (0U)
45330 /*! ACRframeinterpolation - ACR Frame interpolation */
45331 #define FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_MASK)
45332 /*! @} */
45333 
45334 /*! @name FC_RDRB1 - Frame Composer Round Robin ACR Packet Insertion Register 1 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the ACR packet insertion on data island when FC is on RDRB mode this packet. */
45335 /*! @{ */
45336 
45337 #define FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_MASK (0xFU)
45338 #define FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_SHIFT (0U)
45339 /*! ACRpacketlinespacing - ACR packet line spacing */
45340 #define FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_MASK)
45341 
45342 #define FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_MASK (0xF0U)
45343 #define FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_SHIFT (4U)
45344 /*! ACRpacketsinframe - ACR packets in frame */
45345 #define FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_MASK)
45346 /*! @} */
45347 
45348 /*! @name FC_RDRB2 - Frame Composer Round Robin AUDI Packet Insertion Register 2 Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet insertion on data island when FC is on RDRB mode for this packet. */
45349 /*! @{ */
45350 
45351 #define FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_MASK (0xFU)
45352 #define FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_SHIFT (0U)
45353 /*! AUDIframeinterpolation - Audio frame interpolation */
45354 #define FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_MASK)
45355 /*! @} */
45356 
45357 /*! @name FC_RDRB3 - Frame Composer Round Robin AUDI Packet Insertion Register 3 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AUDI packet insertion on data island when FC is on RDRB mode this packet. */
45358 /*! @{ */
45359 
45360 #define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_MASK (0xFU)
45361 #define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_SHIFT (0U)
45362 /*! AUDIpacketlinespacing - Audio packets line spacing */
45363 #define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_MASK)
45364 
45365 #define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_MASK (0xF0U)
45366 #define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_SHIFT (4U)
45367 /*! AUDIpacketsinframe - Audio packets per frame */
45368 #define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_MASK)
45369 /*! @} */
45370 
45371 /*! @name FC_RDRB4 - Frame Composer Round Robin GCP Packet Insertion Register 4 Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet insertion on data island when FC is on RDRB mode for this packet. */
45372 /*! @{ */
45373 
45374 #define FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_MASK (0xFU)
45375 #define FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_SHIFT (0U)
45376 /*! GCPframeinterpolation - Frames interpolated between GCP packets */
45377 #define FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_MASK)
45378 /*! @} */
45379 
45380 /*! @name FC_RDRB5 - Frame Composer Round Robin GCP Packet Insertion Register 5 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the GCP packet insertion on data island when FC is on RDRB mode this packet. */
45381 /*! @{ */
45382 
45383 #define FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_MASK (0xFU)
45384 #define FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_SHIFT (0U)
45385 /*! GCPpacketlinespacing - GCP packets line spacing */
45386 #define FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_MASK)
45387 
45388 #define FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_MASK (0xF0U)
45389 #define FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_SHIFT (4U)
45390 /*! GCPpacketsinframe - GCP packets per frame */
45391 #define FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_MASK)
45392 /*! @} */
45393 
45394 /*! @name FC_RDRB6 - Frame Composer Round Robin AVI Packet Insertion Register 6 Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet insertion on data island when FC is on RDRB mode for this packet. */
45395 /*! @{ */
45396 
45397 #define FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_MASK (0xFU)
45398 #define FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_SHIFT (0U)
45399 /*! AVIframeinterpolation - Frames interpolated between AVI packets */
45400 #define FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_MASK)
45401 /*! @} */
45402 
45403 /*! @name FC_RDRB7 - Frame Composer Round Robin AVI Packet Insertion Register 7 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AVI packet insertion on data island when FC is on RDRB mode this packet. */
45404 /*! @{ */
45405 
45406 #define FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_MASK (0xFU)
45407 #define FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_SHIFT (0U)
45408 /*! AVIpacketlinespacing - AVI packets line spacing */
45409 #define FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_MASK)
45410 
45411 #define FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_MASK (0xF0U)
45412 #define FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_SHIFT (4U)
45413 /*! AVIpacketsinframe - AVI packets per frame */
45414 #define FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_MASK)
45415 /*! @} */
45416 
45417 /*! @name FC_RDRB8 - Frame Composer Round Robin AMP Packet Insertion Register 8 */
45418 /*! @{ */
45419 
45420 #define FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_MASK (0xFU)
45421 #define FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_SHIFT (0U)
45422 /*! AMPframeinterpolation - AMP frame interpolation */
45423 #define FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_MASK)
45424 /*! @} */
45425 
45426 /*! @name FC_RDRB9 - Frame Composer Round Robin AMP Packet Insertion Register 9 */
45427 /*! @{ */
45428 
45429 #define FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_MASK (0xFU)
45430 #define FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_SHIFT (0U)
45431 /*! AMPpacketlinespacing - AMP packets line spacing */
45432 #define FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_MASK)
45433 
45434 #define FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_MASK (0xF0U)
45435 #define FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_SHIFT (4U)
45436 /*! AMPpacketsinframe - AMP packets per frame */
45437 #define FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_MASK)
45438 /*! @} */
45439 
45440 /*! @name FC_RDRB10 - Frame Composer Round Robin NTSC VBI Packet Insertion Register 10 */
45441 /*! @{ */
45442 
45443 #define FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_MASK (0xFU)
45444 #define FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_SHIFT (0U)
45445 /*! NVBIframeinterpolation - NTSC VBI frame interpolation */
45446 #define FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_MASK)
45447 /*! @} */
45448 
45449 /*! @name FC_RDRB11 - Frame Composer Round Robin NTSC VBI Packet Insertion Register 11 */
45450 /*! @{ */
45451 
45452 #define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_MASK (0xFU)
45453 #define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_SHIFT (0U)
45454 /*! NVBIpacketlinespacing - NTSC VBI packets line spacing */
45455 #define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_MASK)
45456 
45457 #define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_MASK (0xF0U)
45458 #define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_SHIFT (4U)
45459 /*! NVBIpacketsinframe - NTSC VBI packets per frame */
45460 #define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_MASK)
45461 /*! @} */
45462 
45463 /*! @name FC_RDRB12 - Frame Composer Round Robin DRM Packet Insertion Register 12 */
45464 /*! @{ */
45465 
45466 #define FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_MASK (0xFU)
45467 #define FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_SHIFT (0U)
45468 /*! DRMframeinterpolation - DRM frame interpolation */
45469 #define FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_MASK)
45470 /*! @} */
45471 
45472 /*! @name FC_RDRB13 - Frame Composer Round Robin DRM Packet Insertion Register 13 */
45473 /*! @{ */
45474 
45475 #define FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_MASK (0xFU)
45476 #define FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_SHIFT (0U)
45477 /*! DRMpacketlinespacing - DRM packets line spacing */
45478 #define FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_MASK)
45479 
45480 #define FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_MASK (0xF0U)
45481 #define FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_SHIFT (4U)
45482 /*! DRMpacketsinframe - DRM packets per frame */
45483 #define FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_MASK)
45484 /*! @} */
45485 
45486 /*! @name FC_MASK0 - Frame Composer Packet Interrupt Mask Register 0 */
45487 /*! @{ */
45488 
45489 #define FRAMECOMPOSER_FC_MASK0_NULL_MASK         (0x1U)
45490 #define FRAMECOMPOSER_FC_MASK0_NULL_SHIFT        (0U)
45491 /*! NULL - Mask bit for FC_INT0. */
45492 #define FRAMECOMPOSER_FC_MASK0_NULL(x)           (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_NULL_SHIFT)) & FRAMECOMPOSER_FC_MASK0_NULL_MASK)
45493 
45494 #define FRAMECOMPOSER_FC_MASK0_ACR_MASK          (0x2U)
45495 #define FRAMECOMPOSER_FC_MASK0_ACR_SHIFT         (1U)
45496 /*! ACR - Mask bit for FC_INT0. */
45497 #define FRAMECOMPOSER_FC_MASK0_ACR(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_ACR_SHIFT)) & FRAMECOMPOSER_FC_MASK0_ACR_MASK)
45498 
45499 #define FRAMECOMPOSER_FC_MASK0_AUDS_MASK         (0x4U)
45500 #define FRAMECOMPOSER_FC_MASK0_AUDS_SHIFT        (2U)
45501 /*! AUDS - Mask bit for FC_INT0. */
45502 #define FRAMECOMPOSER_FC_MASK0_AUDS(x)           (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_AUDS_SHIFT)) & FRAMECOMPOSER_FC_MASK0_AUDS_MASK)
45503 
45504 #define FRAMECOMPOSER_FC_MASK0_NVBI_MASK         (0x8U)
45505 #define FRAMECOMPOSER_FC_MASK0_NVBI_SHIFT        (3U)
45506 /*! NVBI - Mask bit for FC_INT0. */
45507 #define FRAMECOMPOSER_FC_MASK0_NVBI(x)           (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_NVBI_SHIFT)) & FRAMECOMPOSER_FC_MASK0_NVBI_MASK)
45508 
45509 #define FRAMECOMPOSER_FC_MASK0_MAS_MASK          (0x10U)
45510 #define FRAMECOMPOSER_FC_MASK0_MAS_SHIFT         (4U)
45511 /*! MAS - Mask bit for FC_INT0. */
45512 #define FRAMECOMPOSER_FC_MASK0_MAS(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_MAS_SHIFT)) & FRAMECOMPOSER_FC_MASK0_MAS_MASK)
45513 
45514 #define FRAMECOMPOSER_FC_MASK0_HBR_MASK          (0x20U)
45515 #define FRAMECOMPOSER_FC_MASK0_HBR_SHIFT         (5U)
45516 /*! HBR - Mask bit for FC_INT0. */
45517 #define FRAMECOMPOSER_FC_MASK0_HBR(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_HBR_SHIFT)) & FRAMECOMPOSER_FC_MASK0_HBR_MASK)
45518 
45519 #define FRAMECOMPOSER_FC_MASK0_ACP_MASK          (0x40U)
45520 #define FRAMECOMPOSER_FC_MASK0_ACP_SHIFT         (6U)
45521 /*! ACP - Mask bit for FC_INT0. */
45522 #define FRAMECOMPOSER_FC_MASK0_ACP(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_ACP_SHIFT)) & FRAMECOMPOSER_FC_MASK0_ACP_MASK)
45523 
45524 #define FRAMECOMPOSER_FC_MASK0_AUDI_MASK         (0x80U)
45525 #define FRAMECOMPOSER_FC_MASK0_AUDI_SHIFT        (7U)
45526 /*! AUDI - Mask bit for FC_INT0. */
45527 #define FRAMECOMPOSER_FC_MASK0_AUDI(x)           (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_AUDI_SHIFT)) & FRAMECOMPOSER_FC_MASK0_AUDI_MASK)
45528 /*! @} */
45529 
45530 /*! @name FC_MASK1 - Frame Composer Packet Interrupt Mask Register 1 */
45531 /*! @{ */
45532 
45533 #define FRAMECOMPOSER_FC_MASK1_GCP_MASK          (0x1U)
45534 #define FRAMECOMPOSER_FC_MASK1_GCP_SHIFT         (0U)
45535 /*! GCP - Mask bit for FC_INT1. */
45536 #define FRAMECOMPOSER_FC_MASK1_GCP(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_GCP_SHIFT)) & FRAMECOMPOSER_FC_MASK1_GCP_MASK)
45537 
45538 #define FRAMECOMPOSER_FC_MASK1_AVI_MASK          (0x2U)
45539 #define FRAMECOMPOSER_FC_MASK1_AVI_SHIFT         (1U)
45540 /*! AVI - Mask bit for FC_INT1. */
45541 #define FRAMECOMPOSER_FC_MASK1_AVI(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_AVI_SHIFT)) & FRAMECOMPOSER_FC_MASK1_AVI_MASK)
45542 
45543 #define FRAMECOMPOSER_FC_MASK1_AMP_MASK          (0x4U)
45544 #define FRAMECOMPOSER_FC_MASK1_AMP_SHIFT         (2U)
45545 /*! AMP - Mask bit for FC_INT1. */
45546 #define FRAMECOMPOSER_FC_MASK1_AMP(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_AMP_SHIFT)) & FRAMECOMPOSER_FC_MASK1_AMP_MASK)
45547 
45548 #define FRAMECOMPOSER_FC_MASK1_SPD_MASK          (0x8U)
45549 #define FRAMECOMPOSER_FC_MASK1_SPD_SHIFT         (3U)
45550 /*! SPD - Mask bit for FC_INT1. */
45551 #define FRAMECOMPOSER_FC_MASK1_SPD(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_SPD_SHIFT)) & FRAMECOMPOSER_FC_MASK1_SPD_MASK)
45552 
45553 #define FRAMECOMPOSER_FC_MASK1_VSD_MASK          (0x10U)
45554 #define FRAMECOMPOSER_FC_MASK1_VSD_SHIFT         (4U)
45555 /*! VSD - Mask bit for FC_INT1. */
45556 #define FRAMECOMPOSER_FC_MASK1_VSD(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_VSD_SHIFT)) & FRAMECOMPOSER_FC_MASK1_VSD_MASK)
45557 
45558 #define FRAMECOMPOSER_FC_MASK1_ISCR2_MASK        (0x20U)
45559 #define FRAMECOMPOSER_FC_MASK1_ISCR2_SHIFT       (5U)
45560 /*! ISCR2 - Mask bit for FC_INT1. */
45561 #define FRAMECOMPOSER_FC_MASK1_ISCR2(x)          (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_ISCR2_SHIFT)) & FRAMECOMPOSER_FC_MASK1_ISCR2_MASK)
45562 
45563 #define FRAMECOMPOSER_FC_MASK1_ISCR1_MASK        (0x40U)
45564 #define FRAMECOMPOSER_FC_MASK1_ISCR1_SHIFT       (6U)
45565 /*! ISCR1 - Mask bit for FC_INT1. */
45566 #define FRAMECOMPOSER_FC_MASK1_ISCR1(x)          (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_ISCR1_SHIFT)) & FRAMECOMPOSER_FC_MASK1_ISCR1_MASK)
45567 
45568 #define FRAMECOMPOSER_FC_MASK1_GMD_MASK          (0x80U)
45569 #define FRAMECOMPOSER_FC_MASK1_GMD_SHIFT         (7U)
45570 /*! GMD - Mask bit for FC_INT1. */
45571 #define FRAMECOMPOSER_FC_MASK1_GMD(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_GMD_SHIFT)) & FRAMECOMPOSER_FC_MASK1_GMD_MASK)
45572 /*! @} */
45573 
45574 /*! @name FC_MASK2 - Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register 2 */
45575 /*! @{ */
45576 
45577 #define FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_MASK (0x1U)
45578 #define FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_SHIFT (0U)
45579 /*! HighPriority_overflow - Mask bit for FC_INT2. */
45580 #define FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_SHIFT)) & FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_MASK)
45581 
45582 #define FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_MASK (0x2U)
45583 #define FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_SHIFT (1U)
45584 /*! LowPriority_overflow - Mask bit for FC_INT2. */
45585 #define FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_SHIFT)) & FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_MASK)
45586 
45587 #define FRAMECOMPOSER_FC_MASK2_DRM_MASK          (0x10U)
45588 #define FRAMECOMPOSER_FC_MASK2_DRM_SHIFT         (4U)
45589 /*! DRM - Mask bit for FC_INT2. */
45590 #define FRAMECOMPOSER_FC_MASK2_DRM(x)            (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK2_DRM_SHIFT)) & FRAMECOMPOSER_FC_MASK2_DRM_MASK)
45591 /*! @} */
45592 
45593 /*! @name FC_PRCONF - Frame Composer Pixel Repetition Configuration Register */
45594 /*! @{ */
45595 
45596 #define FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_MASK (0xFU)
45597 #define FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_SHIFT (0U)
45598 /*! output_pr_factor - Configures the video pixel repetition ratio to be sent on the AVI InfoFrame. */
45599 #define FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_SHIFT)) & FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_MASK)
45600 
45601 #define FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_MASK (0xF0U)
45602 #define FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_SHIFT (4U)
45603 /*! incoming_pr_factor - Configures the input video pixel repetition. */
45604 #define FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_SHIFT)) & FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_MASK)
45605 /*! @} */
45606 
45607 /*! @name FC_SCRAMBLER_CTRL - Frame Composer Scrambler Control */
45608 /*! @{ */
45609 
45610 #define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_MASK (0x1U)
45611 #define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_SHIFT (0U)
45612 /*! scrambler_on - When set (1'b1), this field activates the HDMI 2. */
45613 #define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_SHIFT)) & FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_MASK)
45614 
45615 #define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_MASK (0x10U)
45616 #define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_SHIFT (4U)
45617 /*! scrambler_ucp_line - Debug register. */
45618 #define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_SHIFT)) & FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_MASK)
45619 /*! @} */
45620 
45621 /*! @name FC_MULTISTREAM_CTRL - Frame Composer Multi-Stream Audio Control */
45622 /*! @{ */
45623 
45624 #define FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_MASK (0x1U)
45625 #define FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_SHIFT (0U)
45626 /*! fc_mas_packet_en - This field, when set (1'b1), activates the HDMI 2. */
45627 #define FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_SHIFT)) & FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_MASK)
45628 /*! @} */
45629 
45630 /*! @name FC_PACKET_TX_EN - Frame Composer Packet Transmission Control */
45631 /*! @{ */
45632 
45633 #define FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_MASK (0x1U)
45634 #define FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_SHIFT (0U)
45635 /*! acr_tx_en - ACR packet transmission control 1b: Transmission enabled 0b: Transmission disabled */
45636 #define FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_MASK)
45637 
45638 #define FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_MASK (0x2U)
45639 #define FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_SHIFT (1U)
45640 /*! gcp_tx_en - GCP transmission control 1b: Transmission enabled 0b: Transmission disabled */
45641 #define FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_MASK)
45642 
45643 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_MASK (0x4U)
45644 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_SHIFT (2U)
45645 /*! avi_tx_en - AVI packet transmission control 1b: Transmission enabled 0b: Transmission disabled */
45646 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_MASK)
45647 
45648 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_MASK (0x8U)
45649 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_SHIFT (3U)
45650 /*! audi_tx_en - AUDI packet transmission control 1b: Transmission enabled 0b: Transmission disabled */
45651 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_MASK)
45652 
45653 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_MASK (0x10U)
45654 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_SHIFT (4U)
45655 /*! aut_tx_en - ACP, SPD, VSIF, ISRC1, and SRC2 packet transmission control 1b: Transmission enabled 0b: Transmission disabled */
45656 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_MASK)
45657 
45658 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_MASK (0x20U)
45659 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_SHIFT (5U)
45660 /*! amp_tx_en - AMP transmission control 1b: Transmission enabled 0b: Transmission disabled */
45661 #define FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_MASK)
45662 
45663 #define FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_MASK (0x40U)
45664 #define FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_SHIFT (6U)
45665 /*! nvbi_tx_en - NTSC VBI transmission control 1b: Transmission enabled 0b: Transmission disabled */
45666 #define FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_MASK)
45667 
45668 #define FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_MASK (0x80U)
45669 #define FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_SHIFT (7U)
45670 /*! drm_tx_en - DRM transmission control 1b: Transmission enabled 0b: Transmission disabled */
45671 #define FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_MASK)
45672 /*! @} */
45673 
45674 /*! @name FC_ACTSPC_HDLR_CFG - Frame Composer Active Space Control */
45675 /*! @{ */
45676 
45677 #define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_MASK (0x1U)
45678 #define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_SHIFT (0U)
45679 /*! actspc_hdlr_en - Active Space Handler Control 1b: Fixed active space value mode enabled. */
45680 #define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_SHIFT)) & FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_MASK)
45681 
45682 #define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_MASK (0x2U)
45683 #define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_SHIFT (1U)
45684 /*! actspc_hdlr_tgl - Active Space handler control 1b: Active space 1 value is different from Active Space 2 value. */
45685 #define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_SHIFT)) & FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_MASK)
45686 /*! @} */
45687 
45688 /*! @name FC_INVACT_2D_0 - Frame Composer Input Video 2D VActive Pixels Register 0 */
45689 /*! @{ */
45690 
45691 #define FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_MASK (0xFFU)
45692 #define FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_SHIFT (0U)
45693 /*! fc_invact_2d_0 - 2D Input video vertical active pixel region width. */
45694 #define FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_SHIFT)) & FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_MASK)
45695 /*! @} */
45696 
45697 /*! @name FC_INVACT_2D_1 - Frame Composer Input Video VActive pixels Register 1 */
45698 /*! @{ */
45699 
45700 #define FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_MASK (0xFU)
45701 #define FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_SHIFT (0U)
45702 /*! fc_invact_2d_1 - 2D Input video vertical active pixel region width. */
45703 #define FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_SHIFT)) & FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_MASK)
45704 /*! @} */
45705 
45706 /*! @name FC_GMD_STAT - Frame Composer GMD Packet Status Register Gamut metadata packet status bit information for no_current_gmd, next_gmd_field, gmd_packet_sequence and current_gamut_seq_num. */
45707 /*! @{ */
45708 
45709 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_MASK (0xFU)
45710 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_SHIFT (0U)
45711 /*! igmdcurrent_gamut_seq_num - Gamut scheduling: Current Gamut packet sequence number */
45712 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_MASK)
45713 
45714 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_MASK (0x30U)
45715 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_SHIFT (4U)
45716 /*! igmdpacket_seq - Gamut scheduling: Gamut packet sequence */
45717 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_MASK)
45718 
45719 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_MASK (0x40U)
45720 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_SHIFT (6U)
45721 /*! igmddnext_field - Gamut scheduling: Gamut Next field */
45722 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_MASK)
45723 
45724 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_MASK (0x80U)
45725 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_SHIFT (7U)
45726 /*! igmdno_crnt_gbd - Gamut scheduling: No current gamut data */
45727 #define FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_MASK)
45728 /*! @} */
45729 
45730 /*! @name FC_GMD_EN - Frame Composer GMD Packet Enable Register This register enables Gamut metadata (GMD) packet transmission. */
45731 /*! @{ */
45732 
45733 #define FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_MASK (0x1U)
45734 #define FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_SHIFT (0U)
45735 /*! gmdenabletx - Gamut Metadata packet transmission enable (1b) */
45736 #define FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_SHIFT)) & FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_MASK)
45737 /*! @} */
45738 
45739 /*! @name FC_GMD_UP - Frame Composer GMD Packet Update Register This register performs an GMD packet content update according to the configured packet body (FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB). */
45740 /*! @{ */
45741 
45742 #define FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_MASK (0x1U)
45743 #define FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_SHIFT (0U)
45744 /*! gmdupdatepacket - Gamut Metadata packet update */
45745 #define FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_SHIFT)) & FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_MASK)
45746 /*! @} */
45747 
45748 /*! @name FC_GMD_CONF - Frame Composer GMD Packet Schedule Configuration Register This register configures the number of GMD packets to be inserted per frame (starting always in the line where the active Vsync appears) and the line spacing between the transmitted GMD packets. */
45749 /*! @{ */
45750 
45751 #define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_MASK (0xFU)
45752 #define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_SHIFT (0U)
45753 /*! gmdpacketlinespacing - Number of line spacing between the transmitted GMD packets */
45754 #define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_MASK)
45755 
45756 #define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_MASK (0xF0U)
45757 #define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_SHIFT (4U)
45758 /*! gmdpacketsinframe - Number of GMD packets per frame or video field (profile P0) */
45759 #define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_MASK)
45760 /*! @} */
45761 
45762 /*! @name FC_GMD_HB - Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits. */
45763 /*! @{ */
45764 
45765 #define FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_MASK (0xFU)
45766 #define FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_SHIFT (0U)
45767 /*! gmdaffected_gamut_seq_num - Affected gamut sequence number */
45768 #define FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_SHIFT)) & FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_MASK)
45769 
45770 #define FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_MASK (0x70U)
45771 #define FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_SHIFT (4U)
45772 /*! gmdgbd_profile - GMD profile bits. */
45773 #define FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_SHIFT)) & FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_MASK)
45774 /*! @} */
45775 
45776 /*! @name FC_AMP_HB1 - Frame Composer AMP Packet Header Register 1 */
45777 /*! @{ */
45778 
45779 #define FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_MASK (0xFFU)
45780 #define FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_SHIFT (0U)
45781 /*! fc_amp_hb0 - Frame Composer AMP Packet Header Register 1 */
45782 #define FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_SHIFT)) & FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_MASK)
45783 /*! @} */
45784 
45785 /*! @name FC_AMP_HB2 - Frame Composer AMP Packet Header Register 2 */
45786 /*! @{ */
45787 
45788 #define FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_MASK (0xFFU)
45789 #define FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_SHIFT (0U)
45790 /*! fc_amp_hb1 - Frame Composer AMP Packet Header Register 2 */
45791 #define FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1(x)   (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_SHIFT)) & FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_MASK)
45792 /*! @} */
45793 
45794 /*! @name FC_NVBI_HB1 - Frame Composer NTSC VBI Packet Header Register 1 */
45795 /*! @{ */
45796 
45797 #define FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_MASK (0xFFU)
45798 #define FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_SHIFT (0U)
45799 /*! fc_nvbi_hb0 - Frame Composer NTSC VBI Packet Header Register 1 */
45800 #define FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_SHIFT)) & FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_MASK)
45801 /*! @} */
45802 
45803 /*! @name FC_NVBI_HB2 - Frame Composer NTSC VBI Packet Header Register 2 */
45804 /*! @{ */
45805 
45806 #define FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_MASK (0xFFU)
45807 #define FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_SHIFT (0U)
45808 /*! fc_nvbi_hb1 - Frame Composer NTSC VBI Packet Header Register 2 */
45809 #define FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_SHIFT)) & FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_MASK)
45810 /*! @} */
45811 
45812 /*! @name FC_DRM_UP - Frame Composer DRM Packet Update Register This register performs an DRM packet content update according to the configured packet body (FC_DRM_PB0 to FC_DRM_PB27) and packet header (FC_DRM_HB). */
45813 /*! @{ */
45814 
45815 #define FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_MASK (0x1U)
45816 #define FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_SHIFT (0U)
45817 /*! drmpacketupdate - DRM packet update */
45818 #define FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_SHIFT)) & FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_MASK)
45819 /*! @} */
45820 
45821 /*! @name FC_DBGFORCE - Frame Composer video/audio Force Enable Register This register allows to force the controller to output audio and video data the values configured in the FC_DBGAUD and FC_DBGTMDS registers. */
45822 /*! @{ */
45823 
45824 #define FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_MASK (0x1U)
45825 #define FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_SHIFT (0U)
45826 /*! forcevideo - Force fixed video output with FC_DBGTMDSx register contents. */
45827 #define FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_SHIFT)) & FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_MASK)
45828 
45829 #define FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_MASK (0x10U)
45830 #define FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_SHIFT (4U)
45831 /*! forceaudio - Force fixed audio output with FC_DBGAUDxCHx register contents. */
45832 #define FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO(x)  (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_SHIFT)) & FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_MASK)
45833 /*! @} */
45834 
45835 /*! @name FC_DBGAUD0CH0 - Frame Composer Audio Data Channel 0 Register 0 Configures the audio fixed data to be used in channel 0 when in fixed audio selection. */
45836 /*! @{ */
45837 
45838 #define FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_MASK (0xFFU)
45839 #define FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_SHIFT (0U)
45840 /*! fc_dbgaud0ch0 - Frame Composer Audio Data Channel 0 Register 0 */
45841 #define FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_MASK)
45842 /*! @} */
45843 
45844 /*! @name FC_DBGAUD1CH0 - Frame Composer Audio Data Channel 0 Register 1 Configures the audio fixed data to be used in channel 0 when in fixed audio selection. */
45845 /*! @{ */
45846 
45847 #define FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_MASK (0xFFU)
45848 #define FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_SHIFT (0U)
45849 /*! fc_dbgaud1ch0 - Frame Composer Audio Data Channel 0 Register 1 */
45850 #define FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_MASK)
45851 /*! @} */
45852 
45853 /*! @name FC_DBGAUD2CH0 - Frame Composer Audio Data Channel 0 Register 2 Configures the audio fixed data to be used in channel 0 when in fixed audio selection. */
45854 /*! @{ */
45855 
45856 #define FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_MASK (0xFFU)
45857 #define FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_SHIFT (0U)
45858 /*! fc_dbgaud2ch0 - Frame Composer Audio Data Channel 0 Register 2 */
45859 #define FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_MASK)
45860 /*! @} */
45861 
45862 /*! @name FC_DBGAUD0CH1 - Frame Composer Audio Data Channel 1 Register 0 Configures the audio fixed data to be used in channel 1 when in fixed audio selection. */
45863 /*! @{ */
45864 
45865 #define FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_MASK (0xFFU)
45866 #define FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_SHIFT (0U)
45867 /*! fc_dbgaud0ch1 - Frame Composer Audio Data Channel 1 Register 0 */
45868 #define FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_MASK)
45869 /*! @} */
45870 
45871 /*! @name FC_DBGAUD1CH1 - Frame Composer Audio Data Channel 1 Register 1 Configures the audio fixed data to be used in channel 1 when in fixed audio selection. */
45872 /*! @{ */
45873 
45874 #define FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_MASK (0xFFU)
45875 #define FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_SHIFT (0U)
45876 /*! fc_dbgaud1ch1 - Frame Composer Audio Data Channel 1 Register 1 */
45877 #define FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_MASK)
45878 /*! @} */
45879 
45880 /*! @name FC_DBGAUD2CH1 - Frame Composer Audio Data Channel 1 Register 2 Configures the audio fixed data to be used in channel 1 when in fixed audio selection. */
45881 /*! @{ */
45882 
45883 #define FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_MASK (0xFFU)
45884 #define FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_SHIFT (0U)
45885 /*! fc_dbgaud2ch1 - Frame Composer Audio Data Channel 1 Register 2 */
45886 #define FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_MASK)
45887 /*! @} */
45888 
45889 /*! @name FC_DBGAUD0CH2 - Frame Composer Audio Data Channel 2 Register 0 Configures the audio fixed data to be used in channel 2 when in fixed audio selection. */
45890 /*! @{ */
45891 
45892 #define FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_MASK (0xFFU)
45893 #define FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_SHIFT (0U)
45894 /*! fc_dbgaud0ch2 - Frame Composer Audio Data Channel 2 Register 0 */
45895 #define FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_MASK)
45896 /*! @} */
45897 
45898 /*! @name FC_DBGAUD1CH2 - Frame Composer Audio Data Channel 2 Register 1 Configures the audio fixed data to be used in channel 2 when in fixed audio selection. */
45899 /*! @{ */
45900 
45901 #define FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_MASK (0xFFU)
45902 #define FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_SHIFT (0U)
45903 /*! fc_dbgaud1ch2 - Frame Composer Audio Data Channel 2 Register 1 */
45904 #define FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_MASK)
45905 /*! @} */
45906 
45907 /*! @name FC_DBGAUD2CH2 - Frame Composer Audio Data Channel 2 Register 2 Configures the audio fixed data to be used in channel 2 when in fixed audio selection. */
45908 /*! @{ */
45909 
45910 #define FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_MASK (0xFFU)
45911 #define FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_SHIFT (0U)
45912 /*! fc_dbgaud2ch2 - Frame Composer Audio Data Channel 2 Register 2 */
45913 #define FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_MASK)
45914 /*! @} */
45915 
45916 /*! @name FC_DBGAUD0CH3 - Frame Composer Audio Data Channel 3 Register 0 Configures the audio fixed data to be used in channel 3 when in fixed audio selection. */
45917 /*! @{ */
45918 
45919 #define FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_MASK (0xFFU)
45920 #define FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_SHIFT (0U)
45921 /*! fc_dbgaud0ch3 - Frame Composer Audio Data Channel 3 Register 0 */
45922 #define FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_MASK)
45923 /*! @} */
45924 
45925 /*! @name FC_DBGAUD1CH3 - Frame Composer Audio Data Channel 3 Register 1 Configures the audio fixed data to be used in channel 3 when in fixed audio selection. */
45926 /*! @{ */
45927 
45928 #define FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_MASK (0xFFU)
45929 #define FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_SHIFT (0U)
45930 /*! fc_dbgaud1ch3 - Frame Composer Audio Data Channel 3 Register 1 */
45931 #define FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_MASK)
45932 /*! @} */
45933 
45934 /*! @name FC_DBGAUD2CH3 - Frame Composer Audio Data Channel 3 Register 2 Configures the audio fixed data to be used in channel 3 when in fixed audio selection. */
45935 /*! @{ */
45936 
45937 #define FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_MASK (0xFFU)
45938 #define FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_SHIFT (0U)
45939 /*! fc_dbgaud2ch3 - Frame Composer Audio Data Channel 3 Register 2 */
45940 #define FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_MASK)
45941 /*! @} */
45942 
45943 /*! @name FC_DBGAUD0CH4 - Frame Composer Audio Data Channel 4 Register 0 Configures the audio fixed data to be used in channel 4 when in fixed audio selection. */
45944 /*! @{ */
45945 
45946 #define FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_MASK (0xFFU)
45947 #define FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_SHIFT (0U)
45948 /*! fc_dbgaud0ch4 - Frame Composer Audio Data Channel 4 Register 0 */
45949 #define FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_MASK)
45950 /*! @} */
45951 
45952 /*! @name FC_DBGAUD1CH4 - Frame Composer Audio Data Channel 4 Register 1 Configures the audio fixed data to be used in channel 4 when in fixed audio selection. */
45953 /*! @{ */
45954 
45955 #define FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_MASK (0xFFU)
45956 #define FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_SHIFT (0U)
45957 /*! fc_dbgaud1ch4 - Frame Composer Audio Data Channel 4 Register 1 */
45958 #define FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_MASK)
45959 /*! @} */
45960 
45961 /*! @name FC_DBGAUD2CH4 - Frame Composer Audio Data Channel 4 Register 2 Configures the audio fixed data to be used in channel 4 when in fixed audio selection. */
45962 /*! @{ */
45963 
45964 #define FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_MASK (0xFFU)
45965 #define FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_SHIFT (0U)
45966 /*! fc_dbgaud2ch4 - Frame Composer Audio Data Channel 4 Register 2 */
45967 #define FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_MASK)
45968 /*! @} */
45969 
45970 /*! @name FC_DBGAUD0CH5 - Frame Composer Audio Data Channel 5 Register 0 Configures the audio fixed data to be used in channel 5 when in fixed audio selection. */
45971 /*! @{ */
45972 
45973 #define FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_MASK (0xFFU)
45974 #define FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_SHIFT (0U)
45975 /*! fc_dbgaud0ch5 - Frame Composer Audio Data Channel 5 Register 0 */
45976 #define FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_MASK)
45977 /*! @} */
45978 
45979 /*! @name FC_DBGAUD1CH5 - Frame Composer Audio Data Channel 5 Register 1 Configures the audio fixed data to be used in channel 5 when in fixed audio selection. */
45980 /*! @{ */
45981 
45982 #define FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_MASK (0xFFU)
45983 #define FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_SHIFT (0U)
45984 /*! fc_dbgaud1ch5 - Frame Composer Audio Data Channel 5 Register 1 */
45985 #define FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_MASK)
45986 /*! @} */
45987 
45988 /*! @name FC_DBGAUD2CH5 - Frame Composer Audio Data Channel 5 Register 2 Configures the audio fixed data to be used in channel 5 when in fixed audio selection. */
45989 /*! @{ */
45990 
45991 #define FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_MASK (0xFFU)
45992 #define FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_SHIFT (0U)
45993 /*! fc_dbgaud2ch5 - Frame Composer Audio Data Channel 5 Register 2 */
45994 #define FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_MASK)
45995 /*! @} */
45996 
45997 /*! @name FC_DBGAUD0CH6 - Frame Composer Audio Data Channel 6 Register 0 Configures the audio fixed data to be used in channel 6 when in fixed audio selection. */
45998 /*! @{ */
45999 
46000 #define FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_MASK (0xFFU)
46001 #define FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_SHIFT (0U)
46002 /*! fc_dbgaud0ch6 - Frame Composer Audio Data Channel 6 Register 0 */
46003 #define FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_MASK)
46004 /*! @} */
46005 
46006 /*! @name FC_DBGAUD1CH6 - Frame Composer Audio Data Channel 6 Register 1 Configures the audio fixed data to be used in channel 6 when in fixed audio selection. */
46007 /*! @{ */
46008 
46009 #define FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_MASK (0xFFU)
46010 #define FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_SHIFT (0U)
46011 /*! fc_dbgaud1ch6 - Frame Composer Audio Data Channel 6 Register 1 */
46012 #define FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_MASK)
46013 /*! @} */
46014 
46015 /*! @name FC_DBGAUD2CH6 - Frame Composer Audio Data Channel 6 Register 2 Configures the audio fixed data to be used in channel 6 when in fixed audio selection. */
46016 /*! @{ */
46017 
46018 #define FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_MASK (0xFFU)
46019 #define FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_SHIFT (0U)
46020 /*! fc_dbgaud2ch6 - Frame Composer Audio Data Channel 6 Register 2 */
46021 #define FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_MASK)
46022 /*! @} */
46023 
46024 /*! @name FC_DBGAUD0CH7 - Frame Composer Audio Data Channel 7 Register 0 Configures the audio fixed data to be used in channel 7 when in fixed audio selection. */
46025 /*! @{ */
46026 
46027 #define FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_MASK (0xFFU)
46028 #define FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_SHIFT (0U)
46029 /*! fc_dbgaud0ch7 - Frame Composer Audio Data Channel 7 Register 0 */
46030 #define FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_MASK)
46031 /*! @} */
46032 
46033 /*! @name FC_DBGAUD1CH7 - Frame Composer Audio Data Channel 7 Register 1 Configures the audio fixed data to be used in channel 7 when in fixed audio selection. */
46034 /*! @{ */
46035 
46036 #define FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_MASK (0xFFU)
46037 #define FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_SHIFT (0U)
46038 /*! fc_dbgaud1ch7 - Frame Composer Audio Data Channel 7 Register 1 */
46039 #define FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_MASK)
46040 /*! @} */
46041 
46042 /*! @name FC_DBGAUD2CH7 - Frame Composer Audio Data Channel 7 Register 2 Configures the audio fixed data to be used in channel 7 when in fixed audio selection. */
46043 /*! @{ */
46044 
46045 #define FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_MASK (0xFFU)
46046 #define FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_SHIFT (0U)
46047 /*! fc_dbgaud2ch7 - Frame Composer Audio Data Channel 7 Register 2 */
46048 #define FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_MASK)
46049 /*! @} */
46050 
46051 
46052 /*!
46053  * @}
46054  */ /* end of group FRAMECOMPOSER_Register_Masks */
46055 
46056 
46057 /* FRAMECOMPOSER - Peripheral instance base addresses */
46058 /** Peripheral FRAMECOMPOSER base address */
46059 #define FRAMECOMPOSER_BASE                       (0x32FD9000u)
46060 /** Peripheral FRAMECOMPOSER base pointer */
46061 #define FRAMECOMPOSER                            ((FRAMECOMPOSER_Type *)FRAMECOMPOSER_BASE)
46062 /** Array initializer of FRAMECOMPOSER peripheral base addresses */
46063 #define FRAMECOMPOSER_BASE_ADDRS                 { FRAMECOMPOSER_BASE }
46064 /** Array initializer of FRAMECOMPOSER peripheral base pointers */
46065 #define FRAMECOMPOSER_BASE_PTRS                  { FRAMECOMPOSER }
46066 
46067 /*!
46068  * @}
46069  */ /* end of group FRAMECOMPOSER_Peripheral_Access_Layer */
46070 
46071 
46072 /* ----------------------------------------------------------------------------
46073    -- GLUE_USB Peripheral Access Layer
46074    ---------------------------------------------------------------------------- */
46075 
46076 /*!
46077  * @addtogroup GLUE_USB_Peripheral_Access_Layer GLUE_USB Peripheral Access Layer
46078  * @{
46079  */
46080 
46081 /** GLUE_USB - Register Layout Typedef */
46082 typedef struct {
46083   __IO uint32_t USB_CTL0_ADDR;                     /**< USB_CTL0_ADDR, offset: 0x0 */
46084   __IO uint32_t USB_CTL1_ADDR;                     /**< USB_CTL1_ADDR, offset: 0x4 */
46085        uint8_t RESERVED_0[24];
46086   __I  uint32_t USB_STS0_ADDR;                     /**< USB_STS0_ADDR, offset: 0x20 */
46087        uint8_t RESERVED_1[28];
46088   __IO uint32_t PHY_CTL0_ADDR;                     /**< PHY_CTL0_ADDR, offset: 0x40 */
46089   __IO uint32_t PHY_CTL1_ADDR;                     /**< PHY_CTL1_ADDR, offset: 0x44 */
46090   __IO uint32_t PHY_CTL2_ADDR;                     /**< PHY_CTL2_ADDR, offset: 0x48 */
46091   __IO uint32_t PHY_CTL3_ADDR;                     /**< PHY_CTL3_ADDR, offset: 0x4C */
46092   __IO uint32_t PHY_CTL4_ADDR;                     /**< PHY_CTL4_ADDR, offset: 0x50 */
46093   __IO uint32_t PHY_CTL5_ADDR;                     /**< PHY_CTL5_ADDR, offset: 0x54 */
46094   __IO uint32_t PHY_CTL6_ADDR;                     /**< PHY_CTL6_ADDR, offset: 0x58 */
46095        uint8_t RESERVED_2[36];
46096   __IO uint32_t PHY_STS0_ADDR;                     /**< PHY_STS0_ADDR, offset: 0x80 */
46097 } GLUE_USB_Type;
46098 
46099 /* ----------------------------------------------------------------------------
46100    -- GLUE_USB Register Masks
46101    ---------------------------------------------------------------------------- */
46102 
46103 /*!
46104  * @addtogroup GLUE_USB_Register_Masks GLUE_USB Register Masks
46105  * @{
46106  */
46107 
46108 /*! @name USB_CTL0_ADDR - USB_CTL0_ADDR */
46109 /*! @{ */
46110 
46111 #define GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_MASK (0x40U)
46112 #define GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_SHIFT (6U)
46113 /*! host_u2_port_disable - USB 2.0 Port Disable control.
46114  *  0b0..Port Enabled
46115  *  0b1..Port Disabled. When '1', this signal stops reporting connect/disconnect events the port and keeps the port in disabled state.
46116  */
46117 #define GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_MASK)
46118 
46119 #define GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_MASK (0x80U)
46120 #define GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_SHIFT (7U)
46121 /*! host_u3_port_disable - USB 3.0 SS Port Disable control.
46122  *  0b0..Port Enabled
46123  *  0b1..Port Disabled
46124  */
46125 #define GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_MASK)
46126 
46127 #define GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_MASK (0xF00U)
46128 #define GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_SHIFT (8U)
46129 /*! bus_filter_bypass - Bus Filter Bypass. */
46130 #define GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_MASK)
46131 
46132 #define GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_MASK (0x1000U)
46133 #define GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_SHIFT (12U)
46134 /*! host_port_power_control_present - This port defines the bit [3] of Capability Parameters (HCCPARAMS).
46135  *  0b0..Indicates that the port does not have port power switches.
46136  *  0b1..Indicates that the port has port power switches.
46137  */
46138 #define GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_MASK)
46139 
46140 #define GLUE_USB_USB_CTL0_ADDR_XHC_BME_MASK      (0x4000U)
46141 #define GLUE_USB_USB_CTL0_ADDR_XHC_BME_SHIFT     (14U)
46142 /*! xhc_bme - Disable the bus mastering capability of the xHC
46143  *  0b0..Bus mastering capability is disabled. The host controller cannot use the bus master interface.
46144  *  0b1..Bus mastering capability is enabled.
46145  */
46146 #define GLUE_USB_USB_CTL0_ADDR_XHC_BME(x)        (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_XHC_BME_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_XHC_BME_MASK)
46147 
46148 #define GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_MASK (0x3F0000U)
46149 #define GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_SHIFT (16U)
46150 /*! fladj_30mhz_reg - HS Jitter Adjustment. */
46151 #define GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_MASK)
46152 
46153 #define GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_MASK (0xC00000U)
46154 #define GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_SHIFT (22U)
46155 /*! hub_port_perm_attach - Indicates if the device attached to a downstream port is permanently attached or not.
46156  *  0b00..Not permanently attached
46157  *  0b01..Permanently attached
46158  */
46159 #define GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_MASK)
46160 
46161 #define GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_MASK (0x1000000U)
46162 #define GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_SHIFT (24U)
46163 /*! utmi_iddig_sel - iddig source select signal
46164  *  0b0..USB PHY ID0
46165  *  0b1..GPIO PAD
46166  */
46167 #define GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_MASK)
46168 
46169 #define GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_MASK (0x2000000U)
46170 #define GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_SHIFT (25U)
46171 /*! StartRxDetU3RxDet - StartRxdetU3RxDet of USB 3.0 SS Ports */
46172 #define GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_MASK)
46173 
46174 #define GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_MASK (0x4000000U)
46175 #define GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_SHIFT (26U)
46176 /*! DisRxDetU3RxDet - DisRxDetU3RxDet of USB 3.0 SS Ports */
46177 #define GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_MASK)
46178 /*! @} */
46179 
46180 /*! @name USB_CTL1_ADDR - USB_CTL1_ADDR */
46181 /*! @{ */
46182 
46183 #define GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_MASK  (0x10000U)
46184 #define GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_SHIFT (16U)
46185 /*! oc_polarity - Overcurrent polarity
46186  *  0b0..Active high
46187  *  0b1..Active low
46188  */
46189 #define GLUE_USB_USB_CTL1_ADDR_OC_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_SHIFT)) & GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_MASK)
46190 
46191 #define GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_MASK (0x20000U)
46192 #define GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_SHIFT (17U)
46193 /*! power_polarity - Power polarity
46194  *  0b0..Active high
46195  *  0b1..Active low
46196  */
46197 #define GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_SHIFT)) & GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_MASK)
46198 /*! @} */
46199 
46200 /*! @name USB_STS0_ADDR - USB_STS0_ADDR */
46201 /*! @{ */
46202 
46203 #define GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_MASK (0xFFFU)
46204 #define GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_SHIFT (0U)
46205 /*! host_current_belt - Current BELT Value */
46206 #define GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_SHIFT)) & GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_MASK)
46207 
46208 #define GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_MASK (0x1000U)
46209 #define GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_SHIFT (12U)
46210 /*! host_system_err - Host System Error */
46211 #define GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_SHIFT)) & GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_MASK)
46212 
46213 #define GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_MASK  (0x2000U)
46214 #define GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_SHIFT (13U)
46215 /*! bc_chirp_on - When asserted indicates an imminent chirp signal. */
46216 #define GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_SHIFT)) & GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_MASK)
46217 
46218 #define GLUE_USB_USB_STS0_ADDR_PME_GENERATION_MASK (0x4000U)
46219 #define GLUE_USB_USB_STS0_ADDR_PME_GENERATION_SHIFT (14U)
46220 /*! pme_generation - PME# Generation. */
46221 #define GLUE_USB_USB_STS0_ADDR_PME_GENERATION(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_PME_GENERATION_SHIFT)) & GLUE_USB_USB_STS0_ADDR_PME_GENERATION_MASK)
46222 
46223 #define GLUE_USB_USB_STS0_ADDR_IDDIG_MASK        (0x8000U)
46224 #define GLUE_USB_USB_STS0_ADDR_IDDIG_SHIFT       (15U)
46225 /*! IDDIG - This controller signal indicates whether the connected plug is a mini-A or mini-B plug.
46226  *  0b0..Connected plug is a mini-A plug.
46227  *  0b1..Connected plug is a mini-B plug.
46228  */
46229 #define GLUE_USB_USB_STS0_ADDR_IDDIG(x)          (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_IDDIG_SHIFT)) & GLUE_USB_USB_STS0_ADDR_IDDIG_MASK)
46230 
46231 #define GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_MASK (0x10000U)
46232 #define GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_SHIFT (16U)
46233 /*! DisRxDetU3RxDet_ack - DisRxDetU3RxDet_ack of USB 3.0 SS Ports */
46234 #define GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_SHIFT)) & GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_MASK)
46235 /*! @} */
46236 
46237 /*! @name PHY_CTL0_ADDR - PHY_CTL0_ADDR */
46238 /*! @{ */
46239 
46240 #define GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_MASK   (0x4U)
46241 #define GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_SHIFT  (2U)
46242 /*! ref_ssp_en - Reference Clock Enable for SS function. */
46243 #define GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN(x)     (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_MASK)
46244 
46245 #define GLUE_USB_PHY_CTL0_ADDR_FSEL_MASK         (0x7E0U)
46246 #define GLUE_USB_PHY_CTL0_ADDR_FSEL_SHIFT        (5U)
46247 /*! fsel - fsel
46248  *  0b100111..100MHz ref clock
46249  *  0b101010..24MHz ref clock
46250  */
46251 #define GLUE_USB_PHY_CTL0_ADDR_FSEL(x)           (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_FSEL_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_FSEL_MASK)
46252 
46253 #define GLUE_USB_PHY_CTL0_ADDR_SSC_EN_MASK       (0x800U)
46254 #define GLUE_USB_PHY_CTL0_ADDR_SSC_EN_SHIFT      (11U)
46255 /*! ssc_en - Spread Spectrum Enable */
46256 #define GLUE_USB_PHY_CTL0_ADDR_SSC_EN(x)         (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_SSC_EN_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_SSC_EN_MASK)
46257 
46258 #define GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_MASK (0x1FF000U)
46259 #define GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_SHIFT (12U)
46260 /*! ssc_ref_clk_sel - Spread Spectrum Reference Clock Shifting */
46261 #define GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_MASK)
46262 
46263 #define GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_MASK    (0xE00000U)
46264 #define GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_SHIFT   (21U)
46265 /*! ssc_range - Spread Spectrum Clock Range
46266  *  0b000..4980
46267  *  0b001..4492
46268  *  0b010..4003
46269  */
46270 #define GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_MASK)
46271 /*! @} */
46272 
46273 /*! @name PHY_CTL1_ADDR - PHY_CTL1_ADDR */
46274 /*! @{ */
46275 
46276 #define GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_MASK    (0x1U)
46277 #define GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_SHIFT   (0U)
46278 /*! phy_reset - USB3.0 PHY Signal */
46279 #define GLUE_USB_PHY_CTL1_ADDR_PHY_RESET(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_MASK)
46280 
46281 #define GLUE_USB_PHY_CTL1_ADDR_COMMONONN_MASK    (0x2U)
46282 #define GLUE_USB_PHY_CTL1_ADDR_COMMONONN_SHIFT   (1U)
46283 /*! COMMONONN - Common Block Power-Down Control */
46284 #define GLUE_USB_PHY_CTL1_ADDR_COMMONONN(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_COMMONONN_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_COMMONONN_MASK)
46285 
46286 #define GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_MASK    (0x8000U)
46287 #define GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_SHIFT   (15U)
46288 /*! rtune_req - Resistor Tune Request */
46289 #define GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_MASK)
46290 
46291 #define GLUE_USB_PHY_CTL1_ADDR_ACAENB0_MASK      (0x10000U)
46292 #define GLUE_USB_PHY_CTL1_ADDR_ACAENB0_SHIFT     (16U)
46293 /*! ACAENB0 - Battery Charging Source Select */
46294 #define GLUE_USB_PHY_CTL1_ADDR_ACAENB0(x)        (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_ACAENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_ACAENB0_MASK)
46295 
46296 #define GLUE_USB_PHY_CTL1_ADDR_DCDENB0_MASK      (0x20000U)
46297 #define GLUE_USB_PHY_CTL1_ADDR_DCDENB0_SHIFT     (17U)
46298 /*! DCDENB0 - Data Contact Detection Enable */
46299 #define GLUE_USB_PHY_CTL1_ADDR_DCDENB0(x)        (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_DCDENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_DCDENB0_MASK)
46300 
46301 #define GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_MASK     (0x40000U)
46302 #define GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_SHIFT    (18U)
46303 /*! CHRGSEL0 - Battery Charging Source Select */
46304 #define GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0(x)       (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_MASK)
46305 
46306 #define GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_MASK  (0x80000U)
46307 #define GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_SHIFT (19U)
46308 /*! VDATSRCENB0 - Battery Charging Sourcing Select */
46309 #define GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_MASK)
46310 
46311 #define GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_MASK  (0x100000U)
46312 #define GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_SHIFT (20U)
46313 /*! VDATDETENB0 - Battery Charging Attach/Connect Detection Enable */
46314 #define GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_MASK)
46315 /*! @} */
46316 
46317 /*! @name PHY_CTL2_ADDR - PHY_CTL2_ADDR */
46318 /*! @{ */
46319 
46320 #define GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_MASK   (0x20U)
46321 #define GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_SHIFT  (5U)
46322 /*! FSDATAEXT0 - USB 1.1 SE0 Generation */
46323 #define GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0(x)     (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_MASK)
46324 
46325 #define GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_MASK    (0x40U)
46326 #define GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_SHIFT   (6U)
46327 /*! FSSE0EXT0 - USB 1.1 Transmit Data */
46328 #define GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_MASK)
46329 
46330 #define GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_MASK (0x80U)
46331 #define GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_SHIFT (7U)
46332 /*! FSXCVROWNER0 - UTMI+/Serial Interface Select */
46333 #define GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0(x)   (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_MASK)
46334 
46335 #define GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_MASK   (0x100U)
46336 #define GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_SHIFT  (8U)
46337 /*! TXENABLEN0 - USB 1.1 Data Enable */
46338 #define GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0(x)     (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_MASK)
46339 
46340 #define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_MASK  (0x400U)
46341 #define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_SHIFT (10U)
46342 /*! VBUSVLDEXT0 - External VBUS Valid Indicator */
46343 #define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_MASK)
46344 
46345 #define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_MASK (0x800U)
46346 #define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_SHIFT (11U)
46347 /*! VBUSVLDEXTSEL0 - Selects the VBUSVLDEXTn input or the internal Session Valid comparator to
46348  *    indicate when the VBUSn signal on the USB cable is valid.
46349  */
46350 #define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_MASK)
46351 
46352 #define GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_MASK (0x4000U)
46353 #define GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_SHIFT (14U)
46354 /*! utmi_idpullup - Analog ID Input Sample Enable */
46355 #define GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP(x)  (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_MASK)
46356 
46357 #define GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_MASK (0x10000U)
46358 #define GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_SHIFT (16U)
46359 /*! rx0loslfpsen - RX LOS LFPS Filter Enable */
46360 #define GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN(x)   (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_MASK)
46361 /*! @} */
46362 
46363 /*! @name PHY_CTL3_ADDR - PHY_CTL3_ADDR */
46364 /*! @{ */
46365 
46366 #define GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_MASK (0x7U)
46367 #define GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_SHIFT (0U)
46368 /*! COMPIDISTUNE - Disconnect Threshold Adjustment.
46369  *  0b111..+ 15.54%
46370  *  0b110..+ 11.86%
46371  *  0b101..+ 7.52%
46372  *  0b100..+ 4.08
46373  *  0b011..0 (default)
46374  *  0b010..- 3.04%
46375  *  0b001..- 6.5%
46376  *  0b000..- 9.01%
46377  */
46378 #define GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE(x)   (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_MASK)
46379 
46380 #define GLUE_USB_PHY_CTL3_ADDR_TUNE0_MASK        (0x38U)
46381 #define GLUE_USB_PHY_CTL3_ADDR_TUNE0_SHIFT       (3U)
46382 /*! TUNE0 - VBUS Valid Threshold Adjustment */
46383 #define GLUE_USB_PHY_CTL3_ADDR_TUNE0(x)          (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TUNE0_MASK)
46384 
46385 #define GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_MASK    (0x1C0U)
46386 #define GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_SHIFT   (6U)
46387 /*! SQRXTUNE0 - Squelch Threshold Adjustment
46388  *  0b111..- 22.32%
46389  *  0b110..- 16.07%
46390  *  0b101..- 10.71%
46391  *  0b100..- 5.36%
46392  *  0b011..0 (default)
46393  *  0b010..+ 5.36%
46394  *  0b001..+ 10.71%
46395  *  0b000..+ 16.07%
46396  */
46397 #define GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_MASK)
46398 
46399 #define GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_MASK  (0x1E00U)
46400 #define GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_SHIFT (9U)
46401 /*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment
46402  *  0b1111..- 3.5%
46403  *  0b0111..- 1.7%
46404  *  0b0011..0 (default)
46405  *  0b0001..+ 1.8%
46406  *  0b0000..+ 3.5%
46407  */
46408 #define GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_MASK)
46409 
46410 #define GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_MASK  (0x6000U)
46411 #define GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_SHIFT (13U)
46412 /*! TXSHXSTUNE0 - Transmitter High-Speed Crossover Adjustment.
46413  *  0b11..0 (default)
46414  *  0b10..+ 14 mV
46415  *  0b01..- 16 mV
46416  *  0b00..Reserved
46417  */
46418 #define GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_MASK)
46419 
46420 #define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_MASK (0x18000U)
46421 #define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_SHIFT (15U)
46422 /*! TXPREEMPMPTUNE0 - HS Transmitter Pre-Emphasis Current Control
46423  *  0b11..3x pre-emphasis current
46424  *  0b10..2x pre-emphasis current
46425  *  0b01..1x pre-emphasis current
46426  *  0b00..Disabled (default)
46427  */
46428 #define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_MASK)
46429 
46430 #define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_MASK (0x20000U)
46431 #define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_SHIFT (17U)
46432 #define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_MASK)
46433 
46434 #define GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_MASK   (0xC0000U)
46435 #define GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_SHIFT  (18U)
46436 #define GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0(x)     (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_MASK)
46437 
46438 #define GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_MASK  (0x300000U)
46439 #define GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_SHIFT (20U)
46440 /*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment
46441  *  0b11..- 3%
46442  *  0b10..- 1%
46443  *  0b01..0 (default)
46444  *  0b00..+ 3%
46445  */
46446 #define GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0(x)    (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_MASK)
46447 
46448 #define GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_MASK   (0x3C00000U)
46449 #define GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_SHIFT  (22U)
46450 /*! TXREFTUNE0 - HS DC Voltage Level Adjustment
46451  *  0b1111..+ 24%
46452  *  0b1110..+ 22%
46453  *  0b1101..+ 20%
46454  *  0b1100..+ 18%
46455  *  0b1011..+ 16%
46456  *  0b1010..+ 14%
46457  *  0b1001..+ 12%
46458  *  0b1000..+ 10
46459  *  0b0111..+ 8%
46460  *  0b0110..+ 6%
46461  *  0b0101..+ 4%
46462  *  0b0100..+ 2%
46463  *  0b0011..0 (default)
46464  *  0b0010..- 2%
46465  *  0b0001..- 4%
46466  *  0b0000..- 6%
46467  */
46468 #define GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0(x)     (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_MASK)
46469 
46470 #define GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_MASK     (0x1C000000U)
46471 #define GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_SHIFT    (26U)
46472 /*! ios_bias - Loss-of-Signal Detector Threshold Level Control */
46473 #define GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS(x)       (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_MASK)
46474 
46475 #define GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_MASK (0xE0000000U)
46476 #define GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_SHIFT (29U)
46477 /*! tx_vboost_lvl - TX Voltage Boost Level */
46478 #define GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL(x)  (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_MASK)
46479 /*! @} */
46480 
46481 /*! @name PHY_CTL4_ADDR - PHY_CTL4_ADDR */
46482 /*! @{ */
46483 
46484 #define GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_MASK (0x7FE0U)
46485 #define GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_SHIFT (5U)
46486 /*! pcs_rx_los_msk_val - Configurable Loss-of-Signal Mask Width */
46487 #define GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_SHIFT)) & GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_MASK)
46488 
46489 #define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_MASK (0x1F8000U)
46490 #define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_SHIFT (15U)
46491 /*! pcs_tx_deemph_3b5db - TX De-Emphasis at 3.5 dB */
46492 #define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_SHIFT)) & GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_MASK)
46493 
46494 #define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_MASK (0x7E00000U)
46495 #define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_SHIFT (21U)
46496 /*! pcs_tx_deemph_6db - TX De-Emphasis at 6 dB */
46497 #define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_SHIFT)) & GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_MASK)
46498 /*! @} */
46499 
46500 /*! @name PHY_CTL5_ADDR - PHY_CTL5_ADDR */
46501 /*! @{ */
46502 
46503 #define GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_MASK (0x7FU)
46504 #define GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_SHIFT (0U)
46505 /*! pcs_tx_swing_full - TX Amplitude (Full Swing Mode) */
46506 #define GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_SHIFT)) & GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_MASK)
46507 /*! @} */
46508 
46509 /*! @name PHY_CTL6_ADDR - PHY_CTL6_ADDR */
46510 /*! @{ */
46511 
46512 #define GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_MASK (0x4U)
46513 #define GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_SHIFT (2U)
46514 /*! lane0_tx2rx_loopbk - Loopback */
46515 #define GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_SHIFT)) & GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_MASK)
46516 
46517 #define GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_MASK (0x8U)
46518 #define GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_SHIFT (3U)
46519 /*! lane0_ext_pclk_req - External PIPE Clock Enable Request */
46520 #define GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_SHIFT)) & GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_MASK)
46521 /*! @} */
46522 
46523 /*! @name PHY_STS0_ADDR - PHY_STS0_ADDR */
46524 /*! @{ */
46525 
46526 #define GLUE_USB_PHY_STS0_ADDR_CHGDET0_MASK      (0x10U)
46527 #define GLUE_USB_PHY_STS0_ADDR_CHGDET0_SHIFT     (4U)
46528 /*! CHGDET0 - Battery Charger Detection Output */
46529 #define GLUE_USB_PHY_STS0_ADDR_CHGDET0(x)        (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_CHGDET0_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_CHGDET0_MASK)
46530 
46531 #define GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_MASK    (0x40U)
46532 #define GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_SHIFT   (6U)
46533 /*! rtune_ack - Resistor Tune Acknowledge. While asserted, indicates that a resistor tune is still in progress. */
46534 #define GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK(x)      (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_MASK)
46535 
46536 #define GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_MASK (0x40000000U)
46537 #define GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_SHIFT (30U)
46538 /*! pipe_clk_vld - USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set. */
46539 #define GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_MASK)
46540 
46541 #define GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_MASK (0x80000000U)
46542 #define GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_SHIFT (31U)
46543 /*! utmi_clk_vld - USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set. */
46544 #define GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_MASK)
46545 /*! @} */
46546 
46547 
46548 /*!
46549  * @}
46550  */ /* end of group GLUE_USB_Register_Masks */
46551 
46552 
46553 /* GLUE_USB - Peripheral instance base addresses */
46554 /** Peripheral USB1_GLUE base address */
46555 #define USB1_GLUE_BASE                           (0x381F0000u)
46556 /** Peripheral USB1_GLUE base pointer */
46557 #define USB1_GLUE                                ((GLUE_USB_Type *)USB1_GLUE_BASE)
46558 /** Peripheral USB2_GLUE base address */
46559 #define USB2_GLUE_BASE                           (0x382F0000u)
46560 /** Peripheral USB2_GLUE base pointer */
46561 #define USB2_GLUE                                ((GLUE_USB_Type *)USB2_GLUE_BASE)
46562 /** Array initializer of GLUE_USB peripheral base addresses */
46563 #define GLUE_USB_BASE_ADDRS                      { USB1_GLUE_BASE, USB2_GLUE_BASE }
46564 /** Array initializer of GLUE_USB peripheral base pointers */
46565 #define GLUE_USB_BASE_PTRS                       { USB1_GLUE, USB2_GLUE }
46566 
46567 /*!
46568  * @}
46569  */ /* end of group GLUE_USB_Peripheral_Access_Layer */
46570 
46571 
46572 /* ----------------------------------------------------------------------------
46573    -- GPC Peripheral Access Layer
46574    ---------------------------------------------------------------------------- */
46575 
46576 /*!
46577  * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
46578  * @{
46579  */
46580 
46581 /** GPC - Register Layout Typedef */
46582 typedef struct {
46583   __IO uint32_t LPCR_A53_BSC;                      /**< Basic Low power control register of A53 platform, offset: 0x0 */
46584   __IO uint32_t LPCR_A53_AD;                       /**< Advanced Low power control register of A53 platform, offset: 0x4 */
46585   __IO uint32_t LPCR_M7;                           /**< Low power control register of CPU1, offset: 0x8 */
46586        uint8_t RESERVED_0[8];
46587   __IO uint32_t SLPCR;                             /**< System low power control register, offset: 0x14 */
46588   __IO uint32_t MST_CPU_MAPPING;                   /**< MASTER LPM Handshake, offset: 0x18 */
46589        uint8_t RESERVED_1[4];
46590   __IO uint32_t MLPCR;                             /**< Memory low power control register, offset: 0x20 */
46591   __IO uint32_t PGC_ACK_SEL_A53;                   /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */
46592   __IO uint32_t PGC_ACK_SEL_M7;                    /**< PGC acknowledge signal selection of M7 platform, offset: 0x28 */
46593   __IO uint32_t MISC;                              /**< GPC Miscellaneous register, offset: 0x2C */
46594   __IO uint32_t IMR_CORE0_A53[5];                  /**< IRQ masking register 1 of A53 core0..IRQ masking register 5 of A53 core0, array offset: 0x30, array step: 0x4 */
46595   __IO uint32_t IMR_CORE1_A53[5];                  /**< IRQ masking register 1 of A53 core1..IRQ masking register 5 of A53 core1, array offset: 0x44, array step: 0x4 */
46596   __IO uint32_t IMR_M7[5];                         /**< IRQ masking register 1 of M7..IRQ masking register 5 of M7, array offset: 0x58, array step: 0x4 */
46597        uint8_t RESERVED_2[20];
46598   __I  uint32_t ISR_A53[5];                        /**< IRQ status register 1 of A53..IRQ status register 5 of A53, array offset: 0x80, array step: 0x4 */
46599   __I  uint32_t ISR_M7[5];                         /**< IRQ status register 1 of M7..IRQ status register 5 of M7, array offset: 0x94, array step: 0x4 */
46600        uint8_t RESERVED_3[40];
46601   __IO uint32_t CPU_PGC_SW_PUP_REQ;                /**< CPU PGC software power up trigger, offset: 0xD0 */
46602   __IO uint32_t MIX_PGC_SW_PUP_REQ;                /**< MIX PGC software power up trigger, offset: 0xD4 */
46603   __IO uint32_t PU_PGC_SW_PUP_REQ;                 /**< PU PGC software up trigger, offset: 0xD8 */
46604   __IO uint32_t CPU_PGC_SW_PDN_REQ;                /**< CPU PGC software down trigger, offset: 0xDC */
46605   __IO uint32_t MIX_PGC_SW_PDN_REQ;                /**< MIX PGC software power down trigger, offset: 0xE0 */
46606   __IO uint32_t PU_PGC_SW_PDN_REQ;                 /**< PU PGC software down trigger, offset: 0xE4 */
46607        uint8_t RESERVED_4[32];
46608   __I  uint32_t CPU_PGC_PUP_STATUS1;               /**< CPU PGC software up trigger status1, offset: 0x108 */
46609   __I  uint32_t A53_MIX_PGC_PUP_STATUS[3];         /**< A53 MIX software up trigger status register, array offset: 0x10C, array step: 0x4 */
46610   __I  uint32_t M7_MIX_PGC_PUP_STATUS[3];          /**< M7 MIX PGC software up trigger status register, array offset: 0x118, array step: 0x4 */
46611   __I  uint32_t A53_PU_PGC_PUP_STATUS[3];          /**< A53 PU software up trigger status register, array offset: 0x124, array step: 0x4 */
46612   __I  uint32_t M7_PU_PGC_PUP_STATUS[3];           /**< M7 PU PGC software up trigger status register, array offset: 0x130, array step: 0x4 */
46613   __I  uint32_t CPU_PGC_PDN_STATUS1;               /**< CPU PGC software dn trigger status1, offset: 0x13C */
46614   __I  uint32_t A53_MIX_PGC_PDN_STATUS[3];         /**< A53 MIX software down trigger status register, array offset: 0x140, array step: 0x4 */
46615   __I  uint32_t M7_MIX_PGC_PDN_STATUS[3];          /**< M7 MIX PGC software power down trigger status register, array offset: 0x14C, array step: 0x4 */
46616   __I  uint32_t A53_PU_PGC_PDN_STATUS[3];          /**< A53 PU PGC software down trigger status, array offset: 0x158, array step: 0x4 */
46617   __I  uint32_t M7_PU_PGC_PDN_STATUS[3];           /**< M7 PU PGC software down trigger status, array offset: 0x164, array step: 0x4 */
46618   __IO uint32_t A53_MIX_PDN_FLG;                   /**< A53 MIX PDN FLG, offset: 0x170 */
46619   __IO uint32_t A53_PU_PDN_FLG;                    /**< A53 PU PDN FLG, offset: 0x174 */
46620   __IO uint32_t M7_MIX_PDN_FLG;                    /**< M7 MIX PDN FLG, offset: 0x178 */
46621   __IO uint32_t M7_PU_PDN_FLG;                     /**< M7 PU PDN FLG, offset: 0x17C */
46622   __IO uint32_t LPCR_A53_BSC2;                     /**< Basic Low power control register of A53 platform, offset: 0x180 */
46623        uint8_t RESERVED_5[12];
46624   __IO uint32_t PU_PWRHSK;                         /**< Power handshake register, offset: 0x190 */
46625   __IO uint32_t IMR_CORE2_A53[5];                  /**< IRQ masking register 1 of A53 core2..IRQ masking register 5 of A53 core2, array offset: 0x194, array step: 0x4 */
46626   __IO uint32_t IMR_CORE3_A53[5];                  /**< IRQ masking register 1 of A53 core3..IRQ masking register 5 of A53 core3, array offset: 0x1A8, array step: 0x4 */
46627   __IO uint32_t ACK_SEL_A53_PU;                    /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1BC */
46628   __IO uint32_t ACK_SEL_A53_PU1;                   /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1C0 */
46629   __IO uint32_t ACK_SEL_M7_PU;                     /**< PGC acknowledge signal selection of M7 platform for PUs, offset: 0x1C4 */
46630   __IO uint32_t ACK_SEL_M7_PU1;                    /**< PGC acknowledge signal selection of M7 platform for PUs, offset: 0x1C8 */
46631   __IO uint32_t PGC_CPU_A53_MAPPING;               /**< PGC CPU A53 mapping, offset: 0x1CC */
46632   __IO uint32_t PGC_CPU_M7_MAPPING;                /**< PGC CPU M7 mapping, offset: 0x1D0 */
46633        uint8_t RESERVED_6[44];
46634   __IO uint32_t SLT_CFG[27];                       /**< Slot configure register for CPUs, array offset: 0x200, array step: 0x4 */
46635        uint8_t RESERVED_7[20];
46636   struct {                                         /* offset: 0x280, array step: 0x8 */
46637     __IO uint32_t SLT_CFG_PU;                        /**< Slot configure register for PGC PUs, array offset: 0x280, array step: 0x8 */
46638     __IO uint32_t SLT_CFG_PU1;                       /**< Extended slot configure register for PGC PUs, array offset: 0x284, array step: 0x8 */
46639   } SLTn_CFG_PU[27];
46640 } GPC_Type;
46641 
46642 /* ----------------------------------------------------------------------------
46643    -- GPC Register Masks
46644    ---------------------------------------------------------------------------- */
46645 
46646 /*!
46647  * @addtogroup GPC_Register_Masks GPC Register Masks
46648  * @{
46649  */
46650 
46651 /*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */
46652 /*! @{ */
46653 
46654 #define GPC_LPCR_A53_BSC_LPM0_MASK               (0x3U)
46655 #define GPC_LPCR_A53_BSC_LPM0_SHIFT              (0U)
46656 /*! LPM0
46657  *  0b00..Remain in RUN mode
46658  *  0b01..Transfer to WAIT mode
46659  *  0b10..Transfer to STOP mode
46660  *  0b11..Reserved
46661  */
46662 #define GPC_LPCR_A53_BSC_LPM0(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK)
46663 
46664 #define GPC_LPCR_A53_BSC_LPM1_MASK               (0xCU)
46665 #define GPC_LPCR_A53_BSC_LPM1_SHIFT              (2U)
46666 /*! LPM1
46667  *  0b00..Remain in RUN mode
46668  *  0b01..Transfer to WAIT mode
46669  *  0b10..Transfer to STOP mode
46670  *  0b11..Reserved
46671  */
46672 #define GPC_LPCR_A53_BSC_LPM1(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK)
46673 
46674 #define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK  (0x40U)
46675 #define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT (6U)
46676 /*! MST0_LPM_HSK_MASK - MASTER0 LPM handshake mask
46677  *  0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0
46678  *  0b1..disable MASTER0 LPM handshake, mask ACK from MASTER0
46679  */
46680 #define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK(x)    (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK)
46681 
46682 #define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK  (0x80U)
46683 #define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT (7U)
46684 /*! MST1_LPM_HSK_MASK - MASTER1 LPM handshake mask
46685  *  0b0..enable MASTER1 LPM handshake, wait ACK from MASTER1
46686  *  0b1..disable MASTER1 LPM handshake, mask ACK from MASTER1
46687  */
46688 #define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK(x)    (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK)
46689 
46690 #define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK  (0x100U)
46691 #define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT (8U)
46692 /*! MST2_LPM_HSK_MASK - MASTER2 LPM handshake mask
46693  *  0b0..enable MASTER2 LPM handshake, wait ACK from MASTER2
46694  *  0b1..disable MASTER2 LPM handshake, mask ACK from MASTER2
46695  */
46696 #define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK(x)    (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK)
46697 
46698 #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK     (0x4000U)
46699 #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT    (14U)
46700 /*! CPU_CLK_ON_LPM
46701  *  0b0..A53 clock disabled on wait/stop mode
46702  *  0b1..A53 clock enabled on wait/stop mode
46703  */
46704 #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x)       (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK)
46705 
46706 #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK     (0x10000U)
46707 #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT    (16U)
46708 /*! MASK_CORE0_WFI
46709  *  0b0..WFI for CORE0 is not masked
46710  *  0b1..WFI for CORE0 is masked
46711  */
46712 #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x)       (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK)
46713 
46714 #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK     (0x20000U)
46715 #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT    (17U)
46716 /*! MASK_CORE1_WFI
46717  *  0b0..WFI for CORE1 is not masked
46718  *  0b1..WFI for CORE1 is masked
46719  */
46720 #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x)       (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK)
46721 
46722 #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK     (0x40000U)
46723 #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT    (18U)
46724 /*! MASK_CORE2_WFI
46725  *  0b0..WFI for CORE2 is not masked
46726  *  0b1..WFI for CORE2 is masked
46727  */
46728 #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x)       (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK)
46729 
46730 #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK     (0x80000U)
46731 #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT    (19U)
46732 /*! MASK_CORE3_WFI
46733  *  0b0..WFI for CORE3 is not masked
46734  *  0b1..WFI for CORE3 is masked
46735  */
46736 #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x)       (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK)
46737 
46738 #define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK         (0x400000U)
46739 #define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT        (22U)
46740 /*! IRQ_SRC_C2
46741  *  0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information.
46742  *  0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1.
46743  */
46744 #define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x)           (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK)
46745 
46746 #define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK         (0x800000U)
46747 #define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT        (23U)
46748 /*! IRQ_SRC_C3
46749  *  0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information.
46750  *  0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1.
46751  */
46752 #define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x)           (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK)
46753 
46754 #define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK       (0x1000000U)
46755 #define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT      (24U)
46756 /*! MASK_SCU_WFI
46757  *  0b0..WFI for SCU is not masked
46758  *  0b1..WFI for SCU is masked
46759  */
46760 #define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK)
46761 
46762 #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK      (0x4000000U)
46763 #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT     (26U)
46764 /*! MASK_L2CC_WFI
46765  *  0b0..WFI for L2 cache controller is not masked
46766  *  0b1..WFI for L2 cache controller is masked
46767  */
46768 #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x)        (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK)
46769 
46770 #define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK         (0x10000000U)
46771 #define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT        (28U)
46772 /*! IRQ_SRC_C0
46773  *  0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for more specific information
46774  *  0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1
46775  */
46776 #define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x)           (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK)
46777 
46778 #define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK         (0x20000000U)
46779 #define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT        (29U)
46780 /*! IRQ_SRC_C1
46781  *  0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for more specific information
46782  *  0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1
46783  */
46784 #define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x)           (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK)
46785 
46786 #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK    (0x40000000U)
46787 #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT   (30U)
46788 /*! IRQ_SRC_A53_WUP
46789  *  0b0..LPM wakeup source be "OR" result of
46790  *       LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting
46791  *  0b1..LPM wakeup source from external INT[127:0], masked by IMR0
46792  */
46793 #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x)      (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK)
46794 
46795 #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK   (0x80000000U)
46796 #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT  (31U)
46797 /*! MASK_DSM_TRIGGER
46798  *  0b0..DSM trigger of A53 platform will not be masked
46799  *  0b1..DSM trigger of A53 platform will be masked
46800  */
46801 #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x)     (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK)
46802 /*! @} */
46803 
46804 /*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */
46805 /*! @{ */
46806 
46807 #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK       (0x1U)
46808 #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT      (0U)
46809 /*! EN_C0_WFI_PDN
46810  *  0b0..CORE0 will not be power down with WFI request
46811  *  0b1..CORE0 will be power down with WFI request
46812  */
46813 #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK)
46814 
46815 #define GPC_LPCR_A53_AD_EN_C0_PDN_MASK           (0x2U)
46816 #define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT          (1U)
46817 /*! EN_C0_PDN
46818  *  0b0..CORE0 will not be power down with low power mode request
46819  *  0b1..CORE0 will be power down with low power mode request
46820  */
46821 #define GPC_LPCR_A53_AD_EN_C0_PDN(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK)
46822 
46823 #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK       (0x4U)
46824 #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT      (2U)
46825 /*! EN_C1_WFI_PDN
46826  *  0b0..CORE1 will not be power down with WFI request
46827  *  0b1..CORE1 will be power down with WFI request
46828  */
46829 #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK)
46830 
46831 #define GPC_LPCR_A53_AD_EN_C1_PDN_MASK           (0x8U)
46832 #define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT          (3U)
46833 /*! EN_C1_PDN
46834  *  0b0..CORE1 will not be power down with low power mode request
46835  *  0b1..CORE1 will be power down with low power mode request
46836  */
46837 #define GPC_LPCR_A53_AD_EN_C1_PDN(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK)
46838 
46839 #define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK         (0x10U)
46840 #define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT        (4U)
46841 /*! EN_PLAT_PDN
46842  *  0b0..SCU and L2 cache RAM will not be power down with low power mode request
46843  *  0b1..SCU and L2 cache RAM will be power down with low power mode request
46844  */
46845 #define GPC_LPCR_A53_AD_EN_PLAT_PDN(x)           (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK)
46846 
46847 #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK       (0x20U)
46848 #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT      (5U)
46849 /*! EN_L2_WFI_PDN
46850  *  0b0..SCU and L2 will not be power down with WFI request
46851  *  0b1..SCU and L2 will be power down with WFI request (default)
46852  */
46853 #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK)
46854 
46855 #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK       (0x100U)
46856 #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT      (8U)
46857 /*! EN_C0_IRQ_PUP
46858  *  0b0..CORE0 will not power up with IRQ request
46859  *  0b1..CORE0 will power up with IRQ request
46860  */
46861 #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK)
46862 
46863 #define GPC_LPCR_A53_AD_EN_C0_PUP_MASK           (0x200U)
46864 #define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT          (9U)
46865 /*! EN_C0_PUP
46866  *  0b0..CORE0 will not power up with low power mode request
46867  *  0b1..CORE0 will power up with low power mode request
46868  */
46869 #define GPC_LPCR_A53_AD_EN_C0_PUP(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK)
46870 
46871 #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK       (0x400U)
46872 #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT      (10U)
46873 /*! EN_C1_IRQ_PUP
46874  *  0b0..CORE1 will not power up with IRQ request
46875  *  0b1..CORE1 will power up with IRQ request
46876  */
46877 #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK)
46878 
46879 #define GPC_LPCR_A53_AD_EN_C1_PUP_MASK           (0x800U)
46880 #define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT          (11U)
46881 /*! EN_C1_PUP
46882  *  0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
46883  *  0b1..CORE1 will power up with low power mode request
46884  */
46885 #define GPC_LPCR_A53_AD_EN_C1_PUP(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK)
46886 
46887 #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK       (0x10000U)
46888 #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT      (16U)
46889 /*! EN_C2_WFI_PDN
46890  *  0b0..CORE2 will not be power down with WFI request
46891  *  0b1..CORE2 will be power down with WFI request
46892  */
46893 #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK)
46894 
46895 #define GPC_LPCR_A53_AD_EN_C2_PDN_MASK           (0x20000U)
46896 #define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT          (17U)
46897 /*! EN_C2_PDN
46898  *  0b0..CORE2 will not be power down with low power mode request
46899  *  0b1..CORE2 will be power down with low power mode request
46900  */
46901 #define GPC_LPCR_A53_AD_EN_C2_PDN(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK)
46902 
46903 #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK       (0x40000U)
46904 #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT      (18U)
46905 /*! EN_C3_WFI_PDN
46906  *  0b0..CORE3 will not be power down with WFI request
46907  *  0b1..CORE3 will be power down with WFI request
46908  */
46909 #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK)
46910 
46911 #define GPC_LPCR_A53_AD_EN_C3_PDN_MASK           (0x80000U)
46912 #define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT          (19U)
46913 /*! EN_C3_PDN
46914  *  0b0..CORE3 will not be power down with low power mode request
46915  *  0b1..CORE3 will be power down with low power mode request
46916  */
46917 #define GPC_LPCR_A53_AD_EN_C3_PDN(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK)
46918 
46919 #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK       (0x1000000U)
46920 #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT      (24U)
46921 /*! EN_C2_IRQ_PUP
46922  *  0b0..CORE2 will not power up with IRQ request
46923  *  0b1..CORE2 will power up with IRQ request
46924  */
46925 #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK)
46926 
46927 #define GPC_LPCR_A53_AD_EN_C2_PUP_MASK           (0x2000000U)
46928 #define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT          (25U)
46929 /*! EN_C2_PUP
46930  *  0b0..CORE2 will not power up with lower power mode request
46931  *  0b1..CORE2 will power up with low power mode request (only used wake up from CPU_OFF)
46932  */
46933 #define GPC_LPCR_A53_AD_EN_C2_PUP(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK)
46934 
46935 #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK       (0x4000000U)
46936 #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT      (26U)
46937 /*! EN_C3_IRQ_PUP
46938  *  0b0..CORE3 will not power up with IRQ request
46939  *  0b1..CORE3 will power up with IRQ request
46940  */
46941 #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x)         (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK)
46942 
46943 #define GPC_LPCR_A53_AD_EN_C3_PUP_MASK           (0x8000000U)
46944 #define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT          (27U)
46945 /*! EN_C3_PUP
46946  *  0b0..CORE3 will not power up with lower power mode request
46947  *  0b1..CORE3 will power up with low power mode request (only used wake up from CPU_OFF)
46948  */
46949 #define GPC_LPCR_A53_AD_EN_C3_PUP(x)             (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK)
46950 
46951 #define GPC_LPCR_A53_AD_L2PGE_MASK               (0x80000000U)
46952 #define GPC_LPCR_A53_AD_L2PGE_SHIFT              (31U)
46953 /*! L2PGE
46954  *  0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode)
46955  *  0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode)
46956  */
46957 #define GPC_LPCR_A53_AD_L2PGE(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK)
46958 /*! @} */
46959 
46960 /*! @name LPCR_M7 - Low power control register of CPU1 */
46961 /*! @{ */
46962 
46963 #define GPC_LPCR_M7_LPM0_MASK                    (0x3U)
46964 #define GPC_LPCR_M7_LPM0_SHIFT                   (0U)
46965 /*! LPM0
46966  *  0b00..Remain in RUN mode
46967  *  0b01..Transfer to WAIT mode
46968  *  0b10..Transfer to STOP mode
46969  *  0b11..Reserved
46970  */
46971 #define GPC_LPCR_M7_LPM0(x)                      (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_LPM0_SHIFT)) & GPC_LPCR_M7_LPM0_MASK)
46972 
46973 #define GPC_LPCR_M7_EN_M7_PDN_MASK               (0x4U)
46974 #define GPC_LPCR_M7_EN_M7_PDN_SHIFT              (2U)
46975 #define GPC_LPCR_M7_EN_M7_PDN(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PDN_SHIFT)) & GPC_LPCR_M7_EN_M7_PDN_MASK)
46976 
46977 #define GPC_LPCR_M7_EN_M7_PUP_MASK               (0x8U)
46978 #define GPC_LPCR_M7_EN_M7_PUP_SHIFT              (3U)
46979 #define GPC_LPCR_M7_EN_M7_PUP(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PUP_SHIFT)) & GPC_LPCR_M7_EN_M7_PUP_MASK)
46980 
46981 #define GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK          (0x4000U)
46982 #define GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT         (14U)
46983 /*! CPU_CLK_ON_LPM
46984  *  0b0..M7 clock disabled on wait/stop mode.
46985  *  0b1..M7 clock enabled on wait/stop mode.
46986  */
46987 #define GPC_LPCR_M7_CPU_CLK_ON_LPM(x)            (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK)
46988 
46989 #define GPC_LPCR_M7_MASK_M7_WFI_MASK             (0x10000U)
46990 #define GPC_LPCR_M7_MASK_M7_WFI_SHIFT            (16U)
46991 /*! MASK_M7_WFI
46992  *  0b0..WFI for M7 is not masked
46993  *  0b1..WFI for M7 is masked
46994  */
46995 #define GPC_LPCR_M7_MASK_M7_WFI(x)               (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_M7_WFI_SHIFT)) & GPC_LPCR_M7_MASK_M7_WFI_MASK)
46996 
46997 #define GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK        (0x80000000U)
46998 #define GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT       (31U)
46999 /*! MASK_DSM_TRIGGER
47000  *  0b0..DSM trigger of M7 platform will not be masked
47001  *  0b1..DSM trigger of M7 platform will be masked
47002  */
47003 #define GPC_LPCR_M7_MASK_DSM_TRIGGER(x)          (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK)
47004 /*! @} */
47005 
47006 /*! @name SLPCR - System low power control register */
47007 /*! @{ */
47008 
47009 #define GPC_SLPCR_BYPASS_PMIC_READY_MASK         (0x1U)
47010 #define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT        (0U)
47011 /*! BYPASS_PMIC_READY
47012  *  0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled
47013  *  0b1..Bypass the PMIC_READY signal - GPC will not wait for its assertion during exit of low power mode if standby voltage was enabled
47014  */
47015 #define GPC_SLPCR_BYPASS_PMIC_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK)
47016 
47017 #define GPC_SLPCR_SBYOS_MASK                     (0x2U)
47018 #define GPC_SLPCR_SBYOS_SHIFT                    (1U)
47019 /*! SBYOS
47020  *  0b0..On chip oscillator will not be powered down, after next entrance to DSM.
47021  *  0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external
47022  *       oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count
47023  *       GPC will continue with the exit from DSM process.
47024  */
47025 #define GPC_SLPCR_SBYOS(x)                       (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK)
47026 
47027 #define GPC_SLPCR_VSTBY_MASK                     (0x4U)
47028 #define GPC_SLPCR_VSTBY_SHIFT                    (2U)
47029 /*! VSTBY
47030  *  0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0')
47031  *  0b1..Voltage will be changed to standby voltage after next entrance to stop mode.
47032  */
47033 #define GPC_SLPCR_VSTBY(x)                       (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK)
47034 
47035 #define GPC_SLPCR_STBY_COUNT_MASK                (0x38U)
47036 #define GPC_SLPCR_STBY_COUNT_SHIFT               (3U)
47037 /*! STBY_COUNT
47038  *  0b000..GPC will wait 4 ckil clock cycles
47039  *  0b001..GPC will wait 8 ckil clock cycles
47040  *  0b010..GPC will wait 16 ckil clock cycles
47041  *  0b011..GPC will wait 32 ckil clock cycles
47042  *  0b100..GPC will wait 64 ckil clock cycles
47043  *  0b101..GPC will wait 128 ckil clock cycles
47044  *  0b110..GPC will wait 256 ckil clock cycles
47045  *  0b111..GPC will wait 512 ckil clock cycles
47046  */
47047 #define GPC_SLPCR_STBY_COUNT(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK)
47048 
47049 #define GPC_SLPCR_COSC_PWRDOWN_MASK              (0x40U)
47050 #define GPC_SLPCR_COSC_PWRDOWN_SHIFT             (6U)
47051 /*! COSC_PWRDOWN
47052  *  0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0
47053  *  0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1
47054  */
47055 #define GPC_SLPCR_COSC_PWRDOWN(x)                (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK)
47056 
47057 #define GPC_SLPCR_COSC_EN_MASK                   (0x80U)
47058 #define GPC_SLPCR_COSC_EN_SHIFT                  (7U)
47059 /*! COSC_EN
47060  *  0b0..Disable on-chip oscillator
47061  *  0b1..Enable on-chip oscillator
47062  */
47063 #define GPC_SLPCR_COSC_EN(x)                     (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK)
47064 
47065 #define GPC_SLPCR_OSCCNT_MASK                    (0xFF00U)
47066 #define GPC_SLPCR_OSCCNT_SHIFT                   (8U)
47067 /*! OSCCNT
47068  *  0b00000000..count 1 ckil
47069  *  0b11111111..count 256 ckils
47070  */
47071 #define GPC_SLPCR_OSCCNT(x)                      (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK)
47072 
47073 #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK  (0x10000U)
47074 #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U)
47075 #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x)    (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK)
47076 
47077 #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK  (0x20000U)
47078 #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U)
47079 #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x)    (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK)
47080 
47081 #define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK   (0x40000U)
47082 #define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT  (18U)
47083 #define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE(x)     (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK)
47084 
47085 #define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK   (0x80000U)
47086 #define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT  (19U)
47087 #define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE(x)     (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK)
47088 
47089 #define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK        (0x800000U)
47090 #define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT       (23U)
47091 /*! DISABLE_A53_IS_DSM
47092  *  0b0..Enable A53 isolation signal in DSM
47093  *  0b1..Disable A53 isolation signal in DSM
47094  */
47095 #define GPC_SLPCR_DISABLE_A53_IS_DSM(x)          (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK)
47096 
47097 #define GPC_SLPCR_REG_BYPASS_COUNT_MASK          (0x3F000000U)
47098 #define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT         (24U)
47099 /*! REG_BYPASS_COUNT
47100  *  0b000000..no delay
47101  *  0b000001..1 CKIL clock period delay
47102  *  0b111111..63 CKIL clock period delay
47103  */
47104 #define GPC_SLPCR_REG_BYPASS_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK)
47105 
47106 #define GPC_SLPCR_RBC_EN_MASK                    (0x40000000U)
47107 #define GPC_SLPCR_RBC_EN_SHIFT                   (30U)
47108 /*! RBC_EN
47109  *  0b0..REG_BYPASS_COUNTER disabled
47110  *  0b1..REG_BYPASS_COUNTER enabled
47111  */
47112 #define GPC_SLPCR_RBC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK)
47113 
47114 #define GPC_SLPCR_EN_DSM_MASK                    (0x80000000U)
47115 #define GPC_SLPCR_EN_DSM_SHIFT                   (31U)
47116 /*! EN_DSM
47117  *  0b0..DSM disabled
47118  *  0b1..DSM enabled
47119  */
47120 #define GPC_SLPCR_EN_DSM(x)                      (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK)
47121 /*! @} */
47122 
47123 /*! @name MST_CPU_MAPPING - MASTER LPM Handshake */
47124 /*! @{ */
47125 
47126 #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U)
47127 #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U)
47128 /*! MST0_CPU_MAPPING - MASTER0 CPU Mapping
47129  *  0b0..GPC will not send out power off requirement
47130  *  0b1..GPC will send out power off requirement
47131  */
47132 #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x)  (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK)
47133 
47134 #define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK (0x2U)
47135 #define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT (1U)
47136 /*! MST1_CPU_MAPPING - MASTER1 CPU Mapping
47137  *  0b0..GPC will not send out power off requirement
47138  *  0b1..GPC will send out power off requirement
47139  */
47140 #define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING(x)  (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK)
47141 
47142 #define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK (0x4U)
47143 #define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT (2U)
47144 /*! MST2_CPU_MAPPING - MASTER2 CPU Mapping
47145  *  0b0..GPC will not send out power off requirement
47146  *  0b1..GPC will send out power off requirement
47147  */
47148 #define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING(x)  (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK)
47149 /*! @} */
47150 
47151 /*! @name MLPCR - Memory low power control register */
47152 /*! @{ */
47153 
47154 #define GPC_MLPCR_MEMLP_CTL_DIS_MASK             (0x1U)
47155 #define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT            (0U)
47156 /*! MEMLP_CTL_DIS
47157  *  0b0..Enable RAM low power control
47158  *  0b1..Disable RAM low power control
47159  */
47160 #define GPC_MLPCR_MEMLP_CTL_DIS(x)               (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK)
47161 
47162 #define GPC_MLPCR_MEMLP_RET_SEL_MASK             (0x2U)
47163 #define GPC_MLPCR_MEMLP_RET_SEL_SHIFT            (1U)
47164 /*! MEMLP_RET_SEL
47165  *  0b0..retention mode 2
47166  *  0b1..retention mode 1
47167  */
47168 #define GPC_MLPCR_MEMLP_RET_SEL(x)               (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK)
47169 
47170 #define GPC_MLPCR_ROMLP_PDN_DIS_MASK             (0x4U)
47171 #define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT            (2U)
47172 /*! ROMLP_PDN_DIS
47173  *  0b0..Enable ROM shut down control(should also enable RAM low power control);
47174  *  0b1..Disable ROM shut down control
47175  */
47176 #define GPC_MLPCR_ROMLP_PDN_DIS(x)               (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK)
47177 
47178 #define GPC_MLPCR_MEMLP_ENT_CNT_MASK             (0xFF00U)
47179 #define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT            (8U)
47180 #define GPC_MLPCR_MEMLP_ENT_CNT(x)               (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK)
47181 
47182 #define GPC_MLPCR_MEM_EXT_CNT_MASK               (0xFF0000U)
47183 #define GPC_MLPCR_MEM_EXT_CNT_SHIFT              (16U)
47184 #define GPC_MLPCR_MEM_EXT_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK)
47185 
47186 #define GPC_MLPCR_MEMLP_RET_PGEN_MASK            (0xFF000000U)
47187 #define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT           (24U)
47188 #define GPC_MLPCR_MEMLP_RET_PGEN(x)              (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK)
47189 /*! @} */
47190 
47191 /*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */
47192 /*! @{ */
47193 
47194 #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U)
47195 #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U)
47196 #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK)
47197 
47198 #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x2U)
47199 #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (1U)
47200 #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK)
47201 
47202 #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x4U)
47203 #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (2U)
47204 #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK)
47205 
47206 #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x8U)
47207 #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (3U)
47208 #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK)
47209 
47210 #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x10U)
47211 #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (4U)
47212 #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK)
47213 
47214 #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20U)
47215 #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (5U)
47216 #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK)
47217 
47218 #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x40U)
47219 #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (6U)
47220 #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK)
47221 
47222 #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x80U)
47223 #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (7U)
47224 #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK)
47225 
47226 #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x100U)
47227 #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (8U)
47228 #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK)
47229 
47230 #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x200U)
47231 #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (9U)
47232 #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK)
47233 
47234 #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK (0x1000U)
47235 #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT (12U)
47236 #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK)
47237 
47238 #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK (0x2000U)
47239 #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT (13U)
47240 #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK)
47241 
47242 #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x40000000U)
47243 #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (30U)
47244 #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK)
47245 
47246 #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U)
47247 #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U)
47248 #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK)
47249 /*! @} */
47250 
47251 /*! @name PGC_ACK_SEL_M7 - PGC acknowledge signal selection of M7 platform */
47252 /*! @{ */
47253 
47254 #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK (0x1U)
47255 #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT (0U)
47256 #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK)
47257 
47258 #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK (0x2U)
47259 #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT (1U)
47260 #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK)
47261 
47262 #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK  (0x1000U)
47263 #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT (12U)
47264 #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK(x)    (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK)
47265 
47266 #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK  (0x2000U)
47267 #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT (13U)
47268 #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK)
47269 
47270 #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK (0x40000000U)
47271 #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT (30U)
47272 #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK)
47273 
47274 #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK (0x80000000U)
47275 #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT (31U)
47276 #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK)
47277 /*! @} */
47278 
47279 /*! @name MISC - GPC Miscellaneous register */
47280 /*! @{ */
47281 
47282 #define GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK        (0x1U)
47283 #define GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT       (0U)
47284 /*! M7_SLEEP_HOLD_REQ_B
47285  *  0b0..Hold M7 platform in sleep mode. This bit is a software control bit to M7 platform.
47286  *  0b1..Don't hold M7 platform in sleep mode.
47287  */
47288 #define GPC_MISC_M7_SLEEP_HOLD_REQ_B(x)          (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK)
47289 
47290 #define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK       (0x2U)
47291 #define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT      (1U)
47292 /*! A53_SLEEP_HOLD_REQ_B
47293  *  0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform.
47294  *  0b1..Don't hold A53 platform in sleep mode.
47295  */
47296 #define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x)         (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK)
47297 
47298 #define GPC_MISC_GPC_IRQ_MASK_MASK               (0x20U)
47299 #define GPC_MISC_GPC_IRQ_MASK_SHIFT              (5U)
47300 /*! GPC_IRQ_MASK
47301  *  0b0..Not masked
47302  *  0b1..Interrupt / event is masked
47303  */
47304 #define GPC_MISC_GPC_IRQ_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK)
47305 
47306 #define GPC_MISC_M7_PDN_REQ_MASK_MASK            (0x100U)
47307 #define GPC_MISC_M7_PDN_REQ_MASK_SHIFT           (8U)
47308 /*! M7_PDN_REQ_MASK
47309  *  0b0..M7 power down request to virtual M7 PGC will be masked.
47310  *  0b1..M7 power down request to virtual M7 PGC will not be masked. Set this bit to 1'b1 when M7 virtual PGC is used.
47311  */
47312 #define GPC_MISC_M7_PDN_REQ_MASK(x)              (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M7_PDN_REQ_MASK_MASK)
47313 
47314 #define GPC_MISC_A53_BYPASS_PUP_MASK_MASK        (0x1000000U)
47315 #define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT       (24U)
47316 #define GPC_MISC_A53_BYPASS_PUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK)
47317 
47318 #define GPC_MISC_M7_BYPASS_PUP_MASK_MASK         (0x2000000U)
47319 #define GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT        (25U)
47320 #define GPC_MISC_M7_BYPASS_PUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M7_BYPASS_PUP_MASK_MASK)
47321 
47322 #define GPC_MISC_MIPI_LDO_EN_CTRL_MASK           (0x80000000U)
47323 #define GPC_MISC_MIPI_LDO_EN_CTRL_SHIFT          (31U)
47324 #define GPC_MISC_MIPI_LDO_EN_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << GPC_MISC_MIPI_LDO_EN_CTRL_SHIFT)) & GPC_MISC_MIPI_LDO_EN_CTRL_MASK)
47325 /*! @} */
47326 
47327 /*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 5 of A53 core0 */
47328 /*! @{ */
47329 
47330 #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK    (0xFFFFFFFFU)
47331 #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT   (0U)
47332 /*! IMR1_CORE0_A53
47333  *  0b00000000000000000000000000000000..IRQ not masked
47334  *  0b00000000000000000000000000000001..IRQ masked
47335  */
47336 #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK)
47337 
47338 #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK    (0xFFFFFFFFU)
47339 #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT   (0U)
47340 /*! IMR2_CORE0_A53
47341  *  0b00000000000000000000000000000000..IRQ not masked
47342  *  0b00000000000000000000000000000001..IRQ masked
47343  */
47344 #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK)
47345 
47346 #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK    (0xFFFFFFFFU)
47347 #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT   (0U)
47348 /*! IMR3_CORE0_A53
47349  *  0b00000000000000000000000000000000..IRQ not masked
47350  *  0b00000000000000000000000000000001..IRQ masked
47351  */
47352 #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK)
47353 
47354 #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK    (0xFFFFFFFFU)
47355 #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT   (0U)
47356 /*! IMR4_CORE0_A53
47357  *  0b00000000000000000000000000000000..IRQ not masked
47358  *  0b00000000000000000000000000000001..IRQ masked
47359  */
47360 #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK)
47361 
47362 #define GPC_IMR_CORE0_A53_IMR5_CORE0_A53_MASK    (0xFFFFFFFFU)
47363 #define GPC_IMR_CORE0_A53_IMR5_CORE0_A53_SHIFT   (0U)
47364 /*! IMR5_CORE0_A53
47365  *  0b00000000000000000000000000000000..IRQ not masked
47366  *  0b00000000000000000000000000000001..IRQ masked
47367  */
47368 #define GPC_IMR_CORE0_A53_IMR5_CORE0_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR5_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR5_CORE0_A53_MASK)
47369 /*! @} */
47370 
47371 /* The count of GPC_IMR_CORE0_A53 */
47372 #define GPC_IMR_CORE0_A53_COUNT                  (5U)
47373 
47374 /*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 5 of A53 core1 */
47375 /*! @{ */
47376 
47377 #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK    (0xFFFFFFFFU)
47378 #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT   (0U)
47379 /*! IMR1_CORE1_A53
47380  *  0b00000000000000000000000000000000..IRQ not masked
47381  *  0b00000000000000000000000000000001..IRQ masked
47382  */
47383 #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK)
47384 
47385 #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK    (0xFFFFFFFFU)
47386 #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT   (0U)
47387 /*! IMR2_CORE1_A53
47388  *  0b00000000000000000000000000000000..IRQ not masked
47389  *  0b00000000000000000000000000000001..IRQ masked
47390  */
47391 #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK)
47392 
47393 #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK    (0xFFFFFFFFU)
47394 #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT   (0U)
47395 /*! IMR3_CORE1_A53
47396  *  0b00000000000000000000000000000000..IRQ not masked
47397  *  0b00000000000000000000000000000001..IRQ masked
47398  */
47399 #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK)
47400 
47401 #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK    (0xFFFFFFFFU)
47402 #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT   (0U)
47403 /*! IMR4_CORE1_A53
47404  *  0b00000000000000000000000000000000..IRQ not masked
47405  *  0b00000000000000000000000000000001..IRQ masked
47406  */
47407 #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK)
47408 
47409 #define GPC_IMR_CORE1_A53_IMR5_CORE1_A53_MASK    (0xFFFFFFFFU)
47410 #define GPC_IMR_CORE1_A53_IMR5_CORE1_A53_SHIFT   (0U)
47411 /*! IMR5_CORE1_A53
47412  *  0b00000000000000000000000000000000..IRQ not masked
47413  *  0b00000000000000000000000000000001..IRQ masked
47414  */
47415 #define GPC_IMR_CORE1_A53_IMR5_CORE1_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR5_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR5_CORE1_A53_MASK)
47416 /*! @} */
47417 
47418 /* The count of GPC_IMR_CORE1_A53 */
47419 #define GPC_IMR_CORE1_A53_COUNT                  (5U)
47420 
47421 /*! @name IMR_M7 - IRQ masking register 1 of M7..IRQ masking register 5 of M7 */
47422 /*! @{ */
47423 
47424 #define GPC_IMR_M7_IMR1_M7_MASK                  (0xFFFFFFFFU)
47425 #define GPC_IMR_M7_IMR1_M7_SHIFT                 (0U)
47426 /*! IMR1_M7
47427  *  0b00000000000000000000000000000000..IRQ not masked
47428  *  0b00000000000000000000000000000001..IRQ masked
47429  */
47430 #define GPC_IMR_M7_IMR1_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR1_M7_SHIFT)) & GPC_IMR_M7_IMR1_M7_MASK)
47431 
47432 #define GPC_IMR_M7_IMR2_M7_MASK                  (0xFFFFFFFFU)
47433 #define GPC_IMR_M7_IMR2_M7_SHIFT                 (0U)
47434 /*! IMR2_M7
47435  *  0b00000000000000000000000000000000..IRQ not masked
47436  *  0b00000000000000000000000000000001..IRQ masked
47437  */
47438 #define GPC_IMR_M7_IMR2_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR2_M7_SHIFT)) & GPC_IMR_M7_IMR2_M7_MASK)
47439 
47440 #define GPC_IMR_M7_IMR3_M7_MASK                  (0xFFFFFFFFU)
47441 #define GPC_IMR_M7_IMR3_M7_SHIFT                 (0U)
47442 /*! IMR3_M7
47443  *  0b00000000000000000000000000000000..IRQ not masked
47444  *  0b00000000000000000000000000000001..IRQ masked
47445  */
47446 #define GPC_IMR_M7_IMR3_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR3_M7_SHIFT)) & GPC_IMR_M7_IMR3_M7_MASK)
47447 
47448 #define GPC_IMR_M7_IMR4_M7_MASK                  (0xFFFFFFFFU)
47449 #define GPC_IMR_M7_IMR4_M7_SHIFT                 (0U)
47450 /*! IMR4_M7
47451  *  0b00000000000000000000000000000000..IRQ not masked
47452  *  0b00000000000000000000000000000001..IRQ masked
47453  */
47454 #define GPC_IMR_M7_IMR4_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR4_M7_SHIFT)) & GPC_IMR_M7_IMR4_M7_MASK)
47455 
47456 #define GPC_IMR_M7_IMR5_M7_MASK                  (0xFFFFFFFFU)
47457 #define GPC_IMR_M7_IMR5_M7_SHIFT                 (0U)
47458 /*! IMR5_M7
47459  *  0b00000000000000000000000000000000..IRQ not masked
47460  *  0b00000000000000000000000000000001..IRQ masked
47461  */
47462 #define GPC_IMR_M7_IMR5_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR5_M7_SHIFT)) & GPC_IMR_M7_IMR5_M7_MASK)
47463 /*! @} */
47464 
47465 /* The count of GPC_IMR_M7 */
47466 #define GPC_IMR_M7_COUNT                         (5U)
47467 
47468 /*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 5 of A53 */
47469 /*! @{ */
47470 
47471 #define GPC_ISR_A53_ISR1_A53_MASK                (0xFFFFFFFFU)
47472 #define GPC_ISR_A53_ISR1_A53_SHIFT               (0U)
47473 #define GPC_ISR_A53_ISR1_A53(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK)
47474 
47475 #define GPC_ISR_A53_ISR2_A53_MASK                (0xFFFFFFFFU)
47476 #define GPC_ISR_A53_ISR2_A53_SHIFT               (0U)
47477 #define GPC_ISR_A53_ISR2_A53(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK)
47478 
47479 #define GPC_ISR_A53_ISR3_A53_MASK                (0xFFFFFFFFU)
47480 #define GPC_ISR_A53_ISR3_A53_SHIFT               (0U)
47481 #define GPC_ISR_A53_ISR3_A53(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK)
47482 
47483 #define GPC_ISR_A53_ISR4_A53_MASK                (0xFFFFFFFFU)
47484 #define GPC_ISR_A53_ISR4_A53_SHIFT               (0U)
47485 #define GPC_ISR_A53_ISR4_A53(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK)
47486 
47487 #define GPC_ISR_A53_ISR5_A53_MASK                (0xFFFFFFFFU)
47488 #define GPC_ISR_A53_ISR5_A53_SHIFT               (0U)
47489 #define GPC_ISR_A53_ISR5_A53(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR5_A53_SHIFT)) & GPC_ISR_A53_ISR5_A53_MASK)
47490 /*! @} */
47491 
47492 /* The count of GPC_ISR_A53 */
47493 #define GPC_ISR_A53_COUNT                        (5U)
47494 
47495 /*! @name ISR_M7 - IRQ status register 1 of M7..IRQ status register 5 of M7 */
47496 /*! @{ */
47497 
47498 #define GPC_ISR_M7_ISR1_M7_MASK                  (0xFFFFFFFFU)
47499 #define GPC_ISR_M7_ISR1_M7_SHIFT                 (0U)
47500 #define GPC_ISR_M7_ISR1_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR1_M7_SHIFT)) & GPC_ISR_M7_ISR1_M7_MASK)
47501 
47502 #define GPC_ISR_M7_ISR2_M7_MASK                  (0xFFFFFFFFU)
47503 #define GPC_ISR_M7_ISR2_M7_SHIFT                 (0U)
47504 #define GPC_ISR_M7_ISR2_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR2_M7_SHIFT)) & GPC_ISR_M7_ISR2_M7_MASK)
47505 
47506 #define GPC_ISR_M7_ISR3_M7_MASK                  (0xFFFFFFFFU)
47507 #define GPC_ISR_M7_ISR3_M7_SHIFT                 (0U)
47508 #define GPC_ISR_M7_ISR3_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR3_M7_SHIFT)) & GPC_ISR_M7_ISR3_M7_MASK)
47509 
47510 #define GPC_ISR_M7_ISR4_M7_MASK                  (0xFFFFFFFFU)
47511 #define GPC_ISR_M7_ISR4_M7_SHIFT                 (0U)
47512 #define GPC_ISR_M7_ISR4_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR4_M7_SHIFT)) & GPC_ISR_M7_ISR4_M7_MASK)
47513 
47514 #define GPC_ISR_M7_ISR5_M7_MASK                  (0xFFFFFFFFU)
47515 #define GPC_ISR_M7_ISR5_M7_SHIFT                 (0U)
47516 #define GPC_ISR_M7_ISR5_M7(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR5_M7_SHIFT)) & GPC_ISR_M7_ISR5_M7_MASK)
47517 /*! @} */
47518 
47519 /* The count of GPC_ISR_M7 */
47520 #define GPC_ISR_M7_COUNT                         (5U)
47521 
47522 /*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */
47523 /*! @{ */
47524 
47525 #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U)
47526 #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U)
47527 #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK)
47528 
47529 #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U)
47530 #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U)
47531 #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK)
47532 
47533 #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x4U)
47534 #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (2U)
47535 #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK)
47536 
47537 #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U)
47538 #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U)
47539 #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK)
47540 
47541 #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U)
47542 #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U)
47543 #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK)
47544 /*! @} */
47545 
47546 /*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */
47547 /*! @{ */
47548 
47549 #define GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_MASK (0x1U)
47550 #define GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_SHIFT (0U)
47551 #define GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ(x)  (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_MASK)
47552 
47553 #define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK (0x2U)
47554 #define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT (1U)
47555 #define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK)
47556 /*! @} */
47557 
47558 /*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */
47559 /*! @{ */
47560 
47561 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_MASK (0x1U)
47562 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_SHIFT (0U)
47563 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_MASK)
47564 
47565 #define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_MASK (0x2U)
47566 #define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_SHIFT (1U)
47567 #define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_MASK)
47568 
47569 #define GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_MASK (0x4U)
47570 #define GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_SHIFT (2U)
47571 #define GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_MASK)
47572 
47573 #define GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_MASK (0x8U)
47574 #define GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_SHIFT (3U)
47575 #define GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_MASK)
47576 
47577 #define GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_MASK (0x10U)
47578 #define GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_SHIFT (4U)
47579 #define GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_MASK)
47580 
47581 #define GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_MASK (0x20U)
47582 #define GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_SHIFT (5U)
47583 #define GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_MASK)
47584 
47585 #define GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_MASK (0x40U)
47586 #define GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_SHIFT (6U)
47587 #define GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_MASK)
47588 
47589 #define GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_MASK (0x80U)
47590 #define GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_SHIFT (7U)
47591 #define GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_MASK)
47592 
47593 #define GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_MASK (0x100U)
47594 #define GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_SHIFT (8U)
47595 #define GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_MASK)
47596 
47597 #define GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_MASK (0x200U)
47598 #define GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_SHIFT (9U)
47599 #define GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_MASK)
47600 
47601 #define GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_MASK (0x400U)
47602 #define GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_SHIFT (10U)
47603 #define GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_MASK)
47604 
47605 #define GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_MASK (0x800U)
47606 #define GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_SHIFT (11U)
47607 #define GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_MASK)
47608 
47609 #define GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_MASK (0x1000U)
47610 #define GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_SHIFT (12U)
47611 #define GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_MASK)
47612 
47613 #define GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_MASK (0x2000U)
47614 #define GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_SHIFT (13U)
47615 #define GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_MASK)
47616 
47617 #define GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_MASK (0x4000U)
47618 #define GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_SHIFT (14U)
47619 #define GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_MASK)
47620 
47621 #define GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_MASK (0x8000U)
47622 #define GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_SHIFT (15U)
47623 #define GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_MASK)
47624 
47625 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_MASK (0x10000U)
47626 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_SHIFT (16U)
47627 #define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_MASK)
47628 
47629 #define GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_MASK (0x20000U)
47630 #define GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_SHIFT (17U)
47631 #define GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_MASK)
47632 
47633 #define GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_MASK (0x40000U)
47634 #define GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_SHIFT (18U)
47635 #define GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_MASK)
47636 
47637 #define GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_MASK (0x80000U)
47638 #define GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_SHIFT (19U)
47639 #define GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_MASK)
47640 /*! @} */
47641 
47642 /*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */
47643 /*! @{ */
47644 
47645 #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U)
47646 #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U)
47647 #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK)
47648 
47649 #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U)
47650 #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U)
47651 #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK)
47652 
47653 #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK (0x4U)
47654 #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT (2U)
47655 #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK)
47656 
47657 #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U)
47658 #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U)
47659 #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK)
47660 
47661 #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U)
47662 #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U)
47663 #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK)
47664 /*! @} */
47665 
47666 /*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */
47667 /*! @{ */
47668 
47669 #define GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_MASK (0x1U)
47670 #define GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_SHIFT (0U)
47671 #define GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ(x)  (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_MASK)
47672 
47673 #define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK (0x2U)
47674 #define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT (1U)
47675 #define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK)
47676 /*! @} */
47677 
47678 /*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */
47679 /*! @{ */
47680 
47681 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_MASK (0x1U)
47682 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_SHIFT (0U)
47683 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_MASK)
47684 
47685 #define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_MASK (0x2U)
47686 #define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_SHIFT (1U)
47687 #define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_MASK)
47688 
47689 #define GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_MASK (0x4U)
47690 #define GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_SHIFT (2U)
47691 #define GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_MASK)
47692 
47693 #define GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_MASK (0x8U)
47694 #define GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_SHIFT (3U)
47695 #define GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_MASK)
47696 
47697 #define GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_MASK (0x10U)
47698 #define GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_SHIFT (4U)
47699 #define GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_MASK)
47700 
47701 #define GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_MASK (0x20U)
47702 #define GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_SHIFT (5U)
47703 #define GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_MASK)
47704 
47705 #define GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_MASK (0x40U)
47706 #define GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_SHIFT (6U)
47707 #define GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_MASK)
47708 
47709 #define GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_MASK (0x80U)
47710 #define GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_SHIFT (7U)
47711 #define GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_MASK)
47712 
47713 #define GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_MASK (0x100U)
47714 #define GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_SHIFT (8U)
47715 #define GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_MASK)
47716 
47717 #define GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_MASK (0x200U)
47718 #define GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_SHIFT (9U)
47719 #define GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_MASK)
47720 
47721 #define GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_MASK (0x400U)
47722 #define GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_SHIFT (10U)
47723 #define GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_MASK)
47724 
47725 #define GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_MASK (0x800U)
47726 #define GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_SHIFT (11U)
47727 #define GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_MASK)
47728 
47729 #define GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_MASK   (0x1000U)
47730 #define GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_SHIFT  (12U)
47731 #define GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ(x)     (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_MASK)
47732 
47733 #define GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_MASK (0x2000U)
47734 #define GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_SHIFT (13U)
47735 #define GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_MASK)
47736 
47737 #define GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_MASK (0x4000U)
47738 #define GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_SHIFT (14U)
47739 #define GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_MASK)
47740 
47741 #define GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_MASK (0x8000U)
47742 #define GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_SHIFT (15U)
47743 #define GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_MASK)
47744 
47745 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_MASK (0x10000U)
47746 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_SHIFT (16U)
47747 #define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_MASK)
47748 
47749 #define GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_MASK (0x20000U)
47750 #define GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_SHIFT (17U)
47751 #define GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_MASK)
47752 
47753 #define GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_MASK (0x40000U)
47754 #define GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_SHIFT (18U)
47755 #define GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_MASK)
47756 
47757 #define GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_MASK (0x80000U)
47758 #define GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_SHIFT (19U)
47759 #define GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_MASK)
47760 /*! @} */
47761 
47762 /*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */
47763 /*! @{ */
47764 
47765 #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U)
47766 #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U)
47767 #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK)
47768 
47769 #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U)
47770 #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U)
47771 #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK)
47772 
47773 #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x4U)
47774 #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (2U)
47775 #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK)
47776 
47777 #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK (0x8U)
47778 #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT (3U)
47779 #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK)
47780 
47781 #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK (0x10U)
47782 #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT (4U)
47783 #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK)
47784 /*! @} */
47785 
47786 /*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */
47787 /*! @{ */
47788 
47789 #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U)
47790 #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U)
47791 #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK)
47792 /*! @} */
47793 
47794 /* The count of GPC_A53_MIX_PGC_PUP_STATUS */
47795 #define GPC_A53_MIX_PGC_PUP_STATUS_COUNT         (3U)
47796 
47797 /*! @name M7_MIX_PGC_PUP_STATUS - M7 MIX PGC software up trigger status register */
47798 /*! @{ */
47799 
47800 #define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK (0x1U)
47801 #define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT (0U)
47802 #define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK)
47803 /*! @} */
47804 
47805 /* The count of GPC_M7_MIX_PGC_PUP_STATUS */
47806 #define GPC_M7_MIX_PGC_PUP_STATUS_COUNT          (3U)
47807 
47808 /*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */
47809 /*! @{ */
47810 
47811 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_MASK (0x1U)
47812 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_SHIFT (0U)
47813 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_MASK)
47814 
47815 #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_MASK (0x2U)
47816 #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_SHIFT (1U)
47817 #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_MASK)
47818 
47819 #define GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_MASK (0x4U)
47820 #define GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_SHIFT (2U)
47821 #define GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_MASK)
47822 
47823 #define GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_MASK (0x8U)
47824 #define GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_SHIFT (3U)
47825 #define GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_MASK)
47826 
47827 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_MASK (0x10U)
47828 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_SHIFT (4U)
47829 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_MASK)
47830 
47831 #define GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_MASK (0x20U)
47832 #define GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_SHIFT (5U)
47833 #define GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_MASK)
47834 
47835 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_MASK (0x40U)
47836 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_SHIFT (6U)
47837 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_MASK)
47838 
47839 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_MASK (0x80U)
47840 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT (7U)
47841 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_MASK)
47842 
47843 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK (0x100U)
47844 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT (8U)
47845 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK)
47846 
47847 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_MASK (0x200U)
47848 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_SHIFT (9U)
47849 #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_MASK)
47850 
47851 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_MASK (0x400U)
47852 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_SHIFT (10U)
47853 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_MASK)
47854 
47855 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_MASK (0x800U)
47856 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_SHIFT (11U)
47857 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_MASK)
47858 
47859 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_MASK (0x1000U)
47860 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_SHIFT (12U)
47861 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_MASK)
47862 
47863 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_MASK (0x2000U)
47864 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_SHIFT (13U)
47865 #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_MASK)
47866 
47867 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_MASK (0x4000U)
47868 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_SHIFT (14U)
47869 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_MASK)
47870 
47871 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_MASK (0x8000U)
47872 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_SHIFT (15U)
47873 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_MASK)
47874 
47875 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_MASK (0x10000U)
47876 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_SHIFT (16U)
47877 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_MASK)
47878 
47879 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_MASK (0x20000U)
47880 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_SHIFT (17U)
47881 #define GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_MASK)
47882 
47883 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_MASK (0x40000U)
47884 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_SHIFT (18U)
47885 #define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_MASK)
47886 
47887 #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_MASK (0x80000U)
47888 #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_SHIFT (19U)
47889 #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_MASK)
47890 /*! @} */
47891 
47892 /* The count of GPC_A53_PU_PGC_PUP_STATUS */
47893 #define GPC_A53_PU_PGC_PUP_STATUS_COUNT          (3U)
47894 
47895 /*! @name M7_PU_PGC_PUP_STATUS - M7 PU PGC software up trigger status register */
47896 /*! @{ */
47897 
47898 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_MASK (0x1U)
47899 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_SHIFT (0U)
47900 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_MASK)
47901 
47902 #define GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_MASK (0x2U)
47903 #define GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_SHIFT (1U)
47904 #define GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_MASK)
47905 
47906 #define GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_MASK (0x4U)
47907 #define GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_SHIFT (2U)
47908 #define GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_MASK)
47909 
47910 #define GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_MASK (0x8U)
47911 #define GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_SHIFT (3U)
47912 #define GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_MASK)
47913 
47914 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_MASK (0x10U)
47915 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_SHIFT (4U)
47916 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_MASK)
47917 
47918 #define GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_MASK (0x20U)
47919 #define GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_SHIFT (5U)
47920 #define GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_MASK)
47921 
47922 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_MASK (0x40U)
47923 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_SHIFT (6U)
47924 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_MASK)
47925 
47926 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_MASK (0x80U)
47927 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT (7U)
47928 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_MASK)
47929 
47930 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK (0x100U)
47931 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT (8U)
47932 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK)
47933 
47934 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_MASK (0x200U)
47935 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_SHIFT (9U)
47936 #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_MASK)
47937 
47938 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_MASK (0x400U)
47939 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_SHIFT (10U)
47940 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_MASK)
47941 
47942 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_MASK (0x800U)
47943 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_SHIFT (11U)
47944 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_MASK)
47945 
47946 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_MASK (0x1000U)
47947 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_SHIFT (12U)
47948 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_MASK)
47949 
47950 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_MASK (0x2000U)
47951 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_SHIFT (13U)
47952 #define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_MASK)
47953 
47954 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_MASK (0x4000U)
47955 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_SHIFT (14U)
47956 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_MASK)
47957 
47958 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_MASK (0x8000U)
47959 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_SHIFT (15U)
47960 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_MASK)
47961 
47962 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_MASK (0x10000U)
47963 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_SHIFT (16U)
47964 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_MASK)
47965 
47966 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_MASK (0x20000U)
47967 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_SHIFT (17U)
47968 #define GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_MASK)
47969 
47970 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_MASK (0x40000U)
47971 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_SHIFT (18U)
47972 #define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_MASK)
47973 
47974 #define GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_MASK (0x80000U)
47975 #define GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_SHIFT (19U)
47976 #define GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_MASK)
47977 /*! @} */
47978 
47979 /* The count of GPC_M7_PU_PGC_PUP_STATUS */
47980 #define GPC_M7_PU_PGC_PUP_STATUS_COUNT           (3U)
47981 
47982 /*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */
47983 /*! @{ */
47984 
47985 #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U)
47986 #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U)
47987 #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK)
47988 
47989 #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U)
47990 #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U)
47991 #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK)
47992 
47993 #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x4U)
47994 #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (2U)
47995 #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK)
47996 
47997 #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK (0x8U)
47998 #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT (3U)
47999 #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK)
48000 
48001 #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK (0x10U)
48002 #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT (4U)
48003 #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK)
48004 /*! @} */
48005 
48006 /*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */
48007 /*! @{ */
48008 
48009 #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U)
48010 #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U)
48011 #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK)
48012 /*! @} */
48013 
48014 /* The count of GPC_A53_MIX_PGC_PDN_STATUS */
48015 #define GPC_A53_MIX_PGC_PDN_STATUS_COUNT         (3U)
48016 
48017 /*! @name M7_MIX_PGC_PDN_STATUS - M7 MIX PGC software power down trigger status register */
48018 /*! @{ */
48019 
48020 #define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK (0x1U)
48021 #define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT (0U)
48022 #define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK)
48023 /*! @} */
48024 
48025 /* The count of GPC_M7_MIX_PGC_PDN_STATUS */
48026 #define GPC_M7_MIX_PGC_PDN_STATUS_COUNT          (3U)
48027 
48028 /*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */
48029 /*! @{ */
48030 
48031 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_MASK (0x1U)
48032 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_SHIFT (0U)
48033 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_MASK)
48034 
48035 #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_MASK (0x2U)
48036 #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_SHIFT (1U)
48037 #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_MASK)
48038 
48039 #define GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_MASK (0x4U)
48040 #define GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_SHIFT (2U)
48041 #define GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_MASK)
48042 
48043 #define GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_MASK (0x8U)
48044 #define GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_SHIFT (3U)
48045 #define GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_MASK)
48046 
48047 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_MASK (0x10U)
48048 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_SHIFT (4U)
48049 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_MASK)
48050 
48051 #define GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_MASK (0x20U)
48052 #define GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_SHIFT (5U)
48053 #define GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_MASK)
48054 
48055 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_MASK (0x40U)
48056 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_SHIFT (6U)
48057 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_MASK)
48058 
48059 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_MASK (0x80U)
48060 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT (7U)
48061 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_MASK)
48062 
48063 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK (0x100U)
48064 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT (8U)
48065 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK)
48066 
48067 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_MASK (0x200U)
48068 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_SHIFT (9U)
48069 #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_MASK)
48070 
48071 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_MASK (0x400U)
48072 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_SHIFT (10U)
48073 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_MASK)
48074 
48075 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_MASK (0x800U)
48076 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_SHIFT (11U)
48077 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_MASK)
48078 
48079 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_MASK (0x1000U)
48080 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_SHIFT (12U)
48081 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_MASK)
48082 
48083 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_MASK (0x2000U)
48084 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_SHIFT (13U)
48085 #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_MASK)
48086 
48087 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_MASK (0x4000U)
48088 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_SHIFT (14U)
48089 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_MASK)
48090 
48091 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_MASK (0x8000U)
48092 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_SHIFT (15U)
48093 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_MASK)
48094 
48095 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_MASK (0x10000U)
48096 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_SHIFT (16U)
48097 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_MASK)
48098 
48099 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_MASK (0x20000U)
48100 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_SHIFT (17U)
48101 #define GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_MASK)
48102 
48103 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_MASK (0x40000U)
48104 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_SHIFT (18U)
48105 #define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_MASK)
48106 
48107 #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_MASK (0x80000U)
48108 #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_SHIFT (19U)
48109 #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_MASK)
48110 /*! @} */
48111 
48112 /* The count of GPC_A53_PU_PGC_PDN_STATUS */
48113 #define GPC_A53_PU_PGC_PDN_STATUS_COUNT          (3U)
48114 
48115 /*! @name M7_PU_PGC_PDN_STATUS - M7 PU PGC software down trigger status */
48116 /*! @{ */
48117 
48118 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_MASK (0x1U)
48119 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_SHIFT (0U)
48120 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_MASK)
48121 
48122 #define GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_MASK (0x2U)
48123 #define GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_SHIFT (1U)
48124 #define GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_MASK)
48125 
48126 #define GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_MASK (0x4U)
48127 #define GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_SHIFT (2U)
48128 #define GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_MASK)
48129 
48130 #define GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_MASK (0x8U)
48131 #define GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_SHIFT (3U)
48132 #define GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_MASK)
48133 
48134 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_MASK (0x10U)
48135 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_SHIFT (4U)
48136 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_MASK)
48137 
48138 #define GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_MASK (0x20U)
48139 #define GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_SHIFT (5U)
48140 #define GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_MASK)
48141 
48142 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_MASK (0x40U)
48143 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_SHIFT (6U)
48144 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_MASK)
48145 
48146 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_MASK (0x80U)
48147 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT (7U)
48148 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_MASK)
48149 
48150 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK (0x100U)
48151 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT (8U)
48152 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK)
48153 
48154 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_MASK (0x200U)
48155 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_SHIFT (9U)
48156 #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_MASK)
48157 
48158 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_MASK (0x400U)
48159 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_SHIFT (10U)
48160 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_MASK)
48161 
48162 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_MASK (0x800U)
48163 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_SHIFT (11U)
48164 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_MASK)
48165 
48166 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_MASK (0x1000U)
48167 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_SHIFT (12U)
48168 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_MASK)
48169 
48170 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_MASK (0x2000U)
48171 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_SHIFT (13U)
48172 #define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_MASK)
48173 
48174 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_MASK (0x4000U)
48175 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_SHIFT (14U)
48176 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_MASK)
48177 
48178 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_MASK (0x8000U)
48179 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_SHIFT (15U)
48180 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_MASK)
48181 
48182 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_MASK (0x10000U)
48183 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_SHIFT (16U)
48184 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_MASK)
48185 
48186 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_MASK (0x20000U)
48187 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_SHIFT (17U)
48188 #define GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_MASK)
48189 
48190 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_MASK (0x40000U)
48191 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_SHIFT (18U)
48192 #define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_MASK)
48193 
48194 #define GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_MASK (0x80000U)
48195 #define GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_SHIFT (19U)
48196 #define GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_MASK)
48197 /*! @} */
48198 
48199 /* The count of GPC_M7_PU_PGC_PDN_STATUS */
48200 #define GPC_M7_PU_PGC_PDN_STATUS_COUNT           (3U)
48201 
48202 /*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */
48203 /*! @{ */
48204 
48205 #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U)
48206 #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U)
48207 #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x)  (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK)
48208 /*! @} */
48209 
48210 /*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */
48211 /*! @{ */
48212 
48213 #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK   (0xFFFFFU)
48214 #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT  (0U)
48215 #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x)     (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK)
48216 /*! @} */
48217 
48218 /*! @name M7_MIX_PDN_FLG - M7 MIX PDN FLG */
48219 /*! @{ */
48220 
48221 #define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK  (0x1U)
48222 #define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT (0U)
48223 #define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG(x)    (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT)) & GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK)
48224 /*! @} */
48225 
48226 /*! @name M7_PU_PDN_FLG - M7 PU PDN FLG */
48227 /*! @{ */
48228 
48229 #define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK     (0xFFFFFU)
48230 #define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT    (0U)
48231 #define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG(x)       (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT)) & GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK)
48232 /*! @} */
48233 
48234 /*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */
48235 /*! @{ */
48236 
48237 #define GPC_LPCR_A53_BSC2_LPM2_MASK              (0x3U)
48238 #define GPC_LPCR_A53_BSC2_LPM2_SHIFT             (0U)
48239 /*! LPM2
48240  *  0b00..Remain in RUN mode
48241  *  0b01..Transfer to WAIT mode
48242  *  0b10..Transfer to STOP mode
48243  *  0b11..Reserved
48244  */
48245 #define GPC_LPCR_A53_BSC2_LPM2(x)                (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK)
48246 
48247 #define GPC_LPCR_A53_BSC2_LPM3_MASK              (0xCU)
48248 #define GPC_LPCR_A53_BSC2_LPM3_SHIFT             (2U)
48249 /*! LPM3
48250  *  0b00..Remain in RUN mode
48251  *  0b01..Transfer to WAIT mode
48252  *  0b10..Transfer to STOP mode
48253  *  0b11..Reserved
48254  */
48255 #define GPC_LPCR_A53_BSC2_LPM3(x)                (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK)
48256 /*! @} */
48257 
48258 /*! @name PU_PWRHSK - Power handshake register */
48259 /*! @{ */
48260 
48261 #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U)
48262 #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U)
48263 #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK)
48264 
48265 #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK  (0x2U)
48266 #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U)
48267 #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x)    (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK)
48268 
48269 #define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_MASK (0x10U)
48270 #define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_SHIFT (4U)
48271 #define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_MASK)
48272 
48273 #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK (0x20U)
48274 #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT (5U)
48275 #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK)
48276 
48277 #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK (0x40U)
48278 #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT (6U)
48279 #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK)
48280 
48281 #define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_MASK (0x80U)
48282 #define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_SHIFT (7U)
48283 #define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_MASK)
48284 
48285 #define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_MASK (0x100U)
48286 #define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_SHIFT (8U)
48287 #define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_MASK)
48288 
48289 #define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_MASK (0x200U)
48290 #define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_SHIFT (9U)
48291 #define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_MASK)
48292 
48293 #define GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_MASK (0x400U)
48294 #define GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_SHIFT (10U)
48295 #define GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_MASK)
48296 
48297 #define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_MASK (0x800U)
48298 #define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_SHIFT (11U)
48299 #define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_MASK)
48300 
48301 #define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_MASK (0x1000U)
48302 #define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_SHIFT (12U)
48303 #define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_MASK)
48304 
48305 #define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_MASK (0x2000U)
48306 #define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_SHIFT (13U)
48307 #define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_MASK)
48308 
48309 #define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_MASK (0x4000U)
48310 #define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_SHIFT (14U)
48311 #define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_MASK)
48312 
48313 #define GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_MASK (0x8000U)
48314 #define GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_SHIFT (15U)
48315 #define GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_MASK)
48316 
48317 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_MASK (0x10000U)
48318 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_SHIFT (16U)
48319 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_MASK)
48320 
48321 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_MASK (0x20000U)
48322 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_SHIFT (17U)
48323 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_MASK)
48324 
48325 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_MASK  (0x40000U)
48326 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_SHIFT (18U)
48327 #define GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK(x)    (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_MASK)
48328 
48329 #define GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_MASK      (0x80000U)
48330 #define GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_SHIFT     (19U)
48331 #define GPC_PU_PWRHSK_GPC_DDR1_CACTIVE(x)        (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_MASK)
48332 
48333 #define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_MASK (0x100000U)
48334 #define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_SHIFT (20U)
48335 #define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_MASK)
48336 
48337 #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_MASK (0x200000U)
48338 #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_SHIFT (21U)
48339 #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_MASK)
48340 
48341 #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_MASK (0x400000U)
48342 #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_SHIFT (22U)
48343 #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_MASK)
48344 
48345 #define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_MASK (0x800000U)
48346 #define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_SHIFT (23U)
48347 #define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_MASK)
48348 
48349 #define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_MASK (0x1000000U)
48350 #define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_SHIFT (24U)
48351 #define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_MASK)
48352 
48353 #define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_MASK (0x2000000U)
48354 #define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_SHIFT (25U)
48355 #define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_MASK)
48356 
48357 #define GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_MASK (0x4000000U)
48358 #define GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_SHIFT (26U)
48359 #define GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_MASK)
48360 
48361 #define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_MASK (0x8000000U)
48362 #define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_SHIFT (27U)
48363 #define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_MASK)
48364 
48365 #define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_MASK (0x10000000U)
48366 #define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_SHIFT (28U)
48367 #define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_MASK)
48368 
48369 #define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_MASK (0x20000000U)
48370 #define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_SHIFT (29U)
48371 #define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_MASK)
48372 
48373 #define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_MASK (0x40000000U)
48374 #define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_SHIFT (30U)
48375 #define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_MASK)
48376 
48377 #define GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_MASK (0x80000000U)
48378 #define GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_SHIFT (31U)
48379 #define GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_MASK)
48380 /*! @} */
48381 
48382 /*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 5 of A53 core2 */
48383 /*! @{ */
48384 
48385 #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK    (0xFFFFFFFFU)
48386 #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT   (0U)
48387 /*! IMR1_CORE2_A53
48388  *  0b00000000000000000000000000000000..IRQ not masked
48389  *  0b00000000000000000000000000000001..IRQ masked
48390  */
48391 #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK)
48392 
48393 #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK    (0xFFFFFFFFU)
48394 #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT   (0U)
48395 /*! IMR2_CORE2_A53
48396  *  0b00000000000000000000000000000000..IRQ not masked
48397  *  0b00000000000000000000000000000001..IRQ masked
48398  */
48399 #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK)
48400 
48401 #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK    (0xFFFFFFFFU)
48402 #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT   (0U)
48403 /*! IMR3_CORE2_A53
48404  *  0b00000000000000000000000000000000..IRQ not masked
48405  *  0b00000000000000000000000000000001..IRQ masked
48406  */
48407 #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK)
48408 
48409 #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK    (0xFFFFFFFFU)
48410 #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT   (0U)
48411 /*! IMR4_CORE2_A53
48412  *  0b00000000000000000000000000000000..IRQ not masked
48413  *  0b00000000000000000000000000000001..IRQ masked
48414  */
48415 #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK)
48416 
48417 #define GPC_IMR_CORE2_A53_IMR5_CORE2_A53_MASK    (0xFFFFFFFFU)
48418 #define GPC_IMR_CORE2_A53_IMR5_CORE2_A53_SHIFT   (0U)
48419 /*! IMR5_CORE2_A53
48420  *  0b00000000000000000000000000000000..IRQ not masked
48421  *  0b00000000000000000000000000000001..IRQ masked
48422  */
48423 #define GPC_IMR_CORE2_A53_IMR5_CORE2_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR5_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR5_CORE2_A53_MASK)
48424 /*! @} */
48425 
48426 /* The count of GPC_IMR_CORE2_A53 */
48427 #define GPC_IMR_CORE2_A53_COUNT                  (5U)
48428 
48429 /*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 5 of A53 core3 */
48430 /*! @{ */
48431 
48432 #define GPC_IMR_CORE3_A53_IM5_CORE3_A53_MASK     (0xFFFFFFFFU)
48433 #define GPC_IMR_CORE3_A53_IM5_CORE3_A53_SHIFT    (0U)
48434 /*! IM5_CORE3_A53
48435  *  0b00000000000000000000000000000000..IRQ not masked
48436  *  0b00000000000000000000000000000001..IRQ masked
48437  */
48438 #define GPC_IMR_CORE3_A53_IM5_CORE3_A53(x)       (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IM5_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IM5_CORE3_A53_MASK)
48439 
48440 #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK    (0xFFFFFFFFU)
48441 #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT   (0U)
48442 /*! IMR1_CORE3_A53
48443  *  0b00000000000000000000000000000000..IRQ not masked
48444  *  0b00000000000000000000000000000001..IRQ masked
48445  */
48446 #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK)
48447 
48448 #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK    (0xFFFFFFFFU)
48449 #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT   (0U)
48450 /*! IMR2_CORE3_A53
48451  *  0b00000000000000000000000000000000..IRQ not masked
48452  *  0b00000000000000000000000000000001..IRQ masked
48453  */
48454 #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK)
48455 
48456 #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK    (0xFFFFFFFFU)
48457 #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT   (0U)
48458 /*! IMR3_CORE3_A53
48459  *  0b00000000000000000000000000000000..IRQ not masked
48460  *  0b00000000000000000000000000000001..IRQ masked
48461  */
48462 #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK)
48463 
48464 #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK    (0xFFFFFFFFU)
48465 #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT   (0U)
48466 /*! IMR4_CORE3_A53
48467  *  0b00000000000000000000000000000000..IRQ not masked
48468  *  0b00000000000000000000000000000001..IRQ masked
48469  */
48470 #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x)      (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK)
48471 /*! @} */
48472 
48473 /* The count of GPC_IMR_CORE3_A53 */
48474 #define GPC_IMR_CORE3_A53_COUNT                  (5U)
48475 
48476 /*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */
48477 /*! @{ */
48478 
48479 #define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_MASK (0x1U)
48480 #define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT (0U)
48481 #define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_MASK)
48482 
48483 #define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_MASK (0x2U)
48484 #define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT (1U)
48485 #define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_MASK)
48486 
48487 #define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_MASK (0x4U)
48488 #define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT (2U)
48489 #define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_MASK)
48490 
48491 #define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_MASK (0x8U)
48492 #define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT (3U)
48493 #define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_MASK)
48494 
48495 #define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_MASK (0x10U)
48496 #define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_SHIFT (4U)
48497 #define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_MASK)
48498 
48499 #define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_MASK (0x20U)
48500 #define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_SHIFT (5U)
48501 #define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_MASK)
48502 
48503 #define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_MASK (0x40U)
48504 #define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_SHIFT (6U)
48505 #define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_MASK)
48506 
48507 #define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_MASK (0x80U)
48508 #define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_SHIFT (7U)
48509 #define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_MASK)
48510 
48511 #define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_MASK (0x100U)
48512 #define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_SHIFT (8U)
48513 #define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_MASK)
48514 
48515 #define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_MASK (0x200U)
48516 #define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_SHIFT (9U)
48517 #define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_MASK)
48518 
48519 #define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_MASK (0x400U)
48520 #define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT (10U)
48521 #define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_MASK)
48522 
48523 #define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_MASK (0x800U)
48524 #define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT (11U)
48525 #define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_MASK)
48526 
48527 #define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_MASK (0x1000U)
48528 #define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_SHIFT (12U)
48529 #define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_MASK)
48530 
48531 #define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_MASK (0x2000U)
48532 #define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_SHIFT (13U)
48533 #define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_MASK)
48534 
48535 #define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x4000U)
48536 #define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (14U)
48537 #define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK)
48538 
48539 #define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x8000U)
48540 #define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (15U)
48541 #define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK)
48542 
48543 #define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x10000U)
48544 #define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (16U)
48545 #define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK)
48546 
48547 #define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x20000U)
48548 #define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (17U)
48549 #define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK)
48550 
48551 #define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_MASK (0x40000U)
48552 #define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_SHIFT (18U)
48553 #define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_MASK)
48554 
48555 #define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_MASK (0x80000U)
48556 #define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_SHIFT (19U)
48557 #define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_MASK)
48558 
48559 #define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_MASK (0x100000U)
48560 #define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_SHIFT (20U)
48561 #define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_MASK)
48562 
48563 #define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_MASK (0x200000U)
48564 #define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_SHIFT (21U)
48565 #define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_MASK)
48566 
48567 #define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_MASK (0x400000U)
48568 #define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_SHIFT (22U)
48569 #define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_MASK)
48570 
48571 #define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_MASK (0x800000U)
48572 #define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_SHIFT (23U)
48573 #define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_MASK)
48574 
48575 #define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_MASK (0x1000000U)
48576 #define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_SHIFT (24U)
48577 #define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_MASK)
48578 
48579 #define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_MASK (0x2000000U)
48580 #define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_SHIFT (25U)
48581 #define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_MASK)
48582 
48583 #define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_MASK (0x4000000U)
48584 #define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT (26U)
48585 #define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_MASK)
48586 
48587 #define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_MASK (0x8000000U)
48588 #define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT (27U)
48589 #define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_MASK)
48590 
48591 #define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_MASK (0x10000000U)
48592 #define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_SHIFT (28U)
48593 #define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_MASK)
48594 
48595 #define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_MASK (0x20000000U)
48596 #define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_SHIFT (29U)
48597 #define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_MASK)
48598 
48599 #define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_MASK (0x40000000U)
48600 #define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT (30U)
48601 #define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_MASK)
48602 
48603 #define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_MASK (0x80000000U)
48604 #define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT (31U)
48605 #define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_MASK)
48606 /*! @} */
48607 
48608 /*! @name ACK_SEL_A53_PU1 - PGC acknowledge signal selection of A53 platform for PUs */
48609 /*! @{ */
48610 
48611 #define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK (0x1U)
48612 #define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT (0U)
48613 #define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK)
48614 
48615 #define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK (0x2U)
48616 #define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT (1U)
48617 #define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK)
48618 
48619 #define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_MASK (0x4U)
48620 #define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT (2U)
48621 #define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_MASK)
48622 
48623 #define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_MASK (0x8U)
48624 #define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT (3U)
48625 #define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_MASK)
48626 
48627 #define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK (0x10U)
48628 #define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT (4U)
48629 #define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK)
48630 
48631 #define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK (0x20U)
48632 #define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT (5U)
48633 #define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK)
48634 
48635 #define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_MASK (0x40U)
48636 #define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_SHIFT (6U)
48637 #define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_MASK)
48638 
48639 #define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_MASK (0x80U)
48640 #define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_SHIFT (7U)
48641 #define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_MASK)
48642 /*! @} */
48643 
48644 /*! @name ACK_SEL_M7_PU - PGC acknowledge signal selection of M7 platform for PUs */
48645 /*! @{ */
48646 
48647 #define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_MASK (0x1U)
48648 #define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT (0U)
48649 #define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_MASK)
48650 
48651 #define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_MASK (0x2U)
48652 #define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT (1U)
48653 #define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_MASK)
48654 
48655 #define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_MASK (0x4U)
48656 #define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT (2U)
48657 #define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_MASK)
48658 
48659 #define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_MASK (0x8U)
48660 #define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT (3U)
48661 #define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_MASK)
48662 
48663 #define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_MASK (0x10U)
48664 #define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_SHIFT (4U)
48665 #define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_MASK)
48666 
48667 #define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_MASK (0x20U)
48668 #define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_SHIFT (5U)
48669 #define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_MASK)
48670 
48671 #define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_MASK (0x40U)
48672 #define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_SHIFT (6U)
48673 #define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_MASK)
48674 
48675 #define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_MASK (0x80U)
48676 #define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_SHIFT (7U)
48677 #define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_MASK)
48678 
48679 #define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_MASK (0x100U)
48680 #define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_SHIFT (8U)
48681 #define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_MASK)
48682 
48683 #define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_MASK (0x200U)
48684 #define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_SHIFT (9U)
48685 #define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_MASK)
48686 
48687 #define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_MASK (0x400U)
48688 #define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT (10U)
48689 #define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_MASK)
48690 
48691 #define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_MASK (0x800U)
48692 #define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT (11U)
48693 #define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_MASK)
48694 
48695 #define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_MASK (0x1000U)
48696 #define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_SHIFT (12U)
48697 #define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_MASK)
48698 
48699 #define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_MASK (0x2000U)
48700 #define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_SHIFT (13U)
48701 #define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_MASK)
48702 
48703 #define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x4000U)
48704 #define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (14U)
48705 #define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK)
48706 
48707 #define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x8000U)
48708 #define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (15U)
48709 #define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK)
48710 
48711 #define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x10000U)
48712 #define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (16U)
48713 #define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK)
48714 
48715 #define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x20000U)
48716 #define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (17U)
48717 #define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK)
48718 
48719 #define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_MASK (0x40000U)
48720 #define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_SHIFT (18U)
48721 #define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_MASK)
48722 
48723 #define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_MASK (0x80000U)
48724 #define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_SHIFT (19U)
48725 #define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_MASK)
48726 
48727 #define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_MASK (0x100000U)
48728 #define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_SHIFT (20U)
48729 #define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_MASK)
48730 
48731 #define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_MASK (0x200000U)
48732 #define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_SHIFT (21U)
48733 #define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_MASK)
48734 
48735 #define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_MASK (0x400000U)
48736 #define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_SHIFT (22U)
48737 #define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_MASK)
48738 
48739 #define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_MASK (0x800000U)
48740 #define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_SHIFT (23U)
48741 #define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_MASK)
48742 
48743 #define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_MASK (0x1000000U)
48744 #define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_SHIFT (24U)
48745 #define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_MASK)
48746 
48747 #define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_MASK (0x2000000U)
48748 #define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_SHIFT (25U)
48749 #define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK(x)  (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_MASK)
48750 
48751 #define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_MASK (0x4000000U)
48752 #define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT (26U)
48753 #define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_MASK)
48754 
48755 #define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_MASK (0x8000000U)
48756 #define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT (27U)
48757 #define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_MASK)
48758 
48759 #define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_MASK (0x10000000U)
48760 #define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_SHIFT (28U)
48761 #define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_MASK)
48762 
48763 #define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_MASK (0x20000000U)
48764 #define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_SHIFT (29U)
48765 #define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_MASK)
48766 
48767 #define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_MASK (0x40000000U)
48768 #define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT (30U)
48769 #define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_MASK)
48770 
48771 #define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_MASK (0x80000000U)
48772 #define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT (31U)
48773 #define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_MASK)
48774 /*! @} */
48775 
48776 /*! @name ACK_SEL_M7_PU1 - PGC acknowledge signal selection of M7 platform for PUs */
48777 /*! @{ */
48778 
48779 #define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK (0x1U)
48780 #define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT (0U)
48781 #define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK)
48782 
48783 #define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK (0x2U)
48784 #define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT (1U)
48785 #define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK)
48786 
48787 #define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_MASK (0x4U)
48788 #define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT (2U)
48789 #define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_MASK)
48790 
48791 #define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_MASK (0x8U)
48792 #define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT (3U)
48793 #define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_MASK)
48794 
48795 #define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK (0x10U)
48796 #define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT (4U)
48797 #define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK)
48798 
48799 #define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK (0x20U)
48800 #define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT (5U)
48801 #define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK)
48802 
48803 #define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_MASK (0x40U)
48804 #define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_SHIFT (6U)
48805 #define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_MASK)
48806 
48807 #define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_MASK (0x80U)
48808 #define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_SHIFT (7U)
48809 #define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_MASK)
48810 /*! @} */
48811 
48812 /*! @name PGC_CPU_A53_MAPPING - PGC CPU A53 mapping */
48813 /*! @{ */
48814 
48815 #define GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK (0x1U)
48816 #define GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT (0U)
48817 /*! MIX0_SUPERMIXM7_DOMAIN
48818  *  0b0..Don't map M7 to A53 domain
48819  *  0b1..Map M7 to A53 domain
48820  */
48821 #define GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK)
48822 
48823 #define GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_MASK (0x2U)
48824 #define GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_SHIFT (1U)
48825 /*! MIX1_NOC_DOMAIN
48826  *  0b0..Don't map NOC to A53 domain
48827  *  0b1..Map NOC to A53 domain
48828  */
48829 #define GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_MASK)
48830 
48831 #define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_MASK (0x4U)
48832 #define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_SHIFT (2U)
48833 /*! MIPI_PHY1_DOMAIN
48834  *  0b0..Don't map MIPI_PHY1 to A53 domain
48835  *  0b1..Map MIPI_PHY1 to A53 domain
48836  */
48837 #define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_MASK)
48838 
48839 #define GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_MASK (0x8U)
48840 #define GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_SHIFT (3U)
48841 /*! PCIE_PHY_DOMAIN
48842  *  0b0..Don't map PCIE_PHY to A53 domain
48843  *  0b1..Map PCIE_PHY to A53 domain
48844  */
48845 #define GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_MASK)
48846 
48847 #define GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_MASK (0x10U)
48848 #define GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_SHIFT (4U)
48849 /*! USB1_PHY_DOMAIN
48850  *  0b0..Don't map USB1_PHY to A53 domain
48851  *  0b1..Map USB1_PHY to A53 domain
48852  */
48853 #define GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_MASK)
48854 
48855 #define GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_MASK (0x20U)
48856 #define GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_SHIFT (5U)
48857 /*! USB2_PHY_DOMAIN
48858  *  0b0..Don't map USB2_PHY to A53 domain
48859  *  0b1..Map USB2_PHY to A53 domain
48860  */
48861 #define GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_MASK)
48862 
48863 #define GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_MASK (0x40U)
48864 #define GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_SHIFT (6U)
48865 /*! MLMIX_DOMAIN
48866  *  0b0..Don't map MLMIX to A53 domain
48867  *  0b1..Map MLMIX to A53 domain
48868  */
48869 #define GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_MASK)
48870 
48871 #define GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_MASK (0x80U)
48872 #define GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_SHIFT (7U)
48873 /*! AUDIOMIX_DOMAIN
48874  *  0b0..Don't map AUDIOMIX to A53 domain
48875  *  0b1..Map AUDIOMIX to A53 domain
48876  */
48877 #define GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_MASK)
48878 
48879 #define GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_MASK (0x100U)
48880 #define GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_SHIFT (8U)
48881 /*! GPU_2D_DOMAIN
48882  *  0b0..Don't map GPU2D to A53 domain
48883  *  0b1..Map GPU2D to A53 domain
48884  */
48885 #define GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_MASK)
48886 
48887 #define GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK (0x200U)
48888 #define GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT (9U)
48889 /*! GPU_SHARE_LOGIC_DOMAIN
48890  *  0b0..Don't map GPU Share Logic to A53 domain
48891  *  0b1..Map GPU Share Logic to A53 domain
48892  */
48893 #define GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK)
48894 
48895 #define GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK (0x400U)
48896 #define GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT (10U)
48897 /*! VPUMIX_SHARE_LOGIC_DOMAIN
48898  *  0b0..Don't map VPUMIX Share Logic to A53 domain
48899  *  0b1..Map VPUMIX Share Logic to A53 domain
48900  */
48901 #define GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK)
48902 
48903 #define GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_MASK (0x800U)
48904 #define GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_SHIFT (11U)
48905 /*! GPU3D_DOMAIN
48906  *  0b0..Don't map GPU2D to A53 domain
48907  *  0b1..Map GPU2D to A53 domain
48908  */
48909 #define GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_MASK)
48910 
48911 #define GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_MASK (0x1000U)
48912 #define GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_SHIFT (12U)
48913 /*! MEDIMIX_DOMAIN
48914  *  0b0..Don't map MEDIMIX to A53 domain
48915  *  0b1..Map MEDIMIX to A53 domain
48916  */
48917 #define GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_MASK)
48918 
48919 #define GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_MASK (0x2000U)
48920 #define GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_SHIFT (13U)
48921 /*! VPU_G1_DOMAIN
48922  *  0b0..Don't map VPU_G1 to A53 domain
48923  *  0b1..Map VPU_G1 to A53 domain
48924  */
48925 #define GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_MASK)
48926 
48927 #define GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_MASK (0x4000U)
48928 #define GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_SHIFT (14U)
48929 /*! VPU_G2_DOMAIN
48930  *  0b0..Don't map VPU_G1 to A53 domain
48931  *  0b1..Map VPU_G1 to A53 domain
48932  */
48933 #define GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_MASK)
48934 
48935 #define GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_MASK (0x8000U)
48936 #define GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_SHIFT (15U)
48937 /*! VPU_VC8K_DOMAIN
48938  *  0b0..Don't map VPU_VC8K to A53 domain
48939  *  0b1..Map VPU_VC8K to A53 domain
48940  */
48941 #define GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_MASK)
48942 
48943 #define GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_MASK (0x10000U)
48944 #define GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_SHIFT (16U)
48945 /*! HDMIMIX_DOMAIN
48946  *  0b0..Don't map HDMI to A53 domain
48947  *  0b1..Map HDMI to A53 domain
48948  */
48949 #define GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_MASK)
48950 
48951 #define GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_MASK (0x20000U)
48952 #define GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_SHIFT (17U)
48953 /*! HDMI_PHY_DOMAIN
48954  *  0b0..Don't map HDMI PHY to A53 domain
48955  *  0b1..Map HDMI PHY to A53 domain
48956  */
48957 #define GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_MASK)
48958 
48959 #define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_MASK (0x40000U)
48960 #define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_SHIFT (18U)
48961 /*! MIPI_PHY2_DOMAIN
48962  *  0b0..Don't map MIPI PHY2 to A53 domain
48963  *  0b1..Map MIPI PHY2 to A53 domain
48964  */
48965 #define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_MASK)
48966 
48967 #define GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_MASK (0x80000U)
48968 #define GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_SHIFT (19U)
48969 /*! HSIOMIX_DOMAIN
48970  *  0b0..Don't map HSIOMIX to A53 domain
48971  *  0b1..Map HSIOMIX to A53 domain
48972  */
48973 #define GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_MASK)
48974 
48975 #define GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK (0x100000U)
48976 #define GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT (20U)
48977 /*! MEDIA_ISP_DWP_DOMAIN
48978  *  0b0..Don't map MEDIA_ISP_DWP_DOMAIN to A53 domain
48979  *  0b1..Map DDR to MEDIA_ISP_DWP_DOMAIN domain
48980  */
48981 #define GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK)
48982 
48983 #define GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_MASK (0x200000U)
48984 #define GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_SHIFT (21U)
48985 /*! DDRMIX_DOMAIN
48986  *  0b0..Don't map DDR to A53 domain
48987  *  0b1..Map DDR to A53 domain
48988  */
48989 #define GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_MASK)
48990 /*! @} */
48991 
48992 /*! @name PGC_CPU_M7_MAPPING - PGC CPU M7 mapping */
48993 /*! @{ */
48994 
48995 #define GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK (0x1U)
48996 #define GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT (0U)
48997 /*! MIX0_SUPERMIXM7_DOMAIN
48998  *  0b0..Don't map MIX0_SUPERMIXM7 to M7 domain
48999  *  0b1..Map MIX0_SUPERMIXM7 to M7 domain
49000  */
49001 #define GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK)
49002 
49003 #define GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_MASK (0x2U)
49004 #define GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_SHIFT (1U)
49005 /*! MIX1_NOC_DOMAIN
49006  *  0b0..Don't map MIX1_NOC to M7 domain
49007  *  0b1..Map MIX1_NOC to M7 domain
49008  */
49009 #define GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_MASK)
49010 
49011 #define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_MASK (0x4U)
49012 #define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_SHIFT (2U)
49013 /*! MIPI_PHY1_DOMAIN
49014  *  0b0..Don't map MIPI_PHY1 to M7 domain
49015  *  0b1..Map MIPI_PHY1 to M7 domain
49016  */
49017 #define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_MASK)
49018 
49019 #define GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_MASK (0x8U)
49020 #define GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_SHIFT (3U)
49021 /*! PCIE_PHY_DOMAIN
49022  *  0b0..Don't map PCIE_PHY to M7 domain
49023  *  0b1..Map PCIE_PHY to M7 domain
49024  */
49025 #define GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_MASK)
49026 
49027 #define GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_MASK (0x10U)
49028 #define GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_SHIFT (4U)
49029 /*! USB1_PHY_DOMAIN
49030  *  0b0..Don't map USB1_PHY to M7 domain
49031  *  0b1..Map USB1_PHY to M7 domain
49032  */
49033 #define GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_MASK)
49034 
49035 #define GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_MASK (0x20U)
49036 #define GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_SHIFT (5U)
49037 /*! USB2_PHY_DOMAIN
49038  *  0b0..Don't map USB2_PHY to M7 domain
49039  *  0b1..Map USB2_PHY to M7 domain
49040  */
49041 #define GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_MASK)
49042 
49043 #define GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_MASK (0x40U)
49044 #define GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_SHIFT (6U)
49045 /*! MLMIX_DOMAIN
49046  *  0b0..Don't map MLMIX to M7 domain
49047  *  0b1..Map MLMIX to M7 domain
49048  */
49049 #define GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_MASK)
49050 
49051 #define GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_MASK (0x80U)
49052 #define GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_SHIFT (7U)
49053 /*! AUDIOMIX_DOMAIN
49054  *  0b0..Don't map AUDIOMIX to M7 domain
49055  *  0b1..Map AUDIOMIX to M7 domain
49056  */
49057 #define GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_MASK)
49058 
49059 #define GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_MASK (0x100U)
49060 #define GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_SHIFT (8U)
49061 /*! GPU_2D_DOMAIN
49062  *  0b0..Don't map GPU2D to M7 domain
49063  *  0b1..Map GPU2D to M7 domain
49064  */
49065 #define GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_MASK)
49066 
49067 #define GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK (0x200U)
49068 #define GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT (9U)
49069 /*! GPU_SHARE_LOGIC_DOMAIN
49070  *  0b0..Don't map GPU Share Logic to M7 domain
49071  *  0b1..Map GPU Share Logic to M7 domain
49072  */
49073 #define GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK)
49074 
49075 #define GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK (0x400U)
49076 #define GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT (10U)
49077 /*! VPUMIX_SHARE_LOGIC_DOMAIN
49078  *  0b0..Don't map VPUMIX Share Logic to M7 domain
49079  *  0b1..Map VPUMIX Share Logic to M7 domain
49080  */
49081 #define GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK)
49082 
49083 #define GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_MASK (0x800U)
49084 #define GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_SHIFT (11U)
49085 /*! GPU3D_DOMAIN
49086  *  0b0..Don't map GPU2D to M7 domain
49087  *  0b1..Map GPU2D to M7 domain
49088  */
49089 #define GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_MASK)
49090 
49091 #define GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_MASK (0x1000U)
49092 #define GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_SHIFT (12U)
49093 /*! MEDIMIX_DOMAIN
49094  *  0b0..Don't map MEDIMIX to M7 domain
49095  *  0b1..Map MEDIMIX to M7 domain
49096  */
49097 #define GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_MASK)
49098 
49099 #define GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_MASK (0x2000U)
49100 #define GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_SHIFT (13U)
49101 /*! VPU_G1_DOMAIN
49102  *  0b0..Don't map VPU_G1 to M7 domain
49103  *  0b1..Map VPU_G1 to M7 domain
49104  */
49105 #define GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_MASK)
49106 
49107 #define GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_MASK (0x4000U)
49108 #define GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_SHIFT (14U)
49109 /*! VPU_G2_DOMAIN
49110  *  0b0..Don't map VPU_G1 to M7 domain
49111  *  0b1..Map VPU_G1 to M7 domain
49112  */
49113 #define GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_MASK)
49114 
49115 #define GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_MASK (0x8000U)
49116 #define GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_SHIFT (15U)
49117 /*! VPU_VC8K_DOMAIN
49118  *  0b0..Don't map VPU_VC8K to M7 domain
49119  *  0b1..Map VPU_VC8K to M7 domain
49120  */
49121 #define GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_MASK)
49122 
49123 #define GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_MASK (0x10000U)
49124 #define GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_SHIFT (16U)
49125 /*! HDMIMIX_DOMAIN
49126  *  0b0..Don't map HDMI to M7 domain
49127  *  0b1..Map HDMI to M7 domain
49128  */
49129 #define GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_MASK)
49130 
49131 #define GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_MASK (0x20000U)
49132 #define GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_SHIFT (17U)
49133 /*! HDMI_PHY_DOMAIN
49134  *  0b0..Don't map HDMI PHY to M7 domain
49135  *  0b1..Map HDMI PHY to M7 domain
49136  */
49137 #define GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_MASK)
49138 
49139 #define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_MASK (0x40000U)
49140 #define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_SHIFT (18U)
49141 /*! MIPI_PHY2_DOMAIN
49142  *  0b0..Don't map MIPI PHY2 to M7 domain
49143  *  0b1..Map MIPI PHY2 to M7 domain
49144  */
49145 #define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_MASK)
49146 
49147 #define GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_MASK (0x80000U)
49148 #define GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_SHIFT (19U)
49149 /*! HSIOMIX_DOMAIN
49150  *  0b0..Don't map HSIOMIX to M7 domain
49151  *  0b1..Map HSIOMIX to M7 domain
49152  */
49153 #define GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_MASK)
49154 
49155 #define GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK (0x100000U)
49156 #define GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT (20U)
49157 /*! MEDIA_ISP_DWP_DOMAIN
49158  *  0b0..Don't map MEDIA_ISP_DWP_DOMAIN to M7 domain
49159  *  0b1..Map MEDIA_ISP_DWP_DOMAIN to M7 domain
49160  */
49161 #define GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK)
49162 
49163 #define GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_MASK (0x200000U)
49164 #define GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_SHIFT (21U)
49165 /*! DDRMIX_DOMAIN
49166  *  0b0..Don't map DDR to M7 domain
49167  *  0b1..Map DDR to M7 domain
49168  */
49169 #define GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_MASK)
49170 /*! @} */
49171 
49172 /*! @name SLT_CFG - Slot configure register for CPUs */
49173 /*! @{ */
49174 
49175 #define GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
49176 #define GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
49177 #define GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
49178 
49179 #define GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
49180 #define GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
49181 #define GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
49182 
49183 #define GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
49184 #define GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
49185 #define GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
49186 
49187 #define GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
49188 #define GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
49189 #define GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
49190 
49191 #define GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
49192 #define GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
49193 #define GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
49194 
49195 #define GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
49196 #define GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
49197 #define GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
49198 
49199 #define GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
49200 #define GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
49201 #define GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
49202 
49203 #define GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
49204 #define GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
49205 #define GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
49206 
49207 #define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_MASK    (0x100U)
49208 #define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_SHIFT   (8U)
49209 #define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL(x)      (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_MASK)
49210 
49211 #define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_MASK    (0x200U)
49212 #define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_SHIFT   (9U)
49213 #define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL(x)      (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_MASK)
49214 
49215 #define GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_MASK    (0x1000U)
49216 #define GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_SHIFT   (12U)
49217 #define GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL(x)      (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_MASK)
49218 
49219 #define GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_MASK    (0x2000U)
49220 #define GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_SHIFT   (13U)
49221 #define GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL(x)      (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_MASK)
49222 /*! @} */
49223 
49224 /* The count of GPC_SLT_CFG */
49225 #define GPC_SLT_CFG_COUNT                        (27U)
49226 
49227 /*! @name SLT_CFG_PU - Slot configure register for PGC PUs */
49228 /*! @{ */
49229 
49230 #define GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_MASK (0x1U)
49231 #define GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_SHIFT (0U)
49232 #define GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_MASK)
49233 
49234 #define GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_MASK (0x2U)
49235 #define GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_SHIFT (1U)
49236 #define GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_MASK)
49237 
49238 #define GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_MASK (0x4U)
49239 #define GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_SHIFT (2U)
49240 #define GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_MASK)
49241 
49242 #define GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_MASK (0x8U)
49243 #define GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_SHIFT (3U)
49244 #define GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_MASK)
49245 
49246 #define GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_MASK (0x10U)
49247 #define GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_SHIFT (4U)
49248 #define GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_MASK)
49249 
49250 #define GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_MASK (0x20U)
49251 #define GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_SHIFT (5U)
49252 #define GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_MASK)
49253 
49254 #define GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_MASK (0x40U)
49255 #define GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_SHIFT (6U)
49256 #define GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_MASK)
49257 
49258 #define GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_MASK (0x80U)
49259 #define GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_SHIFT (7U)
49260 #define GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_MASK)
49261 
49262 #define GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_MASK (0x100U)
49263 #define GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_SHIFT (8U)
49264 #define GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_MASK)
49265 
49266 #define GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_MASK (0x200U)
49267 #define GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_SHIFT (9U)
49268 #define GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_MASK)
49269 
49270 #define GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_MASK (0x400U)
49271 #define GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_SHIFT (10U)
49272 #define GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_MASK)
49273 
49274 #define GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_MASK (0x800U)
49275 #define GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_SHIFT (11U)
49276 #define GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_MASK)
49277 
49278 #define GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_MASK (0x1000U)
49279 #define GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_SHIFT (12U)
49280 #define GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_MASK)
49281 
49282 #define GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_MASK (0x2000U)
49283 #define GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_SHIFT (13U)
49284 #define GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_MASK)
49285 
49286 #define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK (0x4000U)
49287 #define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT (14U)
49288 #define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK)
49289 
49290 #define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK (0x8000U)
49291 #define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT (15U)
49292 #define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK)
49293 
49294 #define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK (0x10000U)
49295 #define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT (16U)
49296 #define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK)
49297 
49298 #define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK (0x20000U)
49299 #define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT (17U)
49300 #define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK)
49301 
49302 #define GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_MASK (0x40000U)
49303 #define GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_SHIFT (18U)
49304 #define GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_MASK)
49305 
49306 #define GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_MASK (0x80000U)
49307 #define GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_SHIFT (19U)
49308 #define GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_MASK)
49309 
49310 #define GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_MASK (0x100000U)
49311 #define GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_SHIFT (20U)
49312 #define GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_MASK)
49313 
49314 #define GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_MASK (0x200000U)
49315 #define GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_SHIFT (21U)
49316 #define GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_MASK)
49317 
49318 #define GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_MASK (0x400000U)
49319 #define GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_SHIFT (22U)
49320 #define GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_MASK)
49321 
49322 #define GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_MASK (0x800000U)
49323 #define GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_SHIFT (23U)
49324 #define GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_MASK)
49325 
49326 #define GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_MASK (0x1000000U)
49327 #define GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_SHIFT (24U)
49328 #define GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_MASK)
49329 
49330 #define GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_MASK (0x2000000U)
49331 #define GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_SHIFT (25U)
49332 #define GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_MASK)
49333 
49334 #define GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_MASK (0x4000000U)
49335 #define GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_SHIFT (26U)
49336 #define GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_MASK)
49337 
49338 #define GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_MASK (0x8000000U)
49339 #define GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_SHIFT (27U)
49340 #define GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_MASK)
49341 
49342 #define GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_MASK (0x10000000U)
49343 #define GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_SHIFT (28U)
49344 #define GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_MASK)
49345 
49346 #define GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_MASK (0x20000000U)
49347 #define GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_SHIFT (29U)
49348 #define GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_MASK)
49349 
49350 #define GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_MASK (0x40000000U)
49351 #define GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_SHIFT (30U)
49352 #define GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_MASK)
49353 
49354 #define GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_MASK (0x80000000U)
49355 #define GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_SHIFT (31U)
49356 #define GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_MASK)
49357 /*! @} */
49358 
49359 /* The count of GPC_SLT_CFG_PU */
49360 #define GPC_SLT_CFG_PU_COUNT                     (27U)
49361 
49362 /*! @name SLT_CFG_PU1 - Extended slot configure register for PGC PUs */
49363 /*! @{ */
49364 
49365 #define GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_MASK (0x1U)
49366 #define GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_SHIFT (0U)
49367 #define GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_MASK)
49368 
49369 #define GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_MASK (0x2U)
49370 #define GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_SHIFT (1U)
49371 #define GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_MASK)
49372 
49373 #define GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_MASK (0x4U)
49374 #define GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_SHIFT (2U)
49375 #define GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_MASK)
49376 
49377 #define GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_MASK (0x8U)
49378 #define GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_SHIFT (3U)
49379 #define GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_MASK)
49380 
49381 #define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_MASK (0x10U)
49382 #define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_SHIFT (4U)
49383 #define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_MASK)
49384 
49385 #define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_MASK (0x20U)
49386 #define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_SHIFT (5U)
49387 #define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_MASK)
49388 
49389 #define GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_MASK (0x40U)
49390 #define GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_SHIFT (6U)
49391 #define GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_MASK)
49392 
49393 #define GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_MASK (0x80U)
49394 #define GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_SHIFT (7U)
49395 #define GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_MASK)
49396 
49397 #define GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_MASK (0x100U)
49398 #define GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_SHIFT (8U)
49399 #define GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_MASK)
49400 
49401 #define GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_MASK (0x200U)
49402 #define GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_SHIFT (9U)
49403 #define GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_MASK)
49404 /*! @} */
49405 
49406 /* The count of GPC_SLT_CFG_PU1 */
49407 #define GPC_SLT_CFG_PU1_COUNT                    (27U)
49408 
49409 
49410 /*!
49411  * @}
49412  */ /* end of group GPC_Register_Masks */
49413 
49414 
49415 /* GPC - Peripheral instance base addresses */
49416 /** Peripheral GPC base address */
49417 #define GPC_BASE                                 (0x303A0000u)
49418 /** Peripheral GPC base pointer */
49419 #define GPC                                      ((GPC_Type *)GPC_BASE)
49420 /** Array initializer of GPC peripheral base addresses */
49421 #define GPC_BASE_ADDRS                           { GPC_BASE }
49422 /** Array initializer of GPC peripheral base pointers */
49423 #define GPC_BASE_PTRS                            { GPC }
49424 
49425 /*!
49426  * @}
49427  */ /* end of group GPC_Peripheral_Access_Layer */
49428 
49429 
49430 /* ----------------------------------------------------------------------------
49431    -- GPC_PGC Peripheral Access Layer
49432    ---------------------------------------------------------------------------- */
49433 
49434 /*!
49435  * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer
49436  * @{
49437  */
49438 
49439 /** GPC_PGC - Register Layout Typedef */
49440 typedef struct {
49441        uint8_t RESERVED_0[2048];
49442   struct {                                         /* offset: 0x800, array step: 0x40 */
49443     __IO uint32_t PGC_CTRL;                          /**< GPC PGC Control Register for PGC CPUs, array offset: 0x800, array step: 0x40 */
49444     __IO uint32_t PGC_PUPSCR;                        /**< GPC PGC Up Sequence Control Register, array offset: 0x804, array step: 0x40 */
49445     __IO uint32_t PGC_PDNSCR;                        /**< GPC PGC Down Sequence Control Register, array offset: 0x808, array step: 0x40 */
49446     __IO uint32_t PGC_SR;                            /**< GPC PGC Status Register, array offset: 0x80C, array step: 0x40 */
49447          uint8_t RESERVED_0[48];
49448   } GPC_PGC_A53COREnCTRL[4];
49449   __IO uint32_t A53SCU_CTRL;                       /**< GPC PGC Control Register for PGC CPUs, offset: 0x900 */
49450   __IO uint32_t A53SCU_PUPSCR;                     /**< GPC PGC Up Sequence Control Register, offset: 0x904 */
49451   __IO uint32_t A53SCU_PDNSCR;                     /**< GPC PGC Down Sequence Control Register, offset: 0x908 */
49452   __IO uint32_t A53SCU_SR;                         /**< GPC PGC Status Register, offset: 0x90C */
49453        uint8_t RESERVED_1[304];
49454   __IO uint32_t NOC_MIX_CTRL;                      /**< GPC PGC Control Register for PGC MIX., offset: 0xA40 */
49455   __IO uint32_t NOC_MIX_PUPSCR;                    /**< GPC PGC Up Sequence Control Register, offset: 0xA44 */
49456   __IO uint32_t NOC_MIX_PDNSCR;                    /**< GPC PGC Down Sequence Control Register, offset: 0xA48 */
49457   __IO uint32_t NOC_MIX_SR;                        /**< GPC PGC Status Register, offset: 0xA4C */
49458        uint8_t RESERVED_2[176];
49459   struct {                                         /* offset: 0xB00, array step: 0x40 */
49460     __IO uint32_t PU_CTRL;                           /**< GPC PGC Control Register for PGC PUs, array offset: 0xB00, array step: 0x40 */
49461     __IO uint32_t PU_PUPSCR;                         /**< GPC PGC Up Sequence Control Register, array offset: 0xB04, array step: 0x40 */
49462     __IO uint32_t PU_PDNSCR;                         /**< GPC PGC Down Sequence Control Register, array offset: 0xB08, array step: 0x40 */
49463     __IO uint32_t PU_SR;                             /**< GPC PGC Status Register, array offset: 0xB0C, array step: 0x40 */
49464          uint8_t RESERVED_0[48];
49465   } GPC_PGC_CTRL[20];
49466 } GPC_PGC_Type;
49467 
49468 /* ----------------------------------------------------------------------------
49469    -- GPC_PGC Register Masks
49470    ---------------------------------------------------------------------------- */
49471 
49472 /*!
49473  * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks
49474  * @{
49475  */
49476 
49477 /*! @name PGC_CTRL - GPC PGC Control Register for PGC CPUs */
49478 /*! @{ */
49479 
49480 #define GPC_PGC_PGC_CTRL_PCR_MASK                (0x1U)
49481 #define GPC_PGC_PGC_CTRL_PCR_SHIFT               (0U)
49482 /*! PCR
49483  *  0b0..Do not switch off power even if pdn_req is asserted.
49484  *  0b1..Switch off power when pdn_req is asserted.
49485  */
49486 #define GPC_PGC_PGC_CTRL_PCR(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_PCR_SHIFT)) & GPC_PGC_PGC_CTRL_PCR_MASK)
49487 
49488 #define GPC_PGC_PGC_CTRL_L2RSTDIS_MASK           (0x7EU)
49489 #define GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT          (1U)
49490 #define GPC_PGC_PGC_CTRL_L2RSTDIS(x)             (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PGC_CTRL_L2RSTDIS_MASK)
49491 
49492 #define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK        (0x3F00U)
49493 #define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT       (8U)
49494 #define GPC_PGC_PGC_CTRL_DFTRAM_TCD1(x)          (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK)
49495 
49496 #define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK    (0x3F0000U)
49497 #define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT   (16U)
49498 #define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR(x)      (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK)
49499 
49500 #define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
49501 #define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
49502 #define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
49503 /*! @} */
49504 
49505 /* The count of GPC_PGC_PGC_CTRL */
49506 #define GPC_PGC_PGC_CTRL_COUNT                   (4U)
49507 
49508 /*! @name PGC_PUPSCR - GPC PGC Up Sequence Control Register */
49509 /*! @{ */
49510 
49511 #define GPC_PGC_PGC_PUPSCR_SW_MASK               (0x3FU)
49512 #define GPC_PGC_PGC_PUPSCR_SW_SHIFT              (0U)
49513 #define GPC_PGC_PGC_PUPSCR_SW(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW_MASK)
49514 
49515 #define GPC_PGC_PGC_PUPSCR_SW2ISO_MASK           (0x7FFF80U)
49516 #define GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT          (7U)
49517 #define GPC_PGC_PGC_PUPSCR_SW2ISO(x)             (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW2ISO_MASK)
49518 /*! @} */
49519 
49520 /* The count of GPC_PGC_PGC_PUPSCR */
49521 #define GPC_PGC_PGC_PUPSCR_COUNT                 (4U)
49522 
49523 /*! @name PGC_PDNSCR - GPC PGC Down Sequence Control Register */
49524 /*! @{ */
49525 
49526 #define GPC_PGC_PGC_PDNSCR_ISO_MASK              (0x3FU)
49527 #define GPC_PGC_PGC_PDNSCR_ISO_SHIFT             (0U)
49528 #define GPC_PGC_PGC_PDNSCR_ISO(x)                (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO_MASK)
49529 
49530 #define GPC_PGC_PGC_PDNSCR_ISO2SW_MASK           (0x3F00U)
49531 #define GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT          (8U)
49532 #define GPC_PGC_PGC_PDNSCR_ISO2SW(x)             (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO2SW_MASK)
49533 /*! @} */
49534 
49535 /* The count of GPC_PGC_PGC_PDNSCR */
49536 #define GPC_PGC_PGC_PDNSCR_COUNT                 (4U)
49537 
49538 /*! @name PGC_SR - GPC PGC Status Register */
49539 /*! @{ */
49540 
49541 #define GPC_PGC_PGC_SR_PSR_MASK                  (0x1U)
49542 #define GPC_PGC_PGC_SR_PSR_SHIFT                 (0U)
49543 /*! PSR
49544  *  0b0..The target subsystem was not powered down for the previous power-down request.
49545  *  0b1..The target subsystem was powered down for the previous power-down request.
49546  */
49547 #define GPC_PGC_PGC_SR_PSR(x)                    (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PSR_SHIFT)) & GPC_PGC_PGC_SR_PSR_MASK)
49548 
49549 #define GPC_PGC_PGC_SR_L2RETN_FLAG_MASK          (0x2U)
49550 #define GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT         (1U)
49551 /*! L2RETN_FLAG
49552  *  0b0..A53 is not wakeup from L2 retention mode.
49553  *  0b1..A53 is wakeup from L2 retention mode.
49554  */
49555 #define GPC_PGC_PGC_SR_L2RETN_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PGC_SR_L2RETN_FLAG_MASK)
49556 
49557 #define GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK          (0x4U)
49558 #define GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT         (2U)
49559 /*! ALLOFF_FLAG
49560  *  0b0..A53 is not wakeup from ALL_OFF mode.
49561  *  0b1..A53 is wakeup from ALL_OFF mode.
49562  */
49563 #define GPC_PGC_PGC_SR_ALLOFF_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK)
49564 
49565 #define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK      (0x78U)
49566 #define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT     (3U)
49567 /*! PUP_CLK_DIV_SEL
49568  *  0b0000..1
49569  *  0b0001..1/2 count_clk
49570  *  0b0010..1/4 count_clk
49571  *  0b0011..1/8 count_clk
49572  *  0b0100..1/16 count_clk
49573  *  0b0101..1/32 count_clk
49574  *  0b0110..1/64 count_clk
49575  *  0b0111..1/128 count_clk
49576  *  0b1000..1/256 count_clk
49577  *  0b1001..1/512 count_clk
49578  *  0b1010..1/1024 count_clk
49579  *  0b1011..1/2056 count_clk
49580  *  0b1100..1/4096 count_clk
49581  *  0b1101..1/8192 count_clk
49582  *  0b1110..1/16384 count_clk
49583  *  0b1111..1/32768 count_clk
49584  */
49585 #define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK)
49586 
49587 #define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
49588 #define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
49589 #define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK)
49590 /*! @} */
49591 
49592 /* The count of GPC_PGC_PGC_SR */
49593 #define GPC_PGC_PGC_SR_COUNT                     (4U)
49594 
49595 /*! @name A53SCU_CTRL - GPC PGC Control Register for PGC CPUs */
49596 /*! @{ */
49597 
49598 #define GPC_PGC_A53SCU_CTRL_PCR_MASK             (0x1U)
49599 #define GPC_PGC_A53SCU_CTRL_PCR_SHIFT            (0U)
49600 /*! PCR
49601  *  0b0..Do not switch off power even if pdn_req is asserted.
49602  *  0b1..Switch off power when pdn_req is asserted.
49603  */
49604 #define GPC_PGC_A53SCU_CTRL_PCR(x)               (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK)
49605 
49606 #define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK        (0x7EU)
49607 #define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT       (1U)
49608 #define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x)          (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK)
49609 
49610 #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK     (0x3F00U)
49611 #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT    (8U)
49612 #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x)       (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK)
49613 
49614 #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
49615 #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
49616 #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK)
49617 
49618 #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
49619 #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
49620 #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
49621 /*! @} */
49622 
49623 /*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */
49624 /*! @{ */
49625 
49626 #define GPC_PGC_A53SCU_PUPSCR_SW_MASK            (0x3FU)
49627 #define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT           (0U)
49628 #define GPC_PGC_A53SCU_PUPSCR_SW(x)              (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK)
49629 
49630 #define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK        (0x7FFF80U)
49631 #define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT       (7U)
49632 #define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x)          (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK)
49633 /*! @} */
49634 
49635 /*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */
49636 /*! @{ */
49637 
49638 #define GPC_PGC_A53SCU_PDNSCR_ISO_MASK           (0x3FU)
49639 #define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT          (0U)
49640 #define GPC_PGC_A53SCU_PDNSCR_ISO(x)             (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK)
49641 
49642 #define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK        (0x3F00U)
49643 #define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT       (8U)
49644 #define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x)          (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK)
49645 /*! @} */
49646 
49647 /*! @name A53SCU_SR - GPC PGC Status Register */
49648 /*! @{ */
49649 
49650 #define GPC_PGC_A53SCU_SR_PSR_MASK               (0x1U)
49651 #define GPC_PGC_A53SCU_SR_PSR_SHIFT              (0U)
49652 /*! PSR
49653  *  0b0..The target subsystem was not powered down for the previous power-down request.
49654  *  0b1..The target subsystem was powered down for the previous power-down request.
49655  */
49656 #define GPC_PGC_A53SCU_SR_PSR(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK)
49657 
49658 #define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK       (0x2U)
49659 #define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT      (1U)
49660 /*! L2RETN_FLAG
49661  *  0b0..A53 is not wakeup from L2 retention mode.
49662  *  0b1..A53 is wakeup from L2 retention mode.
49663  */
49664 #define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK)
49665 
49666 #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK       (0x4U)
49667 #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT      (2U)
49668 /*! ALLOFF_FLAG
49669  *  0b0..A53 is not wakeup from ALL_OFF mode.
49670  *  0b1..A53 is wakeup from ALL_OFF mode.
49671  */
49672 #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK)
49673 
49674 #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK   (0x78U)
49675 #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT  (3U)
49676 /*! PUP_CLK_DIV_SEL
49677  *  0b0000..1
49678  *  0b0001..1/2 count_clk
49679  *  0b0010..1/4 count_clk
49680  *  0b0011..1/8 count_clk
49681  *  0b0100..1/16 count_clk
49682  *  0b0101..1/32 count_clk
49683  *  0b0110..1/64 count_clk
49684  *  0b0111..1/128 count_clk
49685  *  0b1000..1/256 count_clk
49686  *  0b1001..1/512 count_clk
49687  *  0b1010..1/1024 count_clk
49688  *  0b1011..1/2056 count_clk
49689  *  0b1100..1/4096 count_clk
49690  *  0b1101..1/8192 count_clk
49691  *  0b1110..1/16384 count_clk
49692  *  0b1111..1/32768 count_clk
49693  */
49694 #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x)     (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK)
49695 
49696 #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
49697 #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
49698 #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
49699 /*! @} */
49700 
49701 /*! @name NOC_MIX_CTRL - GPC PGC Control Register for PGC MIX. */
49702 /*! @{ */
49703 
49704 #define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK        (0x1U)
49705 #define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT       (0U)
49706 /*! MIX_PCR
49707  *  0b0..Do not switch off power even if pdn_req is asserted.
49708  *  0b1..Switch off power when pdn_req is asserted.
49709  */
49710 #define GPC_PGC_NOC_MIX_CTRL_MIX_PCR(x)          (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK)
49711 
49712 #define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK       (0x7EU)
49713 #define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT      (1U)
49714 #define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS(x)         (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK)
49715 
49716 #define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK    (0x3F00U)
49717 #define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT   (8U)
49718 #define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1(x)      (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK)
49719 
49720 #define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
49721 #define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
49722 #define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR(x)  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK)
49723 
49724 #define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
49725 #define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
49726 #define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
49727 /*! @} */
49728 
49729 /*! @name NOC_MIX_PUPSCR - GPC PGC Up Sequence Control Register */
49730 /*! @{ */
49731 
49732 #define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
49733 #define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
49734 #define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
49735 
49736 #define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK       (0x7FFF80U)
49737 #define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT      (7U)
49738 #define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO(x)         (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK)
49739 /*! @} */
49740 
49741 /*! @name NOC_MIX_PDNSCR - GPC PGC Down Sequence Control Register */
49742 /*! @{ */
49743 
49744 #define GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK          (0x3FU)
49745 #define GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT         (0U)
49746 #define GPC_PGC_NOC_MIX_PDNSCR_ISO(x)            (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK)
49747 
49748 #define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK       (0x3F00U)
49749 #define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT      (8U)
49750 #define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW(x)         (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK)
49751 /*! @} */
49752 
49753 /*! @name NOC_MIX_SR - GPC PGC Status Register */
49754 /*! @{ */
49755 
49756 #define GPC_PGC_NOC_MIX_SR_PSR_MASK              (0x1U)
49757 #define GPC_PGC_NOC_MIX_SR_PSR_SHIFT             (0U)
49758 /*! PSR
49759  *  0b0..The target subsystem was not powered down for the previous power-down request.
49760  *  0b1..The target subsystem was powered down for the previous power-down request.
49761  */
49762 #define GPC_PGC_NOC_MIX_SR_PSR(x)                (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PSR_SHIFT)) & GPC_PGC_NOC_MIX_SR_PSR_MASK)
49763 
49764 #define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK      (0x2U)
49765 #define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT     (1U)
49766 /*! L2RETN_FLAG
49767  *  0b0..A53 is not wakeup from L2 retention mode.
49768  *  0b1..A53 is wakeup from L2 retention mode.
49769  */
49770 #define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG(x)        (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK)
49771 
49772 #define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK      (0x4U)
49773 #define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT     (2U)
49774 /*! ALLOFF_FLAG
49775  *  0b0..A53 is not wakeup from ALL_OFF mode.
49776  *  0b1..A53 is wakeup from ALL_OFF mode.
49777  */
49778 #define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG(x)        (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK)
49779 
49780 #define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK  (0x78U)
49781 #define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
49782 /*! PUP_CLK_DIV_SEL
49783  *  0b0000..1
49784  *  0b0001..1/2 count_clk
49785  *  0b0010..1/4 count_clk
49786  *  0b0011..1/8 count_clk
49787  *  0b0100..1/16 count_clk
49788  *  0b0101..1/32 count_clk
49789  *  0b0110..1/64 count_clk
49790  *  0b0111..1/128 count_clk
49791  *  0b1000..1/256 count_clk
49792  *  0b1001..1/512 count_clk
49793  *  0b1010..1/1024 count_clk
49794  *  0b1011..1/2056 count_clk
49795  *  0b1100..1/4096 count_clk
49796  *  0b1101..1/8192 count_clk
49797  *  0b1110..1/16384 count_clk
49798  *  0b1111..1/32768 count_clk
49799  */
49800 #define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL(x)    (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK)
49801 
49802 #define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
49803 #define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
49804 #define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK)
49805 /*! @} */
49806 
49807 /*! @name PU_CTRL - GPC PGC Control Register for PGC PUs */
49808 /*! @{ */
49809 
49810 #define GPC_PGC_PU_CTRL_PCR_MASK                 (0x1U)
49811 #define GPC_PGC_PU_CTRL_PCR_SHIFT                (0U)
49812 /*! PCR
49813  *  0b0..Do not switch off power even if pdn_req is asserted.
49814  *  0b1..Switch off power when pdn_req is asserted.
49815  */
49816 #define GPC_PGC_PU_CTRL_PCR(x)                   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_PCR_SHIFT)) & GPC_PGC_PU_CTRL_PCR_MASK)
49817 
49818 #define GPC_PGC_PU_CTRL_L2RSTDIS_MASK            (0x7EU)
49819 #define GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT           (1U)
49820 #define GPC_PGC_PU_CTRL_L2RSTDIS(x)              (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU_CTRL_L2RSTDIS_MASK)
49821 
49822 #define GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK         (0x3F00U)
49823 #define GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT        (8U)
49824 #define GPC_PGC_PU_CTRL_DFTRAM_TCD1(x)           (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK)
49825 
49826 #define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK     (0x3F0000U)
49827 #define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT    (16U)
49828 #define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR(x)       (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK)
49829 
49830 #define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
49831 #define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
49832 #define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
49833 /*! @} */
49834 
49835 /* The count of GPC_PGC_PU_CTRL */
49836 #define GPC_PGC_PU_CTRL_COUNT                    (20U)
49837 
49838 /*! @name PU_PUPSCR - GPC PGC Up Sequence Control Register */
49839 /*! @{ */
49840 
49841 #define GPC_PGC_PU_PUPSCR_SW_MASK                (0x3FU)
49842 #define GPC_PGC_PU_PUPSCR_SW_SHIFT               (0U)
49843 #define GPC_PGC_PU_PUPSCR_SW(x)                  (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW_SHIFT)) & GPC_PGC_PU_PUPSCR_SW_MASK)
49844 
49845 #define GPC_PGC_PU_PUPSCR_SW2ISO_MASK            (0x7FFF80U)
49846 #define GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT           (7U)
49847 #define GPC_PGC_PU_PUPSCR_SW2ISO(x)              (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU_PUPSCR_SW2ISO_MASK)
49848 /*! @} */
49849 
49850 /* The count of GPC_PGC_PU_PUPSCR */
49851 #define GPC_PGC_PU_PUPSCR_COUNT                  (20U)
49852 
49853 /*! @name PU_PDNSCR - GPC PGC Down Sequence Control Register */
49854 /*! @{ */
49855 
49856 #define GPC_PGC_PU_PDNSCR_ISO_MASK               (0x3FU)
49857 #define GPC_PGC_PU_PDNSCR_ISO_SHIFT              (0U)
49858 #define GPC_PGC_PU_PDNSCR_ISO(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO_MASK)
49859 
49860 #define GPC_PGC_PU_PDNSCR_ISO2SW_MASK            (0x3F00U)
49861 #define GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT           (8U)
49862 #define GPC_PGC_PU_PDNSCR_ISO2SW(x)              (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO2SW_MASK)
49863 /*! @} */
49864 
49865 /* The count of GPC_PGC_PU_PDNSCR */
49866 #define GPC_PGC_PU_PDNSCR_COUNT                  (20U)
49867 
49868 /*! @name PU_SR - GPC PGC Status Register */
49869 /*! @{ */
49870 
49871 #define GPC_PGC_PU_SR_PSR_MASK                   (0x1U)
49872 #define GPC_PGC_PU_SR_PSR_SHIFT                  (0U)
49873 /*! PSR
49874  *  0b0..The target subsystem was not powered down for the previous power-down request.
49875  *  0b1..The target subsystem was powered down for the previous power-down request.
49876  */
49877 #define GPC_PGC_PU_SR_PSR(x)                     (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PSR_SHIFT)) & GPC_PGC_PU_SR_PSR_MASK)
49878 
49879 #define GPC_PGC_PU_SR_L2RETN_FLAG_MASK           (0x2U)
49880 #define GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT          (1U)
49881 /*! L2RETN_FLAG
49882  *  0b0..A53 is not wakeup from L2 retention mode.
49883  *  0b1..A53 is wakeup from L2 retention mode.
49884  */
49885 #define GPC_PGC_PU_SR_L2RETN_FLAG(x)             (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU_SR_L2RETN_FLAG_MASK)
49886 
49887 #define GPC_PGC_PU_SR_ALLOFF_FLAG_MASK           (0x4U)
49888 #define GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT          (2U)
49889 /*! ALLOFF_FLAG
49890  *  0b0..A53 is not wakeup from ALL_OFF mode.
49891  *  0b1..A53 is wakeup from ALL_OFF mode.
49892  */
49893 #define GPC_PGC_PU_SR_ALLOFF_FLAG(x)             (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU_SR_ALLOFF_FLAG_MASK)
49894 
49895 #define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK       (0x78U)
49896 #define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT      (3U)
49897 /*! PUP_CLK_DIV_SEL
49898  *  0b0000..1
49899  *  0b0001..1/2 count_clk
49900  *  0b0010..1/4 count_clk
49901  *  0b0011..1/8 count_clk
49902  *  0b0100..1/16 count_clk
49903  *  0b0101..1/32 count_clk
49904  *  0b0110..1/64 count_clk
49905  *  0b0111..1/128 count_clk
49906  *  0b1000..1/256 count_clk
49907  *  0b1001..1/512 count_clk
49908  *  0b1010..1/1024 count_clk
49909  *  0b1011..1/2056 count_clk
49910  *  0b1100..1/4096 count_clk
49911  *  0b1101..1/8192 count_clk
49912  *  0b1110..1/16384 count_clk
49913  *  0b1111..1/32768 count_clk
49914  */
49915 #define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK)
49916 
49917 #define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
49918 #define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
49919 #define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT(x)   (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
49920 /*! @} */
49921 
49922 /* The count of GPC_PGC_PU_SR */
49923 #define GPC_PGC_PU_SR_COUNT                      (20U)
49924 
49925 
49926 /*!
49927  * @}
49928  */ /* end of group GPC_PGC_Register_Masks */
49929 
49930 
49931 /* GPC_PGC - Peripheral instance base addresses */
49932 /** Peripheral GPC_PGC base address */
49933 #define GPC_PGC_BASE                             (0x303A0000u)
49934 /** Peripheral GPC_PGC base pointer */
49935 #define GPC_PGC                                  ((GPC_PGC_Type *)GPC_PGC_BASE)
49936 /** Array initializer of GPC_PGC peripheral base addresses */
49937 #define GPC_PGC_BASE_ADDRS                       { GPC_PGC_BASE }
49938 /** Array initializer of GPC_PGC peripheral base pointers */
49939 #define GPC_PGC_BASE_PTRS                        { GPC_PGC }
49940 
49941 /*!
49942  * @}
49943  */ /* end of group GPC_PGC_Peripheral_Access_Layer */
49944 
49945 
49946 /* ----------------------------------------------------------------------------
49947    -- GPIO Peripheral Access Layer
49948    ---------------------------------------------------------------------------- */
49949 
49950 /*!
49951  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
49952  * @{
49953  */
49954 
49955 /** GPIO - Register Layout Typedef */
49956 typedef struct {
49957   __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
49958   __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
49959   __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
49960   __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
49961   __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
49962   __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
49963   __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
49964   __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
49965 } GPIO_Type;
49966 
49967 /* ----------------------------------------------------------------------------
49968    -- GPIO Register Masks
49969    ---------------------------------------------------------------------------- */
49970 
49971 /*!
49972  * @addtogroup GPIO_Register_Masks GPIO Register Masks
49973  * @{
49974  */
49975 
49976 /*! @name DR - GPIO data register */
49977 /*! @{ */
49978 
49979 #define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
49980 #define GPIO_DR_DR_SHIFT                         (0U)
49981 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
49982 /*! @} */
49983 
49984 /*! @name GDIR - GPIO direction register */
49985 /*! @{ */
49986 
49987 #define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
49988 #define GPIO_GDIR_GDIR_SHIFT                     (0U)
49989 /*! GDIR
49990  *  0b00000000000000000000000000000000..GPIO is configured as input.
49991  *  0b00000000000000000000000000000001..GPIO is configured as output.
49992  */
49993 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
49994 /*! @} */
49995 
49996 /*! @name PSR - GPIO pad status register */
49997 /*! @{ */
49998 
49999 #define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
50000 #define GPIO_PSR_PSR_SHIFT                       (0U)
50001 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
50002 /*! @} */
50003 
50004 /*! @name ICR1 - GPIO interrupt configuration register1 */
50005 /*! @{ */
50006 
50007 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
50008 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
50009 /*! ICR0
50010  *  0b00..Interrupt n is low-level sensitive.
50011  *  0b01..Interrupt n is high-level sensitive.
50012  *  0b10..Interrupt n is rising-edge sensitive.
50013  *  0b11..Interrupt n is falling-edge sensitive.
50014  */
50015 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
50016 
50017 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
50018 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
50019 /*! ICR1
50020  *  0b00..Interrupt n is low-level sensitive.
50021  *  0b01..Interrupt n is high-level sensitive.
50022  *  0b10..Interrupt n is rising-edge sensitive.
50023  *  0b11..Interrupt n is falling-edge sensitive.
50024  */
50025 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
50026 
50027 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
50028 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
50029 /*! ICR2
50030  *  0b00..Interrupt n is low-level sensitive.
50031  *  0b01..Interrupt n is high-level sensitive.
50032  *  0b10..Interrupt n is rising-edge sensitive.
50033  *  0b11..Interrupt n is falling-edge sensitive.
50034  */
50035 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
50036 
50037 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
50038 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
50039 /*! ICR3
50040  *  0b00..Interrupt n is low-level sensitive.
50041  *  0b01..Interrupt n is high-level sensitive.
50042  *  0b10..Interrupt n is rising-edge sensitive.
50043  *  0b11..Interrupt n is falling-edge sensitive.
50044  */
50045 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
50046 
50047 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
50048 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
50049 /*! ICR4
50050  *  0b00..Interrupt n is low-level sensitive.
50051  *  0b01..Interrupt n is high-level sensitive.
50052  *  0b10..Interrupt n is rising-edge sensitive.
50053  *  0b11..Interrupt n is falling-edge sensitive.
50054  */
50055 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
50056 
50057 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
50058 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
50059 /*! ICR5
50060  *  0b00..Interrupt n is low-level sensitive.
50061  *  0b01..Interrupt n is high-level sensitive.
50062  *  0b10..Interrupt n is rising-edge sensitive.
50063  *  0b11..Interrupt n is falling-edge sensitive.
50064  */
50065 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
50066 
50067 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
50068 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
50069 /*! ICR6
50070  *  0b00..Interrupt n is low-level sensitive.
50071  *  0b01..Interrupt n is high-level sensitive.
50072  *  0b10..Interrupt n is rising-edge sensitive.
50073  *  0b11..Interrupt n is falling-edge sensitive.
50074  */
50075 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
50076 
50077 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
50078 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
50079 /*! ICR7
50080  *  0b00..Interrupt n is low-level sensitive.
50081  *  0b01..Interrupt n is high-level sensitive.
50082  *  0b10..Interrupt n is rising-edge sensitive.
50083  *  0b11..Interrupt n is falling-edge sensitive.
50084  */
50085 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
50086 
50087 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
50088 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
50089 /*! ICR8
50090  *  0b00..Interrupt n is low-level sensitive.
50091  *  0b01..Interrupt n is high-level sensitive.
50092  *  0b10..Interrupt n is rising-edge sensitive.
50093  *  0b11..Interrupt n is falling-edge sensitive.
50094  */
50095 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
50096 
50097 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
50098 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
50099 /*! ICR9
50100  *  0b00..Interrupt n is low-level sensitive.
50101  *  0b01..Interrupt n is high-level sensitive.
50102  *  0b10..Interrupt n is rising-edge sensitive.
50103  *  0b11..Interrupt n is falling-edge sensitive.
50104  */
50105 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
50106 
50107 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
50108 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
50109 /*! ICR10
50110  *  0b00..Interrupt n is low-level sensitive.
50111  *  0b01..Interrupt n is high-level sensitive.
50112  *  0b10..Interrupt n is rising-edge sensitive.
50113  *  0b11..Interrupt n is falling-edge sensitive.
50114  */
50115 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
50116 
50117 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
50118 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
50119 /*! ICR11
50120  *  0b00..Interrupt n is low-level sensitive.
50121  *  0b01..Interrupt n is high-level sensitive.
50122  *  0b10..Interrupt n is rising-edge sensitive.
50123  *  0b11..Interrupt n is falling-edge sensitive.
50124  */
50125 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
50126 
50127 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
50128 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
50129 /*! ICR12
50130  *  0b00..Interrupt n is low-level sensitive.
50131  *  0b01..Interrupt n is high-level sensitive.
50132  *  0b10..Interrupt n is rising-edge sensitive.
50133  *  0b11..Interrupt n is falling-edge sensitive.
50134  */
50135 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
50136 
50137 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
50138 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
50139 /*! ICR13
50140  *  0b00..Interrupt n is low-level sensitive.
50141  *  0b01..Interrupt n is high-level sensitive.
50142  *  0b10..Interrupt n is rising-edge sensitive.
50143  *  0b11..Interrupt n is falling-edge sensitive.
50144  */
50145 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
50146 
50147 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
50148 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
50149 /*! ICR14
50150  *  0b00..Interrupt n is low-level sensitive.
50151  *  0b01..Interrupt n is high-level sensitive.
50152  *  0b10..Interrupt n is rising-edge sensitive.
50153  *  0b11..Interrupt n is falling-edge sensitive.
50154  */
50155 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
50156 
50157 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
50158 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
50159 /*! ICR15
50160  *  0b00..Interrupt n is low-level sensitive.
50161  *  0b01..Interrupt n is high-level sensitive.
50162  *  0b10..Interrupt n is rising-edge sensitive.
50163  *  0b11..Interrupt n is falling-edge sensitive.
50164  */
50165 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
50166 /*! @} */
50167 
50168 /*! @name ICR2 - GPIO interrupt configuration register2 */
50169 /*! @{ */
50170 
50171 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
50172 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
50173 /*! ICR16
50174  *  0b00..Interrupt n is low-level sensitive.
50175  *  0b01..Interrupt n is high-level sensitive.
50176  *  0b10..Interrupt n is rising-edge sensitive.
50177  *  0b11..Interrupt n is falling-edge sensitive.
50178  */
50179 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
50180 
50181 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
50182 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
50183 /*! ICR17
50184  *  0b00..Interrupt n is low-level sensitive.
50185  *  0b01..Interrupt n is high-level sensitive.
50186  *  0b10..Interrupt n is rising-edge sensitive.
50187  *  0b11..Interrupt n is falling-edge sensitive.
50188  */
50189 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
50190 
50191 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
50192 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
50193 /*! ICR18
50194  *  0b00..Interrupt n is low-level sensitive.
50195  *  0b01..Interrupt n is high-level sensitive.
50196  *  0b10..Interrupt n is rising-edge sensitive.
50197  *  0b11..Interrupt n is falling-edge sensitive.
50198  */
50199 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
50200 
50201 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
50202 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
50203 /*! ICR19
50204  *  0b00..Interrupt n is low-level sensitive.
50205  *  0b01..Interrupt n is high-level sensitive.
50206  *  0b10..Interrupt n is rising-edge sensitive.
50207  *  0b11..Interrupt n is falling-edge sensitive.
50208  */
50209 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
50210 
50211 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
50212 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
50213 /*! ICR20
50214  *  0b00..Interrupt n is low-level sensitive.
50215  *  0b01..Interrupt n is high-level sensitive.
50216  *  0b10..Interrupt n is rising-edge sensitive.
50217  *  0b11..Interrupt n is falling-edge sensitive.
50218  */
50219 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
50220 
50221 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
50222 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
50223 /*! ICR21
50224  *  0b00..Interrupt n is low-level sensitive.
50225  *  0b01..Interrupt n is high-level sensitive.
50226  *  0b10..Interrupt n is rising-edge sensitive.
50227  *  0b11..Interrupt n is falling-edge sensitive.
50228  */
50229 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
50230 
50231 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
50232 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
50233 /*! ICR22
50234  *  0b00..Interrupt n is low-level sensitive.
50235  *  0b01..Interrupt n is high-level sensitive.
50236  *  0b10..Interrupt n is rising-edge sensitive.
50237  *  0b11..Interrupt n is falling-edge sensitive.
50238  */
50239 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
50240 
50241 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
50242 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
50243 /*! ICR23
50244  *  0b00..Interrupt n is low-level sensitive.
50245  *  0b01..Interrupt n is high-level sensitive.
50246  *  0b10..Interrupt n is rising-edge sensitive.
50247  *  0b11..Interrupt n is falling-edge sensitive.
50248  */
50249 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
50250 
50251 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
50252 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
50253 /*! ICR24
50254  *  0b00..Interrupt n is low-level sensitive.
50255  *  0b01..Interrupt n is high-level sensitive.
50256  *  0b10..Interrupt n is rising-edge sensitive.
50257  *  0b11..Interrupt n is falling-edge sensitive.
50258  */
50259 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
50260 
50261 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
50262 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
50263 /*! ICR25
50264  *  0b00..Interrupt n is low-level sensitive.
50265  *  0b01..Interrupt n is high-level sensitive.
50266  *  0b10..Interrupt n is rising-edge sensitive.
50267  *  0b11..Interrupt n is falling-edge sensitive.
50268  */
50269 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
50270 
50271 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
50272 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
50273 /*! ICR26
50274  *  0b00..Interrupt n is low-level sensitive.
50275  *  0b01..Interrupt n is high-level sensitive.
50276  *  0b10..Interrupt n is rising-edge sensitive.
50277  *  0b11..Interrupt n is falling-edge sensitive.
50278  */
50279 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
50280 
50281 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
50282 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
50283 /*! ICR27
50284  *  0b00..Interrupt n is low-level sensitive.
50285  *  0b01..Interrupt n is high-level sensitive.
50286  *  0b10..Interrupt n is rising-edge sensitive.
50287  *  0b11..Interrupt n is falling-edge sensitive.
50288  */
50289 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
50290 
50291 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
50292 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
50293 /*! ICR28
50294  *  0b00..Interrupt n is low-level sensitive.
50295  *  0b01..Interrupt n is high-level sensitive.
50296  *  0b10..Interrupt n is rising-edge sensitive.
50297  *  0b11..Interrupt n is falling-edge sensitive.
50298  */
50299 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
50300 
50301 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
50302 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
50303 /*! ICR29
50304  *  0b00..Interrupt n is low-level sensitive.
50305  *  0b01..Interrupt n is high-level sensitive.
50306  *  0b10..Interrupt n is rising-edge sensitive.
50307  *  0b11..Interrupt n is falling-edge sensitive.
50308  */
50309 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
50310 
50311 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
50312 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
50313 /*! ICR30
50314  *  0b00..Interrupt n is low-level sensitive.
50315  *  0b01..Interrupt n is high-level sensitive.
50316  *  0b10..Interrupt n is rising-edge sensitive.
50317  *  0b11..Interrupt n is falling-edge sensitive.
50318  */
50319 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
50320 
50321 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
50322 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
50323 /*! ICR31
50324  *  0b00..Interrupt n is low-level sensitive.
50325  *  0b01..Interrupt n is high-level sensitive.
50326  *  0b10..Interrupt n is rising-edge sensitive.
50327  *  0b11..Interrupt n is falling-edge sensitive.
50328  */
50329 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
50330 /*! @} */
50331 
50332 /*! @name IMR - GPIO interrupt mask register */
50333 /*! @{ */
50334 
50335 #define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
50336 #define GPIO_IMR_IMR_SHIFT                       (0U)
50337 /*! IMR
50338  *  0b00000000000000000000000000000000..Interrupt n is disabled.
50339  *  0b00000000000000000000000000000001..Interrupt n is enabled.
50340  */
50341 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
50342 /*! @} */
50343 
50344 /*! @name ISR - GPIO interrupt status register */
50345 /*! @{ */
50346 
50347 #define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
50348 #define GPIO_ISR_ISR_SHIFT                       (0U)
50349 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
50350 /*! @} */
50351 
50352 /*! @name EDGE_SEL - GPIO edge select register */
50353 /*! @{ */
50354 
50355 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
50356 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
50357 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
50358 /*! @} */
50359 
50360 
50361 /*!
50362  * @}
50363  */ /* end of group GPIO_Register_Masks */
50364 
50365 
50366 /* GPIO - Peripheral instance base addresses */
50367 /** Peripheral GPIO1 base address */
50368 #define GPIO1_BASE                               (0x30200000u)
50369 /** Peripheral GPIO1 base pointer */
50370 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
50371 /** Peripheral GPIO2 base address */
50372 #define GPIO2_BASE                               (0x30210000u)
50373 /** Peripheral GPIO2 base pointer */
50374 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
50375 /** Peripheral GPIO3 base address */
50376 #define GPIO3_BASE                               (0x30220000u)
50377 /** Peripheral GPIO3 base pointer */
50378 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
50379 /** Peripheral GPIO4 base address */
50380 #define GPIO4_BASE                               (0x30230000u)
50381 /** Peripheral GPIO4 base pointer */
50382 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
50383 /** Peripheral GPIO5 base address */
50384 #define GPIO5_BASE                               (0x30240000u)
50385 /** Peripheral GPIO5 base pointer */
50386 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
50387 /** Array initializer of GPIO peripheral base addresses */
50388 #define GPIO_BASE_ADDRS                          { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
50389 /** Array initializer of GPIO peripheral base pointers */
50390 #define GPIO_BASE_PTRS                           { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
50391 /** Interrupt vectors for the GPIO peripheral type */
50392 #define GPIO_IRQS                                { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
50393 #define GPIO_COMBINED_LOW_IRQS                   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
50394 #define GPIO_COMBINED_HIGH_IRQS                  { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
50395 
50396 /*!
50397  * @}
50398  */ /* end of group GPIO_Peripheral_Access_Layer */
50399 
50400 
50401 /* ----------------------------------------------------------------------------
50402    -- GPMI Peripheral Access Layer
50403    ---------------------------------------------------------------------------- */
50404 
50405 /*!
50406  * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
50407  * @{
50408  */
50409 
50410 /** GPMI - Register Layout Typedef */
50411 typedef struct {
50412   __IO uint32_t CTRL0;                             /**< GPMI Control Register 0 Description, offset: 0x0 */
50413   __IO uint32_t CTRL0_SET;                         /**< GPMI Control Register 0 Description, offset: 0x4 */
50414   __IO uint32_t CTRL0_CLR;                         /**< GPMI Control Register 0 Description, offset: 0x8 */
50415   __IO uint32_t CTRL0_TOG;                         /**< GPMI Control Register 0 Description, offset: 0xC */
50416   __IO uint32_t COMPARE;                           /**< GPMI Compare Register Description, offset: 0x10 */
50417        uint8_t RESERVED_0[12];
50418   __IO uint32_t ECCCTRL;                           /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
50419   __IO uint32_t ECCCTRL_SET;                       /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
50420   __IO uint32_t ECCCTRL_CLR;                       /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
50421   __IO uint32_t ECCCTRL_TOG;                       /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
50422   __IO uint32_t ECCCOUNT;                          /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
50423        uint8_t RESERVED_1[12];
50424   __IO uint32_t PAYLOAD;                           /**< GPMI Payload Address Register Description, offset: 0x40 */
50425        uint8_t RESERVED_2[12];
50426   __IO uint32_t AUXILIARY;                         /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
50427        uint8_t RESERVED_3[12];
50428   __IO uint32_t CTRL1;                             /**< GPMI Control Register 1 Description, offset: 0x60 */
50429   __IO uint32_t CTRL1_SET;                         /**< GPMI Control Register 1 Description, offset: 0x64 */
50430   __IO uint32_t CTRL1_CLR;                         /**< GPMI Control Register 1 Description, offset: 0x68 */
50431   __IO uint32_t CTRL1_TOG;                         /**< GPMI Control Register 1 Description, offset: 0x6C */
50432   __IO uint32_t TIMING0;                           /**< GPMI Timing Register 0 Description, offset: 0x70 */
50433        uint8_t RESERVED_4[12];
50434   __IO uint32_t TIMING1;                           /**< GPMI Timing Register 1 Description, offset: 0x80 */
50435        uint8_t RESERVED_5[12];
50436   __IO uint32_t TIMING2;                           /**< GPMI Timing Register 2 Description, offset: 0x90 */
50437        uint8_t RESERVED_6[12];
50438   __IO uint32_t DATA;                              /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
50439        uint8_t RESERVED_7[12];
50440   __I  uint32_t STAT;                              /**< GPMI Status Register Description, offset: 0xB0 */
50441        uint8_t RESERVED_8[12];
50442   __I  uint32_t DEBUGr;                            /**< GPMI Debug Information Register Description, offset: 0xC0, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
50443        uint8_t RESERVED_9[12];
50444   __I  uint32_t VERSION;                           /**< GPMI Version Register Description, offset: 0xD0 */
50445        uint8_t RESERVED_10[12];
50446   __IO uint32_t DEBUG2;                            /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
50447        uint8_t RESERVED_11[12];
50448   __I  uint32_t DEBUG3;                            /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
50449        uint8_t RESERVED_12[12];
50450   __IO uint32_t READ_DDR_DLL_CTRL;                 /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
50451        uint8_t RESERVED_13[12];
50452   __IO uint32_t WRITE_DDR_DLL_CTRL;                /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
50453        uint8_t RESERVED_14[12];
50454   __I  uint32_t READ_DDR_DLL_STS;                  /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
50455        uint8_t RESERVED_15[12];
50456   __I  uint32_t WRITE_DDR_DLL_STS;                 /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
50457 } GPMI_Type;
50458 
50459 /* ----------------------------------------------------------------------------
50460    -- GPMI Register Masks
50461    ---------------------------------------------------------------------------- */
50462 
50463 /*!
50464  * @addtogroup GPMI_Register_Masks GPMI Register Masks
50465  * @{
50466  */
50467 
50468 /*! @name CTRL0 - GPMI Control Register 0 Description */
50469 /*! @{ */
50470 
50471 #define GPMI_CTRL0_XFER_COUNT_MASK               (0xFFFFU)
50472 #define GPMI_CTRL0_XFER_COUNT_SHIFT              (0U)
50473 #define GPMI_CTRL0_XFER_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
50474 
50475 #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK        (0x10000U)
50476 #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT       (16U)
50477 /*! ADDRESS_INCREMENT
50478  *  0b0..Address does not increment.
50479  *  0b1..Increment address.
50480  */
50481 #define GPMI_CTRL0_ADDRESS_INCREMENT(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
50482 
50483 #define GPMI_CTRL0_ADDRESS_MASK                  (0xE0000U)
50484 #define GPMI_CTRL0_ADDRESS_SHIFT                 (17U)
50485 #define GPMI_CTRL0_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
50486 
50487 #define GPMI_CTRL0_CS_MASK                       (0x700000U)
50488 #define GPMI_CTRL0_CS_SHIFT                      (20U)
50489 #define GPMI_CTRL0_CS(x)                         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
50490 
50491 #define GPMI_CTRL0_WORD_LENGTH_MASK              (0x800000U)
50492 #define GPMI_CTRL0_WORD_LENGTH_SHIFT             (23U)
50493 /*! WORD_LENGTH
50494  *  0b0..Reserved.
50495  *  0b1..8-bit Data Bus mode.
50496  */
50497 #define GPMI_CTRL0_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
50498 
50499 #define GPMI_CTRL0_COMMAND_MODE_MASK             (0x3000000U)
50500 #define GPMI_CTRL0_COMMAND_MODE_SHIFT            (24U)
50501 /*! COMMAND_MODE
50502  *  0b00..Write mode.
50503  *  0b01..Read Mode.
50504  *  0b10..Read and Compare Mode (setting sense flop).
50505  *  0b11..Wait for Ready.
50506  */
50507 #define GPMI_CTRL0_COMMAND_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
50508 
50509 #define GPMI_CTRL0_UDMA_MASK                     (0x4000000U)
50510 #define GPMI_CTRL0_UDMA_SHIFT                    (26U)
50511 /*! UDMA
50512  *  0b0..Use ATA-PIO mode on the external bus.
50513  *  0b1..Use ATA-Ultra DMA mode on the external bus.
50514  */
50515 #define GPMI_CTRL0_UDMA(x)                       (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
50516 
50517 #define GPMI_CTRL0_LOCK_CS_MASK                  (0x8000000U)
50518 #define GPMI_CTRL0_LOCK_CS_SHIFT                 (27U)
50519 #define GPMI_CTRL0_LOCK_CS(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
50520 
50521 #define GPMI_CTRL0_DEV_IRQ_EN_MASK               (0x10000000U)
50522 #define GPMI_CTRL0_DEV_IRQ_EN_SHIFT              (28U)
50523 #define GPMI_CTRL0_DEV_IRQ_EN(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK)
50524 
50525 #define GPMI_CTRL0_RUN_MASK                      (0x20000000U)
50526 #define GPMI_CTRL0_RUN_SHIFT                     (29U)
50527 #define GPMI_CTRL0_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
50528 
50529 #define GPMI_CTRL0_CLKGATE_MASK                  (0x40000000U)
50530 #define GPMI_CTRL0_CLKGATE_SHIFT                 (30U)
50531 #define GPMI_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
50532 
50533 #define GPMI_CTRL0_SFTRST_MASK                   (0x80000000U)
50534 #define GPMI_CTRL0_SFTRST_SHIFT                  (31U)
50535 #define GPMI_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
50536 /*! @} */
50537 
50538 /*! @name CTRL0_SET - GPMI Control Register 0 Description */
50539 /*! @{ */
50540 
50541 #define GPMI_CTRL0_SET_XFER_COUNT_MASK           (0xFFFFU)
50542 #define GPMI_CTRL0_SET_XFER_COUNT_SHIFT          (0U)
50543 #define GPMI_CTRL0_SET_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK)
50544 
50545 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK    (0x10000U)
50546 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT   (16U)
50547 /*! ADDRESS_INCREMENT
50548  *  0b0..Address does not increment.
50549  *  0b1..Increment address.
50550  */
50551 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK)
50552 
50553 #define GPMI_CTRL0_SET_ADDRESS_MASK              (0xE0000U)
50554 #define GPMI_CTRL0_SET_ADDRESS_SHIFT             (17U)
50555 #define GPMI_CTRL0_SET_ADDRESS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK)
50556 
50557 #define GPMI_CTRL0_SET_CS_MASK                   (0x700000U)
50558 #define GPMI_CTRL0_SET_CS_SHIFT                  (20U)
50559 #define GPMI_CTRL0_SET_CS(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK)
50560 
50561 #define GPMI_CTRL0_SET_WORD_LENGTH_MASK          (0x800000U)
50562 #define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT         (23U)
50563 /*! WORD_LENGTH
50564  *  0b0..Reserved.
50565  *  0b1..8-bit Data Bus mode.
50566  */
50567 #define GPMI_CTRL0_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK)
50568 
50569 #define GPMI_CTRL0_SET_COMMAND_MODE_MASK         (0x3000000U)
50570 #define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT        (24U)
50571 /*! COMMAND_MODE
50572  *  0b00..Write mode.
50573  *  0b01..Read Mode.
50574  *  0b10..Read and Compare Mode (setting sense flop).
50575  *  0b11..Wait for Ready.
50576  */
50577 #define GPMI_CTRL0_SET_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK)
50578 
50579 #define GPMI_CTRL0_SET_UDMA_MASK                 (0x4000000U)
50580 #define GPMI_CTRL0_SET_UDMA_SHIFT                (26U)
50581 /*! UDMA
50582  *  0b0..Use ATA-PIO mode on the external bus.
50583  *  0b1..Use ATA-Ultra DMA mode on the external bus.
50584  */
50585 #define GPMI_CTRL0_SET_UDMA(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK)
50586 
50587 #define GPMI_CTRL0_SET_LOCK_CS_MASK              (0x8000000U)
50588 #define GPMI_CTRL0_SET_LOCK_CS_SHIFT             (27U)
50589 #define GPMI_CTRL0_SET_LOCK_CS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK)
50590 
50591 #define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK           (0x10000000U)
50592 #define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT          (28U)
50593 #define GPMI_CTRL0_SET_DEV_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK)
50594 
50595 #define GPMI_CTRL0_SET_RUN_MASK                  (0x20000000U)
50596 #define GPMI_CTRL0_SET_RUN_SHIFT                 (29U)
50597 #define GPMI_CTRL0_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK)
50598 
50599 #define GPMI_CTRL0_SET_CLKGATE_MASK              (0x40000000U)
50600 #define GPMI_CTRL0_SET_CLKGATE_SHIFT             (30U)
50601 #define GPMI_CTRL0_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK)
50602 
50603 #define GPMI_CTRL0_SET_SFTRST_MASK               (0x80000000U)
50604 #define GPMI_CTRL0_SET_SFTRST_SHIFT              (31U)
50605 #define GPMI_CTRL0_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK)
50606 /*! @} */
50607 
50608 /*! @name CTRL0_CLR - GPMI Control Register 0 Description */
50609 /*! @{ */
50610 
50611 #define GPMI_CTRL0_CLR_XFER_COUNT_MASK           (0xFFFFU)
50612 #define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT          (0U)
50613 #define GPMI_CTRL0_CLR_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK)
50614 
50615 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK    (0x10000U)
50616 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT   (16U)
50617 /*! ADDRESS_INCREMENT
50618  *  0b0..Address does not increment.
50619  *  0b1..Increment address.
50620  */
50621 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK)
50622 
50623 #define GPMI_CTRL0_CLR_ADDRESS_MASK              (0xE0000U)
50624 #define GPMI_CTRL0_CLR_ADDRESS_SHIFT             (17U)
50625 #define GPMI_CTRL0_CLR_ADDRESS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK)
50626 
50627 #define GPMI_CTRL0_CLR_CS_MASK                   (0x700000U)
50628 #define GPMI_CTRL0_CLR_CS_SHIFT                  (20U)
50629 #define GPMI_CTRL0_CLR_CS(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK)
50630 
50631 #define GPMI_CTRL0_CLR_WORD_LENGTH_MASK          (0x800000U)
50632 #define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT         (23U)
50633 /*! WORD_LENGTH
50634  *  0b0..Reserved.
50635  *  0b1..8-bit Data Bus mode.
50636  */
50637 #define GPMI_CTRL0_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK)
50638 
50639 #define GPMI_CTRL0_CLR_COMMAND_MODE_MASK         (0x3000000U)
50640 #define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT        (24U)
50641 /*! COMMAND_MODE
50642  *  0b00..Write mode.
50643  *  0b01..Read Mode.
50644  *  0b10..Read and Compare Mode (setting sense flop).
50645  *  0b11..Wait for Ready.
50646  */
50647 #define GPMI_CTRL0_CLR_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK)
50648 
50649 #define GPMI_CTRL0_CLR_UDMA_MASK                 (0x4000000U)
50650 #define GPMI_CTRL0_CLR_UDMA_SHIFT                (26U)
50651 /*! UDMA
50652  *  0b0..Use ATA-PIO mode on the external bus.
50653  *  0b1..Use ATA-Ultra DMA mode on the external bus.
50654  */
50655 #define GPMI_CTRL0_CLR_UDMA(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK)
50656 
50657 #define GPMI_CTRL0_CLR_LOCK_CS_MASK              (0x8000000U)
50658 #define GPMI_CTRL0_CLR_LOCK_CS_SHIFT             (27U)
50659 #define GPMI_CTRL0_CLR_LOCK_CS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK)
50660 
50661 #define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK           (0x10000000U)
50662 #define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT          (28U)
50663 #define GPMI_CTRL0_CLR_DEV_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK)
50664 
50665 #define GPMI_CTRL0_CLR_RUN_MASK                  (0x20000000U)
50666 #define GPMI_CTRL0_CLR_RUN_SHIFT                 (29U)
50667 #define GPMI_CTRL0_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK)
50668 
50669 #define GPMI_CTRL0_CLR_CLKGATE_MASK              (0x40000000U)
50670 #define GPMI_CTRL0_CLR_CLKGATE_SHIFT             (30U)
50671 #define GPMI_CTRL0_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK)
50672 
50673 #define GPMI_CTRL0_CLR_SFTRST_MASK               (0x80000000U)
50674 #define GPMI_CTRL0_CLR_SFTRST_SHIFT              (31U)
50675 #define GPMI_CTRL0_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK)
50676 /*! @} */
50677 
50678 /*! @name CTRL0_TOG - GPMI Control Register 0 Description */
50679 /*! @{ */
50680 
50681 #define GPMI_CTRL0_TOG_XFER_COUNT_MASK           (0xFFFFU)
50682 #define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT          (0U)
50683 #define GPMI_CTRL0_TOG_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK)
50684 
50685 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK    (0x10000U)
50686 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT   (16U)
50687 /*! ADDRESS_INCREMENT
50688  *  0b0..Address does not increment.
50689  *  0b1..Increment address.
50690  */
50691 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK)
50692 
50693 #define GPMI_CTRL0_TOG_ADDRESS_MASK              (0xE0000U)
50694 #define GPMI_CTRL0_TOG_ADDRESS_SHIFT             (17U)
50695 #define GPMI_CTRL0_TOG_ADDRESS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK)
50696 
50697 #define GPMI_CTRL0_TOG_CS_MASK                   (0x700000U)
50698 #define GPMI_CTRL0_TOG_CS_SHIFT                  (20U)
50699 #define GPMI_CTRL0_TOG_CS(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK)
50700 
50701 #define GPMI_CTRL0_TOG_WORD_LENGTH_MASK          (0x800000U)
50702 #define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT         (23U)
50703 /*! WORD_LENGTH
50704  *  0b0..Reserved.
50705  *  0b1..8-bit Data Bus mode.
50706  */
50707 #define GPMI_CTRL0_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK)
50708 
50709 #define GPMI_CTRL0_TOG_COMMAND_MODE_MASK         (0x3000000U)
50710 #define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT        (24U)
50711 /*! COMMAND_MODE
50712  *  0b00..Write mode.
50713  *  0b01..Read Mode.
50714  *  0b10..Read and Compare Mode (setting sense flop).
50715  *  0b11..Wait for Ready.
50716  */
50717 #define GPMI_CTRL0_TOG_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK)
50718 
50719 #define GPMI_CTRL0_TOG_UDMA_MASK                 (0x4000000U)
50720 #define GPMI_CTRL0_TOG_UDMA_SHIFT                (26U)
50721 /*! UDMA
50722  *  0b0..Use ATA-PIO mode on the external bus.
50723  *  0b1..Use ATA-Ultra DMA mode on the external bus.
50724  */
50725 #define GPMI_CTRL0_TOG_UDMA(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK)
50726 
50727 #define GPMI_CTRL0_TOG_LOCK_CS_MASK              (0x8000000U)
50728 #define GPMI_CTRL0_TOG_LOCK_CS_SHIFT             (27U)
50729 #define GPMI_CTRL0_TOG_LOCK_CS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK)
50730 
50731 #define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK           (0x10000000U)
50732 #define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT          (28U)
50733 #define GPMI_CTRL0_TOG_DEV_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK)
50734 
50735 #define GPMI_CTRL0_TOG_RUN_MASK                  (0x20000000U)
50736 #define GPMI_CTRL0_TOG_RUN_SHIFT                 (29U)
50737 #define GPMI_CTRL0_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK)
50738 
50739 #define GPMI_CTRL0_TOG_CLKGATE_MASK              (0x40000000U)
50740 #define GPMI_CTRL0_TOG_CLKGATE_SHIFT             (30U)
50741 #define GPMI_CTRL0_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK)
50742 
50743 #define GPMI_CTRL0_TOG_SFTRST_MASK               (0x80000000U)
50744 #define GPMI_CTRL0_TOG_SFTRST_SHIFT              (31U)
50745 #define GPMI_CTRL0_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK)
50746 /*! @} */
50747 
50748 /*! @name COMPARE - GPMI Compare Register Description */
50749 /*! @{ */
50750 
50751 #define GPMI_COMPARE_REFERENCE_MASK              (0xFFFFU)
50752 #define GPMI_COMPARE_REFERENCE_SHIFT             (0U)
50753 #define GPMI_COMPARE_REFERENCE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
50754 
50755 #define GPMI_COMPARE_MASK_MASK                   (0xFFFF0000U)
50756 #define GPMI_COMPARE_MASK_SHIFT                  (16U)
50757 #define GPMI_COMPARE_MASK(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
50758 /*! @} */
50759 
50760 /*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
50761 /*! @{ */
50762 
50763 #define GPMI_ECCCTRL_BUFFER_MASK_MASK            (0x1FFU)
50764 #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT           (0U)
50765 #define GPMI_ECCCTRL_BUFFER_MASK(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
50766 
50767 #define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK        (0x600U)
50768 #define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT       (9U)
50769 /*! RANDOMIZER_TYPE
50770  *  0b00..Type 0
50771  *  0b01..Type 1
50772  */
50773 #define GPMI_ECCCTRL_RANDOMIZER_TYPE(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK)
50774 
50775 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK      (0x800U)
50776 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT     (11U)
50777 /*! RANDOMIZER_ENABLE
50778  *  0b0..disable
50779  *  0b1..enable
50780  */
50781 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK)
50782 
50783 #define GPMI_ECCCTRL_ENABLE_ECC_MASK             (0x1000U)
50784 #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT            (12U)
50785 #define GPMI_ECCCTRL_ENABLE_ECC(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
50786 
50787 #define GPMI_ECCCTRL_ECC_CMD_MASK                (0x6000U)
50788 #define GPMI_ECCCTRL_ECC_CMD_SHIFT               (13U)
50789 #define GPMI_ECCCTRL_ECC_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
50790 
50791 #define GPMI_ECCCTRL_RSVD2_MASK                  (0x8000U)
50792 #define GPMI_ECCCTRL_RSVD2_SHIFT                 (15U)
50793 #define GPMI_ECCCTRL_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
50794 
50795 #define GPMI_ECCCTRL_HANDLE_MASK                 (0xFFFF0000U)
50796 #define GPMI_ECCCTRL_HANDLE_SHIFT                (16U)
50797 #define GPMI_ECCCTRL_HANDLE(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
50798 /*! @} */
50799 
50800 /*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */
50801 /*! @{ */
50802 
50803 #define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK        (0x1FFU)
50804 #define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT       (0U)
50805 #define GPMI_ECCCTRL_SET_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK)
50806 
50807 #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK    (0x600U)
50808 #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT   (9U)
50809 /*! RANDOMIZER_TYPE
50810  *  0b00..Type 0
50811  *  0b01..Type 1
50812  */
50813 #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK)
50814 
50815 #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK  (0x800U)
50816 #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U)
50817 /*! RANDOMIZER_ENABLE
50818  *  0b0..disable
50819  *  0b1..enable
50820  */
50821 #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK)
50822 
50823 #define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK         (0x1000U)
50824 #define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT        (12U)
50825 #define GPMI_ECCCTRL_SET_ENABLE_ECC(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK)
50826 
50827 #define GPMI_ECCCTRL_SET_ECC_CMD_MASK            (0x6000U)
50828 #define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT           (13U)
50829 #define GPMI_ECCCTRL_SET_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK)
50830 
50831 #define GPMI_ECCCTRL_SET_RSVD2_MASK              (0x8000U)
50832 #define GPMI_ECCCTRL_SET_RSVD2_SHIFT             (15U)
50833 #define GPMI_ECCCTRL_SET_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK)
50834 
50835 #define GPMI_ECCCTRL_SET_HANDLE_MASK             (0xFFFF0000U)
50836 #define GPMI_ECCCTRL_SET_HANDLE_SHIFT            (16U)
50837 #define GPMI_ECCCTRL_SET_HANDLE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK)
50838 /*! @} */
50839 
50840 /*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */
50841 /*! @{ */
50842 
50843 #define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK        (0x1FFU)
50844 #define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT       (0U)
50845 #define GPMI_ECCCTRL_CLR_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK)
50846 
50847 #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK    (0x600U)
50848 #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT   (9U)
50849 /*! RANDOMIZER_TYPE
50850  *  0b00..Type 0
50851  *  0b01..Type 1
50852  */
50853 #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK)
50854 
50855 #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK  (0x800U)
50856 #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U)
50857 /*! RANDOMIZER_ENABLE
50858  *  0b0..disable
50859  *  0b1..enable
50860  */
50861 #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK)
50862 
50863 #define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK         (0x1000U)
50864 #define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT        (12U)
50865 #define GPMI_ECCCTRL_CLR_ENABLE_ECC(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK)
50866 
50867 #define GPMI_ECCCTRL_CLR_ECC_CMD_MASK            (0x6000U)
50868 #define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT           (13U)
50869 #define GPMI_ECCCTRL_CLR_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK)
50870 
50871 #define GPMI_ECCCTRL_CLR_RSVD2_MASK              (0x8000U)
50872 #define GPMI_ECCCTRL_CLR_RSVD2_SHIFT             (15U)
50873 #define GPMI_ECCCTRL_CLR_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK)
50874 
50875 #define GPMI_ECCCTRL_CLR_HANDLE_MASK             (0xFFFF0000U)
50876 #define GPMI_ECCCTRL_CLR_HANDLE_SHIFT            (16U)
50877 #define GPMI_ECCCTRL_CLR_HANDLE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK)
50878 /*! @} */
50879 
50880 /*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */
50881 /*! @{ */
50882 
50883 #define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK        (0x1FFU)
50884 #define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT       (0U)
50885 #define GPMI_ECCCTRL_TOG_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK)
50886 
50887 #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK    (0x600U)
50888 #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT   (9U)
50889 /*! RANDOMIZER_TYPE
50890  *  0b00..Type 0
50891  *  0b01..Type 1
50892  */
50893 #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK)
50894 
50895 #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK  (0x800U)
50896 #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U)
50897 /*! RANDOMIZER_ENABLE
50898  *  0b0..disable
50899  *  0b1..enable
50900  */
50901 #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK)
50902 
50903 #define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK         (0x1000U)
50904 #define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT        (12U)
50905 #define GPMI_ECCCTRL_TOG_ENABLE_ECC(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK)
50906 
50907 #define GPMI_ECCCTRL_TOG_ECC_CMD_MASK            (0x6000U)
50908 #define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT           (13U)
50909 #define GPMI_ECCCTRL_TOG_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK)
50910 
50911 #define GPMI_ECCCTRL_TOG_RSVD2_MASK              (0x8000U)
50912 #define GPMI_ECCCTRL_TOG_RSVD2_SHIFT             (15U)
50913 #define GPMI_ECCCTRL_TOG_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK)
50914 
50915 #define GPMI_ECCCTRL_TOG_HANDLE_MASK             (0xFFFF0000U)
50916 #define GPMI_ECCCTRL_TOG_HANDLE_SHIFT            (16U)
50917 #define GPMI_ECCCTRL_TOG_HANDLE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK)
50918 /*! @} */
50919 
50920 /*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
50921 /*! @{ */
50922 
50923 #define GPMI_ECCCOUNT_COUNT_MASK                 (0xFFFFU)
50924 #define GPMI_ECCCOUNT_COUNT_SHIFT                (0U)
50925 #define GPMI_ECCCOUNT_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
50926 
50927 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK       (0xFF0000U)
50928 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT      (16U)
50929 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
50930 /*! @} */
50931 
50932 /*! @name PAYLOAD - GPMI Payload Address Register Description */
50933 /*! @{ */
50934 
50935 #define GPMI_PAYLOAD_RSVD0_MASK                  (0x3U)
50936 #define GPMI_PAYLOAD_RSVD0_SHIFT                 (0U)
50937 #define GPMI_PAYLOAD_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
50938 
50939 #define GPMI_PAYLOAD_ADDRESS_MASK                (0xFFFFFFFCU)
50940 #define GPMI_PAYLOAD_ADDRESS_SHIFT               (2U)
50941 #define GPMI_PAYLOAD_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
50942 /*! @} */
50943 
50944 /*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
50945 /*! @{ */
50946 
50947 #define GPMI_AUXILIARY_RSVD0_MASK                (0x3U)
50948 #define GPMI_AUXILIARY_RSVD0_SHIFT               (0U)
50949 #define GPMI_AUXILIARY_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
50950 
50951 #define GPMI_AUXILIARY_ADDRESS_MASK              (0xFFFFFFFCU)
50952 #define GPMI_AUXILIARY_ADDRESS_SHIFT             (2U)
50953 #define GPMI_AUXILIARY_ADDRESS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
50954 /*! @} */
50955 
50956 /*! @name CTRL1 - GPMI Control Register 1 Description */
50957 /*! @{ */
50958 
50959 #define GPMI_CTRL1_GPMI_MODE_MASK                (0x1U)
50960 #define GPMI_CTRL1_GPMI_MODE_SHIFT               (0U)
50961 /*! GPMI_MODE
50962  *  0b0..NAND mode.
50963  *  0b1..ATA mode.
50964  */
50965 #define GPMI_CTRL1_GPMI_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
50966 
50967 #define GPMI_CTRL1_CAMERA_MODE_MASK              (0x2U)
50968 #define GPMI_CTRL1_CAMERA_MODE_SHIFT             (1U)
50969 #define GPMI_CTRL1_CAMERA_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
50970 
50971 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK      (0x4U)
50972 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT     (2U)
50973 /*! ATA_IRQRDY_POLARITY
50974  *  0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
50975  *  0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
50976  */
50977 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
50978 
50979 #define GPMI_CTRL1_DEV_RESET_MASK                (0x8U)
50980 #define GPMI_CTRL1_DEV_RESET_SHIFT               (3U)
50981 /*! DEV_RESET
50982  *  0b0..NANDF_WP_B pin is held low (asserted).
50983  *  0b1..NANDF_WP_B pin is held high (de-asserted).
50984  */
50985 #define GPMI_CTRL1_DEV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
50986 
50987 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
50988 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
50989 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
50990 
50991 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK       (0x80U)
50992 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT      (7U)
50993 #define GPMI_CTRL1_ABORT_WAIT_REQUEST(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
50994 
50995 #define GPMI_CTRL1_BURST_EN_MASK                 (0x100U)
50996 #define GPMI_CTRL1_BURST_EN_SHIFT                (8U)
50997 #define GPMI_CTRL1_BURST_EN(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
50998 
50999 #define GPMI_CTRL1_TIMEOUT_IRQ_MASK              (0x200U)
51000 #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT             (9U)
51001 #define GPMI_CTRL1_TIMEOUT_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
51002 
51003 #define GPMI_CTRL1_DEV_IRQ_MASK                  (0x400U)
51004 #define GPMI_CTRL1_DEV_IRQ_SHIFT                 (10U)
51005 #define GPMI_CTRL1_DEV_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
51006 
51007 #define GPMI_CTRL1_DMA2ECC_MODE_MASK             (0x800U)
51008 #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT            (11U)
51009 #define GPMI_CTRL1_DMA2ECC_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
51010 
51011 #define GPMI_CTRL1_RDN_DELAY_MASK                (0xF000U)
51012 #define GPMI_CTRL1_RDN_DELAY_SHIFT               (12U)
51013 #define GPMI_CTRL1_RDN_DELAY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
51014 
51015 #define GPMI_CTRL1_HALF_PERIOD_MASK              (0x10000U)
51016 #define GPMI_CTRL1_HALF_PERIOD_SHIFT             (16U)
51017 #define GPMI_CTRL1_HALF_PERIOD(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
51018 
51019 #define GPMI_CTRL1_DLL_ENABLE_MASK               (0x20000U)
51020 #define GPMI_CTRL1_DLL_ENABLE_SHIFT              (17U)
51021 #define GPMI_CTRL1_DLL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
51022 
51023 #define GPMI_CTRL1_BCH_MODE_MASK                 (0x40000U)
51024 #define GPMI_CTRL1_BCH_MODE_SHIFT                (18U)
51025 #define GPMI_CTRL1_BCH_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
51026 
51027 #define GPMI_CTRL1_GANGED_RDYBUSY_MASK           (0x80000U)
51028 #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT          (19U)
51029 #define GPMI_CTRL1_GANGED_RDYBUSY(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
51030 
51031 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK           (0x100000U)
51032 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT          (20U)
51033 #define GPMI_CTRL1_TIMEOUT_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
51034 
51035 #define GPMI_CTRL1_TEST_TRIGGER_MASK             (0x200000U)
51036 #define GPMI_CTRL1_TEST_TRIGGER_SHIFT            (21U)
51037 /*! TEST_TRIGGER
51038  *  0b0..Disable
51039  *  0b1..Enable
51040  */
51041 #define GPMI_CTRL1_TEST_TRIGGER(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK)
51042 
51043 #define GPMI_CTRL1_WRN_DLY_SEL_MASK              (0xC00000U)
51044 #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT             (22U)
51045 #define GPMI_CTRL1_WRN_DLY_SEL(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
51046 
51047 #define GPMI_CTRL1_DECOUPLE_CS_MASK              (0x1000000U)
51048 #define GPMI_CTRL1_DECOUPLE_CS_SHIFT             (24U)
51049 #define GPMI_CTRL1_DECOUPLE_CS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
51050 
51051 #define GPMI_CTRL1_SSYNCMODE_MASK                (0x2000000U)
51052 #define GPMI_CTRL1_SSYNCMODE_SHIFT               (25U)
51053 #define GPMI_CTRL1_SSYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
51054 
51055 #define GPMI_CTRL1_UPDATE_CS_MASK                (0x4000000U)
51056 #define GPMI_CTRL1_UPDATE_CS_SHIFT               (26U)
51057 #define GPMI_CTRL1_UPDATE_CS(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
51058 
51059 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK         (0x8000000U)
51060 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT        (27U)
51061 /*! GPMI_CLK_DIV2_EN
51062  *  0b0..internal factor-2 clock divider is disabled
51063  *  0b1..internal factor-2 clock divider is enabled.
51064  */
51065 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
51066 
51067 #define GPMI_CTRL1_TOGGLE_MODE_MASK              (0x10000000U)
51068 #define GPMI_CTRL1_TOGGLE_MODE_SHIFT             (28U)
51069 #define GPMI_CTRL1_TOGGLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
51070 
51071 #define GPMI_CTRL1_WRITE_CLK_STOP_MASK           (0x20000000U)
51072 #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT          (29U)
51073 #define GPMI_CTRL1_WRITE_CLK_STOP(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
51074 
51075 #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK           (0x40000000U)
51076 #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT          (30U)
51077 #define GPMI_CTRL1_SSYNC_CLK_STOP(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
51078 
51079 #define GPMI_CTRL1_DEV_CLK_STOP_MASK             (0x80000000U)
51080 #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT            (31U)
51081 #define GPMI_CTRL1_DEV_CLK_STOP(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
51082 /*! @} */
51083 
51084 /*! @name CTRL1_SET - GPMI Control Register 1 Description */
51085 /*! @{ */
51086 
51087 #define GPMI_CTRL1_SET_GPMI_MODE_MASK            (0x1U)
51088 #define GPMI_CTRL1_SET_GPMI_MODE_SHIFT           (0U)
51089 /*! GPMI_MODE
51090  *  0b0..NAND mode.
51091  *  0b1..ATA mode.
51092  */
51093 #define GPMI_CTRL1_SET_GPMI_MODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK)
51094 
51095 #define GPMI_CTRL1_SET_CAMERA_MODE_MASK          (0x2U)
51096 #define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT         (1U)
51097 #define GPMI_CTRL1_SET_CAMERA_MODE(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK)
51098 
51099 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK  (0x4U)
51100 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U)
51101 /*! ATA_IRQRDY_POLARITY
51102  *  0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
51103  *  0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
51104  */
51105 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK)
51106 
51107 #define GPMI_CTRL1_SET_DEV_RESET_MASK            (0x8U)
51108 #define GPMI_CTRL1_SET_DEV_RESET_SHIFT           (3U)
51109 /*! DEV_RESET
51110  *  0b0..NANDF_WP_B pin is held low (asserted).
51111  *  0b1..NANDF_WP_B pin is held high (de-asserted).
51112  */
51113 #define GPMI_CTRL1_SET_DEV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK)
51114 
51115 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
51116 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
51117 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
51118 
51119 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK   (0x80U)
51120 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT  (7U)
51121 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK)
51122 
51123 #define GPMI_CTRL1_SET_BURST_EN_MASK             (0x100U)
51124 #define GPMI_CTRL1_SET_BURST_EN_SHIFT            (8U)
51125 #define GPMI_CTRL1_SET_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK)
51126 
51127 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK          (0x200U)
51128 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT         (9U)
51129 #define GPMI_CTRL1_SET_TIMEOUT_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK)
51130 
51131 #define GPMI_CTRL1_SET_DEV_IRQ_MASK              (0x400U)
51132 #define GPMI_CTRL1_SET_DEV_IRQ_SHIFT             (10U)
51133 #define GPMI_CTRL1_SET_DEV_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK)
51134 
51135 #define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK         (0x800U)
51136 #define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT        (11U)
51137 #define GPMI_CTRL1_SET_DMA2ECC_MODE(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK)
51138 
51139 #define GPMI_CTRL1_SET_RDN_DELAY_MASK            (0xF000U)
51140 #define GPMI_CTRL1_SET_RDN_DELAY_SHIFT           (12U)
51141 #define GPMI_CTRL1_SET_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK)
51142 
51143 #define GPMI_CTRL1_SET_HALF_PERIOD_MASK          (0x10000U)
51144 #define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT         (16U)
51145 #define GPMI_CTRL1_SET_HALF_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK)
51146 
51147 #define GPMI_CTRL1_SET_DLL_ENABLE_MASK           (0x20000U)
51148 #define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT          (17U)
51149 #define GPMI_CTRL1_SET_DLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK)
51150 
51151 #define GPMI_CTRL1_SET_BCH_MODE_MASK             (0x40000U)
51152 #define GPMI_CTRL1_SET_BCH_MODE_SHIFT            (18U)
51153 #define GPMI_CTRL1_SET_BCH_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK)
51154 
51155 #define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK       (0x80000U)
51156 #define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT      (19U)
51157 #define GPMI_CTRL1_SET_GANGED_RDYBUSY(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK)
51158 
51159 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK       (0x100000U)
51160 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT      (20U)
51161 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK)
51162 
51163 #define GPMI_CTRL1_SET_TEST_TRIGGER_MASK         (0x200000U)
51164 #define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT        (21U)
51165 /*! TEST_TRIGGER
51166  *  0b0..Disable
51167  *  0b1..Enable
51168  */
51169 #define GPMI_CTRL1_SET_TEST_TRIGGER(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK)
51170 
51171 #define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK          (0xC00000U)
51172 #define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT         (22U)
51173 #define GPMI_CTRL1_SET_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK)
51174 
51175 #define GPMI_CTRL1_SET_DECOUPLE_CS_MASK          (0x1000000U)
51176 #define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT         (24U)
51177 #define GPMI_CTRL1_SET_DECOUPLE_CS(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK)
51178 
51179 #define GPMI_CTRL1_SET_SSYNCMODE_MASK            (0x2000000U)
51180 #define GPMI_CTRL1_SET_SSYNCMODE_SHIFT           (25U)
51181 #define GPMI_CTRL1_SET_SSYNCMODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK)
51182 
51183 #define GPMI_CTRL1_SET_UPDATE_CS_MASK            (0x4000000U)
51184 #define GPMI_CTRL1_SET_UPDATE_CS_SHIFT           (26U)
51185 #define GPMI_CTRL1_SET_UPDATE_CS(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK)
51186 
51187 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK     (0x8000000U)
51188 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT    (27U)
51189 /*! GPMI_CLK_DIV2_EN
51190  *  0b0..internal factor-2 clock divider is disabled
51191  *  0b1..internal factor-2 clock divider is enabled.
51192  */
51193 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK)
51194 
51195 #define GPMI_CTRL1_SET_TOGGLE_MODE_MASK          (0x10000000U)
51196 #define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT         (28U)
51197 #define GPMI_CTRL1_SET_TOGGLE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK)
51198 
51199 #define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK       (0x20000000U)
51200 #define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT      (29U)
51201 #define GPMI_CTRL1_SET_WRITE_CLK_STOP(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK)
51202 
51203 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK       (0x40000000U)
51204 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT      (30U)
51205 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK)
51206 
51207 #define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK         (0x80000000U)
51208 #define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT        (31U)
51209 #define GPMI_CTRL1_SET_DEV_CLK_STOP(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK)
51210 /*! @} */
51211 
51212 /*! @name CTRL1_CLR - GPMI Control Register 1 Description */
51213 /*! @{ */
51214 
51215 #define GPMI_CTRL1_CLR_GPMI_MODE_MASK            (0x1U)
51216 #define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT           (0U)
51217 /*! GPMI_MODE
51218  *  0b0..NAND mode.
51219  *  0b1..ATA mode.
51220  */
51221 #define GPMI_CTRL1_CLR_GPMI_MODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK)
51222 
51223 #define GPMI_CTRL1_CLR_CAMERA_MODE_MASK          (0x2U)
51224 #define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT         (1U)
51225 #define GPMI_CTRL1_CLR_CAMERA_MODE(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK)
51226 
51227 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK  (0x4U)
51228 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U)
51229 /*! ATA_IRQRDY_POLARITY
51230  *  0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
51231  *  0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
51232  */
51233 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK)
51234 
51235 #define GPMI_CTRL1_CLR_DEV_RESET_MASK            (0x8U)
51236 #define GPMI_CTRL1_CLR_DEV_RESET_SHIFT           (3U)
51237 /*! DEV_RESET
51238  *  0b0..NANDF_WP_B pin is held low (asserted).
51239  *  0b1..NANDF_WP_B pin is held high (de-asserted).
51240  */
51241 #define GPMI_CTRL1_CLR_DEV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK)
51242 
51243 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
51244 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
51245 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
51246 
51247 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK   (0x80U)
51248 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT  (7U)
51249 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK)
51250 
51251 #define GPMI_CTRL1_CLR_BURST_EN_MASK             (0x100U)
51252 #define GPMI_CTRL1_CLR_BURST_EN_SHIFT            (8U)
51253 #define GPMI_CTRL1_CLR_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK)
51254 
51255 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK          (0x200U)
51256 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT         (9U)
51257 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK)
51258 
51259 #define GPMI_CTRL1_CLR_DEV_IRQ_MASK              (0x400U)
51260 #define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT             (10U)
51261 #define GPMI_CTRL1_CLR_DEV_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK)
51262 
51263 #define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK         (0x800U)
51264 #define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT        (11U)
51265 #define GPMI_CTRL1_CLR_DMA2ECC_MODE(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK)
51266 
51267 #define GPMI_CTRL1_CLR_RDN_DELAY_MASK            (0xF000U)
51268 #define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT           (12U)
51269 #define GPMI_CTRL1_CLR_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK)
51270 
51271 #define GPMI_CTRL1_CLR_HALF_PERIOD_MASK          (0x10000U)
51272 #define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT         (16U)
51273 #define GPMI_CTRL1_CLR_HALF_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK)
51274 
51275 #define GPMI_CTRL1_CLR_DLL_ENABLE_MASK           (0x20000U)
51276 #define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT          (17U)
51277 #define GPMI_CTRL1_CLR_DLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK)
51278 
51279 #define GPMI_CTRL1_CLR_BCH_MODE_MASK             (0x40000U)
51280 #define GPMI_CTRL1_CLR_BCH_MODE_SHIFT            (18U)
51281 #define GPMI_CTRL1_CLR_BCH_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK)
51282 
51283 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK       (0x80000U)
51284 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT      (19U)
51285 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK)
51286 
51287 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK       (0x100000U)
51288 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT      (20U)
51289 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK)
51290 
51291 #define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK         (0x200000U)
51292 #define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT        (21U)
51293 /*! TEST_TRIGGER
51294  *  0b0..Disable
51295  *  0b1..Enable
51296  */
51297 #define GPMI_CTRL1_CLR_TEST_TRIGGER(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK)
51298 
51299 #define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK          (0xC00000U)
51300 #define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT         (22U)
51301 #define GPMI_CTRL1_CLR_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK)
51302 
51303 #define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK          (0x1000000U)
51304 #define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT         (24U)
51305 #define GPMI_CTRL1_CLR_DECOUPLE_CS(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK)
51306 
51307 #define GPMI_CTRL1_CLR_SSYNCMODE_MASK            (0x2000000U)
51308 #define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT           (25U)
51309 #define GPMI_CTRL1_CLR_SSYNCMODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK)
51310 
51311 #define GPMI_CTRL1_CLR_UPDATE_CS_MASK            (0x4000000U)
51312 #define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT           (26U)
51313 #define GPMI_CTRL1_CLR_UPDATE_CS(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK)
51314 
51315 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK     (0x8000000U)
51316 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT    (27U)
51317 /*! GPMI_CLK_DIV2_EN
51318  *  0b0..internal factor-2 clock divider is disabled
51319  *  0b1..internal factor-2 clock divider is enabled.
51320  */
51321 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK)
51322 
51323 #define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK          (0x10000000U)
51324 #define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT         (28U)
51325 #define GPMI_CTRL1_CLR_TOGGLE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK)
51326 
51327 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK       (0x20000000U)
51328 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT      (29U)
51329 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK)
51330 
51331 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK       (0x40000000U)
51332 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT      (30U)
51333 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK)
51334 
51335 #define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK         (0x80000000U)
51336 #define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT        (31U)
51337 #define GPMI_CTRL1_CLR_DEV_CLK_STOP(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK)
51338 /*! @} */
51339 
51340 /*! @name CTRL1_TOG - GPMI Control Register 1 Description */
51341 /*! @{ */
51342 
51343 #define GPMI_CTRL1_TOG_GPMI_MODE_MASK            (0x1U)
51344 #define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT           (0U)
51345 /*! GPMI_MODE
51346  *  0b0..NAND mode.
51347  *  0b1..ATA mode.
51348  */
51349 #define GPMI_CTRL1_TOG_GPMI_MODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK)
51350 
51351 #define GPMI_CTRL1_TOG_CAMERA_MODE_MASK          (0x2U)
51352 #define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT         (1U)
51353 #define GPMI_CTRL1_TOG_CAMERA_MODE(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK)
51354 
51355 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK  (0x4U)
51356 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U)
51357 /*! ATA_IRQRDY_POLARITY
51358  *  0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
51359  *  0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
51360  */
51361 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK)
51362 
51363 #define GPMI_CTRL1_TOG_DEV_RESET_MASK            (0x8U)
51364 #define GPMI_CTRL1_TOG_DEV_RESET_SHIFT           (3U)
51365 /*! DEV_RESET
51366  *  0b0..NANDF_WP_B pin is held low (asserted).
51367  *  0b1..NANDF_WP_B pin is held high (de-asserted).
51368  */
51369 #define GPMI_CTRL1_TOG_DEV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK)
51370 
51371 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
51372 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
51373 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
51374 
51375 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK   (0x80U)
51376 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT  (7U)
51377 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK)
51378 
51379 #define GPMI_CTRL1_TOG_BURST_EN_MASK             (0x100U)
51380 #define GPMI_CTRL1_TOG_BURST_EN_SHIFT            (8U)
51381 #define GPMI_CTRL1_TOG_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK)
51382 
51383 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK          (0x200U)
51384 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT         (9U)
51385 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK)
51386 
51387 #define GPMI_CTRL1_TOG_DEV_IRQ_MASK              (0x400U)
51388 #define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT             (10U)
51389 #define GPMI_CTRL1_TOG_DEV_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK)
51390 
51391 #define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK         (0x800U)
51392 #define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT        (11U)
51393 #define GPMI_CTRL1_TOG_DMA2ECC_MODE(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK)
51394 
51395 #define GPMI_CTRL1_TOG_RDN_DELAY_MASK            (0xF000U)
51396 #define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT           (12U)
51397 #define GPMI_CTRL1_TOG_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK)
51398 
51399 #define GPMI_CTRL1_TOG_HALF_PERIOD_MASK          (0x10000U)
51400 #define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT         (16U)
51401 #define GPMI_CTRL1_TOG_HALF_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK)
51402 
51403 #define GPMI_CTRL1_TOG_DLL_ENABLE_MASK           (0x20000U)
51404 #define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT          (17U)
51405 #define GPMI_CTRL1_TOG_DLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK)
51406 
51407 #define GPMI_CTRL1_TOG_BCH_MODE_MASK             (0x40000U)
51408 #define GPMI_CTRL1_TOG_BCH_MODE_SHIFT            (18U)
51409 #define GPMI_CTRL1_TOG_BCH_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK)
51410 
51411 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK       (0x80000U)
51412 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT      (19U)
51413 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK)
51414 
51415 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK       (0x100000U)
51416 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT      (20U)
51417 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK)
51418 
51419 #define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK         (0x200000U)
51420 #define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT        (21U)
51421 /*! TEST_TRIGGER
51422  *  0b0..Disable
51423  *  0b1..Enable
51424  */
51425 #define GPMI_CTRL1_TOG_TEST_TRIGGER(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK)
51426 
51427 #define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK          (0xC00000U)
51428 #define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT         (22U)
51429 #define GPMI_CTRL1_TOG_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK)
51430 
51431 #define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK          (0x1000000U)
51432 #define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT         (24U)
51433 #define GPMI_CTRL1_TOG_DECOUPLE_CS(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK)
51434 
51435 #define GPMI_CTRL1_TOG_SSYNCMODE_MASK            (0x2000000U)
51436 #define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT           (25U)
51437 #define GPMI_CTRL1_TOG_SSYNCMODE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK)
51438 
51439 #define GPMI_CTRL1_TOG_UPDATE_CS_MASK            (0x4000000U)
51440 #define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT           (26U)
51441 #define GPMI_CTRL1_TOG_UPDATE_CS(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK)
51442 
51443 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK     (0x8000000U)
51444 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT    (27U)
51445 /*! GPMI_CLK_DIV2_EN
51446  *  0b0..internal factor-2 clock divider is disabled
51447  *  0b1..internal factor-2 clock divider is enabled.
51448  */
51449 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK)
51450 
51451 #define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK          (0x10000000U)
51452 #define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT         (28U)
51453 #define GPMI_CTRL1_TOG_TOGGLE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK)
51454 
51455 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK       (0x20000000U)
51456 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT      (29U)
51457 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK)
51458 
51459 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK       (0x40000000U)
51460 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT      (30U)
51461 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK)
51462 
51463 #define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK         (0x80000000U)
51464 #define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT        (31U)
51465 #define GPMI_CTRL1_TOG_DEV_CLK_STOP(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK)
51466 /*! @} */
51467 
51468 /*! @name TIMING0 - GPMI Timing Register 0 Description */
51469 /*! @{ */
51470 
51471 #define GPMI_TIMING0_DATA_SETUP_MASK             (0xFFU)
51472 #define GPMI_TIMING0_DATA_SETUP_SHIFT            (0U)
51473 #define GPMI_TIMING0_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
51474 
51475 #define GPMI_TIMING0_DATA_HOLD_MASK              (0xFF00U)
51476 #define GPMI_TIMING0_DATA_HOLD_SHIFT             (8U)
51477 #define GPMI_TIMING0_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
51478 
51479 #define GPMI_TIMING0_ADDRESS_SETUP_MASK          (0xFF0000U)
51480 #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT         (16U)
51481 #define GPMI_TIMING0_ADDRESS_SETUP(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
51482 
51483 #define GPMI_TIMING0_RSVD1_MASK                  (0xFF000000U)
51484 #define GPMI_TIMING0_RSVD1_SHIFT                 (24U)
51485 #define GPMI_TIMING0_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
51486 /*! @} */
51487 
51488 /*! @name TIMING1 - GPMI Timing Register 1 Description */
51489 /*! @{ */
51490 
51491 #define GPMI_TIMING1_RSVD1_MASK                  (0xFFFFU)
51492 #define GPMI_TIMING1_RSVD1_SHIFT                 (0U)
51493 #define GPMI_TIMING1_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
51494 
51495 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK    (0xFFFF0000U)
51496 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT   (16U)
51497 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
51498 /*! @} */
51499 
51500 /*! @name TIMING2 - GPMI Timing Register 2 Description */
51501 /*! @{ */
51502 
51503 #define GPMI_TIMING2_DATA_PAUSE_MASK             (0xFU)
51504 #define GPMI_TIMING2_DATA_PAUSE_SHIFT            (0U)
51505 #define GPMI_TIMING2_DATA_PAUSE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
51506 
51507 #define GPMI_TIMING2_CMDADD_PAUSE_MASK           (0xF0U)
51508 #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT          (4U)
51509 #define GPMI_TIMING2_CMDADD_PAUSE(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
51510 
51511 #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK        (0xF00U)
51512 #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT       (8U)
51513 #define GPMI_TIMING2_POSTAMBLE_DELAY(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
51514 
51515 #define GPMI_TIMING2_PREAMBLE_DELAY_MASK         (0xF000U)
51516 #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT        (12U)
51517 #define GPMI_TIMING2_PREAMBLE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
51518 
51519 #define GPMI_TIMING2_CE_DELAY_MASK               (0x1F0000U)
51520 #define GPMI_TIMING2_CE_DELAY_SHIFT              (16U)
51521 #define GPMI_TIMING2_CE_DELAY(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
51522 
51523 #define GPMI_TIMING2_RSVD0_MASK                  (0xE00000U)
51524 #define GPMI_TIMING2_RSVD0_SHIFT                 (21U)
51525 #define GPMI_TIMING2_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
51526 
51527 #define GPMI_TIMING2_READ_LATENCY_MASK           (0x7000000U)
51528 #define GPMI_TIMING2_READ_LATENCY_SHIFT          (24U)
51529 /*! READ_LATENCY
51530  *  0b000..READ LATENCY is 0
51531  *  0b001..READ LATENCY is 1
51532  *  0b010..READ LATENCY is 2
51533  *  0b011..READ LATENCY is 3
51534  *  0b100..READ LATENCY is 4
51535  *  0b101..READ LATENCY is 5
51536  */
51537 #define GPMI_TIMING2_READ_LATENCY(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
51538 
51539 #define GPMI_TIMING2_TCR_MASK                    (0x18000000U)
51540 #define GPMI_TIMING2_TCR_SHIFT                   (27U)
51541 #define GPMI_TIMING2_TCR(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK)
51542 
51543 #define GPMI_TIMING2_TRPSTH_MASK                 (0xE0000000U)
51544 #define GPMI_TIMING2_TRPSTH_SHIFT                (29U)
51545 #define GPMI_TIMING2_TRPSTH(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK)
51546 /*! @} */
51547 
51548 /*! @name DATA - GPMI DMA Data Transfer Register Description */
51549 /*! @{ */
51550 
51551 #define GPMI_DATA_DATA_MASK                      (0xFFFFFFFFU)
51552 #define GPMI_DATA_DATA_SHIFT                     (0U)
51553 #define GPMI_DATA_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
51554 /*! @} */
51555 
51556 /*! @name STAT - GPMI Status Register Description */
51557 /*! @{ */
51558 
51559 #define GPMI_STAT_PRESENT_MASK                   (0x1U)
51560 #define GPMI_STAT_PRESENT_SHIFT                  (0U)
51561 /*! PRESENT
51562  *  0b0..GPMI is not present in this product.
51563  *  0b1..GPMI is present is in this product.
51564  */
51565 #define GPMI_STAT_PRESENT(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
51566 
51567 #define GPMI_STAT_FIFO_FULL_MASK                 (0x2U)
51568 #define GPMI_STAT_FIFO_FULL_SHIFT                (1U)
51569 /*! FIFO_FULL
51570  *  0b0..FIFO is not full.
51571  *  0b1..FIFO is full.
51572  */
51573 #define GPMI_STAT_FIFO_FULL(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
51574 
51575 #define GPMI_STAT_FIFO_EMPTY_MASK                (0x4U)
51576 #define GPMI_STAT_FIFO_EMPTY_SHIFT               (2U)
51577 /*! FIFO_EMPTY
51578  *  0b0..FIFO is not empty.
51579  *  0b1..FIFO is empty.
51580  */
51581 #define GPMI_STAT_FIFO_EMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
51582 
51583 #define GPMI_STAT_INVALID_BUFFER_MASK_MASK       (0x8U)
51584 #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT      (3U)
51585 /*! INVALID_BUFFER_MASK
51586  *  0b0..ECC Buffer Mask is not invalid.
51587  *  0b1..ECC Buffer Mask is invalid.
51588  */
51589 #define GPMI_STAT_INVALID_BUFFER_MASK(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
51590 
51591 #define GPMI_STAT_ATA_IRQ_MASK                   (0x10U)
51592 #define GPMI_STAT_ATA_IRQ_SHIFT                  (4U)
51593 #define GPMI_STAT_ATA_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
51594 
51595 #define GPMI_STAT_RSVD1_MASK                     (0xE0U)
51596 #define GPMI_STAT_RSVD1_SHIFT                    (5U)
51597 #define GPMI_STAT_RSVD1(x)                       (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
51598 
51599 #define GPMI_STAT_DEV0_ERROR_MASK                (0x100U)
51600 #define GPMI_STAT_DEV0_ERROR_SHIFT               (8U)
51601 /*! DEV0_ERROR
51602  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
51603  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51604  */
51605 #define GPMI_STAT_DEV0_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
51606 
51607 #define GPMI_STAT_DEV1_ERROR_MASK                (0x200U)
51608 #define GPMI_STAT_DEV1_ERROR_SHIFT               (9U)
51609 /*! DEV1_ERROR
51610  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
51611  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51612  */
51613 #define GPMI_STAT_DEV1_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
51614 
51615 #define GPMI_STAT_DEV2_ERROR_MASK                (0x400U)
51616 #define GPMI_STAT_DEV2_ERROR_SHIFT               (10U)
51617 /*! DEV2_ERROR
51618  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
51619  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51620  */
51621 #define GPMI_STAT_DEV2_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
51622 
51623 #define GPMI_STAT_DEV3_ERROR_MASK                (0x800U)
51624 #define GPMI_STAT_DEV3_ERROR_SHIFT               (11U)
51625 /*! DEV3_ERROR
51626  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
51627  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51628  */
51629 #define GPMI_STAT_DEV3_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
51630 
51631 #define GPMI_STAT_DEV4_ERROR_MASK                (0x1000U)
51632 #define GPMI_STAT_DEV4_ERROR_SHIFT               (12U)
51633 /*! DEV4_ERROR
51634  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
51635  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51636  */
51637 #define GPMI_STAT_DEV4_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
51638 
51639 #define GPMI_STAT_DEV5_ERROR_MASK                (0x2000U)
51640 #define GPMI_STAT_DEV5_ERROR_SHIFT               (13U)
51641 /*! DEV5_ERROR
51642  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
51643  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51644  */
51645 #define GPMI_STAT_DEV5_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
51646 
51647 #define GPMI_STAT_DEV6_ERROR_MASK                (0x4000U)
51648 #define GPMI_STAT_DEV6_ERROR_SHIFT               (14U)
51649 /*! DEV6_ERROR
51650  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
51651  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51652  */
51653 #define GPMI_STAT_DEV6_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
51654 
51655 #define GPMI_STAT_DEV7_ERROR_MASK                (0x8000U)
51656 #define GPMI_STAT_DEV7_ERROR_SHIFT               (15U)
51657 /*! DEV7_ERROR
51658  *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
51659  *  0b1..An Error has occurred on ATA/NAND Device accessed by
51660  */
51661 #define GPMI_STAT_DEV7_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
51662 
51663 #define GPMI_STAT_RDY_TIMEOUT_MASK               (0xFF0000U)
51664 #define GPMI_STAT_RDY_TIMEOUT_SHIFT              (16U)
51665 #define GPMI_STAT_RDY_TIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
51666 
51667 #define GPMI_STAT_READY_BUSY_MASK                (0xFF000000U)
51668 #define GPMI_STAT_READY_BUSY_SHIFT               (24U)
51669 #define GPMI_STAT_READY_BUSY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
51670 /*! @} */
51671 
51672 /*! @name DEBUG - GPMI Debug Information Register Description */
51673 /*! @{ */
51674 
51675 #define GPMI_DEBUG_CMD_END_MASK                  (0xFFU)
51676 #define GPMI_DEBUG_CMD_END_SHIFT                 (0U)
51677 #define GPMI_DEBUG_CMD_END(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
51678 
51679 #define GPMI_DEBUG_DMAREQ_MASK                   (0xFF00U)
51680 #define GPMI_DEBUG_DMAREQ_SHIFT                  (8U)
51681 #define GPMI_DEBUG_DMAREQ(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
51682 
51683 #define GPMI_DEBUG_DMA_SENSE_MASK                (0xFF0000U)
51684 #define GPMI_DEBUG_DMA_SENSE_SHIFT               (16U)
51685 #define GPMI_DEBUG_DMA_SENSE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
51686 
51687 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK       (0xFF000000U)
51688 #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT      (24U)
51689 #define GPMI_DEBUG_WAIT_FOR_READY_END(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
51690 /*! @} */
51691 
51692 /*! @name VERSION - GPMI Version Register Description */
51693 /*! @{ */
51694 
51695 #define GPMI_VERSION_STEP_MASK                   (0xFFFFU)
51696 #define GPMI_VERSION_STEP_SHIFT                  (0U)
51697 #define GPMI_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
51698 
51699 #define GPMI_VERSION_MINOR_MASK                  (0xFF0000U)
51700 #define GPMI_VERSION_MINOR_SHIFT                 (16U)
51701 #define GPMI_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
51702 
51703 #define GPMI_VERSION_MAJOR_MASK                  (0xFF000000U)
51704 #define GPMI_VERSION_MAJOR_SHIFT                 (24U)
51705 #define GPMI_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
51706 /*! @} */
51707 
51708 /*! @name DEBUG2 - GPMI Debug2 Information Register Description */
51709 /*! @{ */
51710 
51711 #define GPMI_DEBUG2_RDN_TAP_MASK                 (0x3FU)
51712 #define GPMI_DEBUG2_RDN_TAP_SHIFT                (0U)
51713 #define GPMI_DEBUG2_RDN_TAP(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
51714 
51715 #define GPMI_DEBUG2_UPDATE_WINDOW_MASK           (0x40U)
51716 #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT          (6U)
51717 #define GPMI_DEBUG2_UPDATE_WINDOW(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
51718 
51719 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK        (0x80U)
51720 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT       (7U)
51721 #define GPMI_DEBUG2_VIEW_DELAYED_RDN(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
51722 
51723 #define GPMI_DEBUG2_SYND2GPMI_READY_MASK         (0x100U)
51724 #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT        (8U)
51725 #define GPMI_DEBUG2_SYND2GPMI_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
51726 
51727 #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK         (0x200U)
51728 #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT        (9U)
51729 #define GPMI_DEBUG2_SYND2GPMI_VALID(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
51730 
51731 #define GPMI_DEBUG2_GPMI2SYND_READY_MASK         (0x400U)
51732 #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT        (10U)
51733 #define GPMI_DEBUG2_GPMI2SYND_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
51734 
51735 #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK         (0x800U)
51736 #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT        (11U)
51737 #define GPMI_DEBUG2_GPMI2SYND_VALID(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
51738 
51739 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK            (0xF000U)
51740 #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT           (12U)
51741 #define GPMI_DEBUG2_SYND2GPMI_BE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
51742 
51743 #define GPMI_DEBUG2_MAIN_STATE_MASK              (0xF0000U)
51744 #define GPMI_DEBUG2_MAIN_STATE_SHIFT             (16U)
51745 #define GPMI_DEBUG2_MAIN_STATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
51746 
51747 #define GPMI_DEBUG2_PIN_STATE_MASK               (0x700000U)
51748 #define GPMI_DEBUG2_PIN_STATE_SHIFT              (20U)
51749 #define GPMI_DEBUG2_PIN_STATE(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
51750 
51751 #define GPMI_DEBUG2_BUSY_MASK                    (0x800000U)
51752 #define GPMI_DEBUG2_BUSY_SHIFT                   (23U)
51753 #define GPMI_DEBUG2_BUSY(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
51754 
51755 #define GPMI_DEBUG2_UDMA_STATE_MASK              (0xF000000U)
51756 #define GPMI_DEBUG2_UDMA_STATE_SHIFT             (24U)
51757 #define GPMI_DEBUG2_UDMA_STATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
51758 
51759 #define GPMI_DEBUG2_RSVD1_MASK                   (0xF0000000U)
51760 #define GPMI_DEBUG2_RSVD1_SHIFT                  (28U)
51761 #define GPMI_DEBUG2_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
51762 /*! @} */
51763 
51764 /*! @name DEBUG3 - GPMI Debug3 Information Register Description */
51765 /*! @{ */
51766 
51767 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK           (0xFFFFU)
51768 #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT          (0U)
51769 #define GPMI_DEBUG3_DEV_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
51770 
51771 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK           (0xFFFF0000U)
51772 #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT          (16U)
51773 #define GPMI_DEBUG3_APB_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
51774 /*! @} */
51775 
51776 /*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
51777 /*! @{ */
51778 
51779 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK       (0x1U)
51780 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT      (0U)
51781 #define GPMI_READ_DDR_DLL_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
51782 
51783 #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK        (0x2U)
51784 #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT       (1U)
51785 #define GPMI_READ_DDR_DLL_CTRL_RESET(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
51786 
51787 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
51788 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
51789 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x)  (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
51790 
51791 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
51792 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
51793 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
51794 
51795 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK  (0x80U)
51796 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
51797 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
51798 
51799 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK    (0x100U)
51800 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT   (8U)
51801 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
51802 
51803 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
51804 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
51805 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
51806 
51807 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
51808 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
51809 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
51810 
51811 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK        (0xC0000U)
51812 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT       (18U)
51813 #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
51814 
51815 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
51816 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
51817 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
51818 
51819 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
51820 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
51821 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
51822 /*! @} */
51823 
51824 /*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
51825 /*! @{ */
51826 
51827 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK      (0x1U)
51828 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT     (0U)
51829 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
51830 
51831 #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK       (0x2U)
51832 #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT      (1U)
51833 #define GPMI_WRITE_DDR_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
51834 
51835 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
51836 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
51837 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
51838 
51839 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
51840 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
51841 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
51842 
51843 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
51844 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
51845 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
51846 
51847 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK   (0x100U)
51848 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT  (8U)
51849 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x)     (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
51850 
51851 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
51852 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
51853 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
51854 
51855 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
51856 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
51857 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
51858 
51859 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK       (0xC0000U)
51860 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT      (18U)
51861 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
51862 
51863 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
51864 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
51865 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
51866 
51867 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
51868 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
51869 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
51870 /*! @} */
51871 
51872 /*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
51873 /*! @{ */
51874 
51875 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK      (0x1U)
51876 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT     (0U)
51877 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
51878 
51879 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK       (0x1FEU)
51880 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT      (1U)
51881 #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
51882 
51883 #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK         (0xFE00U)
51884 #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT        (9U)
51885 #define GPMI_READ_DDR_DLL_STS_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
51886 
51887 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK      (0x10000U)
51888 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT     (16U)
51889 #define GPMI_READ_DDR_DLL_STS_REF_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
51890 
51891 #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK       (0x1FE0000U)
51892 #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT      (17U)
51893 #define GPMI_READ_DDR_DLL_STS_REF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
51894 
51895 #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK         (0xFE000000U)
51896 #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT        (25U)
51897 #define GPMI_READ_DDR_DLL_STS_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
51898 /*! @} */
51899 
51900 /*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
51901 /*! @{ */
51902 
51903 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK     (0x1U)
51904 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT    (0U)
51905 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
51906 
51907 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK      (0x1FEU)
51908 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT     (1U)
51909 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
51910 
51911 #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK        (0xFE00U)
51912 #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT       (9U)
51913 #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
51914 
51915 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK     (0x10000U)
51916 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT    (16U)
51917 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
51918 
51919 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK      (0x1FE0000U)
51920 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT     (17U)
51921 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
51922 
51923 #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK        (0xFE000000U)
51924 #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT       (25U)
51925 #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
51926 /*! @} */
51927 
51928 
51929 /*!
51930  * @}
51931  */ /* end of group GPMI_Register_Masks */
51932 
51933 
51934 /* GPMI - Peripheral instance base addresses */
51935 /** Peripheral GPMI base address */
51936 #define GPMI_BASE                                (0x33002000u)
51937 /** Peripheral GPMI base pointer */
51938 #define GPMI                                     ((GPMI_Type *)GPMI_BASE)
51939 /** Array initializer of GPMI peripheral base addresses */
51940 #define GPMI_BASE_ADDRS                          { GPMI_BASE }
51941 /** Array initializer of GPMI peripheral base pointers */
51942 #define GPMI_BASE_PTRS                           { GPMI }
51943 
51944 /*!
51945  * @}
51946  */ /* end of group GPMI_Peripheral_Access_Layer */
51947 
51948 
51949 /* ----------------------------------------------------------------------------
51950    -- GPT Peripheral Access Layer
51951    ---------------------------------------------------------------------------- */
51952 
51953 /*!
51954  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
51955  * @{
51956  */
51957 
51958 /** GPT - Register Layout Typedef */
51959 typedef struct {
51960   __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
51961   __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
51962   __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
51963   __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
51964   __IO uint32_t OCR[3];                            /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
51965   __I  uint32_t ICR[2];                            /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
51966   __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
51967 } GPT_Type;
51968 
51969 /* ----------------------------------------------------------------------------
51970    -- GPT Register Masks
51971    ---------------------------------------------------------------------------- */
51972 
51973 /*!
51974  * @addtogroup GPT_Register_Masks GPT Register Masks
51975  * @{
51976  */
51977 
51978 /*! @name CR - GPT Control Register */
51979 /*! @{ */
51980 
51981 #define GPT_CR_EN_MASK                           (0x1U)
51982 #define GPT_CR_EN_SHIFT                          (0U)
51983 /*! EN
51984  *  0b0..GPT is disabled.
51985  *  0b1..GPT is enabled.
51986  */
51987 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
51988 
51989 #define GPT_CR_ENMOD_MASK                        (0x2U)
51990 #define GPT_CR_ENMOD_SHIFT                       (1U)
51991 /*! ENMOD
51992  *  0b0..GPT counter will retain its value when it is disabled.
51993  *  0b1..GPT counter value is reset to 0 when it is disabled.
51994  */
51995 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
51996 
51997 #define GPT_CR_DBGEN_MASK                        (0x4U)
51998 #define GPT_CR_DBGEN_SHIFT                       (2U)
51999 /*! DBGEN
52000  *  0b0..GPT is disabled in debug mode.
52001  *  0b1..GPT is enabled in debug mode.
52002  */
52003 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
52004 
52005 #define GPT_CR_WAITEN_MASK                       (0x8U)
52006 #define GPT_CR_WAITEN_SHIFT                      (3U)
52007 /*! WAITEN
52008  *  0b0..GPT is disabled in wait mode.
52009  *  0b1..GPT is enabled in wait mode.
52010  */
52011 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
52012 
52013 #define GPT_CR_DOZEEN_MASK                       (0x10U)
52014 #define GPT_CR_DOZEEN_SHIFT                      (4U)
52015 /*! DOZEEN
52016  *  0b0..GPT is disabled in doze mode.
52017  *  0b1..GPT is enabled in doze mode.
52018  */
52019 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
52020 
52021 #define GPT_CR_STOPEN_MASK                       (0x20U)
52022 #define GPT_CR_STOPEN_SHIFT                      (5U)
52023 /*! STOPEN
52024  *  0b0..GPT is disabled in Stop mode.
52025  *  0b1..GPT is enabled in Stop mode.
52026  */
52027 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
52028 
52029 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
52030 #define GPT_CR_CLKSRC_SHIFT                      (6U)
52031 /*! CLKSRC
52032  *  0b000..No clock
52033  *  0b001..Peripheral Clock (ipg_clk)
52034  *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
52035  *  0b011..External Clock
52036  *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
52037  *  0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
52038  */
52039 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
52040 
52041 #define GPT_CR_FRR_MASK                          (0x200U)
52042 #define GPT_CR_FRR_SHIFT                         (9U)
52043 /*! FRR
52044  *  0b0..Restart mode
52045  *  0b1..Free-Run mode
52046  */
52047 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
52048 
52049 #define GPT_CR_EN_24M_MASK                       (0x400U)
52050 #define GPT_CR_EN_24M_SHIFT                      (10U)
52051 /*! EN_24M
52052  *  0b0..24M clock disabled
52053  *  0b1..24M clock enabled
52054  */
52055 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
52056 
52057 #define GPT_CR_SWR_MASK                          (0x8000U)
52058 #define GPT_CR_SWR_SHIFT                         (15U)
52059 /*! SWR
52060  *  0b0..GPT is not in reset state
52061  *  0b1..GPT is in reset state
52062  */
52063 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
52064 
52065 #define GPT_CR_IM1_MASK                          (0x30000U)
52066 #define GPT_CR_IM1_SHIFT                         (16U)
52067 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
52068 
52069 #define GPT_CR_IM2_MASK                          (0xC0000U)
52070 #define GPT_CR_IM2_SHIFT                         (18U)
52071 /*! IM2
52072  *  0b00..capture disabled
52073  *  0b01..capture on rising edge only
52074  *  0b10..capture on falling edge only
52075  *  0b11..capture on both edges
52076  */
52077 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
52078 
52079 #define GPT_CR_OM1_MASK                          (0x700000U)
52080 #define GPT_CR_OM1_SHIFT                         (20U)
52081 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
52082 
52083 #define GPT_CR_OM2_MASK                          (0x3800000U)
52084 #define GPT_CR_OM2_SHIFT                         (23U)
52085 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
52086 
52087 #define GPT_CR_OM3_MASK                          (0x1C000000U)
52088 #define GPT_CR_OM3_SHIFT                         (26U)
52089 /*! OM3
52090  *  0b000..Output disconnected. No response on pin.
52091  *  0b001..Toggle output pin
52092  *  0b010..Clear output pin
52093  *  0b011..Set output pin
52094  *  0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
52095  */
52096 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
52097 
52098 #define GPT_CR_FO1_MASK                          (0x20000000U)
52099 #define GPT_CR_FO1_SHIFT                         (29U)
52100 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
52101 
52102 #define GPT_CR_FO2_MASK                          (0x40000000U)
52103 #define GPT_CR_FO2_SHIFT                         (30U)
52104 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
52105 
52106 #define GPT_CR_FO3_MASK                          (0x80000000U)
52107 #define GPT_CR_FO3_SHIFT                         (31U)
52108 /*! FO3
52109  *  0b0..Writing a 0 has no effect.
52110  *  0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
52111  */
52112 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
52113 /*! @} */
52114 
52115 /*! @name PR - GPT Prescaler Register */
52116 /*! @{ */
52117 
52118 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
52119 #define GPT_PR_PRESCALER_SHIFT                   (0U)
52120 /*! PRESCALER
52121  *  0b000000000000..Divide by 1
52122  *  0b000000000001..Divide by 2
52123  *  0b111111111111..Divide by 4096
52124  */
52125 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
52126 
52127 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
52128 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
52129 /*! PRESCALER24M
52130  *  0b0000..Divide by 1
52131  *  0b0001..Divide by 2
52132  *  0b1111..Divide by 16
52133  */
52134 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
52135 /*! @} */
52136 
52137 /*! @name SR - GPT Status Register */
52138 /*! @{ */
52139 
52140 #define GPT_SR_OF1_MASK                          (0x1U)
52141 #define GPT_SR_OF1_SHIFT                         (0U)
52142 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
52143 
52144 #define GPT_SR_OF2_MASK                          (0x2U)
52145 #define GPT_SR_OF2_SHIFT                         (1U)
52146 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
52147 
52148 #define GPT_SR_OF3_MASK                          (0x4U)
52149 #define GPT_SR_OF3_SHIFT                         (2U)
52150 /*! OF3
52151  *  0b0..Compare event has not occurred.
52152  *  0b1..Compare event has occurred.
52153  */
52154 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
52155 
52156 #define GPT_SR_IF1_MASK                          (0x8U)
52157 #define GPT_SR_IF1_SHIFT                         (3U)
52158 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
52159 
52160 #define GPT_SR_IF2_MASK                          (0x10U)
52161 #define GPT_SR_IF2_SHIFT                         (4U)
52162 /*! IF2
52163  *  0b0..Capture event has not occurred.
52164  *  0b1..Capture event has occurred.
52165  */
52166 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
52167 
52168 #define GPT_SR_ROV_MASK                          (0x20U)
52169 #define GPT_SR_ROV_SHIFT                         (5U)
52170 /*! ROV
52171  *  0b0..Rollover has not occurred.
52172  *  0b1..Rollover has occurred.
52173  */
52174 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
52175 /*! @} */
52176 
52177 /*! @name IR - GPT Interrupt Register */
52178 /*! @{ */
52179 
52180 #define GPT_IR_OF1IE_MASK                        (0x1U)
52181 #define GPT_IR_OF1IE_SHIFT                       (0U)
52182 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
52183 
52184 #define GPT_IR_OF2IE_MASK                        (0x2U)
52185 #define GPT_IR_OF2IE_SHIFT                       (1U)
52186 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
52187 
52188 #define GPT_IR_OF3IE_MASK                        (0x4U)
52189 #define GPT_IR_OF3IE_SHIFT                       (2U)
52190 /*! OF3IE
52191  *  0b0..Output Compare Channel n interrupt is disabled.
52192  *  0b1..Output Compare Channel n interrupt is enabled.
52193  */
52194 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
52195 
52196 #define GPT_IR_IF1IE_MASK                        (0x8U)
52197 #define GPT_IR_IF1IE_SHIFT                       (3U)
52198 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
52199 
52200 #define GPT_IR_IF2IE_MASK                        (0x10U)
52201 #define GPT_IR_IF2IE_SHIFT                       (4U)
52202 /*! IF2IE
52203  *  0b0..IF2IE Input Capture n Interrupt Enable is disabled.
52204  *  0b1..IF2IE Input Capture n Interrupt Enable is enabled.
52205  */
52206 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
52207 
52208 #define GPT_IR_ROVIE_MASK                        (0x20U)
52209 #define GPT_IR_ROVIE_SHIFT                       (5U)
52210 /*! ROVIE
52211  *  0b0..Rollover interrupt is disabled.
52212  *  0b1..Rollover interrupt enabled.
52213  */
52214 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
52215 /*! @} */
52216 
52217 /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
52218 /*! @{ */
52219 
52220 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
52221 #define GPT_OCR_COMP_SHIFT                       (0U)
52222 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
52223 /*! @} */
52224 
52225 /* The count of GPT_OCR */
52226 #define GPT_OCR_COUNT                            (3U)
52227 
52228 /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
52229 /*! @{ */
52230 
52231 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
52232 #define GPT_ICR_CAPT_SHIFT                       (0U)
52233 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
52234 /*! @} */
52235 
52236 /* The count of GPT_ICR */
52237 #define GPT_ICR_COUNT                            (2U)
52238 
52239 /*! @name CNT - GPT Counter Register */
52240 /*! @{ */
52241 
52242 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
52243 #define GPT_CNT_COUNT_SHIFT                      (0U)
52244 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
52245 /*! @} */
52246 
52247 
52248 /*!
52249  * @}
52250  */ /* end of group GPT_Register_Masks */
52251 
52252 
52253 /* GPT - Peripheral instance base addresses */
52254 /** Peripheral GPT1 base address */
52255 #define GPT1_BASE                                (0x302D0000u)
52256 /** Peripheral GPT1 base pointer */
52257 #define GPT1                                     ((GPT_Type *)GPT1_BASE)
52258 /** Peripheral GPT2 base address */
52259 #define GPT2_BASE                                (0x302E0000u)
52260 /** Peripheral GPT2 base pointer */
52261 #define GPT2                                     ((GPT_Type *)GPT2_BASE)
52262 /** Peripheral GPT3 base address */
52263 #define GPT3_BASE                                (0x302F0000u)
52264 /** Peripheral GPT3 base pointer */
52265 #define GPT3                                     ((GPT_Type *)GPT3_BASE)
52266 /** Peripheral GPT4 base address */
52267 #define GPT4_BASE                                (0x30700000u)
52268 /** Peripheral GPT4 base pointer */
52269 #define GPT4                                     ((GPT_Type *)GPT4_BASE)
52270 /** Peripheral GPT5 base address */
52271 #define GPT5_BASE                                (0x306F0000u)
52272 /** Peripheral GPT5 base pointer */
52273 #define GPT5                                     ((GPT_Type *)GPT5_BASE)
52274 /** Peripheral GPT6 base address */
52275 #define GPT6_BASE                                (0x306E0000u)
52276 /** Peripheral GPT6 base pointer */
52277 #define GPT6                                     ((GPT_Type *)GPT6_BASE)
52278 /** Array initializer of GPT peripheral base addresses */
52279 #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
52280 /** Array initializer of GPT peripheral base pointers */
52281 #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
52282 /** Interrupt vectors for the GPT peripheral type */
52283 #define GPT_IRQS                                 { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
52284 
52285 /*!
52286  * @}
52287  */ /* end of group GPT_Peripheral_Access_Layer */
52288 
52289 
52290 /* ----------------------------------------------------------------------------
52291    -- HDCP Peripheral Access Layer
52292    ---------------------------------------------------------------------------- */
52293 
52294 /*!
52295  * @addtogroup HDCP_Peripheral_Access_Layer HDCP Peripheral Access Layer
52296  * @{
52297  */
52298 
52299 /** HDCP - Register Layout Typedef */
52300 typedef struct {
52301   __IO uint8_t A_HDCPCFG0;                         /**< HDCP Enable and Functional Control Configuration Register 0, offset: 0x0 */
52302   __IO uint8_t A_HDCPCFG1;                         /**< HDCP Software Reset and Functional Control Configuration Register 1, offset: 0x1 */
52303   __I  uint8_t A_HDCPOBS0;                         /**< HDCP Observation Register 0, offset: 0x2 */
52304   __I  uint8_t A_HDCPOBS1;                         /**< HDCP Observation Register 1, offset: 0x3 */
52305   __I  uint8_t A_HDCPOBS2;                         /**< HDCP Observation Register 2, offset: 0x4 */
52306   __I  uint8_t A_HDCPOBS3;                         /**< HDCP Observation Register 3, offset: 0x5 */
52307   __O  uint8_t A_APIINTCLR;                        /**< HDCP Interrupt Clear Register Write only register, active high and auto cleared, cleans the respective interruption in the interrupt status register., offset: 0x6 */
52308   __I  uint8_t A_APIINTSTAT;                       /**< HDCP Interrupt Status Register Read only register, reports the interruption which caused the activation of the interruption output pin., offset: 0x7 */
52309   __IO uint8_t A_APIINTMSK;                        /**< HDCP Interrupt Mask Register The configuration of this register mask a given setup of interruption, disabling them from generating interruption pulses in the interruption output pin., offset: 0x8 */
52310   __IO uint8_t A_VIDPOLCFG;                        /**< HDCP Video Polarity Configuration Register, offset: 0x9 */
52311   __IO uint8_t A_OESSWCFG;                         /**< HDCP OESS WOO Configuration Register Pulse width of the encryption enable (CTL3) signal in the HDCP OESS mode., offset: 0xA */
52312        uint8_t RESERVED_0[9];
52313   __I  uint8_t A_COREVERLSB;                       /**< HDCP Controller Version Register LSB Design ID number., offset: 0x14 */
52314   __I  uint8_t A_COREVERMSB;                       /**< HDCP Controller Version Register MSB Revision ID number., offset: 0x15 */
52315   __IO uint8_t A_KSVMEMCTRL;                       /**< HDCP KSV Memory Control Register The KSVCTRLupd bit is a notification flag., offset: 0x16 */
52316        uint8_t RESERVED_1[674];
52317   __IO uint8_t HDCP_REVOC_SIZE_0;                  /**< HDCP Revocation KSV List Size Register 0, offset: 0x2B9 */
52318   __IO uint8_t HDCP_REVOC_SIZE_1;                  /**< HDCP Revocation KSV List Size Register 1, offset: 0x2BA */
52319        uint8_t RESERVED_2[9541];
52320   __I  uint8_t HDCPREG_BKSV0;                      /**< HDCP KSV Status Register 0, offset: 0x2800 */
52321   __I  uint8_t HDCPREG_BKSV1;                      /**< HDCP KSV Status Register 1, offset: 0x2801 */
52322   __I  uint8_t HDCPREG_BKSV2;                      /**< HDCP KSV Status Register 2, offset: 0x2802 */
52323   __I  uint8_t HDCPREG_BKSV3;                      /**< HDCP KSV Status Register 3, offset: 0x2803 */
52324   __I  uint8_t HDCPREG_BKSV4;                      /**< HDCP KSV Status Register 4, offset: 0x2804 */
52325   __IO uint8_t HDCPREG_ANCONF;                     /**< HDCP AN Bypass Control Register, offset: 0x2805 */
52326   __IO uint8_t HDCPREG_AN0;                        /**< HDCP Forced AN Register 0, offset: 0x2806 */
52327   __IO uint8_t HDCPREG_AN1;                        /**< HDCP Forced AN Register 1, offset: 0x2807 */
52328   __IO uint8_t HDCPREG_AN2;                        /**< HDCP forced AN Register 2, offset: 0x2808 */
52329   __IO uint8_t HDCPREG_AN3;                        /**< HDCP Forced AN Register 3, offset: 0x2809 */
52330   __IO uint8_t HDCPREG_AN4;                        /**< HDCP Forced AN Register 4, offset: 0x280A */
52331   __IO uint8_t HDCPREG_AN5;                        /**< HDCP Forced AN Register 5, offset: 0x280B */
52332   __IO uint8_t HDCPREG_AN6;                        /**< HDCP Forced AN Register 6, offset: 0x280C */
52333   __IO uint8_t HDCPREG_AN7;                        /**< HDCP Forced AN Register 7, offset: 0x280D */
52334   __IO uint8_t HDCPREG_RMLCTL;                     /**< HDCP Encrypted Device Private Keys Control Register This register is the control register for the software programmable encrypted DPK embedded storage feature., offset: 0x280E */
52335   __I  uint8_t HDCPREG_RMLSTS;                     /**< HDCP Encrypted DPK Status Register The required software configuration sequence is documented in the DesignWare Cores HDMI Transmitter User Guide in the "Programming" chapter, Section 3., offset: 0x280F */
52336   __O  uint8_t HDCPREG_SEED0;                      /**< HDCP Encrypted DPK Seed Register 0 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys., offset: 0x2810 */
52337   __O  uint8_t HDCPREG_SEED1;                      /**< HDCP Encrypted DPK Seed Register 1 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys., offset: 0x2811 */
52338   __O  uint8_t HDCPREG_DPK0;                       /**< HDCP Encrypted DPK Data Register 0 This register contains an HDCP DPK byte., offset: 0x2812 */
52339   __O  uint8_t HDCPREG_DPK1;                       /**< HDCP Encrypted DPK Data Register 1 This register contains an HDCP DPK byte., offset: 0x2813 */
52340   __O  uint8_t HDCPREG_DPK2;                       /**< HDCP Encrypted DPK Data Register 2 This register contains an HDCP DPK byte., offset: 0x2814 */
52341   __O  uint8_t HDCPREG_DPK3;                       /**< HDCP Encrypted DPK Data Register 3 This register contains an HDCP DPK byte., offset: 0x2815 */
52342   __O  uint8_t HDCPREG_DPK4;                       /**< HDCP Encrypted DPK Data Register 4 This register contains an HDCP DPK byte., offset: 0x2816 */
52343   __O  uint8_t HDCPREG_DPK5;                       /**< HDCP Encrypted DPK Data Register 5 This register contains an HDCP DPK byte., offset: 0x2817 */
52344   __O  uint8_t HDCPREG_DPK6;                       /**< HDCP Encrypted DPK Data Register 6 This register contains an HDCP DPK byte., offset: 0x2818 */
52345 } HDCP_Type;
52346 
52347 /* ----------------------------------------------------------------------------
52348    -- HDCP Register Masks
52349    ---------------------------------------------------------------------------- */
52350 
52351 /*!
52352  * @addtogroup HDCP_Register_Masks HDCP Register Masks
52353  * @{
52354  */
52355 
52356 /*! @name A_HDCPCFG0 - HDCP Enable and Functional Control Configuration Register 0 */
52357 /*! @{ */
52358 
52359 #define HDCP_A_HDCPCFG0_HDMIDVI_MASK             (0x1U)
52360 #define HDCP_A_HDCPCFG0_HDMIDVI_SHIFT            (0U)
52361 /*! hdmidvi - Configures the transmitter to operate with a HDMI capable device or with a DVI device. */
52362 #define HDCP_A_HDCPCFG0_HDMIDVI(x)               (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_HDMIDVI_SHIFT)) & HDCP_A_HDCPCFG0_HDMIDVI_MASK)
52363 
52364 #define HDCP_A_HDCPCFG0_EN11FEATURE_MASK         (0x2U)
52365 #define HDCP_A_HDCPCFG0_EN11FEATURE_SHIFT        (1U)
52366 /*! en11feature - Enable the use of features 1. */
52367 #define HDCP_A_HDCPCFG0_EN11FEATURE(x)           (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_EN11FEATURE_SHIFT)) & HDCP_A_HDCPCFG0_EN11FEATURE_MASK)
52368 
52369 #define HDCP_A_HDCPCFG0_RXDETECT_MASK            (0x4U)
52370 #define HDCP_A_HDCPCFG0_RXDETECT_SHIFT           (2U)
52371 /*! rxdetect - Information that a sink device was detected connected to the HDMI port */
52372 #define HDCP_A_HDCPCFG0_RXDETECT(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_RXDETECT_SHIFT)) & HDCP_A_HDCPCFG0_RXDETECT_MASK)
52373 
52374 #define HDCP_A_HDCPCFG0_AVMUTE_MASK              (0x8U)
52375 #define HDCP_A_HDCPCFG0_AVMUTE_SHIFT             (3U)
52376 /*! avmute - This register holds the current AVMUTE state of the DWC_hdmi_tx controller, as expected
52377  *    to be perceived by the connected HDMI/HDCP sink device.
52378  */
52379 #define HDCP_A_HDCPCFG0_AVMUTE(x)                (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_AVMUTE_SHIFT)) & HDCP_A_HDCPCFG0_AVMUTE_MASK)
52380 
52381 #define HDCP_A_HDCPCFG0_SYNCRICHECK_MASK         (0x10U)
52382 #define HDCP_A_HDCPCFG0_SYNCRICHECK_SHIFT        (4U)
52383 /*! syncricheck - Configures if the Ri check should be done at every 2s even or synchronously to every 128 encrypted frame. */
52384 #define HDCP_A_HDCPCFG0_SYNCRICHECK(x)           (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_SYNCRICHECK_SHIFT)) & HDCP_A_HDCPCFG0_SYNCRICHECK_MASK)
52385 
52386 #define HDCP_A_HDCPCFG0_BYPENCRYPTION_MASK       (0x20U)
52387 #define HDCP_A_HDCPCFG0_BYPENCRYPTION_SHIFT      (5U)
52388 /*! bypencryption - Bypasses all the data encryption stages */
52389 #define HDCP_A_HDCPCFG0_BYPENCRYPTION(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_BYPENCRYPTION_SHIFT)) & HDCP_A_HDCPCFG0_BYPENCRYPTION_MASK)
52390 
52391 #define HDCP_A_HDCPCFG0_I2CFASTMODE_MASK         (0x40U)
52392 #define HDCP_A_HDCPCFG0_I2CFASTMODE_SHIFT        (6U)
52393 /*! I2Cfastmode - Enable the I2C fast mode option from the transmitter's side. */
52394 #define HDCP_A_HDCPCFG0_I2CFASTMODE(x)           (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_I2CFASTMODE_SHIFT)) & HDCP_A_HDCPCFG0_I2CFASTMODE_MASK)
52395 
52396 #define HDCP_A_HDCPCFG0_ELVENA_MASK              (0x80U)
52397 #define HDCP_A_HDCPCFG0_ELVENA_SHIFT             (7U)
52398 /*! ELVena - Enables the Enhanced Link Verification from the transmitter's side */
52399 #define HDCP_A_HDCPCFG0_ELVENA(x)                (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_ELVENA_SHIFT)) & HDCP_A_HDCPCFG0_ELVENA_MASK)
52400 /*! @} */
52401 
52402 /*! @name A_HDCPCFG1 - HDCP Software Reset and Functional Control Configuration Register 1 */
52403 /*! @{ */
52404 
52405 #define HDCP_A_HDCPCFG1_SWRESET_MASK             (0x1U)
52406 #define HDCP_A_HDCPCFG1_SWRESET_SHIFT            (0U)
52407 /*! swreset - Software reset signal, active by writing a zero and auto cleared to 1 in the following cycle. */
52408 #define HDCP_A_HDCPCFG1_SWRESET(x)               (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_SWRESET_SHIFT)) & HDCP_A_HDCPCFG1_SWRESET_MASK)
52409 
52410 #define HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK   (0x2U)
52411 #define HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_SHIFT  (1U)
52412 /*! encryptiondisable - Disable encryption without losing authentication */
52413 #define HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE(x)     (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_SHIFT)) & HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK)
52414 
52415 #define HDCP_A_HDCPCFG1_PH2UPSHFTENC_MASK        (0x4U)
52416 #define HDCP_A_HDCPCFG1_PH2UPSHFTENC_SHIFT       (2U)
52417 /*! ph2upshftenc - Enables the encoding of packet header in the tmdsch0 bit[0] with cipher[2]
52418  *    instead of the tmdsch0 bit[2] Note: This bit must always be set to 1 for all PHYs (PHY GEN1, PHY
52419  *    GEN2, and non-Synopsys PHY).
52420  */
52421 #define HDCP_A_HDCPCFG1_PH2UPSHFTENC(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_PH2UPSHFTENC_SHIFT)) & HDCP_A_HDCPCFG1_PH2UPSHFTENC_MASK)
52422 
52423 #define HDCP_A_HDCPCFG1_DISSHA1CHECK_MASK        (0x8U)
52424 #define HDCP_A_HDCPCFG1_DISSHA1CHECK_SHIFT       (3U)
52425 /*! dissha1check - Disables the request to the API processor to verify the SHA1 message digest of a received KSV List */
52426 #define HDCP_A_HDCPCFG1_DISSHA1CHECK(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_DISSHA1CHECK_SHIFT)) & HDCP_A_HDCPCFG1_DISSHA1CHECK_MASK)
52427 
52428 #define HDCP_A_HDCPCFG1_HDCP_LOCK_MASK           (0x10U)
52429 #define HDCP_A_HDCPCFG1_HDCP_LOCK_SHIFT          (4U)
52430 /*! hdcp_lock - Lock the HDCP bypass and encryption disable mechanisms: - 1'b0: The default 1'b0
52431  *    value enables you to bypass HDCP through bit 5 (bypencryption) of the A_HDCPCFG0 register or to
52432  *    disable the encryption through bit 1 (encryptiondisable) of A_HDCPCFG1.
52433  */
52434 #define HDCP_A_HDCPCFG1_HDCP_LOCK(x)             (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_HDCP_LOCK_SHIFT)) & HDCP_A_HDCPCFG1_HDCP_LOCK_MASK)
52435 
52436 #define HDCP_A_HDCPCFG1_SPARE_MASK               (0xE0U)
52437 #define HDCP_A_HDCPCFG1_SPARE_SHIFT              (5U)
52438 /*! spare - Reserved as "spare" register with no associated functionality. */
52439 #define HDCP_A_HDCPCFG1_SPARE(x)                 (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_SPARE_SHIFT)) & HDCP_A_HDCPCFG1_SPARE_MASK)
52440 /*! @} */
52441 
52442 /*! @name A_HDCPOBS0 - HDCP Observation Register 0 */
52443 /*! @{ */
52444 
52445 #define HDCP_A_HDCPOBS0_HDCPENGAGED_MASK         (0x1U)
52446 #define HDCP_A_HDCPOBS0_HDCPENGAGED_SHIFT        (0U)
52447 /*! hdcpengaged - Informs that the current HDMI link has the HDCP protocol fully engaged. */
52448 #define HDCP_A_HDCPOBS0_HDCPENGAGED(x)           (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS0_HDCPENGAGED_SHIFT)) & HDCP_A_HDCPOBS0_HDCPENGAGED_MASK)
52449 
52450 #define HDCP_A_HDCPOBS0_SUBSTATEA_MASK           (0xEU)
52451 #define HDCP_A_HDCPOBS0_SUBSTATEA_SHIFT          (1U)
52452 /*! SUBSTATEA - Observability register informs in which sub-state the authentication is on. */
52453 #define HDCP_A_HDCPOBS0_SUBSTATEA(x)             (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS0_SUBSTATEA_SHIFT)) & HDCP_A_HDCPOBS0_SUBSTATEA_MASK)
52454 
52455 #define HDCP_A_HDCPOBS0_STATEA_MASK              (0xF0U)
52456 #define HDCP_A_HDCPOBS0_STATEA_SHIFT             (4U)
52457 /*! STATEA - Observability register informs in which state the authentication machine is on. */
52458 #define HDCP_A_HDCPOBS0_STATEA(x)                (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS0_STATEA_SHIFT)) & HDCP_A_HDCPOBS0_STATEA_MASK)
52459 /*! @} */
52460 
52461 /*! @name A_HDCPOBS1 - HDCP Observation Register 1 */
52462 /*! @{ */
52463 
52464 #define HDCP_A_HDCPOBS1_STATER_MASK              (0xFU)
52465 #define HDCP_A_HDCPOBS1_STATER_SHIFT             (0U)
52466 /*! STATER - Observability register informs in which state the revocation machine is on. */
52467 #define HDCP_A_HDCPOBS1_STATER(x)                (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS1_STATER_SHIFT)) & HDCP_A_HDCPOBS1_STATER_MASK)
52468 
52469 #define HDCP_A_HDCPOBS1_STATEOEG_MASK            (0x70U)
52470 #define HDCP_A_HDCPOBS1_STATEOEG_SHIFT           (4U)
52471 /*! STATEOEG - Observability register informs in which state the OESS machine is on. */
52472 #define HDCP_A_HDCPOBS1_STATEOEG(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS1_STATEOEG_SHIFT)) & HDCP_A_HDCPOBS1_STATEOEG_MASK)
52473 /*! @} */
52474 
52475 /*! @name A_HDCPOBS2 - HDCP Observation Register 2 */
52476 /*! @{ */
52477 
52478 #define HDCP_A_HDCPOBS2_STATEEEG_MASK            (0x7U)
52479 #define HDCP_A_HDCPOBS2_STATEEEG_SHIFT           (0U)
52480 /*! STATEEEG - Observability register informs in which state the EESS machine is on. */
52481 #define HDCP_A_HDCPOBS2_STATEEEG(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS2_STATEEEG_SHIFT)) & HDCP_A_HDCPOBS2_STATEEEG_MASK)
52482 
52483 #define HDCP_A_HDCPOBS2_STATEE_MASK              (0x38U)
52484 #define HDCP_A_HDCPOBS2_STATEE_SHIFT             (3U)
52485 /*! STATEE - Observability register informs in which state the cipher machine is on. */
52486 #define HDCP_A_HDCPOBS2_STATEE(x)                (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS2_STATEE_SHIFT)) & HDCP_A_HDCPOBS2_STATEE_MASK)
52487 /*! @} */
52488 
52489 /*! @name A_HDCPOBS3 - HDCP Observation Register 3 */
52490 /*! @{ */
52491 
52492 #define HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_MASK (0x1U)
52493 #define HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_SHIFT (0U)
52494 /*! FAST_REAUTHENTICATION - Register read from attached sink device: Bcap(0x40) bit 0. */
52495 #define HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_SHIFT)) & HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_MASK)
52496 
52497 #define HDCP_A_HDCPOBS3_FEATURES_1_1_MASK        (0x2U)
52498 #define HDCP_A_HDCPOBS3_FEATURES_1_1_SHIFT       (1U)
52499 /*! FEATURES_1_1 - Register read from attached sink device: Bcap(0x40) bit 1. */
52500 #define HDCP_A_HDCPOBS3_FEATURES_1_1(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_FEATURES_1_1_SHIFT)) & HDCP_A_HDCPOBS3_FEATURES_1_1_MASK)
52501 
52502 #define HDCP_A_HDCPOBS3_HDMI_MODE_MASK           (0x4U)
52503 #define HDCP_A_HDCPOBS3_HDMI_MODE_SHIFT          (2U)
52504 /*! HDMI_MODE - Register read from attached sink device: Bstatus(0x41) bit 12. */
52505 #define HDCP_A_HDCPOBS3_HDMI_MODE(x)             (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_HDMI_MODE_SHIFT)) & HDCP_A_HDCPOBS3_HDMI_MODE_MASK)
52506 
52507 #define HDCP_A_HDCPOBS3_HDMI_RESERVED_2_MASK     (0x8U)
52508 #define HDCP_A_HDCPOBS3_HDMI_RESERVED_2_SHIFT    (3U)
52509 /*! HDMI_RESERVED_2 - Register read from attached sink device: Bstatus(0x41) bit 13. */
52510 #define HDCP_A_HDCPOBS3_HDMI_RESERVED_2(x)       (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_HDMI_RESERVED_2_SHIFT)) & HDCP_A_HDCPOBS3_HDMI_RESERVED_2_MASK)
52511 
52512 #define HDCP_A_HDCPOBS3_FAST_I2C_MASK            (0x10U)
52513 #define HDCP_A_HDCPOBS3_FAST_I2C_SHIFT           (4U)
52514 /*! FAST_I2C - Register read from attached sink device: Bcap(0x40) bit 4. */
52515 #define HDCP_A_HDCPOBS3_FAST_I2C(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_FAST_I2C_SHIFT)) & HDCP_A_HDCPOBS3_FAST_I2C_MASK)
52516 
52517 #define HDCP_A_HDCPOBS3_KSV_FIFO_READY_MASK      (0x20U)
52518 #define HDCP_A_HDCPOBS3_KSV_FIFO_READY_SHIFT     (5U)
52519 /*! KSV_FIFO_READY - Register read from attached sink device: Bcap(0x40) bit 5. */
52520 #define HDCP_A_HDCPOBS3_KSV_FIFO_READY(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_KSV_FIFO_READY_SHIFT)) & HDCP_A_HDCPOBS3_KSV_FIFO_READY_MASK)
52521 
52522 #define HDCP_A_HDCPOBS3_REPEATER_MASK            (0x40U)
52523 #define HDCP_A_HDCPOBS3_REPEATER_SHIFT           (6U)
52524 /*! REPEATER - Register read from attached sink device: Bcap(0x40) bit 6. */
52525 #define HDCP_A_HDCPOBS3_REPEATER(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_REPEATER_SHIFT)) & HDCP_A_HDCPOBS3_REPEATER_MASK)
52526 
52527 #define HDCP_A_HDCPOBS3_HDMI_RESERVED_1_MASK     (0x80U)
52528 #define HDCP_A_HDCPOBS3_HDMI_RESERVED_1_SHIFT    (7U)
52529 /*! HDMI_RESERVED_1 - Register read from attached sink device: Bcap(0x40) bit 7. */
52530 #define HDCP_A_HDCPOBS3_HDMI_RESERVED_1(x)       (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_HDMI_RESERVED_1_SHIFT)) & HDCP_A_HDCPOBS3_HDMI_RESERVED_1_MASK)
52531 /*! @} */
52532 
52533 /*! @name A_APIINTCLR - HDCP Interrupt Clear Register Write only register, active high and auto cleared, cleans the respective interruption in the interrupt status register. */
52534 /*! @{ */
52535 
52536 #define HDCP_A_APIINTCLR_KSVACCESSINT_MASK       (0x1U)
52537 #define HDCP_A_APIINTCLR_KSVACCESSINT_SHIFT      (0U)
52538 /*! KSVaccessint - Clears the interruption related to KSV memory access grant for Read-Write access. */
52539 #define HDCP_A_APIINTCLR_KSVACCESSINT(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_KSVACCESSINT_SHIFT)) & HDCP_A_APIINTCLR_KSVACCESSINT_MASK)
52540 
52541 #define HDCP_A_APIINTCLR_KEEPOUTERRORINT_MASK    (0x4U)
52542 #define HDCP_A_APIINTCLR_KEEPOUTERRORINT_SHIFT   (2U)
52543 /*! Keepouterrorint - Clears the interruption related to keep out window error. */
52544 #define HDCP_A_APIINTCLR_KEEPOUTERRORINT(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_KEEPOUTERRORINT_SHIFT)) & HDCP_A_APIINTCLR_KEEPOUTERRORINT_MASK)
52545 
52546 #define HDCP_A_APIINTCLR_LOSTARBITRATION_MASK    (0x8U)
52547 #define HDCP_A_APIINTCLR_LOSTARBITRATION_SHIFT   (3U)
52548 /*! Lostarbitration - Clears the interruption related to I2C arbitration lost. */
52549 #define HDCP_A_APIINTCLR_LOSTARBITRATION(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_LOSTARBITRATION_SHIFT)) & HDCP_A_APIINTCLR_LOSTARBITRATION_MASK)
52550 
52551 #define HDCP_A_APIINTCLR_I2CNACK_MASK            (0x10U)
52552 #define HDCP_A_APIINTCLR_I2CNACK_SHIFT           (4U)
52553 /*! I2Cnack - Clears the interruption related to I2C NACK reception. */
52554 #define HDCP_A_APIINTCLR_I2CNACK(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_I2CNACK_SHIFT)) & HDCP_A_APIINTCLR_I2CNACK_MASK)
52555 
52556 #define HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_MASK (0x20U)
52557 #define HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_SHIFT (5U)
52558 /*! KSVsha1calcdoneint - Clears the interruption related to SHA1 verification has been done */
52559 #define HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT(x)   (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_SHIFT)) & HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_MASK)
52560 
52561 #define HDCP_A_APIINTCLR_HDCP_FAILED_MASK        (0x40U)
52562 #define HDCP_A_APIINTCLR_HDCP_FAILED_SHIFT       (6U)
52563 /*! HDCP_failed - Clears the interruption related to HDCP authentication process failed. */
52564 #define HDCP_A_APIINTCLR_HDCP_FAILED(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_HDCP_FAILED_SHIFT)) & HDCP_A_APIINTCLR_HDCP_FAILED_MASK)
52565 
52566 #define HDCP_A_APIINTCLR_HDCP_ENGAGED_MASK       (0x80U)
52567 #define HDCP_A_APIINTCLR_HDCP_ENGAGED_SHIFT      (7U)
52568 /*! HDCP_engaged - Clears the interruption related to HDCP authentication process successful. */
52569 #define HDCP_A_APIINTCLR_HDCP_ENGAGED(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_HDCP_ENGAGED_SHIFT)) & HDCP_A_APIINTCLR_HDCP_ENGAGED_MASK)
52570 /*! @} */
52571 
52572 /*! @name A_APIINTSTAT - HDCP Interrupt Status Register Read only register, reports the interruption which caused the activation of the interruption output pin. */
52573 /*! @{ */
52574 
52575 #define HDCP_A_APIINTSTAT_KSVACCESSINT_MASK      (0x1U)
52576 #define HDCP_A_APIINTSTAT_KSVACCESSINT_SHIFT     (0U)
52577 /*! KSVaccessint - Notifies that the KSV memory access as been guaranteed for Read-Write access. */
52578 #define HDCP_A_APIINTSTAT_KSVACCESSINT(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_KSVACCESSINT_SHIFT)) & HDCP_A_APIINTSTAT_KSVACCESSINT_MASK)
52579 
52580 #define HDCP_A_APIINTSTAT_KEEPOUTERRORINT_MASK   (0x4U)
52581 #define HDCP_A_APIINTSTAT_KEEPOUTERRORINT_SHIFT  (2U)
52582 /*! Keepouterrorint - Notifies that during the keep out window, the ctlout[3:0] bus was used besides control period. */
52583 #define HDCP_A_APIINTSTAT_KEEPOUTERRORINT(x)     (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_KEEPOUTERRORINT_SHIFT)) & HDCP_A_APIINTSTAT_KEEPOUTERRORINT_MASK)
52584 
52585 #define HDCP_A_APIINTSTAT_LOSTARBITRATION_MASK   (0x8U)
52586 #define HDCP_A_APIINTSTAT_LOSTARBITRATION_SHIFT  (3U)
52587 /*! Lostarbitration - Notifies that the I2C lost the arbitration to communicate. */
52588 #define HDCP_A_APIINTSTAT_LOSTARBITRATION(x)     (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_LOSTARBITRATION_SHIFT)) & HDCP_A_APIINTSTAT_LOSTARBITRATION_MASK)
52589 
52590 #define HDCP_A_APIINTSTAT_I2CNACK_MASK           (0x10U)
52591 #define HDCP_A_APIINTSTAT_I2CNACK_SHIFT          (4U)
52592 /*! I2Cnack - Notifies that the I2C received a NACK from slave device. */
52593 #define HDCP_A_APIINTSTAT_I2CNACK(x)             (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_I2CNACK_SHIFT)) & HDCP_A_APIINTSTAT_I2CNACK_MASK)
52594 
52595 #define HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_MASK (0x20U)
52596 #define HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_SHIFT (5U)
52597 /*! KSVsha1calcdoneint - Notifies that the HDCP13TCTRL block SHA1 verification has been done. */
52598 #define HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT(x)  (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_SHIFT)) & HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_MASK)
52599 
52600 #define HDCP_A_APIINTSTAT_HDCP_FAILED_MASK       (0x40U)
52601 #define HDCP_A_APIINTSTAT_HDCP_FAILED_SHIFT      (6U)
52602 /*! HDCP_failed - Notifies that the HDCP authentication process was failed. */
52603 #define HDCP_A_APIINTSTAT_HDCP_FAILED(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_HDCP_FAILED_SHIFT)) & HDCP_A_APIINTSTAT_HDCP_FAILED_MASK)
52604 
52605 #define HDCP_A_APIINTSTAT_HDCP_ENGAGED_MASK      (0x80U)
52606 #define HDCP_A_APIINTSTAT_HDCP_ENGAGED_SHIFT     (7U)
52607 /*! HDCP_engaged - Notifies that the HDCP authentication process was successful */
52608 #define HDCP_A_APIINTSTAT_HDCP_ENGAGED(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_HDCP_ENGAGED_SHIFT)) & HDCP_A_APIINTSTAT_HDCP_ENGAGED_MASK)
52609 /*! @} */
52610 
52611 /*! @name A_APIINTMSK - HDCP Interrupt Mask Register The configuration of this register mask a given setup of interruption, disabling them from generating interruption pulses in the interruption output pin. */
52612 /*! @{ */
52613 
52614 #define HDCP_A_APIINTMSK_KSVACCESSINT_MASK       (0x1U)
52615 #define HDCP_A_APIINTMSK_KSVACCESSINT_SHIFT      (0U)
52616 /*! KSVaccessint - Masks the interruption related to KSV memory access grant for Read-Write access. */
52617 #define HDCP_A_APIINTMSK_KSVACCESSINT(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_KSVACCESSINT_SHIFT)) & HDCP_A_APIINTMSK_KSVACCESSINT_MASK)
52618 
52619 #define HDCP_A_APIINTMSK_SPARE_MASK              (0x2U)
52620 #define HDCP_A_APIINTMSK_SPARE_SHIFT             (1U)
52621 /*! spare - Reserved as "spare" register with no associated functionality. */
52622 #define HDCP_A_APIINTMSK_SPARE(x)                (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_SPARE_SHIFT)) & HDCP_A_APIINTMSK_SPARE_MASK)
52623 
52624 #define HDCP_A_APIINTMSK_KEEPOUTERRORINT_MASK    (0x4U)
52625 #define HDCP_A_APIINTMSK_KEEPOUTERRORINT_SHIFT   (2U)
52626 /*! Keepouterrorint - Masks the interruption related to keep out window error. */
52627 #define HDCP_A_APIINTMSK_KEEPOUTERRORINT(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_KEEPOUTERRORINT_SHIFT)) & HDCP_A_APIINTMSK_KEEPOUTERRORINT_MASK)
52628 
52629 #define HDCP_A_APIINTMSK_LOSTARBITRATION_MASK    (0x8U)
52630 #define HDCP_A_APIINTMSK_LOSTARBITRATION_SHIFT   (3U)
52631 /*! Lostarbitration - Masks the interruption related to I2C arbitration lost. */
52632 #define HDCP_A_APIINTMSK_LOSTARBITRATION(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_LOSTARBITRATION_SHIFT)) & HDCP_A_APIINTMSK_LOSTARBITRATION_MASK)
52633 
52634 #define HDCP_A_APIINTMSK_I2CNACK_MASK            (0x10U)
52635 #define HDCP_A_APIINTMSK_I2CNACK_SHIFT           (4U)
52636 /*! I2Cnack - Masks the interruption related to I2C NACK reception. */
52637 #define HDCP_A_APIINTMSK_I2CNACK(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_I2CNACK_SHIFT)) & HDCP_A_APIINTMSK_I2CNACK_MASK)
52638 
52639 #define HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_MASK (0x20U)
52640 #define HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_SHIFT (5U)
52641 /*! KSVsha1calcdoneint - Masks the interruption related to SHA1 verification has been done */
52642 #define HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT(x)   (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_SHIFT)) & HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_MASK)
52643 
52644 #define HDCP_A_APIINTMSK_HDCP_FAILED_MASK        (0x40U)
52645 #define HDCP_A_APIINTMSK_HDCP_FAILED_SHIFT       (6U)
52646 /*! HDCP_failed - Masks the interruption related to HDCP authentication process failed. */
52647 #define HDCP_A_APIINTMSK_HDCP_FAILED(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_HDCP_FAILED_SHIFT)) & HDCP_A_APIINTMSK_HDCP_FAILED_MASK)
52648 
52649 #define HDCP_A_APIINTMSK_HDCP_ENGAGED_MASK       (0x80U)
52650 #define HDCP_A_APIINTMSK_HDCP_ENGAGED_SHIFT      (7U)
52651 /*! HDCP_engaged - Masks the interruption related to HDCP authentication process successful. */
52652 #define HDCP_A_APIINTMSK_HDCP_ENGAGED(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_HDCP_ENGAGED_SHIFT)) & HDCP_A_APIINTMSK_HDCP_ENGAGED_MASK)
52653 /*! @} */
52654 
52655 /*! @name A_VIDPOLCFG - HDCP Video Polarity Configuration Register */
52656 /*! @{ */
52657 
52658 #define HDCP_A_VIDPOLCFG_SPARE_1_MASK            (0x1U)
52659 #define HDCP_A_VIDPOLCFG_SPARE_1_SHIFT           (0U)
52660 /*! spare_1 - Reserved as "spare" bit with no associated functionality. */
52661 #define HDCP_A_VIDPOLCFG_SPARE_1(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_SPARE_1_SHIFT)) & HDCP_A_VIDPOLCFG_SPARE_1_MASK)
52662 
52663 #define HDCP_A_VIDPOLCFG_HSYNCPOL_MASK           (0x2U)
52664 #define HDCP_A_VIDPOLCFG_HSYNCPOL_SHIFT          (1U)
52665 /*! hsyncpol - Configuration of the video Horizontal synchronism polarity. */
52666 #define HDCP_A_VIDPOLCFG_HSYNCPOL(x)             (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_HSYNCPOL_SHIFT)) & HDCP_A_VIDPOLCFG_HSYNCPOL_MASK)
52667 
52668 #define HDCP_A_VIDPOLCFG_SPARE_2_MASK            (0x4U)
52669 #define HDCP_A_VIDPOLCFG_SPARE_2_SHIFT           (2U)
52670 /*! spare_2 - Reserved as "spare" bit with no associated functionality. */
52671 #define HDCP_A_VIDPOLCFG_SPARE_2(x)              (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_SPARE_2_SHIFT)) & HDCP_A_VIDPOLCFG_SPARE_2_MASK)
52672 
52673 #define HDCP_A_VIDPOLCFG_VSYNCPOL_MASK           (0x8U)
52674 #define HDCP_A_VIDPOLCFG_VSYNCPOL_SHIFT          (3U)
52675 /*! vsyncpol - Configuration of the video Vertical synchronism polarity */
52676 #define HDCP_A_VIDPOLCFG_VSYNCPOL(x)             (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_VSYNCPOL_SHIFT)) & HDCP_A_VIDPOLCFG_VSYNCPOL_MASK)
52677 
52678 #define HDCP_A_VIDPOLCFG_DATAENPOL_MASK          (0x10U)
52679 #define HDCP_A_VIDPOLCFG_DATAENPOL_SHIFT         (4U)
52680 /*! dataenpol - Configuration of the video data enable polarity */
52681 #define HDCP_A_VIDPOLCFG_DATAENPOL(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_DATAENPOL_SHIFT)) & HDCP_A_VIDPOLCFG_DATAENPOL_MASK)
52682 
52683 #define HDCP_A_VIDPOLCFG_UNENCRYPTCONF_MASK      (0x60U)
52684 #define HDCP_A_VIDPOLCFG_UNENCRYPTCONF_SHIFT     (5U)
52685 /*! unencryptconf - Configuration of the color sent when sending unencrypted video data For a
52686  *    complete table showing the color results (RGB), refer to the "Color Configuration When Sending
52687  *    Unencrypted Video Data" figure in Chapter 2, "Functional Description.
52688  */
52689 #define HDCP_A_VIDPOLCFG_UNENCRYPTCONF(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_UNENCRYPTCONF_SHIFT)) & HDCP_A_VIDPOLCFG_UNENCRYPTCONF_MASK)
52690 /*! @} */
52691 
52692 /*! @name A_OESSWCFG - HDCP OESS WOO Configuration Register Pulse width of the encryption enable (CTL3) signal in the HDCP OESS mode. */
52693 /*! @{ */
52694 
52695 #define HDCP_A_OESSWCFG_A_OESSWCFG_MASK          (0xFFU)
52696 #define HDCP_A_OESSWCFG_A_OESSWCFG_SHIFT         (0U)
52697 /*! a_oesswcfg - HDCP OESS WOO Configuration Register */
52698 #define HDCP_A_OESSWCFG_A_OESSWCFG(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_A_OESSWCFG_A_OESSWCFG_SHIFT)) & HDCP_A_OESSWCFG_A_OESSWCFG_MASK)
52699 /*! @} */
52700 
52701 /*! @name A_COREVERLSB - HDCP Controller Version Register LSB Design ID number. */
52702 /*! @{ */
52703 
52704 #define HDCP_A_COREVERLSB_A_COREVERLSB_MASK      (0xFFU)
52705 #define HDCP_A_COREVERLSB_A_COREVERLSB_SHIFT     (0U)
52706 /*! a_coreverlsb - HDCP Controller Version Register LSB */
52707 #define HDCP_A_COREVERLSB_A_COREVERLSB(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_COREVERLSB_A_COREVERLSB_SHIFT)) & HDCP_A_COREVERLSB_A_COREVERLSB_MASK)
52708 /*! @} */
52709 
52710 /*! @name A_COREVERMSB - HDCP Controller Version Register MSB Revision ID number. */
52711 /*! @{ */
52712 
52713 #define HDCP_A_COREVERMSB_A_COREVERMSB_MASK      (0xFFU)
52714 #define HDCP_A_COREVERMSB_A_COREVERMSB_SHIFT     (0U)
52715 /*! a_corevermsb - HDCP Controller Version Register MSB */
52716 #define HDCP_A_COREVERMSB_A_COREVERMSB(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_COREVERMSB_A_COREVERMSB_SHIFT)) & HDCP_A_COREVERMSB_A_COREVERMSB_MASK)
52717 /*! @} */
52718 
52719 /*! @name A_KSVMEMCTRL - HDCP KSV Memory Control Register The KSVCTRLupd bit is a notification flag. */
52720 /*! @{ */
52721 
52722 #define HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_MASK     (0x1U)
52723 #define HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_SHIFT    (0U)
52724 /*! KSVMEMrequest - Request access to the KSV memory; must be de-asserted after the access is completed by the system. */
52725 #define HDCP_A_KSVMEMCTRL_KSVMEMREQUEST(x)       (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_MASK)
52726 
52727 #define HDCP_A_KSVMEMCTRL_KSVMEMACCESS_MASK      (0x2U)
52728 #define HDCP_A_KSVMEMCTRL_KSVMEMACCESS_SHIFT     (1U)
52729 /*! KSVMEMaccess - Notification that the KSV memory access as been guaranteed. */
52730 #define HDCP_A_KSVMEMCTRL_KSVMEMACCESS(x)        (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVMEMACCESS_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVMEMACCESS_MASK)
52731 
52732 #define HDCP_A_KSVMEMCTRL_KSVCTRLUPD_MASK        (0x4U)
52733 #define HDCP_A_KSVMEMCTRL_KSVCTRLUPD_SHIFT       (2U)
52734 /*! KSVCTRLupd - Set to inform that the KSV list in memory has been analyzed and the response to the
52735  *    Message Digest has been updated if on configurations on software SHA-1 calculation.
52736  */
52737 #define HDCP_A_KSVMEMCTRL_KSVCTRLUPD(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVCTRLUPD_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVCTRLUPD_MASK)
52738 
52739 #define HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_MASK     (0x10U)
52740 #define HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_SHIFT    (4U)
52741 /*! KSVsha1status - Notification whether the KSV list message digest is correct from the controller:
52742  *    1'b1 if digest message verification failed 1'b0 if digest message verification succeeded
52743  */
52744 #define HDCP_A_KSVMEMCTRL_KSVSHA1STATUS(x)       (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_MASK)
52745 /*! @} */
52746 
52747 /*! @name HDCP_REVOC_SIZE_0 - HDCP Revocation KSV List Size Register 0 */
52748 /*! @{ */
52749 
52750 #define HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_MASK (0xFFU)
52751 #define HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_SHIFT (0U)
52752 /*! hdcp_revoc_size_0 - Register containing the LSB of KSV list size (ksv_list_size[7:0]). */
52753 #define HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_SHIFT)) & HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_MASK)
52754 /*! @} */
52755 
52756 /*! @name HDCP_REVOC_SIZE_1 - HDCP Revocation KSV List Size Register 1 */
52757 /*! @{ */
52758 
52759 #define HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_MASK (0xFFU)
52760 #define HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_SHIFT (0U)
52761 /*! hdcp_revoc_size_1 - Register containing the MSB of KSV list size (ksv_list_size[15:8]). */
52762 #define HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_SHIFT)) & HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_MASK)
52763 /*! @} */
52764 
52765 /*! @name HDCPREG_BKSV0 - HDCP KSV Status Register 0 */
52766 /*! @{ */
52767 
52768 #define HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_MASK    (0xFFU)
52769 #define HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_SHIFT   (0U)
52770 /*! hdcpreg_bksv0 - Contains the value of BKSV[7:0]. */
52771 #define HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_SHIFT)) & HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_MASK)
52772 /*! @} */
52773 
52774 /*! @name HDCPREG_BKSV1 - HDCP KSV Status Register 1 */
52775 /*! @{ */
52776 
52777 #define HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_MASK    (0xFFU)
52778 #define HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_SHIFT   (0U)
52779 /*! hdcpreg_bksv1 - Contains the value of BKSV[15:8]. */
52780 #define HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_SHIFT)) & HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_MASK)
52781 /*! @} */
52782 
52783 /*! @name HDCPREG_BKSV2 - HDCP KSV Status Register 2 */
52784 /*! @{ */
52785 
52786 #define HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_MASK    (0xFFU)
52787 #define HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_SHIFT   (0U)
52788 /*! hdcpreg_bksv2 - Contains the value of BKSV[23:16]. */
52789 #define HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_SHIFT)) & HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_MASK)
52790 /*! @} */
52791 
52792 /*! @name HDCPREG_BKSV3 - HDCP KSV Status Register 3 */
52793 /*! @{ */
52794 
52795 #define HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_MASK    (0xFFU)
52796 #define HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_SHIFT   (0U)
52797 /*! hdcpreg_bksv3 - Contains the value of BKSV[31:24]. */
52798 #define HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_SHIFT)) & HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_MASK)
52799 /*! @} */
52800 
52801 /*! @name HDCPREG_BKSV4 - HDCP KSV Status Register 4 */
52802 /*! @{ */
52803 
52804 #define HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_MASK    (0xFFU)
52805 #define HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_SHIFT   (0U)
52806 /*! hdcpreg_bksv4 - Contains the value of BKSV[39:32]. */
52807 #define HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_SHIFT)) & HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_MASK)
52808 /*! @} */
52809 
52810 /*! @name HDCPREG_ANCONF - HDCP AN Bypass Control Register */
52811 /*! @{ */
52812 
52813 #define HDCP_HDCPREG_ANCONF_OANBYPASS_MASK       (0x1U)
52814 #define HDCP_HDCPREG_ANCONF_OANBYPASS_SHIFT      (0U)
52815 /*! oanbypass - - When oanbypass=1, the value of AN used in the HDCP engine comes from the hdcpreg_an0 to hdcpreg_an7 registers. */
52816 #define HDCP_HDCPREG_ANCONF_OANBYPASS(x)         (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_ANCONF_OANBYPASS_SHIFT)) & HDCP_HDCPREG_ANCONF_OANBYPASS_MASK)
52817 /*! @} */
52818 
52819 /*! @name HDCPREG_AN0 - HDCP Forced AN Register 0 */
52820 /*! @{ */
52821 
52822 #define HDCP_HDCPREG_AN0_HDCPREG_AN0_MASK        (0xFFU)
52823 #define HDCP_HDCPREG_AN0_HDCPREG_AN0_SHIFT       (0U)
52824 /*! hdcpreg_an0 - Contains the value of AN[7:0] */
52825 #define HDCP_HDCPREG_AN0_HDCPREG_AN0(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN0_HDCPREG_AN0_SHIFT)) & HDCP_HDCPREG_AN0_HDCPREG_AN0_MASK)
52826 /*! @} */
52827 
52828 /*! @name HDCPREG_AN1 - HDCP Forced AN Register 1 */
52829 /*! @{ */
52830 
52831 #define HDCP_HDCPREG_AN1_HDCPREG_AN1_MASK        (0xFFU)
52832 #define HDCP_HDCPREG_AN1_HDCPREG_AN1_SHIFT       (0U)
52833 /*! hdcpreg_an1 - Contains the value of AN[15:8] */
52834 #define HDCP_HDCPREG_AN1_HDCPREG_AN1(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN1_HDCPREG_AN1_SHIFT)) & HDCP_HDCPREG_AN1_HDCPREG_AN1_MASK)
52835 /*! @} */
52836 
52837 /*! @name HDCPREG_AN2 - HDCP forced AN Register 2 */
52838 /*! @{ */
52839 
52840 #define HDCP_HDCPREG_AN2_HDCPREG_AN2_MASK        (0xFFU)
52841 #define HDCP_HDCPREG_AN2_HDCPREG_AN2_SHIFT       (0U)
52842 /*! hdcpreg_an2 - Contains the value of AN[23:16] */
52843 #define HDCP_HDCPREG_AN2_HDCPREG_AN2(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN2_HDCPREG_AN2_SHIFT)) & HDCP_HDCPREG_AN2_HDCPREG_AN2_MASK)
52844 /*! @} */
52845 
52846 /*! @name HDCPREG_AN3 - HDCP Forced AN Register 3 */
52847 /*! @{ */
52848 
52849 #define HDCP_HDCPREG_AN3_HDCPREG_AN3_MASK        (0xFFU)
52850 #define HDCP_HDCPREG_AN3_HDCPREG_AN3_SHIFT       (0U)
52851 /*! hdcpreg_an3 - Contains the value of AN[31:24] */
52852 #define HDCP_HDCPREG_AN3_HDCPREG_AN3(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN3_HDCPREG_AN3_SHIFT)) & HDCP_HDCPREG_AN3_HDCPREG_AN3_MASK)
52853 /*! @} */
52854 
52855 /*! @name HDCPREG_AN4 - HDCP Forced AN Register 4 */
52856 /*! @{ */
52857 
52858 #define HDCP_HDCPREG_AN4_HDCPREG_AN4_MASK        (0xFFU)
52859 #define HDCP_HDCPREG_AN4_HDCPREG_AN4_SHIFT       (0U)
52860 /*! hdcpreg_an4 - Contains the value of AN[39:32] */
52861 #define HDCP_HDCPREG_AN4_HDCPREG_AN4(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN4_HDCPREG_AN4_SHIFT)) & HDCP_HDCPREG_AN4_HDCPREG_AN4_MASK)
52862 /*! @} */
52863 
52864 /*! @name HDCPREG_AN5 - HDCP Forced AN Register 5 */
52865 /*! @{ */
52866 
52867 #define HDCP_HDCPREG_AN5_HDCPREG_AN5_MASK        (0xFFU)
52868 #define HDCP_HDCPREG_AN5_HDCPREG_AN5_SHIFT       (0U)
52869 /*! hdcpreg_an5 - Contains the value of AN[47:40] */
52870 #define HDCP_HDCPREG_AN5_HDCPREG_AN5(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN5_HDCPREG_AN5_SHIFT)) & HDCP_HDCPREG_AN5_HDCPREG_AN5_MASK)
52871 /*! @} */
52872 
52873 /*! @name HDCPREG_AN6 - HDCP Forced AN Register 6 */
52874 /*! @{ */
52875 
52876 #define HDCP_HDCPREG_AN6_HDCPREG_AN6_MASK        (0xFFU)
52877 #define HDCP_HDCPREG_AN6_HDCPREG_AN6_SHIFT       (0U)
52878 /*! hdcpreg_an6 - Contains the value of AN[55:48] */
52879 #define HDCP_HDCPREG_AN6_HDCPREG_AN6(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN6_HDCPREG_AN6_SHIFT)) & HDCP_HDCPREG_AN6_HDCPREG_AN6_MASK)
52880 /*! @} */
52881 
52882 /*! @name HDCPREG_AN7 - HDCP Forced AN Register 7 */
52883 /*! @{ */
52884 
52885 #define HDCP_HDCPREG_AN7_HDCPREG_AN7_MASK        (0xFFU)
52886 #define HDCP_HDCPREG_AN7_HDCPREG_AN7_SHIFT       (0U)
52887 /*! hdcpreg_an7 - Contains the value of BKSV[63:56] */
52888 #define HDCP_HDCPREG_AN7_HDCPREG_AN7(x)          (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN7_HDCPREG_AN7_SHIFT)) & HDCP_HDCPREG_AN7_HDCPREG_AN7_MASK)
52889 /*! @} */
52890 
52891 /*! @name HDCPREG_RMLCTL - HDCP Encrypted Device Private Keys Control Register This register is the control register for the software programmable encrypted DPK embedded storage feature. */
52892 /*! @{ */
52893 
52894 #define HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_MASK (0x1U)
52895 #define HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_SHIFT (0U)
52896 /*! odpk_decrypt_enable - When set (1'b1), this bit activates the decryption of the Device Private keys. */
52897 #define HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_SHIFT)) & HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_MASK)
52898 /*! @} */
52899 
52900 /*! @name HDCPREG_RMLSTS - HDCP Encrypted DPK Status Register The required software configuration sequence is documented in the DesignWare Cores HDMI Transmitter User Guide in the "Programming" chapter, Section 3. */
52901 /*! @{ */
52902 
52903 #define HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_MASK (0x3FU)
52904 #define HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_SHIFT (0U)
52905 /*! idpk_data_index - Current Device Private Key being written plus one. */
52906 #define HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX(x)   (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_SHIFT)) & HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_MASK)
52907 
52908 #define HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_MASK  (0x40U)
52909 #define HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_SHIFT (6U)
52910 /*! idpk_wr_ok_sts - When high (1'b1), it indicates that a DPK write is allowed. */
52911 #define HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS(x)    (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_SHIFT)) & HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_MASK)
52912 /*! @} */
52913 
52914 /*! @name HDCPREG_SEED0 - HDCP Encrypted DPK Seed Register 0 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys. */
52915 /*! @{ */
52916 
52917 #define HDCP_HDCPREG_SEED0_HDCPREG_SEED0_MASK    (0xFFU)
52918 #define HDCP_HDCPREG_SEED0_HDCPREG_SEED0_SHIFT   (0U)
52919 /*! hdcpreg_seed0 - Least significant byte of the decryption seed value (dpk_decrypt_seed[7:0]). */
52920 #define HDCP_HDCPREG_SEED0_HDCPREG_SEED0(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_SEED0_HDCPREG_SEED0_SHIFT)) & HDCP_HDCPREG_SEED0_HDCPREG_SEED0_MASK)
52921 /*! @} */
52922 
52923 /*! @name HDCPREG_SEED1 - HDCP Encrypted DPK Seed Register 1 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys. */
52924 /*! @{ */
52925 
52926 #define HDCP_HDCPREG_SEED1_HDCPREG_SEED1_MASK    (0xFFU)
52927 #define HDCP_HDCPREG_SEED1_HDCPREG_SEED1_SHIFT   (0U)
52928 /*! hdcpreg_seed1 - Most significant byte of the decryption seed value (dpk_decrypt_seed[15:8]). */
52929 #define HDCP_HDCPREG_SEED1_HDCPREG_SEED1(x)      (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_SEED1_HDCPREG_SEED1_SHIFT)) & HDCP_HDCPREG_SEED1_HDCPREG_SEED1_MASK)
52930 /*! @} */
52931 
52932 /*! @name HDCPREG_DPK0 - HDCP Encrypted DPK Data Register 0 This register contains an HDCP DPK byte. */
52933 /*! @{ */
52934 
52935 #define HDCP_HDCPREG_DPK0_DPK_DATA_MASK          (0xFFU)
52936 #define HDCP_HDCPREG_DPK0_DPK_DATA_SHIFT         (0U)
52937 /*! dpk_data - Byte of the encrypted DPK value. */
52938 #define HDCP_HDCPREG_DPK0_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK0_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK0_DPK_DATA_MASK)
52939 /*! @} */
52940 
52941 /*! @name HDCPREG_DPK1 - HDCP Encrypted DPK Data Register 1 This register contains an HDCP DPK byte. */
52942 /*! @{ */
52943 
52944 #define HDCP_HDCPREG_DPK1_DPK_DATA_MASK          (0xFFU)
52945 #define HDCP_HDCPREG_DPK1_DPK_DATA_SHIFT         (0U)
52946 /*! dpk_data - Byte of the encrypted DPK value. */
52947 #define HDCP_HDCPREG_DPK1_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK1_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK1_DPK_DATA_MASK)
52948 /*! @} */
52949 
52950 /*! @name HDCPREG_DPK2 - HDCP Encrypted DPK Data Register 2 This register contains an HDCP DPK byte. */
52951 /*! @{ */
52952 
52953 #define HDCP_HDCPREG_DPK2_DPK_DATA_MASK          (0xFFU)
52954 #define HDCP_HDCPREG_DPK2_DPK_DATA_SHIFT         (0U)
52955 /*! dpk_data - Byte of the encrypted DPK value. */
52956 #define HDCP_HDCPREG_DPK2_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK2_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK2_DPK_DATA_MASK)
52957 /*! @} */
52958 
52959 /*! @name HDCPREG_DPK3 - HDCP Encrypted DPK Data Register 3 This register contains an HDCP DPK byte. */
52960 /*! @{ */
52961 
52962 #define HDCP_HDCPREG_DPK3_DPK_DATA_MASK          (0xFFU)
52963 #define HDCP_HDCPREG_DPK3_DPK_DATA_SHIFT         (0U)
52964 /*! dpk_data - Byte of the encrypted DPK value. */
52965 #define HDCP_HDCPREG_DPK3_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK3_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK3_DPK_DATA_MASK)
52966 /*! @} */
52967 
52968 /*! @name HDCPREG_DPK4 - HDCP Encrypted DPK Data Register 4 This register contains an HDCP DPK byte. */
52969 /*! @{ */
52970 
52971 #define HDCP_HDCPREG_DPK4_DPK_DATA_MASK          (0xFFU)
52972 #define HDCP_HDCPREG_DPK4_DPK_DATA_SHIFT         (0U)
52973 /*! dpk_data - Byte of the encrypted DPK value. */
52974 #define HDCP_HDCPREG_DPK4_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK4_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK4_DPK_DATA_MASK)
52975 /*! @} */
52976 
52977 /*! @name HDCPREG_DPK5 - HDCP Encrypted DPK Data Register 5 This register contains an HDCP DPK byte. */
52978 /*! @{ */
52979 
52980 #define HDCP_HDCPREG_DPK5_DPK_DATA_MASK          (0xFFU)
52981 #define HDCP_HDCPREG_DPK5_DPK_DATA_SHIFT         (0U)
52982 /*! dpk_data - Contains the value of DPK[x][47:40] */
52983 #define HDCP_HDCPREG_DPK5_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK5_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK5_DPK_DATA_MASK)
52984 /*! @} */
52985 
52986 /*! @name HDCPREG_DPK6 - HDCP Encrypted DPK Data Register 6 This register contains an HDCP DPK byte. */
52987 /*! @{ */
52988 
52989 #define HDCP_HDCPREG_DPK6_DPK_DATA_MASK          (0xFFU)
52990 #define HDCP_HDCPREG_DPK6_DPK_DATA_SHIFT         (0U)
52991 /*! dpk_data - Contains the value of DPK[x][55:48] */
52992 #define HDCP_HDCPREG_DPK6_DPK_DATA(x)            (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK6_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK6_DPK_DATA_MASK)
52993 /*! @} */
52994 
52995 
52996 /*!
52997  * @}
52998  */ /* end of group HDCP_Register_Masks */
52999 
53000 
53001 /* HDCP - Peripheral instance base addresses */
53002 /** Peripheral HDCP base address */
53003 #define HDCP_BASE                                (0x32FDD000u)
53004 /** Peripheral HDCP base pointer */
53005 #define HDCP                                     ((HDCP_Type *)HDCP_BASE)
53006 /** Array initializer of HDCP peripheral base addresses */
53007 #define HDCP_BASE_ADDRS                          { HDCP_BASE }
53008 /** Array initializer of HDCP peripheral base pointers */
53009 #define HDCP_BASE_PTRS                           { HDCP }
53010 
53011 /*!
53012  * @}
53013  */ /* end of group HDCP_Peripheral_Access_Layer */
53014 
53015 
53016 /* ----------------------------------------------------------------------------
53017    -- HDCP22 Peripheral Access Layer
53018    ---------------------------------------------------------------------------- */
53019 
53020 /*!
53021  * @addtogroup HDCP22_Peripheral_Access_Layer HDCP22 Peripheral Access Layer
53022  * @{
53023  */
53024 
53025 /** HDCP22 - Register Layout Typedef */
53026 typedef struct {
53027   __I  uint8_t HDCP22REG_ID;                       /**< HDCP 2., offset: 0x0 */
53028        uint8_t RESERVED_0[3];
53029   __IO uint8_t HDCP22REG_CTRL;                     /**< HDCP 2., offset: 0x4 */
53030   __IO uint8_t HDCP22REG_CTRL1;                    /**< HDCP 2., offset: 0x5 */
53031        uint8_t RESERVED_1[2];
53032   __I  uint8_t HDCP22REG_STS;                      /**< HDCP 2., offset: 0x8 */
53033        uint8_t RESERVED_2[3];
53034   __IO uint8_t HDCP22REG_MASK;                     /**< HDCP 2., offset: 0xC */
53035        uint8_t RESERVED_3[2];
53036   __IO uint8_t HDCP22REG_STAT;                     /**< HDCP 2., offset: 0xF */
53037        uint8_t RESERVED_4[2];
53038   __IO uint8_t HDCP22REG_MUTE;                     /**< HDCP 2., offset: 0x12 */
53039 } HDCP22_Type;
53040 
53041 /* ----------------------------------------------------------------------------
53042    -- HDCP22 Register Masks
53043    ---------------------------------------------------------------------------- */
53044 
53045 /*!
53046  * @addtogroup HDCP22_Register_Masks HDCP22 Register Masks
53047  * @{
53048  */
53049 
53050 /*! @name HDCP22REG_ID - HDCP 2. */
53051 /*! @{ */
53052 
53053 #define HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_MASK (0x2U)
53054 #define HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_SHIFT (1U)
53055 /*! hdcp22_externalif - Indicates that External HDCP 2. */
53056 #define HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_SHIFT)) & HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_MASK)
53057 
53058 #define HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_MASK (0x4U)
53059 #define HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_SHIFT (2U)
53060 /*! hdcp22_3rdparty - Indicates that External HDCP 2. */
53061 #define HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY(x)   (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_SHIFT)) & HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_MASK)
53062 /*! @} */
53063 
53064 /*! @name HDCP22REG_CTRL - HDCP 2. */
53065 /*! @{ */
53066 
53067 #define HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_MASK (0x1U)
53068 #define HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_SHIFT (0U)
53069 /*! hdcp22_switch_lck - HDCP 2. */
53070 #define HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_SHIFT)) & HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_MASK)
53071 
53072 #define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_MASK (0x2U)
53073 #define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_SHIFT (1U)
53074 /*! hdcp22_ovr_en - HDCP 2. */
53075 #define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN(x)   (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_MASK)
53076 
53077 #define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_MASK (0x4U)
53078 #define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_SHIFT (2U)
53079 /*! hdcp22_ovr_val - HDCP 2. */
53080 #define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL(x)  (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_MASK)
53081 
53082 #define HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_MASK    (0x10U)
53083 #define HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_SHIFT   (4U)
53084 /*! hpd_ovr_en - HPD Override enable - 1'b0: The HPD value to the HDCP 2. */
53085 #define HDCP22_HDCP22REG_CTRL_HPD_OVR_EN(x)      (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_MASK)
53086 
53087 #define HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_MASK   (0x20U)
53088 #define HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_SHIFT  (5U)
53089 /*! hpd_ovr_val - HPD Override Value - 1'b0: If hpd_ovr_en is 1'b1 the HPD value to the HDCP 2. */
53090 #define HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL(x)     (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_MASK)
53091 /*! @} */
53092 
53093 /*! @name HDCP22REG_CTRL1 - HDCP 2. */
53094 /*! @{ */
53095 
53096 #define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_MASK (0x1U)
53097 #define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_SHIFT (0U)
53098 /*! hdcp22_avmute_ovr_en - HDCP 2. */
53099 #define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_MASK)
53100 
53101 #define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_MASK (0x2U)
53102 #define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_SHIFT (1U)
53103 /*! hdcp22_avmute_ovr_val - HDCP AV_MUTE override value, which is sent through the HDCP 2. */
53104 #define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_MASK)
53105 
53106 #define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_MASK (0x8U)
53107 #define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_SHIFT (3U)
53108 /*! hdcp22_cd_ovr_en - HDCP 2. */
53109 #define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_MASK)
53110 
53111 #define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_MASK (0xF0U)
53112 #define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_SHIFT (4U)
53113 /*! hdcp22_cd_ovr_val - HDCP color depth override value, which is sent through the HDCP 2. */
53114 #define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_MASK)
53115 /*! @} */
53116 
53117 /*! @name HDCP22REG_STS - HDCP 2. */
53118 /*! @{ */
53119 
53120 #define HDCP22_HDCP22REG_STS_HDMI_HPD_STS_MASK   (0x1U)
53121 #define HDCP22_HDCP22REG_STS_HDMI_HPD_STS_SHIFT  (0U)
53122 /*! hdmi_hpd_sts - HDCP 2. */
53123 #define HDCP22_HDCP22REG_STS_HDMI_HPD_STS(x)     (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDMI_HPD_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDMI_HPD_STS_MASK)
53124 
53125 #define HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_MASK (0x2U)
53126 #define HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_SHIFT (1U)
53127 /*! hdcp_avmute_sts - HDCP 2. */
53128 #define HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS(x)  (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_MASK)
53129 
53130 #define HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_MASK (0x4U)
53131 #define HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_SHIFT (2U)
53132 /*! hdcp22_switch_sts - HDCP 2. */
53133 #define HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_MASK)
53134 
53135 #define HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_MASK (0x8U)
53136 #define HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_SHIFT (3U)
53137 /*! hdcp_decrypted_sts - Value of HDCP 2. */
53138 #define HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_MASK)
53139 /*! @} */
53140 
53141 /*! @name HDCP22REG_MASK - HDCP 2. */
53142 /*! @{ */
53143 
53144 #define HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_MASK (0x1U)
53145 #define HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_SHIFT (0U)
53146 /*! mask_hdcp2_capable - Active high interrupt mask to HDCP 2. */
53147 #define HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_MASK)
53148 
53149 #define HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_MASK (0x2U)
53150 #define HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_SHIFT (1U)
53151 /*! mask_hdcp2_not_capable - Active high interrupt mask to HDCP 2. */
53152 #define HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_MASK)
53153 
53154 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_MASK (0x4U)
53155 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_SHIFT (2U)
53156 /*! mask_hdcp_authentication_lost - Active high interrupt mask to HDCP 2. */
53157 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_MASK)
53158 
53159 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_MASK (0x8U)
53160 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_SHIFT (3U)
53161 /*! mask_hdcp_authenticated - Active high interrupt mask to HDCP 2. */
53162 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_MASK)
53163 
53164 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_MASK (0x10U)
53165 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_SHIFT (4U)
53166 /*! mask_hdcp_authentication_fail - Active high interrupt mask to HDCP 2. */
53167 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_MASK)
53168 
53169 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_MASK (0x20U)
53170 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_SHIFT (5U)
53171 /*! mask_hdcp_decrypted_chg - Active high interrupt mask to HDCP 2. */
53172 #define HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_MASK)
53173 /*! @} */
53174 
53175 /*! @name HDCP22REG_STAT - HDCP 2. */
53176 /*! @{ */
53177 
53178 #define HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_MASK (0x1U)
53179 #define HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_SHIFT (0U)
53180 /*! st_hdcp2_capable - HDCP 2. */
53181 #define HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_MASK)
53182 
53183 #define HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_MASK (0x2U)
53184 #define HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_SHIFT (1U)
53185 /*! st_hdcp2_not_capable - HDCP 2. */
53186 #define HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_MASK)
53187 
53188 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_MASK (0x4U)
53189 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_SHIFT (2U)
53190 /*! st_hdcp_authentication_lost - HDCP 2. */
53191 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_MASK)
53192 
53193 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_MASK (0x8U)
53194 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_SHIFT (3U)
53195 /*! st_hdcp_authenticated - HDCP 2. */
53196 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_MASK)
53197 
53198 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_MASK (0x10U)
53199 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_SHIFT (4U)
53200 /*! st_hdcp_authentication_fail - HDCP 2. */
53201 #define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_MASK)
53202 
53203 #define HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_MASK (0x20U)
53204 #define HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_SHIFT (5U)
53205 /*! st_hdcp_decrypted_chg - HDCP 2. */
53206 #define HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_MASK)
53207 /*! @} */
53208 
53209 /*! @name HDCP22REG_MUTE - HDCP 2. */
53210 /*! @{ */
53211 
53212 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_MASK (0x1U)
53213 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_SHIFT (0U)
53214 /*! mute_hdcp2_capable - Active high interrupt mute to HDCP 2. */
53215 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_MASK)
53216 
53217 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_MASK (0x2U)
53218 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_SHIFT (1U)
53219 /*! mute_hdcp2_not_capable - Active high interrupt mute to HDCP 2. */
53220 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_MASK)
53221 
53222 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_MASK (0x4U)
53223 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_SHIFT (2U)
53224 /*! mute_hdcp_authentication_lost - Active high interrupt mute to HDCP 2. */
53225 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_MASK)
53226 
53227 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_MASK (0x8U)
53228 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_SHIFT (3U)
53229 /*! mute_hdcp_authenticated - Active high interrupt mute to HDCP 2. */
53230 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_MASK)
53231 
53232 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_MASK (0x10U)
53233 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_SHIFT (4U)
53234 /*! mute_hdcp_authentication_fail - Active high interrupt mute to HDCP 2. */
53235 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_MASK)
53236 
53237 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_MASK (0x20U)
53238 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_SHIFT (5U)
53239 /*! mute_hdcp_decrypted_chg - Active high interrupt mute to HDCP 2. */
53240 #define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_MASK)
53241 /*! @} */
53242 
53243 
53244 /*!
53245  * @}
53246  */ /* end of group HDCP22_Register_Masks */
53247 
53248 
53249 /* HDCP22 - Peripheral instance base addresses */
53250 /** Peripheral HDCP22 base address */
53251 #define HDCP22_BASE                              (0x32FDF900u)
53252 /** Peripheral HDCP22 base pointer */
53253 #define HDCP22                                   ((HDCP22_Type *)HDCP22_BASE)
53254 /** Array initializer of HDCP22 peripheral base addresses */
53255 #define HDCP22_BASE_ADDRS                        { HDCP22_BASE }
53256 /** Array initializer of HDCP22 peripheral base pointers */
53257 #define HDCP22_BASE_PTRS                         { HDCP22 }
53258 
53259 /*!
53260  * @}
53261  */ /* end of group HDCP22_Peripheral_Access_Layer */
53262 
53263 
53264 /* ----------------------------------------------------------------------------
53265    -- HDMI_TRNG Peripheral Access Layer
53266    ---------------------------------------------------------------------------- */
53267 
53268 /*!
53269  * @addtogroup HDMI_TRNG_Peripheral_Access_Layer HDMI_TRNG Peripheral Access Layer
53270  * @{
53271  */
53272 
53273 /** HDMI_TRNG - Register Layout Typedef */
53274 typedef struct {
53275   __IO uint32_t CTRL;                              /**< This register causes the DWC_trng to execute one of a number of actions., offset: 0x0 */
53276   __I  uint32_t STAT;                              /**< The NONCE_MODE field indicates that the engine is currently waiting for the host to load a nonce through the SEEDx registers., offset: 0x4 */
53277        uint8_t RESERVED_0[4];
53278   __IO uint32_t SMODE;                             /**< This register is used to enable or disable certain mission-mode run-time features within the core., offset: 0xC */
53279   __IO uint32_t IE;                                /**< This register is used to enable or disable interrupts within the DWC_trng., offset: 0x10 */
53280   __IO uint32_t ISTAT;                             /**< This register allows the user to monitor the interrupt and/or status contributions of the DWC_trng., offset: 0x14 */
53281   __I  uint32_t COREKIT_REL;                       /**< Contains the coreKit release information., offset: 0x18 */
53282   __I  uint32_t FEATURES;                          /**< Contains the build-time parameter enumerations., offset: 0x1C */
53283   __I  uint32_t RAND0;                             /**< The RAND0 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x20 */
53284   __I  uint32_t RAND1;                             /**< The RAND1 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x24 */
53285   __I  uint32_t RAND2;                             /**< The RAND2 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x28 */
53286   __I  uint32_t RAND3;                             /**< The RAND3 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x2C */
53287   __I  uint32_t RAND4;                             /**< The RAND4 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x30 */
53288   __I  uint32_t RAND5;                             /**< The RAND5 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x34 */
53289   __I  uint32_t RAND6;                             /**< The RAND6 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x38 */
53290   __I  uint32_t RAND7;                             /**< The RAND7 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x3C */
53291   __I  uint32_t SEED0;                             /**< The SEED0 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x40 */
53292   __I  uint32_t SEED1;                             /**< The SEED1 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x44 */
53293   __I  uint32_t SEED2;                             /**< The SEED2 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x48 */
53294   __I  uint32_t SEED3;                             /**< The SEED3 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x4C */
53295   __I  uint32_t SEED4;                             /**< The SEED4 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x50 */
53296   __I  uint32_t SEED5;                             /**< The SEED5 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x54 */
53297   __I  uint32_t SEED6;                             /**< The SEED6 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x58 */
53298   __I  uint32_t SEED7;                             /**< The SEED7 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x5C */
53299   __IO uint32_t AUTO_RQSTS;                        /**< This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host., offset: 0x60 */
53300   __IO uint32_t AUTO_AGE;                          /**< This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host., offset: 0x64 */
53301   __I  uint32_t BUILD_CONFIG;                      /**< Contains the build-time parameter enumerations., offset: 0x68 */
53302 } HDMI_TRNG_Type;
53303 
53304 /* ----------------------------------------------------------------------------
53305    -- HDMI_TRNG Register Masks
53306    ---------------------------------------------------------------------------- */
53307 
53308 /*!
53309  * @addtogroup HDMI_TRNG_Register_Masks HDMI_TRNG Register Masks
53310  * @{
53311  */
53312 
53313 /*! @name CTRL - This register causes the DWC_trng to execute one of a number of actions. */
53314 /*! @{ */
53315 
53316 #define HDMI_TRNG_CTRL_CMD_MASK                  (0x7U)
53317 #define HDMI_TRNG_CTRL_CMD_SHIFT                 (0U)
53318 /*! CMD - Execute a command.
53319  *  0b001..Generate a random number
53320  *  0b011..Execute a nonce reseed
53321  *  0b000..Execute a NOP
53322  *  0b010..Execute a random reseed
53323  */
53324 #define HDMI_TRNG_CTRL_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_CTRL_CMD_SHIFT)) & HDMI_TRNG_CTRL_CMD_MASK)
53325 /*! @} */
53326 
53327 /*! @name STAT - The NONCE_MODE field indicates that the engine is currently waiting for the host to load a nonce through the SEEDx registers. */
53328 /*! @{ */
53329 
53330 #define HDMI_TRNG_STAT_NONCE_MODE_MASK           (0x4U)
53331 #define HDMI_TRNG_STAT_NONCE_MODE_SHIFT          (2U)
53332 /*! NONCE_MODE - Current state of NONCE mode.
53333  *  0b0..Nonce mode disabled
53334  *  0b1..Nonce mode enabled
53335  */
53336 #define HDMI_TRNG_STAT_NONCE_MODE(x)             (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_NONCE_MODE_SHIFT)) & HDMI_TRNG_STAT_NONCE_MODE_MASK)
53337 
53338 #define HDMI_TRNG_STAT_R256_MASK                 (0x8U)
53339 #define HDMI_TRNG_STAT_R256_SHIFT                (3U)
53340 /*! R256 - Reflects state of MODE. */
53341 #define HDMI_TRNG_STAT_R256(x)                   (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_R256_SHIFT)) & HDMI_TRNG_STAT_R256_MASK)
53342 
53343 #define HDMI_TRNG_STAT_MISSION_MODE_MASK         (0x100U)
53344 #define HDMI_TRNG_STAT_MISSION_MODE_SHIFT        (8U)
53345 /*! MISSION_MODE - Reflects state of SMODE. */
53346 #define HDMI_TRNG_STAT_MISSION_MODE(x)           (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_MISSION_MODE_SHIFT)) & HDMI_TRNG_STAT_MISSION_MODE_MASK)
53347 
53348 #define HDMI_TRNG_STAT_SEEDED_MASK               (0x200U)
53349 #define HDMI_TRNG_STAT_SEEDED_SHIFT              (9U)
53350 /*! SEEDED - Current SEEDED state.
53351  *  0b0..PRNG core is not seeded
53352  *  0b1..PRNG core is seeded
53353  */
53354 #define HDMI_TRNG_STAT_SEEDED(x)                 (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_SEEDED_SHIFT)) & HDMI_TRNG_STAT_SEEDED_MASK)
53355 
53356 #define HDMI_TRNG_STAT_LAST_RESEED_MASK          (0x70000U)
53357 #define HDMI_TRNG_STAT_LAST_RESEED_SHIFT         (16U)
53358 /*! LAST_RESEED - Action which loaded current seed.
53359  *  0b000..Reseeded by host random reseed command
53360  *  0b011..Reseeded by nonce
53361  *  0b100..Reseeded by <b>I_reseed</b> driven to 1 or internal auto-reseed
53362  *  0b111..Unseeded (zeroized state)
53363  */
53364 #define HDMI_TRNG_STAT_LAST_RESEED(x)            (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_LAST_RESEED_SHIFT)) & HDMI_TRNG_STAT_LAST_RESEED_MASK)
53365 
53366 #define HDMI_TRNG_STAT_SRVC_RQST_MASK            (0x8000000U)
53367 #define HDMI_TRNG_STAT_SRVC_RQST_SHIFT           (27U)
53368 /*! SRVC_RQST - Current state of unacknowledged request indicator.
53369  *  0b0..No unacknowledged service request
53370  *  0b1..Unacknowledged service request
53371  */
53372 #define HDMI_TRNG_STAT_SRVC_RQST(x)              (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_SRVC_RQST_SHIFT)) & HDMI_TRNG_STAT_SRVC_RQST_MASK)
53373 
53374 #define HDMI_TRNG_STAT_RAND_GENERATING_MASK      (0x40000000U)
53375 #define HDMI_TRNG_STAT_RAND_GENERATING_SHIFT     (30U)
53376 /*! RAND_GENERATING - Current state of random number generation operations.
53377  *  0b0..No random number generation process in progress
53378  *  0b1..Random number generation process in progress
53379  */
53380 #define HDMI_TRNG_STAT_RAND_GENERATING(x)        (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_RAND_GENERATING_SHIFT)) & HDMI_TRNG_STAT_RAND_GENERATING_MASK)
53381 
53382 #define HDMI_TRNG_STAT_RAND_RESEEDING_MASK       (0x80000000U)
53383 #define HDMI_TRNG_STAT_RAND_RESEEDING_SHIFT      (31U)
53384 /*! RAND_RESEEDING - Current state of random seed generation operations.
53385  *  0b0..No random reseed generation process in progress
53386  *  0b1..Random reseed generation process in progress
53387  */
53388 #define HDMI_TRNG_STAT_RAND_RESEEDING(x)         (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_RAND_RESEEDING_SHIFT)) & HDMI_TRNG_STAT_RAND_RESEEDING_MASK)
53389 /*! @} */
53390 
53391 /*! @name SMODE - This register is used to enable or disable certain mission-mode run-time features within the core. */
53392 /*! @{ */
53393 
53394 #define HDMI_TRNG_SMODE_NONCE_MODE_MASK          (0x4U)
53395 #define HDMI_TRNG_SMODE_NONCE_MODE_SHIFT         (2U)
53396 /*! NONCE_MODE - Sets the reseed mode to nonce or random.
53397  *  0b0..Disable nonce mode
53398  *  0b1..Enable nonce mode
53399  */
53400 #define HDMI_TRNG_SMODE_NONCE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SMODE_NONCE_MODE_SHIFT)) & HDMI_TRNG_SMODE_NONCE_MODE_MASK)
53401 
53402 #define HDMI_TRNG_SMODE_MISSION_MODE_MASK        (0x100U)
53403 #define HDMI_TRNG_SMODE_MISSION_MODE_SHIFT       (8U)
53404 /*! MISSION_MODE - Sets the operating mode to TEST or MISSION.
53405  *  0b1..Mission mode (no access to internal state)
53406  *  0b0..Test mode (access to internal state and test fields)
53407  */
53408 #define HDMI_TRNG_SMODE_MISSION_MODE(x)          (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SMODE_MISSION_MODE_SHIFT)) & HDMI_TRNG_SMODE_MISSION_MODE_MASK)
53409 
53410 #define HDMI_TRNG_SMODE_MAX_REJECTS_MASK         (0xFF0000U)
53411 #define HDMI_TRNG_SMODE_MAX_REJECTS_SHIFT        (16U)
53412 /*! MAX_REJECTS - Maximum number of consecutive bit rejections before issuing ring tweak. */
53413 #define HDMI_TRNG_SMODE_MAX_REJECTS(x)           (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SMODE_MAX_REJECTS_SHIFT)) & HDMI_TRNG_SMODE_MAX_REJECTS_MASK)
53414 /*! @} */
53415 
53416 /*! @name IE - This register is used to enable or disable interrupts within the DWC_trng. */
53417 /*! @{ */
53418 
53419 #define HDMI_TRNG_IE_RAND_RDY_EN_MASK            (0x1U)
53420 #define HDMI_TRNG_IE_RAND_RDY_EN_SHIFT           (0U)
53421 /*! RAND_RDY_EN - Include or exclude RAND_RDY interrupt contribution.
53422  *  0b0..Disable <b>RAND_RDY</b> interrupt contribution
53423  *  0b1..Enable <b>RAND_RDY</b> interrupt contribution
53424  */
53425 #define HDMI_TRNG_IE_RAND_RDY_EN(x)              (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_RAND_RDY_EN_SHIFT)) & HDMI_TRNG_IE_RAND_RDY_EN_MASK)
53426 
53427 #define HDMI_TRNG_IE_SEED_DONE_EN_MASK           (0x2U)
53428 #define HDMI_TRNG_IE_SEED_DONE_EN_SHIFT          (1U)
53429 /*! SEED_DONE_EN - Include or exclude SEED_DONE interrupt contribution.
53430  *  0b0..Disable <b>SEED_DONE</b> interrupt contribution
53431  *  0b1..Enable <b>SEED_DONE</b> interrupt contribution
53432  */
53433 #define HDMI_TRNG_IE_SEED_DONE_EN(x)             (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_SEED_DONE_EN_SHIFT)) & HDMI_TRNG_IE_SEED_DONE_EN_MASK)
53434 
53435 #define HDMI_TRNG_IE_AGE_ALARM_EN_MASK           (0x4U)
53436 #define HDMI_TRNG_IE_AGE_ALARM_EN_SHIFT          (2U)
53437 /*! AGE_ALARM_EN - Include or exclude AGE_ALARM interrupt contribution.
53438  *  0b0..Disable <b>AGE_ALARM</b> interrupt contribution
53439  *  0b1..Enable <b>AGE_ALARM</b> interrupt contribution
53440  */
53441 #define HDMI_TRNG_IE_AGE_ALARM_EN(x)             (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_AGE_ALARM_EN_SHIFT)) & HDMI_TRNG_IE_AGE_ALARM_EN_MASK)
53442 
53443 #define HDMI_TRNG_IE_RQST_ALARM_EN_MASK          (0x8U)
53444 #define HDMI_TRNG_IE_RQST_ALARM_EN_SHIFT         (3U)
53445 /*! RQST_ALARM_EN - Include or exclude RQST_ALARM interrupt contribution.
53446  *  0b0..Disable <b>RQST_ALARM</b> interrupt contribution
53447  *  0b1..Enable <b>RQST_ALARM</b> interrupt contribution
53448  */
53449 #define HDMI_TRNG_IE_RQST_ALARM_EN(x)            (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_RQST_ALARM_EN_SHIFT)) & HDMI_TRNG_IE_RQST_ALARM_EN_MASK)
53450 
53451 #define HDMI_TRNG_IE_LFSR_LOCKUP_EN_MASK         (0x10U)
53452 #define HDMI_TRNG_IE_LFSR_LOCKUP_EN_SHIFT        (4U)
53453 /*! LFSR_LOCKUP_EN - Include or exclude LFSR_LOCKUP interrupt contribution.
53454  *  0b0..Disable <b>LFSR_LOCKUP</b> interrupt contribution
53455  *  0b1..Enable <b>LFSR_LOCKUP</b> interrupt contribution
53456  */
53457 #define HDMI_TRNG_IE_LFSR_LOCKUP_EN(x)           (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_LFSR_LOCKUP_EN_SHIFT)) & HDMI_TRNG_IE_LFSR_LOCKUP_EN_MASK)
53458 
53459 #define HDMI_TRNG_IE_GLBL_EN_MASK                (0x80000000U)
53460 #define HDMI_TRNG_IE_GLBL_EN_SHIFT               (31U)
53461 /*! GLBL_EN - Global interrupt enable.
53462  *  0b0..Globally disable interrupts
53463  *  0b1..Globally enable interrupts
53464  */
53465 #define HDMI_TRNG_IE_GLBL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_GLBL_EN_SHIFT)) & HDMI_TRNG_IE_GLBL_EN_MASK)
53466 /*! @} */
53467 
53468 /*! @name ISTAT - This register allows the user to monitor the interrupt and/or status contributions of the DWC_trng. */
53469 /*! @{ */
53470 
53471 #define HDMI_TRNG_ISTAT_RAND_RDY_MASK            (0x1U)
53472 #define HDMI_TRNG_ISTAT_RAND_RDY_SHIFT           (0U)
53473 /*! RAND_RDY - Status and acknowledgment (clearing) of RAND_RDY indicator.
53474  *  0b0..No unacknowledged RAND_RDY indicator
53475  *  0b1..Unacknowledged RAND_RDY indicator
53476  *  0b0..NOP
53477  *  0b1..Acknowledge RAND_RDY indicator
53478  */
53479 #define HDMI_TRNG_ISTAT_RAND_RDY(x)              (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_RAND_RDY_SHIFT)) & HDMI_TRNG_ISTAT_RAND_RDY_MASK)
53480 
53481 #define HDMI_TRNG_ISTAT_SEED_DONE_MASK           (0x2U)
53482 #define HDMI_TRNG_ISTAT_SEED_DONE_SHIFT          (1U)
53483 /*! SEED_DONE - Status and acknowledgment (clearing) of SEED_DONE indicator.
53484  *  0b0..No unacknowledged SEED_DONE indicator
53485  *  0b1..Unacknowledged SEED_DONE indicator
53486  *  0b0..NOP
53487  *  0b1..Acknowledge SEED_DONE indicator
53488  */
53489 #define HDMI_TRNG_ISTAT_SEED_DONE(x)             (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_SEED_DONE_SHIFT)) & HDMI_TRNG_ISTAT_SEED_DONE_MASK)
53490 
53491 #define HDMI_TRNG_ISTAT_AGE_ALARM_MASK           (0x4U)
53492 #define HDMI_TRNG_ISTAT_AGE_ALARM_SHIFT          (2U)
53493 /*! AGE_ALARM - Status and acknowledgment (clearing) of AGE_ALARM indicator.
53494  *  0b0..No unacknowledged AGE_ALARM indicator
53495  *  0b1..Unacknowledged AGE_ALARM indicator
53496  *  0b0..NOP
53497  *  0b1..Acknowledge AGE_ALARM indicator
53498  */
53499 #define HDMI_TRNG_ISTAT_AGE_ALARM(x)             (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_AGE_ALARM_SHIFT)) & HDMI_TRNG_ISTAT_AGE_ALARM_MASK)
53500 
53501 #define HDMI_TRNG_ISTAT_RQST_ALARM_MASK          (0x8U)
53502 #define HDMI_TRNG_ISTAT_RQST_ALARM_SHIFT         (3U)
53503 /*! RQST_ALARM - Status and acknowledgment (clearing) of RQST_ALARM indicator.
53504  *  0b0..No unacknowledged RQST_ALARM indicator
53505  *  0b1..Unacknowledged RQST_ALARM indicator
53506  *  0b0..NOP
53507  *  0b1..Acknowledge RQST_ALARM indicator
53508  */
53509 #define HDMI_TRNG_ISTAT_RQST_ALARM(x)            (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_RQST_ALARM_SHIFT)) & HDMI_TRNG_ISTAT_RQST_ALARM_MASK)
53510 
53511 #define HDMI_TRNG_ISTAT_LFSR_LOCKUP_MASK         (0x10U)
53512 #define HDMI_TRNG_ISTAT_LFSR_LOCKUP_SHIFT        (4U)
53513 /*! LFSR_LOCKUP - Status and acknowledgment (clearing) of LFSR_LOCKUP indicator.
53514  *  0b0..No unacknowledged LFSR_LOCKUP indicator
53515  *  0b1..Unacknowledged LFSR_LOCKUP indicator
53516  *  0b0..NOP
53517  *  0b1..Acknowledge LFSR_LOCKUP indicator
53518  */
53519 #define HDMI_TRNG_ISTAT_LFSR_LOCKUP(x)           (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_LFSR_LOCKUP_SHIFT)) & HDMI_TRNG_ISTAT_LFSR_LOCKUP_MASK)
53520 /*! @} */
53521 
53522 /*! @name COREKIT_REL - Contains the coreKit release information. */
53523 /*! @{ */
53524 
53525 #define HDMI_TRNG_COREKIT_REL_REL_NUM_MASK       (0xFFFFU)
53526 #define HDMI_TRNG_COREKIT_REL_REL_NUM_SHIFT      (0U)
53527 /*! REL_NUM - Indicates the coreKit release version in pseudo-BCD. */
53528 #define HDMI_TRNG_COREKIT_REL_REL_NUM(x)         (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_COREKIT_REL_REL_NUM_SHIFT)) & HDMI_TRNG_COREKIT_REL_REL_NUM_MASK)
53529 
53530 #define HDMI_TRNG_COREKIT_REL_EXT_VER_MASK       (0xFF0000U)
53531 #define HDMI_TRNG_COREKIT_REL_EXT_VER_SHIFT      (16U)
53532 /*! EXT_VER - Indicates the coreKit release extension version number. */
53533 #define HDMI_TRNG_COREKIT_REL_EXT_VER(x)         (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_COREKIT_REL_EXT_VER_SHIFT)) & HDMI_TRNG_COREKIT_REL_EXT_VER_MASK)
53534 
53535 #define HDMI_TRNG_COREKIT_REL_EXT_ENUM_MASK      (0xF0000000U)
53536 #define HDMI_TRNG_COREKIT_REL_EXT_ENUM_SHIFT     (28U)
53537 /*! EXT_ENUM - Indicates the coreKit release extension type.
53538  *  0b0010..EA release
53539  *  0b0000..GA release
53540  *  0b0001..LCA release
53541  *  0b0011..LP release
53542  *  0b0100..LPC release
53543  *  0b0101..SOW release
53544  */
53545 #define HDMI_TRNG_COREKIT_REL_EXT_ENUM(x)        (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_COREKIT_REL_EXT_ENUM_SHIFT)) & HDMI_TRNG_COREKIT_REL_EXT_ENUM_MASK)
53546 /*! @} */
53547 
53548 /*! @name FEATURES - Contains the build-time parameter enumerations. */
53549 /*! @{ */
53550 
53551 #define HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_MASK  (0x3U)
53552 #define HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_SHIFT (0U)
53553 /*! MAX_RAND_LENGTH - Maximum length of the PRNG RANDx register set.
53554  *  0b00..PRNG set up for 128-bit maximum
53555  *  0b01..PRNG set up for 256-bit maximum
53556  */
53557 #define HDMI_TRNG_FEATURES_MAX_RAND_LENGTH(x)    (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_SHIFT)) & HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_MASK)
53558 
53559 #define HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_MASK  (0x4U)
53560 #define HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_SHIFT (2U)
53561 /*! RAND_SEED_AVAIL - Indicates the ring-oscillator sub-section is present.
53562  *  0b0..No ring-oscillator seed generator present
53563  *  0b1..Ring-oscillator seed generator present
53564  */
53565 #define HDMI_TRNG_FEATURES_RAND_SEED_AVAIL(x)    (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_SHIFT)) & HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_MASK)
53566 
53567 #define HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_MASK (0x8U)
53568 #define HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_SHIFT (3U)
53569 /*! MISSION_MODE_RESET_STATE - Indicates state of SMODE.
53570  *  0b1..Resets to MISSION_MODE
53571  *  0b0..Resets to TEST_MODE
53572  */
53573 #define HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_SHIFT)) & HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_MASK)
53574 
53575 #define HDMI_TRNG_FEATURES_DIAG_LEVEL_MASK       (0x70U)
53576 #define HDMI_TRNG_FEATURES_DIAG_LEVEL_SHIFT      (4U)
53577 /*! DIAG_LEVEL - Level of diagnostic support provided. */
53578 #define HDMI_TRNG_FEATURES_DIAG_LEVEL(x)         (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_DIAG_LEVEL_SHIFT)) & HDMI_TRNG_FEATURES_DIAG_LEVEL_MASK)
53579 /*! @} */
53580 
53581 /*! @name RAND0 - The RAND0 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53582 /*! @{ */
53583 
53584 #define HDMI_TRNG_RAND0_RAND_MASK                (0xFFFFFFFFU)
53585 #define HDMI_TRNG_RAND0_RAND_SHIFT               (0U)
53586 /*! RAND - Random data word 0. */
53587 #define HDMI_TRNG_RAND0_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND0_RAND_SHIFT)) & HDMI_TRNG_RAND0_RAND_MASK)
53588 /*! @} */
53589 
53590 /*! @name RAND1 - The RAND1 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53591 /*! @{ */
53592 
53593 #define HDMI_TRNG_RAND1_RAND_MASK                (0xFFFFFFFFU)
53594 #define HDMI_TRNG_RAND1_RAND_SHIFT               (0U)
53595 /*! RAND - Random data word 1. */
53596 #define HDMI_TRNG_RAND1_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND1_RAND_SHIFT)) & HDMI_TRNG_RAND1_RAND_MASK)
53597 /*! @} */
53598 
53599 /*! @name RAND2 - The RAND2 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53600 /*! @{ */
53601 
53602 #define HDMI_TRNG_RAND2_RAND_MASK                (0xFFFFFFFFU)
53603 #define HDMI_TRNG_RAND2_RAND_SHIFT               (0U)
53604 /*! RAND - Random data word 2. */
53605 #define HDMI_TRNG_RAND2_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND2_RAND_SHIFT)) & HDMI_TRNG_RAND2_RAND_MASK)
53606 /*! @} */
53607 
53608 /*! @name RAND3 - The RAND3 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53609 /*! @{ */
53610 
53611 #define HDMI_TRNG_RAND3_RAND_MASK                (0xFFFFFFFFU)
53612 #define HDMI_TRNG_RAND3_RAND_SHIFT               (0U)
53613 /*! RAND - Random data word 3. */
53614 #define HDMI_TRNG_RAND3_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND3_RAND_SHIFT)) & HDMI_TRNG_RAND3_RAND_MASK)
53615 /*! @} */
53616 
53617 /*! @name RAND4 - The RAND4 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53618 /*! @{ */
53619 
53620 #define HDMI_TRNG_RAND4_RAND_MASK                (0xFFFFFFFFU)
53621 #define HDMI_TRNG_RAND4_RAND_SHIFT               (0U)
53622 /*! RAND - Random data word 4. */
53623 #define HDMI_TRNG_RAND4_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND4_RAND_SHIFT)) & HDMI_TRNG_RAND4_RAND_MASK)
53624 /*! @} */
53625 
53626 /*! @name RAND5 - The RAND5 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53627 /*! @{ */
53628 
53629 #define HDMI_TRNG_RAND5_RAND_MASK                (0xFFFFFFFFU)
53630 #define HDMI_TRNG_RAND5_RAND_SHIFT               (0U)
53631 /*! RAND - Random data word 5. */
53632 #define HDMI_TRNG_RAND5_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND5_RAND_SHIFT)) & HDMI_TRNG_RAND5_RAND_MASK)
53633 /*! @} */
53634 
53635 /*! @name RAND6 - The RAND6 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53636 /*! @{ */
53637 
53638 #define HDMI_TRNG_RAND6_RAND_MASK                (0xFFFFFFFFU)
53639 #define HDMI_TRNG_RAND6_RAND_SHIFT               (0U)
53640 /*! RAND - Random data word 6. */
53641 #define HDMI_TRNG_RAND6_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND6_RAND_SHIFT)) & HDMI_TRNG_RAND6_RAND_MASK)
53642 /*! @} */
53643 
53644 /*! @name RAND7 - The RAND7 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
53645 /*! @{ */
53646 
53647 #define HDMI_TRNG_RAND7_RAND_MASK                (0xFFFFFFFFU)
53648 #define HDMI_TRNG_RAND7_RAND_SHIFT               (0U)
53649 /*! RAND - Random data word 7. */
53650 #define HDMI_TRNG_RAND7_RAND(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND7_RAND_SHIFT)) & HDMI_TRNG_RAND7_RAND_MASK)
53651 /*! @} */
53652 
53653 /*! @name SEED0 - The SEED0 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53654 /*! @{ */
53655 
53656 #define HDMI_TRNG_SEED0_SEED_MASK                (0xFFFFFFFFU)
53657 #define HDMI_TRNG_SEED0_SEED_SHIFT               (0U)
53658 /*! SEED - Seed data word 0. */
53659 #define HDMI_TRNG_SEED0_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED0_SEED_SHIFT)) & HDMI_TRNG_SEED0_SEED_MASK)
53660 /*! @} */
53661 
53662 /*! @name SEED1 - The SEED1 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53663 /*! @{ */
53664 
53665 #define HDMI_TRNG_SEED1_SEED_MASK                (0xFFFFFFFFU)
53666 #define HDMI_TRNG_SEED1_SEED_SHIFT               (0U)
53667 /*! SEED - Seed data word 1. */
53668 #define HDMI_TRNG_SEED1_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED1_SEED_SHIFT)) & HDMI_TRNG_SEED1_SEED_MASK)
53669 /*! @} */
53670 
53671 /*! @name SEED2 - The SEED2 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53672 /*! @{ */
53673 
53674 #define HDMI_TRNG_SEED2_SEED_MASK                (0xFFFFFFFFU)
53675 #define HDMI_TRNG_SEED2_SEED_SHIFT               (0U)
53676 /*! SEED - Seed data word 2. */
53677 #define HDMI_TRNG_SEED2_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED2_SEED_SHIFT)) & HDMI_TRNG_SEED2_SEED_MASK)
53678 /*! @} */
53679 
53680 /*! @name SEED3 - The SEED3 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53681 /*! @{ */
53682 
53683 #define HDMI_TRNG_SEED3_SEED_MASK                (0xFFFFFFFFU)
53684 #define HDMI_TRNG_SEED3_SEED_SHIFT               (0U)
53685 /*! SEED - Seed data word 3. */
53686 #define HDMI_TRNG_SEED3_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED3_SEED_SHIFT)) & HDMI_TRNG_SEED3_SEED_MASK)
53687 /*! @} */
53688 
53689 /*! @name SEED4 - The SEED4 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53690 /*! @{ */
53691 
53692 #define HDMI_TRNG_SEED4_SEED_MASK                (0xFFFFFFFFU)
53693 #define HDMI_TRNG_SEED4_SEED_SHIFT               (0U)
53694 /*! SEED - Seed data word 4. */
53695 #define HDMI_TRNG_SEED4_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED4_SEED_SHIFT)) & HDMI_TRNG_SEED4_SEED_MASK)
53696 /*! @} */
53697 
53698 /*! @name SEED5 - The SEED5 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53699 /*! @{ */
53700 
53701 #define HDMI_TRNG_SEED5_SEED_MASK                (0xFFFFFFFFU)
53702 #define HDMI_TRNG_SEED5_SEED_SHIFT               (0U)
53703 /*! SEED - Seed data word 5. */
53704 #define HDMI_TRNG_SEED5_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED5_SEED_SHIFT)) & HDMI_TRNG_SEED5_SEED_MASK)
53705 /*! @} */
53706 
53707 /*! @name SEED6 - The SEED6 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53708 /*! @{ */
53709 
53710 #define HDMI_TRNG_SEED6_SEED_MASK                (0xFFFFFFFFU)
53711 #define HDMI_TRNG_SEED6_SEED_SHIFT               (0U)
53712 /*! SEED - Seed data word 6. */
53713 #define HDMI_TRNG_SEED6_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED6_SEED_SHIFT)) & HDMI_TRNG_SEED6_SEED_MASK)
53714 /*! @} */
53715 
53716 /*! @name SEED7 - The SEED7 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
53717 /*! @{ */
53718 
53719 #define HDMI_TRNG_SEED7_SEED_MASK                (0xFFFFFFFFU)
53720 #define HDMI_TRNG_SEED7_SEED_SHIFT               (0U)
53721 /*! SEED - Seed data word 7. */
53722 #define HDMI_TRNG_SEED7_SEED(x)                  (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED7_SEED_SHIFT)) & HDMI_TRNG_SEED7_SEED_MASK)
53723 /*! @} */
53724 
53725 /*! @name AUTO_RQSTS - This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host. */
53726 /*! @{ */
53727 
53728 #define HDMI_TRNG_AUTO_RQSTS_RQSTS_MASK          (0xFFFFU)
53729 #define HDMI_TRNG_AUTO_RQSTS_RQSTS_SHIFT         (0U)
53730 /*! RQSTS - 0 = disable the AUTO_RQSTS alarm feature other = reload value for internal AUTO_RQSTS counter */
53731 #define HDMI_TRNG_AUTO_RQSTS_RQSTS(x)            (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_AUTO_RQSTS_RQSTS_SHIFT)) & HDMI_TRNG_AUTO_RQSTS_RQSTS_MASK)
53732 /*! @} */
53733 
53734 /*! @name AUTO_AGE - This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host. */
53735 /*! @{ */
53736 
53737 #define HDMI_TRNG_AUTO_AGE_AGE_MASK              (0xFFFFU)
53738 #define HDMI_TRNG_AUTO_AGE_AGE_SHIFT             (0U)
53739 /*! AGE - 0 = disable the AUTO_AGE alarm feature other = reload value for internal AUTO_AGE counter */
53740 #define HDMI_TRNG_AUTO_AGE_AGE(x)                (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_AUTO_AGE_AGE_SHIFT)) & HDMI_TRNG_AUTO_AGE_AGE_MASK)
53741 /*! @} */
53742 
53743 /*! @name BUILD_CONFIG - Contains the build-time parameter enumerations. */
53744 /*! @{ */
53745 
53746 #define HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_MASK    (0x3U)
53747 #define HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_SHIFT   (0U)
53748 /*! CORE_TYPE - Configured I/O style (license controlled).
53749  *  0b01..ESM nonce I/O
53750  *  0b10..ESM nonce I/O with multi-ESM support
53751  *  0b00..5-Wire control/status I/O
53752  */
53753 #define HDMI_TRNG_BUILD_CONFIG_CORE_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_MASK)
53754 
53755 #define HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_MASK (0x4U)
53756 #define HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_SHIFT (2U)
53757 /*! MAX_PRNG_LEN - Maximum length of the PRNG RANDx register set.
53758  *  0b0..PRNG set up for 128-bit maximum
53759  *  0b1..PRNG set up for 256-bit maximum
53760  */
53761 #define HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN(x)   (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_MASK)
53762 
53763 #define HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_MASK (0x8U)
53764 #define HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_SHIFT (3U)
53765 /*! PRNG_LEN_AFTER_RST - State of MODE.
53766  *  0b0..PRNG length set to 128-bit after reset
53767  *  0b1..PRNG length set to 256-bit after reset
53768  */
53769 #define HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_MASK)
53770 
53771 #define HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_MASK (0x10U)
53772 #define HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_SHIFT (4U)
53773 /*! MODE_AFTER_RST - Indicates state of SMODE.
53774  *  0b1..Resets to MISSION_MODE
53775  *  0b0..Resets to TEST_MODE
53776  */
53777 #define HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_MASK)
53778 
53779 #define HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_MASK (0x20U)
53780 #define HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_SHIFT (5U)
53781 /*! AUTO_RESEED_LOOPBACK - Indicates auto-reseed configuration setting.
53782  *  0b1..Auto-reseed loopback present
53783  *  0b0..No auto-reseed loopback
53784  */
53785 #define HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_MASK)
53786 
53787 #define HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_MASK (0x700U)
53788 #define HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_SHIFT (8U)
53789 /*! DIAGNOSTIC_LEVEL - Level of diagnostic support provided. */
53790 #define HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_MASK)
53791 
53792 #define HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_MASK    (0xF000U)
53793 #define HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_SHIFT   (12U)
53794 /*! ESM_PORTS - Indicates number of ESM arbitration ports available minus 1. */
53795 #define HDMI_TRNG_BUILD_CONFIG_ESM_PORTS(x)      (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_MASK)
53796 /*! @} */
53797 
53798 
53799 /*!
53800  * @}
53801  */ /* end of group HDMI_TRNG_Register_Masks */
53802 
53803 
53804 /* HDMI_TRNG - Peripheral instance base addresses */
53805 /** Peripheral HDMI_TRNG base address */
53806 #define HDMI_TRNG_BASE                           (0x32FD3000u)
53807 /** Peripheral HDMI_TRNG base pointer */
53808 #define HDMI_TRNG                                ((HDMI_TRNG_Type *)HDMI_TRNG_BASE)
53809 /** Array initializer of HDMI_TRNG peripheral base addresses */
53810 #define HDMI_TRNG_BASE_ADDRS                     { HDMI_TRNG_BASE }
53811 /** Array initializer of HDMI_TRNG peripheral base pointers */
53812 #define HDMI_TRNG_BASE_PTRS                      { HDMI_TRNG }
53813 
53814 /*!
53815  * @}
53816  */ /* end of group HDMI_TRNG_Peripheral_Access_Layer */
53817 
53818 
53819 /* ----------------------------------------------------------------------------
53820    -- HDMI_TX_BLK_CTL Peripheral Access Layer
53821    ---------------------------------------------------------------------------- */
53822 
53823 /*!
53824  * @addtogroup HDMI_TX_BLK_CTL_Peripheral_Access_Layer HDMI_TX_BLK_CTL Peripheral Access Layer
53825  * @{
53826  */
53827 
53828 /** HDMI_TX_BLK_CTL - Register Layout Typedef */
53829 typedef struct {
53830   struct {                                         /* offset: 0x0 */
53831     __IO uint32_t RW;                                /**< HDMI_RTX_GENERAL CONFIG, offset: 0x0 */
53832     __IO uint32_t SET;                               /**< HDMI_RTX_GENERAL CONFIG, offset: 0x4 */
53833     __IO uint32_t CLR;                               /**< HDMI_RTX_GENERAL CONFIG, offset: 0x8 */
53834     __IO uint32_t TOG;                               /**< HDMI_RTX_GENERAL CONFIG, offset: 0xC */
53835   } RTX_GENERAL;
53836   struct {                                         /* offset: 0x10 */
53837     __IO uint32_t RW;                                /**< HDMI_RTX_GENERAL CONFIG, offset: 0x10 */
53838     __IO uint32_t SET;                               /**< HDMI_RTX_GENERAL CONFIG, offset: 0x14 */
53839     __IO uint32_t CLR;                               /**< HDMI_RTX_GENERAL CONFIG, offset: 0x18 */
53840     __IO uint32_t TOG;                               /**< HDMI_RTX_GENERAL CONFIG, offset: 0x1C */
53841   } RTX_GENERAL_1;
53842   struct {                                         /* offset: 0x20 */
53843     __IO uint32_t RW;                                /**< HDMI_RTX_RESET_CTL0, offset: 0x20 */
53844     __IO uint32_t SET;                               /**< HDMI_RTX_RESET_CTL0, offset: 0x24 */
53845     __IO uint32_t CLR;                               /**< HDMI_RTX_RESET_CTL0, offset: 0x28 */
53846     __IO uint32_t TOG;                               /**< HDMI_RTX_RESET_CTL0, offset: 0x2C */
53847   } RTX_RESET_CTL0;
53848        uint8_t RESERVED_0[16];
53849   struct {                                         /* offset: 0x40 */
53850     __IO uint32_t RW;                                /**< HDMI_RTX_CLK_CTL0, offset: 0x40 */
53851     __IO uint32_t SET;                               /**< HDMI_RTX_CLK_CTL0, offset: 0x44 */
53852     __IO uint32_t CLR;                               /**< HDMI_RTX_CLK_CTL0, offset: 0x48 */
53853     __IO uint32_t TOG;                               /**< HDMI_RTX_CLK_CTL0, offset: 0x4C */
53854   } RTX_CLK_CTL0;
53855   struct {                                         /* offset: 0x50 */
53856     __IO uint32_t RW;                                /**< HDMI_RTX_CLK_CTL1, offset: 0x50 */
53857     __IO uint32_t SET;                               /**< HDMI_RTX_CLK_CTL1, offset: 0x54 */
53858     __IO uint32_t CLR;                               /**< HDMI_RTX_CLK_CTL1, offset: 0x58 */
53859     __IO uint32_t TOG;                               /**< HDMI_RTX_CLK_CTL1, offset: 0x5C */
53860   } RTX_CLK_CTL1;
53861   struct {                                         /* offset: 0x60 */
53862     __IO uint32_t RW;                                /**< RTX_CLK_CTL2, offset: 0x60 */
53863     __IO uint32_t SET;                               /**< RTX_CLK_CTL2, offset: 0x64 */
53864     __IO uint32_t CLR;                               /**< RTX_CLK_CTL2, offset: 0x68 */
53865     __IO uint32_t TOG;                               /**< RTX_CLK_CTL2, offset: 0x6C */
53866   } RTX_CLK_CTL2;
53867   struct {                                         /* offset: 0x70 */
53868     __IO uint32_t RW;                                /**< RTX_CLK_CTL3, offset: 0x70 */
53869     __IO uint32_t SET;                               /**< RTX_CLK_CTL3, offset: 0x74 */
53870     __IO uint32_t CLR;                               /**< RTX_CLK_CTL3, offset: 0x78 */
53871     __IO uint32_t TOG;                               /**< RTX_CLK_CTL3, offset: 0x7C */
53872   } RTX_CLK_CTL3;
53873   struct {                                         /* offset: 0x80 */
53874     __IO uint32_t RW;                                /**< RTX_CLK_CTL4, offset: 0x80 */
53875     __IO uint32_t SET;                               /**< RTX_CLK_CTL4, offset: 0x84 */
53876     __IO uint32_t CLR;                               /**< RTX_CLK_CTL4, offset: 0x88 */
53877     __IO uint32_t TOG;                               /**< RTX_CLK_CTL4, offset: 0x8C */
53878   } RTX_CLK_CTL4;
53879   struct {                                         /* offset: 0x90 */
53880     __IO uint32_t RW;                                /**< HDMI_RX_Control, offset: 0x90 */
53881     __IO uint32_t SET;                               /**< HDMI_RX_Control, offset: 0x94 */
53882     __IO uint32_t CLR;                               /**< HDMI_RX_Control, offset: 0x98 */
53883     __IO uint32_t TOG;                               /**< HDMI_RX_Control, offset: 0x9C */
53884   } RTX_IRQ_MASK;
53885   struct {                                         /* offset: 0xA0 */
53886     __I  uint32_t RW;                                /**< HDMI_TX Masked Interrupt status, offset: 0xA0 */
53887     __I  uint32_t SET;                               /**< HDMI_TX Masked Interrupt status, offset: 0xA4 */
53888     __I  uint32_t CLR;                               /**< HDMI_TX Masked Interrupt status, offset: 0xA8 */
53889     __I  uint32_t TOG;                               /**< HDMI_TX Masked Interrupt status, offset: 0xAC */
53890   } RTX_IRQ_MASKED_STATUS;
53891   struct {                                         /* offset: 0xB0 */
53892     __IO uint32_t RW;                                /**< HDMI_RX_Control, offset: 0xB0 */
53893     __IO uint32_t SET;                               /**< HDMI_RX_Control, offset: 0xB4 */
53894     __IO uint32_t CLR;                               /**< HDMI_RX_Control, offset: 0xB8 */
53895     __IO uint32_t TOG;                               /**< HDMI_RX_Control, offset: 0xBC */
53896   } RTX_IRQ_NONMASK_STATUS;
53897        uint8_t RESERVED_1[320];
53898   struct {                                         /* offset: 0x200 */
53899     __IO uint32_t RW;                                /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x200 */
53900     __IO uint32_t SET;                               /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x204 */
53901     __IO uint32_t CLR;                               /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x208 */
53902     __IO uint32_t TOG;                               /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x20C */
53903   } TX_CONTROL0;
53904        uint8_t RESERVED_2[16];
53905   struct {                                         /* offset: 0x220 */
53906     __IO uint32_t RW;                                /**< TX Control, offset: 0x220 */
53907     __IO uint32_t SET;                               /**< TX Control, offset: 0x224 */
53908     __IO uint32_t CLR;                               /**< TX Control, offset: 0x228 */
53909     __IO uint32_t TOG;                               /**< TX Control, offset: 0x22C */
53910   } TX_CONTROL2;
53911   struct {                                         /* offset: 0x230 */
53912     __I  uint32_t RW;                                /**< Status, offset: 0x230 */
53913     __I  uint32_t SET;                               /**< Status, offset: 0x234 */
53914     __I  uint32_t CLR;                               /**< Status, offset: 0x238 */
53915     __I  uint32_t TOG;                               /**< Status, offset: 0x23C */
53916   } TX_STATUS0;
53917        uint8_t RESERVED_3[3456];
53918   struct {                                         /* offset: 0xFC0 */
53919     __IO uint32_t RW;                                /**< Spare Config, offset: 0xFC0 */
53920     __IO uint32_t SET;                               /**< Spare Config, offset: 0xFC4 */
53921     __IO uint32_t CLR;                               /**< Spare Config, offset: 0xFC8 */
53922     __IO uint32_t TOG;                               /**< Spare Config, offset: 0xFCC */
53923   } SPARE_CONFIG0;
53924        uint8_t RESERVED_4[32];
53925   struct {                                         /* offset: 0xFF0 */
53926     __I  uint32_t RW;                                /**< Spare Status0, offset: 0xFF0 */
53927     __I  uint32_t SET;                               /**< Spare Status0, offset: 0xFF4 */
53928     __I  uint32_t CLR;                               /**< Spare Status0, offset: 0xFF8 */
53929     __I  uint32_t TOG;                               /**< Spare Status0, offset: 0xFFC */
53930   } SPARE_STATUS0;
53931 } HDMI_TX_BLK_CTL_Type;
53932 
53933 /* ----------------------------------------------------------------------------
53934    -- HDMI_TX_BLK_CTL Register Masks
53935    ---------------------------------------------------------------------------- */
53936 
53937 /*!
53938  * @addtogroup HDMI_TX_BLK_CTL_Register_Masks HDMI_TX_BLK_CTL Register Masks
53939  * @{
53940  */
53941 
53942 /*! @name RTX_GENERAL - HDMI_RTX_GENERAL CONFIG */
53943 /*! @{ */
53944 
53945 #define HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_MASK (0x1U)
53946 #define HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_SHIFT (0U)
53947 /*! DEBUG_LOCKOUT_EN - RESERVED */
53948 #define HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_MASK)
53949 
53950 #define HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_MASK (0x30U)
53951 #define HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_SHIFT (4U)
53952 /*! HDCP_AXI_ADDR_EXTN - HDCP_AXI_ADDR_EXTN control */
53953 #define HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_MASK)
53954 
53955 #define HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_MASK (0x100U)
53956 #define HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_SHIFT (8U)
53957 /*! LCDIF_AXI_LIMIT_EN - Enables the AXI Read Beat count limiter; the beat limit value is given by the 16b value LCDIF_AXI_BEAT_LIMIT */
53958 #define HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_MASK)
53959 /*! @} */
53960 
53961 /*! @name RTX_GENERAL_1 - HDMI_RTX_GENERAL CONFIG */
53962 /*! @{ */
53963 
53964 #define HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_MASK (0xFFFFU)
53965 #define HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_SHIFT (0U)
53966 /*! LCDIF_AXI_BEAT_LIMIT - LCDIF_AXI_BEAT_LIMIT */
53967 #define HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_MASK)
53968 /*! @} */
53969 
53970 /*! @name RTX_RESET_CTL0 - HDMI_RTX_RESET_CTL0 */
53971 /*! @{ */
53972 
53973 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_MASK (0x1U)
53974 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_SHIFT (0U)
53975 /*! NOC_RESET_N - NOC_RESET_N control */
53976 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_MASK)
53977 
53978 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_MASK (0x10U)
53979 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_SHIFT (4U)
53980 /*! LCDIF_ASYNC_RESET_N - LCDIF_ASYNC_RESET_N control */
53981 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_MASK)
53982 
53983 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_MASK (0x20U)
53984 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_SHIFT (5U)
53985 /*! LCDIF_APB_RESET_N - LCDIF_APB_RESET_N control */
53986 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_MASK)
53987 
53988 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_MASK (0x40U)
53989 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_SHIFT (6U)
53990 /*! FDCC_RESETN - FDCC_RESETN control */
53991 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_MASK)
53992 
53993 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_MASK (0x80U)
53994 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_SHIFT (7U)
53995 /*! FDCC_HDMI_RESETN - FDCC_HDMI_RESETN control */
53996 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_MASK)
53997 
53998 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_MASK (0x400U)
53999 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_SHIFT (10U)
54000 /*! TX_RSTZ - TX_RSTZ control */
54001 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_MASK)
54002 
54003 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_MASK (0x800U)
54004 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_SHIFT (11U)
54005 /*! TX_APBRSTZ - TX_APBRSTZ control */
54006 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_MASK)
54007 
54008 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_MASK (0x1000U)
54009 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_SHIFT (12U)
54010 /*! TX_PHY_PRESETN - TX_PHY_PRESETN control */
54011 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_MASK)
54012 
54013 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_MASK (0x2000U)
54014 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_SHIFT (13U)
54015 /*! TX_KSV_MEM_RESETN - KSV Mem reset control */
54016 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_MASK)
54017 
54018 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_MASK (0x4000U)
54019 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_SHIFT (14U)
54020 /*! TX_SEC_MEM_RESETN - RESERVED */
54021 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_MASK)
54022 
54023 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_MASK (0x8000U)
54024 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_SHIFT (15U)
54025 /*! HRV_MWR_RESETN - HRV_MWR_RESETN control */
54026 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_MASK)
54027 
54028 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_MASK (0x10000U)
54029 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_SHIFT (16U)
54030 /*! IRQ_RESETN - IRQ_RESETN control */
54031 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_MASK)
54032 
54033 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_MASK (0x40000U)
54034 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_SHIFT (18U)
54035 /*! PAI_RESETN - PAI_RESETN control */
54036 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_MASK)
54037 
54038 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_MASK (0x100000U)
54039 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_SHIFT (20U)
54040 /*! TX_TRNG_RESETN - TX_TRNG_RESETN control */
54041 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_MASK)
54042 
54043 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_MASK (0x400000U)
54044 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_SHIFT (22U)
54045 /*! VID_LINK_SLV_RESETN - VID_LINK_SLV_RESETN control */
54046 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_MASK)
54047 
54048 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_MASK (0x800000U)
54049 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_SHIFT (23U)
54050 /*! VSFD_RESETN - VSFD_RESETN control */
54051 #define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_MASK)
54052 /*! @} */
54053 
54054 /*! @name RTX_CLK_CTL0 - HDMI_RTX_CLK_CTL0 */
54055 /*! @{ */
54056 
54057 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_MASK (0x1U)
54058 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_SHIFT (0U)
54059 /*! GLOBAL_APB_CLK_EN - GLOBAL_APB_CLK_EN control */
54060 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_MASK)
54061 
54062 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_MASK (0x2U)
54063 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_SHIFT (1U)
54064 /*! GLOBAL_B_CLK_EN - GLOBAL_B_CLK_EN control */
54065 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_MASK)
54066 
54067 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_MASK (0x4U)
54068 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_SHIFT (2U)
54069 /*! GLOBAL_REF266M_CLK_EN - GLOBAL_REF266M_CLK_EN control */
54070 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_MASK)
54071 
54072 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_MASK (0x8U)
54073 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_SHIFT (3U)
54074 /*! GLOBAL_XTAL27M_CLK_EN - GLOBAL_XTAL27M_CLK_EN control */
54075 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_MASK)
54076 
54077 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_MASK (0x10U)
54078 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_SHIFT (4U)
54079 /*! GLOBAL_XTAL24M_CLK_EN - GLOBAL_XTAL24M_CLK_EN control */
54080 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_MASK)
54081 
54082 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_MASK (0x20U)
54083 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_SHIFT (5U)
54084 /*! GLOBAL_XTAL32K_CLK_EN - GLOBAL_XTAL32K_CLK_EN control */
54085 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_MASK)
54086 
54087 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_MASK (0x40U)
54088 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_SHIFT (6U)
54089 /*! GLOBAL_AUD_PLL_CLK_EN - RESERVED */
54090 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_MASK)
54091 
54092 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_MASK (0x80U)
54093 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_SHIFT (7U)
54094 /*! GLOBAL_TX_PIX_CLK_EN - TX pix clk control */
54095 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_MASK)
54096 
54097 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_MASK (0x100U)
54098 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_SHIFT (8U)
54099 /*! PD1_CLK_EN - RESERVED */
54100 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_MASK)
54101 
54102 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_MASK (0x200U)
54103 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_SHIFT (9U)
54104 /*! IRQS_CLK_EN - clock control for the irq_steer block */
54105 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_MASK)
54106 
54107 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_MASK (0x400U)
54108 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_SHIFT (10U)
54109 /*! NOC_HDMI_CLK_EN - clock enable for the NOC bus_clk enable */
54110 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_MASK)
54111 
54112 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_MASK (0x800U)
54113 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_SHIFT (11U)
54114 /*! NOC_HDCP_CLK_EN - clock enable for the NOC hdcp_clk */
54115 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_MASK)
54116 
54117 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_MASK (0x10000U)
54118 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_SHIFT (16U)
54119 /*! LCDIF_APB_CLK_EN - clock enable for lcdif apb_clk input */
54120 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_MASK)
54121 
54122 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_MASK (0x20000U)
54123 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_SHIFT (17U)
54124 /*! LCDIF_B_CLK_EN - clock enable for lcdif bus_clk input */
54125 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_MASK)
54126 
54127 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_MASK (0x40000U)
54128 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_SHIFT (18U)
54129 /*! LCDIF_PDI_CLK_EN - clock enable for lcdif pdi_clk input */
54130 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_MASK)
54131 
54132 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_MASK (0x80000U)
54133 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_SHIFT (19U)
54134 /*! LCDIF_PIX_CLK_EN - clock enable for lcdif pix_clk input */
54135 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_MASK)
54136 
54137 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_MASK (0x100000U)
54138 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_SHIFT (20U)
54139 /*! LCDIF_SPU_CLK_EN - clock enable for lcdif spu_clk input */
54140 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_MASK)
54141 /*! @} */
54142 
54143 /*! @name RTX_CLK_CTL1 - HDMI_RTX_CLK_CTL1 */
54144 /*! @{ */
54145 
54146 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_MASK (0x2U)
54147 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_SHIFT (1U)
54148 /*! FDCC_IHDMI_CLK_EN - RESERVED */
54149 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_MASK)
54150 
54151 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_MASK (0x4U)
54152 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_SHIFT (2U)
54153 /*! FDCC_REF_CLK_EN - FDCC_REF_CLK_EN control */
54154 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_MASK)
54155 
54156 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_MASK (0x8U)
54157 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_SHIFT (3U)
54158 /*! HRV_MWR_APB_CLK_EN - HRV_MWR_APB_CLK_EN control */
54159 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_MASK)
54160 
54161 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_MASK (0x10U)
54162 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_SHIFT (4U)
54163 /*! HRV_MWR_B_CLK_EN - HRV_MWR_B_CLK_EN control */
54164 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_MASK)
54165 
54166 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_MASK (0x20U)
54167 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_SHIFT (5U)
54168 /*! HRV_MWR_CEA_CLK_EN - HRV_MWR_CEA_CLK_EN control */
54169 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_MASK)
54170 
54171 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_MASK (0x40U)
54172 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_SHIFT (6U)
54173 /*! VSFD_CEA_CLK_EN - VSFD_CEA_CLK_EN control */
54174 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_MASK)
54175 
54176 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_MASK (0x100U)
54177 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_SHIFT (8U)
54178 /*! vpll_clk_sel - RESERVED */
54179 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_MASK)
54180 
54181 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_MASK (0x200U)
54182 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_SHIFT (9U)
54183 /*! fdcc_clk_sel - RESERVED */
54184 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_MASK)
54185 
54186 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_MASK (0x400U)
54187 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_SHIFT (10U)
54188 /*! htxphy_clk_sel - htxphy_clk_sel control */
54189 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_MASK)
54190 
54191 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_MASK (0x800U)
54192 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_SHIFT (11U)
54193 /*! lcdif_clk_sel - lcdif_clk_sel control */
54194 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_MASK)
54195 
54196 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_MASK (0x1000U)
54197 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_SHIFT (12U)
54198 /*! HTX_PIPE_CLK_SEL - HTX_PIPE_CLK_SEL control */
54199 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_MASK)
54200 
54201 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_MASK (0x2000U)
54202 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_SHIFT (13U)
54203 /*! TX_HPI_CLK_EN - TX_HPI_CLK_EN control */
54204 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_MASK)
54205 
54206 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_MASK (0x4000U)
54207 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_SHIFT (14U)
54208 /*! TX_APB_CLK_EN - TX_APB_CLK_EN control */
54209 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_MASK)
54210 
54211 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_MASK (0x8000U)
54212 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_SHIFT (15U)
54213 /*! TX_CEC_CLK_EN - TX_CEC_CLK_EN control */
54214 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_MASK)
54215 
54216 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_MASK (0x10000U)
54217 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_SHIFT (16U)
54218 /*! TX_ESM_CLK_EN - TX_ESM_CLK_EN control */
54219 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_MASK)
54220 
54221 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_MASK (0x20000U)
54222 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_SHIFT (17U)
54223 /*! TX_GPA_CLK_EN - TX_GPA_CLK_EN control */
54224 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_MASK)
54225 
54226 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_MASK (0x40000U)
54227 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_SHIFT (18U)
54228 /*! TX_PIXEL_CLK_EN - TX_PIXEL_CLK_EN control */
54229 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_MASK)
54230 
54231 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_MASK (0x80000U)
54232 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_SHIFT (19U)
54233 /*! TX_SFR_CLK_EN - TX_SFR_CLK_EN control */
54234 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_MASK)
54235 
54236 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_MASK (0x100000U)
54237 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_SHIFT (20U)
54238 /*! TX_SKP_CLK_EN - TX_SKP_CLK_EN control */
54239 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_MASK)
54240 
54241 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_MASK (0x200000U)
54242 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_SHIFT (21U)
54243 /*! TX_PREP_CLK_EN - TX_PREP_CLK_EN control */
54244 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_MASK)
54245 
54246 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_MASK (0x400000U)
54247 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_SHIFT (22U)
54248 /*! TX_PHY_APB_CLK_EN - TX_PHY_APB_CLK_EN control */
54249 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_MASK)
54250 
54251 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_MASK (0x800000U)
54252 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_SHIFT (23U)
54253 /*! TX_PHY_PIXEL_CLK_EN - RESERVED */
54254 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_MASK)
54255 
54256 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_MASK (0x1000000U)
54257 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_SHIFT (24U)
54258 /*! TX_PHY_INT_CLK_EN - TX_PHY_INT_CLK_EN control */
54259 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_MASK)
54260 
54261 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_MASK (0x2000000U)
54262 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_SHIFT (25U)
54263 /*! TX_SEC_MEM_CLK_EN - TX_SEC_MEM_CLK_EN control */
54264 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_MASK)
54265 
54266 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_MASK (0x4000000U)
54267 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_SHIFT (26U)
54268 /*! PAI_CLK_EN - RESERVED */
54269 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_MASK)
54270 
54271 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_MASK (0x8000000U)
54272 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_SHIFT (27U)
54273 /*! TX_TRNG_SKP_CLK_EN - TX_TRNG_SKP_CLK_EN control */
54274 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_MASK)
54275 
54276 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_MASK (0x10000000U)
54277 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_SHIFT (28U)
54278 /*! TX_VID_LINK_PIX_CLK_EN - TX_VID_LINK_PIX_CLK_EN control */
54279 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_MASK)
54280 
54281 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_MASK (0x20000000U)
54282 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_SHIFT (29U)
54283 /*! TX_MEM_266M_CLK_EN - RESERVED */
54284 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_MASK)
54285 
54286 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_MASK (0x40000000U)
54287 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_SHIFT (30U)
54288 /*! TX_TRNG_APB_CLK_EN - TX_TRNG_APB_CLK_EN control */
54289 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_MASK)
54290 /*! @} */
54291 
54292 /*! @name RTX_CLK_CTL2 - RTX_CLK_CTL2 */
54293 /*! @{ */
54294 
54295 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_MASK (0x3U)
54296 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_SHIFT (0U)
54297 /*! IRQS_CLK_CTL - Used to bypass the programmable clock controls for IRQ_STEER */
54298 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_MASK)
54299 
54300 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_MASK (0xCU)
54301 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_SHIFT (2U)
54302 /*! FDCC_APB_CLK_CTL - Used to bypass the programmable clock controls for FDCC apb clock */
54303 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_MASK)
54304 
54305 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_MASK (0x30U)
54306 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_SHIFT (4U)
54307 /*! FDCC_REF_CLK_CTL - Used to bypass the programmable clock controls for FDCC ref clock */
54308 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_MASK)
54309 
54310 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_MASK (0xC0U)
54311 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_SHIFT (6U)
54312 /*! HDMI_TX_HPI_CLK_CTL - Used to bypass the programmable clock controls for hpi_clk input of HDMI TX */
54313 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_MASK)
54314 
54315 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_MASK (0x300U)
54316 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_SHIFT (8U)
54317 /*! HDMI_TX_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of HDMI TX */
54318 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_MASK)
54319 
54320 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_MASK (0xC00U)
54321 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_SHIFT (10U)
54322 /*! HDMI_TX_CEC_CLK_CTL - Used to bypass the programmable clock controls for cec_clk input of HDMI TX */
54323 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_MASK)
54324 
54325 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_MASK (0x3000U)
54326 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_SHIFT (12U)
54327 /*! HDMI_TX_ESM_CLK_CTL - Used to bypass the programmable clock controls for esm_clk input of HDMI TX */
54328 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_MASK)
54329 
54330 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_MASK (0xC000U)
54331 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_SHIFT (14U)
54332 /*! HDMI_TX_GPA_CLK_CTL - Used to bypass the programmable clock controls for gpa_clk input of HDMI TX */
54333 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_MASK)
54334 
54335 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_MASK (0x30000U)
54336 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_SHIFT (16U)
54337 /*! HDMI_TX_PIX_CLK_CTL - Used to bypass the programmable clock controls for ipixel_clk input of HDMI TX */
54338 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_MASK)
54339 
54340 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_MASK (0xC0000U)
54341 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_SHIFT (18U)
54342 /*! HDMI_TX_SFR_CLK_CTL - Used to bypass the programmable clock controls for sfr_clk input of HDMI TX */
54343 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_MASK)
54344 
54345 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_MASK (0x300000U)
54346 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_SHIFT (20U)
54347 /*! HDMI_TX_SKP_CLK_CTL - Used to bypass the programmable clock controls for skp_clk input of HDMI TX */
54348 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_MASK)
54349 
54350 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_MASK (0xC00000U)
54351 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_SHIFT (22U)
54352 /*! HDMI_TX_PREP_CLK_CTL - Used to bypass the programmable clock controls for prep_clk input of HDMI TX */
54353 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_MASK)
54354 
54355 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_MASK (0x3000000U)
54356 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_SHIFT (24U)
54357 /*! TX_PHY_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of the HDMI TX PHY */
54358 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_MASK)
54359 
54360 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_MASK (0xC000000U)
54361 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_SHIFT (26U)
54362 /*! TX_PHY_INT_CLK_CTL - Used to bypass the programmable clock controls for int_clk input of the HDMI TX PHY */
54363 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_MASK)
54364 
54365 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_MASK (0x30000000U)
54366 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_SHIFT (28U)
54367 /*! PAI_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of HTX_PAI */
54368 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_MASK)
54369 
54370 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_MASK (0xC0000000U)
54371 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_SHIFT (30U)
54372 /*! PAI_AUD_CLK_CTL - Used to bypass the programmable clock controls for aud_clk input of HTX_PAI */
54373 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_MASK)
54374 /*! @} */
54375 
54376 /*! @name RTX_CLK_CTL3 - RTX_CLK_CTL3 */
54377 /*! @{ */
54378 
54379 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_MASK (0x3U)
54380 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_SHIFT (0U)
54381 /*! TRNG_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of TRNG */
54382 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_MASK)
54383 
54384 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_MASK (0xCU)
54385 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_SHIFT (2U)
54386 /*! TRNG_SKP_CLK_CTL - Used to bypass the programmable clock controls for skp_clk input of TRNG */
54387 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_MASK)
54388 
54389 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_MASK (0x30U)
54390 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_SHIFT (4U)
54391 /*! VID_SLV_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of video link slave */
54392 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_MASK)
54393 
54394 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_MASK (0xC0U)
54395 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_SHIFT (6U)
54396 /*! VID_SLV_PIX_CLK_CTL - Used to bypass the programmable clock controls for pix_clk input of video link slave */
54397 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_MASK)
54398 
54399 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_MASK (0x300U)
54400 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_SHIFT (8U)
54401 /*! HRV_MWR_B_CLK_CTL - Used to bypass the programmable clock controls for b_clk input of HRV_MWR */
54402 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_MASK)
54403 
54404 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_MASK (0xC00U)
54405 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_SHIFT (10U)
54406 /*! HRV_MWR_CEA_CLK_CTL - Used to bypass the programmable clock controls for cea_clk input of HRV_MWR */
54407 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_MASK)
54408 
54409 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_MASK (0x3000U)
54410 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_SHIFT (12U)
54411 /*! VSFD_HTX_APB_CLK_CTL - Used to bypass the programmable clock controls for the apb clk input of VSFD (including portions of HRV_MWR logic) */
54412 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_MASK)
54413 
54414 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_MASK (0xC000U)
54415 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_SHIFT (14U)
54416 /*! VSFD_HTX_P_CLK_CTL - Used to bypass the programmable clock controls for the htx_p_clk input used
54417  *    in VSFD (including portions of HRV_MWR logic)
54418  */
54419 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_MASK)
54420 
54421 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_MASK (0x30000U)
54422 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_SHIFT (16U)
54423 /*! VSFD_CEA_CLK_CTL - Used to bypass the programmable clock controls for cea_clk input of vsfd */
54424 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_MASK)
54425 
54426 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_MASK (0xC0000U)
54427 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_SHIFT (18U)
54428 /*! LCDIF_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of LCDIF */
54429 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_MASK)
54430 
54431 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_MASK (0x300000U)
54432 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_SHIFT (20U)
54433 /*! LCDIF_B_CLK_CTL - Used to bypass the programmable clock controls for b_clk input of LCDIF */
54434 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_MASK)
54435 
54436 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_MASK (0xC00000U)
54437 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_SHIFT (22U)
54438 /*! LCDIF_PDI_CLK_CTL - Used to bypass the programmable clock controls for pdi_clk input of LCDIF */
54439 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_MASK)
54440 
54441 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_MASK (0x3000000U)
54442 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_SHIFT (24U)
54443 /*! LCDIF_PIX_CLK_CTL - Used to bypass the programmable clock controls for pix_clk input of LCDIF */
54444 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_MASK)
54445 
54446 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_MASK (0xC000000U)
54447 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_SHIFT (26U)
54448 /*! LCDIF_SPU_CLK_CTL - Used to bypass the programmable clock controls for spu_clk input of LCDIF */
54449 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_MASK)
54450 
54451 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_MASK (0x30000000U)
54452 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_SHIFT (28U)
54453 /*! NOC_HDCP_CLK_CTL - Used to bypass the programmable clock controls for hdcp clock input of the HDMI NOC */
54454 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_MASK)
54455 
54456 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_MASK (0xC0000000U)
54457 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_SHIFT (30U)
54458 /*! NOC_B_CLK_CTL - Used to bypass the programmable clock controls for bus clock input of the HDMI NOC */
54459 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_MASK)
54460 /*! @} */
54461 
54462 /*! @name RTX_CLK_CTL4 - RTX_CLK_CTL4 */
54463 /*! @{ */
54464 
54465 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_MASK (0x3U)
54466 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_SHIFT (0U)
54467 /*! REVOCMEM_CLK_CTL - Used to bypass the request based clock gating on revocmem */
54468 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_MASK)
54469 
54470 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_MASK (0xCU)
54471 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_SHIFT (2U)
54472 /*! TX_SEC_MEM_CLK_CTL - Used to bypass the request based clock gating on tx_sec_mem */
54473 #define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_MASK)
54474 /*! @} */
54475 
54476 /*! @name RTX_IRQ_MASK - HDMI_RX_Control */
54477 /*! @{ */
54478 
54479 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_MASK (0x1000U)
54480 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_SHIFT (12U)
54481 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_MASK)
54482 
54483 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_MASK (0x2000U)
54484 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_SHIFT (13U)
54485 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_MASK)
54486 
54487 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_MASK (0x4000U)
54488 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_SHIFT (14U)
54489 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_MASK)
54490 
54491 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_MASK (0x8000U)
54492 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_SHIFT (15U)
54493 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_MASK)
54494 /*! @} */
54495 
54496 /*! @name RTX_IRQ_MASKED_STATUS - HDMI_TX Masked Interrupt status */
54497 /*! @{ */
54498 
54499 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_MASK (0x1000U)
54500 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_SHIFT (12U)
54501 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_MASK)
54502 
54503 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_MASK (0x2000U)
54504 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_SHIFT (13U)
54505 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_MASK)
54506 
54507 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_MASK (0x4000U)
54508 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_SHIFT (14U)
54509 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_MASK)
54510 
54511 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_MASK (0x8000U)
54512 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_SHIFT (15U)
54513 #define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_MASK)
54514 /*! @} */
54515 
54516 /*! @name RTX_IRQ_NONMASK_STATUS - HDMI_RX_Control */
54517 /*! @{ */
54518 
54519 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_MASK (0x1000U)
54520 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_SHIFT (12U)
54521 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_MASK)
54522 
54523 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_MASK (0x2000U)
54524 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_SHIFT (13U)
54525 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_MASK)
54526 
54527 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_MASK (0x4000U)
54528 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_SHIFT (14U)
54529 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_MASK)
54530 
54531 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_MASK (0x8000U)
54532 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_SHIFT (15U)
54533 #define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_MASK)
54534 /*! @} */
54535 
54536 /*! @name TX_CONTROL0 - Miscellaneous Controls for the HDMI TX Controller */
54537 /*! @{ */
54538 
54539 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_MASK (0x1U)
54540 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_SHIFT (0U)
54541 /*! TX_KEY_MEM_WR_LOCK - TX_KEY_MEM_WR_LOCK control */
54542 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_MASK)
54543 
54544 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_MASK (0x2U)
54545 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_SHIFT (1U)
54546 /*! TX_CEC_EN - TX_CEC_EN control */
54547 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_MASK)
54548 
54549 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_MASK (0x4U)
54550 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_SHIFT (2U)
54551 /*! TX_SKP_KEYS_VALID - RESERVED */
54552 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_MASK)
54553 
54554 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_MASK (0x8U)
54555 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_SHIFT (3U)
54556 /*! TX_PHY_PDOWN - TX_PHY_PDOWN control */
54557 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_MASK)
54558 
54559 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_MASK (0x1F0U)
54560 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_SHIFT (4U)
54561 /*! TX_CTL_CLK_DIV_CNT - RESERVED */
54562 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_MASK)
54563 
54564 #define HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_MASK (0x7000U)
54565 #define HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_SHIFT (12U)
54566 /*! LCDIF_NOC_HURRY - LCDIF_NOC_HURRY */
54567 #define HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_MASK)
54568 
54569 #define HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_MASK (0x70000U)
54570 #define HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_SHIFT (16U)
54571 /*! HRV_MWR_NOC_HURRY - HRV_MWR_NOC_HURRY */
54572 #define HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_MASK)
54573 
54574 #define HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_MASK (0x100000U)
54575 #define HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_SHIFT (20U)
54576 /*! HPD_FILT_BYP - HPD_FILT_BYP */
54577 #define HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_MASK)
54578 
54579 #define HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_MASK (0x200000U)
54580 #define HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_SHIFT (21U)
54581 /*! CECIN_FILT_BYP - CECIN_FILT_BYP */
54582 #define HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_MASK)
54583 
54584 #define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_MASK (0x400000U)
54585 #define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_SHIFT (22U)
54586 /*! DDC_SCLIN_FILT_BYP - DDC_SCLIN_FILT_BYP */
54587 #define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_MASK)
54588 
54589 #define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_MASK (0x800000U)
54590 #define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_SHIFT (23U)
54591 /*! DDC_SDAIN_FILT_BYP - DDC_SDAIN_FILT_BYP */
54592 #define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_MASK)
54593 
54594 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_MASK (0x1000000U)
54595 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_SHIFT (24U)
54596 /*! TRNG_LOCK - TRNG_LOCK control */
54597 #define HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_MASK)
54598 /*! @} */
54599 
54600 /*! @name TX_CONTROL2 - TX Control */
54601 /*! @{ */
54602 
54603 #define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_MASK (0x3FF0U)
54604 #define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_SHIFT (4U)
54605 /*! TX_PREPCLK_TOT_COUNT - TX_PREPCLK_TOT_COUNT control */
54606 #define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_MASK)
54607 
54608 #define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_MASK (0x3FF0000U)
54609 #define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_SHIFT (16U)
54610 /*! TX_PREPCLK_ACTCYC_COUNT - TX_PREPCLK_ACTCYC_COUNT control */
54611 #define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_MASK)
54612 /*! @} */
54613 
54614 /*! @name TX_STATUS0 - Status */
54615 /*! @{ */
54616 
54617 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_MASK (0x1FU)
54618 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_SHIFT (0U)
54619 /*! TX_PHY_AFC_CODE - TX_PHY_AFC_CODE status */
54620 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_MASK)
54621 
54622 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_MASK (0x20U)
54623 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_SHIFT (5U)
54624 /*! TX_PHY_CLK_RDY - TX_PHY_CLK_RDY status */
54625 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_MASK)
54626 
54627 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_MASK (0x40U)
54628 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_SHIFT (6U)
54629 /*! TX_PHY_RDY - TX_PHY_RDY status */
54630 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_MASK)
54631 
54632 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_MASK (0x80U)
54633 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_SHIFT (7U)
54634 /*! TX_PHY_PLL_LOCK - TX_PHY_PLL_LOCK status */
54635 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_MASK)
54636 
54637 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_MASK (0x100U)
54638 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_SHIFT (8U)
54639 /*! TX_HPD_STATUS - TX_HPD_STATUS status */
54640 #define HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_MASK)
54641 /*! @} */
54642 
54643 /*! @name SPARE_CONFIG0 - Spare Config */
54644 /*! @{ */
54645 
54646 #define HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_MASK (0xFFFFFFFFU)
54647 #define HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_SHIFT (0U)
54648 #define HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_SHIFT)) & HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_MASK)
54649 /*! @} */
54650 
54651 /*! @name SPARE_STATUS0 - Spare Status0 */
54652 /*! @{ */
54653 
54654 #define HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK (0xFFFFFFFFU)
54655 #define HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT (0U)
54656 /*! SPARE_STATUS - SPARE Control */
54657 #define HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT)) & HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK)
54658 /*! @} */
54659 
54660 
54661 /*!
54662  * @}
54663  */ /* end of group HDMI_TX_BLK_CTL_Register_Masks */
54664 
54665 
54666 /* HDMI_TX_BLK_CTL - Peripheral instance base addresses */
54667 /** Peripheral HDMI_TX_BLK_CTRL base address */
54668 #define HDMI_TX_BLK_CTRL_BASE                    (0x32FC0000u)
54669 /** Peripheral HDMI_TX_BLK_CTRL base pointer */
54670 #define HDMI_TX_BLK_CTRL                         ((HDMI_TX_BLK_CTL_Type *)HDMI_TX_BLK_CTRL_BASE)
54671 /** Array initializer of HDMI_TX_BLK_CTL peripheral base addresses */
54672 #define HDMI_TX_BLK_CTL_BASE_ADDRS               { HDMI_TX_BLK_CTRL_BASE }
54673 /** Array initializer of HDMI_TX_BLK_CTL peripheral base pointers */
54674 #define HDMI_TX_BLK_CTL_BASE_PTRS                { HDMI_TX_BLK_CTRL }
54675 
54676 /*!
54677  * @}
54678  */ /* end of group HDMI_TX_BLK_CTL_Peripheral_Access_Layer */
54679 
54680 
54681 /* ----------------------------------------------------------------------------
54682    -- HSIO_BLK_CTRL Peripheral Access Layer
54683    ---------------------------------------------------------------------------- */
54684 
54685 /*!
54686  * @addtogroup HSIO_BLK_CTRL_Peripheral_Access_Layer HSIO_BLK_CTRL Peripheral Access Layer
54687  * @{
54688  */
54689 
54690 /** HSIO_BLK_CTRL - Register Layout Typedef */
54691 typedef struct {
54692   __IO uint32_t GPR_REG0;                          /**< Clock select reset and debug info select, offset: 0x0 */
54693   __I  uint32_t GPR_REG1;                          /**< PCIE controller status, offset: 0x4 */
54694   __IO uint32_t GPR_REG2;                          /**< PLL configuration 0, offset: 0x8 */
54695   __IO uint32_t GPR_REG3;                          /**< PLL configuration 1, offset: 0xC */
54696   __IO uint32_t GPR_REG4;                          /**< PCIE PME message and error detect register, offset: 0x10 */
54697   __IO uint32_t GPR_REG5;                          /**< PCIE PME message and error detect interrupt enable register, offset: 0x14 */
54698   __IO uint32_t GPR_REG6;                          /**< PCIE PME message and error detect interrupt detect disable register, offset: 0x18 */
54699   __IO uint32_t GPR_REG7;                          /**< USB1 beat limit and enable, offset: 0x1C */
54700   __IO uint32_t GPR_REG8;                          /**< USB2 beat limit and enable, offset: 0x20 */
54701   __IO uint32_t GPR_REG9;                          /**< PCIE beat limit and enable, offset: 0x24 */
54702        uint8_t RESERVED_0[216];
54703   __IO uint32_t USB1_WAKEUP_CTRL;                  /**< Register for USB1 wakeup, offset: 0x100 */
54704   __I  uint32_t USB1_WAKEUP_STATUS;                /**< Status of USB1 wakeup, offset: 0x104 */
54705   __IO uint32_t USB2_WAKEUP_CTRL;                  /**< Register for USB2 wakeup, offset: 0x108 */
54706   __I  uint32_t USB2_WAKEUP_STATUS;                /**< Status of USB2 wakeup, offset: 0x10C */
54707 } HSIO_BLK_CTRL_Type;
54708 
54709 /* ----------------------------------------------------------------------------
54710    -- HSIO_BLK_CTRL Register Masks
54711    ---------------------------------------------------------------------------- */
54712 
54713 /*!
54714  * @addtogroup HSIO_BLK_CTRL_Register_Masks HSIO_BLK_CTRL Register Masks
54715  * @{
54716  */
54717 
54718 /*! @name GPR_REG0 - Clock select reset and debug info select */
54719 /*! @{ */
54720 
54721 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_MASK (0x1U)
54722 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_SHIFT (0U)
54723 /*! PCIE_CLOCK_MODULE_EN - PCIE related clock enable */
54724 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_MASK)
54725 
54726 #define HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_MASK (0x2U)
54727 #define HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_SHIFT (1U)
54728 /*! USB_CLOCK_MODULE_EN - USB related clock enable */
54729 #define HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_MASK)
54730 
54731 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_MASK (0xCU)
54732 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_SHIFT (2U)
54733 /*! PCIE_USB_DEBUG_INFO_SEL - PCIE USB debug information selection */
54734 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_MASK)
54735 
54736 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_MASK (0x10U)
54737 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_SHIFT (4U)
54738 /*! PCIE_PHY_APB_RESETN_INTERNAL - PCIE PHY APB interface reset */
54739 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_MASK)
54740 
54741 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_MASK (0x20U)
54742 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_SHIFT (5U)
54743 /*! PCIE_PHY_INIT_RESETN_INTERNAL - PCIE PHY init reset */
54744 #define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_MASK)
54745 
54746 #define HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_MASK (0x40U)
54747 #define HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_SHIFT (6U)
54748 /*! USB_PHY_REF_CLK_SEL - USB PHY ref clock selection
54749  *  0b0..24Mhz exteral osc
54750  *  0b1..100Mhz high performace PLL
54751  */
54752 #define HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_MASK)
54753 
54754 #define HSIO_BLK_CTRL_GPR_REG0_CFG_READY_MASK    (0x80U)
54755 #define HSIO_BLK_CTRL_GPR_REG0_CFG_READY_SHIFT   (7U)
54756 /*! CFG_READY - Configuration ready */
54757 #define HSIO_BLK_CTRL_GPR_REG0_CFG_READY(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_CFG_READY_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_CFG_READY_MASK)
54758 
54759 #define HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_MASK    (0x100U)
54760 #define HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_SHIFT   (8U)
54761 /*! CRS_CLEAR - Clear CSR interrupt */
54762 #define HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_MASK)
54763 /*! @} */
54764 
54765 /*! @name GPR_REG1 - PCIE controller status */
54766 /*! @{ */
54767 
54768 #define HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_MASK (0x1U)
54769 #define HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_SHIFT (0U)
54770 /*! PM_EN_CORE_CLK - pm_en_core_clk pin status of pcie ctrl */
54771 #define HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_MASK)
54772 
54773 #define HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_MASK (0x7EU)
54774 #define HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_SHIFT (1U)
54775 /*! SMLH_LTSSM_STATE - PCIE link state */
54776 #define HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_MASK)
54777 
54778 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_MASK (0x80U)
54779 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_SHIFT (7U)
54780 /*! PCIE_CTRL_PM_LINKST_IN_L1SUB - PCIE ctrl link in l1sub state */
54781 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_MASK)
54782 
54783 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_MASK (0x100U)
54784 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_SHIFT (8U)
54785 /*! PCIE_CTRL_PM_LINKST_IN_L1 - PCIE ctrl link in l1 state */
54786 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_MASK)
54787 
54788 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_MASK (0x200U)
54789 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_SHIFT (9U)
54790 /*! PCIE_CTRL_PM_LINKST_IN_L0S - PCIE ctrl link in l0s state */
54791 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_MASK)
54792 
54793 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_MASK (0x1C00U)
54794 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_SHIFT (10U)
54795 /*! PCIE_CTRL_PM_DSTATE - PCIE ctrl's pm dstate */
54796 #define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_MASK)
54797 
54798 #define HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_MASK     (0x2000U)
54799 #define HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_SHIFT    (13U)
54800 /*! PLL_LOCK - High performance PLL lock status */
54801 #define HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_MASK)
54802 /*! @} */
54803 
54804 /*! @name GPR_REG2 - PLL configuration 0 */
54805 /*! @{ */
54806 
54807 #define HSIO_BLK_CTRL_GPR_REG2_P_PLL_MASK        (0x3FU)
54808 #define HSIO_BLK_CTRL_GPR_REG2_P_PLL_SHIFT       (0U)
54809 /*! P_PLL - P pin input of high performance PLL */
54810 #define HSIO_BLK_CTRL_GPR_REG2_P_PLL(x)          (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_P_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_P_PLL_MASK)
54811 
54812 #define HSIO_BLK_CTRL_GPR_REG2_M_PLL_MASK        (0xFFC0U)
54813 #define HSIO_BLK_CTRL_GPR_REG2_M_PLL_SHIFT       (6U)
54814 /*! M_PLL - M pin input of high performance PLL */
54815 #define HSIO_BLK_CTRL_GPR_REG2_M_PLL(x)          (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_M_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_M_PLL_MASK)
54816 
54817 #define HSIO_BLK_CTRL_GPR_REG2_S_PLL_MASK        (0x70000U)
54818 #define HSIO_BLK_CTRL_GPR_REG2_S_PLL_SHIFT       (16U)
54819 /*! S_PLL - S pin input of high performance PLL */
54820 #define HSIO_BLK_CTRL_GPR_REG2_S_PLL(x)          (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_S_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_S_PLL_MASK)
54821 
54822 #define HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_MASK      (0x180000U)
54823 #define HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_SHIFT     (19U)
54824 /*! ICP_PLL - ICP pin input of high performance PLL */
54825 #define HSIO_BLK_CTRL_GPR_REG2_ICP_PLL(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_MASK)
54826 
54827 #define HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_MASK   (0x200000U)
54828 #define HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_SHIFT  (21U)
54829 /*! BYPASS_PLL - Bypass pin input of high performance PLL */
54830 #define HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL(x)     (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_MASK)
54831 
54832 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_MASK  (0x400000U)
54833 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_SHIFT (22U)
54834 /*! LOCK_EN_PLL - locken pin input of high performance PLL */
54835 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_MASK)
54836 
54837 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_MASK (0x1800000U)
54838 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_SHIFT (23U)
54839 /*! LOCK_CON_IN_PLL - Lock con in pin input of high performance PLL */
54840 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_MASK)
54841 
54842 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_MASK (0x6000000U)
54843 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_SHIFT (25U)
54844 /*! LOCK_CON_OUT_PLL - Lock con input of high performance PLL */
54845 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_MASK)
54846 
54847 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_MASK (0x18000000U)
54848 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_SHIFT (27U)
54849 /*! LOCK_CON_DLY_PLL - Lock con delay input of high performance PLL */
54850 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_MASK)
54851 
54852 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_MASK (0x60000000U)
54853 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_SHIFT (29U)
54854 /*! LOCK_CON_REV_PLL - Lock con rev pin input of high performance PLL */
54855 #define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_MASK)
54856 
54857 #define HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_MASK  (0x80000000U)
54858 #define HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_SHIFT (31U)
54859 /*! AFC_ENB_PLL - AFC_ENB input of high performance PLL */
54860 #define HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_MASK)
54861 /*! @} */
54862 
54863 /*! @name GPR_REG3 - PLL configuration 1 */
54864 /*! @{ */
54865 
54866 #define HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_MASK   (0x1FU)
54867 #define HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_SHIFT  (0U)
54868 /*! EXTAFC_PLL - Extafc pin input of high performance PLL */
54869 #define HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL(x)     (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_MASK)
54870 
54871 #define HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_MASK  (0x20U)
54872 #define HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_SHIFT (5U)
54873 /*! FEED_EN_PLL - Feed en pin input of high performance PLL */
54874 #define HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL(x)    (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_MASK)
54875 
54876 #define HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_MASK     (0x40U)
54877 #define HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_SHIFT    (6U)
54878 /*! FSEL_PLL - FSEL pin input of high performance PLL */
54879 #define HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_MASK)
54880 
54881 #define HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_MASK (0x80U)
54882 #define HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_SHIFT (7U)
54883 /*! AFCINIT_SEL_PLL - AFCINT SEL input of high performance PLL */
54884 #define HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_MASK)
54885 
54886 #define HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_MASK (0x100U)
54887 #define HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_SHIFT (8U)
54888 /*! FOUT_MASK_PLL - FOUT MASK pin input of high performance PLL */
54889 #define HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL(x)  (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_MASK)
54890 
54891 #define HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_MASK (0x200U)
54892 #define HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_SHIFT (9U)
54893 /*! VCO_BOOST_PLL - VCO BOOST pin input of high performance PLL */
54894 #define HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL(x)  (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_MASK)
54895 
54896 #define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_MASK (0x400U)
54897 #define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_SHIFT (10U)
54898 /*! PBIAS_CTRL_EN_PLL - PBIAS CTRL EN pin input of high performance PLL */
54899 #define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_MASK)
54900 
54901 #define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_MASK (0x800U)
54902 #define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_SHIFT (11U)
54903 /*! PBIAS_CTRL_PLL - PBIAS CTRL pin input of high performance PLL */
54904 #define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_MASK)
54905 
54906 #define HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_MASK   (0x1000U)
54907 #define HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_SHIFT  (12U)
54908 /*! LRD_EN_PLL - LRD EN pin input of high performance PLL */
54909 #define HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL(x)     (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_MASK)
54910 
54911 #define HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_MASK     (0x1E000U)
54912 #define HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_SHIFT    (13U)
54913 /*! RSEL_PLL - RSEL pin input of high performance PLL */
54914 #define HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_MASK)
54915 
54916 #define HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_MASK      (0x20000U)
54917 #define HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_SHIFT     (17U)
54918 /*! PLL_CKE - PLL cke pin input of high performance PLL */
54919 #define HSIO_BLK_CTRL_GPR_REG3_PLL_CKE(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_MASK)
54920 
54921 #define HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_MASK (0x40000U)
54922 #define HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_SHIFT (18U)
54923 /*! PLL_EXT_BYPASS - PLL ext bypass pin input of high performance PLL */
54924 #define HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_MASK)
54925 
54926 #define HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_MASK   (0x80000000U)
54927 #define HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_SHIFT  (31U)
54928 /*! PLL_RESETB - reset pin input of high performance PLL */
54929 #define HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB(x)     (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_MASK)
54930 /*! @} */
54931 
54932 /*! @name GPR_REG4 - PCIE PME message and error detect register */
54933 /*! @{ */
54934 
54935 #define HSIO_BLK_CTRL_GPR_REG4_LUD_MASK          (0x1U)
54936 #define HSIO_BLK_CTRL_GPR_REG4_LUD_SHIFT         (0U)
54937 /*! LUD - Indicates a link up was detected */
54938 #define HSIO_BLK_CTRL_GPR_REG4_LUD(x)            (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_LUD_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_LUD_MASK)
54939 
54940 #define HSIO_BLK_CTRL_GPR_REG4_LDD_MASK          (0x2U)
54941 #define HSIO_BLK_CTRL_GPR_REG4_LDD_SHIFT         (1U)
54942 /*! LDD - Indicates a link down was detected */
54943 #define HSIO_BLK_CTRL_GPR_REG4_LDD(x)            (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_LDD_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_LDD_MASK)
54944 
54945 #define HSIO_BLK_CTRL_GPR_REG4_HRD_MASK          (0x4U)
54946 #define HSIO_BLK_CTRL_GPR_REG4_HRD_SHIFT         (2U)
54947 /*! HRD - Indicates a hot reset was detected */
54948 #define HSIO_BLK_CTRL_GPR_REG4_HRD(x)            (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_HRD_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_HRD_MASK)
54949 
54950 #define HSIO_BLK_CTRL_GPR_REG4_PTO_MASK          (0x8U)
54951 #define HSIO_BLK_CTRL_GPR_REG4_PTO_SHIFT         (3U)
54952 /*! PTO - Indicates that PME turn off was detected */
54953 #define HSIO_BLK_CTRL_GPR_REG4_PTO(x)            (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_PTO_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_PTO_MASK)
54954 
54955 #define HSIO_BLK_CTRL_GPR_REG4_UREP_MASK         (0x10U)
54956 #define HSIO_BLK_CTRL_GPR_REG4_UREP_SHIFT        (4U)
54957 /*! UREP - Indicates an unsupported request completion was detected */
54958 #define HSIO_BLK_CTRL_GPR_REG4_UREP(x)           (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_UREP_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_UREP_MASK)
54959 
54960 #define HSIO_BLK_CTRL_GPR_REG4_CDNSC_MASK        (0x20U)
54961 #define HSIO_BLK_CTRL_GPR_REG4_CDNSC_SHIFT       (5U)
54962 /*! CDNSC - Completion with data not succsessful was detected. */
54963 #define HSIO_BLK_CTRL_GPR_REG4_CDNSC(x)          (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_CDNSC_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_CDNSC_MASK)
54964 
54965 #define HSIO_BLK_CTRL_GPR_REG4_PCAC_MASK         (0x40U)
54966 #define HSIO_BLK_CTRL_GPR_REG4_PCAC_SHIFT        (6U)
54967 /*! PCAC - Completer abort was detected. */
54968 #define HSIO_BLK_CTRL_GPR_REG4_PCAC(x)           (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_PCAC_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_PCAC_MASK)
54969 
54970 #define HSIO_BLK_CTRL_GPR_REG4_PCT_MASK          (0x80U)
54971 #define HSIO_BLK_CTRL_GPR_REG4_PCT_SHIFT         (7U)
54972 /*! PCT - Indicates completion timeout */
54973 #define HSIO_BLK_CTRL_GPR_REG4_PCT(x)            (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_PCT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_PCT_MASK)
54974 
54975 #define HSIO_BLK_CTRL_GPR_REG4_ME_MASK           (0x100U)
54976 #define HSIO_BLK_CTRL_GPR_REG4_ME_SHIFT          (8U)
54977 /*! ME - Indicates Multiple errors of same type. If any of the detectable errors in PEX_ERR_DET
54978  *    register is detected more than one time the ME bit will be set
54979  */
54980 #define HSIO_BLK_CTRL_GPR_REG4_ME(x)             (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_ME_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_ME_MASK)
54981 
54982 #define HSIO_BLK_CTRL_GPR_REG4_INTE_MASK         (0x40000000U)
54983 #define HSIO_BLK_CTRL_GPR_REG4_INTE_SHIFT        (30U)
54984 /*! INTE - Per PF dependent error interrupt is pending. */
54985 #define HSIO_BLK_CTRL_GPR_REG4_INTE(x)           (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_INTE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_INTE_MASK)
54986 
54987 #define HSIO_BLK_CTRL_GPR_REG4_INTM_MASK         (0x80000000U)
54988 #define HSIO_BLK_CTRL_GPR_REG4_INTM_SHIFT        (31U)
54989 /*! INTM - Per PF dependent message interrupt is pending */
54990 #define HSIO_BLK_CTRL_GPR_REG4_INTM(x)           (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_INTM_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_INTM_MASK)
54991 /*! @} */
54992 
54993 /*! @name GPR_REG5 - PCIE PME message and error detect interrupt enable register */
54994 /*! @{ */
54995 
54996 #define HSIO_BLK_CTRL_GPR_REG5_LUD_IE_MASK       (0x1U)
54997 #define HSIO_BLK_CTRL_GPR_REG5_LUD_IE_SHIFT      (0U)
54998 /*! LUD_IE - Link up detect interrupt enable */
54999 #define HSIO_BLK_CTRL_GPR_REG5_LUD_IE(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_LUD_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_LUD_IE_MASK)
55000 
55001 #define HSIO_BLK_CTRL_GPR_REG5_LDD_IE_MASK       (0x2U)
55002 #define HSIO_BLK_CTRL_GPR_REG5_LDD_IE_SHIFT      (1U)
55003 /*! LDD_IE - Link down detect interrupt enable */
55004 #define HSIO_BLK_CTRL_GPR_REG5_LDD_IE(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_LDD_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_LDD_IE_MASK)
55005 
55006 #define HSIO_BLK_CTRL_GPR_REG5_HRD_IE_MASK       (0x4U)
55007 #define HSIO_BLK_CTRL_GPR_REG5_HRD_IE_SHIFT      (2U)
55008 /*! HRD_IE - Hot reset detect interrupt enable. */
55009 #define HSIO_BLK_CTRL_GPR_REG5_HRD_IE(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_HRD_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_HRD_IE_MASK)
55010 
55011 #define HSIO_BLK_CTRL_GPR_REG5_PTO_IE_MASK       (0x8U)
55012 #define HSIO_BLK_CTRL_GPR_REG5_PTO_IE_SHIFT      (3U)
55013 /*! PTO_IE - PME turn off detect interrupt enable */
55014 #define HSIO_BLK_CTRL_GPR_REG5_PTO_IE(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_PTO_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_PTO_IE_MASK)
55015 
55016 #define HSIO_BLK_CTRL_GPR_REG5_UREP_IE_MASK      (0x10U)
55017 #define HSIO_BLK_CTRL_GPR_REG5_UREP_IE_SHIFT     (4U)
55018 /*! UREP_IE - Unsupported request in EP mode interrupt enable. */
55019 #define HSIO_BLK_CTRL_GPR_REG5_UREP_IE(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_UREP_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_UREP_IE_MASK)
55020 
55021 #define HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_MASK     (0x20U)
55022 #define HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_SHIFT    (5U)
55023 /*! CDNSC_IE - Completion with data not succsessful interrupt enable */
55024 #define HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_MASK)
55025 
55026 #define HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_MASK      (0x40U)
55027 #define HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_SHIFT     (6U)
55028 /*! PCAC_IE - Completer abort interrupt enable. */
55029 #define HSIO_BLK_CTRL_GPR_REG5_PCAC_IE(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_MASK)
55030 
55031 #define HSIO_BLK_CTRL_GPR_REG5_PCT_IE_MASK       (0x80U)
55032 #define HSIO_BLK_CTRL_GPR_REG5_PCT_IE_SHIFT      (7U)
55033 /*! PCT_IE - completion timeout interrupt enable */
55034 #define HSIO_BLK_CTRL_GPR_REG5_PCT_IE(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_PCT_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_PCT_IE_MASK)
55035 /*! @} */
55036 
55037 /*! @name GPR_REG6 - PCIE PME message and error detect interrupt detect disable register */
55038 /*! @{ */
55039 
55040 #define HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_MASK      (0x1U)
55041 #define HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_SHIFT     (0U)
55042 /*! LUD_DIS - Link up detect disable */
55043 #define HSIO_BLK_CTRL_GPR_REG6_LUD_DIS(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_MASK)
55044 
55045 #define HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_MASK      (0x2U)
55046 #define HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_SHIFT     (1U)
55047 /*! LDD_DIS - Link down detect disable */
55048 #define HSIO_BLK_CTRL_GPR_REG6_LDD_DIS(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_MASK)
55049 
55050 #define HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_MASK      (0x4U)
55051 #define HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_SHIFT     (2U)
55052 /*! HRD_DIS - Hot reset detect disable */
55053 #define HSIO_BLK_CTRL_GPR_REG6_HRD_DIS(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_MASK)
55054 
55055 #define HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_MASK      (0x8U)
55056 #define HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_SHIFT     (3U)
55057 /*! PTO_DIS - PME turn off detect disabled. */
55058 #define HSIO_BLK_CTRL_GPR_REG6_PTO_DIS(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_MASK)
55059 
55060 #define HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_MASK     (0x10U)
55061 #define HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_SHIFT    (4U)
55062 /*! UREP_DIS - Unsupported request in EP mode detection disable */
55063 #define HSIO_BLK_CTRL_GPR_REG6_UREP_DIS(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_MASK)
55064 
55065 #define HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_MASK    (0x20U)
55066 #define HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_SHIFT   (5U)
55067 /*! CDNSC_DIS - Completion with data not succsessful detection disable */
55068 #define HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS(x)      (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_MASK)
55069 
55070 #define HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_MASK     (0x40U)
55071 #define HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_SHIFT    (6U)
55072 /*! PCAC_DIS - Completer abort detection disable. */
55073 #define HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS(x)       (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_MASK)
55074 
55075 #define HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_MASK      (0x80U)
55076 #define HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_SHIFT     (7U)
55077 /*! PCT_DIS - completion detection disable */
55078 #define HSIO_BLK_CTRL_GPR_REG6_PCT_DIS(x)        (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_MASK)
55079 
55080 #define HSIO_BLK_CTRL_GPR_REG6_ME_DIS_MASK       (0x100U)
55081 #define HSIO_BLK_CTRL_GPR_REG6_ME_DIS_SHIFT      (8U)
55082 /*! ME_DIS - Multiple errors of same type detection disable */
55083 #define HSIO_BLK_CTRL_GPR_REG6_ME_DIS(x)         (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_ME_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_ME_DIS_MASK)
55084 /*! @} */
55085 
55086 /*! @name GPR_REG7 - USB1 beat limit and enable */
55087 /*! @{ */
55088 
55089 #define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_MASK (0xFFFFU)
55090 #define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_SHIFT (0U)
55091 /*! USB1_BEAT_LIMIT - USB1 beat limit number */
55092 #define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_MASK)
55093 
55094 #define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_MASK (0x10000U)
55095 #define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_SHIFT (16U)
55096 /*! USB1_BEAT_LIMIT_EN - USB1 beat limit enable */
55097 #define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_MASK)
55098 /*! @} */
55099 
55100 /*! @name GPR_REG8 - USB2 beat limit and enable */
55101 /*! @{ */
55102 
55103 #define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_MASK (0xFFFFU)
55104 #define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_SHIFT (0U)
55105 /*! USB2_BEAT_LIMIT - USB2 beat limit number */
55106 #define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_MASK)
55107 
55108 #define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_MASK (0x10000U)
55109 #define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_SHIFT (16U)
55110 /*! USB2_BEAT_LIMIT_EN - USB2 beat limit enable */
55111 #define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_MASK)
55112 /*! @} */
55113 
55114 /*! @name GPR_REG9 - PCIE beat limit and enable */
55115 /*! @{ */
55116 
55117 #define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_MASK (0xFFFFU)
55118 #define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_SHIFT (0U)
55119 /*! PCIE_BEAT_LIMIT - PCIE beat limit number */
55120 #define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_MASK)
55121 
55122 #define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_MASK (0x10000U)
55123 #define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_SHIFT (16U)
55124 /*! PCIE_BEAT_LIMIT_EN - PCIE beat limit enable */
55125 #define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_MASK)
55126 /*! @} */
55127 
55128 /*! @name USB1_WAKEUP_CTRL - Register for USB1 wakeup */
55129 /*! @{ */
55130 
55131 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK (0x1U)
55132 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT (0U)
55133 /*! OTG_WKDPDMCHG_EN
55134  *  0b1..enable
55135  *  0b0..disable
55136  */
55137 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK)
55138 
55139 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK (0x2U)
55140 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT (1U)
55141 /*! OTG_VBUS_WAKE_EN
55142  *  0b1..enable
55143  *  0b0..disable
55144  */
55145 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK)
55146 
55147 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK (0x4U)
55148 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT (2U)
55149 /*! OTG_ID_WAKEUP_EN
55150  *  0b1..enable
55151  *  0b0..disable
55152  */
55153 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK)
55154 
55155 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK (0x8U)
55156 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT (3U)
55157 /*! OTG_U3_WAKE_EN
55158  *  0b1..enable
55159  *  0b0..disable
55160  */
55161 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK)
55162 
55163 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK (0x10U)
55164 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT (4U)
55165 /*! OTG_VBUS_SOURCE_SEL
55166  *  0b0..select vbus_valid
55167  *  0b1..select sessvld
55168  */
55169 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK)
55170 
55171 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK (0x20U)
55172 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT (5U)
55173 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK)
55174 
55175 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_MASK (0x100U)
55176 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_SHIFT (8U)
55177 /*! AUTORESUME_EN
55178  *  0b1..enable.
55179  *  0b0..disable.
55180  */
55181 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_MASK)
55182 
55183 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK (0x200U)
55184 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT (9U)
55185 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK)
55186 
55187 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK (0x400U)
55188 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT (10U)
55189 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK)
55190 
55191 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_MASK (0x800U)
55192 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_SHIFT (11U)
55193 /*! LOWSPEED_EN
55194  *  0b1..lowspeed
55195  *  0b0..full/high speed
55196  */
55197 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_MASK)
55198 
55199 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK (0x1000U)
55200 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT (12U)
55201 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK)
55202 
55203 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK (0x2000U)
55204 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT (13U)
55205 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK)
55206 
55207 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK (0x4000U)
55208 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT (14U)
55209 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK)
55210 
55211 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK (0x8000U)
55212 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT (15U)
55213 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK)
55214 
55215 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_MASK (0x10000U)
55216 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT (16U)
55217 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_MASK)
55218 
55219 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK (0x80000000U)
55220 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT (31U)
55221 #define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK)
55222 /*! @} */
55223 
55224 /*! @name USB1_WAKEUP_STATUS - Status of USB1 wakeup */
55225 /*! @{ */
55226 
55227 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK (0x1U)
55228 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT (0U)
55229 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK)
55230 
55231 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK (0x2U)
55232 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT (1U)
55233 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK)
55234 
55235 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK (0x4U)
55236 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT (2U)
55237 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK)
55238 
55239 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK (0x8U)
55240 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT (3U)
55241 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK)
55242 
55243 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK (0x10U)
55244 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT (4U)
55245 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK)
55246 
55247 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK (0x20U)
55248 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT (5U)
55249 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK)
55250 
55251 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK (0x40U)
55252 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT (6U)
55253 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK)
55254 
55255 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK (0x80U)
55256 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT (7U)
55257 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK)
55258 
55259 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK (0x100U)
55260 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT (8U)
55261 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK)
55262 
55263 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK (0x200U)
55264 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT (9U)
55265 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK)
55266 
55267 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_MASK (0x400U)
55268 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT (10U)
55269 /*! OTG_HOST_MODE
55270  *  0b1..host mode
55271  *  0b0..device mode
55272  */
55273 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_MASK)
55274 
55275 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK (0x1800U)
55276 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT (11U)
55277 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK)
55278 
55279 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK (0x2000U)
55280 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT (13U)
55281 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK)
55282 
55283 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK (0x80000000U)
55284 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT (31U)
55285 #define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK)
55286 /*! @} */
55287 
55288 /*! @name USB2_WAKEUP_CTRL - Register for USB2 wakeup */
55289 /*! @{ */
55290 
55291 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK (0x1U)
55292 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT (0U)
55293 /*! OTG_WKDPDMCHG_EN
55294  *  0b1..enable
55295  *  0b0..disable
55296  */
55297 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK)
55298 
55299 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK (0x2U)
55300 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT (1U)
55301 /*! OTG_VBUS_WAKE_EN
55302  *  0b1..enable
55303  *  0b0..disable
55304  */
55305 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK)
55306 
55307 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK (0x4U)
55308 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT (2U)
55309 /*! OTG_ID_WAKEUP_EN
55310  *  0b1..enable
55311  *  0b0..disable
55312  */
55313 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK)
55314 
55315 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK (0x8U)
55316 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT (3U)
55317 /*! OTG_U3_WAKE_EN
55318  *  0b1..enable
55319  *  0b0..disable
55320  */
55321 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK)
55322 
55323 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK (0x10U)
55324 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT (4U)
55325 /*! OTG_VBUS_SOURCE_SEL
55326  *  0b0..select vbus_valid
55327  *  0b1..select sessvld
55328  */
55329 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK)
55330 
55331 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK (0x20U)
55332 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT (5U)
55333 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK)
55334 
55335 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_MASK (0x100U)
55336 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_SHIFT (8U)
55337 /*! AUTORESUME_EN
55338  *  0b1..enable.
55339  *  0b0..disable.
55340  */
55341 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_MASK)
55342 
55343 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK (0x200U)
55344 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT (9U)
55345 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK)
55346 
55347 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK (0x400U)
55348 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT (10U)
55349 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK)
55350 
55351 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_MASK (0x800U)
55352 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_SHIFT (11U)
55353 /*! LOWSPEED_EN
55354  *  0b1..lowspeed
55355  *  0b0..full/high speed
55356  */
55357 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_MASK)
55358 
55359 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK (0x1000U)
55360 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT (12U)
55361 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK)
55362 
55363 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK (0x2000U)
55364 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT (13U)
55365 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK)
55366 
55367 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK (0x4000U)
55368 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT (14U)
55369 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK)
55370 
55371 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK (0x8000U)
55372 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT (15U)
55373 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK)
55374 
55375 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_MASK (0x10000U)
55376 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT (16U)
55377 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_MASK)
55378 
55379 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK (0x80000000U)
55380 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT (31U)
55381 #define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK)
55382 /*! @} */
55383 
55384 /*! @name USB2_WAKEUP_STATUS - Status of USB2 wakeup */
55385 /*! @{ */
55386 
55387 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK (0x1U)
55388 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT (0U)
55389 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK)
55390 
55391 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK (0x2U)
55392 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT (1U)
55393 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK)
55394 
55395 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK (0x4U)
55396 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT (2U)
55397 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK)
55398 
55399 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK (0x8U)
55400 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT (3U)
55401 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK)
55402 
55403 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK (0x10U)
55404 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT (4U)
55405 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK)
55406 
55407 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK (0x20U)
55408 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT (5U)
55409 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK)
55410 
55411 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK (0x40U)
55412 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT (6U)
55413 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK)
55414 
55415 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK (0x80U)
55416 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT (7U)
55417 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK)
55418 
55419 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK (0x100U)
55420 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT (8U)
55421 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK)
55422 
55423 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK (0x200U)
55424 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT (9U)
55425 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK)
55426 
55427 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_MASK (0x400U)
55428 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT (10U)
55429 /*! OTG_HOST_MODE
55430  *  0b1..host mode
55431  *  0b0..device mode
55432  */
55433 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_MASK)
55434 
55435 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK (0x1800U)
55436 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT (11U)
55437 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK)
55438 
55439 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK (0x2000U)
55440 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT (13U)
55441 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK)
55442 
55443 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK (0x80000000U)
55444 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT (31U)
55445 #define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK)
55446 /*! @} */
55447 
55448 
55449 /*!
55450  * @}
55451  */ /* end of group HSIO_BLK_CTRL_Register_Masks */
55452 
55453 
55454 /* HSIO_BLK_CTRL - Peripheral instance base addresses */
55455 /** Peripheral HSIO_BLK_CTRL base address */
55456 #define HSIO_BLK_CTRL_BASE                       (0x32F10000u)
55457 /** Peripheral HSIO_BLK_CTRL base pointer */
55458 #define HSIO_BLK_CTRL                            ((HSIO_BLK_CTRL_Type *)HSIO_BLK_CTRL_BASE)
55459 /** Array initializer of HSIO_BLK_CTRL peripheral base addresses */
55460 #define HSIO_BLK_CTRL_BASE_ADDRS                 { HSIO_BLK_CTRL_BASE }
55461 /** Array initializer of HSIO_BLK_CTRL peripheral base pointers */
55462 #define HSIO_BLK_CTRL_BASE_PTRS                  { HSIO_BLK_CTRL }
55463 
55464 /*!
55465  * @}
55466  */ /* end of group HSIO_BLK_CTRL_Peripheral_Access_Layer */
55467 
55468 
55469 /* ----------------------------------------------------------------------------
55470    -- HTX_PAI Peripheral Access Layer
55471    ---------------------------------------------------------------------------- */
55472 
55473 /*!
55474  * @addtogroup HTX_PAI_Peripheral_Access_Layer HTX_PAI Peripheral Access Layer
55475  * @{
55476  */
55477 
55478 /** HTX_PAI - Register Layout Typedef */
55479 typedef struct {
55480   __IO uint32_t HTX_PAI_CTRL;                      /**< HTX PAI Control, offset: 0x0 */
55481   __IO uint32_t HTX_PAI_CTRL_EXT;                  /**< HTX PAI Control Extended, offset: 0x4 */
55482   __IO uint32_t HTX_PAI_FIELD_CTRL;                /**< HTX PAI Field Control, offset: 0x8 */
55483   __I  uint32_t HTX_PAI_STAT;                      /**< HTX PAI Status, offset: 0xC */
55484   __IO uint32_t HTX_PAI_IRQ_NOMASK;                /**< HTX PAI Nonmasked Interrupt Flags, offset: 0x10 */
55485   __IO uint32_t HTX_PAI_IRQ_MASKED;                /**< HTX PAI Masked Interrupt Flags, offset: 0x14 */
55486   __IO uint32_t HTX_PAI_IRQ_MASK;                  /**< HTX PAI IRQ Masks, offset: 0x18 */
55487 } HTX_PAI_Type;
55488 
55489 /* ----------------------------------------------------------------------------
55490    -- HTX_PAI Register Masks
55491    ---------------------------------------------------------------------------- */
55492 
55493 /*!
55494  * @addtogroup HTX_PAI_Register_Masks HTX_PAI Register Masks
55495  * @{
55496  */
55497 
55498 /*! @name HTX_PAI_CTRL - HTX PAI Control */
55499 /*! @{ */
55500 
55501 #define HTX_PAI_HTX_PAI_CTRL_ENABLE_MASK         (0x1U)
55502 #define HTX_PAI_HTX_PAI_CTRL_ENABLE_SHIFT        (0U)
55503 /*! ENABLE - HTX PAI Enable */
55504 #define HTX_PAI_HTX_PAI_CTRL_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_ENABLE_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_ENABLE_MASK)
55505 /*! @} */
55506 
55507 /*! @name HTX_PAI_CTRL_EXT - HTX PAI Control Extended */
55508 /*! @{ */
55509 
55510 #define HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_MASK     (0x1U)
55511 #define HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_SHIFT    (0U)
55512 /*! SOURCE - HTX PAI Source Select
55513  *  0b0..Normal operation. Data input from the audio subsystem.
55514  *  0b1..Low latency bypass mode. Data input from RASFD.
55515  */
55516 #define HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_MASK)
55517 
55518 #define HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_MASK     (0x700U)
55519 #define HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_SHIFT    (8U)
55520 /*! NUM_CH - Number of Channels Per Packet
55521  *  0b000..There is 1 channel per packet.
55522  *  0b001..There are 2 channels per packet.
55523  *  0b010..There are 3 channels per packet.
55524  *  0b011..There are 4 channels per packet.
55525  *  0b100..There are 5 channels per packet.
55526  *  0b101..There are 6 channels per packet.
55527  *  0b110..There are 7 channels per packet.
55528  *  0b111..There are 8 channels per packet.
55529  */
55530 #define HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_MASK)
55531 
55532 #define HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_MASK      (0x800U)
55533 #define HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_SHIFT     (11U)
55534 /*! B_EXT - B-Field Extension
55535  *  0b0..Use default B-Preamble timing (from selected input source).
55536  *  0b1..Extend B-Preamble timing to ensure it is set for at least 2 cycles.
55537  */
55538 #define HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_MASK)
55539 
55540 #define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_MASK   (0xFF0000U)
55541 #define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_SHIFT  (16U)
55542 /*! WTMK_LOW - HTX PAI Watermark Low */
55543 #define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_MASK)
55544 
55545 #define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_MASK  (0xFF000000U)
55546 #define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_SHIFT (24U)
55547 /*! WTMK_HIGH - HTX PAI Watermark High */
55548 #define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_MASK)
55549 /*! @} */
55550 
55551 /*! @name HTX_PAI_FIELD_CTRL - HTX PAI Field Control */
55552 /*! @{ */
55553 
55554 #define HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_MASK    (0x1FU)
55555 #define HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_SHIFT   (0U)
55556 /*! P_SEL - IEC60958 P Select */
55557 #define HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL(x)      (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_MASK)
55558 
55559 #define HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_MASK    (0x3E0U)
55560 #define HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_SHIFT   (5U)
55561 /*! C_SEL - IEC60958 C Select */
55562 #define HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL(x)      (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_MASK)
55563 
55564 #define HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_MASK    (0x7C00U)
55565 #define HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_SHIFT   (10U)
55566 /*! U_SEL - IEC60958 U Select */
55567 #define HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL(x)      (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_MASK)
55568 
55569 #define HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_MASK    (0xF8000U)
55570 #define HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_SHIFT   (15U)
55571 /*! V_SEL - IEC60958 V Select */
55572 #define HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL(x)      (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_MASK)
55573 
55574 #define HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_MASK    (0xF00000U)
55575 #define HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_SHIFT   (20U)
55576 /*! D_SEL - IEC60958 Data Select */
55577 #define HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL(x)      (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_MASK)
55578 
55579 #define HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_MASK  (0x1F000000U)
55580 #define HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_SHIFT (24U)
55581 /*! PRE_SEL - IEC60958 Preamble Select */
55582 #define HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_MASK)
55583 
55584 #define HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_MASK  (0x20000000U)
55585 #define HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_SHIFT (29U)
55586 /*! END_SEL - Endianness Select */
55587 #define HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_MASK)
55588 
55589 #define HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_MASK (0x40000000U)
55590 #define HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_SHIFT (30U)
55591 /*! PARITY_EN - Parity Enable */
55592 #define HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN(x)  (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_MASK)
55593 
55594 #define HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_MASK   (0x80000000U)
55595 #define HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_SHIFT  (31U)
55596 /*! B_FILT - B-Detect Filter */
55597 #define HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_MASK)
55598 /*! @} */
55599 
55600 /*! @name HTX_PAI_STAT - HTX PAI Status */
55601 /*! @{ */
55602 
55603 #define HTX_PAI_HTX_PAI_STAT_WM_LOW_MASK         (0x1U)
55604 #define HTX_PAI_HTX_PAI_STAT_WM_LOW_SHIFT        (0U)
55605 /*! WM_LOW - Watermark Low Flag */
55606 #define HTX_PAI_HTX_PAI_STAT_WM_LOW(x)           (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_STAT_WM_LOW_SHIFT)) & HTX_PAI_HTX_PAI_STAT_WM_LOW_MASK)
55607 
55608 #define HTX_PAI_HTX_PAI_STAT_WM_HIGH_MASK        (0x2U)
55609 #define HTX_PAI_HTX_PAI_STAT_WM_HIGH_SHIFT       (1U)
55610 /*! WM_HIGH - Watermark High Flag */
55611 #define HTX_PAI_HTX_PAI_STAT_WM_HIGH(x)          (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_STAT_WM_HIGH_SHIFT)) & HTX_PAI_HTX_PAI_STAT_WM_HIGH_MASK)
55612 /*! @} */
55613 
55614 /*! @name HTX_PAI_IRQ_NOMASK - HTX PAI Nonmasked Interrupt Flags */
55615 /*! @{ */
55616 
55617 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_MASK      (0x1U)
55618 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_SHIFT     (0U)
55619 /*! OVF - HTX PAI Buffer Overflow */
55620 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_MASK)
55621 
55622 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_MASK      (0x2U)
55623 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_SHIFT     (1U)
55624 /*! UND - HTX PAI Buffer Underflow */
55625 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_UND(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_MASK)
55626 
55627 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_MASK (0x4U)
55628 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_SHIFT (2U)
55629 /*! WM_LOW_IRQ - Watermark Low IRQ */
55630 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_MASK)
55631 
55632 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_MASK (0x8U)
55633 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_SHIFT (3U)
55634 /*! WM_HIGH_IRQ - Watermark High IRQ */
55635 #define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_MASK)
55636 /*! @} */
55637 
55638 /*! @name HTX_PAI_IRQ_MASKED - HTX PAI Masked Interrupt Flags */
55639 /*! @{ */
55640 
55641 #define HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_MASK      (0x1U)
55642 #define HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_SHIFT     (0U)
55643 /*! OVF - HTX PAI Buffer Overflow */
55644 #define HTX_PAI_HTX_PAI_IRQ_MASKED_OVF(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_MASK)
55645 
55646 #define HTX_PAI_HTX_PAI_IRQ_MASKED_UND_MASK      (0x2U)
55647 #define HTX_PAI_HTX_PAI_IRQ_MASKED_UND_SHIFT     (1U)
55648 /*! UND - HTX PAI Buffer Underflow */
55649 #define HTX_PAI_HTX_PAI_IRQ_MASKED_UND(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_UND_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_UND_MASK)
55650 
55651 #define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_MASK (0x4U)
55652 #define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_SHIFT (2U)
55653 /*! WM_LOW_IRQ - Watermark Low IRQ Masked */
55654 #define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_MASK)
55655 
55656 #define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_MASK (0x8U)
55657 #define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_SHIFT (3U)
55658 /*! WM_HIGH_IRQ - Watermark High IRQ Masked */
55659 #define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_MASK)
55660 /*! @} */
55661 
55662 /*! @name HTX_PAI_IRQ_MASK - HTX PAI IRQ Masks */
55663 /*! @{ */
55664 
55665 #define HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_MASK   (0x1U)
55666 #define HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_SHIFT  (0U)
55667 /*! OVF_MASK - HTX PAI Buffer Overflow Mask */
55668 #define HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_MASK)
55669 
55670 #define HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_MASK   (0x2U)
55671 #define HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_SHIFT  (1U)
55672 /*! UND_MASK - HTX PAI Buffer Underflow Mask */
55673 #define HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_MASK)
55674 
55675 #define HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_MASK (0x4U)
55676 #define HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_SHIFT (2U)
55677 /*! WM_LOW_IRQ_MASK - Watermark Low IRQ Mask */
55678 #define HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_MASK)
55679 
55680 #define HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_MASK (0x8U)
55681 #define HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_SHIFT (3U)
55682 /*! WM_HIGH_IRQ_MASK - Watermark High IRQ Mask */
55683 #define HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_MASK)
55684 /*! @} */
55685 
55686 
55687 /*!
55688  * @}
55689  */ /* end of group HTX_PAI_Register_Masks */
55690 
55691 
55692 /* HTX_PAI - Peripheral instance base addresses */
55693 /** Peripheral HTX_PAI base address */
55694 #define HTX_PAI_BASE                             (0x32FC4800u)
55695 /** Peripheral HTX_PAI base pointer */
55696 #define HTX_PAI                                  ((HTX_PAI_Type *)HTX_PAI_BASE)
55697 /** Array initializer of HTX_PAI peripheral base addresses */
55698 #define HTX_PAI_BASE_ADDRS                       { HTX_PAI_BASE }
55699 /** Array initializer of HTX_PAI peripheral base pointers */
55700 #define HTX_PAI_BASE_PTRS                        { HTX_PAI }
55701 
55702 /*!
55703  * @}
55704  */ /* end of group HTX_PAI_Peripheral_Access_Layer */
55705 
55706 
55707 /* ----------------------------------------------------------------------------
55708    -- HTX_PVI Peripheral Access Layer
55709    ---------------------------------------------------------------------------- */
55710 
55711 /*!
55712  * @addtogroup HTX_PVI_Peripheral_Access_Layer HTX_PVI Peripheral Access Layer
55713  * @{
55714  */
55715 
55716 /** HTX_PVI - Register Layout Typedef */
55717 typedef struct {
55718   __IO uint32_t HTX_PVI_CTRL;                      /**< HTX_PVI Control Reg, offset: 0x0 */
55719   __IO uint32_t HTX_PVI_IRQ_MASK;                  /**< Masks off the Interrupts, offset: 0x4 */
55720   __I  uint32_t HTX_PVI_IRQ_STATUS;                /**< Interrupt Status, offset: 0x8 */
55721   __IO uint32_t HTX_PVI_IRQ_CLR;                   /**< Interrupts, offset: 0xC */
55722   __IO uint32_t HTX_TMG_GEN_DISP_LRC;              /**< Display Coordinates, offset: 0x10 */
55723   __IO uint32_t HTX_TMG_GEN_DE_ULC;                /**< Data Enable Coordinates, offset: 0x14 */
55724   __IO uint32_t HTX_TMG_GEN_DE_LRC;                /**< Data Enable Coordinates, offset: 0x18 */
55725   __IO uint32_t HTX_TMG_GEN_HSYNC;                 /**< Hsync Start and End, offset: 0x1C */
55726   __IO uint32_t HTX_TMG_GEN_VSYNC;                 /**< Vsync Start and End, offset: 0x20 */
55727   __IO uint32_t HTX_TMG_GEN_IRQ0;                  /**< Controls the Position of first IRQ from Timing Generator, offset: 0x24 */
55728   __IO uint32_t HTX_TMG_GEN_IRQ1;                  /**< Controls the Position of Second IRQ from Timing Generator, offset: 0x28 */
55729   __IO uint32_t HTX_TMG_GEN_IRQ2;                  /**< Controls the Position of Third IRQ from Timing Generator, offset: 0x2C */
55730   __IO uint32_t HTX_TMG_GEN_IRQ3;                  /**< Controls the Position of Fourth IRQ from Timing Generator, offset: 0x30 */
55731   __IO uint32_t HTX_TMG_GEN_BG0;                   /**< Background Color insertion for R or Y, offset: 0x34 */
55732   __IO uint32_t HTX_TMG_GEN_BG1;                   /**< Background Color insertion for G or Cb, offset: 0x38 */
55733   __IO uint32_t HTX_TMG_GEN_BG2;                   /**< Background Color insertion for B or Cr, offset: 0x3C */
55734   __IO uint32_t HTX_TMG_GEN_CFG;                   /**< HStart and Vstart Delay Configuration, offset: 0x40 */
55735 } HTX_PVI_Type;
55736 
55737 /* ----------------------------------------------------------------------------
55738    -- HTX_PVI Register Masks
55739    ---------------------------------------------------------------------------- */
55740 
55741 /*!
55742  * @addtogroup HTX_PVI_Register_Masks HTX_PVI Register Masks
55743  * @{
55744  */
55745 
55746 /*! @name HTX_PVI_CTRL - HTX_PVI Control Reg */
55747 /*! @{ */
55748 
55749 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_MASK     (0x1U)
55750 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_SHIFT    (0U)
55751 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_MASK)
55752 
55753 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_MASK   (0x6U)
55754 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_SHIFT  (1U)
55755 /*! HTX_PVI_MODE - Selects the mode of operation in HTX PVI
55756  *  0b00..Select the DCSS Path
55757  *  0b01..Select the Bypass path from HDMI Rx
55758  *  0b10..Select the LCDIF Path
55759  *  0b11..Reserved
55760  */
55761 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_MASK)
55762 
55763 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_MASK (0x8U)
55764 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_SHIFT (3U)
55765 /*! HTX_PVI_UPSMPL - Select the mode of upsample in case of 16bit output and 12bit input
55766  *  0b0..Fill LSB with 4'b0
55767  *  0b1..Fill LSB with MSB 4 bits, i.e. [11:8]
55768  */
55769 #define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL(x)   (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_MASK)
55770 
55771 #define HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_MASK (0x10U)
55772 #define HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_SHIFT (4U)
55773 #define HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_MASK)
55774 
55775 #define HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_MASK     (0x20U)
55776 #define HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_SHIFT    (5U)
55777 #define HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_MASK)
55778 
55779 #define HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_MASK      (0xC0U)
55780 #define HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_SHIFT     (6U)
55781 /*! PIPE_MODE - Sets the Timing Generator mode.
55782  *  0b00..bypass
55783  *  0b01..422 subsample
55784  *  0b10..420 subsample
55785  *  0b11..bypass
55786  */
55787 #define HTX_PVI_HTX_PVI_CTRL_PIPE_MODE(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_MASK)
55788 
55789 #define HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_MASK    (0x100U)
55790 #define HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_SHIFT   (8U)
55791 /*! VSYNC_SHIFT - VSYNC shift
55792  *  0b0..Run in general interlaced mode. Every other field the vsync is shifted forward 1/2 scan lines. In
55793  *       addition, the horizontal back porch is extended 1 scan line.
55794  *  0b1..Run in special interlaced format. This shifts vsync backwards 1/2 scan line every other field. Remaining timing won't change.
55795  */
55796 #define HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT(x)      (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_MASK)
55797 
55798 #define HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_MASK     (0x200U)
55799 #define HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_SHIFT    (9U)
55800 /*! TMG_GEN_EN - Enable Timing Generator to insert the hsync and vsync.
55801  *  0b0..Disable
55802  *  0b1..Enable
55803  */
55804 #define HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_MASK)
55805 
55806 #define HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_MASK      (0x400U)
55807 #define HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_SHIFT     (10U)
55808 /*! INTRLC_EN - Enable interlaced HDMI timing
55809  *  0b0..Disable
55810  *  0b1..Enable
55811  */
55812 #define HTX_PVI_HTX_PVI_CTRL_INTRLC_EN(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_MASK)
55813 
55814 #define HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_MASK     (0x1000U)
55815 #define HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_SHIFT    (12U)
55816 /*! INP_DE_POL
55817  *  0b0..Active Low
55818  *  0b1..Active High
55819  */
55820 #define HTX_PVI_HTX_PVI_CTRL_INP_DE_POL(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_MASK)
55821 
55822 #define HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_MASK  (0x2000U)
55823 #define HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_SHIFT (13U)
55824 /*! INP_HSYNC_POL
55825  *  0b0..Active Low
55826  *  0b1..Active High
55827  */
55828 #define HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_MASK)
55829 
55830 #define HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_MASK  (0x4000U)
55831 #define HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_SHIFT (14U)
55832 /*! INP_VSYNC_POL
55833  *  0b0..Active Low
55834  *  0b1..Active High
55835  */
55836 #define HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_MASK)
55837 
55838 #define HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_MASK      (0x10000U)
55839 #define HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_SHIFT     (16U)
55840 /*! OP_DE_POL
55841  *  0b0..Active Low
55842  *  0b1..Active High
55843  */
55844 #define HTX_PVI_HTX_PVI_CTRL_OP_DE_POL(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_MASK)
55845 
55846 #define HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_MASK   (0x20000U)
55847 #define HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_SHIFT  (17U)
55848 /*! OP_HSYNC_POL
55849  *  0b0..Active Low
55850  *  0b1..Active High
55851  */
55852 #define HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_MASK)
55853 
55854 #define HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_MASK   (0x40000U)
55855 #define HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_SHIFT  (18U)
55856 /*! OP_VSYNC_POL
55857  *  0b0..Active Low
55858  *  0b1..Active High
55859  */
55860 #define HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_MASK)
55861 
55862 #define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_MASK (0x100000U)
55863 #define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_SHIFT (20U)
55864 #define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC(x)   (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_MASK)
55865 
55866 #define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_MASK (0x200000U)
55867 #define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_SHIFT (21U)
55868 #define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_MASK)
55869 /*! @} */
55870 
55871 /*! @name HTX_PVI_IRQ_MASK - Masks off the Interrupts */
55872 /*! @{ */
55873 
55874 #define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_MASK (0x1U)
55875 #define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_SHIFT (0U)
55876 #define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_MASK)
55877 
55878 #define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_MASK (0x2U)
55879 #define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_SHIFT (1U)
55880 #define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_MASK)
55881 
55882 #define HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_MASK (0x3CU)
55883 #define HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_SHIFT (2U)
55884 #define HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_MASK)
55885 /*! @} */
55886 
55887 /*! @name HTX_PVI_IRQ_STATUS - Interrupt Status */
55888 /*! @{ */
55889 
55890 #define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_MASK (0x1U)
55891 #define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_SHIFT (0U)
55892 #define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_MASK)
55893 
55894 #define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_MASK (0x2U)
55895 #define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_SHIFT (1U)
55896 #define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_MASK)
55897 
55898 #define HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_MASK (0x3CU)
55899 #define HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_SHIFT (2U)
55900 #define HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_MASK)
55901 /*! @} */
55902 
55903 /*! @name HTX_PVI_IRQ_CLR - Interrupts */
55904 /*! @{ */
55905 
55906 #define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_MASK (0x1U)
55907 #define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_SHIFT (0U)
55908 #define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_MASK)
55909 
55910 #define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_MASK (0x2U)
55911 #define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_SHIFT (1U)
55912 #define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_MASK)
55913 
55914 #define HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_MASK (0x3CU)
55915 #define HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_SHIFT (2U)
55916 #define HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_MASK)
55917 /*! @} */
55918 
55919 /*! @name HTX_TMG_GEN_DISP_LRC - Display Coordinates */
55920 /*! @{ */
55921 
55922 #define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_MASK   (0xFFFFU)
55923 #define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_SHIFT  (0U)
55924 #define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_MASK)
55925 
55926 #define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_MASK   (0xFFFF0000U)
55927 #define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_SHIFT  (16U)
55928 #define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX(x)     (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_MASK)
55929 /*! @} */
55930 
55931 /*! @name HTX_TMG_GEN_DE_ULC - Data Enable Coordinates */
55932 /*! @{ */
55933 
55934 #define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_MASK     (0xFFFFU)
55935 #define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_SHIFT    (0U)
55936 #define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_MASK)
55937 
55938 #define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_MASK     (0xFFFF0000U)
55939 #define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_SHIFT    (16U)
55940 #define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_MASK)
55941 /*! @} */
55942 
55943 /*! @name HTX_TMG_GEN_DE_LRC - Data Enable Coordinates */
55944 /*! @{ */
55945 
55946 #define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_MASK     (0xFFFFU)
55947 #define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_SHIFT    (0U)
55948 #define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_MASK)
55949 
55950 #define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_MASK     (0xFFFF0000U)
55951 #define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_SHIFT    (16U)
55952 #define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_MASK)
55953 /*! @} */
55954 
55955 /*! @name HTX_TMG_GEN_HSYNC - Hsync Start and End */
55956 /*! @{ */
55957 
55958 #define HTX_PVI_HTX_TMG_GEN_HSYNC_END_MASK       (0xFFFFU)
55959 #define HTX_PVI_HTX_TMG_GEN_HSYNC_END_SHIFT      (0U)
55960 #define HTX_PVI_HTX_TMG_GEN_HSYNC_END(x)         (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_HSYNC_END_SHIFT)) & HTX_PVI_HTX_TMG_GEN_HSYNC_END_MASK)
55961 
55962 #define HTX_PVI_HTX_TMG_GEN_HSYNC_START_MASK     (0xFFFF0000U)
55963 #define HTX_PVI_HTX_TMG_GEN_HSYNC_START_SHIFT    (16U)
55964 #define HTX_PVI_HTX_TMG_GEN_HSYNC_START(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_HSYNC_START_SHIFT)) & HTX_PVI_HTX_TMG_GEN_HSYNC_START_MASK)
55965 /*! @} */
55966 
55967 /*! @name HTX_TMG_GEN_VSYNC - Vsync Start and End */
55968 /*! @{ */
55969 
55970 #define HTX_PVI_HTX_TMG_GEN_VSYNC_END_MASK       (0xFFFFU)
55971 #define HTX_PVI_HTX_TMG_GEN_VSYNC_END_SHIFT      (0U)
55972 #define HTX_PVI_HTX_TMG_GEN_VSYNC_END(x)         (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_VSYNC_END_SHIFT)) & HTX_PVI_HTX_TMG_GEN_VSYNC_END_MASK)
55973 
55974 #define HTX_PVI_HTX_TMG_GEN_VSYNC_START_MASK     (0xFFFF0000U)
55975 #define HTX_PVI_HTX_TMG_GEN_VSYNC_START_SHIFT    (16U)
55976 #define HTX_PVI_HTX_TMG_GEN_VSYNC_START(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_VSYNC_START_SHIFT)) & HTX_PVI_HTX_TMG_GEN_VSYNC_START_MASK)
55977 /*! @} */
55978 
55979 /*! @name HTX_TMG_GEN_IRQ0 - Controls the Position of first IRQ from Timing Generator */
55980 /*! @{ */
55981 
55982 #define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_MASK      (0xFFFFU)
55983 #define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_SHIFT     (0U)
55984 #define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_MASK)
55985 
55986 #define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_MASK      (0xFFFF0000U)
55987 #define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_SHIFT     (16U)
55988 #define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_MASK)
55989 /*! @} */
55990 
55991 /*! @name HTX_TMG_GEN_IRQ1 - Controls the Position of Second IRQ from Timing Generator */
55992 /*! @{ */
55993 
55994 #define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_MASK      (0xFFFFU)
55995 #define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_SHIFT     (0U)
55996 #define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_MASK)
55997 
55998 #define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_MASK      (0xFFFF0000U)
55999 #define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_SHIFT     (16U)
56000 #define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_MASK)
56001 /*! @} */
56002 
56003 /*! @name HTX_TMG_GEN_IRQ2 - Controls the Position of Third IRQ from Timing Generator */
56004 /*! @{ */
56005 
56006 #define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_MASK      (0xFFFFU)
56007 #define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_SHIFT     (0U)
56008 #define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_MASK)
56009 
56010 #define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_MASK      (0xFFFF0000U)
56011 #define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_SHIFT     (16U)
56012 #define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_MASK)
56013 /*! @} */
56014 
56015 /*! @name HTX_TMG_GEN_IRQ3 - Controls the Position of Fourth IRQ from Timing Generator */
56016 /*! @{ */
56017 
56018 #define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_MASK      (0xFFFFU)
56019 #define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_SHIFT     (0U)
56020 #define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_MASK)
56021 
56022 #define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_MASK      (0xFFFF0000U)
56023 #define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_SHIFT     (16U)
56024 #define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X(x)        (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_MASK)
56025 /*! @} */
56026 
56027 /*! @name HTX_TMG_GEN_BG0 - Background Color insertion for R or Y */
56028 /*! @{ */
56029 
56030 #define HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_MASK     (0xFFFU)
56031 #define HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_SHIFT    (0U)
56032 #define HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_SHIFT)) & HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_MASK)
56033 /*! @} */
56034 
56035 /*! @name HTX_TMG_GEN_BG1 - Background Color insertion for G or Cb */
56036 /*! @{ */
56037 
56038 #define HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_MASK     (0xFFFU)
56039 #define HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_SHIFT    (0U)
56040 #define HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_SHIFT)) & HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_MASK)
56041 /*! @} */
56042 
56043 /*! @name HTX_TMG_GEN_BG2 - Background Color insertion for B or Cr */
56044 /*! @{ */
56045 
56046 #define HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_MASK     (0xFFFU)
56047 #define HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_SHIFT    (0U)
56048 #define HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL(x)       (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_SHIFT)) & HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_MASK)
56049 /*! @} */
56050 
56051 /*! @name HTX_TMG_GEN_CFG - HStart and Vstart Delay Configuration */
56052 /*! @{ */
56053 
56054 #define HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_MASK  (0x1FFFU)
56055 #define HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_SHIFT (0U)
56056 #define HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_MASK)
56057 
56058 #define HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_MASK  (0x1FFF0000U)
56059 #define HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_SHIFT (16U)
56060 #define HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY(x)    (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_MASK)
56061 
56062 #define HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_MASK (0x40000000U)
56063 #define HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_SHIFT (30U)
56064 #define HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_MASK)
56065 
56066 #define HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_MASK (0x80000000U)
56067 #define HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_SHIFT (31U)
56068 #define HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_MASK)
56069 /*! @} */
56070 
56071 
56072 /*!
56073  * @}
56074  */ /* end of group HTX_PVI_Register_Masks */
56075 
56076 
56077 /* HTX_PVI - Peripheral instance base addresses */
56078 /** Peripheral HTX_PVI base address */
56079 #define HTX_PVI_BASE                             (0x32FC4000u)
56080 /** Peripheral HTX_PVI base pointer */
56081 #define HTX_PVI                                  ((HTX_PVI_Type *)HTX_PVI_BASE)
56082 /** Array initializer of HTX_PVI peripheral base addresses */
56083 #define HTX_PVI_BASE_ADDRS                       { HTX_PVI_BASE }
56084 /** Array initializer of HTX_PVI peripheral base pointers */
56085 #define HTX_PVI_BASE_PTRS                        { HTX_PVI }
56086 
56087 /*!
56088  * @}
56089  */ /* end of group HTX_PVI_Peripheral_Access_Layer */
56090 
56091 
56092 /* ----------------------------------------------------------------------------
56093    -- I2C Peripheral Access Layer
56094    ---------------------------------------------------------------------------- */
56095 
56096 /*!
56097  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
56098  * @{
56099  */
56100 
56101 /** I2C - Register Layout Typedef */
56102 typedef struct {
56103   __IO uint16_t IADR;                              /**< I2C Address Register, offset: 0x0 */
56104        uint8_t RESERVED_0[2];
56105   __IO uint16_t IFDR;                              /**< I2C Frequency Divider Register, offset: 0x4 */
56106        uint8_t RESERVED_1[2];
56107   __IO uint16_t I2CR;                              /**< I2C Control Register, offset: 0x8 */
56108        uint8_t RESERVED_2[2];
56109   __IO uint16_t I2SR;                              /**< I2C Status Register, offset: 0xC */
56110        uint8_t RESERVED_3[2];
56111   __IO uint16_t I2DR;                              /**< I2C Data I/O Register, offset: 0x10 */
56112 } I2C_Type;
56113 
56114 /* ----------------------------------------------------------------------------
56115    -- I2C Register Masks
56116    ---------------------------------------------------------------------------- */
56117 
56118 /*!
56119  * @addtogroup I2C_Register_Masks I2C Register Masks
56120  * @{
56121  */
56122 
56123 /*! @name IADR - I2C Address Register */
56124 /*! @{ */
56125 
56126 #define I2C_IADR_ADR_MASK                        (0xFEU)
56127 #define I2C_IADR_ADR_SHIFT                       (1U)
56128 #define I2C_IADR_ADR(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK)
56129 /*! @} */
56130 
56131 /*! @name IFDR - I2C Frequency Divider Register */
56132 /*! @{ */
56133 
56134 #define I2C_IFDR_IC_MASK                         (0x3FU)
56135 #define I2C_IFDR_IC_SHIFT                        (0U)
56136 #define I2C_IFDR_IC(x)                           (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK)
56137 /*! @} */
56138 
56139 /*! @name I2CR - I2C Control Register */
56140 /*! @{ */
56141 
56142 #define I2C_I2CR_RSTA_MASK                       (0x4U)
56143 #define I2C_I2CR_RSTA_SHIFT                      (2U)
56144 /*! RSTA
56145  *  0b0..No repeat start
56146  *  0b1..Generates a Repeated Start condition
56147  */
56148 #define I2C_I2CR_RSTA(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK)
56149 
56150 #define I2C_I2CR_TXAK_MASK                       (0x8U)
56151 #define I2C_I2CR_TXAK_SHIFT                      (3U)
56152 /*! TXAK
56153  *  0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
56154  *  0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1).
56155  */
56156 #define I2C_I2CR_TXAK(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK)
56157 
56158 #define I2C_I2CR_MTX_MASK                        (0x10U)
56159 #define I2C_I2CR_MTX_SHIFT                       (4U)
56160 /*! MTX
56161  *  0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in
56162  *       the I2C status register (I2C_I2SR[SRW]).
56163  *  0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1.
56164  */
56165 #define I2C_I2CR_MTX(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK)
56166 
56167 #define I2C_I2CR_MSTA_MASK                       (0x20U)
56168 #define I2C_I2CR_MSTA_SHIFT                      (5U)
56169 /*! MSTA
56170  *  0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode.
56171  *  0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode.
56172  */
56173 #define I2C_I2CR_MSTA(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK)
56174 
56175 #define I2C_I2CR_IIEN_MASK                       (0x40U)
56176 #define I2C_I2CR_IIEN_SHIFT                      (6U)
56177 /*! IIEN
56178  *  0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs.
56179  *  0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
56180  */
56181 #define I2C_I2CR_IIEN(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK)
56182 
56183 #define I2C_I2CR_IEN_MASK                        (0x80U)
56184 #define I2C_I2CR_IEN_SHIFT                       (7U)
56185 /*! IEN
56186  *  0b0..The block is disabled, but registers can still be accessed.
56187  *  0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect.
56188  */
56189 #define I2C_I2CR_IEN(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK)
56190 /*! @} */
56191 
56192 /*! @name I2SR - I2C Status Register */
56193 /*! @{ */
56194 
56195 #define I2C_I2SR_RXAK_MASK                       (0x1U)
56196 #define I2C_I2SR_RXAK_SHIFT                      (0U)
56197 /*! RXAK
56198  *  0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
56199  *  0b1..A "No acknowledge" signal was detected at the ninth clock.
56200  */
56201 #define I2C_I2SR_RXAK(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK)
56202 
56203 #define I2C_I2SR_IIF_MASK                        (0x2U)
56204 #define I2C_I2SR_IIF_SHIFT                       (1U)
56205 /*! IIF
56206  *  0b0..No I2C interrupt pending.
56207  *  0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted
56208  *       [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the
56209  *       interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific
56210  *       address in Slave Receive mode. Arbitration is lost.
56211  */
56212 #define I2C_I2SR_IIF(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK)
56213 
56214 #define I2C_I2SR_SRW_MASK                        (0x4U)
56215 #define I2C_I2SR_SRW_SHIFT                       (2U)
56216 /*! SRW
56217  *  0b0..Slave receive, master writing to slave
56218  *  0b1..Slave transmit, master reading from slave
56219  */
56220 #define I2C_I2SR_SRW(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK)
56221 
56222 #define I2C_I2SR_IAL_MASK                        (0x10U)
56223 #define I2C_I2SR_IAL_SHIFT                       (4U)
56224 /*! IAL
56225  *  0b0..No arbitration lost.
56226  *  0b1..Arbitration is lost.
56227  */
56228 #define I2C_I2SR_IAL(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK)
56229 
56230 #define I2C_I2SR_IBB_MASK                        (0x20U)
56231 #define I2C_I2SR_IBB_SHIFT                       (5U)
56232 /*! IBB
56233  *  0b0..Bus is idle. If a Stop signal is detected, IBB is cleared.
56234  *  0b1..Bus is busy. When Start is detected, IBB is set.
56235  */
56236 #define I2C_I2SR_IBB(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK)
56237 
56238 #define I2C_I2SR_IAAS_MASK                       (0x40U)
56239 #define I2C_I2SR_IAAS_SHIFT                      (6U)
56240 /*! IAAS
56241  *  0b0..Not addressed
56242  *  0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
56243  */
56244 #define I2C_I2SR_IAAS(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK)
56245 
56246 #define I2C_I2SR_ICF_MASK                        (0x80U)
56247 #define I2C_I2SR_ICF_SHIFT                       (7U)
56248 /*! ICF
56249  *  0b0..Transfer is in progress.
56250  *  0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer.
56251  */
56252 #define I2C_I2SR_ICF(x)                          (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK)
56253 /*! @} */
56254 
56255 /*! @name I2DR - I2C Data I/O Register */
56256 /*! @{ */
56257 
56258 #define I2C_I2DR_DATA_MASK                       (0xFFU)
56259 #define I2C_I2DR_DATA_SHIFT                      (0U)
56260 #define I2C_I2DR_DATA(x)                         (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK)
56261 /*! @} */
56262 
56263 
56264 /*!
56265  * @}
56266  */ /* end of group I2C_Register_Masks */
56267 
56268 
56269 /* I2C - Peripheral instance base addresses */
56270 /** Peripheral I2C1 base address */
56271 #define I2C1_BASE                                (0x30A20000u)
56272 /** Peripheral I2C1 base pointer */
56273 #define I2C1                                     ((I2C_Type *)I2C1_BASE)
56274 /** Peripheral I2C2 base address */
56275 #define I2C2_BASE                                (0x30A30000u)
56276 /** Peripheral I2C2 base pointer */
56277 #define I2C2                                     ((I2C_Type *)I2C2_BASE)
56278 /** Peripheral I2C3 base address */
56279 #define I2C3_BASE                                (0x30A40000u)
56280 /** Peripheral I2C3 base pointer */
56281 #define I2C3                                     ((I2C_Type *)I2C3_BASE)
56282 /** Peripheral I2C4 base address */
56283 #define I2C4_BASE                                (0x30A50000u)
56284 /** Peripheral I2C4 base pointer */
56285 #define I2C4                                     ((I2C_Type *)I2C4_BASE)
56286 /** Peripheral I2C5 base address */
56287 #define I2C5_BASE                                (0x30AD0000u)
56288 /** Peripheral I2C5 base pointer */
56289 #define I2C5                                     ((I2C_Type *)I2C5_BASE)
56290 /** Peripheral I2C6 base address */
56291 #define I2C6_BASE                                (0x30AE0000u)
56292 /** Peripheral I2C6 base pointer */
56293 #define I2C6                                     ((I2C_Type *)I2C6_BASE)
56294 /** Array initializer of I2C peripheral base addresses */
56295 #define I2C_BASE_ADDRS                           { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE }
56296 /** Array initializer of I2C peripheral base pointers */
56297 #define I2C_BASE_PTRS                            { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6 }
56298 /** Interrupt vectors for the I2C peripheral type */
56299 #define I2C_IRQS                                 { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn, I2C5_IRQn, I2C6_IRQn }
56300 
56301 /*!
56302  * @}
56303  */ /* end of group I2C_Peripheral_Access_Layer */
56304 
56305 
56306 /* ----------------------------------------------------------------------------
56307    -- I2S Peripheral Access Layer
56308    ---------------------------------------------------------------------------- */
56309 
56310 /*!
56311  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
56312  * @{
56313  */
56314 
56315 /** I2S - Register Layout Typedef */
56316 typedef struct {
56317   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
56318   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
56319   __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x8 */
56320   __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0xC */
56321   __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
56322   __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
56323   __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
56324   __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
56325   __O  uint32_t TDR[8];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
56326   __I  uint32_t TFR[8];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
56327   __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
56328        uint8_t RESERVED_0[12];
56329   __IO uint32_t TTCR;                              /**< SAI Transmit Timestamp Control Register, offset: 0x70 */
56330   __I  uint32_t TTSR;                              /**< SAI Transmit Timestamp Register, offset: 0x74 */
56331   __I  uint32_t TBCR;                              /**< SAI Transmit Bit Count Register, offset: 0x78 */
56332   __I  uint32_t TBCTR;                             /**< SAI Transmit Bit Count Timestamp Register, offset: 0x7C */
56333        uint8_t RESERVED_1[8];
56334   __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x88 */
56335   __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x8C */
56336   __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x90 */
56337   __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x94 */
56338   __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x98 */
56339   __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x9C */
56340   __I  uint32_t RDR[8];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
56341   __I  uint32_t RFR[8];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
56342   __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
56343        uint8_t RESERVED_2[12];
56344   __IO uint32_t RTCR;                              /**< SAI Receive Timestamp Control Register, offset: 0xF0 */
56345   __I  uint32_t RTSR;                              /**< SAI Receive Timestamp Register, offset: 0xF4 */
56346   __I  uint32_t RBCR;                              /**< SAI Receive Bit Count Register, offset: 0xF8 */
56347   __I  uint32_t RBCTR;                             /**< SAI Receive Bit Count Timestamp Register, offset: 0xFC */
56348   __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
56349 } I2S_Type;
56350 
56351 /* ----------------------------------------------------------------------------
56352    -- I2S Register Masks
56353    ---------------------------------------------------------------------------- */
56354 
56355 /*!
56356  * @addtogroup I2S_Register_Masks I2S Register Masks
56357  * @{
56358  */
56359 
56360 /*! @name VERID - Version ID Register */
56361 /*! @{ */
56362 
56363 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
56364 #define I2S_VERID_FEATURE_SHIFT                  (0U)
56365 /*! FEATURE - Feature Specification Number
56366  *  0b0000000000000000..Standard feature set.
56367  *  0b0000000000000010..Standard feature set with Timestamp Registers.
56368  */
56369 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
56370 
56371 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
56372 #define I2S_VERID_MINOR_SHIFT                    (16U)
56373 /*! MINOR - Minor Version Number */
56374 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
56375 
56376 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
56377 #define I2S_VERID_MAJOR_SHIFT                    (24U)
56378 /*! MAJOR - Major Version Number */
56379 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
56380 /*! @} */
56381 
56382 /*! @name PARAM - Parameter Register */
56383 /*! @{ */
56384 
56385 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
56386 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
56387 /*! DATALINE - Number of Datalines */
56388 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
56389 
56390 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
56391 #define I2S_PARAM_FIFO_SHIFT                     (8U)
56392 /*! FIFO - FIFO Size */
56393 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
56394 
56395 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
56396 #define I2S_PARAM_FRAME_SHIFT                    (16U)
56397 /*! FRAME - Frame Size */
56398 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
56399 /*! @} */
56400 
56401 /*! @name TCSR - SAI Transmit Control Register */
56402 /*! @{ */
56403 
56404 #define I2S_TCSR_FRDE_MASK                       (0x1U)
56405 #define I2S_TCSR_FRDE_SHIFT                      (0U)
56406 /*! FRDE - FIFO Request DMA Enable
56407  *  0b0..Disables the DMA request.
56408  *  0b1..Enables the DMA request.
56409  */
56410 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
56411 
56412 #define I2S_TCSR_FWDE_MASK                       (0x2U)
56413 #define I2S_TCSR_FWDE_SHIFT                      (1U)
56414 /*! FWDE - FIFO Warning DMA Enable
56415  *  0b0..Disables the DMA request.
56416  *  0b1..Enables the DMA request.
56417  */
56418 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
56419 
56420 #define I2S_TCSR_FRIE_MASK                       (0x100U)
56421 #define I2S_TCSR_FRIE_SHIFT                      (8U)
56422 /*! FRIE - FIFO Request Interrupt Enable
56423  *  0b0..Disables the interrupt.
56424  *  0b1..Enables the interrupt.
56425  */
56426 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
56427 
56428 #define I2S_TCSR_FWIE_MASK                       (0x200U)
56429 #define I2S_TCSR_FWIE_SHIFT                      (9U)
56430 /*! FWIE - FIFO Warning Interrupt Enable
56431  *  0b0..Disables the interrupt.
56432  *  0b1..Enables the interrupt.
56433  */
56434 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
56435 
56436 #define I2S_TCSR_FEIE_MASK                       (0x400U)
56437 #define I2S_TCSR_FEIE_SHIFT                      (10U)
56438 /*! FEIE - FIFO Error Interrupt Enable
56439  *  0b0..Disables the interrupt.
56440  *  0b1..Enables the interrupt.
56441  */
56442 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
56443 
56444 #define I2S_TCSR_SEIE_MASK                       (0x800U)
56445 #define I2S_TCSR_SEIE_SHIFT                      (11U)
56446 /*! SEIE - Sync Error Interrupt Enable
56447  *  0b0..Disables interrupt.
56448  *  0b1..Enables interrupt.
56449  */
56450 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
56451 
56452 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
56453 #define I2S_TCSR_WSIE_SHIFT                      (12U)
56454 /*! WSIE - Word Start Interrupt Enable
56455  *  0b0..Disables interrupt.
56456  *  0b1..Enables interrupt.
56457  */
56458 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
56459 
56460 #define I2S_TCSR_FRF_MASK                        (0x10000U)
56461 #define I2S_TCSR_FRF_SHIFT                       (16U)
56462 /*! FRF - FIFO Request Flag
56463  *  0b0..Transmit FIFO watermark has not been reached.
56464  *  0b1..Transmit FIFO watermark has been reached.
56465  */
56466 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
56467 
56468 #define I2S_TCSR_FWF_MASK                        (0x20000U)
56469 #define I2S_TCSR_FWF_SHIFT                       (17U)
56470 /*! FWF - FIFO Warning Flag
56471  *  0b0..No enabled transmit FIFO is empty.
56472  *  0b1..Enabled transmit FIFO is empty.
56473  */
56474 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
56475 
56476 #define I2S_TCSR_FEF_MASK                        (0x40000U)
56477 #define I2S_TCSR_FEF_SHIFT                       (18U)
56478 /*! FEF - FIFO Error Flag
56479  *  0b0..Transmit underrun not detected.
56480  *  0b1..Transmit underrun detected.
56481  */
56482 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
56483 
56484 #define I2S_TCSR_SEF_MASK                        (0x80000U)
56485 #define I2S_TCSR_SEF_SHIFT                       (19U)
56486 /*! SEF - Sync Error Flag
56487  *  0b0..Sync error not detected.
56488  *  0b1..Frame sync error detected.
56489  */
56490 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
56491 
56492 #define I2S_TCSR_WSF_MASK                        (0x100000U)
56493 #define I2S_TCSR_WSF_SHIFT                       (20U)
56494 /*! WSF - Word Start Flag
56495  *  0b0..Start of word not detected.
56496  *  0b1..Start of word detected.
56497  */
56498 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
56499 
56500 #define I2S_TCSR_SR_MASK                         (0x1000000U)
56501 #define I2S_TCSR_SR_SHIFT                        (24U)
56502 /*! SR - Software Reset
56503  *  0b0..No effect.
56504  *  0b1..Software reset.
56505  */
56506 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
56507 
56508 #define I2S_TCSR_FR_MASK                         (0x2000000U)
56509 #define I2S_TCSR_FR_SHIFT                        (25U)
56510 /*! FR - FIFO Reset
56511  *  0b0..No effect.
56512  *  0b1..FIFO reset.
56513  */
56514 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
56515 
56516 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
56517 #define I2S_TCSR_BCE_SHIFT                       (28U)
56518 /*! BCE - Bit Clock Enable
56519  *  0b0..Transmit bit clock is disabled.
56520  *  0b1..Transmit bit clock is enabled.
56521  */
56522 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
56523 
56524 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
56525 #define I2S_TCSR_DBGE_SHIFT                      (29U)
56526 /*! DBGE - Debug Enable
56527  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
56528  *  0b1..Transmitter is enabled in Debug mode.
56529  */
56530 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
56531 
56532 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
56533 #define I2S_TCSR_STOPE_SHIFT                     (30U)
56534 /*! STOPE - Stop Enable
56535  *  0b0..Transmitter disabled in Stop mode.
56536  *  0b1..Transmitter enabled in Stop mode.
56537  */
56538 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
56539 
56540 #define I2S_TCSR_TE_MASK                         (0x80000000U)
56541 #define I2S_TCSR_TE_SHIFT                        (31U)
56542 /*! TE - Transmitter Enable
56543  *  0b0..Transmitter is disabled.
56544  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
56545  */
56546 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
56547 /*! @} */
56548 
56549 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
56550 /*! @{ */
56551 
56552 #define I2S_TCR1_TFW_MASK                        (0x7FU)
56553 #define I2S_TCR1_TFW_SHIFT                       (0U)
56554 /*! TFW - Transmit FIFO Watermark */
56555 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
56556 /*! @} */
56557 
56558 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
56559 /*! @{ */
56560 
56561 #define I2S_TCR2_DIV_MASK                        (0xFFU)
56562 #define I2S_TCR2_DIV_SHIFT                       (0U)
56563 /*! DIV - Bit Clock Divide */
56564 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
56565 
56566 #define I2S_TCR2_BYP_MASK                        (0x800000U)
56567 #define I2S_TCR2_BYP_SHIFT                       (23U)
56568 /*! BYP - Bit Clock Bypass
56569  *  0b0..Internal bit clock is generated from bit clock divider.
56570  *  0b1..Internal bit clock is divide by one of the audio master clock.
56571  */
56572 #define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
56573 
56574 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
56575 #define I2S_TCR2_BCD_SHIFT                       (24U)
56576 /*! BCD - Bit Clock Direction
56577  *  0b0..Bit clock is generated externally in Slave mode.
56578  *  0b1..Bit clock is generated internally in Master mode.
56579  */
56580 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
56581 
56582 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
56583 #define I2S_TCR2_BCP_SHIFT                       (25U)
56584 /*! BCP - Bit Clock Polarity
56585  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
56586  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
56587  */
56588 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
56589 
56590 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
56591 #define I2S_TCR2_MSEL_SHIFT                      (26U)
56592 /*! MSEL - MCLK Select
56593  *  0b00..Bus Clock selected.
56594  *  0b01..Master Clock (MCLK) 1 option selected.
56595  *  0b10..Master Clock (MCLK) 2 option selected.
56596  *  0b11..Master Clock (MCLK) 3 option selected.
56597  */
56598 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
56599 
56600 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
56601 #define I2S_TCR2_BCI_SHIFT                       (28U)
56602 /*! BCI - Bit Clock Input
56603  *  0b0..No effect.
56604  *  0b1..Internal logic is clocked as if bit clock was externally generated.
56605  */
56606 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
56607 
56608 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
56609 #define I2S_TCR2_BCS_SHIFT                       (29U)
56610 /*! BCS - Bit Clock Swap
56611  *  0b0..Use the normal bit clock source.
56612  *  0b1..Swap the bit clock source.
56613  */
56614 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
56615 
56616 #define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
56617 #define I2S_TCR2_SYNC_SHIFT                      (30U)
56618 /*! SYNC - Synchronous Mode
56619  *  0b00..Asynchronous mode.
56620  *  0b01..Synchronous with receiver.
56621  *  0b10..Reserved.
56622  *  0b11..Reserved.
56623  */
56624 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
56625 /*! @} */
56626 
56627 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
56628 /*! @{ */
56629 
56630 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
56631 #define I2S_TCR3_WDFL_SHIFT                      (0U)
56632 /*! WDFL - Word Flag Configuration */
56633 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
56634 
56635 #define I2S_TCR3_TCE_MASK                        (0xFF0000U)
56636 #define I2S_TCR3_TCE_SHIFT                       (16U)
56637 /*! TCE - Transmit Channel Enable */
56638 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
56639 
56640 #define I2S_TCR3_CFR_MASK                        (0xFF000000U)
56641 #define I2S_TCR3_CFR_SHIFT                       (24U)
56642 /*! CFR - Channel FIFO Reset */
56643 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
56644 /*! @} */
56645 
56646 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
56647 /*! @{ */
56648 
56649 #define I2S_TCR4_FSD_MASK                        (0x1U)
56650 #define I2S_TCR4_FSD_SHIFT                       (0U)
56651 /*! FSD - Frame Sync Direction
56652  *  0b0..Frame sync is generated externally in Slave mode.
56653  *  0b1..Frame sync is generated internally in Master mode.
56654  */
56655 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
56656 
56657 #define I2S_TCR4_FSP_MASK                        (0x2U)
56658 #define I2S_TCR4_FSP_SHIFT                       (1U)
56659 /*! FSP - Frame Sync Polarity
56660  *  0b0..Frame sync is active high.
56661  *  0b1..Frame sync is active low.
56662  */
56663 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
56664 
56665 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
56666 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
56667 /*! ONDEM - On Demand Mode
56668  *  0b0..Internal frame sync is generated continuously.
56669  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
56670  */
56671 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
56672 
56673 #define I2S_TCR4_FSE_MASK                        (0x8U)
56674 #define I2S_TCR4_FSE_SHIFT                       (3U)
56675 /*! FSE - Frame Sync Early
56676  *  0b0..Frame sync asserts with the first bit of the frame.
56677  *  0b1..Frame sync asserts one bit before the first bit of the frame.
56678  */
56679 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
56680 
56681 #define I2S_TCR4_MF_MASK                         (0x10U)
56682 #define I2S_TCR4_MF_SHIFT                        (4U)
56683 /*! MF - MSB First
56684  *  0b0..LSB is transmitted first.
56685  *  0b1..MSB is transmitted first.
56686  */
56687 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
56688 
56689 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
56690 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
56691 /*! CHMOD - Channel Mode
56692  *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
56693  *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
56694  */
56695 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
56696 
56697 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
56698 #define I2S_TCR4_SYWD_SHIFT                      (8U)
56699 /*! SYWD - Sync Width */
56700 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
56701 
56702 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
56703 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
56704 /*! FRSZ - Frame size */
56705 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
56706 
56707 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
56708 #define I2S_TCR4_FPACK_SHIFT                     (24U)
56709 /*! FPACK - FIFO Packing Mode
56710  *  0b00..FIFO packing is disabled
56711  *  0b01..Reserved
56712  *  0b10..8-bit FIFO packing is enabled
56713  *  0b11..16-bit FIFO packing is enabled
56714  */
56715 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
56716 
56717 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
56718 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
56719 /*! FCOMB - FIFO Combine Mode
56720  *  0b00..FIFO combine mode disabled.
56721  *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
56722  *  0b10..FIFO combine mode enabled on FIFO writes (by software).
56723  *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
56724  */
56725 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
56726 
56727 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
56728 #define I2S_TCR4_FCONT_SHIFT                     (28U)
56729 /*! FCONT - FIFO Continue on Error
56730  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
56731  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
56732  */
56733 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
56734 /*! @} */
56735 
56736 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
56737 /*! @{ */
56738 
56739 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
56740 #define I2S_TCR5_FBT_SHIFT                       (8U)
56741 /*! FBT - First Bit Shifted */
56742 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
56743 
56744 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
56745 #define I2S_TCR5_W0W_SHIFT                       (16U)
56746 /*! W0W - Word 0 Width */
56747 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
56748 
56749 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
56750 #define I2S_TCR5_WNW_SHIFT                       (24U)
56751 /*! WNW - Word N Width */
56752 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
56753 /*! @} */
56754 
56755 /*! @name TDR - SAI Transmit Data Register */
56756 /*! @{ */
56757 
56758 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
56759 #define I2S_TDR_TDR_SHIFT                        (0U)
56760 /*! TDR - Transmit Data Register */
56761 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
56762 /*! @} */
56763 
56764 /* The count of I2S_TDR */
56765 #define I2S_TDR_COUNT                            (8U)
56766 
56767 /*! @name TFR - SAI Transmit FIFO Register */
56768 /*! @{ */
56769 
56770 #define I2S_TFR_RFP_MASK                         (0xFFU)
56771 #define I2S_TFR_RFP_SHIFT                        (0U)
56772 /*! RFP - Read FIFO Pointer */
56773 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
56774 
56775 #define I2S_TFR_WFP_MASK                         (0xFF0000U)
56776 #define I2S_TFR_WFP_SHIFT                        (16U)
56777 /*! WFP - Write FIFO Pointer */
56778 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
56779 
56780 #define I2S_TFR_WCP_MASK                         (0x80000000U)
56781 #define I2S_TFR_WCP_SHIFT                        (31U)
56782 /*! WCP - Write Channel Pointer
56783  *  0b0..No effect.
56784  *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
56785  */
56786 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
56787 /*! @} */
56788 
56789 /* The count of I2S_TFR */
56790 #define I2S_TFR_COUNT                            (8U)
56791 
56792 /*! @name TMR - SAI Transmit Mask Register */
56793 /*! @{ */
56794 
56795 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
56796 #define I2S_TMR_TWM_SHIFT                        (0U)
56797 /*! TWM - Transmit Word Mask
56798  *  0b00000000000000000000000000000000..Word N is enabled.
56799  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
56800  */
56801 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
56802 /*! @} */
56803 
56804 /*! @name TTCR - SAI Transmit Timestamp Control Register */
56805 /*! @{ */
56806 
56807 #define I2S_TTCR_TSEN_MASK                       (0x1U)
56808 #define I2S_TTCR_TSEN_SHIFT                      (0U)
56809 /*! TSEN - Timestamp Enable
56810  *  0b0..Timestamp counter is disabled.
56811  *  0b1..Timestamp counter is enabled.
56812  */
56813 #define I2S_TTCR_TSEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK)
56814 
56815 #define I2S_TTCR_TSINC_MASK                      (0x2U)
56816 #define I2S_TTCR_TSINC_SHIFT                     (1U)
56817 /*! TSINC - Timestamp Increment
56818  *  0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
56819  *  0b1..Timestamp counter starts to increment when enabled.
56820  */
56821 #define I2S_TTCR_TSINC(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK)
56822 
56823 #define I2S_TTCR_RTSC_MASK                       (0x100U)
56824 #define I2S_TTCR_RTSC_SHIFT                      (8U)
56825 /*! RTSC - Reset Timestamp Counter
56826  *  0b0..Timestamp counter is not reset.
56827  *  0b1..Timestamp counter is reset.
56828  */
56829 #define I2S_TTCR_RTSC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK)
56830 
56831 #define I2S_TTCR_RBC_MASK                        (0x200U)
56832 #define I2S_TTCR_RBC_SHIFT                       (9U)
56833 /*! RBC - Reset Bit Counter
56834  *  0b0..Bit counter is not reset.
56835  *  0b1..Bit counter is reset.
56836  */
56837 #define I2S_TTCR_RBC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK)
56838 /*! @} */
56839 
56840 /*! @name TTSR - SAI Transmit Timestamp Register */
56841 /*! @{ */
56842 
56843 #define I2S_TTSR_TSC_MASK                        (0xFFFFFFFFU)
56844 #define I2S_TTSR_TSC_SHIFT                       (0U)
56845 /*! TSC - Timestamp Counter */
56846 #define I2S_TTSR_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK)
56847 /*! @} */
56848 
56849 /*! @name TBCR - SAI Transmit Bit Count Register */
56850 /*! @{ */
56851 
56852 #define I2S_TBCR_BCNT_MASK                       (0xFFFFFFFFU)
56853 #define I2S_TBCR_BCNT_SHIFT                      (0U)
56854 /*! BCNT - Bit Counter */
56855 #define I2S_TBCR_BCNT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK)
56856 /*! @} */
56857 
56858 /*! @name TBCTR - SAI Transmit Bit Count Timestamp Register */
56859 /*! @{ */
56860 
56861 #define I2S_TBCTR_BCTS_MASK                      (0xFFFFFFFFU)
56862 #define I2S_TBCTR_BCTS_SHIFT                     (0U)
56863 /*! BCTS - Bit Timestamp */
56864 #define I2S_TBCTR_BCTS(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK)
56865 /*! @} */
56866 
56867 /*! @name RCSR - SAI Receive Control Register */
56868 /*! @{ */
56869 
56870 #define I2S_RCSR_FRDE_MASK                       (0x1U)
56871 #define I2S_RCSR_FRDE_SHIFT                      (0U)
56872 /*! FRDE - FIFO Request DMA Enable
56873  *  0b0..Disables the DMA request.
56874  *  0b1..Enables the DMA request.
56875  */
56876 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
56877 
56878 #define I2S_RCSR_FWDE_MASK                       (0x2U)
56879 #define I2S_RCSR_FWDE_SHIFT                      (1U)
56880 /*! FWDE - FIFO Warning DMA Enable
56881  *  0b0..Disables the DMA request.
56882  *  0b1..Enables the DMA request.
56883  */
56884 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
56885 
56886 #define I2S_RCSR_FRIE_MASK                       (0x100U)
56887 #define I2S_RCSR_FRIE_SHIFT                      (8U)
56888 /*! FRIE - FIFO Request Interrupt Enable
56889  *  0b0..Disables the interrupt.
56890  *  0b1..Enables the interrupt.
56891  */
56892 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
56893 
56894 #define I2S_RCSR_FWIE_MASK                       (0x200U)
56895 #define I2S_RCSR_FWIE_SHIFT                      (9U)
56896 /*! FWIE - FIFO Warning Interrupt Enable
56897  *  0b0..Disables the interrupt.
56898  *  0b1..Enables the interrupt.
56899  */
56900 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
56901 
56902 #define I2S_RCSR_FEIE_MASK                       (0x400U)
56903 #define I2S_RCSR_FEIE_SHIFT                      (10U)
56904 /*! FEIE - FIFO Error Interrupt Enable
56905  *  0b0..Disables the interrupt.
56906  *  0b1..Enables the interrupt.
56907  */
56908 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
56909 
56910 #define I2S_RCSR_SEIE_MASK                       (0x800U)
56911 #define I2S_RCSR_SEIE_SHIFT                      (11U)
56912 /*! SEIE - Sync Error Interrupt Enable
56913  *  0b0..Disables interrupt.
56914  *  0b1..Enables interrupt.
56915  */
56916 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
56917 
56918 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
56919 #define I2S_RCSR_WSIE_SHIFT                      (12U)
56920 /*! WSIE - Word Start Interrupt Enable
56921  *  0b0..Disables interrupt.
56922  *  0b1..Enables interrupt.
56923  */
56924 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
56925 
56926 #define I2S_RCSR_FRF_MASK                        (0x10000U)
56927 #define I2S_RCSR_FRF_SHIFT                       (16U)
56928 /*! FRF - FIFO Request Flag
56929  *  0b0..Receive FIFO watermark not reached.
56930  *  0b1..Receive FIFO watermark has been reached.
56931  */
56932 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
56933 
56934 #define I2S_RCSR_FWF_MASK                        (0x20000U)
56935 #define I2S_RCSR_FWF_SHIFT                       (17U)
56936 /*! FWF - FIFO Warning Flag
56937  *  0b0..No enabled receive FIFO is full.
56938  *  0b1..Enabled receive FIFO is full.
56939  */
56940 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
56941 
56942 #define I2S_RCSR_FEF_MASK                        (0x40000U)
56943 #define I2S_RCSR_FEF_SHIFT                       (18U)
56944 /*! FEF - FIFO Error Flag
56945  *  0b0..Receive overflow not detected.
56946  *  0b1..Receive overflow detected.
56947  */
56948 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
56949 
56950 #define I2S_RCSR_SEF_MASK                        (0x80000U)
56951 #define I2S_RCSR_SEF_SHIFT                       (19U)
56952 /*! SEF - Sync Error Flag
56953  *  0b0..Sync error not detected.
56954  *  0b1..Frame sync error detected.
56955  */
56956 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
56957 
56958 #define I2S_RCSR_WSF_MASK                        (0x100000U)
56959 #define I2S_RCSR_WSF_SHIFT                       (20U)
56960 /*! WSF - Word Start Flag
56961  *  0b0..Start of word not detected.
56962  *  0b1..Start of word detected.
56963  */
56964 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
56965 
56966 #define I2S_RCSR_SR_MASK                         (0x1000000U)
56967 #define I2S_RCSR_SR_SHIFT                        (24U)
56968 /*! SR - Software Reset
56969  *  0b0..No effect.
56970  *  0b1..Software reset.
56971  */
56972 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
56973 
56974 #define I2S_RCSR_FR_MASK                         (0x2000000U)
56975 #define I2S_RCSR_FR_SHIFT                        (25U)
56976 /*! FR - FIFO Reset
56977  *  0b0..No effect.
56978  *  0b1..FIFO reset.
56979  */
56980 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
56981 
56982 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
56983 #define I2S_RCSR_BCE_SHIFT                       (28U)
56984 /*! BCE - Bit Clock Enable
56985  *  0b0..Receive bit clock is disabled.
56986  *  0b1..Receive bit clock is enabled.
56987  */
56988 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
56989 
56990 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
56991 #define I2S_RCSR_DBGE_SHIFT                      (29U)
56992 /*! DBGE - Debug Enable
56993  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
56994  *  0b1..Receiver is enabled in Debug mode.
56995  */
56996 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
56997 
56998 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
56999 #define I2S_RCSR_STOPE_SHIFT                     (30U)
57000 /*! STOPE - Stop Enable
57001  *  0b0..Receiver disabled in Stop mode.
57002  *  0b1..Receiver enabled in Stop mode.
57003  */
57004 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
57005 
57006 #define I2S_RCSR_RE_MASK                         (0x80000000U)
57007 #define I2S_RCSR_RE_SHIFT                        (31U)
57008 /*! RE - Receiver Enable
57009  *  0b0..Receiver is disabled.
57010  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
57011  */
57012 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
57013 /*! @} */
57014 
57015 /*! @name RCR1 - SAI Receive Configuration 1 Register */
57016 /*! @{ */
57017 
57018 #define I2S_RCR1_RFW_MASK                        (0x7FU)
57019 #define I2S_RCR1_RFW_SHIFT                       (0U)
57020 /*! RFW - Receive FIFO Watermark */
57021 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
57022 /*! @} */
57023 
57024 /*! @name RCR2 - SAI Receive Configuration 2 Register */
57025 /*! @{ */
57026 
57027 #define I2S_RCR2_DIV_MASK                        (0xFFU)
57028 #define I2S_RCR2_DIV_SHIFT                       (0U)
57029 /*! DIV - Bit Clock Divide */
57030 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
57031 
57032 #define I2S_RCR2_BYP_MASK                        (0x800000U)
57033 #define I2S_RCR2_BYP_SHIFT                       (23U)
57034 /*! BYP - Bit Clock Bypass
57035  *  0b0..Internal bit clock is generated from bit clock divider.
57036  *  0b1..Internal bit clock is divide by one of the audio master clock.
57037  */
57038 #define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
57039 
57040 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
57041 #define I2S_RCR2_BCD_SHIFT                       (24U)
57042 /*! BCD - Bit Clock Direction
57043  *  0b0..Bit clock is generated externally in Slave mode.
57044  *  0b1..Bit clock is generated internally in Master mode.
57045  */
57046 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
57047 
57048 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
57049 #define I2S_RCR2_BCP_SHIFT                       (25U)
57050 /*! BCP - Bit Clock Polarity
57051  *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
57052  *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
57053  */
57054 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
57055 
57056 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
57057 #define I2S_RCR2_MSEL_SHIFT                      (26U)
57058 /*! MSEL - MCLK Select
57059  *  0b00..Bus Clock selected.
57060  *  0b01..Master Clock (MCLK) 1 option selected.
57061  *  0b10..Master Clock (MCLK) 2 option selected.
57062  *  0b11..Master Clock (MCLK) 3 option selected.
57063  */
57064 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
57065 
57066 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
57067 #define I2S_RCR2_BCI_SHIFT                       (28U)
57068 /*! BCI - Bit Clock Input
57069  *  0b0..No effect.
57070  *  0b1..Internal logic is clocked as if bit clock was externally generated.
57071  */
57072 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
57073 
57074 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
57075 #define I2S_RCR2_BCS_SHIFT                       (29U)
57076 /*! BCS - Bit Clock Swap
57077  *  0b0..Use the normal bit clock source.
57078  *  0b1..Swap the bit clock source.
57079  */
57080 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
57081 
57082 #define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
57083 #define I2S_RCR2_SYNC_SHIFT                      (30U)
57084 /*! SYNC - Synchronous Mode
57085  *  0b00..Asynchronous mode.
57086  *  0b01..Synchronous with transmitter.
57087  *  0b10..Reserved.
57088  *  0b11..Reserved.
57089  */
57090 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
57091 /*! @} */
57092 
57093 /*! @name RCR3 - SAI Receive Configuration 3 Register */
57094 /*! @{ */
57095 
57096 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
57097 #define I2S_RCR3_WDFL_SHIFT                      (0U)
57098 /*! WDFL - Word Flag Configuration */
57099 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
57100 
57101 #define I2S_RCR3_RCE_MASK                        (0xFF0000U)
57102 #define I2S_RCR3_RCE_SHIFT                       (16U)
57103 /*! RCE - Receive Channel Enable */
57104 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
57105 
57106 #define I2S_RCR3_CFR_MASK                        (0xFF000000U)
57107 #define I2S_RCR3_CFR_SHIFT                       (24U)
57108 /*! CFR - Channel FIFO Reset */
57109 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
57110 /*! @} */
57111 
57112 /*! @name RCR4 - SAI Receive Configuration 4 Register */
57113 /*! @{ */
57114 
57115 #define I2S_RCR4_FSD_MASK                        (0x1U)
57116 #define I2S_RCR4_FSD_SHIFT                       (0U)
57117 /*! FSD - Frame Sync Direction
57118  *  0b0..Frame Sync is generated externally in Slave mode.
57119  *  0b1..Frame Sync is generated internally in Master mode.
57120  */
57121 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
57122 
57123 #define I2S_RCR4_FSP_MASK                        (0x2U)
57124 #define I2S_RCR4_FSP_SHIFT                       (1U)
57125 /*! FSP - Frame Sync Polarity
57126  *  0b0..Frame sync is active high.
57127  *  0b1..Frame sync is active low.
57128  */
57129 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
57130 
57131 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
57132 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
57133 /*! ONDEM - On Demand Mode
57134  *  0b0..Internal frame sync is generated continuously.
57135  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
57136  */
57137 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
57138 
57139 #define I2S_RCR4_FSE_MASK                        (0x8U)
57140 #define I2S_RCR4_FSE_SHIFT                       (3U)
57141 /*! FSE - Frame Sync Early
57142  *  0b0..Frame sync asserts with the first bit of the frame.
57143  *  0b1..Frame sync asserts one bit before the first bit of the frame.
57144  */
57145 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
57146 
57147 #define I2S_RCR4_MF_MASK                         (0x10U)
57148 #define I2S_RCR4_MF_SHIFT                        (4U)
57149 /*! MF - MSB First
57150  *  0b0..LSB is received first.
57151  *  0b1..MSB is received first.
57152  */
57153 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
57154 
57155 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
57156 #define I2S_RCR4_SYWD_SHIFT                      (8U)
57157 /*! SYWD - Sync Width */
57158 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
57159 
57160 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
57161 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
57162 /*! FRSZ - Frame Size */
57163 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
57164 
57165 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
57166 #define I2S_RCR4_FPACK_SHIFT                     (24U)
57167 /*! FPACK - FIFO Packing Mode
57168  *  0b00..FIFO packing is disabled
57169  *  0b01..Reserved.
57170  *  0b10..8-bit FIFO packing is enabled
57171  *  0b11..16-bit FIFO packing is enabled
57172  */
57173 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
57174 
57175 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
57176 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
57177 /*! FCOMB - FIFO Combine Mode
57178  *  0b00..FIFO combine mode disabled.
57179  *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
57180  *  0b10..FIFO combine mode enabled on FIFO reads (by software).
57181  *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
57182  */
57183 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
57184 
57185 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
57186 #define I2S_RCR4_FCONT_SHIFT                     (28U)
57187 /*! FCONT - FIFO Continue on Error
57188  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
57189  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
57190  */
57191 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
57192 /*! @} */
57193 
57194 /*! @name RCR5 - SAI Receive Configuration 5 Register */
57195 /*! @{ */
57196 
57197 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
57198 #define I2S_RCR5_FBT_SHIFT                       (8U)
57199 /*! FBT - First Bit Shifted */
57200 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
57201 
57202 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
57203 #define I2S_RCR5_W0W_SHIFT                       (16U)
57204 /*! W0W - Word 0 Width */
57205 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
57206 
57207 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
57208 #define I2S_RCR5_WNW_SHIFT                       (24U)
57209 /*! WNW - Word N Width */
57210 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
57211 /*! @} */
57212 
57213 /*! @name RDR - SAI Receive Data Register */
57214 /*! @{ */
57215 
57216 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
57217 #define I2S_RDR_RDR_SHIFT                        (0U)
57218 /*! RDR - Receive Data Register */
57219 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
57220 /*! @} */
57221 
57222 /* The count of I2S_RDR */
57223 #define I2S_RDR_COUNT                            (8U)
57224 
57225 /*! @name RFR - SAI Receive FIFO Register */
57226 /*! @{ */
57227 
57228 #define I2S_RFR_RFP_MASK                         (0xFFU)
57229 #define I2S_RFR_RFP_SHIFT                        (0U)
57230 /*! RFP - Read FIFO Pointer */
57231 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
57232 
57233 #define I2S_RFR_RCP_MASK                         (0x8000U)
57234 #define I2S_RFR_RCP_SHIFT                        (15U)
57235 /*! RCP - Receive Channel Pointer
57236  *  0b0..No effect.
57237  *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
57238  */
57239 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
57240 
57241 #define I2S_RFR_WFP_MASK                         (0xFF0000U)
57242 #define I2S_RFR_WFP_SHIFT                        (16U)
57243 /*! WFP - Write FIFO Pointer */
57244 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
57245 /*! @} */
57246 
57247 /* The count of I2S_RFR */
57248 #define I2S_RFR_COUNT                            (8U)
57249 
57250 /*! @name RMR - SAI Receive Mask Register */
57251 /*! @{ */
57252 
57253 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
57254 #define I2S_RMR_RWM_SHIFT                        (0U)
57255 /*! RWM - Receive Word Mask
57256  *  0b00000000000000000000000000000000..Word N is enabled.
57257  *  0b00000000000000000000000000000001..Word N is masked.
57258  */
57259 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
57260 /*! @} */
57261 
57262 /*! @name RTCR - SAI Receive Timestamp Control Register */
57263 /*! @{ */
57264 
57265 #define I2S_RTCR_TSEN_MASK                       (0x1U)
57266 #define I2S_RTCR_TSEN_SHIFT                      (0U)
57267 /*! TSEN - Timestamp Enable
57268  *  0b0..Timestamp counter is disabled.
57269  *  0b1..Timestamp counter is enabled.
57270  */
57271 #define I2S_RTCR_TSEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK)
57272 
57273 #define I2S_RTCR_TSINC_MASK                      (0x2U)
57274 #define I2S_RTCR_TSINC_SHIFT                     (1U)
57275 /*! TSINC - Timestamp Increment
57276  *  0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
57277  *  0b1..Timestamp counter starts to increment when enabled.
57278  */
57279 #define I2S_RTCR_TSINC(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK)
57280 
57281 #define I2S_RTCR_RTSC_MASK                       (0x100U)
57282 #define I2S_RTCR_RTSC_SHIFT                      (8U)
57283 /*! RTSC - Reset Timestamp Counter
57284  *  0b0..Timestamp counter is not reset.
57285  *  0b1..Timestamp counter is reset.
57286  */
57287 #define I2S_RTCR_RTSC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK)
57288 
57289 #define I2S_RTCR_RBC_MASK                        (0x200U)
57290 #define I2S_RTCR_RBC_SHIFT                       (9U)
57291 /*! RBC - Reset Bit Counter
57292  *  0b0..Bit counter is not reset.
57293  *  0b1..Bit counter is reset.
57294  */
57295 #define I2S_RTCR_RBC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK)
57296 /*! @} */
57297 
57298 /*! @name RTSR - SAI Receive Timestamp Register */
57299 /*! @{ */
57300 
57301 #define I2S_RTSR_TSC_MASK                        (0xFFFFFFFFU)
57302 #define I2S_RTSR_TSC_SHIFT                       (0U)
57303 /*! TSC - Timestamp Counter */
57304 #define I2S_RTSR_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK)
57305 /*! @} */
57306 
57307 /*! @name RBCR - SAI Receive Bit Count Register */
57308 /*! @{ */
57309 
57310 #define I2S_RBCR_BCNT_MASK                       (0xFFFFFFFFU)
57311 #define I2S_RBCR_BCNT_SHIFT                      (0U)
57312 /*! BCNT - Bit Counter */
57313 #define I2S_RBCR_BCNT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK)
57314 /*! @} */
57315 
57316 /*! @name RBCTR - SAI Receive Bit Count Timestamp Register */
57317 /*! @{ */
57318 
57319 #define I2S_RBCTR_BCTS_MASK                      (0xFFFFFFFFU)
57320 #define I2S_RBCTR_BCTS_SHIFT                     (0U)
57321 /*! BCTS - Bit Timestamp */
57322 #define I2S_RBCTR_BCTS(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK)
57323 /*! @} */
57324 
57325 /*! @name MCR - SAI MCLK Control Register */
57326 /*! @{ */
57327 
57328 #define I2S_MCR_DIV_MASK                         (0xFFU)
57329 #define I2S_MCR_DIV_SHIFT                        (0U)
57330 /*! DIV - MCLK Post Divide */
57331 #define I2S_MCR_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK)
57332 
57333 #define I2S_MCR_DIVEN_MASK                       (0x800000U)
57334 #define I2S_MCR_DIVEN_SHIFT                      (23U)
57335 /*! DIVEN - MCLK Post Divide Enable
57336  *  0b0..Output on MCLK signal pin is the audio master clock.
57337  *  0b1..Output on MCLK signal pin is a post-divided version of audio master clock.
57338  */
57339 #define I2S_MCR_DIVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK)
57340 
57341 #define I2S_MCR_MOE_MASK                         (0x40000000U)
57342 #define I2S_MCR_MOE_SHIFT                        (30U)
57343 /*! MOE - MCLK Output Enable
57344  *  0b0..MCLK signal pin is an input.
57345  *  0b1..MCLK signal pin is an output.
57346  */
57347 #define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
57348 /*! @} */
57349 
57350 
57351 /*!
57352  * @}
57353  */ /* end of group I2S_Register_Masks */
57354 
57355 
57356 /* I2S - Peripheral instance base addresses */
57357 /** Peripheral I2S1 base address */
57358 #define I2S1_BASE                                (0x30C10000u)
57359 /** Peripheral I2S1 base pointer */
57360 #define I2S1                                     ((I2S_Type *)I2S1_BASE)
57361 /** Peripheral I2S2 base address */
57362 #define I2S2_BASE                                (0x30C20000u)
57363 /** Peripheral I2S2 base pointer */
57364 #define I2S2                                     ((I2S_Type *)I2S2_BASE)
57365 /** Peripheral I2S3 base address */
57366 #define I2S3_BASE                                (0x30C30000u)
57367 /** Peripheral I2S3 base pointer */
57368 #define I2S3                                     ((I2S_Type *)I2S3_BASE)
57369 /** Peripheral I2S5 base address */
57370 #define I2S5_BASE                                (0x30C50000u)
57371 /** Peripheral I2S5 base pointer */
57372 #define I2S5                                     ((I2S_Type *)I2S5_BASE)
57373 /** Peripheral I2S6 base address */
57374 #define I2S6_BASE                                (0x30C60000u)
57375 /** Peripheral I2S6 base pointer */
57376 #define I2S6                                     ((I2S_Type *)I2S6_BASE)
57377 /** Peripheral I2S7 base address */
57378 #define I2S7_BASE                                (0x30C80000u)
57379 /** Peripheral I2S7 base pointer */
57380 #define I2S7                                     ((I2S_Type *)I2S7_BASE)
57381 /** Array initializer of I2S peripheral base addresses */
57382 #define I2S_BASE_ADDRS                           { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE, 0u, I2S5_BASE, I2S6_BASE, I2S7_BASE }
57383 /** Array initializer of I2S peripheral base pointers */
57384 #define I2S_BASE_PTRS                            { (I2S_Type *)0u, I2S1, I2S2, I2S3, (I2S_Type *)0u, I2S5, I2S6, I2S7 }
57385 /** Interrupt vectors for the I2S peripheral type */
57386 #define I2S_RX_IRQS                              { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn }
57387 #define I2S_TX_IRQS                              { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn }
57388 
57389 /*!
57390  * @}
57391  */ /* end of group I2S_Peripheral_Access_Layer */
57392 
57393 
57394 /* ----------------------------------------------------------------------------
57395    -- IDENTIFICATION Peripheral Access Layer
57396    ---------------------------------------------------------------------------- */
57397 
57398 /*!
57399  * @addtogroup IDENTIFICATION_Peripheral_Access_Layer IDENTIFICATION Peripheral Access Layer
57400  * @{
57401  */
57402 
57403 /** IDENTIFICATION - Register Layout Typedef */
57404 typedef struct {
57405   __I  uint8_t DESIGN_ID;                          /**< Design Identification Register, offset: 0x0 */
57406   __I  uint8_t REVISION_ID;                        /**< Revision Identification Register, offset: 0x1 */
57407   __I  uint8_t PRODUCT_ID0;                        /**< Product Identification Register 0, offset: 0x2 */
57408   __I  uint8_t PRODUCT_ID1;                        /**< Product Identification Register 1, offset: 0x3 */
57409   __I  uint8_t CONFIG0_ID;                         /**< Configuration Identification Register 0, offset: 0x4 */
57410   __I  uint8_t CONFIG1_ID;                         /**< Configuration Identification Register 1, offset: 0x5 */
57411   __I  uint8_t CONFIG2_ID;                         /**< Configuration Identification Register 2, offset: 0x6 */
57412   __I  uint8_t CONFIG3_ID;                         /**< Configuration Identification Register 3, offset: 0x7 */
57413 } IDENTIFICATION_Type;
57414 
57415 /* ----------------------------------------------------------------------------
57416    -- IDENTIFICATION Register Masks
57417    ---------------------------------------------------------------------------- */
57418 
57419 /*!
57420  * @addtogroup IDENTIFICATION_Register_Masks IDENTIFICATION Register Masks
57421  * @{
57422  */
57423 
57424 /*! @name DESIGN_ID - Design Identification Register */
57425 /*! @{ */
57426 
57427 #define IDENTIFICATION_DESIGN_ID_design_id_MASK  (0xFFU)
57428 #define IDENTIFICATION_DESIGN_ID_design_id_SHIFT (0U)
57429 /*! design_id - Design ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller. */
57430 #define IDENTIFICATION_DESIGN_ID_design_id(x)    (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_DESIGN_ID_design_id_SHIFT)) & IDENTIFICATION_DESIGN_ID_design_id_MASK)
57431 /*! @} */
57432 
57433 /*! @name REVISION_ID - Revision Identification Register */
57434 /*! @{ */
57435 
57436 #define IDENTIFICATION_REVISION_ID_revision_id_MASK (0xFFU)
57437 #define IDENTIFICATION_REVISION_ID_revision_id_SHIFT (0U)
57438 /*! revision_id - Revision ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller. */
57439 #define IDENTIFICATION_REVISION_ID_revision_id(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_REVISION_ID_revision_id_SHIFT)) & IDENTIFICATION_REVISION_ID_revision_id_MASK)
57440 /*! @} */
57441 
57442 /*! @name PRODUCT_ID0 - Product Identification Register 0 */
57443 /*! @{ */
57444 
57445 #define IDENTIFICATION_PRODUCT_ID0_product_id0_MASK (0xFFU)
57446 #define IDENTIFICATION_PRODUCT_ID0_product_id0_SHIFT (0U)
57447 /*! product_id0 - This one byte fixed code Identifies Synopsys's product line ("A0h" for DWC_hdmi_tx products). */
57448 #define IDENTIFICATION_PRODUCT_ID0_product_id0(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID0_product_id0_SHIFT)) & IDENTIFICATION_PRODUCT_ID0_product_id0_MASK)
57449 /*! @} */
57450 
57451 /*! @name PRODUCT_ID1 - Product Identification Register 1 */
57452 /*! @{ */
57453 
57454 #define IDENTIFICATION_PRODUCT_ID1_product_id1_tx_MASK (0x1U)
57455 #define IDENTIFICATION_PRODUCT_ID1_product_id1_tx_SHIFT (0U)
57456 /*! product_id1_tx - This bit Identifies Synopsys's DWC_hdmi_tx Controller according to Synopsys product line. */
57457 #define IDENTIFICATION_PRODUCT_ID1_product_id1_tx(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID1_product_id1_tx_SHIFT)) & IDENTIFICATION_PRODUCT_ID1_product_id1_tx_MASK)
57458 
57459 #define IDENTIFICATION_PRODUCT_ID1_product_id1_rx_MASK (0x2U)
57460 #define IDENTIFICATION_PRODUCT_ID1_product_id1_rx_SHIFT (1U)
57461 /*! product_id1_rx - This bit Identifies Synopsys's DWC_hdmi_rx Controller according to Synopsys product line. */
57462 #define IDENTIFICATION_PRODUCT_ID1_product_id1_rx(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID1_product_id1_rx_SHIFT)) & IDENTIFICATION_PRODUCT_ID1_product_id1_rx_MASK)
57463 
57464 #define IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_MASK (0xC0U)
57465 #define IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_SHIFT (6U)
57466 /*! product_id1_hdcp - These bits identify a Synopsys's HDMI Controller with HDCP encryption according to Synopsys product line. */
57467 #define IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_SHIFT)) & IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_MASK)
57468 /*! @} */
57469 
57470 /*! @name CONFIG0_ID - Configuration Identification Register 0 */
57471 /*! @{ */
57472 
57473 #define IDENTIFICATION_CONFIG0_ID_hdcp_MASK      (0x1U)
57474 #define IDENTIFICATION_CONFIG0_ID_hdcp_SHIFT     (0U)
57475 /*! hdcp - Indicates if HDCP is present */
57476 #define IDENTIFICATION_CONFIG0_ID_hdcp(x)        (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_hdcp_SHIFT)) & IDENTIFICATION_CONFIG0_ID_hdcp_MASK)
57477 
57478 #define IDENTIFICATION_CONFIG0_ID_cec_MASK       (0x2U)
57479 #define IDENTIFICATION_CONFIG0_ID_cec_SHIFT      (1U)
57480 /*! cec - Indicates if CEC is present */
57481 #define IDENTIFICATION_CONFIG0_ID_cec(x)         (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_cec_SHIFT)) & IDENTIFICATION_CONFIG0_ID_cec_MASK)
57482 
57483 #define IDENTIFICATION_CONFIG0_ID_csc_MASK       (0x4U)
57484 #define IDENTIFICATION_CONFIG0_ID_csc_SHIFT      (2U)
57485 /*! csc - Indicates if Color Space Conversion block is present */
57486 #define IDENTIFICATION_CONFIG0_ID_csc(x)         (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_csc_SHIFT)) & IDENTIFICATION_CONFIG0_ID_csc_MASK)
57487 
57488 #define IDENTIFICATION_CONFIG0_ID_hdmi14_MASK    (0x8U)
57489 #define IDENTIFICATION_CONFIG0_ID_hdmi14_SHIFT   (3U)
57490 /*! hdmi14 - Indicates if HDMI 1. */
57491 #define IDENTIFICATION_CONFIG0_ID_hdmi14(x)      (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_hdmi14_SHIFT)) & IDENTIFICATION_CONFIG0_ID_hdmi14_MASK)
57492 
57493 #define IDENTIFICATION_CONFIG0_ID_audi2s_MASK    (0x10U)
57494 #define IDENTIFICATION_CONFIG0_ID_audi2s_SHIFT   (4U)
57495 /*! audi2s - Indicates if I2S interface is present */
57496 #define IDENTIFICATION_CONFIG0_ID_audi2s(x)      (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_audi2s_SHIFT)) & IDENTIFICATION_CONFIG0_ID_audi2s_MASK)
57497 
57498 #define IDENTIFICATION_CONFIG0_ID_audspdif_MASK  (0x20U)
57499 #define IDENTIFICATION_CONFIG0_ID_audspdif_SHIFT (5U)
57500 /*! audspdif - Indicates if the SPDIF audio interface is present */
57501 #define IDENTIFICATION_CONFIG0_ID_audspdif(x)    (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_audspdif_SHIFT)) & IDENTIFICATION_CONFIG0_ID_audspdif_MASK)
57502 
57503 #define IDENTIFICATION_CONFIG0_ID_prepen_MASK    (0x80U)
57504 #define IDENTIFICATION_CONFIG0_ID_prepen_SHIFT   (7U)
57505 /*! prepen - Indicates if it is possible to use internal pixel repetition */
57506 #define IDENTIFICATION_CONFIG0_ID_prepen(x)      (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_prepen_SHIFT)) & IDENTIFICATION_CONFIG0_ID_prepen_MASK)
57507 /*! @} */
57508 
57509 /*! @name CONFIG1_ID - Configuration Identification Register 1 */
57510 /*! @{ */
57511 
57512 #define IDENTIFICATION_CONFIG1_ID_confapb_MASK   (0x2U)
57513 #define IDENTIFICATION_CONFIG1_ID_confapb_SHIFT  (1U)
57514 /*! confapb - Indicates that configuration interface is APB interface */
57515 #define IDENTIFICATION_CONFIG1_ID_confapb(x)     (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG1_ID_confapb_SHIFT)) & IDENTIFICATION_CONFIG1_ID_confapb_MASK)
57516 
57517 #define IDENTIFICATION_CONFIG1_ID_hdmi20_MASK    (0x20U)
57518 #define IDENTIFICATION_CONFIG1_ID_hdmi20_SHIFT   (5U)
57519 /*! hdmi20 - Indicates if HDMI 2. */
57520 #define IDENTIFICATION_CONFIG1_ID_hdmi20(x)      (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG1_ID_hdmi20_SHIFT)) & IDENTIFICATION_CONFIG1_ID_hdmi20_MASK)
57521 
57522 #define IDENTIFICATION_CONFIG1_ID_hdcp22_ext_MASK (0x40U)
57523 #define IDENTIFICATION_CONFIG1_ID_hdcp22_ext_SHIFT (6U)
57524 /*! hdcp22_ext - Indicates if external HDCP 2. */
57525 #define IDENTIFICATION_CONFIG1_ID_hdcp22_ext(x)  (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG1_ID_hdcp22_ext_SHIFT)) & IDENTIFICATION_CONFIG1_ID_hdcp22_ext_MASK)
57526 /*! @} */
57527 
57528 /*! @name CONFIG2_ID - Configuration Identification Register 2 */
57529 /*! @{ */
57530 
57531 #define IDENTIFICATION_CONFIG2_ID_phytype_MASK   (0xFFU)
57532 #define IDENTIFICATION_CONFIG2_ID_phytype_SHIFT  (0U)
57533 /*! phytype - Indicates the type of PHY interface selected: 0x00: Legacy PHY (HDMI TX PHY) 0xF2: PHY
57534  *    GEN2 (HDMI 3D TX PHY) 0xE2: PHY GEN2 (HDMI 3D TX PHY) + HEAC PHY 0xC2: PHY MHL COMBO
57535  *    (MHL+HDMI 2.
57536  */
57537 #define IDENTIFICATION_CONFIG2_ID_phytype(x)     (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG2_ID_phytype_SHIFT)) & IDENTIFICATION_CONFIG2_ID_phytype_MASK)
57538 /*! @} */
57539 
57540 /*! @name CONFIG3_ID - Configuration Identification Register 3 */
57541 /*! @{ */
57542 
57543 #define IDENTIFICATION_CONFIG3_ID_confgpaud_MASK (0x1U)
57544 #define IDENTIFICATION_CONFIG3_ID_confgpaud_SHIFT (0U)
57545 /*! confgpaud - Indicates that the audio interface is Generic Parallel Audio (GPAUD) */
57546 #define IDENTIFICATION_CONFIG3_ID_confgpaud(x)   (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG3_ID_confgpaud_SHIFT)) & IDENTIFICATION_CONFIG3_ID_confgpaud_MASK)
57547 
57548 #define IDENTIFICATION_CONFIG3_ID_confahbauddma_MASK (0x2U)
57549 #define IDENTIFICATION_CONFIG3_ID_confahbauddma_SHIFT (1U)
57550 /*! confahbauddma - Indicates that the audio interface is AHB AUD DMA */
57551 #define IDENTIFICATION_CONFIG3_ID_confahbauddma(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG3_ID_confahbauddma_SHIFT)) & IDENTIFICATION_CONFIG3_ID_confahbauddma_MASK)
57552 /*! @} */
57553 
57554 
57555 /*!
57556  * @}
57557  */ /* end of group IDENTIFICATION_Register_Masks */
57558 
57559 
57560 /* IDENTIFICATION - Peripheral instance base addresses */
57561 /** Peripheral IDENTIFICATION base address */
57562 #define IDENTIFICATION_BASE                      (0x32FD8000u)
57563 /** Peripheral IDENTIFICATION base pointer */
57564 #define IDENTIFICATION                           ((IDENTIFICATION_Type *)IDENTIFICATION_BASE)
57565 /** Array initializer of IDENTIFICATION peripheral base addresses */
57566 #define IDENTIFICATION_BASE_ADDRS                { IDENTIFICATION_BASE }
57567 /** Array initializer of IDENTIFICATION peripheral base pointers */
57568 #define IDENTIFICATION_BASE_PTRS                 { IDENTIFICATION }
57569 
57570 /*!
57571  * @}
57572  */ /* end of group IDENTIFICATION_Peripheral_Access_Layer */
57573 
57574 
57575 /* ----------------------------------------------------------------------------
57576    -- INTERRUPT Peripheral Access Layer
57577    ---------------------------------------------------------------------------- */
57578 
57579 /*!
57580  * @addtogroup INTERRUPT_Peripheral_Access_Layer INTERRUPT Peripheral Access Layer
57581  * @{
57582  */
57583 
57584 /** INTERRUPT - Register Layout Typedef */
57585 typedef struct {
57586   __IO uint8_t IH_FC_STAT0;                        /**< Frame Composer Interrupt Status Register 0 (Packet Interrupts), offset: 0x0 */
57587   __IO uint8_t IH_FC_STAT1;                        /**< Frame Composer Interrupt Status Register 1 (Packet Interrupts), offset: 0x1 */
57588   __IO uint8_t IH_FC_STAT2;                        /**< Frame Composer Interrupt Status Register 2 (Packet Interrupts), offset: 0x2 */
57589   __IO uint8_t IH_AS_STAT0;                        /**< Audio Sampler Interrupt Status Register (FIFO Threshold, Underflow and Overflow Interrupts), offset: 0x3 */
57590   __IO uint8_t IH_PHY_STAT0;                       /**< PHY Interface Interrupt Status Register (RXSENSE, PLL Lock and HPD Interrupts), offset: 0x4 */
57591   __IO uint8_t IH_I2CM_STAT0;                      /**< E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts), offset: 0x5 */
57592   __IO uint8_t IH_CEC_STAT0;                       /**< CEC Interrupt Status Register (Functional Operation Interrupts), offset: 0x6 */
57593   __IO uint8_t IH_VP_STAT0;                        /**< Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts), offset: 0x7 */
57594   __IO uint8_t IH_I2CMPHY_STAT0;                   /**< PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts), offset: 0x8 */
57595        uint8_t RESERVED_0[103];
57596   __I  uint8_t IH_DECODE;                          /**< Interruption Handler Decode Assist Register, offset: 0x70 */
57597        uint8_t RESERVED_1[15];
57598   __IO uint8_t IH_MUTE_FC_STAT0;                   /**< Frame Composer Interrupt Mute Control Register 0, offset: 0x80 */
57599   __IO uint8_t IH_MUTE_FC_STAT1;                   /**< Frame Composer Interrupt Mute Control Register 1, offset: 0x81 */
57600   __IO uint8_t IH_MUTE_FC_STAT2;                   /**< Frame Composer Interrupt Mute Control Register 2, offset: 0x82 */
57601   __IO uint8_t IH_MUTE_AS_STAT0;                   /**< Audio Sampler Interrupt Mute Control Register, offset: 0x83 */
57602   __IO uint8_t IH_MUTE_PHY_STAT0;                  /**< PHY Interface Interrupt Mute Control Register, offset: 0x84 */
57603   __IO uint8_t IH_MUTE_I2CM_STAT0;                 /**< E-DDC I2C Master Interrupt Mute Control Register, offset: 0x85 */
57604   __IO uint8_t IH_MUTE_CEC_STAT0;                  /**< CEC Interrupt Mute Control Register, offset: 0x86 */
57605   __IO uint8_t IH_MUTE_VP_STAT0;                   /**< Video Packetizer Interrupt Mute Control Register, offset: 0x87 */
57606   __IO uint8_t IH_MUTE_I2CMPHY_STAT0;              /**< PHY GEN2 I2C Master Interrupt Mute Control Register, offset: 0x88 */
57607        uint8_t RESERVED_2[118];
57608   __IO uint8_t IH_MUTE;                            /**< Global Interrupt Mute Control Register, offset: 0xFF */
57609 } INTERRUPT_Type;
57610 
57611 /* ----------------------------------------------------------------------------
57612    -- INTERRUPT Register Masks
57613    ---------------------------------------------------------------------------- */
57614 
57615 /*!
57616  * @addtogroup INTERRUPT_Register_Masks INTERRUPT Register Masks
57617  * @{
57618  */
57619 
57620 /*! @name IH_FC_STAT0 - Frame Composer Interrupt Status Register 0 (Packet Interrupts) */
57621 /*! @{ */
57622 
57623 #define INTERRUPT_IH_FC_STAT0_NULL_MASK          (0x1U)
57624 #define INTERRUPT_IH_FC_STAT0_NULL_SHIFT         (0U)
57625 /*! NULL - Active after successful transmission of an Null packet. */
57626 #define INTERRUPT_IH_FC_STAT0_NULL(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_NULL_SHIFT)) & INTERRUPT_IH_FC_STAT0_NULL_MASK)
57627 
57628 #define INTERRUPT_IH_FC_STAT0_ACR_MASK           (0x2U)
57629 #define INTERRUPT_IH_FC_STAT0_ACR_SHIFT          (1U)
57630 /*! ACR - Active after successful transmission of an Audio Clock Regeneration (N/CTS transmission) packet. */
57631 #define INTERRUPT_IH_FC_STAT0_ACR(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_ACR_SHIFT)) & INTERRUPT_IH_FC_STAT0_ACR_MASK)
57632 
57633 #define INTERRUPT_IH_FC_STAT0_AUDS_MASK          (0x4U)
57634 #define INTERRUPT_IH_FC_STAT0_AUDS_SHIFT         (2U)
57635 /*! AUDS - Active after successful transmission of an Audio Sample packet. */
57636 #define INTERRUPT_IH_FC_STAT0_AUDS(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_AUDS_SHIFT)) & INTERRUPT_IH_FC_STAT0_AUDS_MASK)
57637 
57638 #define INTERRUPT_IH_FC_STAT0_NVBI_MASK          (0x8U)
57639 #define INTERRUPT_IH_FC_STAT0_NVBI_SHIFT         (3U)
57640 /*! NVBI - Active after successful transmission of an NTSC VBI packet */
57641 #define INTERRUPT_IH_FC_STAT0_NVBI(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_NVBI_SHIFT)) & INTERRUPT_IH_FC_STAT0_NVBI_MASK)
57642 
57643 #define INTERRUPT_IH_FC_STAT0_MAS_MASK           (0x10U)
57644 #define INTERRUPT_IH_FC_STAT0_MAS_SHIFT          (4U)
57645 /*! MAS - Active after successful transmission of an MultiStream Audio packet */
57646 #define INTERRUPT_IH_FC_STAT0_MAS(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_MAS_SHIFT)) & INTERRUPT_IH_FC_STAT0_MAS_MASK)
57647 
57648 #define INTERRUPT_IH_FC_STAT0_HBR_MASK           (0x20U)
57649 #define INTERRUPT_IH_FC_STAT0_HBR_SHIFT          (5U)
57650 /*! HBR - Active after successful transmission of an Audio HBR packet. */
57651 #define INTERRUPT_IH_FC_STAT0_HBR(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_HBR_SHIFT)) & INTERRUPT_IH_FC_STAT0_HBR_MASK)
57652 
57653 #define INTERRUPT_IH_FC_STAT0_ACP_MASK           (0x40U)
57654 #define INTERRUPT_IH_FC_STAT0_ACP_SHIFT          (6U)
57655 /*! ACP - Active after successful transmission of an Audio Content Protection packet. */
57656 #define INTERRUPT_IH_FC_STAT0_ACP(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_ACP_SHIFT)) & INTERRUPT_IH_FC_STAT0_ACP_MASK)
57657 
57658 #define INTERRUPT_IH_FC_STAT0_AUDI_MASK          (0x80U)
57659 #define INTERRUPT_IH_FC_STAT0_AUDI_SHIFT         (7U)
57660 /*! AUDI - Active after successful transmission of an Audio InfoFrame packet. */
57661 #define INTERRUPT_IH_FC_STAT0_AUDI(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_AUDI_SHIFT)) & INTERRUPT_IH_FC_STAT0_AUDI_MASK)
57662 /*! @} */
57663 
57664 /*! @name IH_FC_STAT1 - Frame Composer Interrupt Status Register 1 (Packet Interrupts) */
57665 /*! @{ */
57666 
57667 #define INTERRUPT_IH_FC_STAT1_GCP_MASK           (0x1U)
57668 #define INTERRUPT_IH_FC_STAT1_GCP_SHIFT          (0U)
57669 /*! GCP - Active after successful transmission of an General Control Packet. */
57670 #define INTERRUPT_IH_FC_STAT1_GCP(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_GCP_SHIFT)) & INTERRUPT_IH_FC_STAT1_GCP_MASK)
57671 
57672 #define INTERRUPT_IH_FC_STAT1_AVI_MASK           (0x2U)
57673 #define INTERRUPT_IH_FC_STAT1_AVI_SHIFT          (1U)
57674 /*! AVI - Active after successful transmission of an AVI InfoFrame packet. */
57675 #define INTERRUPT_IH_FC_STAT1_AVI(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_AVI_SHIFT)) & INTERRUPT_IH_FC_STAT1_AVI_MASK)
57676 
57677 #define INTERRUPT_IH_FC_STAT1_AMP_MASK           (0x4U)
57678 #define INTERRUPT_IH_FC_STAT1_AMP_SHIFT          (2U)
57679 /*! AMP - Active after successful transmission of an Audio Metadata packet */
57680 #define INTERRUPT_IH_FC_STAT1_AMP(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_AMP_SHIFT)) & INTERRUPT_IH_FC_STAT1_AMP_MASK)
57681 
57682 #define INTERRUPT_IH_FC_STAT1_SPD_MASK           (0x8U)
57683 #define INTERRUPT_IH_FC_STAT1_SPD_SHIFT          (3U)
57684 /*! SPD - Active after successful transmission of an Source Product Descriptor InfoFrame packet. */
57685 #define INTERRUPT_IH_FC_STAT1_SPD(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_SPD_SHIFT)) & INTERRUPT_IH_FC_STAT1_SPD_MASK)
57686 
57687 #define INTERRUPT_IH_FC_STAT1_VSD_MASK           (0x10U)
57688 #define INTERRUPT_IH_FC_STAT1_VSD_SHIFT          (4U)
57689 /*! VSD - Active after successful transmission of an Vendor Specific Data InfoFrame packet. */
57690 #define INTERRUPT_IH_FC_STAT1_VSD(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_VSD_SHIFT)) & INTERRUPT_IH_FC_STAT1_VSD_MASK)
57691 
57692 #define INTERRUPT_IH_FC_STAT1_ISCR2_MASK         (0x20U)
57693 #define INTERRUPT_IH_FC_STAT1_ISCR2_SHIFT        (5U)
57694 /*! ISCR2 - Active after successful transmission of an International Standard Recording Code 2 packet */
57695 #define INTERRUPT_IH_FC_STAT1_ISCR2(x)           (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_ISCR2_SHIFT)) & INTERRUPT_IH_FC_STAT1_ISCR2_MASK)
57696 
57697 #define INTERRUPT_IH_FC_STAT1_ISCR1_MASK         (0x40U)
57698 #define INTERRUPT_IH_FC_STAT1_ISCR1_SHIFT        (6U)
57699 /*! ISCR1 - Active after successful transmission of an International Standard Recording Code 1 packet. */
57700 #define INTERRUPT_IH_FC_STAT1_ISCR1(x)           (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_ISCR1_SHIFT)) & INTERRUPT_IH_FC_STAT1_ISCR1_MASK)
57701 
57702 #define INTERRUPT_IH_FC_STAT1_GMD_MASK           (0x80U)
57703 #define INTERRUPT_IH_FC_STAT1_GMD_SHIFT          (7U)
57704 /*! GMD - Active after successful transmission of an Gamut metadata packet. */
57705 #define INTERRUPT_IH_FC_STAT1_GMD(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_GMD_SHIFT)) & INTERRUPT_IH_FC_STAT1_GMD_MASK)
57706 /*! @} */
57707 
57708 /*! @name IH_FC_STAT2 - Frame Composer Interrupt Status Register 2 (Packet Interrupts) */
57709 /*! @{ */
57710 
57711 #define INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK (0x1U)
57712 #define INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT (0U)
57713 /*! HighPriority_overflow - Frame Composer high priority packet queue descriptor overflow indication */
57714 #define INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK)
57715 
57716 #define INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK (0x2U)
57717 #define INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT (1U)
57718 /*! LowPriority_overflow - Frame Composer low priority packet queue descriptor overflow indication */
57719 #define INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK)
57720 
57721 #define INTERRUPT_IH_FC_STAT2_DRM_MASK           (0x10U)
57722 #define INTERRUPT_IH_FC_STAT2_DRM_SHIFT          (4U)
57723 /*! DRM - Active after successful transmission of an DRM packet */
57724 #define INTERRUPT_IH_FC_STAT2_DRM(x)             (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT2_DRM_SHIFT)) & INTERRUPT_IH_FC_STAT2_DRM_MASK)
57725 /*! @} */
57726 
57727 /*! @name IH_AS_STAT0 - Audio Sampler Interrupt Status Register (FIFO Threshold, Underflow and Overflow Interrupts) */
57728 /*! @{ */
57729 
57730 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_MASK (0x1U)
57731 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT (0U)
57732 /*! Aud_fifo_overflow - Audio Sampler audio FIFO full indication. */
57733 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT)) & INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_MASK)
57734 
57735 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK (0x2U)
57736 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT (1U)
57737 /*! Aud_fifo_underflow - Audio Sampler audio FIFO empty indication. */
57738 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT)) & INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK)
57739 
57740 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK (0x4U)
57741 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT (2U)
57742 /*! Aud_fifo_underflow_thr - Audio Sampler audio FIFO empty threshold (four samples) indication for the legacy HBR audio interface. */
57743 #define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT)) & INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK)
57744 
57745 #define INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_MASK  (0x8U)
57746 #define INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_SHIFT (3U)
57747 /*! fifo_overrun - Indicates an overrun on the audio FIFO. */
57748 #define INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN(x)    (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_SHIFT)) & INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_MASK)
57749 /*! @} */
57750 
57751 /*! @name IH_PHY_STAT0 - PHY Interface Interrupt Status Register (RXSENSE, PLL Lock and HPD Interrupts) */
57752 /*! @{ */
57753 
57754 #define INTERRUPT_IH_PHY_STAT0_HPD_MASK          (0x1U)
57755 #define INTERRUPT_IH_PHY_STAT0_HPD_SHIFT         (0U)
57756 /*! HPD - HDMI Hot Plug Detect indication. */
57757 #define INTERRUPT_IH_PHY_STAT0_HPD(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_HPD_SHIFT)) & INTERRUPT_IH_PHY_STAT0_HPD_MASK)
57758 
57759 #define INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_MASK  (0x2U)
57760 #define INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_SHIFT (1U)
57761 /*! TX_PHY_LOCK - TX PHY PLL lock indication. */
57762 #define INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK(x)    (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_SHIFT)) & INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_MASK)
57763 
57764 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_MASK   (0x4U)
57765 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_SHIFT  (2U)
57766 /*! RX_SENSE_0 - TX PHY RX_SENSE indication for driver 0. */
57767 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_0(x)     (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_MASK)
57768 
57769 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_MASK   (0x8U)
57770 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_SHIFT  (3U)
57771 /*! RX_SENSE_1 - TX PHY RX_SENSE indication for driver 1. */
57772 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_1(x)     (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_MASK)
57773 
57774 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_MASK   (0x10U)
57775 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_SHIFT  (4U)
57776 /*! RX_SENSE_2 - TX PHY RX_SENSE indication for driver 2. */
57777 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_2(x)     (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_MASK)
57778 
57779 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_MASK   (0x20U)
57780 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_SHIFT  (5U)
57781 /*! RX_SENSE_3 - TX PHY RX_SENSE indication for driver 3. */
57782 #define INTERRUPT_IH_PHY_STAT0_RX_SENSE_3(x)     (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_MASK)
57783 /*! @} */
57784 
57785 /*! @name IH_I2CM_STAT0 - E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts) */
57786 /*! @{ */
57787 
57788 #define INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_MASK (0x1U)
57789 #define INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_SHIFT (0U)
57790 /*! I2Cmastererror - I2C Master error indication */
57791 #define INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_SHIFT)) & INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_MASK)
57792 
57793 #define INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_MASK (0x2U)
57794 #define INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_SHIFT (1U)
57795 /*! I2Cmasterdone - I2C Master done indication */
57796 #define INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_SHIFT)) & INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_MASK)
57797 
57798 #define INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_MASK (0x4U)
57799 #define INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_SHIFT (2U)
57800 /*! scdc_readreq - I2C Master SCDC read request indication. */
57801 #define INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ(x)  (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_SHIFT)) & INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_MASK)
57802 /*! @} */
57803 
57804 /*! @name IH_CEC_STAT0 - CEC Interrupt Status Register (Functional Operation Interrupts) */
57805 /*! @{ */
57806 
57807 #define INTERRUPT_IH_CEC_STAT0_DONE_MASK         (0x1U)
57808 #define INTERRUPT_IH_CEC_STAT0_DONE_SHIFT        (0U)
57809 /*! DONE - CEC Done Indication */
57810 #define INTERRUPT_IH_CEC_STAT0_DONE(x)           (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_DONE_SHIFT)) & INTERRUPT_IH_CEC_STAT0_DONE_MASK)
57811 
57812 #define INTERRUPT_IH_CEC_STAT0_EOM_MASK          (0x2U)
57813 #define INTERRUPT_IH_CEC_STAT0_EOM_SHIFT         (1U)
57814 /*! EOM - CEC End of Message Indication */
57815 #define INTERRUPT_IH_CEC_STAT0_EOM(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_EOM_SHIFT)) & INTERRUPT_IH_CEC_STAT0_EOM_MASK)
57816 
57817 #define INTERRUPT_IH_CEC_STAT0_NACK_MASK         (0x4U)
57818 #define INTERRUPT_IH_CEC_STAT0_NACK_SHIFT        (2U)
57819 /*! NACK - CEC Not Acknowledge indication */
57820 #define INTERRUPT_IH_CEC_STAT0_NACK(x)           (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_NACK_SHIFT)) & INTERRUPT_IH_CEC_STAT0_NACK_MASK)
57821 
57822 #define INTERRUPT_IH_CEC_STAT0_ARB_LOST_MASK     (0x8U)
57823 #define INTERRUPT_IH_CEC_STAT0_ARB_LOST_SHIFT    (3U)
57824 /*! ARB_LOST - CEC Arbitration Lost indication */
57825 #define INTERRUPT_IH_CEC_STAT0_ARB_LOST(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_ARB_LOST_SHIFT)) & INTERRUPT_IH_CEC_STAT0_ARB_LOST_MASK)
57826 
57827 #define INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_MASK (0x10U)
57828 #define INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_SHIFT (4U)
57829 /*! ERROR_INITIATOR - CEC Error Initiator indication */
57830 #define INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_SHIFT)) & INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_MASK)
57831 
57832 #define INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_MASK (0x20U)
57833 #define INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_SHIFT (5U)
57834 /*! ERROR_FOLLOW - CEC Error Follow indication */
57835 #define INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW(x)   (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_SHIFT)) & INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_MASK)
57836 
57837 #define INTERRUPT_IH_CEC_STAT0_WAKEUP_MASK       (0x40U)
57838 #define INTERRUPT_IH_CEC_STAT0_WAKEUP_SHIFT      (6U)
57839 /*! WAKEUP - CEC Wake-up indication */
57840 #define INTERRUPT_IH_CEC_STAT0_WAKEUP(x)         (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_WAKEUP_SHIFT)) & INTERRUPT_IH_CEC_STAT0_WAKEUP_MASK)
57841 /*! @} */
57842 
57843 /*! @name IH_VP_STAT0 - Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts) */
57844 /*! @{ */
57845 
57846 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_MASK (0x4U)
57847 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_SHIFT (2U)
57848 /*! fifoemptyremap - Video Packetizer pixel YCbCr 422 re-mapper FIFO empty interrupt */
57849 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP(x)  (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_MASK)
57850 
57851 #define INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_MASK (0x8U)
57852 #define INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_SHIFT (3U)
57853 /*! fifofullremap - Video Packetizer pixel YCbCr 422 re-mapper FIFO full interrupt */
57854 #define INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP(x)   (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_MASK)
57855 
57856 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_MASK   (0x10U)
57857 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_SHIFT  (4U)
57858 /*! fifoemptypp - Video Packetizer pixel packing FIFO empty interrupt */
57859 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP(x)     (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_MASK)
57860 
57861 #define INTERRUPT_IH_VP_STAT0_FIFOFULLPP_MASK    (0x20U)
57862 #define INTERRUPT_IH_VP_STAT0_FIFOFULLPP_SHIFT   (5U)
57863 /*! fifofullpp - Video Packetizer pixel packing FIFO full interrupt */
57864 #define INTERRUPT_IH_VP_STAT0_FIFOFULLPP(x)      (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOFULLPP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOFULLPP_MASK)
57865 
57866 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_MASK (0x40U)
57867 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_SHIFT (6U)
57868 /*! fifoemptyrepet - Video Packetizer pixel repeater FIFO empty interrupt */
57869 #define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET(x)  (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_MASK)
57870 
57871 #define INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_MASK (0x80U)
57872 #define INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_SHIFT (7U)
57873 /*! fifofullrepet - Video Packetizer pixel repeater FIFO full interrupt */
57874 #define INTERRUPT_IH_VP_STAT0_FIFOFULLREPET(x)   (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_MASK)
57875 /*! @} */
57876 
57877 /*! @name IH_I2CMPHY_STAT0 - PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts) */
57878 /*! @{ */
57879 
57880 #define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_MASK (0x1U)
57881 #define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT (0U)
57882 /*! I2Cmphyerror - I2C Master PHY error indication */
57883 #define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT)) & INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_MASK)
57884 
57885 #define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_MASK (0x2U)
57886 #define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT (1U)
57887 /*! I2Cmphydone - I2C Master PHY done indication */
57888 #define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT)) & INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_MASK)
57889 /*! @} */
57890 
57891 /*! @name IH_DECODE - Interruption Handler Decode Assist Register */
57892 /*! @{ */
57893 
57894 #define INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_MASK (0x1U)
57895 #define INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_SHIFT (0U)
57896 /*! ih_ahbdmaaud_stat0 - Interruption active at the ih_ahbdmaaud_stat0 register */
57897 #define INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_MASK)
57898 
57899 #define INTERRUPT_IH_DECODE_IH_CEC_STAT0_MASK    (0x2U)
57900 #define INTERRUPT_IH_DECODE_IH_CEC_STAT0_SHIFT   (1U)
57901 /*! ih_cec_stat0 - Interruption active at the ih_cec_stat0 register */
57902 #define INTERRUPT_IH_DECODE_IH_CEC_STAT0(x)      (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_CEC_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_CEC_STAT0_MASK)
57903 
57904 #define INTERRUPT_IH_DECODE_IH_I2CM_STAT0_MASK   (0x4U)
57905 #define INTERRUPT_IH_DECODE_IH_I2CM_STAT0_SHIFT  (2U)
57906 /*! ih_i2cm_stat0 - Interruption active at the ih_i2cm_stat0 register */
57907 #define INTERRUPT_IH_DECODE_IH_I2CM_STAT0(x)     (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_I2CM_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_I2CM_STAT0_MASK)
57908 
57909 #define INTERRUPT_IH_DECODE_IH_PHY_MASK          (0x8U)
57910 #define INTERRUPT_IH_DECODE_IH_PHY_SHIFT         (3U)
57911 /*! ih_phy - Interruption active at the ih_phy_stat0 or ih_i2cmphy_stat0 register */
57912 #define INTERRUPT_IH_DECODE_IH_PHY(x)            (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_PHY_SHIFT)) & INTERRUPT_IH_DECODE_IH_PHY_MASK)
57913 
57914 #define INTERRUPT_IH_DECODE_IH_AS_STAT0_MASK     (0x10U)
57915 #define INTERRUPT_IH_DECODE_IH_AS_STAT0_SHIFT    (4U)
57916 /*! ih_as_stat0 - Interruption active at the ih_as_stat0 register */
57917 #define INTERRUPT_IH_DECODE_IH_AS_STAT0(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_AS_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_AS_STAT0_MASK)
57918 
57919 #define INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_MASK  (0x20U)
57920 #define INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_SHIFT (5U)
57921 /*! ih_fc_stat2_vp - Interruption active at the ih_fc_stat2 or ih_vp_stat0 register */
57922 #define INTERRUPT_IH_DECODE_IH_FC_STAT2_VP(x)    (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_SHIFT)) & INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_MASK)
57923 
57924 #define INTERRUPT_IH_DECODE_IH_FC_STAT1_MASK     (0x40U)
57925 #define INTERRUPT_IH_DECODE_IH_FC_STAT1_SHIFT    (6U)
57926 /*! ih_fc_stat1 - Interruption active at the ih_fc_stat1 register */
57927 #define INTERRUPT_IH_DECODE_IH_FC_STAT1(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_FC_STAT1_SHIFT)) & INTERRUPT_IH_DECODE_IH_FC_STAT1_MASK)
57928 
57929 #define INTERRUPT_IH_DECODE_IH_FC_STAT0_MASK     (0x80U)
57930 #define INTERRUPT_IH_DECODE_IH_FC_STAT0_SHIFT    (7U)
57931 /*! ih_fc_stat0 - Interruption active at the ih_fc_stat0 register */
57932 #define INTERRUPT_IH_DECODE_IH_FC_STAT0(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_FC_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_FC_STAT0_MASK)
57933 /*! @} */
57934 
57935 /*! @name IH_MUTE_FC_STAT0 - Frame Composer Interrupt Mute Control Register 0 */
57936 /*! @{ */
57937 
57938 #define INTERRUPT_IH_MUTE_FC_STAT0_NULL_MASK     (0x1U)
57939 #define INTERRUPT_IH_MUTE_FC_STAT0_NULL_SHIFT    (0U)
57940 /*! NULL - When set to 1, mutes ih_fc_stat0[0] */
57941 #define INTERRUPT_IH_MUTE_FC_STAT0_NULL(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_NULL_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_NULL_MASK)
57942 
57943 #define INTERRUPT_IH_MUTE_FC_STAT0_ACR_MASK      (0x2U)
57944 #define INTERRUPT_IH_MUTE_FC_STAT0_ACR_SHIFT     (1U)
57945 /*! ACR - When set to 1, mutes ih_fc_stat0[1] */
57946 #define INTERRUPT_IH_MUTE_FC_STAT0_ACR(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_ACR_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_ACR_MASK)
57947 
57948 #define INTERRUPT_IH_MUTE_FC_STAT0_AUDS_MASK     (0x4U)
57949 #define INTERRUPT_IH_MUTE_FC_STAT0_AUDS_SHIFT    (2U)
57950 /*! AUDS - When set to 1, mutes ih_fc_stat0[2] */
57951 #define INTERRUPT_IH_MUTE_FC_STAT0_AUDS(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_AUDS_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_AUDS_MASK)
57952 
57953 #define INTERRUPT_IH_MUTE_FC_STAT0_NVBI_MASK     (0x8U)
57954 #define INTERRUPT_IH_MUTE_FC_STAT0_NVBI_SHIFT    (3U)
57955 /*! NVBI - When set to 1, mutes ih_fc_stat0[3]. */
57956 #define INTERRUPT_IH_MUTE_FC_STAT0_NVBI(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_NVBI_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_NVBI_MASK)
57957 
57958 #define INTERRUPT_IH_MUTE_FC_STAT0_MAS_MASK      (0x10U)
57959 #define INTERRUPT_IH_MUTE_FC_STAT0_MAS_SHIFT     (4U)
57960 /*! MAS - When set to 1, mutes ih_fc_stat0[4]. */
57961 #define INTERRUPT_IH_MUTE_FC_STAT0_MAS(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_MAS_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_MAS_MASK)
57962 
57963 #define INTERRUPT_IH_MUTE_FC_STAT0_HBR_MASK      (0x20U)
57964 #define INTERRUPT_IH_MUTE_FC_STAT0_HBR_SHIFT     (5U)
57965 /*! HBR - When set to 1, mutes ih_fc_stat0[5] */
57966 #define INTERRUPT_IH_MUTE_FC_STAT0_HBR(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_HBR_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_HBR_MASK)
57967 
57968 #define INTERRUPT_IH_MUTE_FC_STAT0_ACP_MASK      (0x40U)
57969 #define INTERRUPT_IH_MUTE_FC_STAT0_ACP_SHIFT     (6U)
57970 /*! ACP - When set to 1, mutes ih_fc_stat0[6] */
57971 #define INTERRUPT_IH_MUTE_FC_STAT0_ACP(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_ACP_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_ACP_MASK)
57972 
57973 #define INTERRUPT_IH_MUTE_FC_STAT0_AUDI_MASK     (0x80U)
57974 #define INTERRUPT_IH_MUTE_FC_STAT0_AUDI_SHIFT    (7U)
57975 /*! AUDI - When set to 1, mutes ih_fc_stat0[7] */
57976 #define INTERRUPT_IH_MUTE_FC_STAT0_AUDI(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_AUDI_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_AUDI_MASK)
57977 /*! @} */
57978 
57979 /*! @name IH_MUTE_FC_STAT1 - Frame Composer Interrupt Mute Control Register 1 */
57980 /*! @{ */
57981 
57982 #define INTERRUPT_IH_MUTE_FC_STAT1_GCP_MASK      (0x1U)
57983 #define INTERRUPT_IH_MUTE_FC_STAT1_GCP_SHIFT     (0U)
57984 /*! GCP - When set to 1, mutes ih_fc_stat1[0] */
57985 #define INTERRUPT_IH_MUTE_FC_STAT1_GCP(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_GCP_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_GCP_MASK)
57986 
57987 #define INTERRUPT_IH_MUTE_FC_STAT1_AVI_MASK      (0x2U)
57988 #define INTERRUPT_IH_MUTE_FC_STAT1_AVI_SHIFT     (1U)
57989 /*! AVI - When set to 1, mutes ih_fc_stat1[1] */
57990 #define INTERRUPT_IH_MUTE_FC_STAT1_AVI(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_AVI_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_AVI_MASK)
57991 
57992 #define INTERRUPT_IH_MUTE_FC_STAT1_AMP_MASK      (0x4U)
57993 #define INTERRUPT_IH_MUTE_FC_STAT1_AMP_SHIFT     (2U)
57994 /*! AMP - When set to 1, mutes ih_fc_stat1[2]. */
57995 #define INTERRUPT_IH_MUTE_FC_STAT1_AMP(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_AMP_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_AMP_MASK)
57996 
57997 #define INTERRUPT_IH_MUTE_FC_STAT1_SPD_MASK      (0x8U)
57998 #define INTERRUPT_IH_MUTE_FC_STAT1_SPD_SHIFT     (3U)
57999 /*! SPD - When set to 1, mutes ih_fc_stat1[3] */
58000 #define INTERRUPT_IH_MUTE_FC_STAT1_SPD(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_SPD_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_SPD_MASK)
58001 
58002 #define INTERRUPT_IH_MUTE_FC_STAT1_VSD_MASK      (0x10U)
58003 #define INTERRUPT_IH_MUTE_FC_STAT1_VSD_SHIFT     (4U)
58004 /*! VSD - When set to 1, mutes ih_fc_stat1[4] */
58005 #define INTERRUPT_IH_MUTE_FC_STAT1_VSD(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_VSD_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_VSD_MASK)
58006 
58007 #define INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_MASK    (0x20U)
58008 #define INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_SHIFT   (5U)
58009 /*! ISCR2 - When set to 1, mutes ih_fc_stat1[5] */
58010 #define INTERRUPT_IH_MUTE_FC_STAT1_ISCR2(x)      (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_MASK)
58011 
58012 #define INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_MASK    (0x40U)
58013 #define INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_SHIFT   (6U)
58014 /*! ISCR1 - When set to 1, mutes ih_fc_stat1[6] */
58015 #define INTERRUPT_IH_MUTE_FC_STAT1_ISCR1(x)      (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_MASK)
58016 
58017 #define INTERRUPT_IH_MUTE_FC_STAT1_GMD_MASK      (0x80U)
58018 #define INTERRUPT_IH_MUTE_FC_STAT1_GMD_SHIFT     (7U)
58019 /*! GMD - When set to 1, mutes ih_fc_stat1[7] */
58020 #define INTERRUPT_IH_MUTE_FC_STAT1_GMD(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_GMD_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_GMD_MASK)
58021 /*! @} */
58022 
58023 /*! @name IH_MUTE_FC_STAT2 - Frame Composer Interrupt Mute Control Register 2 */
58024 /*! @{ */
58025 
58026 #define INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK (0x1U)
58027 #define INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT (0U)
58028 /*! HighPriority_overflow - When set to 1, mutes ih_fc_stat2[0] */
58029 #define INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK)
58030 
58031 #define INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK (0x2U)
58032 #define INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT (1U)
58033 /*! LowPriority_overflow - When set to 1, mutes ih_fc_stat2[1] */
58034 #define INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK)
58035 
58036 #define INTERRUPT_IH_MUTE_FC_STAT2_DRM_MASK      (0x10U)
58037 #define INTERRUPT_IH_MUTE_FC_STAT2_DRM_SHIFT     (4U)
58038 /*! DRM - When set to 1, mutes ih_fc_stat2[4]. */
58039 #define INTERRUPT_IH_MUTE_FC_STAT2_DRM(x)        (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT2_DRM_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT2_DRM_MASK)
58040 /*! @} */
58041 
58042 /*! @name IH_MUTE_AS_STAT0 - Audio Sampler Interrupt Mute Control Register */
58043 /*! @{ */
58044 
58045 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_MASK (0x1U)
58046 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT (0U)
58047 /*! Aud_fifo_overflow - When set to 1, mutes ih_as_stat0[0] */
58048 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_MASK)
58049 
58050 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK (0x2U)
58051 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT (1U)
58052 /*! Aud_fifo_underflow - When set to 1, mutes ih_as_stat0[1] */
58053 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK)
58054 
58055 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK (0x4U)
58056 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT (2U)
58057 /*! Aud_fifo_underflow_thr - When set to 1, mutes ih_as_stat0[2] */
58058 #define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK)
58059 
58060 #define INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_MASK (0x8U)
58061 #define INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_SHIFT (3U)
58062 /*! fifo_overrun - When set to 1, mutes ih_as_stat0[3] */
58063 #define INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_MASK)
58064 /*! @} */
58065 
58066 /*! @name IH_MUTE_PHY_STAT0 - PHY Interface Interrupt Mute Control Register */
58067 /*! @{ */
58068 
58069 #define INTERRUPT_IH_MUTE_PHY_STAT0_HPD_MASK     (0x1U)
58070 #define INTERRUPT_IH_MUTE_PHY_STAT0_HPD_SHIFT    (0U)
58071 /*! HPD - When set to 1, mutes ih_phy_stat0[0] */
58072 #define INTERRUPT_IH_MUTE_PHY_STAT0_HPD(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_HPD_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_HPD_MASK)
58073 
58074 #define INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_MASK (0x2U)
58075 #define INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_SHIFT (1U)
58076 /*! TX_PHY_LOCK - When set to 1, mutes ih_phy_stat0[1] */
58077 #define INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_MASK)
58078 
58079 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_MASK (0x4U)
58080 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_SHIFT (2U)
58081 /*! RX_SENSE_0 - When set to 1, mutes ih_phy_stat0[2] */
58082 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_MASK)
58083 
58084 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_MASK (0x8U)
58085 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_SHIFT (3U)
58086 /*! RX_SENSE_1 - When set to 1, mutes ih_phy_stat0[3] */
58087 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_MASK)
58088 
58089 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_MASK (0x10U)
58090 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_SHIFT (4U)
58091 /*! RX_SENSE_2 - When set to 1, mutes ih_phy_stat0[4] */
58092 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_MASK)
58093 
58094 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_MASK (0x20U)
58095 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_SHIFT (5U)
58096 /*! RX_SENSE_3 - When set to 1, mutes ih_phy_stat0[5] */
58097 #define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_MASK)
58098 /*! @} */
58099 
58100 /*! @name IH_MUTE_I2CM_STAT0 - E-DDC I2C Master Interrupt Mute Control Register */
58101 /*! @{ */
58102 
58103 #define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_MASK (0x1U)
58104 #define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_SHIFT (0U)
58105 /*! I2Cmastererror - When set to 1, mutes ih_i2cm_stat0[0] */
58106 #define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_SHIFT)) & INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_MASK)
58107 
58108 #define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_MASK (0x2U)
58109 #define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_SHIFT (1U)
58110 /*! I2Cmasterdone - When set to 1, mutes ih_i2cm_stat0[1] */
58111 #define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_SHIFT)) & INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_MASK)
58112 
58113 #define INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_MASK (0x4U)
58114 #define INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_SHIFT (2U)
58115 /*! scdc_readreq - When set to 1, mutes ih_i2cm_stat0[2] */
58116 #define INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_SHIFT)) & INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_MASK)
58117 /*! @} */
58118 
58119 /*! @name IH_MUTE_CEC_STAT0 - CEC Interrupt Mute Control Register */
58120 /*! @{ */
58121 
58122 #define INTERRUPT_IH_MUTE_CEC_STAT0_DONE_MASK    (0x1U)
58123 #define INTERRUPT_IH_MUTE_CEC_STAT0_DONE_SHIFT   (0U)
58124 /*! DONE - When set to 1, mutes ih_cec_stat0[0] */
58125 #define INTERRUPT_IH_MUTE_CEC_STAT0_DONE(x)      (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_DONE_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_DONE_MASK)
58126 
58127 #define INTERRUPT_IH_MUTE_CEC_STAT0_EOM_MASK     (0x2U)
58128 #define INTERRUPT_IH_MUTE_CEC_STAT0_EOM_SHIFT    (1U)
58129 /*! EOM - When set to 1, mutes ih_cec_stat0[1] */
58130 #define INTERRUPT_IH_MUTE_CEC_STAT0_EOM(x)       (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_EOM_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_EOM_MASK)
58131 
58132 #define INTERRUPT_IH_MUTE_CEC_STAT0_NACK_MASK    (0x4U)
58133 #define INTERRUPT_IH_MUTE_CEC_STAT0_NACK_SHIFT   (2U)
58134 /*! NACK - When set to 1, mutes ih_cec_stat0[2] */
58135 #define INTERRUPT_IH_MUTE_CEC_STAT0_NACK(x)      (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_NACK_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_NACK_MASK)
58136 
58137 #define INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_MASK (0x8U)
58138 #define INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_SHIFT (3U)
58139 /*! ARB_LOST - When set to 1, mutes ih_cec_stat0[3] */
58140 #define INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST(x)  (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_MASK)
58141 
58142 #define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_MASK (0x10U)
58143 #define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_SHIFT (4U)
58144 /*! ERROR_INITIATOR - When set to 1, mutes ih_cec_stat0[4] */
58145 #define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_MASK)
58146 
58147 #define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_MASK (0x20U)
58148 #define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_SHIFT (5U)
58149 /*! ERROR_FOLLOW - When set to 1, mutes ih_cec_stat0[5] */
58150 #define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_MASK)
58151 
58152 #define INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_MASK  (0x40U)
58153 #define INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_SHIFT (6U)
58154 /*! WAKEUP - When set to 1, mutes ih_cec_stat0[6] */
58155 #define INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP(x)    (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_MASK)
58156 /*! @} */
58157 
58158 /*! @name IH_MUTE_VP_STAT0 - Video Packetizer Interrupt Mute Control Register */
58159 /*! @{ */
58160 
58161 #define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_MASK  (0x1U)
58162 #define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_SHIFT (0U)
58163 /*! spare_1 - Reserved as "spare" bit with no associated functionality. */
58164 #define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1(x)    (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_MASK)
58165 
58166 #define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_MASK  (0x2U)
58167 #define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_SHIFT (1U)
58168 /*! spare_2 - Reserved as "spare" bit with no associated functionality. */
58169 #define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2(x)    (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_MASK)
58170 
58171 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_MASK (0x4U)
58172 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_SHIFT (2U)
58173 /*! fifoemptyremap - When set to 1, mutes ih_vp_stat0[2] */
58174 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_MASK)
58175 
58176 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_MASK (0x8U)
58177 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_SHIFT (3U)
58178 /*! fifofullremap - When set to 1, mutes ih_vp_stat0[3] */
58179 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_MASK)
58180 
58181 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_MASK (0x10U)
58182 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_SHIFT (4U)
58183 /*! fifoemptypp - When set to 1, mutes ih_vp_stat0[4] */
58184 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_MASK)
58185 
58186 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_MASK (0x20U)
58187 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_SHIFT (5U)
58188 /*! fifofullpp - When set to 1, mutes ih_vp_stat0[5] */
58189 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_MASK)
58190 
58191 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_MASK (0x40U)
58192 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_SHIFT (6U)
58193 /*! fifoemptyrepet - When set to 1, mutes ih_vp_stat0[6] */
58194 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_MASK)
58195 
58196 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_MASK (0x80U)
58197 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_SHIFT (7U)
58198 /*! fifofullrepet - When set to 1, mutes ih_vp_stat0[7] */
58199 #define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_MASK)
58200 /*! @} */
58201 
58202 /*! @name IH_MUTE_I2CMPHY_STAT0 - PHY GEN2 I2C Master Interrupt Mute Control Register */
58203 /*! @{ */
58204 
58205 #define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_MASK (0x1U)
58206 #define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT (0U)
58207 /*! I2Cmphyerror - When set to 1, mutes ih_i2cmphy_stat0[0] */
58208 #define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT)) & INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_MASK)
58209 
58210 #define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_MASK (0x2U)
58211 #define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT (1U)
58212 /*! I2Cmphydone - When set to 1, mutes ih_i2cmphy_stat0[1] */
58213 #define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT)) & INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_MASK)
58214 /*! @} */
58215 
58216 /*! @name IH_MUTE - Global Interrupt Mute Control Register */
58217 /*! @{ */
58218 
58219 #define INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_MASK (0x1U)
58220 #define INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_SHIFT (0U)
58221 /*! mute_all_interrupt - When set to 1, mutes the main interrupt line (where all interrupts are ORed). */
58222 #define INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT(x)  (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_SHIFT)) & INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_MASK)
58223 
58224 #define INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_MASK (0x2U)
58225 #define INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_SHIFT (1U)
58226 /*! mute_wakeup_interrupt - When set to 1, mutes the main interrupt output port. */
58227 #define INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_SHIFT)) & INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_MASK)
58228 /*! @} */
58229 
58230 
58231 /*!
58232  * @}
58233  */ /* end of group INTERRUPT_Register_Masks */
58234 
58235 
58236 /* INTERRUPT - Peripheral instance base addresses */
58237 /** Peripheral INTERRUPT base address */
58238 #define INTERRUPT_BASE                           (0x32FD8100u)
58239 /** Peripheral INTERRUPT base pointer */
58240 #define INTERRUPT                                ((INTERRUPT_Type *)INTERRUPT_BASE)
58241 /** Array initializer of INTERRUPT peripheral base addresses */
58242 #define INTERRUPT_BASE_ADDRS                     { INTERRUPT_BASE }
58243 /** Array initializer of INTERRUPT peripheral base pointers */
58244 #define INTERRUPT_BASE_PTRS                      { INTERRUPT }
58245 
58246 /*!
58247  * @}
58248  */ /* end of group INTERRUPT_Peripheral_Access_Layer */
58249 
58250 
58251 /* ----------------------------------------------------------------------------
58252    -- IOMUXC Peripheral Access Layer
58253    ---------------------------------------------------------------------------- */
58254 
58255 /*!
58256  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
58257  * @{
58258  */
58259 
58260 /** IOMUXC - Register Layout Typedef */
58261 typedef struct {
58262        uint8_t RESERVED_0[20];
58263   __IO uint32_t SW_MUX_CTL_PAD[143];               /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control Register, array offset: 0x14, array step: 0x4 */
58264   __IO uint32_t SW_PAD_CTL_PAD[156];               /**< SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register..SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register, array offset: 0x250, array step: 0x4 */
58265   __IO uint32_t SELECT_INPUT[94];                  /**< AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register..USDHC3_WP_ON_SELECT_INPUT DAISY Register, array offset: 0x4C0, array step: 0x4 */
58266 } IOMUXC_Type;
58267 
58268 /* ----------------------------------------------------------------------------
58269    -- IOMUXC Register Masks
58270    ---------------------------------------------------------------------------- */
58271 
58272 /*!
58273  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
58274  * @{
58275  */
58276 
58277 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control Register */
58278 /*! @{ */
58279 
58280 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0x7U)
58281 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
58282 /*! MUX_MODE - MUX Mode Select Field.
58283  *  0b000..Select mux mode: ALT0 mux port: AUDIOMIX_SAI2_RX_DATA00 of instance: sai2
58284  *  0b001..Select mux mode: ALT1 mux port: AUDIOMIX_SAI5_TX_DATA00 of instance: sai5
58285  *  0b010..Select mux mode: ALT2 mux port: ENET_QOS_1588_EVENT2_OUT of instance: enet_qos
58286  *  0b011..Select mux mode: ALT3 mux port: AUDIOMIX_SAI2_TX_DATA01 of instance: sai2
58287  *  0b100..Select mux mode: ALT4 mux port: UART1_RTS_B of instance: uart1
58288  *  0b101..Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4
58289  *  0b110..Select mux mode: ALT6 mux port: AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
58290  */
58291 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
58292 
58293 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
58294 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
58295 /*! SION - Software Input On Field.
58296  *  0b1..Force input path of pad SPDIF_EXT_CLK
58297  *  0b0..Input Path is determined by functionality
58298  */
58299 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
58300 /*! @} */
58301 
58302 /* The count of IOMUXC_SW_MUX_CTL_PAD */
58303 #define IOMUXC_SW_MUX_CTL_PAD_COUNT              (143U)
58304 
58305 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register..SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register */
58306 /*! @{ */
58307 
58308 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x6U)
58309 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (1U)
58310 /*! DSE - Drive Strength Field
58311  *  0b00..X1
58312  *  0b10..X2
58313  *  0b01..X4
58314  *  0b11..X6
58315  */
58316 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
58317 
58318 #define IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK          (0x10U)
58319 #define IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT         (4U)
58320 /*! FSEL - Slew Rate Field
58321  *  0b0..Slow Slew Rate (SR=1)
58322  *  0b1..Fast Slew Rate (SR=0)
58323  */
58324 #define IOMUXC_SW_PAD_CTL_PAD_FSEL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK)
58325 
58326 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x20U)
58327 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (5U)
58328 /*! ODE - Open Drain Field
58329  *  0b0..Open Drain Disable
58330  *  0b1..Open Drain Enable
58331  */
58332 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
58333 
58334 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x40U)
58335 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (6U)
58336 /*! PUE - Pull Up / Down Config. Field
58337  *  0b0..Weak pull down
58338  *  0b1..Weak pull up
58339  */
58340 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
58341 
58342 #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK           (0x80U)
58343 #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT          (7U)
58344 /*! HYS - Input Select Field
58345  *  0b0..CMOS
58346  *  0b1..Schmitt
58347  */
58348 #define IOMUXC_SW_PAD_CTL_PAD_HYS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
58349 
58350 #define IOMUXC_SW_PAD_CTL_PAD_PE_MASK            (0x100U)
58351 #define IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT           (8U)
58352 /*! PE - Pull Select Field
58353  *  0b0..Pull Disable
58354  *  0b1..Pull Enable
58355  */
58356 #define IOMUXC_SW_PAD_CTL_PAD_PE(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PE_MASK)
58357 /*! @} */
58358 
58359 /* The count of IOMUXC_SW_PAD_CTL_PAD */
58360 #define IOMUXC_SW_PAD_CTL_PAD_COUNT              (156U)
58361 
58362 /*! @name SELECT_INPUT - AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register..USDHC3_WP_ON_SELECT_INPUT DAISY Register */
58363 /*! @{ */
58364 
58365 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0xFU)  /* Merged from fields with different position or width, of widths (1, 2, 3, 4), largest definition used */
58366 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
58367 /*! DAISY - Selecting Pads Involved in Daisy Chain.
58368  *  0b0000..Selecting Pad: SD2_CLK for Mode: ALT3
58369  *  0b0001..Selecting Pad: SD2_CMD for Mode: ALT3
58370  *  0b0010..Selecting Pad: NAND_CLE for Mode: ALT4
58371  *  0b0011..Selecting Pad: NAND_DATA00 for Mode: ALT4
58372  *  0b0100..Selecting Pad: NAND_DATA01 for Mode: ALT4
58373  *  0b0101..Selecting Pad: NAND_RE_B for Mode: ALT4
58374  *  0b0110..Selecting Pad: ECSPI2_SCLK for Mode: ALT1
58375  *  0b0111..Selecting Pad: ECSPI2_MOSI for Mode: ALT1
58376  *  0b1000..Selecting Pad: UART4_RXD for Mode: ALT0
58377  *  0b1001..Selecting Pad: UART4_TXD for Mode: ALT0
58378  */
58379 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2, 3, 4), largest definition used */
58380 /*! @} */
58381 
58382 /* The count of IOMUXC_SELECT_INPUT */
58383 #define IOMUXC_SELECT_INPUT_COUNT                (94U)
58384 
58385 
58386 /*!
58387  * @}
58388  */ /* end of group IOMUXC_Register_Masks */
58389 
58390 
58391 /* IOMUXC - Peripheral instance base addresses */
58392 /** Peripheral IOMUXC base address */
58393 #define IOMUXC_BASE                              (0x30330000u)
58394 /** Peripheral IOMUXC base pointer */
58395 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
58396 /** Array initializer of IOMUXC peripheral base addresses */
58397 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
58398 /** Array initializer of IOMUXC peripheral base pointers */
58399 #define IOMUXC_BASE_PTRS                         { IOMUXC }
58400 
58401 /*!
58402  * @}
58403  */ /* end of group IOMUXC_Peripheral_Access_Layer */
58404 
58405 
58406 /* ----------------------------------------------------------------------------
58407    -- IOMUXC_GPR Peripheral Access Layer
58408    ---------------------------------------------------------------------------- */
58409 
58410 /*!
58411  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
58412  * @{
58413  */
58414 
58415 /** IOMUXC_GPR - Register Layout Typedef */
58416 typedef struct {
58417        uint32_t GPR0;                              /**< General Purpose Register 0, offset: 0x0 */
58418   __IO uint32_t GPR1;                              /**< General Purpose Register 1, offset: 0x4 */
58419   __IO uint32_t GPR2;                              /**< General Purpose Register 2, offset: 0x8 */
58420        uint32_t GPR3;                              /**< General Purpose Register 3, offset: 0xC */
58421   __IO uint32_t GPR4;                              /**< General Purpose Register 4, offset: 0x10 */
58422   __IO uint32_t GPR5;                              /**< General Purpose Register 5, offset: 0x14 */
58423   __IO uint32_t GPR6;                              /**< General Purpose Register 6, offset: 0x18 */
58424        uint32_t GPR7;                              /**< General Purpose Register 7, offset: 0x1C */
58425        uint32_t GPR8;                              /**< General Purpose Register 8, offset: 0x20 */
58426        uint32_t GPR9;                              /**< General Purpose Register 9, offset: 0x24 */
58427   __IO uint32_t GPR10;                             /**< General Purpose Register 10, offset: 0x28 */
58428   __IO uint32_t GPR11;                             /**< General Purpose Register 11, offset: 0x2C */
58429   __IO uint32_t GPR12;                             /**< General Purpose Register 12, offset: 0x30 */
58430   __IO uint32_t GPR13;                             /**< General Purpose Register 13, offset: 0x34 */
58431   __IO uint32_t GPR14;                             /**< General Purpose Register 14, offset: 0x38 */
58432   __IO uint32_t GPR15;                             /**< General Purpose Register 15, offset: 0x3C */
58433   __IO uint32_t GPR16;                             /**< General Purpose Register 16, offset: 0x40 */
58434        uint32_t GPR17;                             /**< General Purpose Register 17, offset: 0x44 */
58435        uint32_t GPR18;                             /**< General Purpose Register 18, offset: 0x48 */
58436   __I  uint32_t GPR19;                             /**< General Purpose Register 19, offset: 0x4C */
58437   __IO uint32_t GPR20;                             /**< General Purpose Register 20, offset: 0x50 */
58438   __IO uint32_t GPR21;                             /**< General Purpose Register 21, offset: 0x54 */
58439   __IO uint32_t GPR22;                             /**< General Purpose Register 22, offset: 0x58 */
58440        uint32_t GPR23;                             /**< General Purpose Register 23, offset: 0x5C */
58441   __I  uint32_t GPR24;                             /**< General Purpose Register 24, offset: 0x60 */
58442 } IOMUXC_GPR_Type;
58443 
58444 /* ----------------------------------------------------------------------------
58445    -- IOMUXC_GPR Register Masks
58446    ---------------------------------------------------------------------------- */
58447 
58448 /*!
58449  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
58450  * @{
58451  */
58452 
58453 /*! @name GPR1 - General Purpose Register 1 */
58454 /*! @{ */
58455 
58456 #define IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_MASK (0x1U)
58457 #define IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_SHIFT (0U)
58458 /*! GPR_ENET1_EVENT0IN_SEL
58459  *  0b0..IOMUX
58460  *  0b1..GPT1 CMPOUT2
58461  */
58462 #define IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_MASK)
58463 
58464 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_MASK (0x2U)
58465 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_SHIFT (1U)
58466 /*! GPR_ENET_QOS_EVENT0IN_SEL
58467  *  0b0..IOMUX;
58468  *  0b1..GPT1 CMPOUT2
58469  */
58470 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_MASK)
58471 
58472 #define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_MASK (0x4U)
58473 #define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_SHIFT (2U)
58474 /*! GPR_GPT1_CAPIN1_SEL
58475  *  0b0..IOMUX
58476  *  0b1..ENET1 TIMIER1 EVENT
58477  */
58478 #define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_MASK)
58479 
58480 #define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_MASK (0x8U)
58481 #define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_SHIFT (3U)
58482 /*! GPR_GPT1_CAPIN2_SEL
58483  *  0b0..IOMUX
58484  *  0b1..ENET QOS TIMIER1 EVENT
58485  */
58486 #define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_MASK)
58487 
58488 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_MASK (0x10U)
58489 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_SHIFT (4U)
58490 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_MASK)
58491 
58492 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_MASK (0x20U)
58493 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_SHIFT (5U)
58494 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_MASK)
58495 
58496 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_MASK (0x40U)
58497 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_SHIFT (6U)
58498 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_MASK)
58499 
58500 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_MASK (0x80U)
58501 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_SHIFT (7U)
58502 #define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_MASK)
58503 
58504 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK             (0x1000U)
58505 #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT            (12U)
58506 #define IOMUXC_GPR_GPR1_GPR_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR1_GPR_IRQ_MASK)
58507 
58508 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U)
58509 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_SHIFT (13U)
58510 /*! IOMUXC_GPR_ENET1_TX_CLK_SEL
58511  *  0b1..ENET1 RMII clock comes from ccm->pad->loopback
58512  *  0b0..ENET1 RMII clock comes from external PHY or OSC
58513  */
58514 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_MASK)
58515 
58516 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_MASK (0x4000U)
58517 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_SHIFT (14U)
58518 /*! GPR_ENET_QOS_DIS_CRC_CHK
58519  *  0b0..do not disable
58520  *  0b1..disable
58521  */
58522 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_MASK)
58523 
58524 #define IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_MASK (0x8000U)
58525 #define IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_SHIFT (15U)
58526 /*! GPR_ANAMIX_IPT_MODE
58527  *  0b0..masked to 0
58528  *  0b1..unmasked
58529  */
58530 #define IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_MASK)
58531 
58532 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK (0x70000U)
58533 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_SHIFT (16U)
58534 /*! GPR_ENET_QOS_INTF_SEL
58535  *  0b000..MII
58536  *  0b001..RGMII
58537  *  0b100..RMII
58538  */
58539 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK)
58540 
58541 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_MASK (0x80000U)
58542 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_SHIFT (19U)
58543 /*! GPR_ENET_QOS_CLK_GEN_EN
58544  *  0b0..disable
58545  *  0b1..enable
58546  */
58547 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_MASK)
58548 
58549 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_MASK (0x100000U)
58550 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_SHIFT (20U)
58551 /*! IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL
58552  *  0b1..ENET QOS RMII clock comes from ccm->pad->loopback
58553  *  0b0..ENET QOS RMII clock comes from external PHY or OSC
58554  */
58555 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_MASK)
58556 
58557 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_MASK (0x200000U)
58558 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_SHIFT (21U)
58559 /*! IOMUXC_GPR_ENET_QOS_RGMII_EN
58560  *  0b0..MII(input)
58561  *  0b1..RGMII(output)
58562  */
58563 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_MASK)
58564 
58565 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_MASK (0x400000U)
58566 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_SHIFT (22U)
58567 /*! IOMUXC_GPR_ENET1_RGMII_EN
58568  *  0b0..MII(input)
58569  *  0b1..RGMII(output)
58570  */
58571 #define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_MASK)
58572 
58573 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U)
58574 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U)
58575 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK)
58576 
58577 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_MASK (0x8000000U)
58578 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_SHIFT (27U)
58579 /*! GPR_DBG_ACK_M7_MASK
58580  *  0b0..unmasked
58581  *  0b1..mask to 0
58582  */
58583 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_MASK)
58584 
58585 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_MASK (0xF0000000U)
58586 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_SHIFT (28U)
58587 /*! GPR_DBG_ACK_A53_MASK
58588  *  0b0000..unmasked
58589  *  0b0001..mask to 0
58590  */
58591 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_MASK)
58592 /*! @} */
58593 
58594 /*! @name GPR2 - General Purpose Register 2 */
58595 /*! @{ */
58596 
58597 #define IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_MASK (0x3U)
58598 #define IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_SHIFT (0U)
58599 #define IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_SHIFT)) & IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_MASK)
58600 /*! @} */
58601 
58602 /*! @name GPR4 - General Purpose Register 4 */
58603 /*! @{ */
58604 
58605 #define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK  (0x1U)
58606 #define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT (0U)
58607 #define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK)
58608 
58609 #define IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_MASK (0x2U)
58610 #define IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_SHIFT (1U)
58611 #define IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_MASK)
58612 
58613 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK  (0x8U)
58614 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT (3U)
58615 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK)
58616 
58617 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK   (0x10U)
58618 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT  (4U)
58619 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK)
58620 
58621 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK   (0x20U)
58622 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT  (5U)
58623 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK)
58624 
58625 #define IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_MASK (0x10000U)
58626 #define IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_SHIFT (16U)
58627 #define IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_MASK)
58628 
58629 #define IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_MASK (0x20000U)
58630 #define IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_SHIFT (17U)
58631 #define IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_MASK)
58632 
58633 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_MASK (0x80000U)
58634 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_SHIFT (19U)
58635 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_MASK)
58636 
58637 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_MASK (0x100000U)
58638 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_SHIFT (20U)
58639 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_MASK)
58640 
58641 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_MASK (0x200000U)
58642 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_SHIFT (21U)
58643 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_MASK)
58644 
58645 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK      (0xF000000U)
58646 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT     (24U)
58647 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFI(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK)
58648 
58649 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK      (0xF0000000U)
58650 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT     (28U)
58651 #define IOMUXC_GPR_GPR4_CPU_STANDBYWFE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK)
58652 /*! @} */
58653 
58654 /*! @name GPR5 - General Purpose Register 5 */
58655 /*! @{ */
58656 
58657 #define IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_MASK (0x1U)
58658 #define IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_SHIFT (0U)
58659 #define IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_MASK)
58660 
58661 #define IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_MASK (0x2U)
58662 #define IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_SHIFT (1U)
58663 #define IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_MASK)
58664 
58665 #define IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_MASK  (0x4U)
58666 #define IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_SHIFT (2U)
58667 #define IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_SHIFT)) & IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_MASK)
58668 
58669 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK      (0x40U)
58670 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT     (6U)
58671 /*! GPR_WDOG1_MASK
58672  *  0b0..wdog1 low will make the GPIO1_IO02.alt5_out low;
58673  *  0b1..wdog1 low will NOT impact the GPIO1_IO02.alt5_out
58674  */
58675 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK)
58676 
58677 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK      (0x80U)
58678 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT     (7U)
58679 /*! GPR_WDOG2_MASK
58680  *  0b0..wdog2 low will make the GPIO1_IO02.alt5_out low;
58681  *  0b1..wdog2 low will NOT impact the GPIO1_IO02.alt5_out
58682  */
58683 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK)
58684 
58685 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK      (0x100000U)
58686 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT     (20U)
58687 /*! GPR_WDOG3_MASK
58688  *  0b0..wdog3 low will make the GPIO1_IO02.alt5_out low;
58689  *  0b1..wdog3 low will NOT impact the GPIO1_IO02.alt5_out
58690  */
58691 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK)
58692 /*! @} */
58693 
58694 /*! @name GPR6 - General Purpose Register 6 */
58695 /*! @{ */
58696 
58697 #define IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_MASK     (0xFFFFFF80U)
58698 #define IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_SHIFT    (7U)
58699 #define IOMUXC_GPR_GPR6_GPR_M7_INITVTOR(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_SHIFT)) & IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_MASK)
58700 /*! @} */
58701 
58702 /*! @name GPR10 - General Purpose Register 10 */
58703 /*! @{ */
58704 
58705 #define IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK       (0x1U)
58706 #define IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT      (0U)
58707 #define IOMUXC_GPR_GPR10_GPR_TZASC_EN(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK)
58708 
58709 #define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U)
58710 #define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U)
58711 #define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK)
58712 
58713 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK (0x4U)
58714 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT (2U)
58715 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK)
58716 
58717 #define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK (0x8U)
58718 #define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT (3U)
58719 #define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK)
58720 
58721 #define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_MASK  (0x10U)
58722 #define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_SHIFT (4U)
58723 #define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_MASK)
58724 
58725 #define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_MASK (0x7E0U)
58726 #define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_SHIFT (5U)
58727 #define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_MASK)
58728 
58729 #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK  (0x10000U)
58730 #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT (16U)
58731 #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK)
58732 
58733 #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x20000U)
58734 #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (17U)
58735 #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK)
58736 
58737 #define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK (0x40000U)
58738 #define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT (18U)
58739 #define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK)
58740 
58741 #define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK (0x80000U)
58742 #define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT (19U)
58743 #define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK)
58744 /*! @} */
58745 
58746 /*! @name GPR11 - General Purpose Register 11 */
58747 /*! @{ */
58748 
58749 #define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_MASK    (0x1U)
58750 #define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_SHIFT   (0U)
58751 #define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_MASK)
58752 
58753 #define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_MASK (0x1FEU)
58754 #define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_SHIFT (1U)
58755 #define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_MASK)
58756 
58757 #define IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_MASK (0x200U)
58758 #define IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT (9U)
58759 /*! GPR_CAAM_CAAM_IPS_MANAGER
58760  *  0b0..not controlled by CSU/RDC slot
58761  *  0b1..controlled by CSU/RDC slot
58762  */
58763 #define IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT)) & IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_MASK)
58764 
58765 #define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_MASK  (0x400U)
58766 #define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_SHIFT (10U)
58767 #define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_MASK)
58768 
58769 #define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_MASK (0x7800U)
58770 #define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_SHIFT (11U)
58771 #define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_MASK)
58772 
58773 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_MASK (0x10000U)
58774 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_SHIFT (16U)
58775 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_MASK)
58776 
58777 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_MASK (0x1FE0000U)
58778 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_SHIFT (17U)
58779 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_MASK)
58780 
58781 #define IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_MASK (0x2000000U)
58782 #define IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT (25U)
58783 #define IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_MASK)
58784 
58785 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_MASK (0x4000000U)
58786 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_SHIFT (26U)
58787 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_MASK)
58788 
58789 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_MASK (0x38000000U)
58790 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_SHIFT (27U)
58791 #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_MASK)
58792 /*! @} */
58793 
58794 /*! @name GPR12 - General Purpose Register 12 */
58795 /*! @{ */
58796 
58797 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK (0xF000U)
58798 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT (12U)
58799 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK)
58800 
58801 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E0000U)
58802 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (17U)
58803 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
58804 
58805 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK (0x600000U)
58806 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT (21U)
58807 #define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK)
58808 
58809 #define IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_MASK (0x80000000U)
58810 #define IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_SHIFT (31U)
58811 #define IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_MASK)
58812 /*! @} */
58813 
58814 /*! @name GPR13 - General Purpose Register 13 */
58815 /*! @{ */
58816 
58817 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK  (0x1U)
58818 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT (0U)
58819 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK)
58820 
58821 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK  (0x2U)
58822 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT (1U)
58823 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK)
58824 
58825 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK   (0x10U)
58826 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT  (4U)
58827 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK)
58828 
58829 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK   (0x20U)
58830 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT  (5U)
58831 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK)
58832 
58833 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_MASK   (0x80U)
58834 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_SHIFT  (7U)
58835 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_MASK)
58836 
58837 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_MASK   (0x100U)
58838 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_SHIFT  (8U)
58839 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_MASK)
58840 
58841 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK (0x400U)
58842 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT (10U)
58843 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK)
58844 
58845 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK (0x800U)
58846 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT (11U)
58847 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK)
58848 
58849 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_MASK   (0x2000U)
58850 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_SHIFT  (13U)
58851 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_MASK)
58852 
58853 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_MASK   (0x4000U)
58854 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_SHIFT  (14U)
58855 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_MASK)
58856 /*! @} */
58857 
58858 /*! @name GPR14 - General Purpose Register 14 */
58859 /*! @{ */
58860 
58861 #define IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_MASK (0x100U)
58862 #define IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_SHIFT (8U)
58863 #define IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_MASK)
58864 
58865 #define IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_MASK (0x200U)
58866 #define IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_SHIFT (9U)
58867 #define IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_MASK)
58868 
58869 #define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_MASK (0x400U)
58870 #define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_SHIFT (10U)
58871 #define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_MASK)
58872 
58873 #define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_MASK (0x800U)
58874 #define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_SHIFT (11U)
58875 #define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_MASK)
58876 
58877 #define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_MASK (0xF0000U)
58878 #define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_SHIFT (16U)
58879 #define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_MASK)
58880 
58881 #define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_MASK (0x3000000U)
58882 #define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_SHIFT (24U)
58883 /*! GPR_PCIE_PHY_PLL_REF_CLK_SEL
58884  *  0b00..N/A
58885  *  0b01..Selects reference clock from XO (pll_refclk_from_xo)
58886  *  0b10..Selects reference clock from IO (ext_ref_clkp/n)
58887  *  0b11..Selects reference clock from SOC PLL (pll_refclk_from_syspll)
58888  */
58889 #define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_MASK)
58890 /*! @} */
58891 
58892 /*! @name GPR15 - General Purpose Register 15 */
58893 /*! @{ */
58894 
58895 #define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_MASK (0xFFFFU)
58896 #define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_SHIFT (0U)
58897 #define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_SHIFT)) & IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_MASK)
58898 
58899 #define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_MASK (0xFFFF0000U)
58900 #define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_SHIFT (16U)
58901 #define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_SHIFT)) & IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_MASK)
58902 /*! @} */
58903 
58904 /*! @name GPR16 - General Purpose Register 16 */
58905 /*! @{ */
58906 
58907 #define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_MASK (0x1U)
58908 #define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_SHIFT (0U)
58909 #define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_SHIFT)) & IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_MASK)
58910 
58911 #define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_MASK (0x2U)
58912 #define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_SHIFT (1U)
58913 #define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_SHIFT)) & IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_MASK)
58914 /*! @} */
58915 
58916 /*! @name GPR19 - General Purpose Register 19 */
58917 /*! @{ */
58918 
58919 #define IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_MASK   (0xFFFFFFFFU)
58920 #define IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_SHIFT  (0U)
58921 #define IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_SHIFT)) & IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_MASK)
58922 /*! @} */
58923 
58924 /*! @name GPR20 - General Purpose Register 20 */
58925 /*! @{ */
58926 
58927 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_MASK (0x1U)
58928 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_SHIFT (0U)
58929 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_MASK)
58930 
58931 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_MASK (0x2U)
58932 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_SHIFT (1U)
58933 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_MASK)
58934 
58935 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_MASK (0x4U)
58936 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_SHIFT (2U)
58937 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_MASK)
58938 
58939 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_MASK (0x8U)
58940 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_SHIFT (3U)
58941 #define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_MASK)
58942 
58943 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_MASK (0x10U)
58944 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_SHIFT (4U)
58945 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_MASK)
58946 
58947 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_MASK (0x20U)
58948 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_SHIFT (5U)
58949 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_MASK)
58950 
58951 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_MASK (0x40U)
58952 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_SHIFT (6U)
58953 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_MASK)
58954 
58955 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_MASK (0x80U)
58956 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_SHIFT (7U)
58957 #define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_MASK)
58958 
58959 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_MASK (0x100U)
58960 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_SHIFT (8U)
58961 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_MASK)
58962 
58963 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_MASK (0x200U)
58964 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_SHIFT (9U)
58965 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_MASK)
58966 
58967 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_MASK (0x400U)
58968 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_SHIFT (10U)
58969 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_MASK)
58970 
58971 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_MASK (0x800U)
58972 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_SHIFT (11U)
58973 #define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_MASK)
58974 
58975 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_MASK (0x1000U)
58976 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_SHIFT (12U)
58977 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_MASK)
58978 
58979 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_MASK (0x2000U)
58980 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_SHIFT (13U)
58981 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_MASK)
58982 
58983 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_MASK (0x4000U)
58984 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_SHIFT (14U)
58985 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_MASK)
58986 
58987 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_MASK (0x8000U)
58988 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_SHIFT (15U)
58989 #define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_MASK)
58990 
58991 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_MASK (0x10000U)
58992 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_SHIFT (16U)
58993 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_MASK)
58994 
58995 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_MASK (0x20000U)
58996 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_SHIFT (17U)
58997 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_MASK)
58998 
58999 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_MASK (0x40000U)
59000 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_SHIFT (18U)
59001 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_MASK)
59002 
59003 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_MASK (0x80000U)
59004 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_SHIFT (19U)
59005 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_MASK)
59006 
59007 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_MASK (0x100000U)
59008 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_SHIFT (20U)
59009 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_MASK)
59010 
59011 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_MASK (0x200000U)
59012 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_SHIFT (21U)
59013 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_MASK)
59014 
59015 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_MASK (0x400000U)
59016 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_SHIFT (22U)
59017 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_MASK)
59018 
59019 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_MASK (0x800000U)
59020 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_SHIFT (23U)
59021 #define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_MASK)
59022 
59023 #define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_MASK (0x1000000U)
59024 #define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_SHIFT (24U)
59025 #define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_MASK)
59026 
59027 #define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_MASK (0x2000000U)
59028 #define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_SHIFT (25U)
59029 #define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_MASK)
59030 
59031 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_MASK (0x4000000U)
59032 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_SHIFT (26U)
59033 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_MASK)
59034 
59035 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_MASK (0x8000000U)
59036 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_SHIFT (27U)
59037 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_MASK)
59038 
59039 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_MASK (0x10000000U)
59040 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_SHIFT (28U)
59041 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_MASK)
59042 
59043 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_MASK (0x20000000U)
59044 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_SHIFT (29U)
59045 #define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_MASK)
59046 
59047 #define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_MASK (0x40000000U)
59048 #define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_SHIFT (30U)
59049 #define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_MASK)
59050 
59051 #define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_MASK (0x80000000U)
59052 #define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_SHIFT (31U)
59053 #define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_MASK)
59054 /*! @} */
59055 
59056 /*! @name GPR21 - General Purpose Register 21 */
59057 /*! @{ */
59058 
59059 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_MASK (0x4000000U)
59060 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_SHIFT (26U)
59061 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_MASK)
59062 
59063 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_MASK (0x8000000U)
59064 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_SHIFT (27U)
59065 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_MASK)
59066 
59067 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_MASK (0x10000000U)
59068 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_SHIFT (28U)
59069 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_MASK)
59070 
59071 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_MASK (0x20000000U)
59072 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_SHIFT (29U)
59073 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_MASK)
59074 
59075 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_MASK (0x40000000U)
59076 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_SHIFT (30U)
59077 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_MASK)
59078 
59079 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_MASK (0x80000000U)
59080 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_SHIFT (31U)
59081 #define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_MASK)
59082 /*! @} */
59083 
59084 /*! @name GPR22 - General Purpose Register 22 */
59085 /*! @{ */
59086 
59087 #define IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_MASK     (0x1U)
59088 #define IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_SHIFT    (0U)
59089 /*! GPR_M7_CPUWAIT
59090  *  0b0..do not let CM7 enter wait mode
59091  *  0b1..let CM7 enter wait mode
59092  */
59093 #define IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_SHIFT)) & IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_MASK)
59094 
59095 #define IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_MASK (0x4U)
59096 #define IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_SHIFT (2U)
59097 /*! GPR_M7_HCLK_AUTO_GATE_EN
59098  *  0b0..depends on the value of "GPR_M7_HCLK_GATE_EN"
59099  *  0b1..ignore the value of "GPR_M7_HCLK_GATE_EN"
59100  */
59101 #define IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_SHIFT)) & IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_MASK)
59102 
59103 #define IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_MASK (0x8U)
59104 #define IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_SHIFT (3U)
59105 /*! GPR_M7_HCLK_GATE_EN
59106  *  0b0..gate on
59107  *  0b1..gate off
59108  */
59109 #define IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_SHIFT)) & IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_MASK)
59110 
59111 #define IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_MASK (0x10000U)
59112 #define IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_SHIFT (16U)
59113 #define IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_SHIFT)) & IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_MASK)
59114 /*! @} */
59115 
59116 /*! @name GPR24 - General Purpose Register 24 */
59117 /*! @{ */
59118 
59119 #define IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_MASK (0xFFU)
59120 #define IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_SHIFT (0U)
59121 #define IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_SHIFT)) & IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_MASK)
59122 
59123 #define IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_MASK (0xFF00U)
59124 #define IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_SHIFT (8U)
59125 #define IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_SHIFT)) & IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_MASK)
59126 
59127 #define IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_MASK (0xFF0000U)
59128 #define IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_SHIFT (16U)
59129 #define IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_SHIFT)) & IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_MASK)
59130 /*! @} */
59131 
59132 
59133 /*!
59134  * @}
59135  */ /* end of group IOMUXC_GPR_Register_Masks */
59136 
59137 
59138 /* IOMUXC_GPR - Peripheral instance base addresses */
59139 /** Peripheral IOMUXC_GPR base address */
59140 #define IOMUXC_GPR_BASE                          (0x30340000u)
59141 /** Peripheral IOMUXC_GPR base pointer */
59142 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
59143 /** Array initializer of IOMUXC_GPR peripheral base addresses */
59144 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
59145 /** Array initializer of IOMUXC_GPR peripheral base pointers */
59146 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
59147 
59148 /*!
59149  * @}
59150  */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
59151 
59152 
59153 /* ----------------------------------------------------------------------------
59154    -- IRQSTEER Peripheral Access Layer
59155    ---------------------------------------------------------------------------- */
59156 
59157 /*!
59158  * @addtogroup IRQSTEER_Peripheral_Access_Layer IRQSTEER Peripheral Access Layer
59159  * @{
59160  */
59161 
59162 /** IRQSTEER - Register Layout Typedef */
59163 typedef struct {
59164        uint8_t RESERVED_0[4];
59165   __IO uint32_t CHn_MASK[5];                       /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */
59166   __IO uint32_t CHn_SET[5];                        /**< Channel n Interrupt Set Register, array offset: 0x18, array step: 0x4 */
59167   __I  uint32_t CHn_STATUS[5];                     /**< Channel n Interrupt Status Register, array offset: 0x2C, array step: 0x4 */
59168   __IO uint32_t CHn_MINTDIS;                       /**< Channel n Master Interrupt Disable Register, offset: 0x40 */
59169   __I  uint32_t CHn_MSTRSTAT;                      /**< Channel n Master Status Register, offset: 0x44 */
59170 } IRQSTEER_Type;
59171 
59172 /* ----------------------------------------------------------------------------
59173    -- IRQSTEER Register Masks
59174    ---------------------------------------------------------------------------- */
59175 
59176 /*!
59177  * @addtogroup IRQSTEER_Register_Masks IRQSTEER Register Masks
59178  * @{
59179  */
59180 
59181 /*! @name CHN_MASK - Channel n Interrupt Mask Register */
59182 /*! @{ */
59183 
59184 #define IRQSTEER_CHn_MASK_MASKFLD_MASK           (0xFFFFFFFFU)
59185 #define IRQSTEER_CHn_MASK_MASKFLD_SHIFT          (0U)
59186 /*! MASKFLD - Mask bits
59187  *  0b00000000000000000000000000000000..Mask interrupt
59188  *  0b00000000000000000000000000000001..Do not mask interrupt
59189  */
59190 #define IRQSTEER_CHn_MASK_MASKFLD(x)             (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MASK_MASKFLD_SHIFT)) & IRQSTEER_CHn_MASK_MASKFLD_MASK)
59191 /*! @} */
59192 
59193 /* The count of IRQSTEER_CHN_MASK */
59194 #define IRQSTEER_CHn_MASK_COUNT                  (5U)
59195 
59196 /*! @name CHN_SET - Channel n Interrupt Set Register */
59197 /*! @{ */
59198 
59199 #define IRQSTEER_CHn_SET_FORCEFLD_MASK           (0xFFFFFFFFU)
59200 #define IRQSTEER_CHn_SET_FORCEFLD_SHIFT          (0U)
59201 /*! FORCEFLD - Force interrupt.
59202  *  0b00000000000000000000000000000000..Normal operation
59203  *  0b00000000000000000000000000000001..Force interrupt
59204  */
59205 #define IRQSTEER_CHn_SET_FORCEFLD(x)             (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_SET_FORCEFLD_SHIFT)) & IRQSTEER_CHn_SET_FORCEFLD_MASK)
59206 /*! @} */
59207 
59208 /* The count of IRQSTEER_CHN_SET */
59209 #define IRQSTEER_CHn_SET_COUNT                   (5U)
59210 
59211 /*! @name CHN_STATUS - Channel n Interrupt Status Register */
59212 /*! @{ */
59213 
59214 #define IRQSTEER_CHn_STATUS_STATUS_MASK          (0xFFFFFFFFU)
59215 #define IRQSTEER_CHn_STATUS_STATUS_SHIFT         (0U)
59216 /*! STATUS - Status of an interrupt
59217  *  0b00000000000000000000000000000000..Interrupt is not set.
59218  *  0b00000000000000000000000000000001..Interrupt is set.
59219  */
59220 #define IRQSTEER_CHn_STATUS_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_STATUS_STATUS_SHIFT)) & IRQSTEER_CHn_STATUS_STATUS_MASK)
59221 /*! @} */
59222 
59223 /* The count of IRQSTEER_CHN_STATUS */
59224 #define IRQSTEER_CHn_STATUS_COUNT                (5U)
59225 
59226 /*! @name CHN_MINTDIS - Channel n Master Interrupt Disable Register */
59227 /*! @{ */
59228 
59229 #define IRQSTEER_CHn_MINTDIS_DISABLE_MASK        (0x7U)
59230 #define IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT       (0U)
59231 /*! DISABLE - Each bit of this field disables the corresponding interrupts in table above.
59232  *  0b000..Enable interrupts
59233  *  0b001..Disable interrupts
59234  */
59235 #define IRQSTEER_CHn_MINTDIS_DISABLE(x)          (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT)) & IRQSTEER_CHn_MINTDIS_DISABLE_MASK)
59236 /*! @} */
59237 
59238 /*! @name CHN_MSTRSTAT - Channel n Master Status Register */
59239 /*! @{ */
59240 
59241 #define IRQSTEER_CHn_MSTRSTAT_STATUS_MASK        (0x1U)
59242 #define IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT       (0U)
59243 /*! STATUS - Status of all interrupts
59244  *  0b0..No interrupts are asserted.
59245  *  0b1..At least one interrupt is asserted.
59246  */
59247 #define IRQSTEER_CHn_MSTRSTAT_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT)) & IRQSTEER_CHn_MSTRSTAT_STATUS_MASK)
59248 /*! @} */
59249 
59250 
59251 /*!
59252  * @}
59253  */ /* end of group IRQSTEER_Register_Masks */
59254 
59255 
59256 /* IRQSTEER - Peripheral instance base addresses */
59257 /** Peripheral IRQ_STEER_AUDIO_PROCESSOR base address */
59258 #define IRQ_STEER_AUDIO_PROCESSOR_BASE           (0x30A80000u)
59259 /** Peripheral IRQ_STEER_AUDIO_PROCESSOR base pointer */
59260 #define IRQ_STEER_AUDIO_PROCESSOR                ((IRQSTEER_Type *)IRQ_STEER_AUDIO_PROCESSOR_BASE)
59261 /** Peripheral IRQ_STEER_HDMI base address */
59262 #define IRQ_STEER_HDMI_BASE                      (0x32FC2000u)
59263 /** Peripheral IRQ_STEER_HDMI base pointer */
59264 #define IRQ_STEER_HDMI                           ((IRQSTEER_Type *)IRQ_STEER_HDMI_BASE)
59265 /** Array initializer of IRQSTEER peripheral base addresses */
59266 #define IRQSTEER_BASE_ADDRS                      { IRQ_STEER_AUDIO_PROCESSOR_BASE, IRQ_STEER_HDMI_BASE }
59267 /** Array initializer of IRQSTEER peripheral base pointers */
59268 #define IRQSTEER_BASE_PTRS                       { IRQ_STEER_AUDIO_PROCESSOR, IRQ_STEER_HDMI }
59269 
59270 /*!
59271  * @}
59272  */ /* end of group IRQSTEER_Peripheral_Access_Layer */
59273 
59274 
59275 /* ----------------------------------------------------------------------------
59276    -- ISI Peripheral Access Layer
59277    ---------------------------------------------------------------------------- */
59278 
59279 /*!
59280  * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer
59281  * @{
59282  */
59283 
59284 /** ISI - Register Layout Typedef */
59285 typedef struct {
59286   __IO uint32_t CHNL_CTRL;                         /**< Channel Control Register, offset: 0x0 */
59287   __IO uint32_t CHNL_IMG_CTRL;                     /**< Channel Image Control Register, offset: 0x4 */
59288   __IO uint32_t CHNL_OUT_BUF_CTRL;                 /**< Channel Output Buffer Control Register, offset: 0x8 */
59289   __IO uint32_t CHNL_IMG_CFG;                      /**< Channel Image Configuration, offset: 0xC */
59290   __IO uint32_t CHNL_IER;                          /**< Channel Interrupt Enable Register, offset: 0x10 */
59291   __IO uint32_t CHNL_STS;                          /**< Channel Status Register, offset: 0x14 */
59292   __IO uint32_t CHNL_SCALE_FACTOR;                 /**< Channel Scale Factor Register, offset: 0x18 */
59293   __IO uint32_t CHNL_SCALE_OFFSET;                 /**< Channel Scale Offset Register, offset: 0x1C */
59294   __IO uint32_t CHNL_CROP_ULC;                     /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */
59295   __IO uint32_t CHNL_CROP_LRC;                     /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */
59296   __IO uint32_t CHNL_CSC_COEFF0;                   /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */
59297   __IO uint32_t CHNL_CSC_COEFF1;                   /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */
59298   __IO uint32_t CHNL_CSC_COEFF2;                   /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */
59299   __IO uint32_t CHNL_CSC_COEFF3;                   /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */
59300   __IO uint32_t CHNL_CSC_COEFF4;                   /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */
59301   __IO uint32_t CHNL_CSC_COEFF5;                   /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */
59302   __IO uint32_t CHNL_ROI_0_ALPHA;                  /**< Channel Alpha Value Register for Region of Interest 0, offset: 0x40 */
59303   __IO uint32_t CHNL_ROI_0_ULC;                    /**< Channel Upper Left Coordinate Register for Region of Interest 0, offset: 0x44 */
59304   __IO uint32_t CHNL_ROI_0_LRC;                    /**< Channel Lower Right Coordinate Register for Region of Interest 0, offset: 0x48 */
59305   __IO uint32_t CHNL_ROI_1_ALPHA;                  /**< Channel Alpha Value Register for Region of Interest 1, offset: 0x4C */
59306   __IO uint32_t CHNL_ROI_1_ULC;                    /**< Channel Upper Left Coordinate Register for Region of Interest 1, offset: 0x50 */
59307   __IO uint32_t CHNL_ROI_1_LRC;                    /**< Channel Lower Right Coordinate Register for Region of Interest 1, offset: 0x54 */
59308   __IO uint32_t CHNL_ROI_2_ALPHA;                  /**< Channel Alpha Value Register for Region of Interest 2, offset: 0x58 */
59309   __IO uint32_t CHNL_ROI_2_ULC;                    /**< Channel Upper Left Coordinate Register for Region of Interest 2, offset: 0x5C */
59310   __IO uint32_t CHNL_ROI_2_LRC;                    /**< Channel Lower Right Coordinate Register for Region of Interest 2, offset: 0x60 */
59311   __IO uint32_t CHNL_ROI_3_ALPHA;                  /**< Channel Alpha Value Register for Region of Interest 3, offset: 0x64 */
59312   __IO uint32_t CHNL_ROI_3_ULC;                    /**< Channel Upper Left Coordinate Register for Region of Interest 3, offset: 0x68 */
59313   __IO uint32_t CHNL_ROI_3_LRC;                    /**< Channel Lower Right Coordinate Register for Region of Interest 3, offset: 0x6C */
59314   __IO uint32_t CHNL_OUT_BUF1_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */
59315   __IO uint32_t CHNL_OUT_BUF1_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */
59316   __IO uint32_t CHNL_OUT_BUF1_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */
59317   __IO uint32_t CHNL_OUT_BUF_PITCH;                /**< Channel Output Buffer Pitch, offset: 0x7C */
59318   __IO uint32_t CHNL_IN_BUF_ADDR;                  /**< Channel Input Buffer Address, offset: 0x80 */
59319   __IO uint32_t CHNL_IN_BUF_PITCH;                 /**< Channel Input Buffer Pitch, offset: 0x84 */
59320   __IO uint32_t CHNL_MEM_RD_CTRL;                  /**< Channel Memory Read Control, offset: 0x88 */
59321   __IO uint32_t CHNL_OUT_BUF2_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */
59322   __IO uint32_t CHNL_OUT_BUF2_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */
59323   __IO uint32_t CHNL_OUT_BUF2_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */
59324   __IO uint32_t CHNL_SCL_IMG_CFG;                  /**< Channel Scaled Image Configuration, offset: 0x98 */
59325   __IO uint32_t CHNL_FLOW_CTRL;                    /**< Channel Flow Control Register, offset: 0x9C */
59326   __IO uint32_t CHNL_Y_BUF1_XTND_ADDR;             /**< Channel Output Y-Buffer 1 Extended Address Bits Register, offset: 0xA0 */
59327   __IO uint32_t CHNL_U_BUF1_XTND_ADDR;             /**< Channel Output U-Buffer 1 Extended Address Bits Register, offset: 0xA4 */
59328   __IO uint32_t CHNL_V_BUF1_XTND_ADDR;             /**< Channel Output V-Buffer 1 Extended Address Bits Register, offset: 0xA8 */
59329   __IO uint32_t CHNL_Y_BUF2_XTND_ADDR;             /**< Channel Output Y-Buffer 2 Extended Address Bits Register, offset: 0xAC */
59330   __IO uint32_t CHNL_U_BUF2_XTND_ADDR;             /**< Channel Output U-Buffer 2 Extended Address Bits Register, offset: 0xB0 */
59331   __IO uint32_t CHNL_V_BUF2_XTND_ADDR;             /**< Channel Output V-Buffer 2 Extended Address Bits Register, offset: 0xB4 */
59332   __IO uint32_t CHNL_IN_BUF_XTND_ADDR;             /**< Channel Input Buffer Extended Address Bits Register, offset: 0xB8 */
59333 } ISI_Type;
59334 
59335 /* ----------------------------------------------------------------------------
59336    -- ISI Register Masks
59337    ---------------------------------------------------------------------------- */
59338 
59339 /*!
59340  * @addtogroup ISI_Register_Masks ISI Register Masks
59341  * @{
59342  */
59343 
59344 /*! @name CHNL_CTRL - Channel Control Register */
59345 /*! @{ */
59346 
59347 #define ISI_CHNL_CTRL_SRC_MASK                   (0x1U)
59348 #define ISI_CHNL_CTRL_SRC_SHIFT                  (0U)
59349 /*! SRC - Input image source port selection
59350  *  0b0..Image will be sourced from input port 0 of the Pixel Link Crossbar
59351  *  0b1..Image will be sourced from input port 1 of the Pixel Link Crossbar
59352  */
59353 #define ISI_CHNL_CTRL_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK)
59354 
59355 #define ISI_CHNL_CTRL_SRC_TYPE_MASK              (0x10U)
59356 #define ISI_CHNL_CTRL_SRC_TYPE_SHIFT             (4U)
59357 /*! SRC_TYPE - Type of selected input image source
59358  *  0b0..Image input source is Pixel Link
59359  *  0b1..Image input source is Memory
59360  */
59361 #define ISI_CHNL_CTRL_SRC_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK)
59362 
59363 #define ISI_CHNL_CTRL_SEC_LB_SRC_MASK            (0x700U)
59364 #define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT           (8U)
59365 /*! SEC_LB_SRC - Secondary line buffer source */
59366 #define ISI_CHNL_CTRL_SEC_LB_SRC(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK)
59367 
59368 #define ISI_CHNL_CTRL_SW_RST_MASK                (0x1000000U)
59369 #define ISI_CHNL_CTRL_SW_RST_SHIFT               (24U)
59370 /*! SW_RST - Software reset bit
59371  *  0b0..No Reset
59372  *  0b1..Channel pipeline is under software reset
59373  */
59374 #define ISI_CHNL_CTRL_SW_RST(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK)
59375 
59376 #define ISI_CHNL_CTRL_CHAIN_BUF_MASK             (0x6000000U)
59377 #define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT            (25U)
59378 /*! CHAIN_BUF - Chain line buffer control
59379  *  0b00..No line buffers chained (supports 2048 or less horizontal resolution)
59380  *  0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are chained.
59381  *  0b10..4 line buffers chained (supports 8192 horizontal resolution). Line buffers of channels 'n', 'n+1', 'n+2' and 'n+3' are chained.
59382  *  0b11..Reserved for future use
59383  */
59384 #define ISI_CHNL_CTRL_CHAIN_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK)
59385 
59386 #define ISI_CHNL_CTRL_CHNL_BYPASS_MASK           (0x20000000U)
59387 #define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT          (29U)
59388 /*! CHNL_BYPASS - Channel bypass enable
59389  *  0b0..Channel is not bypassed
59390  *  0b1..Channel is bypassed
59391  */
59392 #define ISI_CHNL_CTRL_CHNL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK)
59393 
59394 #define ISI_CHNL_CTRL_CLK_EN_MASK                (0x40000000U)
59395 #define ISI_CHNL_CTRL_CLK_EN_SHIFT               (30U)
59396 /*! CLK_EN - Channel clock enable
59397  *  0b0..Channel processing clock is disabled
59398  *  0b1..Channel processing clock is enabled
59399  */
59400 #define ISI_CHNL_CTRL_CLK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK)
59401 
59402 #define ISI_CHNL_CTRL_CHNL_EN_MASK               (0x80000000U)
59403 #define ISI_CHNL_CTRL_CHNL_EN_SHIFT              (31U)
59404 /*! CHNL_EN - Enable channel processing
59405  *  0b0..Processing channel is disabled
59406  *  0b1..Processing channel is enabled
59407  */
59408 #define ISI_CHNL_CTRL_CHNL_EN(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK)
59409 /*! @} */
59410 
59411 /*! @name CHNL_IMG_CTRL - Channel Image Control Register */
59412 /*! @{ */
59413 
59414 #define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK           (0x1U)
59415 #define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT          (0U)
59416 /*! CSC_BYP - Color Space Conversion bypass control
59417  *  0b0..CSC is operational
59418  *  0b1..CSC is bypassed
59419  */
59420 #define ISI_CHNL_IMG_CTRL_CSC_BYP(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK)
59421 
59422 #define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK          (0x6U)
59423 #define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT         (1U)
59424 /*! CSC_MODE - Color Space Conversion operating mode
59425  *  0b00..Convert from YUV to RGB
59426  *  0b01..Convert from YCbCr to RGB
59427  *  0b10..Convert from RGB to YUV
59428  *  0b11..Convert from RGB to YCbCr
59429  */
59430 #define ISI_CHNL_IMG_CTRL_CSC_MODE(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK)
59431 
59432 #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK        (0x8U)
59433 #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT       (3U)
59434 /*! YCBCR_MODE - YCbCr Mode
59435  *  0b0..YCbCr mode is disabled
59436  *  0b1..YCbCr mode is enabled
59437  */
59438 #define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK)
59439 
59440 #define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK          (0x20U)
59441 #define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT         (5U)
59442 /*! HFLIP_EN - Horizontal flip control
59443  *  0b0..Horizantal image flip disabled
59444  *  0b1..Horizontal image flip enabled
59445  */
59446 #define ISI_CHNL_IMG_CTRL_HFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK)
59447 
59448 #define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK          (0x40U)
59449 #define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT         (6U)
59450 /*! VFLIP_EN - Veritical flip control
59451  *  0b0..Vertical image flip disabled
59452  *  0b1..Vertical image flip enabled
59453  */
59454 #define ISI_CHNL_IMG_CTRL_VFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK)
59455 
59456 #define ISI_CHNL_IMG_CTRL_CROP_EN_MASK           (0x80U)
59457 #define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT          (7U)
59458 /*! CROP_EN - Output image cropping enable
59459  *  0b0..Image cropping is disabled
59460  *  0b1..Image cropping is enabled
59461  */
59462 #define ISI_CHNL_IMG_CTRL_CROP_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK)
59463 
59464 #define ISI_CHNL_IMG_CTRL_DEC_Y_MASK             (0x300U)
59465 #define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT            (8U)
59466 /*! DEC_Y - Vertical pre-decimation control
59467  *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
59468  *  0b01..Decimate by 2
59469  *  0b10..Decimate by 4
59470  *  0b11..Decimate by 8
59471  */
59472 #define ISI_CHNL_IMG_CTRL_DEC_Y(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK)
59473 
59474 #define ISI_CHNL_IMG_CTRL_DEC_X_MASK             (0xC00U)
59475 #define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT            (10U)
59476 /*! DEC_X - Horizontal pre-decimation control
59477  *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
59478  *  0b01..Decimate by 2
59479  *  0b10..Decimate by 4
59480  *  0b11..Decimate by 8
59481  */
59482 #define ISI_CHNL_IMG_CTRL_DEC_X(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK)
59483 
59484 #define ISI_CHNL_IMG_CTRL_DEINT_MASK             (0x7000U)
59485 #define ISI_CHNL_IMG_CTRL_DEINT_SHIFT            (12U)
59486 /*! DEINT - De-interlace control
59487  *  0b000, 0b001..No de-interlacing done
59488  *  0b010..Weave de-interlacing (Odd, Even) method used
59489  *  0b011..Weave de-interlacing (Even, Odd) method used
59490  *  0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used
59491  *  0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used
59492  *  0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled.
59493  */
59494 #define ISI_CHNL_IMG_CTRL_DEINT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK)
59495 
59496 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK      (0x8000U)
59497 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT     (15U)
59498 /*! GBL_ALPHA_EN - Global alpha value insertion enable
59499  *  0b0..Global Alpha value insertion is disabled
59500  *  0b1..Global Alpha value insertion is enabled
59501  */
59502 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK)
59503 
59504 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK     (0xFF0000U)
59505 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT    (16U)
59506 /*! GBL_ALPHA_VAL - Global alpha value
59507  *  0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels
59508  */
59509 #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK)
59510 
59511 #define ISI_CHNL_IMG_CTRL_FORMAT_MASK            (0x3F000000U)
59512 #define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT           (24U)
59513 /*! FORMAT - Output image format
59514  *  0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value.
59515  *  0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
59516  *  0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
59517  *  0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' indicates the waste bits.
59518  *  0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
59519  *  0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
59520  *  0b000110..RGB888P - RGB format with 8-bits per color component (packed into 24-bits). No waste bits.
59521  *  0b000111..BGR888P - BGR format with 8-bits per color component (packed into 24-bits). No waste bits.
59522  *  0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
59523  *  0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
59524  *  0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 16-bits WORD). No waste bits.
59525  *  0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD
59526  *  0b001100..RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits
59527  *  0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD
59528  *  0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits
59529  *  0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD
59530  *  0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
59531  *  0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
59532  *  0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
59533  *  0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
59534  *  0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59535  *  0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59536  *  0b010110..YUV444_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59537  *  0b010111..Reserved for future use
59538  *  0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59539  *  0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59540  *  0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59541  *  0b011011..Reserved for future use
59542  *  0b011100..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59543  *  0b011101..YUV444_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59544  *  0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59545  *  0b011111..Reserved for future use
59546  *  0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
59547  *  0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
59548  *  0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
59549  *  0b100011..Reserved for future use
59550  *  0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59551  *  0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59552  *  0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59553  *  0b100111..Reserved for future use
59554  *  0b101000..YUV422_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59555  *  0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59556  *  0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59557  *  0b101011..Reserved for future use
59558  *  0b101100..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59559  *  0b101101..YUV422_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59560  *  0b101110..YUV422_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59561  *  0b101111..Reserved for future use
59562  *  0b110000..Reserved for future use
59563  *  0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
59564  *  0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
59565  *  0b110011..Reserved for future use
59566  *  0b110100..Reserved for future use
59567  *  0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59568  *  0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
59569  *  0b110111..Reserved for future use
59570  *  0b111000..Reserved for future use
59571  *  0b111001..YUV420_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59572  *  0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
59573  *  0b111011..Reserved for future use
59574  *  0b111100..Reserved for future use
59575  *  0b111101..YUV420_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59576  *  0b111110..YUV420_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
59577  *  0b111111..Reserved for future use
59578  */
59579 #define ISI_CHNL_IMG_CTRL_FORMAT(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK)
59580 /*! @} */
59581 
59582 /*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */
59583 /*! @{ */
59584 
59585 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU)
59586 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U)
59587 /*! PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer
59588  *  0b0000..No panic alert will be asserted
59589  *  0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
59590  */
59591 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK)
59592 
59593 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U)
59594 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U)
59595 /*! PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer
59596  *  0b0000..No panic alert will be asserted
59597  *  0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
59598  */
59599 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK)
59600 
59601 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U)
59602 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U)
59603 /*! LOAD_BUF1_ADDR - Load Buffer 1 Address from CHNLOUT_BUF1_ADDR_* registers */
59604 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK)
59605 
59606 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U)
59607 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U)
59608 /*! LOAD_BUF2_ADDR - Load Buffer 2 Address from CHNLOUT_BUF2_ADDR_* registers */
59609 #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK)
59610 
59611 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U)
59612 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U)
59613 /*! PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer
59614  *  0b0000..No panic alert will be asserted
59615  *  0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
59616  */
59617 #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK)
59618 
59619 #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U)
59620 #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U)
59621 /*! MAX_WR_BEATS_UV - Maximum AXI write beats for U and V-buffers
59622  *  0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
59623  *  0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
59624  */
59625 #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK)
59626 
59627 #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U)
59628 #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U)
59629 /*! MAX_WR_BEATS_Y - Maximum AXI write beats for Y-buffer
59630  *  0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
59631  *  0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
59632  */
59633 #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK)
59634 /*! @} */
59635 
59636 /*! @name CHNL_IMG_CFG - Channel Image Configuration */
59637 /*! @{ */
59638 
59639 #define ISI_CHNL_IMG_CFG_WIDTH_MASK              (0x1FFFU)
59640 #define ISI_CHNL_IMG_CFG_WIDTH_SHIFT             (0U)
59641 /*! WIDTH - Input image width (pixels) */
59642 #define ISI_CHNL_IMG_CFG_WIDTH(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK)
59643 
59644 #define ISI_CHNL_IMG_CFG_HEIGHT_MASK             (0x1FFF0000U)
59645 #define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT            (16U)
59646 /*! HEIGHT - Input image height (lines) */
59647 #define ISI_CHNL_IMG_CFG_HEIGHT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK)
59648 /*! @} */
59649 
59650 /*! @name CHNL_IER - Channel Interrupt Enable Register */
59651 /*! @{ */
59652 
59653 #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK      (0x10000U)
59654 #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT     (16U)
59655 /*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit
59656  *  0b0..Interrupt is disabled
59657  *  0b1..Interrupt is enabled
59658  */
59659 #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK)
59660 
59661 #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK     (0x20000U)
59662 #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT    (17U)
59663 /*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit
59664  *  0b0..Interrupt is disabled
59665  *  0b1..Interrupt is enabled
59666  */
59667 #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK)
59668 
59669 #define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK          (0x40000U)
59670 #define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT         (18U)
59671 /*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit
59672  *  0b0..Interrupt is disabled
59673  *  0b1..Interrupt is enabled
59674  */
59675 #define ISI_CHNL_IER_OFLW_Y_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK)
59676 
59677 #define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK         (0x80000U)
59678 #define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT        (19U)
59679 /*! PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit
59680  *  0b0..Interrupt is disabled
59681  *  0b1..Interrupt is enabled
59682  */
59683 #define ISI_CHNL_IER_PANIC_Y_BUF_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK)
59684 
59685 #define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK          (0x100000U)
59686 #define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT         (20U)
59687 /*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit
59688  *  0b0..Interrupt is disabled
59689  *  0b1..Interrupt is enabled
59690  */
59691 #define ISI_CHNL_IER_OFLW_U_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK)
59692 
59693 #define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK         (0x200000U)
59694 #define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT        (21U)
59695 /*! PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit
59696  *  0b0..Interrupt is disabled
59697  *  0b1..Interrupt is enabled
59698  */
59699 #define ISI_CHNL_IER_PANIC_U_BUF_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK)
59700 
59701 #define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK          (0x400000U)
59702 #define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT         (22U)
59703 /*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit
59704  *  0b0..Interrupt is disabled
59705  *  0b1..Interrupt is enabled
59706  */
59707 #define ISI_CHNL_IER_OFLW_V_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK)
59708 
59709 #define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK         (0x800000U)
59710 #define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT        (23U)
59711 /*! PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit
59712  *  0b0..Interrupt is disabled
59713  *  0b1..Interrupt is enabled
59714  */
59715 #define ISI_CHNL_IER_PANIC_V_BUF_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK)
59716 
59717 #define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK          (0x2000000U)
59718 #define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT         (25U)
59719 /*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit
59720  *  0b0..Interrupt is disabled
59721  *  0b1..Interrupt is enabled
59722  */
59723 #define ISI_CHNL_IER_AXI_RD_ERR_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK)
59724 
59725 #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK        (0x4000000U)
59726 #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT       (26U)
59727 /*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer
59728  *  0b0..Interrupt is disabled
59729  *  0b1..Interrupt is enabled
59730  */
59731 #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK)
59732 
59733 #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK        (0x8000000U)
59734 #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT       (27U)
59735 /*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer
59736  *  0b0..Interrupt is disabled
59737  *  0b1..Interrupt is enabled
59738  */
59739 #define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK)
59740 
59741 #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK        (0x10000000U)
59742 #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT       (28U)
59743 /*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer
59744  *  0b0..Interrupt is disabled
59745  *  0b1..Interrupt is enabled
59746  */
59747 #define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK)
59748 
59749 #define ISI_CHNL_IER_FRM_RCVD_EN_MASK            (0x20000000U)
59750 #define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT           (29U)
59751 /*! FRM_RCVD_EN - Frame received interrupt enable bit
59752  *  0b0..Interrupt is disabled
59753  *  0b1..Interrupt is enabled
59754  */
59755 #define ISI_CHNL_IER_FRM_RCVD_EN(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK)
59756 
59757 #define ISI_CHNL_IER_LINE_RCVD_EN_MASK           (0x40000000U)
59758 #define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT          (30U)
59759 /*! LINE_RCVD_EN - Line received interrupt enable bit
59760  *  0b0..Interrupt is disabled
59761  *  0b1..Interrupt is enabled
59762  */
59763 #define ISI_CHNL_IER_LINE_RCVD_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK)
59764 
59765 #define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK         (0x80000000U)
59766 #define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT        (31U)
59767 /*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit
59768  *  0b0..Interrupt is disabled
59769  *  0b1..Interrupt is enabled
59770  */
59771 #define ISI_CHNL_IER_MEM_RD_DONE_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK)
59772 /*! @} */
59773 
59774 /*! @name CHNL_STS - Channel Status Register */
59775 /*! @{ */
59776 
59777 #define ISI_CHNL_STS_BUF1_ACTIVE_MASK            (0x100U)
59778 #define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT           (8U)
59779 /*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address
59780  *  0b0..Buffer 1 Address inactive
59781  *  0b1..Buffer 1 Address in use
59782  */
59783 #define ISI_CHNL_STS_BUF1_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK)
59784 
59785 #define ISI_CHNL_STS_BUF2_ACTIVE_MASK            (0x200U)
59786 #define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT           (9U)
59787 /*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address
59788  *  0b0..Buffer 2 Address inactive
59789  *  0b1..Buffer 2 Address in use
59790  */
59791 #define ISI_CHNL_STS_BUF2_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK)
59792 
59793 #define ISI_CHNL_STS_MEM_RD_OFLOW_MASK           (0x400U)
59794 #define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT          (10U)
59795 /*! MEM_RD_OFLOW - Memory read FIFO overflow error status
59796  *  0b0..No overflow occurred during memory read
59797  *  0b1..FIFO overflow occurred during memory read
59798  */
59799 #define ISI_CHNL_STS_MEM_RD_OFLOW(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK)
59800 
59801 #define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK         (0x10000U)
59802 #define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT        (16U)
59803 /*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag
59804  *  0b0..No error
59805  *  0b1..VSYNC detected later than expected
59806  */
59807 #define ISI_CHNL_STS_LATE_VSYNC_ERR(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK)
59808 
59809 #define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK        (0x20000U)
59810 #define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT       (17U)
59811 /*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag
59812  *  0b0..No error
59813  *  0b1..VSYNC detected earlier than expected
59814  */
59815 #define ISI_CHNL_STS_EARLY_VSYNC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK)
59816 
59817 #define ISI_CHNL_STS_OFLW_Y_BUF_MASK             (0x40000U)
59818 #define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT            (18U)
59819 /*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag
59820  *  0b0..No overflow
59821  *  0b1..Overflow has occured in the channel
59822  */
59823 #define ISI_CHNL_STS_OFLW_Y_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK)
59824 
59825 #define ISI_CHNL_STS_PANIC_Y_BUF_MASK            (0x80000U)
59826 #define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT           (19U)
59827 /*! PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag
59828  *  0b0..Buffer has not crossed the panic threshold limit
59829  *  0b1..Panic threshold limit crossed. Software must take action.
59830  */
59831 #define ISI_CHNL_STS_PANIC_Y_BUF(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK)
59832 
59833 #define ISI_CHNL_STS_OFLW_U_BUF_MASK             (0x100000U)
59834 #define ISI_CHNL_STS_OFLW_U_BUF_SHIFT            (20U)
59835 /*! OFLW_U_BUF - Overflow in U output buffer interrupt flag
59836  *  0b0..No overflow
59837  *  0b1..Overflow has occured in the channel
59838  */
59839 #define ISI_CHNL_STS_OFLW_U_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK)
59840 
59841 #define ISI_CHNL_STS_PANIC_U_BUF_MASK            (0x200000U)
59842 #define ISI_CHNL_STS_PANIC_U_BUF_SHIFT           (21U)
59843 /*! PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag
59844  *  0b0..Buffer has not crossed the panic threshold limit
59845  *  0b1..Panic threshold limit crossed. Software must take action.
59846  */
59847 #define ISI_CHNL_STS_PANIC_U_BUF(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK)
59848 
59849 #define ISI_CHNL_STS_OFLW_V_BUF_MASK             (0x400000U)
59850 #define ISI_CHNL_STS_OFLW_V_BUF_SHIFT            (22U)
59851 /*! OFLW_V_BUF - Overflow in U output buffer interrupt flag
59852  *  0b0..No overflow
59853  *  0b1..Overflow has occured in the channel
59854  */
59855 #define ISI_CHNL_STS_OFLW_V_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK)
59856 
59857 #define ISI_CHNL_STS_PANIC_V_BUF_MASK            (0x800000U)
59858 #define ISI_CHNL_STS_PANIC_V_BUF_SHIFT           (23U)
59859 /*! PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag
59860  *  0b0..Buffer has not crossed the panic threshold limit
59861  *  0b1..Panic threshold limit crossed. Software must take action.
59862  */
59863 #define ISI_CHNL_STS_PANIC_V_BUF(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK)
59864 
59865 #define ISI_CHNL_STS_AXI_RD_ERR_MASK             (0x2000000U)
59866 #define ISI_CHNL_STS_AXI_RD_ERR_SHIFT            (25U)
59867 /*! AXI_RD_ERR - AXI Bus read error interrupt flag
59868  *  0b0..No error
59869  *  0b1..Error occured during read
59870  */
59871 #define ISI_CHNL_STS_AXI_RD_ERR(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK)
59872 
59873 #define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK           (0x4000000U)
59874 #define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT          (26U)
59875 /*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer
59876  *  0b0..No error
59877  *  0b1..Error occured during write
59878  */
59879 #define ISI_CHNL_STS_AXI_WR_ERR_Y(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK)
59880 
59881 #define ISI_CHNL_STS_AXI_WR_ERR_U_MASK           (0x8000000U)
59882 #define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT          (27U)
59883 /*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer
59884  *  0b0..No error
59885  *  0b1..Error occured during write
59886  */
59887 #define ISI_CHNL_STS_AXI_WR_ERR_U(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK)
59888 
59889 #define ISI_CHNL_STS_AXI_WR_ERR_V_MASK           (0x10000000U)
59890 #define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT          (28U)
59891 /*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer
59892  *  0b0..No error
59893  *  0b1..Error occured during write
59894  */
59895 #define ISI_CHNL_STS_AXI_WR_ERR_V(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK)
59896 
59897 #define ISI_CHNL_STS_FRM_STRD_MASK               (0x20000000U)
59898 #define ISI_CHNL_STS_FRM_STRD_SHIFT              (29U)
59899 /*! FRM_STRD - Frame stored successfully interrupt flag
59900  *  0b0..No frame being received or in progress
59901  *  0b1..One full frame has been received and stored in memory
59902  */
59903 #define ISI_CHNL_STS_FRM_STRD(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK)
59904 
59905 #define ISI_CHNL_STS_LINE_STRD_MASK              (0x40000000U)
59906 #define ISI_CHNL_STS_LINE_STRD_SHIFT             (30U)
59907 /*! LINE_STRD - Line received and stored interrupt flag
59908  *  0b0..No new line received
59909  *  0b1..New line received and stored into memory
59910  */
59911 #define ISI_CHNL_STS_LINE_STRD(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK)
59912 
59913 #define ISI_CHNL_STS_MEM_RD_DONE_MASK            (0x80000000U)
59914 #define ISI_CHNL_STS_MEM_RD_DONE_SHIFT           (31U)
59915 /*! MEM_RD_DONE - Memory read complete interrupt flag
59916  *  0b0..Image read from memory not complete or not started
59917  *  0b1..Image read from memory completed
59918  */
59919 #define ISI_CHNL_STS_MEM_RD_DONE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK)
59920 /*! @} */
59921 
59922 /*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */
59923 /*! @{ */
59924 
59925 #define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK       (0x3FFFU)
59926 #define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT      (0U)
59927 /*! X_SCALE - Horizontal scaling factor */
59928 #define ISI_CHNL_SCALE_FACTOR_X_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK)
59929 
59930 #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK       (0x3FFF0000U)
59931 #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT      (16U)
59932 /*! Y_SCALE - Vertical scaling factor */
59933 #define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK)
59934 /*! @} */
59935 
59936 /*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */
59937 /*! @{ */
59938 
59939 #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK      (0xFFFU)
59940 #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT     (0U)
59941 /*! X_OFFSET - Horizontal scaling offset */
59942 #define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK)
59943 
59944 #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK      (0xFFF0000U)
59945 #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT     (16U)
59946 /*! Y_OFFSET - Vertical scaling offset */
59947 #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK)
59948 /*! @} */
59949 
59950 /*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */
59951 /*! @{ */
59952 
59953 #define ISI_CHNL_CROP_ULC_Y_MASK                 (0xFFFU)
59954 #define ISI_CHNL_CROP_ULC_Y_SHIFT                (0U)
59955 /*! Y - Upper Left Y-coordinate */
59956 #define ISI_CHNL_CROP_ULC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK)
59957 
59958 #define ISI_CHNL_CROP_ULC_X_MASK                 (0xFFF0000U)
59959 #define ISI_CHNL_CROP_ULC_X_SHIFT                (16U)
59960 /*! X - Upper Left X-coordinate */
59961 #define ISI_CHNL_CROP_ULC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK)
59962 /*! @} */
59963 
59964 /*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */
59965 /*! @{ */
59966 
59967 #define ISI_CHNL_CROP_LRC_Y_MASK                 (0xFFFU)
59968 #define ISI_CHNL_CROP_LRC_Y_SHIFT                (0U)
59969 /*! Y - Lower Right Y-coordinate */
59970 #define ISI_CHNL_CROP_LRC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK)
59971 
59972 #define ISI_CHNL_CROP_LRC_X_MASK                 (0xFFF0000U)
59973 #define ISI_CHNL_CROP_LRC_X_SHIFT                (16U)
59974 /*! X - Lower Right X-coordinate */
59975 #define ISI_CHNL_CROP_LRC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK)
59976 /*! @} */
59977 
59978 /*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */
59979 /*! @{ */
59980 
59981 #define ISI_CHNL_CSC_COEFF0_A1_MASK              (0x7FFU)
59982 #define ISI_CHNL_CSC_COEFF0_A1_SHIFT             (0U)
59983 /*! A1 - CSC Coefficient A1 value */
59984 #define ISI_CHNL_CSC_COEFF0_A1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK)
59985 
59986 #define ISI_CHNL_CSC_COEFF0_A2_MASK              (0x7FF0000U)
59987 #define ISI_CHNL_CSC_COEFF0_A2_SHIFT             (16U)
59988 /*! A2 - CSC Coefficient A2 value */
59989 #define ISI_CHNL_CSC_COEFF0_A2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK)
59990 /*! @} */
59991 
59992 /*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */
59993 /*! @{ */
59994 
59995 #define ISI_CHNL_CSC_COEFF1_A3_MASK              (0x7FFU)
59996 #define ISI_CHNL_CSC_COEFF1_A3_SHIFT             (0U)
59997 /*! A3 - CSC Coefficient A3 value */
59998 #define ISI_CHNL_CSC_COEFF1_A3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK)
59999 
60000 #define ISI_CHNL_CSC_COEFF1_B1_MASK              (0x7FF0000U)
60001 #define ISI_CHNL_CSC_COEFF1_B1_SHIFT             (16U)
60002 /*! B1 - CSC Coefficient B1 value */
60003 #define ISI_CHNL_CSC_COEFF1_B1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK)
60004 /*! @} */
60005 
60006 /*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */
60007 /*! @{ */
60008 
60009 #define ISI_CHNL_CSC_COEFF2_B2_MASK              (0x7FFU)
60010 #define ISI_CHNL_CSC_COEFF2_B2_SHIFT             (0U)
60011 /*! B2 - CSC Coefficient B2 value */
60012 #define ISI_CHNL_CSC_COEFF2_B2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK)
60013 
60014 #define ISI_CHNL_CSC_COEFF2_B3_MASK              (0x7FF0000U)
60015 #define ISI_CHNL_CSC_COEFF2_B3_SHIFT             (16U)
60016 /*! B3 - CSC Coefficient B3 value */
60017 #define ISI_CHNL_CSC_COEFF2_B3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK)
60018 /*! @} */
60019 
60020 /*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */
60021 /*! @{ */
60022 
60023 #define ISI_CHNL_CSC_COEFF3_C1_MASK              (0x7FFU)
60024 #define ISI_CHNL_CSC_COEFF3_C1_SHIFT             (0U)
60025 /*! C1 - CSC Coefficient C1 value */
60026 #define ISI_CHNL_CSC_COEFF3_C1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK)
60027 
60028 #define ISI_CHNL_CSC_COEFF3_C2_MASK              (0x7FF0000U)
60029 #define ISI_CHNL_CSC_COEFF3_C2_SHIFT             (16U)
60030 /*! C2 - CSC Coefficient C2 value */
60031 #define ISI_CHNL_CSC_COEFF3_C2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK)
60032 /*! @} */
60033 
60034 /*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */
60035 /*! @{ */
60036 
60037 #define ISI_CHNL_CSC_COEFF4_C3_MASK              (0x7FFU)
60038 #define ISI_CHNL_CSC_COEFF4_C3_SHIFT             (0U)
60039 /*! C3 - CSC Coefficient C3 value */
60040 #define ISI_CHNL_CSC_COEFF4_C3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK)
60041 
60042 #define ISI_CHNL_CSC_COEFF4_D1_MASK              (0x1FF0000U)
60043 #define ISI_CHNL_CSC_COEFF4_D1_SHIFT             (16U)
60044 /*! D1 - CSC Coefficient D1 value */
60045 #define ISI_CHNL_CSC_COEFF4_D1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK)
60046 /*! @} */
60047 
60048 /*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */
60049 /*! @{ */
60050 
60051 #define ISI_CHNL_CSC_COEFF5_D2_MASK              (0x1FFU)
60052 #define ISI_CHNL_CSC_COEFF5_D2_SHIFT             (0U)
60053 /*! D2 - CSC Coefficient D2 value */
60054 #define ISI_CHNL_CSC_COEFF5_D2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK)
60055 
60056 #define ISI_CHNL_CSC_COEFF5_D3_MASK              (0x1FF0000U)
60057 #define ISI_CHNL_CSC_COEFF5_D3_SHIFT             (16U)
60058 /*! D3 - CSC Coefficient D3 value */
60059 #define ISI_CHNL_CSC_COEFF5_D3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK)
60060 /*! @} */
60061 
60062 /*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value Register for Region of Interest 0 */
60063 /*! @{ */
60064 
60065 #define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK       (0x10000U)
60066 #define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT      (16U)
60067 /*! ALPHA_EN - Alpha value insertion enable
60068  *  0b0..Alpha value insertion is disabled
60069  *  0b1..Alpha value insertion is enabled
60070  */
60071 #define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK)
60072 
60073 #define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK          (0xFF000000U)
60074 #define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT         (24U)
60075 /*! ALPHA - Alpha Value to be inserted with image */
60076 #define ISI_CHNL_ROI_0_ALPHA_ALPHA(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK)
60077 /*! @} */
60078 
60079 /*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate Register for Region of Interest 0 */
60080 /*! @{ */
60081 
60082 #define ISI_CHNL_ROI_0_ULC_Y_MASK                (0xFFFU)
60083 #define ISI_CHNL_ROI_0_ULC_Y_SHIFT               (0U)
60084 /*! Y - Upper Left Y-coordinate */
60085 #define ISI_CHNL_ROI_0_ULC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK)
60086 
60087 #define ISI_CHNL_ROI_0_ULC_X_MASK                (0xFFF0000U)
60088 #define ISI_CHNL_ROI_0_ULC_X_SHIFT               (16U)
60089 /*! X - Upper Left X-coordinate */
60090 #define ISI_CHNL_ROI_0_ULC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK)
60091 /*! @} */
60092 
60093 /*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate Register for Region of Interest 0 */
60094 /*! @{ */
60095 
60096 #define ISI_CHNL_ROI_0_LRC_Y_MASK                (0xFFFU)
60097 #define ISI_CHNL_ROI_0_LRC_Y_SHIFT               (0U)
60098 /*! Y - Lower Right Y-coordinate */
60099 #define ISI_CHNL_ROI_0_LRC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK)
60100 
60101 #define ISI_CHNL_ROI_0_LRC_X_MASK                (0xFFF0000U)
60102 #define ISI_CHNL_ROI_0_LRC_X_SHIFT               (16U)
60103 /*! X - Lower Right X-coordinate */
60104 #define ISI_CHNL_ROI_0_LRC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK)
60105 /*! @} */
60106 
60107 /*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value Register for Region of Interest 1 */
60108 /*! @{ */
60109 
60110 #define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK       (0x10000U)
60111 #define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT      (16U)
60112 /*! ALPHA_EN - Alpha value insertion enable
60113  *  0b0..Alpha value insertion is disabled
60114  *  0b1..Alpha value insertion is enabled
60115  */
60116 #define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK)
60117 
60118 #define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK          (0xFF000000U)
60119 #define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT         (24U)
60120 /*! ALPHA - Alpha Value to be inserted with image */
60121 #define ISI_CHNL_ROI_1_ALPHA_ALPHA(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK)
60122 /*! @} */
60123 
60124 /*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate Register for Region of Interest 1 */
60125 /*! @{ */
60126 
60127 #define ISI_CHNL_ROI_1_ULC_Y_MASK                (0xFFFU)
60128 #define ISI_CHNL_ROI_1_ULC_Y_SHIFT               (0U)
60129 /*! Y - Upper Left Y-coordinate */
60130 #define ISI_CHNL_ROI_1_ULC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK)
60131 
60132 #define ISI_CHNL_ROI_1_ULC_X_MASK                (0xFFF0000U)
60133 #define ISI_CHNL_ROI_1_ULC_X_SHIFT               (16U)
60134 /*! X - Upper Left X-coordinate */
60135 #define ISI_CHNL_ROI_1_ULC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK)
60136 /*! @} */
60137 
60138 /*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate Register for Region of Interest 1 */
60139 /*! @{ */
60140 
60141 #define ISI_CHNL_ROI_1_LRC_Y_MASK                (0xFFFU)
60142 #define ISI_CHNL_ROI_1_LRC_Y_SHIFT               (0U)
60143 /*! Y - Lower Right Y-coordinate */
60144 #define ISI_CHNL_ROI_1_LRC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK)
60145 
60146 #define ISI_CHNL_ROI_1_LRC_X_MASK                (0xFFF0000U)
60147 #define ISI_CHNL_ROI_1_LRC_X_SHIFT               (16U)
60148 /*! X - Lower Right X-coordinate */
60149 #define ISI_CHNL_ROI_1_LRC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK)
60150 /*! @} */
60151 
60152 /*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value Register for Region of Interest 2 */
60153 /*! @{ */
60154 
60155 #define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK       (0x10000U)
60156 #define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT      (16U)
60157 /*! ALPHA_EN - Alpha value insertion enable
60158  *  0b0..Alpha value insertion is disabled
60159  *  0b1..Alpha value insertion is enabled
60160  */
60161 #define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK)
60162 
60163 #define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK          (0xFF000000U)
60164 #define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT         (24U)
60165 /*! ALPHA - Alpha Value to be inserted with image */
60166 #define ISI_CHNL_ROI_2_ALPHA_ALPHA(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK)
60167 /*! @} */
60168 
60169 /*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate Register for Region of Interest 2 */
60170 /*! @{ */
60171 
60172 #define ISI_CHNL_ROI_2_ULC_Y_MASK                (0xFFFU)
60173 #define ISI_CHNL_ROI_2_ULC_Y_SHIFT               (0U)
60174 /*! Y - Upper Left Y-coordinate */
60175 #define ISI_CHNL_ROI_2_ULC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK)
60176 
60177 #define ISI_CHNL_ROI_2_ULC_X_MASK                (0xFFF0000U)
60178 #define ISI_CHNL_ROI_2_ULC_X_SHIFT               (16U)
60179 /*! X - Upper Left X-coordinate */
60180 #define ISI_CHNL_ROI_2_ULC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK)
60181 /*! @} */
60182 
60183 /*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate Register for Region of Interest 2 */
60184 /*! @{ */
60185 
60186 #define ISI_CHNL_ROI_2_LRC_Y_MASK                (0xFFFU)
60187 #define ISI_CHNL_ROI_2_LRC_Y_SHIFT               (0U)
60188 /*! Y - Lower Right Y-coordinate */
60189 #define ISI_CHNL_ROI_2_LRC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK)
60190 
60191 #define ISI_CHNL_ROI_2_LRC_X_MASK                (0xFFF0000U)
60192 #define ISI_CHNL_ROI_2_LRC_X_SHIFT               (16U)
60193 /*! X - Lower Right X-coordinate */
60194 #define ISI_CHNL_ROI_2_LRC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK)
60195 /*! @} */
60196 
60197 /*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value Register for Region of Interest 3 */
60198 /*! @{ */
60199 
60200 #define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK       (0x10000U)
60201 #define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT      (16U)
60202 /*! ALPHA_EN - Alpha value insertion enable
60203  *  0b0..Alpha value insertion is disabled
60204  *  0b1..Alpha value insertion is enabled
60205  */
60206 #define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK)
60207 
60208 #define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK          (0xFF000000U)
60209 #define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT         (24U)
60210 /*! ALPHA - Alpha Value to be inserted with image */
60211 #define ISI_CHNL_ROI_3_ALPHA_ALPHA(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK)
60212 /*! @} */
60213 
60214 /*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate Register for Region of Interest 3 */
60215 /*! @{ */
60216 
60217 #define ISI_CHNL_ROI_3_ULC_Y_MASK                (0xFFFU)
60218 #define ISI_CHNL_ROI_3_ULC_Y_SHIFT               (0U)
60219 /*! Y - Upper Left Y-coordinate */
60220 #define ISI_CHNL_ROI_3_ULC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK)
60221 
60222 #define ISI_CHNL_ROI_3_ULC_X_MASK                (0xFFF0000U)
60223 #define ISI_CHNL_ROI_3_ULC_X_SHIFT               (16U)
60224 /*! X - Upper Left X-coordinate */
60225 #define ISI_CHNL_ROI_3_ULC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK)
60226 /*! @} */
60227 
60228 /*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate Register for Region of Interest 3 */
60229 /*! @{ */
60230 
60231 #define ISI_CHNL_ROI_3_LRC_Y_MASK                (0xFFFU)
60232 #define ISI_CHNL_ROI_3_LRC_Y_SHIFT               (0U)
60233 /*! Y - Lower Right Y-coordinate */
60234 #define ISI_CHNL_ROI_3_LRC_Y(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK)
60235 
60236 #define ISI_CHNL_ROI_3_LRC_X_MASK                (0xFFF0000U)
60237 #define ISI_CHNL_ROI_3_LRC_X_SHIFT               (16U)
60238 /*! X - Lower Right X-coordinate */
60239 #define ISI_CHNL_ROI_3_LRC_X(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK)
60240 /*! @} */
60241 
60242 /*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */
60243 /*! @{ */
60244 
60245 #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
60246 #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT      (0U)
60247 /*! ADDR - Starting address for the RGB or Y (luma) memory location */
60248 #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK)
60249 /*! @} */
60250 
60251 /*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
60252 /*! @{ */
60253 
60254 #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
60255 #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT      (0U)
60256 /*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location */
60257 #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK)
60258 /*! @} */
60259 
60260 /*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */
60261 /*! @{ */
60262 
60263 #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
60264 #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT      (0U)
60265 /*! ADDR - Starting address for the V/Cr memory location */
60266 #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK)
60267 /*! @} */
60268 
60269 /*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */
60270 /*! @{ */
60271 
60272 #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK   (0xFFFFU)
60273 #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT  (0U)
60274 /*! LINE_PITCH - Output Buffer Line Pitch */
60275 #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x)     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK)
60276 /*! @} */
60277 
60278 /*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */
60279 /*! @{ */
60280 
60281 #define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK           (0xFFFFFFFFU)
60282 #define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT          (0U)
60283 #define ISI_CHNL_IN_BUF_ADDR_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK)
60284 /*! @} */
60285 
60286 /*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */
60287 /*! @{ */
60288 
60289 #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK    (0xFFFFU)
60290 #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT   (0U)
60291 /*! LINE_PITCH - Line Pitch */
60292 #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK)
60293 
60294 #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK     (0xFFFF0000U)
60295 #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT    (16U)
60296 /*! FRM_PITCH - Frame Pitch */
60297 #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK)
60298 /*! @} */
60299 
60300 /*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */
60301 /*! @{ */
60302 
60303 #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK       (0x1U)
60304 #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT      (0U)
60305 /*! READ_MEM - Initiate read from memory
60306  *  0b0..No reads from memory done
60307  *  0b1..Reads from memory initiated
60308  */
60309 #define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK)
60310 
60311 #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK       (0xF0000000U)
60312 #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT      (28U)
60313 /*! IMG_TYPE - Input image format
60314  *  0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD)
60315  *  0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD)
60316  *  0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
60317  *  0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD)
60318  *  0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
60319  *  0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD)
60320  *  0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component
60321  *  0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component
60322  *  0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
60323  *  0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
60324  *  0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit WORD)
60325  *  0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
60326  *  0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
60327  *  0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV interleaved packed bytes
60328  *  0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
60329  *  0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved packed bytes (4 MSBs waste bits in 16-bit WORD)
60330  */
60331 #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK)
60332 /*! @} */
60333 
60334 /*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */
60335 /*! @{ */
60336 
60337 #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
60338 #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT      (0U)
60339 /*! ADDR - Starting address for the RGB or Y (luma) memory location */
60340 #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK)
60341 /*! @} */
60342 
60343 /*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
60344 /*! @{ */
60345 
60346 #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
60347 #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT      (0U)
60348 /*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location */
60349 #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK)
60350 /*! @} */
60351 
60352 /*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */
60353 /*! @{ */
60354 
60355 #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
60356 #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT      (0U)
60357 /*! ADDR - Starting address for the V/Cr memory location */
60358 #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK)
60359 /*! @} */
60360 
60361 /*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */
60362 /*! @{ */
60363 
60364 #define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK          (0x1FFFU)
60365 #define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT         (0U)
60366 /*! WIDTH - Scaled image width (pixels) */
60367 #define ISI_CHNL_SCL_IMG_CFG_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK)
60368 
60369 #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK         (0x1FFF0000U)
60370 #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT        (16U)
60371 /*! HEIGHT - Scaled image height (lines) */
60372 #define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK)
60373 /*! @} */
60374 
60375 /*! @name CHNL_FLOW_CTRL - Channel Flow Control Register */
60376 /*! @{ */
60377 
60378 #define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK         (0xFFU)
60379 #define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT        (0U)
60380 /*! FC_DENOM - Denominator value of fraction of usable bandwidth
60381  *  0b00000000..Invalid value. Flow control will be disabled.
60382  */
60383 #define ISI_CHNL_FLOW_CTRL_FC_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK)
60384 
60385 #define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK         (0xFF0000U)
60386 #define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT        (16U)
60387 /*! FC_NUMER - Numertor value of fraction of usable bandwidth
60388  *  0b00000000..Flow control is disabled.
60389  */
60390 #define ISI_CHNL_FLOW_CTRL_FC_NUMER(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK)
60391 /*! @} */
60392 
60393 /*! @name CHNL_Y_BUF1_XTND_ADDR - Channel Output Y-Buffer 1 Extended Address Bits Register */
60394 /*! @{ */
60395 
60396 #define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_MASK (0xFU)
60397 #define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_SHIFT (0U)
60398 /*! Y1ADDR_MSB - Extended Address Most Significant Bits */
60399 #define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_SHIFT)) & ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_MASK)
60400 /*! @} */
60401 
60402 /*! @name CHNL_U_BUF1_XTND_ADDR - Channel Output U-Buffer 1 Extended Address Bits Register */
60403 /*! @{ */
60404 
60405 #define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_MASK (0xFU)
60406 #define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_SHIFT (0U)
60407 /*! U1ADDR_MSB - Extended Address Most Significant Bits */
60408 #define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_SHIFT)) & ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_MASK)
60409 /*! @} */
60410 
60411 /*! @name CHNL_V_BUF1_XTND_ADDR - Channel Output V-Buffer 1 Extended Address Bits Register */
60412 /*! @{ */
60413 
60414 #define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_MASK (0xFU)
60415 #define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_SHIFT (0U)
60416 /*! V1ADDR_MSB - Extended Address Most Significant Bits */
60417 #define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_SHIFT)) & ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_MASK)
60418 /*! @} */
60419 
60420 /*! @name CHNL_Y_BUF2_XTND_ADDR - Channel Output Y-Buffer 2 Extended Address Bits Register */
60421 /*! @{ */
60422 
60423 #define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_MASK (0xFU)
60424 #define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_SHIFT (0U)
60425 /*! Y2ADDR_MSB - Extended Address Most Significant Bits */
60426 #define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_SHIFT)) & ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_MASK)
60427 /*! @} */
60428 
60429 /*! @name CHNL_U_BUF2_XTND_ADDR - Channel Output U-Buffer 2 Extended Address Bits Register */
60430 /*! @{ */
60431 
60432 #define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_MASK (0xFU)
60433 #define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_SHIFT (0U)
60434 /*! U2ADDR_MSB - Extended Address Most Significant Bits */
60435 #define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_SHIFT)) & ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_MASK)
60436 /*! @} */
60437 
60438 /*! @name CHNL_V_BUF2_XTND_ADDR - Channel Output V-Buffer 2 Extended Address Bits Register */
60439 /*! @{ */
60440 
60441 #define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_MASK (0xFU)
60442 #define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_SHIFT (0U)
60443 /*! V2ADDR_MSB - Extended Address Most Significant Bits */
60444 #define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_SHIFT)) & ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_MASK)
60445 /*! @} */
60446 
60447 /*! @name CHNL_IN_BUF_XTND_ADDR - Channel Input Buffer Extended Address Bits Register */
60448 /*! @{ */
60449 
60450 #define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_MASK (0xFU)
60451 #define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_SHIFT (0U)
60452 /*! XADDR_MSB - Extended Address Most Significant Bits */
60453 #define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB(x)   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_SHIFT)) & ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_MASK)
60454 /*! @} */
60455 
60456 
60457 /*!
60458  * @}
60459  */ /* end of group ISI_Register_Masks */
60460 
60461 
60462 /* ISI - Peripheral instance base addresses */
60463 /** Peripheral ISI base address */
60464 #define ISI_BASE                                 (0x32E00000u)
60465 /** Peripheral ISI base pointer */
60466 #define ISI                                      ((ISI_Type *)ISI_BASE)
60467 /** Array initializer of ISI peripheral base addresses */
60468 #define ISI_BASE_ADDRS                           { ISI_BASE }
60469 /** Array initializer of ISI peripheral base pointers */
60470 #define ISI_BASE_PTRS                            { ISI }
60471 
60472 /*!
60473  * @}
60474  */ /* end of group ISI_Peripheral_Access_Layer */
60475 
60476 
60477 /* ----------------------------------------------------------------------------
60478    -- LCDIF Peripheral Access Layer
60479    ---------------------------------------------------------------------------- */
60480 
60481 /*!
60482  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
60483  * @{
60484  */
60485 
60486 /** LCDIF - Register Layout Typedef */
60487 typedef struct {
60488   __IO uint32_t CTRL;                              /**< LCDIF display control Register, offset: 0x0 */
60489   __IO uint32_t CTRL_SET;                          /**< LCDIF display control Register, offset: 0x4 */
60490   __IO uint32_t CTRL_CLR;                          /**< LCDIF display control Register, offset: 0x8 */
60491   __IO uint32_t CTRL_TOG;                          /**< LCDIF display control Register, offset: 0xC */
60492   __IO uint32_t DISP_PARA;                         /**< Display Parameter Register, offset: 0x10 */
60493   __IO uint32_t DISP_SIZE;                         /**< Display Size Register, offset: 0x14 */
60494   __IO uint32_t HSYN_PARA;                         /**< Horizontal Sync Parameter Register, offset: 0x18 */
60495   __IO uint32_t VSYN_PARA;                         /**< Vertical Sync Parameter Register, offset: 0x1C */
60496   __IO uint32_t VSYN_HSYN_WIDTH;                   /**< Vertical and Horizontal Pulse Width Parameter Register, offset: 0x20 */
60497   __IO uint32_t INT_STATUS_D0;                     /**< Interrupt Status Register for domain 0, offset: 0x24 */
60498   __IO uint32_t INT_ENABLE_D0;                     /**< Interrupt Enable Register for domain 0, offset: 0x28 */
60499        uint8_t RESERVED_0[4];
60500   __IO uint32_t INT_STATUS_D1;                     /**< Interrupt Status Register for domain 0, offset: 0x30 */
60501   __IO uint32_t INT_ENABLE_D1;                     /**< Interrupt Enable Register for domain 0, offset: 0x34 */
60502        uint8_t RESERVED_1[456];
60503   __IO uint32_t CTRLDESCL0_1;                      /**< Control Descriptor Layer Register 1, offset: 0x200 */
60504        uint8_t RESERVED_2[4];
60505   __IO uint32_t CTRLDESCL0_3;                      /**< Control Descriptor Layer Register 3, offset: 0x208 */
60506   __IO uint32_t CTRLDESCL_LOW0_4;                  /**< Control Descriptor Layer Register 4, offset: 0x20C */
60507   __IO uint32_t CTRLDESCL_HIGH0_4;                 /**< Control Descriptor Layer Register 4, offset: 0x210 */
60508   __IO uint32_t CTRLDESCL0_5;                      /**< Control Descriptor Layer Register 5, offset: 0x214 */
60509        uint8_t RESERVED_3[4];
60510   __IO uint32_t CSC0_CTRL;                         /**< Color Space Conversion Ctrl Register, offset: 0x21C */
60511   __IO uint32_t CSC0_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x220 */
60512   __IO uint32_t CSC0_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x224 */
60513   __IO uint32_t CSC0_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x228 */
60514   __IO uint32_t CSC0_COEF3;                        /**< Color Space Conversion Coefficient Register 3, offset: 0x22C */
60515   __IO uint32_t CSC0_COEF4;                        /**< Color Space Conversion Coefficient Register 4, offset: 0x230 */
60516   __IO uint32_t CSC0_COEF5;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x234 */
60517   __IO uint32_t PANIC0_THRES;                      /**< Memory request priority threshold register, offset: 0x238 */
60518 } LCDIF_Type;
60519 
60520 /* ----------------------------------------------------------------------------
60521    -- LCDIF Register Masks
60522    ---------------------------------------------------------------------------- */
60523 
60524 /*!
60525  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
60526  * @{
60527  */
60528 
60529 /*! @name CTRL - LCDIF display control Register */
60530 /*! @{ */
60531 
60532 #define LCDIF_CTRL_INV_HS_MASK                   (0x1U)
60533 #define LCDIF_CTRL_INV_HS_SHIFT                  (0U)
60534 /*! INV_HS - Invert Horizontal synchronization signal.
60535  *  0b0..HSYNC signal not inverted (active HIGH).
60536  *  0b1..Invert HSYNC signal (active LOW).
60537  */
60538 #define LCDIF_CTRL_INV_HS(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_HS_SHIFT)) & LCDIF_CTRL_INV_HS_MASK)
60539 
60540 #define LCDIF_CTRL_INV_VS_MASK                   (0x2U)
60541 #define LCDIF_CTRL_INV_VS_SHIFT                  (1U)
60542 /*! INV_VS - Invert Vertical synchronization signal.
60543  *  0b0..VSYNC signal not inverted (active HIGH).
60544  *  0b1..Invert VSYNC signal (active LOW).
60545  */
60546 #define LCDIF_CTRL_INV_VS(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_VS_SHIFT)) & LCDIF_CTRL_INV_VS_MASK)
60547 
60548 #define LCDIF_CTRL_INV_DE_MASK                   (0x4U)
60549 #define LCDIF_CTRL_INV_DE_SHIFT                  (2U)
60550 /*! INV_DE - Invert Data Enable polarity
60551  *  0b0..Data enable is active high
60552  *  0b1..Data enable is active low
60553  */
60554 #define LCDIF_CTRL_INV_DE(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_DE_SHIFT)) & LCDIF_CTRL_INV_DE_MASK)
60555 
60556 #define LCDIF_CTRL_INV_PXCK_MASK                 (0x8U)
60557 #define LCDIF_CTRL_INV_PXCK_SHIFT                (3U)
60558 /*! INV_PXCK - Polarity change of Pixel Clock.
60559  *  0b0..Display samples data on the falling edge
60560  *  0b1..Display samples data on the rising edge
60561  */
60562 #define LCDIF_CTRL_INV_PXCK(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_PXCK_SHIFT)) & LCDIF_CTRL_INV_PXCK_MASK)
60563 
60564 #define LCDIF_CTRL_NEG_MASK                      (0x10U)
60565 #define LCDIF_CTRL_NEG_SHIFT                     (4U)
60566 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
60567  *  0b0..Output is to remain same
60568  *  0b1..Output to be negated
60569  */
60570 #define LCDIF_CTRL_NEG(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_NEG_SHIFT)) & LCDIF_CTRL_NEG_MASK)
60571 
60572 #define LCDIF_CTRL_fetch_start_option_MASK       (0x300U)
60573 #define LCDIF_CTRL_fetch_start_option_SHIFT      (8U)
60574 /*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
60575  *  0b00..fetch start as soon as FPV begins(as the end of the data_enable)
60576  *  0b01..fetch start as soon as PWV begins
60577  *  0b10..fetch start as soon as BPV begins
60578  *  0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
60579  */
60580 #define LCDIF_CTRL_fetch_start_option(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_fetch_start_option_SHIFT)) & LCDIF_CTRL_fetch_start_option_MASK)
60581 
60582 #define LCDIF_CTRL_SW_RESET_MASK                 (0x80000000U)
60583 #define LCDIF_CTRL_SW_RESET_SHIFT                (31U)
60584 /*! SW_RESET - SW_RESET
60585  *  0b0..No action
60586  *  0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
60587  */
60588 #define LCDIF_CTRL_SW_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SW_RESET_SHIFT)) & LCDIF_CTRL_SW_RESET_MASK)
60589 /*! @} */
60590 
60591 /*! @name CTRL_SET - LCDIF display control Register */
60592 /*! @{ */
60593 
60594 #define LCDIF_CTRL_SET_INV_HS_MASK               (0x1U)
60595 #define LCDIF_CTRL_SET_INV_HS_SHIFT              (0U)
60596 /*! INV_HS - Invert Horizontal synchronization signal.
60597  *  0b0..HSYNC signal not inverted (active HIGH).
60598  *  0b1..Invert HSYNC signal (active LOW).
60599  */
60600 #define LCDIF_CTRL_SET_INV_HS(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_HS_SHIFT)) & LCDIF_CTRL_SET_INV_HS_MASK)
60601 
60602 #define LCDIF_CTRL_SET_INV_VS_MASK               (0x2U)
60603 #define LCDIF_CTRL_SET_INV_VS_SHIFT              (1U)
60604 /*! INV_VS - Invert Vertical synchronization signal.
60605  *  0b0..VSYNC signal not inverted (active HIGH).
60606  *  0b1..Invert VSYNC signal (active LOW).
60607  */
60608 #define LCDIF_CTRL_SET_INV_VS(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_VS_SHIFT)) & LCDIF_CTRL_SET_INV_VS_MASK)
60609 
60610 #define LCDIF_CTRL_SET_INV_DE_MASK               (0x4U)
60611 #define LCDIF_CTRL_SET_INV_DE_SHIFT              (2U)
60612 /*! INV_DE - Invert Data Enable polarity
60613  *  0b0..Data enable is active high
60614  *  0b1..Data enable is active low
60615  */
60616 #define LCDIF_CTRL_SET_INV_DE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_DE_SHIFT)) & LCDIF_CTRL_SET_INV_DE_MASK)
60617 
60618 #define LCDIF_CTRL_SET_INV_PXCK_MASK             (0x8U)
60619 #define LCDIF_CTRL_SET_INV_PXCK_SHIFT            (3U)
60620 /*! INV_PXCK - Polarity change of Pixel Clock.
60621  *  0b0..Display samples data on the falling edge
60622  *  0b1..Display samples data on the rising edge
60623  */
60624 #define LCDIF_CTRL_SET_INV_PXCK(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_PXCK_SHIFT)) & LCDIF_CTRL_SET_INV_PXCK_MASK)
60625 
60626 #define LCDIF_CTRL_SET_NEG_MASK                  (0x10U)
60627 #define LCDIF_CTRL_SET_NEG_SHIFT                 (4U)
60628 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
60629  *  0b0..Output is to remain same
60630  *  0b1..Output to be negated
60631  */
60632 #define LCDIF_CTRL_SET_NEG(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_NEG_SHIFT)) & LCDIF_CTRL_SET_NEG_MASK)
60633 
60634 #define LCDIF_CTRL_SET_fetch_start_option_MASK   (0x300U)
60635 #define LCDIF_CTRL_SET_fetch_start_option_SHIFT  (8U)
60636 /*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
60637  *  0b00..fetch start as soon as FPV begins(as the end of the data_enable)
60638  *  0b01..fetch start as soon as PWV begins
60639  *  0b10..fetch start as soon as BPV begins
60640  *  0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
60641  */
60642 #define LCDIF_CTRL_SET_fetch_start_option(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_fetch_start_option_SHIFT)) & LCDIF_CTRL_SET_fetch_start_option_MASK)
60643 
60644 #define LCDIF_CTRL_SET_SW_RESET_MASK             (0x80000000U)
60645 #define LCDIF_CTRL_SET_SW_RESET_SHIFT            (31U)
60646 /*! SW_RESET - SW_RESET
60647  *  0b0..No action
60648  *  0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
60649  */
60650 #define LCDIF_CTRL_SET_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SW_RESET_SHIFT)) & LCDIF_CTRL_SET_SW_RESET_MASK)
60651 /*! @} */
60652 
60653 /*! @name CTRL_CLR - LCDIF display control Register */
60654 /*! @{ */
60655 
60656 #define LCDIF_CTRL_CLR_INV_HS_MASK               (0x1U)
60657 #define LCDIF_CTRL_CLR_INV_HS_SHIFT              (0U)
60658 /*! INV_HS - Invert Horizontal synchronization signal.
60659  *  0b0..HSYNC signal not inverted (active HIGH).
60660  *  0b1..Invert HSYNC signal (active LOW).
60661  */
60662 #define LCDIF_CTRL_CLR_INV_HS(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_HS_SHIFT)) & LCDIF_CTRL_CLR_INV_HS_MASK)
60663 
60664 #define LCDIF_CTRL_CLR_INV_VS_MASK               (0x2U)
60665 #define LCDIF_CTRL_CLR_INV_VS_SHIFT              (1U)
60666 /*! INV_VS - Invert Vertical synchronization signal.
60667  *  0b0..VSYNC signal not inverted (active HIGH).
60668  *  0b1..Invert VSYNC signal (active LOW).
60669  */
60670 #define LCDIF_CTRL_CLR_INV_VS(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_VS_SHIFT)) & LCDIF_CTRL_CLR_INV_VS_MASK)
60671 
60672 #define LCDIF_CTRL_CLR_INV_DE_MASK               (0x4U)
60673 #define LCDIF_CTRL_CLR_INV_DE_SHIFT              (2U)
60674 /*! INV_DE - Invert Data Enable polarity
60675  *  0b0..Data enable is active high
60676  *  0b1..Data enable is active low
60677  */
60678 #define LCDIF_CTRL_CLR_INV_DE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_DE_SHIFT)) & LCDIF_CTRL_CLR_INV_DE_MASK)
60679 
60680 #define LCDIF_CTRL_CLR_INV_PXCK_MASK             (0x8U)
60681 #define LCDIF_CTRL_CLR_INV_PXCK_SHIFT            (3U)
60682 /*! INV_PXCK - Polarity change of Pixel Clock.
60683  *  0b0..Display samples data on the falling edge
60684  *  0b1..Display samples data on the rising edge
60685  */
60686 #define LCDIF_CTRL_CLR_INV_PXCK(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIF_CTRL_CLR_INV_PXCK_MASK)
60687 
60688 #define LCDIF_CTRL_CLR_NEG_MASK                  (0x10U)
60689 #define LCDIF_CTRL_CLR_NEG_SHIFT                 (4U)
60690 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
60691  *  0b0..Output is to remain same
60692  *  0b1..Output to be negated
60693  */
60694 #define LCDIF_CTRL_CLR_NEG(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_NEG_SHIFT)) & LCDIF_CTRL_CLR_NEG_MASK)
60695 
60696 #define LCDIF_CTRL_CLR_fetch_start_option_MASK   (0x300U)
60697 #define LCDIF_CTRL_CLR_fetch_start_option_SHIFT  (8U)
60698 /*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
60699  *  0b00..fetch start as soon as FPV begins(as the end of the data_enable)
60700  *  0b01..fetch start as soon as PWV begins
60701  *  0b10..fetch start as soon as BPV begins
60702  *  0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
60703  */
60704 #define LCDIF_CTRL_CLR_fetch_start_option(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_fetch_start_option_SHIFT)) & LCDIF_CTRL_CLR_fetch_start_option_MASK)
60705 
60706 #define LCDIF_CTRL_CLR_SW_RESET_MASK             (0x80000000U)
60707 #define LCDIF_CTRL_CLR_SW_RESET_SHIFT            (31U)
60708 /*! SW_RESET - SW_RESET
60709  *  0b0..No action
60710  *  0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
60711  */
60712 #define LCDIF_CTRL_CLR_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SW_RESET_SHIFT)) & LCDIF_CTRL_CLR_SW_RESET_MASK)
60713 /*! @} */
60714 
60715 /*! @name CTRL_TOG - LCDIF display control Register */
60716 /*! @{ */
60717 
60718 #define LCDIF_CTRL_TOG_INV_HS_MASK               (0x1U)
60719 #define LCDIF_CTRL_TOG_INV_HS_SHIFT              (0U)
60720 /*! INV_HS - Invert Horizontal synchronization signal.
60721  *  0b0..HSYNC signal not inverted (active HIGH).
60722  *  0b1..Invert HSYNC signal (active LOW).
60723  */
60724 #define LCDIF_CTRL_TOG_INV_HS(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_HS_SHIFT)) & LCDIF_CTRL_TOG_INV_HS_MASK)
60725 
60726 #define LCDIF_CTRL_TOG_INV_VS_MASK               (0x2U)
60727 #define LCDIF_CTRL_TOG_INV_VS_SHIFT              (1U)
60728 /*! INV_VS - Invert Vertical synchronization signal.
60729  *  0b0..VSYNC signal not inverted (active HIGH).
60730  *  0b1..Invert VSYNC signal (active LOW).
60731  */
60732 #define LCDIF_CTRL_TOG_INV_VS(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_VS_SHIFT)) & LCDIF_CTRL_TOG_INV_VS_MASK)
60733 
60734 #define LCDIF_CTRL_TOG_INV_DE_MASK               (0x4U)
60735 #define LCDIF_CTRL_TOG_INV_DE_SHIFT              (2U)
60736 /*! INV_DE - Invert Data Enable polarity
60737  *  0b0..Data enable is active high
60738  *  0b1..Data enable is active low
60739  */
60740 #define LCDIF_CTRL_TOG_INV_DE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_DE_SHIFT)) & LCDIF_CTRL_TOG_INV_DE_MASK)
60741 
60742 #define LCDIF_CTRL_TOG_INV_PXCK_MASK             (0x8U)
60743 #define LCDIF_CTRL_TOG_INV_PXCK_SHIFT            (3U)
60744 /*! INV_PXCK - Polarity change of Pixel Clock.
60745  *  0b0..Display samples data on the falling edge
60746  *  0b1..Display samples data on the rising edge
60747  */
60748 #define LCDIF_CTRL_TOG_INV_PXCK(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIF_CTRL_TOG_INV_PXCK_MASK)
60749 
60750 #define LCDIF_CTRL_TOG_NEG_MASK                  (0x10U)
60751 #define LCDIF_CTRL_TOG_NEG_SHIFT                 (4U)
60752 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
60753  *  0b0..Output is to remain same
60754  *  0b1..Output to be negated
60755  */
60756 #define LCDIF_CTRL_TOG_NEG(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_NEG_SHIFT)) & LCDIF_CTRL_TOG_NEG_MASK)
60757 
60758 #define LCDIF_CTRL_TOG_fetch_start_option_MASK   (0x300U)
60759 #define LCDIF_CTRL_TOG_fetch_start_option_SHIFT  (8U)
60760 /*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
60761  *  0b00..fetch start as soon as FPV begins(as the end of the data_enable)
60762  *  0b01..fetch start as soon as PWV begins
60763  *  0b10..fetch start as soon as BPV begins
60764  *  0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
60765  */
60766 #define LCDIF_CTRL_TOG_fetch_start_option(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_fetch_start_option_SHIFT)) & LCDIF_CTRL_TOG_fetch_start_option_MASK)
60767 
60768 #define LCDIF_CTRL_TOG_SW_RESET_MASK             (0x80000000U)
60769 #define LCDIF_CTRL_TOG_SW_RESET_SHIFT            (31U)
60770 /*! SW_RESET - SW_RESET
60771  *  0b0..No action
60772  *  0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
60773  */
60774 #define LCDIF_CTRL_TOG_SW_RESET(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SW_RESET_SHIFT)) & LCDIF_CTRL_TOG_SW_RESET_MASK)
60775 /*! @} */
60776 
60777 /*! @name DISP_PARA - Display Parameter Register */
60778 /*! @{ */
60779 
60780 #define LCDIF_DISP_PARA_BGND_B_MASK              (0xFFU)
60781 #define LCDIF_DISP_PARA_BGND_B_SHIFT             (0U)
60782 /*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active. */
60783 #define LCDIF_DISP_PARA_BGND_B(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_B_SHIFT)) & LCDIF_DISP_PARA_BGND_B_MASK)
60784 
60785 #define LCDIF_DISP_PARA_BGND_G_MASK              (0xFF00U)
60786 #define LCDIF_DISP_PARA_BGND_G_SHIFT             (8U)
60787 /*! BGND_G - Green component of the default color displayed in the sectors where no layer is active. */
60788 #define LCDIF_DISP_PARA_BGND_G(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_G_SHIFT)) & LCDIF_DISP_PARA_BGND_G_MASK)
60789 
60790 #define LCDIF_DISP_PARA_BGND_R_MASK              (0xFF0000U)
60791 #define LCDIF_DISP_PARA_BGND_R_SHIFT             (16U)
60792 /*! BGND_R - Red component of the default color displayed in the sectors where no layer is active. */
60793 #define LCDIF_DISP_PARA_BGND_R(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_R_SHIFT)) & LCDIF_DISP_PARA_BGND_R_MASK)
60794 
60795 #define LCDIF_DISP_PARA_DISP_MODE_MASK           (0x3000000U)
60796 #define LCDIF_DISP_PARA_DISP_MODE_SHIFT          (24U)
60797 /*! DISP_MODE - LCDIF operating mode.
60798  *  0b00..Normal mode. Panel content controlled by layer configuration.
60799  *  0b01..Test Mode1.(BGND Color Display)
60800  *  0b10..Test Mode2.(Column Color Bar)
60801  *  0b11..Test Mode3.(Row Color Bar)
60802  */
60803 #define LCDIF_DISP_PARA_DISP_MODE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_MODE_SHIFT)) & LCDIF_DISP_PARA_DISP_MODE_MASK)
60804 
60805 #define LCDIF_DISP_PARA_LINE_PATTERN_MASK        (0x3C000000U)
60806 #define LCDIF_DISP_PARA_LINE_PATTERN_SHIFT       (26U)
60807 /*! LINE_PATTERN - LCDIF line output order.
60808  *  0b0000..RGB/YUV.
60809  *  0b0001..RBG.
60810  *  0b0010..GBR.
60811  *  0b0011..GRB/UYV.
60812  *  0b0100..BRG.
60813  *  0b0101..BGR.
60814  *  0b0110..RGB555.
60815  *  0b0111..RGB565.
60816  *  0b1000..YUYV at [16:0].
60817  *  0b1001..UYVY at [16:0].
60818  *  0b1010..YVYU at [16:0].
60819  *  0b1011..YUYV at [16:0].
60820  *  0b1100..YUYV at [23:8].
60821  *  0b1101..UYVY at [23:8].
60822  *  0b1110..YVYU at [23:8].
60823  *  0b1111..YUYV at [23:8].
60824  */
60825 #define LCDIF_DISP_PARA_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIF_DISP_PARA_LINE_PATTERN_MASK)
60826 
60827 #define LCDIF_DISP_PARA_SWAP_EN_MASK             (0x40000000U)
60828 #define LCDIF_DISP_PARA_SWAP_EN_SHIFT            (30U)
60829 /*! SWAP_EN - output data swap enable.
60830  *  0b0..swap disable
60831  *  0b1..swap enbale, output data will swap the high 16bits with the low 16bits.
60832  */
60833 #define LCDIF_DISP_PARA_SWAP_EN(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_SWAP_EN_SHIFT)) & LCDIF_DISP_PARA_SWAP_EN_MASK)
60834 
60835 #define LCDIF_DISP_PARA_DISP_ON_MASK             (0x80000000U)
60836 #define LCDIF_DISP_PARA_DISP_ON_SHIFT            (31U)
60837 /*! DISP_ON - Display panel On/Off mode.
60838  *  0b0..Display Off.
60839  *  0b1..Display On.
60840  */
60841 #define LCDIF_DISP_PARA_DISP_ON(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_ON_SHIFT)) & LCDIF_DISP_PARA_DISP_ON_MASK)
60842 /*! @} */
60843 
60844 /*! @name DISP_SIZE - Display Size Register */
60845 /*! @{ */
60846 
60847 #define LCDIF_DISP_SIZE_DELTA_X_MASK             (0xFFFFU)
60848 #define LCDIF_DISP_SIZE_DELTA_X_SHIFT            (0U)
60849 /*! DELTA_X - Sets the display size horizontal resolution in pixels. */
60850 #define LCDIF_DISP_SIZE_DELTA_X(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_X_SHIFT)) & LCDIF_DISP_SIZE_DELTA_X_MASK)
60851 
60852 #define LCDIF_DISP_SIZE_DELTA_Y_MASK             (0xFFFF0000U)
60853 #define LCDIF_DISP_SIZE_DELTA_Y_SHIFT            (16U)
60854 /*! DELTA_Y - Sets the display size vertical resolution in pixels. */
60855 #define LCDIF_DISP_SIZE_DELTA_Y(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIF_DISP_SIZE_DELTA_Y_MASK)
60856 /*! @} */
60857 
60858 /*! @name HSYN_PARA - Horizontal Sync Parameter Register */
60859 /*! @{ */
60860 
60861 #define LCDIF_HSYN_PARA_FP_H_MASK                (0xFFFFU)
60862 #define LCDIF_HSYN_PARA_FP_H_SHIFT               (0U)
60863 /*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */
60864 #define LCDIF_HSYN_PARA_FP_H(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_FP_H_SHIFT)) & LCDIF_HSYN_PARA_FP_H_MASK)
60865 
60866 #define LCDIF_HSYN_PARA_BP_H_MASK                (0xFFFF0000U)
60867 #define LCDIF_HSYN_PARA_BP_H_SHIFT               (16U)
60868 /*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */
60869 #define LCDIF_HSYN_PARA_BP_H(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_BP_H_SHIFT)) & LCDIF_HSYN_PARA_BP_H_MASK)
60870 /*! @} */
60871 
60872 /*! @name VSYN_PARA - Vertical Sync Parameter Register */
60873 /*! @{ */
60874 
60875 #define LCDIF_VSYN_PARA_FP_V_MASK                (0xFFFFU)
60876 #define LCDIF_VSYN_PARA_FP_V_SHIFT               (0U)
60877 /*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */
60878 #define LCDIF_VSYN_PARA_FP_V(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_FP_V_SHIFT)) & LCDIF_VSYN_PARA_FP_V_MASK)
60879 
60880 #define LCDIF_VSYN_PARA_BP_V_MASK                (0xFFFF0000U)
60881 #define LCDIF_VSYN_PARA_BP_V_SHIFT               (16U)
60882 /*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */
60883 #define LCDIF_VSYN_PARA_BP_V(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_BP_V_SHIFT)) & LCDIF_VSYN_PARA_BP_V_MASK)
60884 /*! @} */
60885 
60886 /*! @name VSYN_HSYN_WIDTH - Vertical and Horizontal Pulse Width Parameter Register */
60887 /*! @{ */
60888 
60889 #define LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK          (0xFFFFU)
60890 #define LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT         (0U)
60891 /*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */
60892 #define LCDIF_VSYN_HSYN_WIDTH_PW_H(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK)
60893 
60894 #define LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK          (0xFFFF0000U)
60895 #define LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT         (16U)
60896 /*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */
60897 #define LCDIF_VSYN_HSYN_WIDTH_PW_V(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK)
60898 /*! @} */
60899 
60900 /*! @name INT_STATUS_D0 - Interrupt Status Register for domain 0 */
60901 /*! @{ */
60902 
60903 #define LCDIF_INT_STATUS_D0_VSYNC_MASK           (0x1U)
60904 #define LCDIF_INT_STATUS_D0_VSYNC_SHIFT          (0U)
60905 /*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame). */
60906 #define LCDIF_INT_STATUS_D0_VSYNC(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VSYNC_SHIFT)) & LCDIF_INT_STATUS_D0_VSYNC_MASK)
60907 
60908 #define LCDIF_INT_STATUS_D0_UNDERRUN_MASK        (0x2U)
60909 #define LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT       (1U)
60910 /*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition. */
60911 #define LCDIF_INT_STATUS_D0_UNDERRUN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT)) & LCDIF_INT_STATUS_D0_UNDERRUN_MASK)
60912 
60913 #define LCDIF_INT_STATUS_D0_VS_BLANK_MASK        (0x4U)
60914 #define LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT       (2U)
60915 /*! VS_BLANK - Interrupt flag to indicate vertical blanking period. */
60916 #define LCDIF_INT_STATUS_D0_VS_BLANK(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT)) & LCDIF_INT_STATUS_D0_VS_BLANK_MASK)
60917 
60918 #define LCDIF_INT_STATUS_D0_DMA_ERR_MASK         (0x100U)
60919 #define LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT        (8U)
60920 /*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. */
60921 #define LCDIF_INT_STATUS_D0_DMA_ERR(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_ERR_MASK)
60922 
60923 #define LCDIF_INT_STATUS_D0_DMA_DONE_MASK        (0x10000U)
60924 #define LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT       (16U)
60925 /*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. */
60926 #define LCDIF_INT_STATUS_D0_DMA_DONE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_DONE_MASK)
60927 
60928 #define LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK      (0x1000000U)
60929 #define LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT     (24U)
60930 /*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */
60931 #define LCDIF_INT_STATUS_D0_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT)) & LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK)
60932 /*! @} */
60933 
60934 /*! @name INT_ENABLE_D0 - Interrupt Enable Register for domain 0 */
60935 /*! @{ */
60936 
60937 #define LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK        (0x1U)
60938 #define LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT       (0U)
60939 /*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame). */
60940 #define LCDIF_INT_ENABLE_D0_VSYNC_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK)
60941 
60942 #define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK     (0x2U)
60943 #define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT    (1U)
60944 /*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition. */
60945 #define LCDIF_INT_ENABLE_D0_UNDERRUN_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK)
60946 
60947 #define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK     (0x4U)
60948 #define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT    (2U)
60949 /*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period. */
60950 #define LCDIF_INT_ENABLE_D0_VS_BLANK_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK)
60951 
60952 #define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK      (0x100U)
60953 #define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT     (8U)
60954 /*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. */
60955 #define LCDIF_INT_ENABLE_D0_DMA_ERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK)
60956 
60957 #define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK     (0x10000U)
60958 #define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT    (16U)
60959 /*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. */
60960 #define LCDIF_INT_ENABLE_D0_DMA_DONE_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK)
60961 
60962 #define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK   (0x1000000U)
60963 #define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT  (24U)
60964 /*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */
60965 #define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK)
60966 /*! @} */
60967 
60968 /*! @name INT_STATUS_D1 - Interrupt Status Register for domain 0 */
60969 /*! @{ */
60970 
60971 #define LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK     (0x1U)
60972 #define LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT    (0U)
60973 /*! PLANE_PANIC - plane panic to indicate that which FIFO reaches the panic threshold. */
60974 #define LCDIF_INT_STATUS_D1_PLANE_PANIC(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT)) & LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK)
60975 /*! @} */
60976 
60977 /*! @name INT_ENABLE_D1 - Interrupt Enable Register for domain 0 */
60978 /*! @{ */
60979 
60980 #define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK  (0x1U)
60981 #define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT (0U)
60982 /*! PLANE_PANIC_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */
60983 #define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT)) & LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK)
60984 /*! @} */
60985 
60986 /*! @name CTRLDESCL0_1 - Control Descriptor Layer Register 1 */
60987 /*! @{ */
60988 
60989 #define LCDIF_CTRLDESCL0_1_WIDTH_MASK            (0xFFFFU)
60990 #define LCDIF_CTRLDESCL0_1_WIDTH_SHIFT           (0U)
60991 /*! WIDTH - Width of the layer in pixels. */
60992 #define LCDIF_CTRLDESCL0_1_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_1_WIDTH_SHIFT)) & LCDIF_CTRLDESCL0_1_WIDTH_MASK)
60993 
60994 #define LCDIF_CTRLDESCL0_1_HEIGHT_MASK           (0xFFFF0000U)
60995 #define LCDIF_CTRLDESCL0_1_HEIGHT_SHIFT          (16U)
60996 /*! HEIGHT - Height of the layer in pixels. */
60997 #define LCDIF_CTRLDESCL0_1_HEIGHT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_1_HEIGHT_SHIFT)) & LCDIF_CTRLDESCL0_1_HEIGHT_MASK)
60998 /*! @} */
60999 
61000 /*! @name CTRLDESCL0_3 - Control Descriptor Layer Register 3 */
61001 /*! @{ */
61002 
61003 #define LCDIF_CTRLDESCL0_3_PITCH_MASK            (0xFFFFU)
61004 #define LCDIF_CTRLDESCL0_3_PITCH_SHIFT           (0U)
61005 /*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity
61006  *    is supported, but SW should align to 64B boundry.
61007  */
61008 #define LCDIF_CTRLDESCL0_3_PITCH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_3_PITCH_SHIFT)) & LCDIF_CTRLDESCL0_3_PITCH_MASK)
61009 /*! @} */
61010 
61011 /*! @name CTRLDESCL_LOW0_4 - Control Descriptor Layer Register 4 */
61012 /*! @{ */
61013 
61014 #define LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_MASK     (0xFFFFFFFFU)
61015 #define LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_SHIFT    (0U)
61016 /*! ADDR_LOW - Address of layer data in the memory. The address programmed should be 64-bit aligned. */
61017 #define LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_SHIFT)) & LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_MASK)
61018 /*! @} */
61019 
61020 /*! @name CTRLDESCL_HIGH0_4 - Control Descriptor Layer Register 4 */
61021 /*! @{ */
61022 
61023 #define LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK   (0xFU)
61024 #define LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_SHIFT  (0U)
61025 /*! ADDR_HIGH - Address of layer data in the memory. The address programmed should be 64-bit aligned. */
61026 #define LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_SHIFT)) & LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK)
61027 /*! @} */
61028 
61029 /*! @name CTRLDESCL0_5 - Control Descriptor Layer Register 5 */
61030 /*! @{ */
61031 
61032 #define LCDIF_CTRLDESCL0_5_YUV_FORMAT_MASK       (0xC000U)
61033 #define LCDIF_CTRLDESCL0_5_YUV_FORMAT_SHIFT      (14U)
61034 /*! YUV_FORMAT - The YUV422 input format selection.
61035  *  0b00..The YUV422 32bit memory is {Y2,V1,Y1,U1}
61036  *  0b01..The YUV422 32bit memory is {Y2,U1,Y1,V1}
61037  *  0b10..The YUV422 32bit memory is {V1,Y2,U1,Y1}
61038  *  0b11..The YUV422 32bit memory is {U1,Y2,V1,Y1}
61039  */
61040 #define LCDIF_CTRLDESCL0_5_YUV_FORMAT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_YUV_FORMAT_SHIFT)) & LCDIF_CTRLDESCL0_5_YUV_FORMAT_MASK)
61041 
61042 #define LCDIF_CTRLDESCL0_5_BPP_MASK              (0xF000000U)
61043 #define LCDIF_CTRLDESCL0_5_BPP_SHIFT             (24U)
61044 /*! BPP - Layer encoding format (bit per pixel)
61045  *  0b0100..16 bpp (RGB565)
61046  *  0b0101..16 bpp (ARGB1555)
61047  *  0b0110..16 bpp (ARGB4444)
61048  *  0b0111..YCbCr422
61049  *  0b1000..24 bpp (RGB888)
61050  *  0b1001..32 bpp (ARGB8888)
61051  *  0b1010..32 bpp (ABGR8888)
61052  */
61053 #define LCDIF_CTRLDESCL0_5_BPP(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_BPP_SHIFT)) & LCDIF_CTRLDESCL0_5_BPP_MASK)
61054 
61055 #define LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_MASK   (0x40000000U)
61056 #define LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_SHIFT  (30U)
61057 /*! SHADOW_LOAD_EN - Shadow Load Enable */
61058 #define LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_SHIFT)) & LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_MASK)
61059 
61060 #define LCDIF_CTRLDESCL0_5_EN_MASK               (0x80000000U)
61061 #define LCDIF_CTRLDESCL0_5_EN_SHIFT              (31U)
61062 /*! EN - Enable the layer for DMA.
61063  *  0b0..OFF
61064  *  0b1..ON
61065  */
61066 #define LCDIF_CTRLDESCL0_5_EN(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_EN_SHIFT)) & LCDIF_CTRLDESCL0_5_EN_MASK)
61067 /*! @} */
61068 
61069 /*! @name CSC0_CTRL - Color Space Conversion Ctrl Register */
61070 /*! @{ */
61071 
61072 #define LCDIF_CSC0_CTRL_BYPASS_MASK              (0x1U)
61073 #define LCDIF_CSC0_CTRL_BYPASS_SHIFT             (0U)
61074 /*! BYPASS - This bit controls whether the pixels entering the CSC2 unit get converted or not. When
61075  *    BYPASS is set, no operations occur on the pixels. When BYPASS is cleared, the selected CSC
61076  *    operation takes place.
61077  */
61078 #define LCDIF_CSC0_CTRL_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_CTRL_BYPASS_SHIFT)) & LCDIF_CSC0_CTRL_BYPASS_MASK)
61079 
61080 #define LCDIF_CSC0_CTRL_CSC_MODE_MASK            (0x6U)
61081 #define LCDIF_CSC0_CTRL_CSC_MODE_SHIFT           (1U)
61082 /*! CSC_MODE - This field controls how the CSC unit operates on pixels when the CSC is not bypassed.
61083  *    0x0 YUV2RGB--Convert from YUV to RGB. 0x1 YCbCr2RGB-- Convert from YCbCr to RGB. 0x2 RGB2YUV
61084  *    -- Convert from RGB to YUV. 0x3 RGB2YCbCr -- Convert from RGB to YCbCr.
61085  */
61086 #define LCDIF_CSC0_CTRL_CSC_MODE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_CTRL_CSC_MODE_SHIFT)) & LCDIF_CSC0_CTRL_CSC_MODE_MASK)
61087 /*! @} */
61088 
61089 /*! @name CSC0_COEF0 - Color Space Conversion Coefficient Register 0 */
61090 /*! @{ */
61091 
61092 #define LCDIF_CSC0_COEF0_A1_MASK                 (0x7FFU)
61093 #define LCDIF_CSC0_COEF0_A1_SHIFT                (0U)
61094 /*! A1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61095  *    bits of fraction as ###.####_####.
61096  */
61097 #define LCDIF_CSC0_COEF0_A1(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF0_A1_SHIFT)) & LCDIF_CSC0_COEF0_A1_MASK)
61098 
61099 #define LCDIF_CSC0_COEF0_A2_MASK                 (0x7FF0000U)
61100 #define LCDIF_CSC0_COEF0_A2_SHIFT                (16U)
61101 /*! A2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61102  *    bits of fraction as ###.####_####.
61103  */
61104 #define LCDIF_CSC0_COEF0_A2(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF0_A2_SHIFT)) & LCDIF_CSC0_COEF0_A2_MASK)
61105 /*! @} */
61106 
61107 /*! @name CSC0_COEF1 - Color Space Conversion Coefficient Register 1 */
61108 /*! @{ */
61109 
61110 #define LCDIF_CSC0_COEF1_A3_MASK                 (0x7FFU)
61111 #define LCDIF_CSC0_COEF1_A3_SHIFT                (0U)
61112 /*! A3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61113  *    bits of fraction as ###.####_####.
61114  */
61115 #define LCDIF_CSC0_COEF1_A3(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF1_A3_SHIFT)) & LCDIF_CSC0_COEF1_A3_MASK)
61116 
61117 #define LCDIF_CSC0_COEF1_B1_MASK                 (0x7FF0000U)
61118 #define LCDIF_CSC0_COEF1_B1_SHIFT                (16U)
61119 /*! B1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61120  *    bits of fraction as ###.####_####.
61121  */
61122 #define LCDIF_CSC0_COEF1_B1(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF1_B1_SHIFT)) & LCDIF_CSC0_COEF1_B1_MASK)
61123 /*! @} */
61124 
61125 /*! @name CSC0_COEF2 - Color Space Conversion Coefficient Register 2 */
61126 /*! @{ */
61127 
61128 #define LCDIF_CSC0_COEF2_B2_MASK                 (0x7FFU)
61129 #define LCDIF_CSC0_COEF2_B2_SHIFT                (0U)
61130 /*! B2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61131  *    bits of fraction as ###.####_####.
61132  */
61133 #define LCDIF_CSC0_COEF2_B2(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF2_B2_SHIFT)) & LCDIF_CSC0_COEF2_B2_MASK)
61134 
61135 #define LCDIF_CSC0_COEF2_B3_MASK                 (0x7FF0000U)
61136 #define LCDIF_CSC0_COEF2_B3_SHIFT                (16U)
61137 /*! B3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61138  *    bits of fraction as ###.####_####.
61139  */
61140 #define LCDIF_CSC0_COEF2_B3(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF2_B3_SHIFT)) & LCDIF_CSC0_COEF2_B3_MASK)
61141 /*! @} */
61142 
61143 /*! @name CSC0_COEF3 - Color Space Conversion Coefficient Register 3 */
61144 /*! @{ */
61145 
61146 #define LCDIF_CSC0_COEF3_C1_MASK                 (0x7FFU)
61147 #define LCDIF_CSC0_COEF3_C1_SHIFT                (0U)
61148 /*! C1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61149  *    bits of fraction as ###.####_####.
61150  */
61151 #define LCDIF_CSC0_COEF3_C1(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF3_C1_SHIFT)) & LCDIF_CSC0_COEF3_C1_MASK)
61152 
61153 #define LCDIF_CSC0_COEF3_C2_MASK                 (0x7FF0000U)
61154 #define LCDIF_CSC0_COEF3_C2_SHIFT                (16U)
61155 /*! C2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61156  *    bits of fraction as ###.####_####.
61157  */
61158 #define LCDIF_CSC0_COEF3_C2(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF3_C2_SHIFT)) & LCDIF_CSC0_COEF3_C2_MASK)
61159 /*! @} */
61160 
61161 /*! @name CSC0_COEF4 - Color Space Conversion Coefficient Register 4 */
61162 /*! @{ */
61163 
61164 #define LCDIF_CSC0_COEF4_C3_MASK                 (0x7FFU)
61165 #define LCDIF_CSC0_COEF4_C3_SHIFT                (0U)
61166 /*! C3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
61167  *    bits of fraction as ###.####_####.
61168  */
61169 #define LCDIF_CSC0_COEF4_C3(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF4_C3_SHIFT)) & LCDIF_CSC0_COEF4_C3_MASK)
61170 
61171 #define LCDIF_CSC0_COEF4_D1_MASK                 (0x1FF0000U)
61172 #define LCDIF_CSC0_COEF4_D1_SHIFT                (16U)
61173 /*! D1 - Two's complement D1 coefficient integer offset to be added. */
61174 #define LCDIF_CSC0_COEF4_D1(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF4_D1_SHIFT)) & LCDIF_CSC0_COEF4_D1_MASK)
61175 /*! @} */
61176 
61177 /*! @name CSC0_COEF5 - Color Space Conversion Coefficient Register 0 */
61178 /*! @{ */
61179 
61180 #define LCDIF_CSC0_COEF5_D2_MASK                 (0x1FFU)
61181 #define LCDIF_CSC0_COEF5_D2_SHIFT                (0U)
61182 /*! D2 - Two's complement D2 coefficient integer offset to be added. */
61183 #define LCDIF_CSC0_COEF5_D2(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF5_D2_SHIFT)) & LCDIF_CSC0_COEF5_D2_MASK)
61184 
61185 #define LCDIF_CSC0_COEF5_D3_MASK                 (0x1FF0000U)
61186 #define LCDIF_CSC0_COEF5_D3_SHIFT                (16U)
61187 /*! D3 - Two's complement D3 coefficient integer offset to be added. */
61188 #define LCDIF_CSC0_COEF5_D3(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF5_D3_SHIFT)) & LCDIF_CSC0_COEF5_D3_MASK)
61189 /*! @} */
61190 
61191 /*! @name PANIC0_THRES - Memory request priority threshold register */
61192 /*! @{ */
61193 
61194 #define LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_MASK (0x1FFU)
61195 #define LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_SHIFT (0U)
61196 /*! PANIC_THRES_HIGH - This value should be set to a value of pixels, from (0+1)*128bits to
61197  *    (511+1)*128bits. When the number of pixels in the input pixel FIFO is more than this value, the panic
61198  *    control output will be removed.This signal can be used to raise the access LCDIF's access
61199  *    priority.
61200  */
61201 #define LCDIF_PANIC0_THRES_PANIC_THRES_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_SHIFT)) & LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_MASK)
61202 
61203 #define LCDIF_PANIC0_THRES_PANIC_THRES_LOW_MASK  (0x1FF0000U)
61204 #define LCDIF_PANIC0_THRES_PANIC_THRES_LOW_SHIFT (16U)
61205 /*! PANIC_THRES_LOW - This value should be set to a value of pixels, from (0+1)*128bits to
61206  *    (511+1)*128bits. When the number of pixels in the input pixel FIFO is less than this value, the panic
61207  *    control output will be raised.This signal can be used to raise the access LCDIF's access
61208  *    priority.
61209  */
61210 #define LCDIF_PANIC0_THRES_PANIC_THRES_LOW(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC0_THRES_PANIC_THRES_LOW_SHIFT)) & LCDIF_PANIC0_THRES_PANIC_THRES_LOW_MASK)
61211 /*! @} */
61212 
61213 
61214 /*!
61215  * @}
61216  */ /* end of group LCDIF_Register_Masks */
61217 
61218 
61219 /* LCDIF - Peripheral instance base addresses */
61220 /** Peripheral LCDIF1 base address */
61221 #define LCDIF1_BASE                              (0x32E80000u)
61222 /** Peripheral LCDIF1 base pointer */
61223 #define LCDIF1                                   ((LCDIF_Type *)LCDIF1_BASE)
61224 /** Peripheral LCDIF2 base address */
61225 #define LCDIF2_BASE                              (0x32E90000u)
61226 /** Peripheral LCDIF2 base pointer */
61227 #define LCDIF2                                   ((LCDIF_Type *)LCDIF2_BASE)
61228 /** Peripheral LCDIF3 base address */
61229 #define LCDIF3_BASE                              (0x32FC6000u)
61230 /** Peripheral LCDIF3 base pointer */
61231 #define LCDIF3                                   ((LCDIF_Type *)LCDIF3_BASE)
61232 /** Array initializer of LCDIF peripheral base addresses */
61233 #define LCDIF_BASE_ADDRS                         { LCDIF1_BASE, LCDIF2_BASE, LCDIF3_BASE }
61234 /** Array initializer of LCDIF peripheral base pointers */
61235 #define LCDIF_BASE_PTRS                          { LCDIF1, LCDIF2, LCDIF3 }
61236 
61237 /*!
61238  * @}
61239  */ /* end of group LCDIF_Peripheral_Access_Layer */
61240 
61241 
61242 /* ----------------------------------------------------------------------------
61243    -- MAINCONTROLLER Peripheral Access Layer
61244    ---------------------------------------------------------------------------- */
61245 
61246 /*!
61247  * @addtogroup MAINCONTROLLER_Peripheral_Access_Layer MAINCONTROLLER Peripheral Access Layer
61248  * @{
61249  */
61250 
61251 /** MAINCONTROLLER - Register Layout Typedef */
61252 typedef struct {
61253        uint8_t RESERVED_0[1];
61254   __IO uint8_t MC_CLKDIS;                          /**< Main Controller Synchronous Clock Domain Disable Register, offset: 0x1 */
61255   __IO uint8_t MC_SWRSTZREQ_1;                     /**< Main Controller Software Reset Register Main controller software reset request per clock domain., offset: 0x2 */
61256   __IO uint8_t MC_OPCTRL;                          /**< Main Controller HDCP Bypass Control Register, offset: 0x3 */
61257   __IO uint8_t MC_FLOWCTRL;                        /**< Main Controller Feed Through Control Register, offset: 0x4 */
61258   __IO uint8_t MC_PHYRSTZ;                         /**< Main Controller PHY Reset Register, offset: 0x5 */
61259   __IO uint8_t MC_LOCKONCLOCK_1;                   /**< Main Controller Clock Present Register, offset: 0x6 */
61260 } MAINCONTROLLER_Type;
61261 
61262 /* ----------------------------------------------------------------------------
61263    -- MAINCONTROLLER Register Masks
61264    ---------------------------------------------------------------------------- */
61265 
61266 /*!
61267  * @addtogroup MAINCONTROLLER_Register_Masks MAINCONTROLLER Register Masks
61268  * @{
61269  */
61270 
61271 /*! @name MC_CLKDIS - Main Controller Synchronous Clock Domain Disable Register */
61272 /*! @{ */
61273 
61274 #define MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_MASK (0x1U)
61275 #define MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_SHIFT (0U)
61276 /*! pixelclk_disable - Pixel clock synchronous disable signal. */
61277 #define MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_MASK)
61278 
61279 #define MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_MASK (0x2U)
61280 #define MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_SHIFT (1U)
61281 /*! tmdsclk_disable - TMDS clock synchronous disable signal. */
61282 #define MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_MASK)
61283 
61284 #define MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_MASK (0x4U)
61285 #define MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_SHIFT (2U)
61286 /*! prepclk_disable - Pixel Repetition clock synchronous disable signal. */
61287 #define MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_MASK)
61288 
61289 #define MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_MASK (0x8U)
61290 #define MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_SHIFT (3U)
61291 /*! audclk_disable - Audio Sampler clock synchronous disable signal. */
61292 #define MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_MASK)
61293 
61294 #define MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_MASK (0x10U)
61295 #define MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_SHIFT (4U)
61296 /*! cscclk_disable - Color Space Converter clock synchronous disable signal. */
61297 #define MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_MASK)
61298 
61299 #define MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_MASK (0x20U)
61300 #define MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_SHIFT (5U)
61301 /*! cecclk_disable - CEC Engine clock synchronous disable signal. */
61302 #define MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_MASK)
61303 
61304 #define MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_MASK (0x40U)
61305 #define MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_SHIFT (6U)
61306 /*! hdcpclk_disable - HDCP clock synchronous disable signal. */
61307 #define MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_MASK)
61308 /*! @} */
61309 
61310 /*! @name MC_SWRSTZREQ_1 - Main Controller Software Reset Register Main controller software reset request per clock domain. */
61311 /*! @{ */
61312 
61313 #define MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_MASK (0x1U)
61314 #define MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_SHIFT (0U)
61315 /*! pixelswrst_req - Pixel software reset request. */
61316 #define MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_MASK)
61317 
61318 #define MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_MASK (0x2U)
61319 #define MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_SHIFT (1U)
61320 /*! tmdsswrst_req - TMDS software reset request. */
61321 #define MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_MASK)
61322 
61323 #define MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_MASK (0x4U)
61324 #define MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_SHIFT (2U)
61325 /*! prepswrst_req - Pixel Repetition software reset request. */
61326 #define MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_MASK)
61327 
61328 #define MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_MASK (0x8U)
61329 #define MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_SHIFT (3U)
61330 /*! ii2sswrst_req - I2S audio software reset request. */
61331 #define MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_MASK)
61332 
61333 #define MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_MASK (0x10U)
61334 #define MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_SHIFT (4U)
61335 /*! ispdifswrst_req - SPDIF audio software reset request. */
61336 #define MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_MASK)
61337 
61338 #define MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_MASK (0x40U)
61339 #define MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_SHIFT (6U)
61340 /*! cecswrst_req - CEC software reset request. */
61341 #define MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_MASK)
61342 
61343 #define MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_MASK (0x80U)
61344 #define MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_SHIFT (7U)
61345 /*! igpaswrst_req - GPAUD interface soft reset request. */
61346 #define MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_MASK)
61347 /*! @} */
61348 
61349 /*! @name MC_OPCTRL - Main Controller HDCP Bypass Control Register */
61350 /*! @{ */
61351 
61352 #define MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_MASK (0x1U)
61353 #define MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_SHIFT (0U)
61354 /*! hdcp_block_byp - Block HDCP bypass mechanism - 1'b0: This is the default value. */
61355 #define MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_SHIFT)) & MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_MASK)
61356 /*! @} */
61357 
61358 /*! @name MC_FLOWCTRL - Main Controller Feed Through Control Register */
61359 /*! @{ */
61360 
61361 #define MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK (0x1U)
61362 #define MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_SHIFT (0U)
61363 /*! Feed_through_off - Video path Feed Through enable bit: - 1b: Color Space Converter is in the video data path. */
61364 #define MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_SHIFT)) & MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK)
61365 /*! @} */
61366 
61367 /*! @name MC_PHYRSTZ - Main Controller PHY Reset Register */
61368 /*! @{ */
61369 
61370 #define MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_MASK   (0x1U)
61371 #define MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_SHIFT  (0U)
61372 /*! phyrstz - HDMI Source PHY active low reset control for PHY GEN1, active high reset control for PHY GEN2. */
61373 #define MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ(x)     (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_SHIFT)) & MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_MASK)
61374 /*! @} */
61375 
61376 /*! @name MC_LOCKONCLOCK_1 - Main Controller Clock Present Register */
61377 /*! @{ */
61378 
61379 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_MASK (0x1U)
61380 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_SHIFT (0U)
61381 /*! cecclk - CEC clock status. */
61382 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_MASK)
61383 
61384 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_MASK (0x4U)
61385 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_SHIFT (2U)
61386 /*! audiospdifclk - SPDIF clock status. */
61387 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_MASK)
61388 
61389 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_MASK (0x8U)
61390 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_SHIFT (3U)
61391 /*! i2sclk - I2S clock status. */
61392 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_MASK)
61393 
61394 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_MASK (0x10U)
61395 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_SHIFT (4U)
61396 /*! prepclk - Pixel Repetition clock status. */
61397 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_MASK)
61398 
61399 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_MASK (0x20U)
61400 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_SHIFT (5U)
61401 /*! tclk - TMDS clock status. */
61402 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK(x)  (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_MASK)
61403 
61404 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_MASK (0x40U)
61405 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_SHIFT (6U)
61406 /*! pclk - Pixel clock status. */
61407 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK(x)  (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_MASK)
61408 
61409 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_MASK (0x80U)
61410 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_SHIFT (7U)
61411 /*! igpaclk - GPAUD interface clock status. */
61412 #define MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_MASK)
61413 /*! @} */
61414 
61415 
61416 /*!
61417  * @}
61418  */ /* end of group MAINCONTROLLER_Register_Masks */
61419 
61420 
61421 /* MAINCONTROLLER - Peripheral instance base addresses */
61422 /** Peripheral MAINCONTROLLER base address */
61423 #define MAINCONTROLLER_BASE                      (0x32FDC000u)
61424 /** Peripheral MAINCONTROLLER base pointer */
61425 #define MAINCONTROLLER                           ((MAINCONTROLLER_Type *)MAINCONTROLLER_BASE)
61426 /** Array initializer of MAINCONTROLLER peripheral base addresses */
61427 #define MAINCONTROLLER_BASE_ADDRS                { MAINCONTROLLER_BASE }
61428 /** Array initializer of MAINCONTROLLER peripheral base pointers */
61429 #define MAINCONTROLLER_BASE_PTRS                 { MAINCONTROLLER }
61430 
61431 /*!
61432  * @}
61433  */ /* end of group MAINCONTROLLER_Peripheral_Access_Layer */
61434 
61435 
61436 /* ----------------------------------------------------------------------------
61437    -- MEDIA_BLK_CTRL Peripheral Access Layer
61438    ---------------------------------------------------------------------------- */
61439 
61440 /*!
61441  * @addtogroup MEDIA_BLK_CTRL_Peripheral_Access_Layer MEDIA_BLK_CTRL Peripheral Access Layer
61442  * @{
61443  */
61444 
61445 /** MEDIA_BLK_CTRL - Register Layout Typedef */
61446 typedef struct {
61447   __IO uint32_t SFT_RSTN;                          /**< Media Mix Software Reset Register, offset: 0x0 */
61448   __IO uint32_t CLK_EN;                            /**< Media Mix Clock Enable Register, offset: 0x4 */
61449   __IO uint32_t MIPI_RESET_DIV;                    /**< MIPI PHY Control Register, offset: 0x8 */
61450   __IO uint32_t MIPI_M_PLLPMS;                     /**< Master PLL PMS Value setting Register, offset: 0xC */
61451   __IO uint32_t MIPI_M_PLLCTL_LOW;                 /**< Master PLL Control Low Register, offset: 0x10 */
61452   __IO uint32_t MIPI_M_PLLCTL_HIGH;                /**< Master PLL Control High Register, offset: 0x14 */
61453   __IO uint32_t MIPI_B_DPHYCTL_LOW;                /**< Master and Slave DPHY Control Low Register, offset: 0x18 */
61454   __IO uint32_t MIPI_B_DPHYCTL_HIGH;               /**< Master and Slave DPHY Control High Register, offset: 0x1C */
61455   __IO uint32_t MIPI_M_DPHYCTL_LOW;                /**< Master and Slave DPHY Control Low Register, offset: 0x20 */
61456   __IO uint32_t MIPI_M_DPHYCTL_HIGH;               /**< Master and Slave DPHY Control High Register, offset: 0x24 */
61457   __IO uint32_t MIPI_S_DPHYCTL_LOW;                /**< Master and Slave DPHY Control Low Register, offset: 0x28 */
61458   __IO uint32_t MIPI_S_DPHYCTL_HIGH;               /**< Master and Slave DPHY Control High Register, offset: 0x2C */
61459        uint8_t RESERVED_0[28];
61460   __IO uint32_t LCDIF_ARCACHE_CTRL;                /**< LCDIF ARCACHE Control Register, offset: 0x4C */
61461   __IO uint32_t ISI_CACHE_CTRL;                    /**< ISI CACHE Control Register, offset: 0x50 */
61462   __IO uint32_t LDO_CTRL;                          /**< LDO Control Register, offset: 0x54 */
61463   __IO uint32_t LDO_TRIM;                          /**< LDO Trim Register, offset: 0x58 */
61464   __IO uint32_t LDB_CTRL;                          /**< LDB Control Register, offset: 0x5C */
61465   __IO uint32_t GASKET_0_CTRL;                     /**< Gasket 0 Control Register, offset: 0x60 */
61466   __IO uint32_t GASKET_0_HSIZE;                    /**< Gasket 0 Video Horizontal Size Register, offset: 0x64 */
61467   __IO uint32_t GASKET_0_VSIZE;                    /**< Gasket 0 Video Vertical Size Register, offset: 0x68 */
61468   __IO uint32_t GASKET_0_HFP;                      /**< Gasket 0 Video Horizontal Front Porch Register, offset: 0x6C */
61469   __IO uint32_t GASKET_0_HBP;                      /**< Gasket 0 Video Horizontal Back Porch Register, offset: 0x70 */
61470   __IO uint32_t GASKET_0_VFP;                      /**< Gasket 0 Video Vertical Front Porch Register, offset: 0x74 */
61471   __IO uint32_t GASKET_0_VBP;                      /**< Gasket 0 Video Vertical Back Porch Register, offset: 0x78 */
61472   __IO uint32_t GASKET_0_ISI_PIXEL_CNT;            /**< Gasket 0 ISI Pixel Count Register, offset: 0x7C */
61473   __IO uint32_t GASKET_0_ISI_LINE_CNT;             /**< Gasket 0 ISI Line Count Register, offset: 0x80 */
61474   __IO uint32_t GASKET_0_ISI_PIXEL_CTRL;           /**< Gasket 0 ISI Pixel Control Information Register, offset: 0x84 */
61475        uint8_t RESERVED_1[8];
61476   __IO uint32_t GASKET_1_CTRL;                     /**< Gasket 1 Control Register, offset: 0x90 */
61477   __IO uint32_t GASKET_1_HSIZE;                    /**< Gasket 1 Video Horizontal Size Register, offset: 0x94 */
61478   __IO uint32_t GASKET_1_VSIZE;                    /**< Gasket 1 Video Vertical Size Register, offset: 0x98 */
61479   __IO uint32_t GASKET_1_HFP;                      /**< Gasket 1 Video Horizontal Front Porch Register, offset: 0x9C */
61480   __IO uint32_t GASKET_1_HBP;                      /**< Gasket 1 Video Horizontal Back Porch Register, offset: 0xA0 */
61481   __IO uint32_t GASKET_1_VFP;                      /**< Gasket 1 Video Vertical Front Porch Register, offset: 0xA4 */
61482   __IO uint32_t GASKET_1_VBP;                      /**< Gasket 1 Video Vertical Back Porch Register, offset: 0xA8 */
61483   __IO uint32_t GASKET_1_ISI_PIXEL_CNT;            /**< Gasket 1 ISI Pixel Count Register, offset: 0xAC */
61484   __IO uint32_t GASKET_1_ISI_LINE_CNT;             /**< Gasket 1 ISI Line Count Register, offset: 0xB0 */
61485   __IO uint32_t GASKET_1_ISI_PIXEL_CTRL;           /**< Gasket 1 ISI Pixel Control Information Register, offset: 0xB4 */
61486        uint8_t RESERVED_2[104];
61487   __IO uint32_t MIPI_B2_DPHYCTL_LOW;               /**< Master and Slave DPHY Control Low Register, offset: 0x120 */
61488   __IO uint32_t MIPI_B2_DPHYCTL_HIGH;              /**< Master and Slave DPHY Control High Register, offset: 0x124 */
61489   __IO uint32_t LVDS_CTRL;                         /**< LVDS Control Register, offset: 0x128 */
61490   __IO uint32_t AXI_LIMIT_CONTROL;                 /**< AXI Limit Control Register, offset: 0x12C */
61491   __IO uint32_t AXI_LIMIT_THRESH0;                 /**< AXI Limit Threshold Register 0, offset: 0x130 */
61492   __IO uint32_t AXI_LIMIT_THRESH1;                 /**< AXI Limit Threshold Register 1, offset: 0x134 */
61493   __IO uint32_t ISP_DEWARP_CONTROL;                /**< ISP Dewarp Control Register, offset: 0x138 */
61494 } MEDIA_BLK_CTRL_Type;
61495 
61496 /* ----------------------------------------------------------------------------
61497    -- MEDIA_BLK_CTRL Register Masks
61498    ---------------------------------------------------------------------------- */
61499 
61500 /*!
61501  * @addtogroup MEDIA_BLK_CTRL_Register_Masks MEDIA_BLK_CTRL Register Masks
61502  * @{
61503  */
61504 
61505 /*! @name SFT_RSTN - Media Mix Software Reset Register */
61506 /*! @{ */
61507 
61508 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_MASK (0x1U)
61509 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_SHIFT (0U)
61510 /*! SFT_EN_MIPI_DSI_PCLK_RESETN - sft_en_mipi_dsi_pclk_resetn
61511  *  0b1..software reset disable for mipi_dsi_pclk
61512  *  0b0..software reset enable for mipi_dsi_pclk
61513  */
61514 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_MASK)
61515 
61516 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_MASK (0x2U)
61517 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_SHIFT (1U)
61518 /*! SFT_EN_MIPI_DSI_CLKREF_RESETN - sft_en_mipi_dsi_CLKREF_resetn
61519  *  0b1..software reset disable for mipi_dsi_CLKREF
61520  *  0b0..software reset enable for mipi_dsi_CLKREF
61521  */
61522 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_MASK)
61523 
61524 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_MASK (0x4U)
61525 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_SHIFT (2U)
61526 /*! SFT_EN_MIPI_CSI_PCLK_RESETN - sft_en_mipi_csi_pclk_resetn
61527  *  0b1..software reset disable for mipi_csi_pclk
61528  *  0b0..software reset enable for mipi_csi_pclk
61529  */
61530 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_MASK)
61531 
61532 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_MASK (0x8U)
61533 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_SHIFT (3U)
61534 /*! SFT_EN_MIPI_CSI_ACLK_RESETN - sft_en_mipi_csi_aclk_resetn
61535  *  0b1..software reset disable for mipi_csi_aclk
61536  *  0b0..software reset enable for mipi_csi_aclk
61537  */
61538 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_MASK)
61539 
61540 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_MASK (0x10U)
61541 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_SHIFT (4U)
61542 /*! SFT_EN_LCDIF_PIXEL_CLK_RESETN - sft_en_lcdif_pixel_clk_resetn
61543  *  0b1..software reset disable for lcdif_pixel_clk
61544  *  0b0..software reset enable for lcdif_pixel_clk
61545  */
61546 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_MASK)
61547 
61548 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_MASK (0x20U)
61549 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_SHIFT (5U)
61550 /*! SFT_EN_LCDIF_APB_CLK_RESETN - sft_en_lcdif_apb_clk_resetn
61551  *  0b1..software reset disable for lcdif_apb_clk
61552  *  0b0..software reset enable for lcdif_apb_clk
61553  */
61554 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_MASK)
61555 
61556 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_MASK (0x40U)
61557 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_SHIFT (6U)
61558 /*! SFT_EN_ISI_PROC_CLK_RESETN - sft_en_isi_proc_clk_resetn
61559  *  0b1..software reset disable for isi_proc_clk
61560  *  0b0..software reset enable for isi_proc_clk
61561  */
61562 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_MASK)
61563 
61564 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_MASK (0x80U)
61565 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_SHIFT (7U)
61566 /*! SFT_EN_ISI_APB_CLK_RESETN - sft_en_isi_apb_clk_resetn
61567  *  0b1..software reset disable for isi_apb_clk
61568  *  0b0..software reset enable for isi_apb_clk
61569  */
61570 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_MASK)
61571 
61572 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_MASK (0x100U)
61573 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_SHIFT (8U)
61574 /*! SFT_EN_BUS_BLK_CLK_RESETN - sft_en_bus_blk_clk_resetn
61575  *  0b1..software reset disable for bus_blk_clk
61576  *  0b0..software reset enable for bus_blk_clk
61577  */
61578 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_MASK)
61579 
61580 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_MASK (0x200U)
61581 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_SHIFT (9U)
61582 /*! SFT_EN_MIPI_CSI2_PCLK_RESETN - sft_en_mipi_csi2_pclk_resetn
61583  *  0b1..software reset disable for mipi_csi2_pclk
61584  *  0b0..software reset enable for mipi_csi2_pclk
61585  */
61586 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_MASK)
61587 
61588 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_MASK (0x400U)
61589 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_SHIFT (10U)
61590 /*! SFT_EN_MIPI_CSI2_ACLK_RESETN - sft_en_mipi_csi2_aclk_resetn
61591  *  0b1..software reset disable for mipi_csi2_aclk
61592  *  0b0..software reset enable for mipi_csi2_aclk
61593  */
61594 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_MASK)
61595 
61596 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_MASK (0x800U)
61597 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_SHIFT (11U)
61598 /*! SFT_EN_LCDIF2_PIXEL_CLK_RESETN - sft_en_lcdif2_pixel_clk_resetn
61599  *  0b1..software reset disable for lcdif2_pixel_clk
61600  *  0b0..software reset enable for lcdif2_pixel_clk
61601  */
61602 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_MASK)
61603 
61604 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_MASK (0x1000U)
61605 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_SHIFT (12U)
61606 /*! SFT_EN_LCDIF2_APB_CLK_RESETN - sft_en_lcdif2_apb_clk_resetn
61607  *  0b1..software reset disable for lcdif2_apb_clk
61608  *  0b0..software reset enable for lcdif2_apb_clk
61609  */
61610 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_MASK)
61611 
61612 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_MASK (0x10000U)
61613 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_SHIFT (16U)
61614 /*! SFT_EN_ISP_COR_CLK_RESETN - sft_en_isp_cor_clk_resetn;
61615  *  0b1..software reset disable for isp_cor_clk
61616  *  0b0..software reset enable for isp_cor_clk
61617  */
61618 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_MASK)
61619 
61620 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_MASK (0x20000U)
61621 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_SHIFT (17U)
61622 /*! SFT_EN_ISP_AXI_CLK_RESETN - sft_en_isp_axi_clk_resetn;
61623  *  0b1..software reset disable for isp_axi_clk
61624  *  0b0..software reset enable for isp_axi_clk
61625  */
61626 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_MASK)
61627 
61628 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_MASK (0x40000U)
61629 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_SHIFT (18U)
61630 /*! SFT_EN_ISP_AHB_CLK_RESETN - sft_en_isp_ahb_clk_resetn;
61631  *  0b1..software reset disable for isp_ahb_clk
61632  *  0b0..software reset enable for isp_ahb_clk
61633  */
61634 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_MASK)
61635 
61636 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_MASK (0x80000U)
61637 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_SHIFT (19U)
61638 /*! SFT_EN_DWE_COR_CLK_RESETN - sft_en_dwe_cor_clk_resetn;
61639  *  0b1..software reset disable for dwe_cor_clk
61640  *  0b0..software reset enable for dwe_cor_clk
61641  */
61642 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_MASK)
61643 
61644 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_MASK (0x100000U)
61645 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_SHIFT (20U)
61646 /*! SFT_EN_DWE_AXI_CLK_RESETN - sft_en_dwe_axi_clk_resetn;
61647  *  0b1..software reset disable for dwe_axi_clk
61648  *  0b0..software reset enable for dwe_axi_clk
61649  */
61650 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_MASK)
61651 
61652 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_MASK (0x200000U)
61653 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_SHIFT (21U)
61654 /*! SFT_EN_DWE_AHB_CLK_RESETN - sft_en_dwe_ahb_clk_resetn;
61655  *  0b1..software reset disable for dwe_ahb_clk
61656  *  0b0..software reset enable for dwe_ahb_clk
61657  */
61658 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_MASK)
61659 
61660 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_MASK (0x400000U)
61661 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_SHIFT (22U)
61662 /*! SFT_EN_MIPI_DSI2_CLKREF_RESETN - sft_en_mipi_dsi2_CLKREF_resetn
61663  *  0b1..software reset disable for mipi_dsi2_CLKREF
61664  *  0b0..software reset enable for mipi_dsi2_CLKREF
61665  */
61666 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_MASK)
61667 
61668 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_MASK (0x800000U)
61669 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_SHIFT (23U)
61670 /*! SFT_EN_LCDIF_AXI_CLK_RESETN - sft_en_lcdif_axi_clk_resetn
61671  *  0b1..software reset disable for lcdif_axi_clk
61672  *  0b0..software reset enable for lcdif_axi_clk
61673  */
61674 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_MASK)
61675 
61676 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_MASK (0x1000000U)
61677 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_SHIFT (24U)
61678 /*! SFT_EN_LCDIF2_AXI_CLK_RESETN - sft_en_lcdif2_axi_clk_resetn
61679  *  0b1..software reset disable for lcdif2_axi_clk
61680  *  0b0..software reset enable for lcdif2_axi_clk
61681  */
61682 #define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_MASK)
61683 /*! @} */
61684 
61685 /*! @name CLK_EN - Media Mix Clock Enable Register */
61686 /*! @{ */
61687 
61688 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_MASK (0x1U)
61689 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_SHIFT (0U)
61690 /*! SFT_EN_MIPI_DSI_PCLK - sft_en_mipi_dsi_pclk
61691  *  0b1..clock enable for mipi_dsi_pclk
61692  *  0b0..clock disable (gated) for mipi_dsi_pclk
61693  */
61694 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_MASK)
61695 
61696 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_MASK (0x2U)
61697 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_SHIFT (1U)
61698 /*! SFT_EN_MIPI_DSI_CLKREF - sft_en_mipi_dsi_CLKREF
61699  *  0b1..clock enable for mipi_dsi_CLKREF
61700  *  0b0..clock disable (gated) for mipi_dsi_CLKREF
61701  */
61702 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_MASK)
61703 
61704 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_MASK (0x4U)
61705 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_SHIFT (2U)
61706 /*! SFT_EN_MIPI_CSI_PCLK - sft_en_mipi_csi_pclk
61707  *  0b1..clock enable for mipi_csi_pclk
61708  *  0b0..clock disable (gated) for mipi_csi_pclk
61709  */
61710 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_MASK)
61711 
61712 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_MASK (0x8U)
61713 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_SHIFT (3U)
61714 /*! SFT_EN_MIPI_CSI_ACLK - sft_en_mipi_csi_aclk
61715  *  0b1..clock enable for mipi_csi_aclk
61716  *  0b0..clock disable (gated) for mipi_csi_aclk
61717  */
61718 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_MASK)
61719 
61720 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_MASK (0x10U)
61721 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_SHIFT (4U)
61722 /*! SFT_EN_LCDIF_PIXEL_CLK - sft_en_lcdif_pixel_clk
61723  *  0b1..clock enable for lcdif_pixel_clk
61724  *  0b0..clock disable (gated) for lcdif_pixel_clk
61725  */
61726 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_MASK)
61727 
61728 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_MASK (0x20U)
61729 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_SHIFT (5U)
61730 /*! SFT_EN_LCDIF_APB_CLK - sft_en_lcdif_apb_clk
61731  *  0b1..clock enable for lcdif_apb_clk
61732  *  0b0..clock disable (gated) for lcdif_apb_clk
61733  */
61734 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_MASK)
61735 
61736 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_MASK (0x40U)
61737 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_SHIFT (6U)
61738 /*! SFT_EN_ISI_PROC_CLK - sft_en_isi_proc_clk
61739  *  0b1..clock enable for isi_proc_clk
61740  *  0b0..clock disable (gated) for isi_proc_clk
61741  */
61742 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_MASK)
61743 
61744 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_MASK (0x80U)
61745 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_SHIFT (7U)
61746 /*! SFT_EN_ISI_APB_CLK - sft_en_isi_apb_clk
61747  *  0b1..clock enable for isi_apb_clk
61748  *  0b0..clock disable (gated) for isi_apb_clk
61749  */
61750 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_MASK)
61751 
61752 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_MASK (0x100U)
61753 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_SHIFT (8U)
61754 /*! SFT_EN_BUS_BLK_CLK - sft_en_bus_blk_clk
61755  *  0b1..clock enable for bus_blk_clk
61756  *  0b0..clock disable (gated) for bus_blk_clk
61757  */
61758 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_MASK)
61759 
61760 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_MASK (0x200U)
61761 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_SHIFT (9U)
61762 /*! SFT_EN_MIPI_CSI2_PCLK - sft_en_mipi_csi2_pclk
61763  *  0b1..clock enable for mipi_csi2_pclk
61764  *  0b0..clock disable (gated) for mipi_csi2_pclk
61765  */
61766 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_MASK)
61767 
61768 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_MASK (0x400U)
61769 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_SHIFT (10U)
61770 /*! SFT_EN_MIPI_CSI2_ACLK - sft_en_mipi_csi2_aclk
61771  *  0b1..clock enable for mipi_csi2_aclk
61772  *  0b0..clock disable (gated) for mipi_csi2_aclk
61773  */
61774 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_MASK)
61775 
61776 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_MASK (0x800U)
61777 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_SHIFT (11U)
61778 /*! SFT_EN_LCDIF2_PIXEL_CLK - sft_en_lcdif2_pixel_clk
61779  *  0b1..clock enable for lcdif2_pixel_clk
61780  *  0b0..clock disable (gated) for lcdif2_pixel_clk
61781  */
61782 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_MASK)
61783 
61784 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_MASK (0x1000U)
61785 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_SHIFT (12U)
61786 /*! SFT_EN_LCDIF2_APB_CLK - sft_en_lcdif2_apb_clk
61787  *  0b1..clock enable for lcdif2_apb_clk
61788  *  0b0..clock disable (gated) for lcdif2_apb_clk
61789  */
61790 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_MASK)
61791 
61792 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_MASK (0x10000U)
61793 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_SHIFT (16U)
61794 /*! SFT_EN_ISP_COR_CLK - sft_en_isp_cor_clk
61795  *  0b1..clock enable for isp_cor_clk
61796  *  0b0..clock disable (gated) for isp_cor_clk
61797  */
61798 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_MASK)
61799 
61800 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_MASK (0x20000U)
61801 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_SHIFT (17U)
61802 /*! SFT_EN_ISP_AXI_CLK - sft_en_isp_axi_clk
61803  *  0b1..clock enable for isp_axi_clk
61804  *  0b0..clock disable (gated) for isp_axi_clk
61805  */
61806 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_MASK)
61807 
61808 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_MASK (0x40000U)
61809 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_SHIFT (18U)
61810 /*! SFT_EN_ISP_AHB_CLK - sft_en_isp_ahb_clk
61811  *  0b1..clock enable for isp_ahb_clk
61812  *  0b0..clock disable (gated) for isp_ahb_clk
61813  */
61814 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_MASK)
61815 
61816 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_MASK (0x80000U)
61817 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_SHIFT (19U)
61818 /*! SFT_EN_DWE_COR_CLK - sft_en_dwe_cor_clk
61819  *  0b1..clock enable for dwe_cor_clk
61820  *  0b0..clock disable (gated) for dwe_cor_clk
61821  */
61822 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_MASK)
61823 
61824 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_MASK (0x100000U)
61825 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_SHIFT (20U)
61826 /*! SFT_EN_DWE_AXI_CLK - sft_en_dwe_axi_clk
61827  *  0b1..clock enable for dwe_axi_clk
61828  *  0b0..clock disable (gated) for dwe_axi_clk
61829  */
61830 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_MASK)
61831 
61832 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_MASK (0x200000U)
61833 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_SHIFT (21U)
61834 /*! SFT_EN_DWE_AHB_CLK - sft_en_dwe_ahb_clk
61835  *  0b1..clock enable for dwe_ahb_clk
61836  *  0b0..clock disable (gated) for dwe_ahb_clk
61837  */
61838 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_MASK)
61839 
61840 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_MASK (0x400000U)
61841 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_SHIFT (22U)
61842 /*! SFT_EN_MIPI_DSI2_CLKREF - sft_en_mipi_dsi2_CLKREF
61843  *  0b1..clock enable for mipi_dsi2_CLKREF
61844  *  0b0..clock disable (gated) for mipi_dsi2_CLKREF
61845  */
61846 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_MASK)
61847 
61848 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_MASK (0x800000U)
61849 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_SHIFT (23U)
61850 /*! SFT_EN_LCDIF_AXI_CLK - sft_en_lcdif_axi_clk
61851  *  0b1..clock enable for lcdif_axi_clk
61852  *  0b0..clock disable (gated) for lcdif_axi_clk
61853  */
61854 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_MASK)
61855 
61856 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_MASK (0x1000000U)
61857 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_SHIFT (24U)
61858 /*! SFT_EN_LCDIF2_AXI_CLK - sft_en_lcdif2_axi_clk
61859  *  0b1..clock enable for lcdif2_axi_clk
61860  *  0b0..clock disable (gated) for lcdif2_axi_clk
61861  */
61862 #define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_MASK)
61863 /*! @} */
61864 
61865 /*! @name MIPI_RESET_DIV - MIPI PHY Control Register */
61866 /*! @{ */
61867 
61868 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_MASK (0x10000U)
61869 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_SHIFT (16U)
61870 /*! GPR_MIPI_S_RESETN - GPR_MIPI_S_RESETN
61871  *  0b1..MIPI DPHY S_RESETN reset disable
61872  *  0b0..MIPI DPHY S_RESETN reset enable
61873  */
61874 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_MASK)
61875 
61876 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_MASK (0x20000U)
61877 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_SHIFT (17U)
61878 /*! GPR_MIPI_M_RESETN - GPR_MIPI_M_RESETN
61879  *  0b1..MIPI DPHY M_RESETN reset disable
61880  *  0b0..MIPI DPHY M_RESETN reset enable
61881  */
61882 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_MASK)
61883 
61884 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_MASK (0x40000U)
61885 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_SHIFT (18U)
61886 /*! GPR_CTRL_S3_BIASEN - GPR_CTRL_S3_BIASEN. Used in MIPI PHY
61887  *  0b1..S3_BIASEN active
61888  *  0b0..S3_BIASEN disable
61889  */
61890 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_MASK)
61891 
61892 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_MASK (0x80000U)
61893 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_SHIFT (19U)
61894 /*! GPR_CTRL_S2_BIASEN - GPR_CTRL_S2_BIASEN. Used in MIPI PHY
61895  *  0b1..S2_BIASEN active
61896  *  0b0..S2_BIASEN disable
61897  */
61898 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_MASK)
61899 
61900 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_MASK (0x100000U)
61901 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_SHIFT (20U)
61902 /*! GPR_CTRL_S1_BIASEN - GPR_CTRL_S1_BIASEN. Used in MIPI PHY
61903  *  0b1..S1_BIASEN active
61904  *  0b0..S1_BIASEN disable
61905  */
61906 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_MASK)
61907 
61908 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_MASK (0x200000U)
61909 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_SHIFT (21U)
61910 /*! GPR_CTRL_M2_BIASEN - GPR_CTRL_M2_BIASEN. Used in MIPI PHY
61911  *  0b1..M2_BIASEN active
61912  *  0b0..M2_BIASEN disable
61913  */
61914 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_MASK)
61915 
61916 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_MASK (0x400000U)
61917 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_SHIFT (22U)
61918 /*! GPR_CTRL_M1_BIASEN - GPR_CTRL_M1_BIASEN. Used in MIPI PHY
61919  *  0b1..M1_BIASEN active
61920  *  0b0..M1_BIASEN disable
61921  */
61922 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_MASK)
61923 
61924 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_MASK (0x800000U)
61925 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_SHIFT (23U)
61926 /*! GPR_MIPI_S_DPDN_SWAP_DAT - GPR_MIPI_S_DPDN_SWAP_DAT
61927  *  0b1..Master DPHY data lane DP and DN swap enable
61928  *  0b0..Master DPHY data lane DP and DN swap disable
61929  */
61930 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_MASK)
61931 
61932 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_MASK (0x1000000U)
61933 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_SHIFT (24U)
61934 /*! GPR_MIPI_S_DPDN_SWAP_CLK - GPR_MIPI_S_DPDN_SWAP_CLK
61935  *  0b1..Slave DPHY clock lane DP and DN swap enable
61936  *  0b0..Slave DPHY clock lane DP and DN swap disable
61937  */
61938 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_MASK)
61939 
61940 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_MASK (0x2000000U)
61941 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_SHIFT (25U)
61942 /*! GPR_MIPI_M_DPDN_SWAP_DAT - GPR_MIPI_M_DPDN_SWAP_DAT
61943  *  0b1..Master DPHY data lane DP and DN swap enable
61944  *  0b0..Master DPHY data lane DP and DN swap disable
61945  */
61946 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_MASK)
61947 
61948 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_MASK (0x4000000U)
61949 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_SHIFT (26U)
61950 /*! GPR_MIPI_M_DPDN_SWAP_CLK - GPR_MIPI_M_DPDN_SWAP_CLK
61951  *  0b1..Master DPHY clock lane DP and DN swap enable
61952  *  0b0..Master DPHY clock lane DP and DN swap disable
61953  */
61954 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_MASK)
61955 
61956 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_MASK (0x20000000U)
61957 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_SHIFT (29U)
61958 /*! GPR_MIPI_M2_RESETN - GPR_MIPI_M2_RESETN
61959  *  0b1..MIPI DPHY M2_RESETN reset disable
61960  *  0b0..MIPI DPHY M2_RESETN reset enable
61961  */
61962 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_MASK)
61963 
61964 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_MASK (0x40000000U)
61965 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_SHIFT (30U)
61966 /*! GPR_MIPI_S2_RESETN - GPR_MIPI_S2_RESETN
61967  *  0b1..MIPI DPHY S2_RESETN reset disable
61968  *  0b0..MIPI DPHY S2_RESETN reset enable
61969  */
61970 #define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_MASK)
61971 /*! @} */
61972 
61973 /*! @name MIPI_M_PLLPMS - Master PLL PMS Value setting Register */
61974 /*! @{ */
61975 
61976 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_MASK  (0x6U)
61977 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_SHIFT (1U)
61978 /*! PMS_S - PMS_S
61979  *  0b00..Divide by 1
61980  *  0b01..Divide by 2
61981  *  0b10..Divide by 4
61982  *  0b11..Divide by 8
61983  */
61984 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S(x)    (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_MASK)
61985 
61986 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_MASK  (0x1FF0U)
61987 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_SHIFT (4U)
61988 /*! PMS_M - PMS_M
61989  *  0b000000000..Do not program, can cause malfunction
61990  *  0b000011001..Divide by 25
61991  *  0b000011010..Divide by 26
61992  *  0b000011011..Divide by 27
61993  *  0b000011100..Divide by 28
61994  *  0b000011101..Divide by 29
61995  *  0b001111010..Divide by 122
61996  *  0b001111011..Divide by 123
61997  *  0b001111100..Divide by 124
61998  *  0b001111101..Divide by 125
61999  */
62000 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M(x)    (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_MASK)
62001 
62002 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_MASK  (0x7E000U)
62003 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_SHIFT (13U)
62004 /*! PMS_P - PMS_P
62005  *  0b000000..Do not program, can cause malfunction
62006  *  0b000001..Divide by 1
62007  *  0b000010..Divide by 2
62008  *  0b000011..Divide by 3
62009  *  0b000100..Divide by 4
62010  *  0b000101..Divide by 5
62011  *  0b011110..Divide by 30
62012  *  0b011111..Divide by 31
62013  *  0b100000..Divide by 32
62014  *  0b100001..Divide by 33
62015  */
62016 #define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P(x)    (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_MASK)
62017 /*! @} */
62018 
62019 /*! @name MIPI_M_PLLCTL_LOW - Master PLL Control Low Register */
62020 /*! @{ */
62021 
62022 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_MASK (0x1U)
62023 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_SHIFT (0U)
62024 /*! AFC_ENB - Automatic Frequency Control Enable/Disable
62025  *  0b0..AFC is enabled
62026  *  0b1..AFC is disabled
62027  */
62028 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_MASK)
62029 
62030 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_MASK (0x3EU)
62031 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_SHIFT (1U)
62032 /*! EXTAFC - EXTAFC */
62033 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_MASK)
62034 
62035 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_MASK (0x40U)
62036 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_SHIFT (6U)
62037 /*! AFCINIT_SEL - AFC initial delay select pin */
62038 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_MASK)
62039 
62040 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_MASK (0x300000U)
62041 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_SHIFT (20U)
62042 /*! ICP - Controls the charge-pump current */
62043 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP(x)  (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_MASK)
62044 
62045 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_MASK (0x400000U)
62046 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_SHIFT (22U)
62047 /*! BYPASS - BYPASS */
62048 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_MASK)
62049 
62050 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_MASK (0x800000U)
62051 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_SHIFT (23U)
62052 /*! FSEL - Monitoring frequency select pin */
62053 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_MASK)
62054 
62055 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_MASK (0x8000000U)
62056 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_SHIFT (27U)
62057 /*! PBIAS_CTRL_EN - PBIAS voltage pull-down enable pin (active-high) */
62058 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_MASK)
62059 
62060 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_MASK (0x10000000U)
62061 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_SHIFT (28U)
62062 /*! PBIAS_CTRL - PBIAS pull-down initial voltage control pin */
62063 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_MASK)
62064 
62065 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_MASK (0x20000000U)
62066 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_SHIFT (29U)
62067 /*! FEED_EN - FEED_OUT enable pin (active-high) */
62068 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_MASK)
62069 
62070 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_MASK (0x40000000U)
62071 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_SHIFT (30U)
62072 /*! AFC_SEL - AFC operation mode select pin */
62073 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_MASK)
62074 
62075 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_MASK (0x80000000U)
62076 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_SHIFT (31U)
62077 /*! SSCG_EN - Enable pin for dithered mode. (Active-high) */
62078 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_MASK)
62079 /*! @} */
62080 
62081 /*! @name MIPI_M_PLLCTL_HIGH - Master PLL Control High Register */
62082 /*! @{ */
62083 
62084 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_MASK (0xFFU)
62085 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_SHIFT (0U)
62086 /*! MFR - Value of 8-bit Modulation Frequency (MF) control */
62087 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_MASK)
62088 
62089 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_MASK (0x3F00U)
62090 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_SHIFT (8U)
62091 /*! MRR - Value of 6-bit Modulation Rate (MR) control */
62092 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_MASK)
62093 
62094 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_MASK (0xC000U)
62095 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_SHIFT (14U)
62096 /*! SEL_PF - Value of 2-bit modulation method control */
62097 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_MASK)
62098 
62099 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_MASK (0xFFFF0000U)
62100 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_SHIFT (16U)
62101 /*! K - Value of 16-bit Delta-Sigma Modulator (DSM) */
62102 #define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K(x)   (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_MASK)
62103 /*! @} */
62104 
62105 /*! @name MIPI_B_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
62106 /*! @{ */
62107 
62108 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK (0x3FFU)
62109 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT (0U)
62110 /*! ULPS_EXIT_COUNTER - ULPS_EXIT_COUNTER
62111  *  0b0000000000..0.01 MHz
62112  *  0b0000000011..0.10 MHz
62113  *  0b0000011001..1.00 MHz
62114  *  0b0000110010..2.00 MHz
62115  *  0b0001001011..3.00 MHz
62116  *  0b0001100100..4.00 MHz
62117  *  0b0001111101..5.00 MHz
62118  *  0b0010010110..6.00 MHz
62119  *  0b0010101111..7.00 MHz
62120  *  0b0011001000..8.00 MHz
62121  *  0b0011100001..9.00 MHz
62122  *  0b0011111010..10.00 MHz
62123  *  0b0100010011..11.00 MHz
62124  *  0b0100101100..12.00 MHz
62125  *  0b0101000101..13.00 MHz
62126  *  0b0101011110..14.00 MHz
62127  *  0b0101110111..15.00 MHz
62128  *  0b0110010000..16.00 MHz
62129  *  0b0110101001..17.00 MHz
62130  *  0b0111000010..18.00 MHz
62131  *  0b0111011011..19.00 MHz
62132  *  0b0111110100..20.00 MHz
62133  */
62134 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK)
62135 
62136 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK (0x400U)
62137 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT (10U)
62138 /*! TX_TRIGGER_CLK_EN - TX_TRIGGER_CLK_EN
62139  *  0b0..Enable
62140  *  0b1..Disable
62141  */
62142 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK)
62143 
62144 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK (0x800U)
62145 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT (11U)
62146 /*! ERR_CONT_LP_EN - ERR_CONT_LP_EN
62147  *  0b0..Enable
62148  *  0b1..Disable
62149  */
62150 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK)
62151 
62152 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK (0x1000U)
62153 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT (12U)
62154 /*! BGR_CHOPPER_EN - BGR_CHOPPER_EN
62155  *  0b0..Enable
62156  *  0b1..Disable
62157  */
62158 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK)
62159 
62160 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_MASK (0x2000U)
62161 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_SHIFT (13U)
62162 /*! LP_CD_HYS - LP_CD_HYS
62163  *  0b0..60mV
62164  *  0b1..70mV
62165  */
62166 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_MASK)
62167 
62168 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK (0x4000U)
62169 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT (14U)
62170 /*! MSTR_CLK_SLEW_RATE_UP - MSTR_CLK_SLEW_RATE_UP
62171  *  0b0..No change
62172  *  0b1..Slew Rate UP
62173  */
62174 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK)
62175 
62176 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK (0x18000U)
62177 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT (15U)
62178 /*! MSTR_CLK_SLEW_RATE_DOWN - MSTR_CLK_SLEW_RATE_DOWN
62179  *  0b00..No change
62180  *  0b01..Decrease the slew rate by about 15%
62181  *  0b10..Decrease the slew rate by about 15%
62182  *  0b11..Decrease the slew rate by about 30%
62183  */
62184 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK)
62185 
62186 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK (0x20000U)
62187 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT (17U)
62188 /*! LP_RX_PULSE_REJ - LP_RX_PULSE_REJ
62189  *  0b0..Enable
62190  *  0b1..Disable
62191  */
62192 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK)
62193 
62194 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK (0xC0000U)
62195 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT (18U)
62196 /*! LP_RX_VREF_LVL - LP_RX_VREF_LVL
62197  *  0b00..715mV
62198  *  0b01..743mV
62199  *  0b10..650mV
62200  *  0b11..682mV
62201  */
62202 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK)
62203 
62204 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_MASK (0x100000U)
62205 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT (20U)
62206 /*! VREF_SRC_SEL - VREF_SRC_SEL
62207  *  0b0..Generated from the BGR
62208  *  0b1..Generated from the current mirror
62209  */
62210 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_MASK)
62211 
62212 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK (0x600000U)
62213 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT (21U)
62214 /*! LP_RX_HYS_CTL - LP_RX_HYS_CTL
62215  *  0b00..80mV
62216  *  0b01..100mV
62217  *  0b10..120mV
62218  *  0b11..140mV
62219  */
62220 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK)
62221 
62222 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_MASK (0x800000U)
62223 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_SHIFT (23U)
62224 /*! REG_VALID_1_2 - REG_VALID_1_2
62225  *  0b0..Use "ulps_en" signal
62226  *  0b1..Use valid signal from 1.2V regulator
62227  */
62228 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_MASK)
62229 
62230 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK (0x3000000U)
62231 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT (24U)
62232 /*! REG_LVL_CTL_1_2 - REG_LVL_CTL_1_2
62233  *  0b00..1.2V
62234  *  0b01..1.23V
62235  *  0b10..1.27V
62236  *  0b11..1.26V
62237  */
62238 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK)
62239 
62240 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK (0x4000000U)
62241 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT (26U)
62242 /*! REG_VALID_CTL_1_2 - REG_VALID_CTL_1_2
62243  *  0b0..Internal 1.2V regulator
62244  *  0b1..External 1.2V power
62245  */
62246 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK)
62247 
62248 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK (0x8000000U)
62249 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT (27U)
62250 /*! BGR_CHOPPER_FREQ_CTL - BGR_CHOPPER_FREQ_CTL
62251  *  0b0..3MHz
62252  *  0b1..1.5MHz
62253  */
62254 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK)
62255 
62256 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK (0x30000000U)
62257 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT (28U)
62258 /*! BIAS_REF_VOLT_CTL - BIAS_REF_VOLT_CTL
62259  *  0b00..712mV
62260  *  0b01..724mV
62261  *  0b10..733mV
62262  *  0b11..706mV
62263  */
62264 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK)
62265 
62266 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_MASK (0xC0000000U)
62267 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_SHIFT (30U)
62268 /*! USER_DATA_HS - User Data Pattern for HS Loopback mode */
62269 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_MASK)
62270 /*! @} */
62271 
62272 /*! @name MIPI_B_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
62273 /*! @{ */
62274 
62275 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_MASK (0x3FU)
62276 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_SHIFT (0U)
62277 /*! USER_DATA_HS - User Data Pattern for HS Loopback mode */
62278 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_MASK)
62279 
62280 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_MASK (0xC0U)
62281 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT (6U)
62282 /*! HS_MODE_CTL - HS_MODE_CTL
62283  *  0b00..Designated Pattern
62284  *  0b01..PRBS7
62285  *  0b10..All zero
62286  *  0b11..User Data Pattern
62287  */
62288 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_MASK)
62289 
62290 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK (0x300U)
62291 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT (8U)
62292 /*! BGR_VOLT_TUNING_CTL - BGR_VOLT_TUNING_CTL
62293  *  0b00..820mV
62294  *  0b01..760mV
62295  *  0b10..800mV
62296  *  0b11..840mV
62297  */
62298 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK)
62299 
62300 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_MASK (0x800U)
62301 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT (11U)
62302 /*! DCC_DONE_CTL - DCC_DONE_CTL
62303  *  0b0.."DONE" from DCC block
62304  *  0b1..U"DONE" is always 1
62305  */
62306 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_MASK)
62307 
62308 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK (0x2000U)
62309 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT (13U)
62310 /*! RX_SKEW_CALIB_FIX_CODE_EN - RX_SKEW_CALIB_FIX_CODE_EN
62311  *  0b0..Disable
62312  *  0b1..Enable
62313  */
62314 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK)
62315 
62316 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK (0x4000U)
62317 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT (14U)
62318 /*! LP_VREF_REG_SRC_SEL - LP_VREF_REG_SRC_SEL
62319  *  0b0..Generated from BGR
62320  *  0b1..Generated from Current Mirror
62321  */
62322 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK)
62323 
62324 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK (0x100000U)
62325 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT (20U)
62326 /*! MSTR_DATA0_SLEW_RATE_UP - MSTR_DATA0_SLEW_RATE_UP
62327  *  0b0..No change
62328  *  0b1..Slew Rate UP
62329  */
62330 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK)
62331 
62332 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK (0x600000U)
62333 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT (21U)
62334 /*! MSTR_DATA0_SLEW_RATE_DOWN - MSTR_DATA0_SLEW_RATE_DOWN
62335  *  0b00..No change
62336  *  0b01..Decrease the slew rate by about 15%
62337  *  0b10..Decrease the slew rate by about 15%
62338  *  0b11..Decrease the slew rate by about 30%
62339  */
62340 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK)
62341 
62342 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK (0x800000U)
62343 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT (23U)
62344 /*! MSTR_DATA1_SLEW_RATE_UP - MSTR_DATA1_SLEW_RATE_UP
62345  *  0b0..No change
62346  *  0b1..Slew Rate UP
62347  */
62348 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK)
62349 
62350 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK (0x3000000U)
62351 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT (24U)
62352 /*! MSTR_DATA1_SLEW_RATE_DOWN - MSTR_DATA1_SLEW_RATE_DOWN
62353  *  0b00..No change
62354  *  0b01..Decrease the slew rate by about 15%
62355  *  0b10..Decrease the slew rate by about 15%
62356  *  0b11..Decrease the slew rate by about 30%
62357  */
62358 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK)
62359 
62360 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK (0x4000000U)
62361 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT (26U)
62362 /*! MSTR_DATA2_SLEW_RATE_UP - MSTR_DATA2_SLEW_RATE_UP
62363  *  0b0..No change
62364  *  0b1..Slew Rate UP
62365  */
62366 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK)
62367 
62368 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK (0x18000000U)
62369 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT (27U)
62370 /*! MSTR_DATA2_SLEW_RATE_DOWN - MSTR_DATA2_SLEW_RATE_DOWN
62371  *  0b00..No change
62372  *  0b01..Decrease the slew rate by about 15%
62373  *  0b10..Decrease the slew rate by about 15%
62374  *  0b11..Decrease the slew rate by about 30%
62375  */
62376 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK)
62377 
62378 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK (0x20000000U)
62379 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT (29U)
62380 /*! MSTR_DATA3_SLEW_RATE_UP - MSTR_DATA3_SLEW_RATE_UP
62381  *  0b0..No change
62382  *  0b1..Slew Rate UP
62383  */
62384 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK)
62385 
62386 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK (0xC0000000U)
62387 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT (30U)
62388 /*! MSTR_DATA3_SLEW_RATE_DOWN - MSTR_DATA3_SLEW_RATE_DOWN
62389  *  0b00..No change
62390  *  0b01..Decrease the slew rate by about 15%
62391  *  0b10..Decrease the slew rate by about 15%
62392  *  0b11..Decrease the slew rate by about 30%
62393  */
62394 #define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK)
62395 /*! @} */
62396 
62397 /*! @name MIPI_M_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
62398 /*! @{ */
62399 
62400 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_MASK (0x3U)
62401 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_SHIFT (0U)
62402 /*! DATA_HS_TX_DELAY_CTL - DATA_HS_TX_DELAY_CTL
62403  *  0b00..No change
62404  *  0b01..25 ps
62405  *  0b10..55 ps
62406  *  0b11..90 ps
62407  */
62408 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_MASK)
62409 
62410 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_MASK (0xCU)
62411 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_SHIFT (2U)
62412 /*! HS_TX_REG_AMP_CTL - HS_TX_REG_AMP_CTL
62413  *  0b00..No Change
62414  *  0b01..12.5 uA
62415  *  0b10..50 uA
62416  *  0b11..16.6 uA
62417  */
62418 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_MASK)
62419 
62420 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_MASK (0x10U)
62421 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_SHIFT (4U)
62422 /*! HS_TX_REG_TURN_ON_CTL - HS_TX_REG_TURN_ON_CTL
62423  *  0b0..No Change
62424  *  0b1..Always Turn-On the HS Regulator
62425  */
62426 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_MASK)
62427 
62428 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_MASK (0x60U)
62429 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_SHIFT (5U)
62430 /*! CLK_HS_TX_DELAY_CTL - CLK_HS_TX_DELAY_CTL
62431  *  0b00..No change
62432  *  0b01..25 ps
62433  *  0b10..55 ps
62434  *  0b11..90 ps
62435  */
62436 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_MASK)
62437 
62438 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_MASK (0x380U)
62439 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_SHIFT (7U)
62440 /*! HS_TX_SLEW_RATE_CTL - HS_TX_SLEW_RATE_CTL */
62441 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_MASK)
62442 
62443 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_MASK (0x400U)
62444 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_SHIFT (10U)
62445 /*! HS_TX_SLEW_RATE_EN - HS_TX_SLEW_RATE_EN
62446  *  0b0..SRC Disable
62447  *  0b1..SRC Enable
62448  */
62449 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_MASK)
62450 
62451 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_MASK (0x1800U)
62452 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_SHIFT (11U)
62453 /*! CLK_LANE_CAP_CTL - CLK_LANE_CAP_CTL
62454  *  0b00..No change
62455  *  0b01..-6.6%
62456  *  0b10..13.3%
62457  *  0b11..6.6%
62458  */
62459 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_MASK)
62460 
62461 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_MASK (0x6000U)
62462 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_SHIFT (13U)
62463 /*! DATA_LANE_CAP_CTL - DATA_LANE_CAP_CTL
62464  *  0b00..No change
62465  *  0b01..-6.6%
62466  *  0b10..13.3%
62467  *  0b11..6.6%
62468  */
62469 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_MASK)
62470 
62471 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK (0x18000U)
62472 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT (15U)
62473 /*! ANA_TIMER_HYS_CTL - ANA_TIMER_HYS_CTL
62474  *  0b00..70mV
62475  *  0b01..95mV
62476  *  0b10..95mV
62477  *  0b11..110mV
62478  */
62479 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK)
62480 
62481 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_MASK (0xE0000U)
62482 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_SHIFT (17U)
62483 /*! HS_TX_TERM_IMP_UP_CTL - HS_TX_TERM_IMP_UP_CTL
62484  *  0b000..50 ohm
62485  *  0b001..52 ohm
62486  *  0b010..54 ohm
62487  *  0b011..56 ohm
62488  *  0b100..44 ohm
62489  *  0b101..46 ohm
62490  *  0b110..47 ohm
62491  *  0b111..48 ohm
62492  */
62493 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_MASK)
62494 
62495 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_MASK (0x700000U)
62496 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_SHIFT (20U)
62497 /*! HS_TX_TERM_IMP_DOWN_CTL - HS_TX_TERM_IMP_DOWN_CTL
62498  *  0b000..50 ohm
62499  *  0b001..52 ohm
62500  *  0b010..54 ohm
62501  *  0b011..56 ohm
62502  *  0b100..44 ohm
62503  *  0b101..46 ohm
62504  *  0b110..47 ohm
62505  *  0b111..48 ohm
62506  */
62507 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_MASK)
62508 
62509 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_MASK (0x800000U)
62510 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_SHIFT (23U)
62511 /*! HS_TX_REG_CURRENT_CTL - HS_TX_REG_CURRENT_CTL
62512  *  0b0..No change
62513  *  0b1..2.5 uA
62514  */
62515 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_MASK)
62516 
62517 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_MASK (0x7000000U)
62518 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_SHIFT (24U)
62519 /*! HS_TX_REG_OUT_CTL - HS_TX_REG_OUT_CTL
62520  *  0b000..400mV
62521  *  0b001..410mV
62522  *  0b010..420mV
62523  *  0b011..440mV
62524  *  0b100..200mV
62525  *  0b101..360mV
62526  *  0b110..380mV
62527  *  0b111..390mV
62528  */
62529 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_MASK)
62530 
62531 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_MASK (0x38000000U)
62532 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_SHIFT (27U)
62533 /*! HS_TX_RISE_FALL_TIME_CTL - HS_TX_RISE_FALL_TIME_CTL
62534  *  0b000..135mV
62535  *  0b001..130mV
62536  *  0b010..125mV
62537  *  0b011..120mV
62538  *  0b100..230mV
62539  *  0b101..225mV
62540  *  0b110..220mV
62541  *  0b111..215mV
62542  */
62543 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_MASK)
62544 
62545 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_MASK (0x40000000U)
62546 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_SHIFT (30U)
62547 /*! CLK_BUFFER_EN_CTL - CLK_BUFFER_EN_CTL
62548  *  0b0..HS_TX enable
62549  *  0b1..PLL lock
62550  */
62551 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_MASK)
62552 
62553 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_MASK (0x80000000U)
62554 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_SHIFT (31U)
62555 /*! HS_REG_VREF_SRC_SEL - HS_REG_VREF_SRC_SEL
62556  *  0b0..Generated from BGR
62557  *  0b1..Generated from Current Mirror
62558  */
62559 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_MASK)
62560 /*! @} */
62561 
62562 /*! @name MIPI_M_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
62563 /*! @{ */
62564 
62565 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_MASK (0x1U)
62566 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_SHIFT (0U)
62567 /*! CLK_SEL_CTL - CLK_SEL_CTL
62568  *  0b0..Generated from Internal PLL
62569  *  0b1..Generated from External PLL
62570  */
62571 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_MASK)
62572 
62573 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_MASK (0xF00U)
62574 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_SHIFT (8U)
62575 /*! TXSKEWCALHS_CTL - TXSKEWCALHS_CTL */
62576 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_MASK)
62577 
62578 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_MASK (0xF000U)
62579 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_SHIFT (12U)
62580 /*! TXSKEWCALHS_INIT_CTL - TXSKEWCALHS_INIT_CTL */
62581 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_MASK)
62582 
62583 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_MASK (0xF0000U)
62584 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_SHIFT (16U)
62585 /*! TXSKEWCALHS_WAIT_CTL - TXSKEWCALHS_WAIT_CTL */
62586 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_MASK)
62587 
62588 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_MASK (0x10000000U)
62589 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_SHIFT (28U)
62590 /*! PLL_CLK_OUT_SEL - PLL_CLK_OUT_SEL
62591  *  0b0..Disable OUT to Other lane
62592  *  0b1..Enable OUT to Other lane
62593  */
62594 #define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_MASK)
62595 /*! @} */
62596 
62597 /*! @name MIPI_S_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
62598 /*! @{ */
62599 
62600 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_MASK (0x3U)
62601 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_SHIFT (0U)
62602 /*! HS_RX_BIAS_CTL - HS_RX_BIAS_CTL
62603  *  0b00..25 uA
62604  *  0b01..30 uA
62605  *  0b10..37.5 uA
62606  *  0b11..50 uA
62607  */
62608 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_MASK)
62609 
62610 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_MASK (0xCU)
62611 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_SHIFT (2U)
62612 /*! HS_RX_DELAY_CTRL - HS_RX_DELAY_CTRL
62613  *  0b00..0 ps
62614  *  0b01..30 ps
62615  *  0b10..60 ps
62616  *  0b11..90 ps
62617  */
62618 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_MASK)
62619 
62620 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_MASK (0x30U)
62621 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_SHIFT (4U)
62622 /*! XXX - xxx
62623  *  0b00..-
62624  *  0b01..30 ps
62625  *  0b10..60 ps
62626  *  0b11..90 ps
62627  */
62628 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_MASK)
62629 
62630 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_MASK (0xC0U)
62631 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_SHIFT (6U)
62632 /*! HS_RX_TERM_IMP_CTL - HS_RX_TERM_IMP_CTL
62633  *  0b00..98 ohm
62634  *  0b01..106 ohm
62635  *  0b10..85 ohm
62636  *  0b11..91 ohm
62637  */
62638 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_MASK)
62639 
62640 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_MASK (0x300U)
62641 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_SHIFT (8U)
62642 /*! CLK_LANE_CAP_CTL_TCLK_SETTLE - CLK_LANE_CAP_CTL_TCLK_SETTLE
62643  *  0b00..No change
62644  *  0b01..3.45%
62645  *  0b10..6.9%
62646  *  0b11..10.35%
62647  */
62648 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_MASK)
62649 
62650 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_MASK (0xC00U)
62651 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_SHIFT (10U)
62652 /*! CLK_LANE_CAP_CTL_TCLK_MISS - CLK_LANE_CAP_CTL_TCLK_MISS
62653  *  0b00..No change
62654  *  0b01..6.6%
62655  *  0b10..13.2%
62656  *  0b11..19.8%
62657  */
62658 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_MASK)
62659 
62660 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_MASK (0x1000U)
62661 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_SHIFT (12U)
62662 /*! CLK_MISS_EN - CLK_MISS_EN
62663  *  0b0..Enable
62664  *  0b1..Disable
62665  */
62666 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_MASK)
62667 
62668 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK (0x6000U)
62669 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT (13U)
62670 /*! ANA_TIMER_HYS_CTL - ANA_TIMER_HYS_CTL
62671  *  0b00..70mV
62672  *  0b01..95mV
62673  *  0b10..95mV
62674  *  0b11..110mV
62675  */
62676 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK)
62677 
62678 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_MASK (0x30000U)
62679 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_SHIFT (16U)
62680 /*! DCC_CCO_GAIN_CTL - DCC_CCO_GAIN_CTL
62681  *  0b00..1/1
62682  *  0b01..1/4
62683  *  0b10..1/0.66
62684  *  0b11..1/1.33
62685  */
62686 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_MASK)
62687 
62688 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_MASK (0x7C0000U)
62689 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_SHIFT (18U)
62690 /*! DCC_BYPASS_UP_CODE_CTL_DBG1 - DCC_BYPASS_UP_CODE_CTL_DBG1 */
62691 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_MASK)
62692 
62693 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_MASK (0xF800000U)
62694 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_SHIFT (23U)
62695 /*! DCC_BYPASS_UP_CODE_CTL_DBG2 - DCC_BYPASS_UP_CODE_CTL_DBG2 */
62696 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_MASK)
62697 
62698 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_MASK (0x70000000U)
62699 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_SHIFT (28U)
62700 /*! DCC_INIT_TOLERANCE - DCC_INIT_TOLERANCE
62701  *  0b000..4
62702  *  0b001..5
62703  *  0b010..6
62704  *  0b011..7
62705  *  0b100..0
62706  *  0b101..1
62707  *  0b110..2
62708  *  0b111..3
62709  */
62710 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_MASK)
62711 
62712 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_MASK (0x80000000U)
62713 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_SHIFT (31U)
62714 /*! DCC_STABLE_CTL - DCC_STABLE_CTL
62715  *  0b0..1 number counter running
62716  *  0b1..2 number counter running
62717  */
62718 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_MASK)
62719 /*! @} */
62720 
62721 /*! @name MIPI_S_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
62722 /*! @{ */
62723 
62724 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_MASK (0x1U)
62725 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_SHIFT (0U)
62726 /*! DCC_EN - DCC_EN
62727  *  0b0..DCC Disable
62728  *  0b1..DCC Enable
62729  */
62730 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_MASK)
62731 
62732 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_MASK (0x2U)
62733 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_SHIFT (1U)
62734 /*! SKEW_CALIB_EN - SKEW_CALIB_EN
62735  *  0b0..Skew Calibration Disable
62736  *  0b1..Skew Calibration Enable
62737  */
62738 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_MASK)
62739 
62740 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_MASK (0xFCU)
62741 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_SHIFT (2U)
62742 /*! SKEW_CALIB_MAX_CODE_CTL - SKEW_CALIB_MAX_CODE_CTL */
62743 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_MASK)
62744 
62745 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_MASK (0x3F00U)
62746 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_SHIFT (8U)
62747 /*! SKEW_CALIB_FAIL_MIN_CTL - SKEW_CALIB_FAIL_MIN_CTL */
62748 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_MASK)
62749 
62750 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_MASK (0x3F0000U)
62751 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_SHIFT (16U)
62752 /*! SKEW_CALIB_PASS_MIN_CTL - SKEW_CALIB_PASS_MIN_CTL */
62753 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_MASK)
62754 
62755 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_MASK (0x3000000U)
62756 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_SHIFT (24U)
62757 /*! SKEW_CALIB_FAIL_TOL_CTL - SKEW_CALIB_FAIL_TOL_CTL
62758  *  0b00..Recognizes the pass although fail appears 3 times
62759  *  0b01..Recognizes the pass although fail appears 2 times
62760  *  0b10..Recognizes the pass although fail appears 1 time
62761  *  0b11..Reserved
62762  */
62763 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_MASK)
62764 
62765 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_MASK (0xC000000U)
62766 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_SHIFT (26U)
62767 /*! SKEW_CALIB_CMP_WAIT_TIME_CTL - SKEW_CALIB_CMP_WAIT_TIME_CTL
62768  *  0b00..Min (Fast)
62769  *  0b01..Reserved
62770  *  0b10..Reserved
62771  *  0b11..Mx (Slow)
62772  */
62773 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_MASK)
62774 
62775 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_MASK (0xF0000000U)
62776 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_SHIFT (28U)
62777 /*! SKEW_CALIB_CMP_RUN_TIME_CTL - SKEW_CALIB_CMP_RUN_TIME_CTL */
62778 #define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_MASK)
62779 /*! @} */
62780 
62781 /*! @name LCDIF_ARCACHE_CTRL - LCDIF ARCACHE Control Register */
62782 /*! @{ */
62783 
62784 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_MASK (0x1U)
62785 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_SHIFT (0U)
62786 /*! GPR_ARCACHE_LCDIF_EN - AXI master ARCACHE control enable
62787  *  0b0..disable LCDIF AXI master ARCACHE control
62788  *  0b1..enable LCDIF AXI master ARCACHE control
62789  */
62790 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_MASK)
62791 
62792 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_MASK (0x1EU)
62793 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_SHIFT (1U)
62794 /*! GPR_ARCACHE_LCDIF - Control LCDIF AXI master ARCACHE type */
62795 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_MASK)
62796 
62797 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_MASK (0x20U)
62798 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_SHIFT (5U)
62799 /*! GPR_ARCACHE_LCDIF2_EN - AXI master ARCACHE control enable
62800  *  0b0..disable LCDIF2 AXI master ARCACHE control
62801  *  0b1..enable LCDIF2 AXI master ARCACHE control
62802  */
62803 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_MASK)
62804 
62805 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_MASK (0x3C0U)
62806 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_SHIFT (6U)
62807 /*! GPR_ARCACHE_LCDIF2 - Control LCDIF2 AXI master ARCACHE type */
62808 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_MASK)
62809 
62810 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_MASK (0x1C00U)
62811 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_SHIFT (10U)
62812 /*! GPR_LCDIF_0_RD_HURRY - GPR_lcdif_0_rd_hurry */
62813 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_MASK)
62814 
62815 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_MASK (0xE000U)
62816 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_SHIFT (13U)
62817 /*! GPR_LCDIF_1_RD_HURRY - GPR_lcdif_1_rd_hurry */
62818 #define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_MASK)
62819 /*! @} */
62820 
62821 /*! @name ISI_CACHE_CTRL - ISI CACHE Control Register */
62822 /*! @{ */
62823 
62824 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_MASK (0x1U)
62825 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_SHIFT (0U)
62826 /*! GPR_ARCACHE_ISI_Y_EN - ISI Y channel AXI master ARCACHE control enable
62827  *  0b0..disable
62828  *  0b1..enable
62829  */
62830 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_MASK)
62831 
62832 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_MASK (0x1EU)
62833 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_SHIFT (1U)
62834 /*! GPR_ARCACHE_ISI_Y - Control ISI Y channel AXI master ARCACHE type */
62835 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_MASK)
62836 
62837 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_MASK (0x20U)
62838 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_SHIFT (5U)
62839 /*! GPR_AWCACHE_ISI_Y_EN - ISI Y channel AXI master AWCACHE control enable
62840  *  0b0..disable
62841  *  0b1..enable
62842  */
62843 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_MASK)
62844 
62845 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_MASK (0x3C0U)
62846 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_SHIFT (6U)
62847 /*! GPR_AWCACHE_ISI_Y - Control ISI Y channel AXI master AWCACHE type */
62848 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_MASK)
62849 
62850 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_MASK (0x400U)
62851 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_SHIFT (10U)
62852 /*! GPR_AWCACHE_ISI_U_EN - ISI U channel AXI master AWCACHE control enable
62853  *  0b0..disable
62854  *  0b1..enable
62855  */
62856 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_MASK)
62857 
62858 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_MASK (0x7800U)
62859 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_SHIFT (11U)
62860 /*! GPR_AWCACHE_ISI_U - Control ISI U channel AXI master AWCACHE type */
62861 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_MASK)
62862 
62863 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_MASK (0x8000U)
62864 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_SHIFT (15U)
62865 /*! GPR_AWCACHE_ISI_V_EN - ISI V channel AXI master AWCACHE control enable
62866  *  0b0..disable
62867  *  0b1..enable
62868  */
62869 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_MASK)
62870 
62871 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_MASK (0xF0000U)
62872 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_SHIFT (16U)
62873 /*! GPR_AWCACHE_ISI_V - Control ISI V channel AXI master AWCACHE type */
62874 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_MASK)
62875 
62876 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_MASK (0x700000U)
62877 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_SHIFT (20U)
62878 /*! GPR_ISI_Y_WR_HURRY - GPR_ISI_y_wr_hurry */
62879 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_MASK)
62880 
62881 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_MASK (0x3800000U)
62882 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_SHIFT (23U)
62883 /*! GPR_ISI_U_WR_HURRY - GPR_ISI_u_wr_hurry */
62884 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_MASK)
62885 
62886 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_MASK (0x1C000000U)
62887 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_SHIFT (26U)
62888 /*! GPR_ISI_V_WR_HURRY - GPR_ISI_v_wr_hurry */
62889 #define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_MASK)
62890 /*! @} */
62891 
62892 /*! @name LDO_CTRL - LDO Control Register */
62893 /*! @{ */
62894 
62895 #define MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_MASK (0x1FU)
62896 #define MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_SHIFT (0U)
62897 /*! MIPI_DPHY_LDO_VOUT_CTRL - LDO output control port(high level 0.8v,low level 0v) */
62898 #define MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_SHIFT)) & MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_MASK)
62899 /*! @} */
62900 
62901 /*! @name LDO_TRIM - LDO Trim Register */
62902 /*! @{ */
62903 
62904 #define MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_MASK (0x1FU)
62905 #define MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_SHIFT (0U)
62906 /*! MIPI_DPHY_LDO_VOUT_TRIM - LDO output trimming port(high level 0.8v,low level 0v) */
62907 #define MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_SHIFT)) & MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_MASK)
62908 /*! @} */
62909 
62910 /*! @name LDB_CTRL - LDB Control Register */
62911 /*! @{ */
62912 
62913 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_MASK  (0x1U)
62914 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_SHIFT (0U)
62915 /*! CH0_ENABLE - ch0_enable */
62916 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_MASK)
62917 
62918 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_MASK (0x2U)
62919 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_SHIFT (1U)
62920 /*! CH0_DI_SELECT - ch0_di_select
62921  *  0b0..LDB data from source 0
62922  *  0b1..LDB data from source 1
62923  */
62924 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_MASK)
62925 
62926 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_MASK  (0x4U)
62927 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_SHIFT (2U)
62928 /*! CH1_ENABLE - ch1_enable */
62929 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_MASK)
62930 
62931 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_MASK (0x8U)
62932 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_SHIFT (3U)
62933 /*! CH1_DI_SELECT - ch1_di_select
62934  *  0b0..LDB data from source 0
62935  *  0b1..LDB data from source 1
62936  */
62937 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_MASK)
62938 
62939 #define MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_MASK  (0x10U)
62940 #define MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_SHIFT (4U)
62941 /*! SPLIT_MODE - split_mode */
62942 #define MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE(x)    (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_MASK)
62943 
62944 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_MASK (0x20U)
62945 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_SHIFT (5U)
62946 /*! CH0_DATA_WIDTH - ch0_data_width
62947  *  0b1..24bits
62948  *  0b0..18bits
62949  */
62950 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_MASK)
62951 
62952 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_MASK (0x40U)
62953 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_SHIFT (6U)
62954 /*! CH0_BIT_MAPPING - ch0_bit_mapping
62955  *  0b1..JEIDA mapping
62956  *  0b0..SPWG mapping
62957  */
62958 #define MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_MASK)
62959 
62960 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_MASK (0x80U)
62961 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_SHIFT (7U)
62962 /*! CH1_DATA_WIDTH - ch1_data_width */
62963 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_MASK)
62964 
62965 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_MASK (0x100U)
62966 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_SHIFT (8U)
62967 /*! CH1_BIT_MAPPING - ch1_bit_mapping
62968  *  0b1..JEIDA mapping
62969  *  0b0..SPWG mapping
62970  */
62971 #define MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_MASK)
62972 
62973 #define MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_MASK (0x200U)
62974 #define MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_SHIFT (9U)
62975 /*! DI0_VSYNC_POLARITY - di0 VSYNC polarity select
62976  *  0b1..positive polarity
62977  *  0b0..negative polarity
62978  */
62979 #define MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_MASK)
62980 
62981 #define MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_MASK (0x400U)
62982 #define MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_SHIFT (10U)
62983 /*! DI1_VSYNC_POLARITY - di1 VSYNC polarity select
62984  *  0b1..positive polarity
62985  *  0b0..negative polarity
62986  */
62987 #define MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_MASK)
62988 
62989 #define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_MASK (0x800U)
62990 #define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_SHIFT (11U)
62991 /*! REG_CH0_FIFO_RESET - reg_ch0_fifo_reset */
62992 #define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_MASK)
62993 
62994 #define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_MASK (0x1000U)
62995 #define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_SHIFT (12U)
62996 /*! REG_CH1_FIFO_RESET - reg_ch1_fifo_reset */
62997 #define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_MASK)
62998 /*! @} */
62999 
63000 /*! @name GASKET_0_CTRL - Gasket 0 Control Register */
63001 /*! @{ */
63002 
63003 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_MASK (0x1U)
63004 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_SHIFT (0U)
63005 /*! GASKET_0_ENABLE - Gasket 0 enable
63006  *  0b1..Gasket 0 output enable
63007  *  0b0..Gasket output disable
63008  */
63009 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_MASK)
63010 
63011 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_MASK (0x2U)
63012 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_SHIFT (1U)
63013 /*! GASKET_0_DOUBLE_COMP - Gasket 0 double component enable
63014  *  0b1..Gasket 0 input double component per pixel clock for YUV422
63015  *  0b0..Gasket 0 input single component per pixel clock for YUV422
63016  */
63017 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_MASK)
63018 
63019 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_MASK (0x4U)
63020 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_SHIFT (2U)
63021 /*! GASKET_0_LEFT_JUST_MODE - Gasket 0 Left justified mode
63022  *  0b1..unused LSB equal most significant bit of valid data
63023  *  0b0..unused LSB equal lease significant bit of valid data
63024  */
63025 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_MASK)
63026 
63027 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_MASK (0x8U)
63028 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_SHIFT (3U)
63029 /*! GASKET_0_YUV420_LINE_SEL - Gasket 0 YUV420 ODD/EVEN line first select
63030  *  0b1..Gasket 0 EVEN line first for YUV420 data type
63031  *  0b0..Gasket 0 ODD line first for YUV420 data type
63032  */
63033 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_MASK)
63034 
63035 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_MASK (0x30U)
63036 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_SHIFT (4U)
63037 /*! GASKET_0_VC_ID - Gasket 0 Virtual channel identifier, */
63038 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_MASK)
63039 
63040 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_MASK (0xC0U)
63041 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_SHIFT (6U)
63042 /*! GASKET_0_INTER_MODE - Gasket 0 interlace mode
63043  *  0b11..reserved
63044  *  0b10..interlaced right
63045  *  0b01..interlaced left
63046  *  0b00..not interlaced
63047  */
63048 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_MASK)
63049 
63050 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_MASK (0x3F00U)
63051 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_SHIFT (8U)
63052 /*! GASKET_0_DATA_TYPE - Gasket 0 data type
63053  *  0b011000..YUV420 8-bit
63054  *  0b011001..YUV420 10-bit
63055  *  0b011010..Legacy YUV420 8-bit
63056  *  0b011100..YUV420 8-bit(Chroma Shifted Pixel Sampling)
63057  *  0b011101..YUV420 10-bit(Chroma Shifted Pixel Sampling)
63058  *  0b011110..YUV422 8-bit
63059  *  0b011111..YUV422 10-bit
63060  *  0b100010..RGB565
63061  *  0b100011..RGB666
63062  *  0b100100..RGB888
63063  *  0b101000..RAW6
63064  *  0b101001..RAW7
63065  *  0b101010..RAW8
63066  *  0b101011..RAW10
63067  *  0b101100..RAW12
63068  *  0b101101..RAW14
63069  */
63070 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_MASK)
63071 
63072 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_MASK (0xC000U)
63073 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_SHIFT (14U)
63074 /*! GASKET_0_SRC_SEL - Gasket 0 source when support ISI de-interlace line_doubling mode
63075  *  0b11..source from mipi_csi channel 3
63076  *  0b10..source from mipi_csi channel 2
63077  *  0b01..source from mipi_csi channel 1
63078  *  0b00..source from mipi_csi channel 0
63079  */
63080 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_MASK)
63081 
63082 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_MASK (0x10000U)
63083 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_SHIFT (16U)
63084 /*! GASKET_0_LINE_DOUBLING_EN - Gasket 0 output for ISI de-interlace line_doubling mode enable
63085  *  0b1..Gasket 0 output for ISI de-interlace line_doubling mode
63086  *  0b0..Gasket 0 not output for ISI de-interlace line_doubling mode
63087  */
63088 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_MASK)
63089 
63090 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_MASK (0x20000U)
63091 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_SHIFT (17U)
63092 /*! MIPI_ISP_LEFT_JUST_MODE - mipi_isp_left_just_mode */
63093 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_MASK)
63094 
63095 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_MASK (0xC0000U)
63096 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_SHIFT (18U)
63097 /*! MIPI_CSI_VS_SEL - mipi_csi_vs_sel */
63098 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_MASK)
63099 
63100 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_MASK (0x100000U)
63101 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_SHIFT (20U)
63102 /*! MIPI_CSI_HS_POLARITY - mipi_csi_hs_polarity */
63103 #define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_MASK)
63104 /*! @} */
63105 
63106 /*! @name GASKET_0_HSIZE - Gasket 0 Video Horizontal Size Register */
63107 /*! @{ */
63108 
63109 #define MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_MASK (0xFFFFFFFFU)
63110 #define MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_SHIFT (0U)
63111 /*! GASKET_0_HSIZE - Gasket 0 video Horizontal size(count in pixel) */
63112 #define MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_MASK)
63113 /*! @} */
63114 
63115 /*! @name GASKET_0_VSIZE - Gasket 0 Video Vertical Size Register */
63116 /*! @{ */
63117 
63118 #define MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_MASK (0xFFFFFFFFU)
63119 #define MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_SHIFT (0U)
63120 /*! GASKET_0_VSIZE - Gasket 0 video Vertical size(count in line) */
63121 #define MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_MASK)
63122 /*! @} */
63123 
63124 /*! @name GASKET_0_HFP - Gasket 0 Video Horizontal Front Porch Register */
63125 /*! @{ */
63126 
63127 #define MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_MASK (0xFFFFFFFFU)
63128 #define MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_SHIFT (0U)
63129 /*! GASKET_0_HFP - Gasket 0 video Horizontal front porch(count in pixel) */
63130 #define MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_MASK)
63131 /*! @} */
63132 
63133 /*! @name GASKET_0_HBP - Gasket 0 Video Horizontal Back Porch Register */
63134 /*! @{ */
63135 
63136 #define MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_MASK (0xFFFFFFFFU)
63137 #define MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_SHIFT (0U)
63138 /*! GASKET_0_HBP - Gasket 0 video Horizontal back porch(count in pixel) */
63139 #define MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_MASK)
63140 /*! @} */
63141 
63142 /*! @name GASKET_0_VFP - Gasket 0 Video Vertical Front Porch Register */
63143 /*! @{ */
63144 
63145 #define MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_MASK (0xFFFFFFFFU)
63146 #define MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_SHIFT (0U)
63147 /*! GASKET_0_VFP - Gasket 0 video Vertical front porch(count in line) */
63148 #define MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_MASK)
63149 /*! @} */
63150 
63151 /*! @name GASKET_0_VBP - Gasket 0 Video Vertical Back Porch Register */
63152 /*! @{ */
63153 
63154 #define MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_MASK (0xFFFFFFFFU)
63155 #define MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_SHIFT (0U)
63156 /*! GASKET_0_VBP - Gasket 0 video Vertical back porch(count in line) */
63157 #define MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_MASK)
63158 /*! @} */
63159 
63160 /*! @name GASKET_0_ISI_PIXEL_CNT - Gasket 0 ISI Pixel Count Register */
63161 /*! @{ */
63162 
63163 #define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_MASK (0xFFFFFFFFU)
63164 #define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_SHIFT (0U)
63165 /*! GASKET_0_ISI_PIXEL_CNT - Gasket 0 output to ISI pixel count status */
63166 #define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_MASK)
63167 /*! @} */
63168 
63169 /*! @name GASKET_0_ISI_LINE_CNT - Gasket 0 ISI Line Count Register */
63170 /*! @{ */
63171 
63172 #define MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_MASK (0xFFFFFFFFU)
63173 #define MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_SHIFT (0U)
63174 /*! GASKET_0_ISI_LINE_CNT - Gasket 0 output to ISI line count status */
63175 #define MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_MASK)
63176 /*! @} */
63177 
63178 /*! @name GASKET_0_ISI_PIXEL_CTRL - Gasket 0 ISI Pixel Control Information Register */
63179 /*! @{ */
63180 
63181 #define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_MASK (0xFFFU)
63182 #define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_SHIFT (0U)
63183 /*! GASKET_0_ISI_PIXEL_CTRL - Gasket 0 output to ISI pixel control information status */
63184 #define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_MASK)
63185 /*! @} */
63186 
63187 /*! @name GASKET_1_CTRL - Gasket 1 Control Register */
63188 /*! @{ */
63189 
63190 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_MASK (0x1U)
63191 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_SHIFT (0U)
63192 /*! GASKET_1_ENABLE - Gasket 1 enable
63193  *  0b1..Gasket 1 output enable;
63194  *  0b0..Gasket output disable
63195  */
63196 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_MASK)
63197 
63198 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_MASK (0x2U)
63199 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_SHIFT (1U)
63200 /*! GASKET_1_DOUBLE_COMP - Gasket 1 double component enable
63201  *  0b1..Gasket 1 input double component per pixel clock for YUV422
63202  *  0b0..Gasket 1 input single component per pixel clock for YUV422
63203  */
63204 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_MASK)
63205 
63206 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_MASK (0x4U)
63207 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_SHIFT (2U)
63208 /*! GASKET_1_LEFT_JUST_MODE - Gasket 1 Left justified mode
63209  *  0b1..unused LSB equal most significant bit of valid data
63210  *  0b0..unused LSB equal lease significant bit of valid data
63211  */
63212 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_MASK)
63213 
63214 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_MASK (0x8U)
63215 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_SHIFT (3U)
63216 /*! GASKET_1_YUV420_LINE_SEL - Gasket 1 YUV420 ODD/EVEN line first select
63217  *  0b1..Gasket 1 EVEN line first for YUV420 data type
63218  *  0b0..Gasket 1 ODD line first for YUV420 data type
63219  */
63220 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_MASK)
63221 
63222 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_MASK (0x30U)
63223 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_SHIFT (4U)
63224 /*! GASKET_1_VC_ID - Gasket 1 Virtual channel identifier, */
63225 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_MASK)
63226 
63227 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_MASK (0xC0U)
63228 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_SHIFT (6U)
63229 /*! GASKET_1_INTER_MODE - Gasket 1 interlace mode
63230  *  0b11..reserved
63231  *  0b10..interlaced right
63232  *  0b01..interlaced left
63233  *  0b00..not interlaced
63234  */
63235 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_MASK)
63236 
63237 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_MASK (0x3F00U)
63238 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_SHIFT (8U)
63239 /*! GASKET_1_DATA_TYPE - Gasket 1 data type
63240  *  0b011000..YUV420 8-bit
63241  *  0b011001..YUV420 10-bit
63242  *  0b011010..Legacy YUV420 8-bit
63243  *  0b011100..YUV420 8-bit(Chroma Shifted Pixel Sampling)
63244  *  0b011101..YUV420 10-bit(Chroma Shifted Pixel Sampling)
63245  *  0b011110..YUV422 8-bit
63246  *  0b011111..YUV422 10-bit
63247  *  0b100010..RGB565
63248  *  0b100011..RGB666
63249  *  0b100100..RGB888
63250  *  0b101000..RAW6
63251  *  0b101001..RAW7
63252  *  0b101010..RAW8
63253  *  0b101011..RAW10
63254  *  0b101100..RAW12
63255  *  0b101101..RAW14
63256  */
63257 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_MASK)
63258 
63259 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_MASK (0xC000U)
63260 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_SHIFT (14U)
63261 /*! GASKET_1_SRC_SEL - Gasket 1 source when support ISI de-interlace line_doubling mode
63262  *  0b11..source from mipi_csi channel 3
63263  *  0b10..source from mipi_csi channel 2
63264  *  0b01..source from mipi_csi channel 1
63265  *  0b00..source from mipi_csi channel 0
63266  */
63267 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_MASK)
63268 
63269 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_MASK (0x10000U)
63270 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_SHIFT (16U)
63271 /*! GASKET_1_LINE_DOUBLING_EN - Gasket 1 output for ISI de-interlace line_doubling mode enable
63272  *  0b1..Gasket 1 output for ISI de-interlace line_doubling mode
63273  *  0b0..Gasket 0 not output for ISI de-interlace line_doubling mode
63274  */
63275 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_MASK)
63276 
63277 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_MASK (0x20000U)
63278 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT (17U)
63279 /*! MIPI_ISP2_LEFT_JUST_MODE - mipi_isp2_left_just_mode */
63280 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_MASK)
63281 
63282 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_MASK (0xC0000U)
63283 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_SHIFT (18U)
63284 /*! MIPI_CSI2_VS_SEL - mipi_csi2_vs_sel */
63285 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_MASK)
63286 
63287 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_MASK (0x100000U)
63288 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_SHIFT (20U)
63289 /*! MIPI_CSI2_HS_POLARITY - mipi_csi2_hs_polarity */
63290 #define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_MASK)
63291 /*! @} */
63292 
63293 /*! @name GASKET_1_HSIZE - Gasket 1 Video Horizontal Size Register */
63294 /*! @{ */
63295 
63296 #define MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_MASK   (0xFFFFFFFFU)
63297 #define MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_SHIFT  (0U)
63298 /*! GP0 - Gasket 1 video Horizontal size(count in pixel) */
63299 #define MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0(x)     (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_MASK)
63300 /*! @} */
63301 
63302 /*! @name GASKET_1_VSIZE - Gasket 1 Video Vertical Size Register */
63303 /*! @{ */
63304 
63305 #define MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_MASK (0xFFFFFFFFU)
63306 #define MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_SHIFT (0U)
63307 /*! GASKET_1_VSIZE - Gasket 1 video Vertical size(count in line) */
63308 #define MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_MASK)
63309 /*! @} */
63310 
63311 /*! @name GASKET_1_HFP - Gasket 1 Video Horizontal Front Porch Register */
63312 /*! @{ */
63313 
63314 #define MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_MASK (0xFFFFFFFFU)
63315 #define MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_SHIFT (0U)
63316 /*! GASKET_1_HFP - Gasket 1 video Horizontal front porch(count in pixel) */
63317 #define MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_MASK)
63318 /*! @} */
63319 
63320 /*! @name GASKET_1_HBP - Gasket 1 Video Horizontal Back Porch Register */
63321 /*! @{ */
63322 
63323 #define MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_MASK (0xFFFFFFFFU)
63324 #define MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_SHIFT (0U)
63325 /*! GASKET_1_HBP - Gasket 1 video Horizontal back porch(count in pixel) */
63326 #define MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_MASK)
63327 /*! @} */
63328 
63329 /*! @name GASKET_1_VFP - Gasket 1 Video Vertical Front Porch Register */
63330 /*! @{ */
63331 
63332 #define MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_MASK (0xFFFFFFFFU)
63333 #define MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_SHIFT (0U)
63334 /*! GASKET_1_VFP - Gasket 1 video Vertical front porch(count in line) */
63335 #define MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_MASK)
63336 /*! @} */
63337 
63338 /*! @name GASKET_1_VBP - Gasket 1 Video Vertical Back Porch Register */
63339 /*! @{ */
63340 
63341 #define MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_MASK (0xFFFFFFFFU)
63342 #define MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_SHIFT (0U)
63343 /*! GASKET_1_VBP - Gasket 1 video Vertical back porch(count in line) */
63344 #define MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_MASK)
63345 /*! @} */
63346 
63347 /*! @name GASKET_1_ISI_PIXEL_CNT - Gasket 1 ISI Pixel Count Register */
63348 /*! @{ */
63349 
63350 #define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_MASK (0xFFFFFFFFU)
63351 #define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_SHIFT (0U)
63352 /*! GASKET_1_ISI_PIXEL_CNT - Gasket 1 output to ISI pixel count status */
63353 #define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_MASK)
63354 /*! @} */
63355 
63356 /*! @name GASKET_1_ISI_LINE_CNT - Gasket 1 ISI Line Count Register */
63357 /*! @{ */
63358 
63359 #define MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_MASK (0xFFFFFFFFU)
63360 #define MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_SHIFT (0U)
63361 /*! GASKET_1_ISI_LINE_CNT - Gasket 1 output to ISI line count status */
63362 #define MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_MASK)
63363 /*! @} */
63364 
63365 /*! @name GASKET_1_ISI_PIXEL_CTRL - Gasket 1 ISI Pixel Control Information Register */
63366 /*! @{ */
63367 
63368 #define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_MASK (0xFFFU)
63369 #define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_SHIFT (0U)
63370 /*! GASKET_1_ISI_PIXEL_CTRL - Gasket 1 output to ISI pixel control information status */
63371 #define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_MASK)
63372 /*! @} */
63373 
63374 /*! @name MIPI_B2_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
63375 /*! @{ */
63376 
63377 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK (0x3FFU)
63378 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT (0U)
63379 /*! ULPS_EXIT_COUNTER - ULPS_EXIT_COUNTER
63380  *  0b0000000000..0.01 MHz
63381  *  0b0000000011..0.10 MHz
63382  *  0b0000011001..1.00 MHz
63383  *  0b0000110010..2.00 MHz
63384  *  0b0001001011..3.00 MHz
63385  *  0b0001100100..4.00 MHz
63386  *  0b0001111101..5.00 MHz
63387  *  0b0010010110..6.00 MHz
63388  *  0b0010101111..7.00 MHz
63389  *  0b0011001000..8.00 MHz
63390  *  0b0011100001..9.00 MHz
63391  *  0b0011111010..10.00 MHz
63392  *  0b0100010011..11.00 MHz
63393  *  0b0100101100..12.00 MHz
63394  *  0b0101000101..13.00 MHz
63395  *  0b0101011110..14.00 MHz
63396  *  0b0101110111..15.00 MHz
63397  *  0b0110010000..16.00 MHz
63398  *  0b0110101001..17.00 MHz
63399  *  0b0111000010..18.00 MHz
63400  *  0b0111011011..19.00 MHz
63401  *  0b0111110100..20.00 MHz
63402  */
63403 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK)
63404 
63405 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK (0x400U)
63406 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT (10U)
63407 /*! TX_TRIGGER_CLK_EN - TX_TRIGGER_CLK_EN
63408  *  0b0..Enable
63409  *  0b1..Disable
63410  */
63411 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK)
63412 
63413 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK (0x800U)
63414 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT (11U)
63415 /*! ERR_CONT_LP_EN - ERR_CONT_LP_EN
63416  *  0b0..Enable
63417  *  0b1..Disable
63418  */
63419 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK)
63420 
63421 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK (0x1000U)
63422 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT (12U)
63423 /*! BGR_CHOPPER_EN - BGR_CHOPPER_EN
63424  *  0b0..Enable
63425  *  0b1..Disable
63426  */
63427 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK)
63428 
63429 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_MASK (0x2000U)
63430 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_SHIFT (13U)
63431 /*! LP_CD_HYS - LP_CD_HYS
63432  *  0b0..60mV
63433  *  0b1..70mV
63434  */
63435 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_MASK)
63436 
63437 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK (0x4000U)
63438 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT (14U)
63439 /*! MSTR_CLK_SLEW_RATE_UP - MSTR_CLK_SLEW_RATE_UP
63440  *  0b0..No change
63441  *  0b1..Slew Rate UP
63442  */
63443 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK)
63444 
63445 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK (0x18000U)
63446 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT (15U)
63447 /*! MSTR_CLK_SLEW_RATE_DOWN - MSTR_CLK_SLEW_RATE_DOWN
63448  *  0b00..No change
63449  *  0b01..Decrease the slew rate by about 15%
63450  *  0b10..Decrease the slew rate by about 15%
63451  *  0b11..Decrease the slew rate by about 30%
63452  */
63453 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK)
63454 
63455 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK (0x20000U)
63456 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT (17U)
63457 /*! LP_RX_PULSE_REJ - LP_RX_PULSE_REJ
63458  *  0b0..Enable
63459  *  0b1..Disable
63460  */
63461 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK)
63462 
63463 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK (0xC0000U)
63464 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT (18U)
63465 /*! LP_RX_VREF_LVL - LP_RX_VREF_LVL
63466  *  0b00..715mV
63467  *  0b01..743mV
63468  *  0b10..650mV
63469  *  0b11..682mV
63470  */
63471 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK)
63472 
63473 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_MASK (0x100000U)
63474 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT (20U)
63475 /*! VREF_SRC_SEL - VREF_SRC_SEL
63476  *  0b0..Generated from the BGR
63477  *  0b1..Generated from the current mirror
63478  */
63479 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_MASK)
63480 
63481 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK (0x600000U)
63482 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT (21U)
63483 /*! LP_RX_HYS_CTL - LP_RX_HYS_CTL
63484  *  0b00..80mV
63485  *  0b01..100mV
63486  *  0b10..120mV
63487  *  0b11..140mV
63488  */
63489 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK)
63490 
63491 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_MASK (0x800000U)
63492 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_SHIFT (23U)
63493 /*! REG_VALID_1_2 - REG_VALID_1_2
63494  *  0b0..Use "ulps_en" signal
63495  *  0b1..Use valid signal from 1.2V regulator
63496  */
63497 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_MASK)
63498 
63499 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK (0x3000000U)
63500 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT (24U)
63501 /*! REG_LVL_CTL_1_2 - REG_LVL_CTL_1_2
63502  *  0b00..1.2V
63503  *  0b01..1.23V
63504  *  0b10..1.27V
63505  *  0b11..1.26V
63506  */
63507 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK)
63508 
63509 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK (0x4000000U)
63510 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT (26U)
63511 /*! REG_VALID_CTL_1_2 - REG_VALID_CTL_1_2
63512  *  0b0..Internal 1.2V regulator
63513  *  0b1..External 1.2V power
63514  */
63515 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK)
63516 
63517 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK (0x8000000U)
63518 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT (27U)
63519 /*! BGR_CHOPPER_FREQ_CTL - BGR_CHOPPER_FREQ_CTL
63520  *  0b0..3MHz
63521  *  0b1..1.5MHz
63522  */
63523 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK)
63524 
63525 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK (0x30000000U)
63526 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT (28U)
63527 /*! BIAS_REF_VOLT_CTL - BIAS_REF_VOLT_CTL
63528  *  0b00..712mV
63529  *  0b01..724mV
63530  *  0b10..733mV
63531  *  0b11..706mV
63532  */
63533 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK)
63534 
63535 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_MASK (0xC0000000U)
63536 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_SHIFT (30U)
63537 /*! USER_DATA_HS - User Data Pattern for HS Loopback mode */
63538 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_MASK)
63539 /*! @} */
63540 
63541 /*! @name MIPI_B2_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
63542 /*! @{ */
63543 
63544 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_MASK (0x3FU)
63545 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_SHIFT (0U)
63546 /*! USER_DATA_HS - User Data Pattern for HS Loopback mode */
63547 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_MASK)
63548 
63549 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_MASK (0xC0U)
63550 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT (6U)
63551 /*! HS_MODE_CTL - HS_MODE_CTL
63552  *  0b00..Designated Pattern
63553  *  0b01..PRBS7
63554  *  0b10..All zero
63555  *  0b11..User Data Pattern
63556  */
63557 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_MASK)
63558 
63559 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK (0x300U)
63560 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT (8U)
63561 /*! BGR_VOLT_TUNING_CTL - BGR_VOLT_TUNING_CTL
63562  *  0b00..820mV
63563  *  0b01..760mV
63564  *  0b10..800mV
63565  *  0b11..840mV
63566  */
63567 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK)
63568 
63569 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_MASK (0x800U)
63570 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT (11U)
63571 /*! DCC_DONE_CTL - DCC_DONE_CTL
63572  *  0b0.."DONE" from DCC block
63573  *  0b1..U"DONE" is always 1
63574  */
63575 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_MASK)
63576 
63577 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK (0x2000U)
63578 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT (13U)
63579 /*! RX_SKEW_CALIB_FIX_CODE_EN - RX_SKEW_CALIB_FIX_CODE_EN
63580  *  0b0..Disable
63581  *  0b1..Enable
63582  */
63583 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK)
63584 
63585 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK (0x4000U)
63586 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT (14U)
63587 /*! LP_VREF_REG_SRC_SEL - LP_VREF_REG_SRC_SEL
63588  *  0b0..Generated from BGR
63589  *  0b1..Generated from Current Mirror
63590  */
63591 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK)
63592 
63593 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK (0x100000U)
63594 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT (20U)
63595 /*! MSTR_DATA0_SLEW_RATE_UP - MSTR_DATA0_SLEW_RATE_UP
63596  *  0b0..No change
63597  *  0b1..Slew Rate UP
63598  */
63599 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK)
63600 
63601 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK (0x600000U)
63602 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT (21U)
63603 /*! MSTR_DATA0_SLEW_RATE_DOWN - MSTR_DATA0_SLEW_RATE_DOWN
63604  *  0b00..No change
63605  *  0b01..Decrease the slew rate by about 15%
63606  *  0b10..Decrease the slew rate by about 15%
63607  *  0b11..Decrease the slew rate by about 30%
63608  */
63609 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK)
63610 
63611 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK (0x800000U)
63612 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT (23U)
63613 /*! MSTR_DATA1_SLEW_RATE_UP - MSTR_DATA1_SLEW_RATE_UP
63614  *  0b0..No change
63615  *  0b1..Slew Rate UP
63616  */
63617 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK)
63618 
63619 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK (0x3000000U)
63620 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT (24U)
63621 /*! MSTR_DATA1_SLEW_RATE_DOWN - MSTR_DATA1_SLEW_RATE_DOWN
63622  *  0b00..No change
63623  *  0b01..Decrease the slew rate by about 15%
63624  *  0b10..Decrease the slew rate by about 15%
63625  *  0b11..Decrease the slew rate by about 30%
63626  */
63627 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK)
63628 
63629 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK (0x4000000U)
63630 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT (26U)
63631 /*! MSTR_DATA2_SLEW_RATE_UP - MSTR_DATA2_SLEW_RATE_UP
63632  *  0b0..No change
63633  *  0b1..Slew Rate UP
63634  */
63635 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK)
63636 
63637 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK (0x18000000U)
63638 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT (27U)
63639 /*! MSTR_DATA2_SLEW_RATE_DOWN - MSTR_DATA2_SLEW_RATE_DOWN
63640  *  0b00..No change
63641  *  0b01..Decrease the slew rate by about 15%
63642  *  0b10..Decrease the slew rate by about 15%
63643  *  0b11..Decrease the slew rate by about 30%
63644  */
63645 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK)
63646 
63647 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK (0x20000000U)
63648 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT (29U)
63649 /*! MSTR_DATA3_SLEW_RATE_UP - MSTR_DATA3_SLEW_RATE_UP
63650  *  0b0..No change
63651  *  0b1..Slew Rate UP
63652  */
63653 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK)
63654 
63655 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK (0xC0000000U)
63656 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT (30U)
63657 /*! MSTR_DATA3_SLEW_RATE_DOWN - MSTR_DATA3_SLEW_RATE_DOWN
63658  *  0b00..No change
63659  *  0b01..Decrease the slew rate by about 15%
63660  *  0b10..Decrease the slew rate by about 15%
63661  *  0b11..Decrease the slew rate by about 30%
63662  */
63663 #define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK)
63664 /*! @} */
63665 
63666 /*! @name LVDS_CTRL - LVDS Control Register */
63667 /*! @{ */
63668 
63669 #define MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_MASK     (0x1U)
63670 #define MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_SHIFT    (0U)
63671 /*! CH0_EN - channel0 enable */
63672 #define MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN(x)       (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_MASK)
63673 
63674 #define MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_MASK     (0x2U)
63675 #define MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_SHIFT    (1U)
63676 /*! CH1_EN - channel1 enable */
63677 #define MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN(x)       (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_MASK)
63678 
63679 #define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_MASK     (0x4U)
63680 #define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_SHIFT    (2U)
63681 /*! VBG_EN - Bandgap enable. */
63682 #define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN(x)       (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_MASK)
63683 
63684 #define MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_MASK      (0x8U)
63685 #define MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_SHIFT     (3U)
63686 /*! HS_EN - hs_en
63687  *  0b1..enable the 100 Ohm terminated resistor in the chip, at the same time, the power dissipation will also be double.
63688  */
63689 #define MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN(x)        (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_MASK)
63690 
63691 #define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_MASK (0x10U)
63692 #define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_SHIFT (4U)
63693 /*! PRE_EMPH_EN - Enable pre-emphasis */
63694 #define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN(x)  (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_MASK)
63695 
63696 #define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_MASK (0xE0U)
63697 #define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_SHIFT (5U)
63698 /*! PRE_EMPH_ADJ - Pre-emphasis adjustment. */
63699 #define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_MASK)
63700 
63701 #define MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_MASK     (0x700U)
63702 #define MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_SHIFT    (8U)
63703 /*! CM_ADJ - Output common mode(Vos) adjustment. */
63704 #define MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ(x)       (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_MASK)
63705 
63706 #define MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_MASK     (0x3800U)
63707 #define MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_SHIFT    (11U)
63708 /*! CC_ADJ - Output current adjustment. */
63709 #define MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ(x)       (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_MASK)
63710 
63711 #define MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_MASK   (0x1C000U)
63712 #define MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_SHIFT  (14U)
63713 /*! SLEW_ADJ - Output transition time adjustment. */
63714 #define MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ(x)     (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_MASK)
63715 
63716 #define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_MASK    (0xE0000U)
63717 #define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_SHIFT   (17U)
63718 /*! VBG_ADJ - Bandgap adjustment. */
63719 #define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ(x)      (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_MASK)
63720 /*! @} */
63721 
63722 /*! @name AXI_LIMIT_CONTROL - AXI Limit Control Register */
63723 /*! @{ */
63724 
63725 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_MASK (0x1U)
63726 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_SHIFT (0U)
63727 /*! GPR_AXI_LIMIT_LCDIF0_EN - gpr_axi_limit_lcdif0_en */
63728 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_MASK)
63729 
63730 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_MASK (0x2U)
63731 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_SHIFT (1U)
63732 /*! GPR_AXI_LIMIT_LCDIF1_EN - gpr_axi_limit_lcdif1_en */
63733 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_MASK)
63734 
63735 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_MASK (0x4U)
63736 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_SHIFT (2U)
63737 /*! GPR_AXI_LIMIT_ISI_EN - gpr_axi_limit_isi_en */
63738 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_MASK)
63739 
63740 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_MASK (0x8U)
63741 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_SHIFT (3U)
63742 /*! GPR_AXI_LIMIT_DEWARP_EN - gpr_axi_limit_dewarp_en */
63743 #define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_MASK)
63744 /*! @} */
63745 
63746 /*! @name AXI_LIMIT_THRESH0 - AXI Limit Threshold Register 0 */
63747 /*! @{ */
63748 
63749 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_MASK (0xFFFFU)
63750 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_SHIFT (0U)
63751 /*! GPR_AXI_LIMIT_LCDIF0_THRESH - gpr_axi_limit_lcdif0_thresh */
63752 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_MASK)
63753 
63754 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_MASK (0xFFFF0000U)
63755 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_SHIFT (16U)
63756 /*! GPR_AXI_LIMIT_LCDIF1_THRESH - gpr_axi_limit_lcdif1_thresh */
63757 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_MASK)
63758 /*! @} */
63759 
63760 /*! @name AXI_LIMIT_THRESH1 - AXI Limit Threshold Register 1 */
63761 /*! @{ */
63762 
63763 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_MASK (0xFFFFU)
63764 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_SHIFT (0U)
63765 /*! GPR_AXI_LIMIT_ISI_THRESH - gpr_axi_limit_isi_thresh */
63766 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_MASK)
63767 
63768 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_MASK (0xFFFF0000U)
63769 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_SHIFT (16U)
63770 /*! GPR_AXI_LIMIT_DEWARP_THRESH - gpr_axi_limit_dewarp_thresh */
63771 #define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_MASK)
63772 /*! @} */
63773 
63774 /*! @name ISP_DEWARP_CONTROL - ISP Dewarp Control Register */
63775 /*! @{ */
63776 
63777 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_MASK (0x1U)
63778 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_SHIFT (0U)
63779 /*! GPR_ISP_0_DISABLE - gpr_isp_0_disable */
63780 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_MASK)
63781 
63782 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_MASK (0x2U)
63783 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_SHIFT (1U)
63784 /*! GPR_ISP_1_DISABLE - gpr_isp_1_disable */
63785 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_MASK)
63786 
63787 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_MASK (0x1F8U)
63788 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_SHIFT (3U)
63789 /*! MIPI_ISP_DATA_TYPE - mipi_isp_data_type
63790  *  0b101000..RAW6
63791  *  0b101001..RAW7
63792  *  0b101010..RAW8
63793  *  0b101011..RAW10
63794  *  0b101100..RAW12
63795  *  0b101101..RAW14
63796  */
63797 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_MASK)
63798 
63799 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_MASK (0x200U)
63800 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_SHIFT (9U)
63801 /*! MIPI_ISP_LEFT_JUST_MODE - mipi_isp_left_just_mode */
63802 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_MASK)
63803 
63804 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK (0x7E000U)
63805 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_SHIFT (13U)
63806 /*! MIPI_ISP2_DATA_TYPE - mipi_isp2_data_type
63807  *  0b101000..RAW6
63808  *  0b101001..RAW7
63809  *  0b101010..RAW8
63810  *  0b101011..RAW10
63811  *  0b101100..RAW12
63812  *  0b101101..RAW14
63813  */
63814 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK)
63815 
63816 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_MASK (0x80000U)
63817 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT (19U)
63818 /*! MIPI_ISP2_LEFT_JUST_MODE - mipi_isp2_left_just_mode */
63819 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_MASK)
63820 
63821 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_MASK (0x1800000U)
63822 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_SHIFT (23U)
63823 /*! ISP_ID_MODE - isp_id_mode
63824  *  0b11..vc_id_02 toggle 0,1,2 during no data transmit;
63825  *  0b10..vc_id_01 toggle 0,1 during no data transmit;
63826  *  0b01..vc_id_012 toggle 0,2 during no data transmit;
63827  *  0b00..vc_id_disable; ID will not toggle during no data transmit;
63828  */
63829 #define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_MASK)
63830 /*! @} */
63831 
63832 
63833 /*!
63834  * @}
63835  */ /* end of group MEDIA_BLK_CTRL_Register_Masks */
63836 
63837 
63838 /* MEDIA_BLK_CTRL - Peripheral instance base addresses */
63839 /** Peripheral MEDIA_BLK_CTRL base address */
63840 #define MEDIA_BLK_CTRL_BASE                      (0x32EC0000u)
63841 /** Peripheral MEDIA_BLK_CTRL base pointer */
63842 #define MEDIA_BLK_CTRL                           ((MEDIA_BLK_CTRL_Type *)MEDIA_BLK_CTRL_BASE)
63843 /** Array initializer of MEDIA_BLK_CTRL peripheral base addresses */
63844 #define MEDIA_BLK_CTRL_BASE_ADDRS                { MEDIA_BLK_CTRL_BASE }
63845 /** Array initializer of MEDIA_BLK_CTRL peripheral base pointers */
63846 #define MEDIA_BLK_CTRL_BASE_PTRS                 { MEDIA_BLK_CTRL }
63847 
63848 /*!
63849  * @}
63850  */ /* end of group MEDIA_BLK_CTRL_Peripheral_Access_Layer */
63851 
63852 
63853 /* ----------------------------------------------------------------------------
63854    -- MIPI_CSI Peripheral Access Layer
63855    ---------------------------------------------------------------------------- */
63856 
63857 /*!
63858  * @addtogroup MIPI_CSI_Peripheral_Access_Layer MIPI_CSI Peripheral Access Layer
63859  * @{
63860  */
63861 
63862 /** MIPI_CSI - Register Layout Typedef */
63863 typedef struct {
63864        uint8_t RESERVED_0[4];
63865   __IO uint32_t CSIS_COMMON_CTRL;                  /**< CSIS Common Control Register, offset: 0x4 */
63866   __IO uint32_t CSIS_CLOCK_CTRL;                   /**< CSIS Clock Control Register, offset: 0x8 */
63867        uint8_t RESERVED_1[4];
63868   __IO uint32_t INTERRUPT_MASK_0;                  /**< Interrupt mask register 0, offset: 0x10 */
63869   __IO uint32_t INTERRUPT_SOURCE_0;                /**< Interrupt source register 0, offset: 0x14 */
63870   __IO uint32_t INTERRUPT_MASK_1;                  /**< Interrupt mask register 1, offset: 0x18 */
63871   __IO uint32_t INTERRUPT_SOURCE_1;                /**< Interrupt source register 1, offset: 0x1C */
63872   __IO uint32_t DPHY_STATUS;                       /**< D-PHY status register, offset: 0x20 */
63873   __IO uint32_t DPHY_COMMON_CTRL;                  /**< D-PHY common control register, offset: 0x24 */
63874        uint8_t RESERVED_2[8];
63875   __IO uint32_t DPHY_MASTER_SLAVE_CTRL_LOW;        /**< D-PHY Master and Slave Control register Low, offset: 0x30 */
63876   __IO uint32_t DPHY_MASTER_SLAVE_CTRL_HIGH;       /**< D-PHY Master and Slave Control register HIGH, offset: 0x34 */
63877   __IO uint32_t DPHY_SLAVE_CTRL_LOW;               /**< D-PHY Slave Control register Low, offset: 0x38 */
63878   __IO uint32_t DPHY_SLAVE_CTRL_HIGH;              /**< D-PHY Slave Control register HIGH, offset: 0x3C */
63879   __IO uint32_t ISP_CONFIG;                        /**< ISP Configuration Register, offset: 0x40 */
63880   __IO uint32_t ISP_RESOLUTION;                    /**< ISP Resolution Register, offset: 0x44 */
63881   __IO uint32_t ISP_SYNC;                          /**< ISP SYNC Register, offset: 0x48 */
63882        uint8_t RESERVED_3[52];
63883   __I  uint32_t SHADOW_CONFIG;                     /**< Shadow Configuration Register, offset: 0x80 */
63884   __I  uint32_t SHADOW_RESOLUTION;                 /**< Shadow Resolution Register, offset: 0x84 */
63885   __I  uint32_t SHADOW_SYNC;                       /**< Shadow SYNC Register, offset: 0x88 */
63886        uint8_t RESERVED_4[116];
63887   __IO uint32_t FRAME_COUNTER;                     /**< Frame Counter, offset: 0x100 */
63888        uint8_t RESERVED_5[12];
63889   __IO uint32_t LINE_INTERRUPT_RATIO;              /**< Line Interrupt Ratio, offset: 0x110 */
63890 } MIPI_CSI_Type;
63891 
63892 /* ----------------------------------------------------------------------------
63893    -- MIPI_CSI Register Masks
63894    ---------------------------------------------------------------------------- */
63895 
63896 /*!
63897  * @addtogroup MIPI_CSI_Register_Masks MIPI_CSI Register Masks
63898  * @{
63899  */
63900 
63901 /*! @name CSIS_COMMON_CTRL - CSIS Common Control Register */
63902 /*! @{ */
63903 
63904 #define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK    (0x1U)
63905 #define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT   (0U)
63906 /*! CSI_EN
63907  *  0b0..Disable
63908  *  0b1..Enable
63909  */
63910 #define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK)
63911 
63912 #define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK  (0x2U)
63913 #define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT (1U)
63914 /*! SW_RESET - Software reset
63915  *  0b0..Ready
63916  *  0b1..Reset
63917  */
63918 #define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK)
63919 
63920 #define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK (0x300U)
63921 #define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT (8U)
63922 /*! LANE_NUMBER
63923  *  0b00..1 data lane
63924  *  0b01..2 data lane
63925  *  0b10..3 data lane
63926  *  0b11..4 data lane
63927  */
63928 #define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK)
63929 
63930 #define MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_MASK (0xC00U)
63931 #define MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_SHIFT (10U)
63932 /*! INTERLEAVE_MODE - Select Interleave mode
63933  *  0b00..CH0 only, no data interleave
63934  *  0b01..DT (Data type) only
63935  *  0b10..Reserved
63936  *  0b11..Reserved
63937  */
63938 #define MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_MASK)
63939 
63940 #define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK (0x10000U)
63941 #define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT (16U)
63942 /*! UPDATE_SHADOW - Strobe of updating shadow registers */
63943 #define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK)
63944 /*! @} */
63945 
63946 /*! @name CSIS_CLOCK_CTRL - CSIS Clock Control Register */
63947 /*! @{ */
63948 
63949 #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK (0x10U)
63950 #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT (4U)
63951 /*! CLKGATE_EN
63952  *  0b0..Pixel clock is always alive
63953  *  0b1..Pixel clock is alive during the interval of frame
63954  */
63955 #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT)) & MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK)
63956 
63957 #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK (0xF0000U)
63958 #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT (16U)
63959 /*! CLKGATE_TRAIL - 0 ~ 3 (1~4 Trailing clocks) */
63960 #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT)) & MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK)
63961 /*! @} */
63962 
63963 /*! @name INTERRUPT_MASK_0 - Interrupt mask register 0 */
63964 /*! @{ */
63965 
63966 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK (0x1U)
63967 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT (0U)
63968 /*! MSK_ERR_ID - Unknown ID error
63969  *  0b0..Disable (masked)
63970  *  0b1..Enable (unmasked)
63971  */
63972 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK)
63973 
63974 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK (0x2U)
63975 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT (1U)
63976 /*! MSK_ERR_CRC - CRC error
63977  *  0b0..Disable (masked)
63978  *  0b1..Enable (unmasked)
63979  */
63980 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK)
63981 
63982 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK (0x4U)
63983 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT (2U)
63984 /*! MSK_ERR_ECC - ECC error
63985  *  0b0..Disable (masked)
63986  *  0b1..Enable (unmasked)
63987  */
63988 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK)
63989 
63990 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK (0x8U)
63991 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT (3U)
63992 /*! MSK_ERR_WRONG_CFG - Wrong configuration
63993  *  0b0..Disable (masked)
63994  *  0b1..Enable (unmasked)
63995  */
63996 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK)
63997 
63998 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK (0x10U)
63999 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT (4U)
64000 /*! MSK_ERR_OVER - Image FIFO overflow interrupt
64001  *  0b0..Disable (masked)
64002  *  0b1..Enable (unmasked)
64003  */
64004 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK)
64005 
64006 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK (0x100U)
64007 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT (8U)
64008 /*! MSK_ERR_LOST_FE - Lost of Frame End packet, CH0.
64009  *  0b0..Disable (masked)
64010  *  0b1..Enable (unmasked)
64011  */
64012 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK)
64013 
64014 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK (0x1000U)
64015 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT (12U)
64016 /*! MSK_ERR_LOST_FS - Lost of Frame Start packet, CH0.
64017  *  0b0..Disable (masked)
64018  *  0b1..Enable (unmasked)
64019  */
64020 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK)
64021 
64022 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK (0xF0000U)
64023 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT (16U)
64024 /*! MSK_ERR_SOT_HS - Start of transmission error [Lane3, Lane2, Lane1, Lane0]
64025  *  0b0000..Disable (masked)
64026  *  0b0001..Enable (unmasked)
64027  */
64028 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK)
64029 
64030 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK (0x100000U)
64031 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT (20U)
64032 /*! MSK_FRAMEEND - FE packet is received, CH0.
64033  *  0b0..Disable (masked)
64034  *  0b1..Enable (unmasked)
64035  */
64036 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK)
64037 
64038 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK (0x1000000U)
64039 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT (24U)
64040 /*! MSK_FRAMESTART - FS packet is received, CH0.
64041  *  0b0..Disable (masked)
64042  *  0b1..Enable (unmasked)
64043  */
64044 #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK)
64045 /*! @} */
64046 
64047 /*! @name INTERRUPT_SOURCE_0 - Interrupt source register 0 */
64048 /*! @{ */
64049 
64050 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK  (0x1U)
64051 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT (0U)
64052 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK)
64053 
64054 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK (0x2U)
64055 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT (1U)
64056 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK)
64057 
64058 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK (0x4U)
64059 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT (2U)
64060 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK)
64061 
64062 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK (0x8U)
64063 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT (3U)
64064 /*! ERR_WRONG_CFG - Wrong configuration */
64065 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK)
64066 
64067 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK (0x10U)
64068 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT (4U)
64069 /*! ERR_OVER - Overflow is caused in image FIFO. */
64070 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK)
64071 
64072 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK (0x100U)
64073 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT (8U)
64074 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK)
64075 
64076 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK (0x1000U)
64077 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT (12U)
64078 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK)
64079 
64080 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK (0xF0000U)
64081 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT (16U)
64082 #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK)
64083 
64084 #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK (0x100000U)
64085 #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT (20U)
64086 #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK)
64087 
64088 #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK (0x1000000U)
64089 #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT (24U)
64090 #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK)
64091 /*! @} */
64092 
64093 /*! @name INTERRUPT_MASK_1 - Interrupt mask register 1 */
64094 /*! @{ */
64095 
64096 #define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK (0x1U)
64097 #define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT (0U)
64098 #define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK)
64099 /*! @} */
64100 
64101 /*! @name INTERRUPT_SOURCE_1 - Interrupt source register 1 */
64102 /*! @{ */
64103 
64104 #define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK (0x1U)
64105 #define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT (0U)
64106 #define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK)
64107 /*! @} */
64108 
64109 /*! @name DPHY_STATUS - D-PHY status register */
64110 /*! @{ */
64111 
64112 #define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK   (0x1U)
64113 #define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT  (0U)
64114 /*! STOPSTATECLK
64115  *  0b0..Not Stop state
64116  *  0b1..Stop state
64117  */
64118 #define MIPI_CSI_DPHY_STATUS_STOPSTATECLK(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK)
64119 
64120 #define MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK        (0x2U)
64121 #define MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT       (1U)
64122 /*! ULPSCLK
64123  *  0b0..Not ULPS
64124  *  0b1..ULPS
64125  */
64126 #define MIPI_CSI_DPHY_STATUS_ULPSCLK(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK)
64127 
64128 #define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK   (0xF0U)
64129 #define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT  (4U)
64130 /*! STOPSTATEDAT - Data lane [3:0] is in Stop State
64131  *  0b0000..Not Stop state
64132  *  0b0001..Stop state
64133  */
64134 #define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK)
64135 
64136 #define MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK        (0xF00U)
64137 #define MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT       (8U)
64138 /*! ULPSDAT - Data lane [3:0] is in ULPS
64139  *  0b0000..Not ULPS
64140  *  0b0001..ULPS
64141  */
64142 #define MIPI_CSI_DPHY_STATUS_ULPSDAT(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK)
64143 /*! @} */
64144 
64145 /*! @name DPHY_COMMON_CTRL - D-PHY common control register */
64146 /*! @{ */
64147 
64148 #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK (0x1U)
64149 #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT (0U)
64150 /*! ENABLE_CLK
64151  *  0b0..Disable
64152  *  0b1..Enable
64153  */
64154 #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK)
64155 
64156 #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK (0x1EU)
64157 #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT (1U)
64158 /*! ENABLE_DAT - D-PHY enable
64159  *  0b0000..Disable
64160  *  0b0001..Enable
64161  */
64162 #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK)
64163 
64164 #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK (0x20U)
64165 #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT (5U)
64166 /*! S_DPDN_SWAP_DAT - Swapping Dp and Dn channel of data lanes.
64167  *  0b0..Default
64168  *  0b1..Swapped
64169  */
64170 #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK)
64171 
64172 #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK (0x40U)
64173 #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT (6U)
64174 /*! S_DPDN_SWAP_CLK
64175  *  0b0..Default
64176  *  0b1..Swapped
64177  */
64178 #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK)
64179 
64180 #define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK (0xC00000U)
64181 #define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT (22U)
64182 /*! S_CLKSETTLECTL - Slave clock lane control for Tclk-settle */
64183 #define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK)
64184 
64185 #define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK  (0xFF000000U)
64186 #define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT (24U)
64187 /*! HSSETTLE - HS-RX settle time control */
64188 #define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK)
64189 /*! @} */
64190 
64191 /*! @name DPHY_MASTER_SLAVE_CTRL_LOW - D-PHY Master and Slave Control register Low */
64192 /*! @{ */
64193 
64194 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK (0x3FFU)
64195 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT (0U)
64196 /*! B_DPHYCTRL - ULPS EXIT Counter Value Control. You should set B_DPHYCTL[9:0] during initial or power-up sequence */
64197 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK)
64198 
64199 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_MASK (0x400U)
64200 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_SHIFT (10U)
64201 /*! TXTRIGGER_CLK_EN - TxTrigger_Clk Enable */
64202 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_MASK)
64203 
64204 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_MASK (0x800U)
64205 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_SHIFT (11U)
64206 /*! ERRCONTENTION_LP_EN - ErrContention LP Enable */
64207 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_MASK)
64208 
64209 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_MASK (0x1000U)
64210 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_SHIFT (12U)
64211 /*! BGR_CHOPPER_EN - BGR Chopper Function Enable */
64212 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_MASK)
64213 
64214 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_MASK (0x2000U)
64215 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_SHIFT (13U)
64216 /*! LP_CD_HYS - LP-CD Hysteresis Level Control */
64217 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_MASK)
64218 
64219 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_MASK (0x4000U)
64220 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_SHIFT (14U)
64221 /*! MSTRCLK_LP_SLEW_RATE_UP - Master Clock Lane's LP-TX Driver Slew Rate Up Control */
64222 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_MASK)
64223 
64224 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_MASK (0x18000U)
64225 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_SHIFT (15U)
64226 /*! MSTRCLK_LP_SLEW_RATE_DOWN - Master Clock Lane's LP-TX Driver Slew Rate Down Control */
64227 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_MASK)
64228 
64229 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_MASK (0x20000U)
64230 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_SHIFT (17U)
64231 /*! LP_RX_PULSE_REJECT - LP-RX Pulse Rejection Control */
64232 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_MASK)
64233 
64234 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_MASK (0xC0000U)
64235 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_SHIFT (18U)
64236 /*! LP_RX_VREF_LVL - LP-RX Vref Level Control */
64237 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_MASK)
64238 
64239 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_MASK (0x100000U)
64240 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_SHIFT (20U)
64241 /*! VREF_SRC_SEL - Vref Source Selection */
64242 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_MASK)
64243 
64244 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_MASK (0x600000U)
64245 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_SHIFT (21U)
64246 /*! LP_RX_HYS_LVL - LP-RX Hysteresis Level Control */
64247 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_MASK)
64248 
64249 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_MASK (0x800000U)
64250 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_SHIFT (23U)
64251 /*! REG_1P2_LVL_SEL - 1.2V Regulator Valid Level Selection */
64252 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_MASK)
64253 
64254 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_MASK (0x3000000U)
64255 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_SHIFT (24U)
64256 /*! REG_1P2_LVL_CTL - 1.2V Regulator Level Control (No regulator in JF) */
64257 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_MASK)
64258 
64259 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_MASK (0x4000000U)
64260 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_SHIFT (26U)
64261 /*! VREG12_EXTPWR_EN_CTL - VREG12_EXTPWR Enable Control (No regulator in JF) */
64262 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_MASK)
64263 
64264 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_MASK (0x8000000U)
64265 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_SHIFT (27U)
64266 /*! BGR_CHOPPER_FREQ - BGR Chopper Frequency Control */
64267 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_MASK)
64268 
64269 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_MASK (0x30000000U)
64270 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_SHIFT (28U)
64271 /*! BIAS_REF_VOLT - Bias Reference Voltage 710m Control */
64272 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_MASK)
64273 
64274 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_MASK (0xC0000000U)
64275 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_SHIFT (30U)
64276 /*! USER_DATA_PATTERN_LOW - User Data Pattern for HS Loopback mode */
64277 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_MASK)
64278 /*! @} */
64279 
64280 /*! @name DPHY_MASTER_SLAVE_CTRL_HIGH - D-PHY Master and Slave Control register HIGH */
64281 /*! @{ */
64282 
64283 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_MASK (0x3FU)
64284 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_SHIFT (0U)
64285 /*! USER_DATA_PATTERN_HIGH - User Data Pattern for HS Loopback mode */
64286 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_MASK)
64287 
64288 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_MASK (0xC0U)
64289 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_SHIFT (6U)
64290 /*! HS_LOOPBACK_MODE_CTL - HS Loopback Mode Control */
64291 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_MASK)
64292 
64293 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_MASK (0x300U)
64294 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_SHIFT (8U)
64295 /*! BGR_VOLT_TUNE - BGR voltage tuning control */
64296 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_MASK)
64297 
64298 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_MASK (0x800U)
64299 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_SHIFT (11U)
64300 /*! DCC_DONE - DCC "DONE" Signal Control */
64301 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_MASK)
64302 
64303 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_MASK (0x2000U)
64304 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_SHIFT (13U)
64305 /*! RX_SKEW_CALIB_FIX_EN - RX Skew Calibration Fixing Code Enable/Disable Control */
64306 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_MASK)
64307 
64308 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_MASK (0x4000U)
64309 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_SHIFT (14U)
64310 /*! LP_REG_VREF_SRC_SEL - LP Regulator Vref Source Selection (No regulator in JF) */
64311 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_MASK)
64312 
64313 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_MASK (0x100000U)
64314 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_SHIFT (20U)
64315 /*! MST_DATA0_TX_SLEW_UP - Master Data0 Lane's LP-TX Driver Slew Rate Up Control */
64316 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_MASK)
64317 
64318 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_MASK (0x600000U)
64319 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_SHIFT (21U)
64320 /*! MST_DATA0_TX_SLEW_DOWN - Master Data0 Lane's LP-TX Driver Slew Rate Down Control */
64321 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_MASK)
64322 
64323 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_MASK (0x800000U)
64324 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_SHIFT (23U)
64325 /*! MST_DATA1_TX_SLEW_UP - Master Data1 Lane's LP-TX Driver Slew Rate Up Control */
64326 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_MASK)
64327 
64328 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_MASK (0x3000000U)
64329 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_SHIFT (24U)
64330 /*! MST_DATA1_TX_SLEW_DOWN - Master Data1 Lane's LP-TX Driver Slew Rate Down Control */
64331 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_MASK)
64332 
64333 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_MASK (0x4000000U)
64334 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_SHIFT (26U)
64335 /*! MST_DATA2_TX_SLEW_UP - Master Data2 Lane's LP-TX Driver Slew Rate Up Control */
64336 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_MASK)
64337 
64338 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_MASK (0x18000000U)
64339 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_SHIFT (27U)
64340 /*! MST_DATA2_TX_SLEW_DOWN - Master Data2 Lane's LP-TX Driver Slew Rate Down Control */
64341 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_MASK)
64342 
64343 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_MASK (0x20000000U)
64344 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_SHIFT (29U)
64345 /*! MST_DATA3_TX_SLEW_UP - Master Data3 Lane's LP-TX Driver Slew Rate Up Control */
64346 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_MASK)
64347 
64348 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_MASK (0xC0000000U)
64349 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_SHIFT (30U)
64350 /*! MST_DATA3_TX_SLEW_DOWN - Master Data3 Lane's LP-TX Driver Slew Rate Down Control */
64351 #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_MASK)
64352 /*! @} */
64353 
64354 /*! @name DPHY_SLAVE_CTRL_LOW - D-PHY Slave Control register Low */
64355 /*! @{ */
64356 
64357 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_MASK (0x3U)
64358 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_SHIFT (0U)
64359 /*! HS_RX_BIAS - HS RX Bias Control */
64360 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_MASK)
64361 
64362 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_MASK (0xCU)
64363 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_SHIFT (2U)
64364 /*! CLK_LANE_HS_RX_DELAY - Clock Lane HS RX Delay Control */
64365 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_MASK)
64366 
64367 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_MASK (0x30U)
64368 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_SHIFT (4U)
64369 /*! DATA_LANE_HS_RX_DELAY - Data Lane HS RX Delay Control */
64370 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_MASK)
64371 
64372 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_MASK (0xC0U)
64373 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_SHIFT (6U)
64374 /*! HS_RX_TERMINATION_IMPEDENCE - HS-RX Termination Impedance Control */
64375 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_MASK)
64376 
64377 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_MASK (0x300U)
64378 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_SHIFT (8U)
64379 /*! CLOCK_LANE_CAP_TCLK_SETTLE - Clock Lane Cap. Value Control for Tclk-settle */
64380 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_MASK)
64381 
64382 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_MASK (0xC00U)
64383 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_SHIFT (10U)
64384 /*! CLOCK_LANE_CAP_TCLK_MISS - Clock Lane Cap. Value Control for Tclk_miss */
64385 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_MASK)
64386 
64387 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_MASK (0x1000U)
64388 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_SHIFT (12U)
64389 /*! CLK_MISS_EN - Clock Miss Function Enable/Disable Control */
64390 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_MASK)
64391 
64392 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_MASK (0x6000U)
64393 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_SHIFT (13U)
64394 /*! ANA_TIMER_HYS - Analog Timer Hysteresis Control */
64395 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_MASK)
64396 
64397 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_MASK (0x30000U)
64398 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_SHIFT (16U)
64399 /*! DCC_CCO_GAIN - DCC CCO Gain Control */
64400 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_MASK)
64401 
64402 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_MASK (0x70000000U)
64403 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_SHIFT (28U)
64404 /*! DCC_INIT_TOLERANCE - DCC Initial Tolerance */
64405 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_MASK)
64406 
64407 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_MASK (0x80000000U)
64408 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_SHIFT (31U)
64409 /*! DCC_STABLE - DCC Stable Control */
64410 #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_MASK)
64411 /*! @} */
64412 
64413 /*! @name DPHY_SLAVE_CTRL_HIGH - D-PHY Slave Control register HIGH */
64414 /*! @{ */
64415 
64416 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_MASK (0x1U)
64417 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_SHIFT (0U)
64418 /*! DCC_EN - DCC Function Enable/Disable Control */
64419 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_MASK)
64420 
64421 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_MASK (0x2U)
64422 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_SHIFT (1U)
64423 /*! SKEW_CALIB_EN - Skew Calibration Function Enable/Disable Control */
64424 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_MASK)
64425 
64426 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_MASK (0xFCU)
64427 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_SHIFT (2U)
64428 /*! RX_SKEW_CALIB_MAX - RX Skew Calibration Max Code Control */
64429 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_MASK)
64430 
64431 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_MASK (0x3F00U)
64432 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_SHIFT (8U)
64433 /*! RX_SKEW_CALIB_FAIL_MIN - RX Skew Calibration Fail-min Control */
64434 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_MASK)
64435 
64436 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_MASK (0x3F0000U)
64437 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_SHIFT (16U)
64438 /*! RX_SKEW_CALIB_PASS_MIN - RX Skew Calibration Pass-min Control */
64439 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_MASK)
64440 
64441 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_MASK (0x3000000U)
64442 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_SHIFT (24U)
64443 /*! RX_SKEW_CALIB_FAIL_TOLERANCE - RX Skew Calibration Fail-tolerance Control */
64444 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_MASK)
64445 
64446 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_MASK (0xC000000U)
64447 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_SHIFT (26U)
64448 /*! RX_SKEW_CALIB_COMPARE_WAIT_TIME - RX Skew Calibration Compare-wait time Control */
64449 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_MASK)
64450 
64451 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_MASK (0xF0000000U)
64452 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_SHIFT (28U)
64453 /*! RX_SKEW_CALIB_COMPARE_RUN_TIME - RX Skew Calibration Compare-run time Control */
64454 #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_MASK)
64455 /*! @} */
64456 
64457 /*! @name ISP_CONFIG - ISP Configuration Register */
64458 /*! @{ */
64459 
64460 #define MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK      (0xFCU)
64461 #define MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT     (2U)
64462 /*! DATAFORMAT - Image Data Format */
64463 #define MIPI_CSI_ISP_CONFIG_DATAFORMAT(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK)
64464 
64465 #define MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK        (0x400U)
64466 #define MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT       (10U)
64467 /*! RGB_SWAP
64468  *  0b0..MSB is R and LSB is B
64469  *  0b1..MSB is B and LSB is R (swapped)
64470  */
64471 #define MIPI_CSI_ISP_CONFIG_RGB_SWAP(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT)) & MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK)
64472 
64473 #define MIPI_CSI_ISP_CONFIG_PARALLEL_MASK        (0x800U)
64474 #define MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT       (11U)
64475 /*! PARALLEL - Output bus width of CH0 is 32 bits.
64476  *  0b0..Normal output
64477  *  0b1..32bit data alignment
64478  */
64479 #define MIPI_CSI_ISP_CONFIG_PARALLEL(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT)) & MIPI_CSI_ISP_CONFIG_PARALLEL_MASK)
64480 
64481 #define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK      (0x3000U)
64482 #define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT     (12U)
64483 /*! PIXEL_MODE - Pixel mode selection, */
64484 #define MIPI_CSI_ISP_CONFIG_PIXEL_MODE(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK)
64485 /*! @} */
64486 
64487 /*! @name ISP_RESOLUTION - ISP Resolution Register */
64488 /*! @{ */
64489 
64490 #define MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK      (0xFFFFU)
64491 #define MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT     (0U)
64492 /*! HRESOL - Horizontal Image resolution */
64493 #define MIPI_CSI_ISP_RESOLUTION_HRESOL(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK)
64494 
64495 #define MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK      (0xFFFF0000U)
64496 #define MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT     (16U)
64497 /*! VRESOL - Vertical Image resolution */
64498 #define MIPI_CSI_ISP_RESOLUTION_VRESOL(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK)
64499 /*! @} */
64500 
64501 /*! @name ISP_SYNC - ISP SYNC Register */
64502 /*! @{ */
64503 
64504 #define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK       (0xFC0000U)
64505 #define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT      (18U)
64506 #define MIPI_CSI_ISP_SYNC_HSYNC_LINTV(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT)) & MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK)
64507 /*! @} */
64508 
64509 /*! @name SHADOW_CONFIG - Shadow Configuration Register */
64510 /*! @{ */
64511 
64512 #define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK   (0xFCU)
64513 #define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT  (2U)
64514 #define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK)
64515 
64516 #define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK (0x400U)
64517 #define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT (10U)
64518 #define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK)
64519 
64520 #define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK (0x800U)
64521 #define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT (11U)
64522 #define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK)
64523 
64524 #define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK   (0x3000U)
64525 #define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT  (12U)
64526 #define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK)
64527 /*! @} */
64528 
64529 /*! @name SHADOW_RESOLUTION - Shadow Resolution Register */
64530 /*! @{ */
64531 
64532 #define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK (0xFFFFU)
64533 #define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT (0U)
64534 #define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT)) & MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK)
64535 
64536 #define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK (0xFFFF0000U)
64537 #define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT (16U)
64538 #define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT)) & MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK)
64539 /*! @} */
64540 
64541 /*! @name SHADOW_SYNC - Shadow SYNC Register */
64542 /*! @{ */
64543 
64544 #define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK (0xFC0000U)
64545 #define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT (18U)
64546 #define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT)) & MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK)
64547 /*! @} */
64548 
64549 /*! @name FRAME_COUNTER - Frame Counter */
64550 /*! @{ */
64551 
64552 #define MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK      (0xFFFFFFFFU)
64553 #define MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT     (0U)
64554 #define MIPI_CSI_FRAME_COUNTER_FRM_CNT(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT)) & MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK)
64555 /*! @} */
64556 
64557 /*! @name LINE_INTERRUPT_RATIO - Line Interrupt Ratio */
64558 /*! @{ */
64559 
64560 #define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK (0xFFFFFFFFU)
64561 #define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT (0U)
64562 #define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT)) & MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK)
64563 /*! @} */
64564 
64565 
64566 /*!
64567  * @}
64568  */ /* end of group MIPI_CSI_Register_Masks */
64569 
64570 
64571 /* MIPI_CSI - Peripheral instance base addresses */
64572 /** Peripheral MIPI_CSI1 base address */
64573 #define MIPI_CSI1_BASE                           (0x32E40000u)
64574 /** Peripheral MIPI_CSI1 base pointer */
64575 #define MIPI_CSI1                                ((MIPI_CSI_Type *)MIPI_CSI1_BASE)
64576 /** Peripheral MIPI_CSI2 base address */
64577 #define MIPI_CSI2_BASE                           (0x32E50000u)
64578 /** Peripheral MIPI_CSI2 base pointer */
64579 #define MIPI_CSI2                                ((MIPI_CSI_Type *)MIPI_CSI2_BASE)
64580 /** Array initializer of MIPI_CSI peripheral base addresses */
64581 #define MIPI_CSI_BASE_ADDRS                      { MIPI_CSI1_BASE, MIPI_CSI2_BASE }
64582 /** Array initializer of MIPI_CSI peripheral base pointers */
64583 #define MIPI_CSI_BASE_PTRS                       { MIPI_CSI1, MIPI_CSI2 }
64584 
64585 /*!
64586  * @}
64587  */ /* end of group MIPI_CSI_Peripheral_Access_Layer */
64588 
64589 
64590 /* ----------------------------------------------------------------------------
64591    -- MIPI_DSI Peripheral Access Layer
64592    ---------------------------------------------------------------------------- */
64593 
64594 /*!
64595  * @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer
64596  * @{
64597  */
64598 
64599 /** MIPI_DSI - Register Layout Typedef */
64600 typedef struct {
64601   __I  uint32_t DSI_VERSION;                       /**< Specifies the DSI version register., offset: 0x0 */
64602   __I  uint32_t DSI_STATUS;                        /**< Specifies the status register., offset: 0x4 */
64603   __I  uint32_t DSI_RGB_STATUS;                    /**< Specifies the RGB FSM status register., offset: 0x8 */
64604   __IO uint32_t DSI_SWRST;                         /**< Specifies the software reset register., offset: 0xC */
64605   __IO uint32_t DSI_CLKCTRL;                       /**< Specifies the clock control register., offset: 0x10 */
64606   __IO uint32_t DSI_TIMEOUT;                       /**< Specifies the time out register., offset: 0x14 */
64607   __IO uint32_t DSI_CONFIG;                        /**< Specifies the configuration register., offset: 0x18 */
64608   __IO uint32_t DSI_ESCMODE;                       /**< Specifies the escape mode register., offset: 0x1C */
64609   __IO uint32_t DSI_MDRESOL;                       /**< Specifies the main display image resolution register., offset: 0x20 */
64610   __IO uint32_t DSI_MVPORCH;                       /**< Specifies the main display Vporch register., offset: 0x24 */
64611   __IO uint32_t DSI_MHPORCH;                       /**< Specifies the main display Hporch register., offset: 0x28 */
64612   __IO uint32_t DSI_MSYNC;                         /**< Specifies the main display Sync Area register., offset: 0x2C */
64613   __IO uint32_t DSI_SDRESOL;                       /**< Specifies the sub display image resolution register., offset: 0x30 */
64614   __IO uint32_t DSI_INTSRC;                        /**< Specifies the interrupt source register., offset: 0x34 */
64615   __IO uint32_t DSI_INTMSK;                        /**< Specifies the interrupt mask register., offset: 0x38 */
64616   __O  uint32_t DSI_PKTHDR;                        /**< Specifies the packet header FIFO register., offset: 0x3C */
64617   __O  uint32_t DSI_PAYLOAD;                       /**< Specifies the payload FIFO register., offset: 0x40 */
64618   __I  uint32_t DSI_RXFIFO;                        /**< Specifies the read FIFO register., offset: 0x44 */
64619   __IO uint32_t DSI_FIFOTHLD;                      /**< Specifies the FIFO threshold level register., offset: 0x48 */
64620   __IO uint32_t DSI_FIFOCTRL;                      /**< Specifies the FIFO status and control register., offset: 0x4C */
64621   __IO uint32_t DSI_MEMACCHR;                      /**< Specifies the FIFO memory AC characteristic register., offset: 0x50 */
64622        uint8_t RESERVED_0[36];
64623   __IO uint32_t DSI_MULTI_PKT;                     /**< Specifies the Multi Packet, Packet Go register., offset: 0x78 */
64624        uint8_t RESERVED_1[20];
64625   __IO uint32_t DSI_PLLCTRL_1G;                    /**< Specifies the 1Gbps D-PHY PLL control register., offset: 0x90 */
64626   __IO uint32_t DSI_PLLCTRL;                       /**< Specifies the PLL control register., offset: 0x94 */
64627   __IO uint32_t DSI_PLLCTRL1;                      /**< Specifies the PLL control register 1., offset: 0x98 */
64628   __IO uint32_t DSI_PLLCTRL2;                      /**< Specifies the PLL control register 2., offset: 0x9C */
64629   __IO uint32_t DSI_PLLTMR;                        /**< Specifies the PLL timer register., offset: 0xA0 */
64630   __IO uint32_t DSI_PHYCTRL_B1;                    /**< Specifies the D-PHY control register 1., offset: 0xA4 */
64631   __IO uint32_t DSI_PHYCTRL_B2;                    /**< Specifies the D-PHY control register 2., offset: 0xA8 */
64632   __IO uint32_t DSI_PHYCTRL_M1;                    /**< Specifies the D-PHY control register 1., offset: 0xAC */
64633   __IO uint32_t DSI_PHYCTRL_M2;                    /**< Specifies the D-PHY control register 2., offset: 0xB0 */
64634   __IO uint32_t DSI_PHYTIMING;                     /**< Specifies the D-PHY timing register., offset: 0xB4 */
64635   __IO uint32_t DSI_PHYTIMING1;                    /**< Specifies the D-PHY timing register 1., offset: 0xB8 */
64636   __IO uint32_t DSI_PHYTIMING2;                    /**< Specifies the D-PHY timing register 2., offset: 0xBC */
64637 } MIPI_DSI_Type;
64638 
64639 /* ----------------------------------------------------------------------------
64640    -- MIPI_DSI Register Masks
64641    ---------------------------------------------------------------------------- */
64642 
64643 /*!
64644  * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks
64645  * @{
64646  */
64647 
64648 /*! @name DSI_VERSION - Specifies the DSI version register. */
64649 /*! @{ */
64650 
64651 #define MIPI_DSI_DSI_VERSION_VERSION_MASK        (0xFFFFFFFFU)
64652 #define MIPI_DSI_DSI_VERSION_VERSION_SHIFT       (0U)
64653 #define MIPI_DSI_DSI_VERSION_VERSION(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_VERSION_VERSION_SHIFT)) & MIPI_DSI_DSI_VERSION_VERSION_MASK)
64654 /*! @} */
64655 
64656 /*! @name DSI_STATUS - Specifies the status register. */
64657 /*! @{ */
64658 
64659 #define MIPI_DSI_DSI_STATUS_STOPSTATEDAT_MASK    (0xFU)
64660 #define MIPI_DSI_DSI_STATUS_STOPSTATEDAT_SHIFT   (0U)
64661 #define MIPI_DSI_DSI_STATUS_STOPSTATEDAT(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_STOPSTATEDAT_SHIFT)) & MIPI_DSI_DSI_STATUS_STOPSTATEDAT_MASK)
64662 
64663 #define MIPI_DSI_DSI_STATUS_ULPSDAT_MASK         (0xF0U)
64664 #define MIPI_DSI_DSI_STATUS_ULPSDAT_SHIFT        (4U)
64665 #define MIPI_DSI_DSI_STATUS_ULPSDAT(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_ULPSDAT_SHIFT)) & MIPI_DSI_DSI_STATUS_ULPSDAT_MASK)
64666 
64667 #define MIPI_DSI_DSI_STATUS_STOPSTATECLK_MASK    (0x100U)
64668 #define MIPI_DSI_DSI_STATUS_STOPSTATECLK_SHIFT   (8U)
64669 #define MIPI_DSI_DSI_STATUS_STOPSTATECLK(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_STOPSTATECLK_SHIFT)) & MIPI_DSI_DSI_STATUS_STOPSTATECLK_MASK)
64670 
64671 #define MIPI_DSI_DSI_STATUS_ULPSCLK_MASK         (0x200U)
64672 #define MIPI_DSI_DSI_STATUS_ULPSCLK_SHIFT        (9U)
64673 #define MIPI_DSI_DSI_STATUS_ULPSCLK(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_ULPSCLK_SHIFT)) & MIPI_DSI_DSI_STATUS_ULPSCLK_MASK)
64674 
64675 #define MIPI_DSI_DSI_STATUS_TXREADYHSCLK_MASK    (0x400U)
64676 #define MIPI_DSI_DSI_STATUS_TXREADYHSCLK_SHIFT   (10U)
64677 #define MIPI_DSI_DSI_STATUS_TXREADYHSCLK(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_TXREADYHSCLK_SHIFT)) & MIPI_DSI_DSI_STATUS_TXREADYHSCLK_MASK)
64678 
64679 #define MIPI_DSI_DSI_STATUS_DIRECTION_MASK       (0x10000U)
64680 #define MIPI_DSI_DSI_STATUS_DIRECTION_SHIFT      (16U)
64681 #define MIPI_DSI_DSI_STATUS_DIRECTION(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_DIRECTION_SHIFT)) & MIPI_DSI_DSI_STATUS_DIRECTION_MASK)
64682 
64683 #define MIPI_DSI_DSI_STATUS_SWRSTRLS_MASK        (0x100000U)
64684 #define MIPI_DSI_DSI_STATUS_SWRSTRLS_SHIFT       (20U)
64685 #define MIPI_DSI_DSI_STATUS_SWRSTRLS(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_SWRSTRLS_SHIFT)) & MIPI_DSI_DSI_STATUS_SWRSTRLS_MASK)
64686 
64687 #define MIPI_DSI_DSI_STATUS_PLLSTABLE_MASK       (0x80000000U)
64688 #define MIPI_DSI_DSI_STATUS_PLLSTABLE_SHIFT      (31U)
64689 #define MIPI_DSI_DSI_STATUS_PLLSTABLE(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_PLLSTABLE_SHIFT)) & MIPI_DSI_DSI_STATUS_PLLSTABLE_MASK)
64690 /*! @} */
64691 
64692 /*! @name DSI_RGB_STATUS - Specifies the RGB FSM status register. */
64693 /*! @{ */
64694 
64695 #define MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_MASK    (0x1FFFU)
64696 #define MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_SHIFT   (0U)
64697 #define MIPI_DSI_DSI_RGB_STATUS_RGBSTATE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_SHIFT)) & MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_MASK)
64698 
64699 #define MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_MASK (0x80000000U)
64700 #define MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_SHIFT (31U)
64701 #define MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_SHIFT)) & MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_MASK)
64702 /*! @} */
64703 
64704 /*! @name DSI_SWRST - Specifies the software reset register. */
64705 /*! @{ */
64706 
64707 #define MIPI_DSI_DSI_SWRST_SWRST_MASK            (0x1U)
64708 #define MIPI_DSI_DSI_SWRST_SWRST_SHIFT           (0U)
64709 #define MIPI_DSI_DSI_SWRST_SWRST(x)              (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_SWRST_SHIFT)) & MIPI_DSI_DSI_SWRST_SWRST_MASK)
64710 
64711 #define MIPI_DSI_DSI_SWRST_FUNCRST_MASK          (0x10000U)
64712 #define MIPI_DSI_DSI_SWRST_FUNCRST_SHIFT         (16U)
64713 #define MIPI_DSI_DSI_SWRST_FUNCRST(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_FUNCRST_SHIFT)) & MIPI_DSI_DSI_SWRST_FUNCRST_MASK)
64714 /*! @} */
64715 
64716 /*! @name DSI_CLKCTRL - Specifies the clock control register. */
64717 /*! @{ */
64718 
64719 #define MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_MASK   (0xFFFFU)
64720 #define MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_SHIFT  (0U)
64721 #define MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_MASK)
64722 
64723 #define MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_MASK   (0xF80000U)
64724 #define MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT  (19U)
64725 #define MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_MASK)
64726 
64727 #define MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_MASK      (0x1000000U)
64728 #define MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_SHIFT     (24U)
64729 #define MIPI_DSI_DSI_CLKCTRL_BYTECLKEN(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_MASK)
64730 
64731 #define MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_MASK     (0x6000000U)
64732 #define MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_SHIFT    (25U)
64733 #define MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_MASK)
64734 
64735 #define MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_MASK      (0x8000000U)
64736 #define MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_SHIFT     (27U)
64737 #define MIPI_DSI_DSI_CLKCTRL_PLLBYPASS(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_MASK)
64738 
64739 #define MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_MASK       (0x10000000U)
64740 #define MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_SHIFT      (28U)
64741 #define MIPI_DSI_DSI_CLKCTRL_ESCCLKEN(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_MASK)
64742 
64743 #define MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_MASK       (0x20000000U)
64744 #define MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_SHIFT      (29U)
64745 #define MIPI_DSI_DSI_CLKCTRL_DPHY_SEL(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_MASK)
64746 
64747 #define MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_MASK (0x80000000U)
64748 #define MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_SHIFT (31U)
64749 #define MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_MASK)
64750 /*! @} */
64751 
64752 /*! @name DSI_TIMEOUT - Specifies the time out register. */
64753 /*! @{ */
64754 
64755 #define MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_MASK       (0xFFFFU)
64756 #define MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_SHIFT      (0U)
64757 #define MIPI_DSI_DSI_TIMEOUT_LPDRTOUT(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_MASK)
64758 
64759 #define MIPI_DSI_DSI_TIMEOUT_BTATOUT_MASK        (0xFF0000U)
64760 #define MIPI_DSI_DSI_TIMEOUT_BTATOUT_SHIFT       (16U)
64761 #define MIPI_DSI_DSI_TIMEOUT_BTATOUT(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_BTATOUT_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_BTATOUT_MASK)
64762 /*! @} */
64763 
64764 /*! @name DSI_CONFIG - Specifies the configuration register. */
64765 /*! @{ */
64766 
64767 #define MIPI_DSI_DSI_CONFIG_LANEEN_MASK          (0x1FU)
64768 #define MIPI_DSI_DSI_CONFIG_LANEEN_SHIFT         (0U)
64769 #define MIPI_DSI_DSI_CONFIG_LANEEN(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_LANEEN_SHIFT)) & MIPI_DSI_DSI_CONFIG_LANEEN_MASK)
64770 
64771 #define MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_MASK    (0x60U)
64772 #define MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_SHIFT   (5U)
64773 #define MIPI_DSI_DSI_CONFIG_NUMOFDATLANE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_SHIFT)) & MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_MASK)
64774 
64775 #define MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_MASK    (0x700U)
64776 #define MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_SHIFT   (8U)
64777 #define MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_SHIFT)) & MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_MASK)
64778 
64779 #define MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_MASK   (0x7000U)
64780 #define MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_SHIFT  (12U)
64781 #define MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_SHIFT)) & MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_MASK)
64782 
64783 #define MIPI_DSI_DSI_CONFIG_SUBVC_MASK           (0x30000U)
64784 #define MIPI_DSI_DSI_CONFIG_SUBVC_SHIFT          (16U)
64785 #define MIPI_DSI_DSI_CONFIG_SUBVC(x)             (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SUBVC_SHIFT)) & MIPI_DSI_DSI_CONFIG_SUBVC_MASK)
64786 
64787 #define MIPI_DSI_DSI_CONFIG_MAINVC_MASK          (0xC0000U)
64788 #define MIPI_DSI_DSI_CONFIG_MAINVC_SHIFT         (18U)
64789 #define MIPI_DSI_DSI_CONFIG_MAINVC(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MAINVC_SHIFT)) & MIPI_DSI_DSI_CONFIG_MAINVC_MASK)
64790 
64791 #define MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_MASK  (0x100000U)
64792 #define MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_SHIFT (20U)
64793 #define MIPI_DSI_DSI_CONFIG_HSADISABLEMODE(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_MASK)
64794 
64795 #define MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_MASK  (0x200000U)
64796 #define MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_SHIFT (21U)
64797 #define MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_MASK)
64798 
64799 #define MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_MASK  (0x400000U)
64800 #define MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_SHIFT (22U)
64801 #define MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_MASK)
64802 
64803 #define MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_MASK  (0x800000U)
64804 #define MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_SHIFT (23U)
64805 #define MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_MASK)
64806 
64807 #define MIPI_DSI_DSI_CONFIG_AUTOMODE_MASK        (0x1000000U)
64808 #define MIPI_DSI_DSI_CONFIG_AUTOMODE_SHIFT       (24U)
64809 #define MIPI_DSI_DSI_CONFIG_AUTOMODE(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_AUTOMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_AUTOMODE_MASK)
64810 
64811 #define MIPI_DSI_DSI_CONFIG_VIDEOMODE_MASK       (0x2000000U)
64812 #define MIPI_DSI_DSI_CONFIG_VIDEOMODE_SHIFT      (25U)
64813 #define MIPI_DSI_DSI_CONFIG_VIDEOMODE(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_VIDEOMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_VIDEOMODE_MASK)
64814 
64815 #define MIPI_DSI_DSI_CONFIG_BURSTMODE_MASK       (0x4000000U)
64816 #define MIPI_DSI_DSI_CONFIG_BURSTMODE_SHIFT      (26U)
64817 #define MIPI_DSI_DSI_CONFIG_BURSTMODE(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_BURSTMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_BURSTMODE_MASK)
64818 
64819 #define MIPI_DSI_DSI_CONFIG_SYNCINFORM_MASK      (0x8000000U)
64820 #define MIPI_DSI_DSI_CONFIG_SYNCINFORM_SHIFT     (27U)
64821 #define MIPI_DSI_DSI_CONFIG_SYNCINFORM(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SYNCINFORM_SHIFT)) & MIPI_DSI_DSI_CONFIG_SYNCINFORM_MASK)
64822 
64823 #define MIPI_DSI_DSI_CONFIG_EOT_R03_MASK         (0x10000000U)
64824 #define MIPI_DSI_DSI_CONFIG_EOT_R03_SHIFT        (28U)
64825 #define MIPI_DSI_DSI_CONFIG_EOT_R03(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_EOT_R03_SHIFT)) & MIPI_DSI_DSI_CONFIG_EOT_R03_MASK)
64826 
64827 #define MIPI_DSI_DSI_CONFIG_MFLUSH_VS_MASK       (0x20000000U)
64828 #define MIPI_DSI_DSI_CONFIG_MFLUSH_VS_SHIFT      (29U)
64829 #define MIPI_DSI_DSI_CONFIG_MFLUSH_VS(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MFLUSH_VS_SHIFT)) & MIPI_DSI_DSI_CONFIG_MFLUSH_VS_MASK)
64830 
64831 #define MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_MASK (0x40000000U)
64832 #define MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_SHIFT (30U)
64833 #define MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_SHIFT)) & MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_MASK)
64834 
64835 #define MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_MASK (0x80000000U)
64836 #define MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_SHIFT (31U)
64837 #define MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_SHIFT)) & MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_MASK)
64838 /*! @} */
64839 
64840 /*! @name DSI_ESCMODE - Specifies the escape mode register. */
64841 /*! @{ */
64842 
64843 #define MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_MASK  (0x1U)
64844 #define MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_SHIFT (0U)
64845 #define MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_MASK)
64846 
64847 #define MIPI_DSI_DSI_ESCMODE_TXULPSCLK_MASK      (0x2U)
64848 #define MIPI_DSI_DSI_ESCMODE_TXULPSCLK_SHIFT     (1U)
64849 #define MIPI_DSI_DSI_ESCMODE_TXULPSCLK(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSCLK_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSCLK_MASK)
64850 
64851 #define MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_MASK     (0x4U)
64852 #define MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_SHIFT    (2U)
64853 #define MIPI_DSI_DSI_ESCMODE_TXULPSEXIT(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_MASK)
64854 
64855 #define MIPI_DSI_DSI_ESCMODE_TXULPSDAT_MASK      (0x8U)
64856 #define MIPI_DSI_DSI_ESCMODE_TXULPSDAT_SHIFT     (3U)
64857 #define MIPI_DSI_DSI_ESCMODE_TXULPSDAT(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSDAT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSDAT_MASK)
64858 
64859 #define MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_MASK   (0x10U)
64860 #define MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_SHIFT  (4U)
64861 #define MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_MASK)
64862 
64863 #define MIPI_DSI_DSI_ESCMODE_TXLPDT_MASK         (0x40U)
64864 #define MIPI_DSI_DSI_ESCMODE_TXLPDT_SHIFT        (6U)
64865 #define MIPI_DSI_DSI_ESCMODE_TXLPDT(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXLPDT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXLPDT_MASK)
64866 
64867 #define MIPI_DSI_DSI_ESCMODE_CMDLPDT_MASK        (0x80U)
64868 #define MIPI_DSI_DSI_ESCMODE_CMDLPDT_SHIFT       (7U)
64869 #define MIPI_DSI_DSI_ESCMODE_CMDLPDT(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_CMDLPDT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_CMDLPDT_MASK)
64870 
64871 #define MIPI_DSI_DSI_ESCMODE_FORCEBTA_MASK       (0x10000U)
64872 #define MIPI_DSI_DSI_ESCMODE_FORCEBTA_SHIFT      (16U)
64873 #define MIPI_DSI_DSI_ESCMODE_FORCEBTA(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_FORCEBTA_SHIFT)) & MIPI_DSI_DSI_ESCMODE_FORCEBTA_MASK)
64874 
64875 #define MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__MASK (0x100000U)
64876 #define MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__SHIFT (20U)
64877 #define MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE_(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__SHIFT)) & MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__MASK)
64878 
64879 #define MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_MASK  (0xFFE00000U)
64880 #define MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT (21U)
64881 #define MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_MASK)
64882 /*! @} */
64883 
64884 /*! @name DSI_MDRESOL - Specifies the main display image resolution register. */
64885 /*! @{ */
64886 
64887 #define MIPI_DSI_DSI_MDRESOL_MAINHRESOL_MASK     (0xFFFU)
64888 #define MIPI_DSI_DSI_MDRESOL_MAINHRESOL_SHIFT    (0U)
64889 #define MIPI_DSI_DSI_MDRESOL_MAINHRESOL(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MAINHRESOL_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MAINHRESOL_MASK)
64890 
64891 #define MIPI_DSI_DSI_MDRESOL_MAINVRESOL_MASK     (0xFFF0000U)
64892 #define MIPI_DSI_DSI_MDRESOL_MAINVRESOL_SHIFT    (16U)
64893 #define MIPI_DSI_DSI_MDRESOL_MAINVRESOL(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MAINVRESOL_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MAINVRESOL_MASK)
64894 
64895 #define MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_MASK    (0x80000000U)
64896 #define MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_SHIFT   (31U)
64897 #define MIPI_DSI_DSI_MDRESOL_MAINSTANDBY(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_MASK)
64898 /*! @} */
64899 
64900 /*! @name DSI_MVPORCH - Specifies the main display Vporch register. */
64901 /*! @{ */
64902 
64903 #define MIPI_DSI_DSI_MVPORCH_MAINVBP_MASK        (0x7FFU)
64904 #define MIPI_DSI_DSI_MVPORCH_MAINVBP_SHIFT       (0U)
64905 #define MIPI_DSI_DSI_MVPORCH_MAINVBP(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_MAINVBP_SHIFT)) & MIPI_DSI_DSI_MVPORCH_MAINVBP_MASK)
64906 
64907 #define MIPI_DSI_DSI_MVPORCH_STABLEVFP_MASK      (0x7FF0000U)
64908 #define MIPI_DSI_DSI_MVPORCH_STABLEVFP_SHIFT     (16U)
64909 #define MIPI_DSI_DSI_MVPORCH_STABLEVFP(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_STABLEVFP_SHIFT)) & MIPI_DSI_DSI_MVPORCH_STABLEVFP_MASK)
64910 
64911 #define MIPI_DSI_DSI_MVPORCH_CMDALLOW_MASK       (0xF0000000U)
64912 #define MIPI_DSI_DSI_MVPORCH_CMDALLOW_SHIFT      (28U)
64913 #define MIPI_DSI_DSI_MVPORCH_CMDALLOW(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_CMDALLOW_SHIFT)) & MIPI_DSI_DSI_MVPORCH_CMDALLOW_MASK)
64914 /*! @} */
64915 
64916 /*! @name DSI_MHPORCH - Specifies the main display Hporch register. */
64917 /*! @{ */
64918 
64919 #define MIPI_DSI_DSI_MHPORCH_MAINHBP_MASK        (0xFFFFU)
64920 #define MIPI_DSI_DSI_MHPORCH_MAINHBP_SHIFT       (0U)
64921 #define MIPI_DSI_DSI_MHPORCH_MAINHBP(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MAINHBP_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MAINHBP_MASK)
64922 
64923 #define MIPI_DSI_DSI_MHPORCH_MAINHFP_MASK        (0xFFFF0000U)
64924 #define MIPI_DSI_DSI_MHPORCH_MAINHFP_SHIFT       (16U)
64925 #define MIPI_DSI_DSI_MHPORCH_MAINHFP(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MAINHFP_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MAINHFP_MASK)
64926 /*! @} */
64927 
64928 /*! @name DSI_MSYNC - Specifies the main display Sync Area register. */
64929 /*! @{ */
64930 
64931 #define MIPI_DSI_DSI_MSYNC_MAINHSA_MASK          (0xFFFFU)
64932 #define MIPI_DSI_DSI_MSYNC_MAINHSA_SHIFT         (0U)
64933 #define MIPI_DSI_DSI_MSYNC_MAINHSA(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MAINHSA_SHIFT)) & MIPI_DSI_DSI_MSYNC_MAINHSA_MASK)
64934 
64935 #define MIPI_DSI_DSI_MSYNC_MAINVSA_MASK          (0xFFC00000U)
64936 #define MIPI_DSI_DSI_MSYNC_MAINVSA_SHIFT         (22U)
64937 #define MIPI_DSI_DSI_MSYNC_MAINVSA(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MAINVSA_SHIFT)) & MIPI_DSI_DSI_MSYNC_MAINVSA_MASK)
64938 /*! @} */
64939 
64940 /*! @name DSI_SDRESOL - Specifies the sub display image resolution register. */
64941 /*! @{ */
64942 
64943 #define MIPI_DSI_DSI_SDRESOL_SUBHRESOL_MASK      (0x7FFU)
64944 #define MIPI_DSI_DSI_SDRESOL_SUBHRESOL_SHIFT     (0U)
64945 #define MIPI_DSI_DSI_SDRESOL_SUBHRESOL(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SUBHRESOL_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SUBHRESOL_MASK)
64946 
64947 #define MIPI_DSI_DSI_SDRESOL_SUBVRESOL_MASK      (0x7FF0000U)
64948 #define MIPI_DSI_DSI_SDRESOL_SUBVRESOL_SHIFT     (16U)
64949 #define MIPI_DSI_DSI_SDRESOL_SUBVRESOL(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SUBVRESOL_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SUBVRESOL_MASK)
64950 
64951 #define MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_MASK     (0x80000000U)
64952 #define MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_SHIFT    (31U)
64953 #define MIPI_DSI_DSI_SDRESOL_SUBSTANDBY(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_MASK)
64954 /*! @} */
64955 
64956 /*! @name DSI_INTSRC - Specifies the interrupt source register. */
64957 /*! @{ */
64958 
64959 #define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_MASK   (0x1U)
64960 #define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_SHIFT  (0U)
64961 #define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_MASK)
64962 
64963 #define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_MASK   (0x2U)
64964 #define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_SHIFT  (1U)
64965 #define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_MASK)
64966 
64967 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL0_MASK     (0x4U)
64968 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL0_SHIFT    (2U)
64969 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL0(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL0_MASK)
64970 
64971 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL1_MASK     (0x8U)
64972 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL1_SHIFT    (3U)
64973 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL1(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL1_MASK)
64974 
64975 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL2_MASK     (0x10U)
64976 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL2_SHIFT    (4U)
64977 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL2(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL2_MASK)
64978 
64979 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL3_MASK     (0x20U)
64980 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL3_SHIFT    (5U)
64981 #define MIPI_DSI_DSI_INTSRC_ERRCONTROL3(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL3_MASK)
64982 
64983 #define MIPI_DSI_DSI_INTSRC_ERRSYNC0_MASK        (0x40U)
64984 #define MIPI_DSI_DSI_INTSRC_ERRSYNC0_SHIFT       (6U)
64985 #define MIPI_DSI_DSI_INTSRC_ERRSYNC0(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC0_MASK)
64986 
64987 #define MIPI_DSI_DSI_INTSRC_ERRSYNC1_MASK        (0x80U)
64988 #define MIPI_DSI_DSI_INTSRC_ERRSYNC1_SHIFT       (7U)
64989 #define MIPI_DSI_DSI_INTSRC_ERRSYNC1(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC1_MASK)
64990 
64991 #define MIPI_DSI_DSI_INTSRC_ERRSYNC2_MASK        (0x100U)
64992 #define MIPI_DSI_DSI_INTSRC_ERRSYNC2_SHIFT       (8U)
64993 #define MIPI_DSI_DSI_INTSRC_ERRSYNC2(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC2_MASK)
64994 
64995 #define MIPI_DSI_DSI_INTSRC_ERRSYNC3_MASK        (0x200U)
64996 #define MIPI_DSI_DSI_INTSRC_ERRSYNC3_SHIFT       (9U)
64997 #define MIPI_DSI_DSI_INTSRC_ERRSYNC3(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC3_MASK)
64998 
64999 #define MIPI_DSI_DSI_INTSRC_ERRESC0_MASK         (0x400U)
65000 #define MIPI_DSI_DSI_INTSRC_ERRESC0_SHIFT        (10U)
65001 #define MIPI_DSI_DSI_INTSRC_ERRESC0(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC0_MASK)
65002 
65003 #define MIPI_DSI_DSI_INTSRC_ERRESC1_MASK         (0x800U)
65004 #define MIPI_DSI_DSI_INTSRC_ERRESC1_SHIFT        (11U)
65005 #define MIPI_DSI_DSI_INTSRC_ERRESC1(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC1_MASK)
65006 
65007 #define MIPI_DSI_DSI_INTSRC_ERRESC2_MASK         (0x1000U)
65008 #define MIPI_DSI_DSI_INTSRC_ERRESC2_SHIFT        (12U)
65009 #define MIPI_DSI_DSI_INTSRC_ERRESC2(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC2_MASK)
65010 
65011 #define MIPI_DSI_DSI_INTSRC_ERRESC3_MASK         (0x2000U)
65012 #define MIPI_DSI_DSI_INTSRC_ERRESC3_SHIFT        (13U)
65013 #define MIPI_DSI_DSI_INTSRC_ERRESC3(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC3_MASK)
65014 
65015 #define MIPI_DSI_DSI_INTSRC_ERRRXCRC_MASK        (0x4000U)
65016 #define MIPI_DSI_DSI_INTSRC_ERRRXCRC_SHIFT       (14U)
65017 #define MIPI_DSI_DSI_INTSRC_ERRRXCRC(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRRXCRC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRRXCRC_MASK)
65018 
65019 #define MIPI_DSI_DSI_INTSRC_ERRRXECC_MASK        (0x8000U)
65020 #define MIPI_DSI_DSI_INTSRC_ERRRXECC_SHIFT       (15U)
65021 #define MIPI_DSI_DSI_INTSRC_ERRRXECC(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRRXECC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRRXECC_MASK)
65022 
65023 #define MIPI_DSI_DSI_INTSRC_RXACK_MASK           (0x10000U)
65024 #define MIPI_DSI_DSI_INTSRC_RXACK_SHIFT          (16U)
65025 #define MIPI_DSI_DSI_INTSRC_RXACK(x)             (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RXACK_SHIFT)) & MIPI_DSI_DSI_INTSRC_RXACK_MASK)
65026 
65027 #define MIPI_DSI_DSI_INTSRC_RXTE_MASK            (0x20000U)
65028 #define MIPI_DSI_DSI_INTSRC_RXTE_SHIFT           (17U)
65029 #define MIPI_DSI_DSI_INTSRC_RXTE(x)              (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RXTE_SHIFT)) & MIPI_DSI_DSI_INTSRC_RXTE_MASK)
65030 
65031 #define MIPI_DSI_DSI_INTSRC_RXDATDONE_MASK       (0x40000U)
65032 #define MIPI_DSI_DSI_INTSRC_RXDATDONE_SHIFT      (18U)
65033 #define MIPI_DSI_DSI_INTSRC_RXDATDONE(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RXDATDONE_SHIFT)) & MIPI_DSI_DSI_INTSRC_RXDATDONE_MASK)
65034 
65035 #define MIPI_DSI_DSI_INTSRC_TATOUT_MASK          (0x100000U)
65036 #define MIPI_DSI_DSI_INTSRC_TATOUT_SHIFT         (20U)
65037 #define MIPI_DSI_DSI_INTSRC_TATOUT(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_TATOUT_SHIFT)) & MIPI_DSI_DSI_INTSRC_TATOUT_MASK)
65038 
65039 #define MIPI_DSI_DSI_INTSRC_LPDRTOUT_MASK        (0x200000U)
65040 #define MIPI_DSI_DSI_INTSRC_LPDRTOUT_SHIFT       (21U)
65041 #define MIPI_DSI_DSI_INTSRC_LPDRTOUT(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_LPDRTOUT_SHIFT)) & MIPI_DSI_DSI_INTSRC_LPDRTOUT_MASK)
65042 
65043 #define MIPI_DSI_DSI_INTSRC_FRAMEDONE_MASK       (0x1000000U)
65044 #define MIPI_DSI_DSI_INTSRC_FRAMEDONE_SHIFT      (24U)
65045 #define MIPI_DSI_DSI_INTSRC_FRAMEDONE(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_FRAMEDONE_SHIFT)) & MIPI_DSI_DSI_INTSRC_FRAMEDONE_MASK)
65046 
65047 #define MIPI_DSI_DSI_INTSRC_BUSTURNOVER_MASK     (0x2000000U)
65048 #define MIPI_DSI_DSI_INTSRC_BUSTURNOVER_SHIFT    (25U)
65049 #define MIPI_DSI_DSI_INTSRC_BUSTURNOVER(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_BUSTURNOVER_SHIFT)) & MIPI_DSI_DSI_INTSRC_BUSTURNOVER_MASK)
65050 
65051 #define MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_MASK    (0x8000000U)
65052 #define MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_SHIFT   (27U)
65053 #define MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_SHIFT)) & MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_MASK)
65054 
65055 #define MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_MASK  (0x10000000U)
65056 #define MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_SHIFT (28U)
65057 #define MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_MASK)
65058 
65059 #define MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_MASK  (0x20000000U)
65060 #define MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_SHIFT (29U)
65061 #define MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_MASK)
65062 
65063 #define MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_MASK    (0x40000000U)
65064 #define MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_SHIFT   (30U)
65065 #define MIPI_DSI_DSI_INTSRC_SWRSTRELEASE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_SHIFT)) & MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_MASK)
65066 
65067 #define MIPI_DSI_DSI_INTSRC_PLLSTABLE_MASK       (0x80000000U)
65068 #define MIPI_DSI_DSI_INTSRC_PLLSTABLE_SHIFT      (31U)
65069 #define MIPI_DSI_DSI_INTSRC_PLLSTABLE(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_PLLSTABLE_SHIFT)) & MIPI_DSI_DSI_INTSRC_PLLSTABLE_MASK)
65070 /*! @} */
65071 
65072 /*! @name DSI_INTMSK - Specifies the interrupt mask register. */
65073 /*! @{ */
65074 
65075 #define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_MASK   (0x1U)
65076 #define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_SHIFT  (0U)
65077 #define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_MASK)
65078 
65079 #define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_MASK   (0x2U)
65080 #define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_SHIFT  (1U)
65081 #define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_MASK)
65082 
65083 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL0_MASK     (0x4U)
65084 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL0_SHIFT    (2U)
65085 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL0(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL0_MASK)
65086 
65087 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL1_MASK     (0x8U)
65088 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL1_SHIFT    (3U)
65089 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL1(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL1_MASK)
65090 
65091 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL2_MASK     (0x10U)
65092 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL2_SHIFT    (4U)
65093 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL2(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL2_MASK)
65094 
65095 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL3_MASK     (0x20U)
65096 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL3_SHIFT    (5U)
65097 #define MIPI_DSI_DSI_INTMSK_MSKCONTROL3(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL3_MASK)
65098 
65099 #define MIPI_DSI_DSI_INTMSK_MSKSYNC0_MASK        (0x40U)
65100 #define MIPI_DSI_DSI_INTMSK_MSKSYNC0_SHIFT       (6U)
65101 #define MIPI_DSI_DSI_INTMSK_MSKSYNC0(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC0_MASK)
65102 
65103 #define MIPI_DSI_DSI_INTMSK_MSKSYNC1_MASK        (0x80U)
65104 #define MIPI_DSI_DSI_INTMSK_MSKSYNC1_SHIFT       (7U)
65105 #define MIPI_DSI_DSI_INTMSK_MSKSYNC1(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC1_MASK)
65106 
65107 #define MIPI_DSI_DSI_INTMSK_MSKSYNC2_MASK        (0x100U)
65108 #define MIPI_DSI_DSI_INTMSK_MSKSYNC2_SHIFT       (8U)
65109 #define MIPI_DSI_DSI_INTMSK_MSKSYNC2(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC2_MASK)
65110 
65111 #define MIPI_DSI_DSI_INTMSK_MSKSYNC3_MASK        (0x200U)
65112 #define MIPI_DSI_DSI_INTMSK_MSKSYNC3_SHIFT       (9U)
65113 #define MIPI_DSI_DSI_INTMSK_MSKSYNC3(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC3_MASK)
65114 
65115 #define MIPI_DSI_DSI_INTMSK_MSKESC0_MASK         (0x400U)
65116 #define MIPI_DSI_DSI_INTMSK_MSKESC0_SHIFT        (10U)
65117 #define MIPI_DSI_DSI_INTMSK_MSKESC0(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC0_MASK)
65118 
65119 #define MIPI_DSI_DSI_INTMSK_MSKESC1_MASK         (0x800U)
65120 #define MIPI_DSI_DSI_INTMSK_MSKESC1_SHIFT        (11U)
65121 #define MIPI_DSI_DSI_INTMSK_MSKESC1(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC1_MASK)
65122 
65123 #define MIPI_DSI_DSI_INTMSK_MSKESC2_MASK         (0x1000U)
65124 #define MIPI_DSI_DSI_INTMSK_MSKESC2_SHIFT        (12U)
65125 #define MIPI_DSI_DSI_INTMSK_MSKESC2(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC2_MASK)
65126 
65127 #define MIPI_DSI_DSI_INTMSK_MSKESC3_MASK         (0x2000U)
65128 #define MIPI_DSI_DSI_INTMSK_MSKESC3_SHIFT        (13U)
65129 #define MIPI_DSI_DSI_INTMSK_MSKESC3(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC3_MASK)
65130 
65131 #define MIPI_DSI_DSI_INTMSK_MSKRXCRC_MASK        (0x4000U)
65132 #define MIPI_DSI_DSI_INTMSK_MSKRXCRC_SHIFT       (14U)
65133 #define MIPI_DSI_DSI_INTMSK_MSKRXCRC(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXCRC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXCRC_MASK)
65134 
65135 #define MIPI_DSI_DSI_INTMSK_MSKRXECC_MASK        (0x8000U)
65136 #define MIPI_DSI_DSI_INTMSK_MSKRXECC_SHIFT       (15U)
65137 #define MIPI_DSI_DSI_INTMSK_MSKRXECC(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXECC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXECC_MASK)
65138 
65139 #define MIPI_DSI_DSI_INTMSK_MSKRXACK_MASK        (0x10000U)
65140 #define MIPI_DSI_DSI_INTMSK_MSKRXACK_SHIFT       (16U)
65141 #define MIPI_DSI_DSI_INTMSK_MSKRXACK(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXACK_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXACK_MASK)
65142 
65143 #define MIPI_DSI_DSI_INTMSK_MSKRXTE_MASK         (0x20000U)
65144 #define MIPI_DSI_DSI_INTMSK_MSKRXTE_SHIFT        (17U)
65145 #define MIPI_DSI_DSI_INTMSK_MSKRXTE(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXTE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXTE_MASK)
65146 
65147 #define MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_MASK    (0x40000U)
65148 #define MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_SHIFT   (18U)
65149 #define MIPI_DSI_DSI_INTMSK_MSKRXDATDONE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_MASK)
65150 
65151 #define MIPI_DSI_DSI_INTMSK_MSKTATOUT_MASK       (0x100000U)
65152 #define MIPI_DSI_DSI_INTMSK_MSKTATOUT_SHIFT      (20U)
65153 #define MIPI_DSI_DSI_INTMSK_MSKTATOUT(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKTATOUT_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKTATOUT_MASK)
65154 
65155 #define MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_MASK     (0x200000U)
65156 #define MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_SHIFT    (21U)
65157 #define MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_MASK)
65158 
65159 #define MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_MASK    (0x1000000U)
65160 #define MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_SHIFT   (24U)
65161 #define MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_MASK)
65162 
65163 #define MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_MASK  (0x2000000U)
65164 #define MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_SHIFT (25U)
65165 #define MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_MASK)
65166 
65167 #define MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_MASK (0x8000000U)
65168 #define MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_SHIFT (27U)
65169 #define MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_MASK)
65170 
65171 #define MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_MASK (0x10000000U)
65172 #define MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_SHIFT (28U)
65173 #define MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_MASK)
65174 
65175 #define MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_MASK (0x20000000U)
65176 #define MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_SHIFT (29U)
65177 #define MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_MASK)
65178 
65179 #define MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_MASK (0x40000000U)
65180 #define MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_SHIFT (30U)
65181 #define MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_MASK)
65182 
65183 #define MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_MASK    (0x80000000U)
65184 #define MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_SHIFT   (31U)
65185 #define MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_MASK)
65186 /*! @} */
65187 
65188 /*! @name DSI_PKTHDR - Specifies the packet header FIFO register. */
65189 /*! @{ */
65190 
65191 #define MIPI_DSI_DSI_PKTHDR_PACKETHEADER_MASK    (0xFFFFFFU)
65192 #define MIPI_DSI_DSI_PKTHDR_PACKETHEADER_SHIFT   (0U)
65193 #define MIPI_DSI_DSI_PKTHDR_PACKETHEADER(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PKTHDR_PACKETHEADER_SHIFT)) & MIPI_DSI_DSI_PKTHDR_PACKETHEADER_MASK)
65194 /*! @} */
65195 
65196 /*! @name DSI_PAYLOAD - Specifies the payload FIFO register. */
65197 /*! @{ */
65198 
65199 #define MIPI_DSI_DSI_PAYLOAD_PAYLOAD_MASK        (0xFFFFFFFFU)
65200 #define MIPI_DSI_DSI_PAYLOAD_PAYLOAD_SHIFT       (0U)
65201 #define MIPI_DSI_DSI_PAYLOAD_PAYLOAD(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PAYLOAD_PAYLOAD_SHIFT)) & MIPI_DSI_DSI_PAYLOAD_PAYLOAD_MASK)
65202 /*! @} */
65203 
65204 /*! @name DSI_RXFIFO - Specifies the read FIFO register. */
65205 /*! @{ */
65206 
65207 #define MIPI_DSI_DSI_RXFIFO_RXDAT_MASK           (0xFFFFFFFFU)
65208 #define MIPI_DSI_DSI_RXFIFO_RXDAT_SHIFT          (0U)
65209 #define MIPI_DSI_DSI_RXFIFO_RXDAT(x)             (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RXFIFO_RXDAT_SHIFT)) & MIPI_DSI_DSI_RXFIFO_RXDAT_MASK)
65210 /*! @} */
65211 
65212 /*! @name DSI_FIFOTHLD - Specifies the FIFO threshold level register. */
65213 /*! @{ */
65214 
65215 #define MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK (0x1FFU)
65216 #define MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT (0U)
65217 #define MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT)) & MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK)
65218 /*! @} */
65219 
65220 /*! @name DSI_FIFOCTRL - Specifies the FIFO status and control register. */
65221 /*! @{ */
65222 
65223 #define MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_MASK     (0x1U)
65224 #define MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_SHIFT    (0U)
65225 #define MIPI_DSI_DSI_FIFOCTRL_NINITMAIN(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_MASK)
65226 
65227 #define MIPI_DSI_DSI_FIFOCTRL_NINITSUB_MASK      (0x2U)
65228 #define MIPI_DSI_DSI_FIFOCTRL_NINITSUB_SHIFT     (1U)
65229 #define MIPI_DSI_DSI_FIFOCTRL_NINITSUB(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITSUB_MASK)
65230 
65231 #define MIPI_DSI_DSI_FIFOCTRL_NINITI80_MASK      (0x4U)
65232 #define MIPI_DSI_DSI_FIFOCTRL_NINITI80_SHIFT     (2U)
65233 #define MIPI_DSI_DSI_FIFOCTRL_NINITI80(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITI80_MASK)
65234 
65235 #define MIPI_DSI_DSI_FIFOCTRL_NINITSFR_MASK      (0x8U)
65236 #define MIPI_DSI_DSI_FIFOCTRL_NINITSFR_SHIFT     (3U)
65237 #define MIPI_DSI_DSI_FIFOCTRL_NINITSFR(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITSFR_MASK)
65238 
65239 #define MIPI_DSI_DSI_FIFOCTRL_NINITRX_MASK       (0x10U)
65240 #define MIPI_DSI_DSI_FIFOCTRL_NINITRX_SHIFT      (4U)
65241 #define MIPI_DSI_DSI_FIFOCTRL_NINITRX(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITRX_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITRX_MASK)
65242 
65243 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_MASK    (0x100U)
65244 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_SHIFT   (8U)
65245 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_MASK)
65246 
65247 #define MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_MASK     (0x200U)
65248 #define MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_SHIFT    (9U)
65249 #define MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_MASK)
65250 
65251 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_MASK    (0x400U)
65252 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_SHIFT   (10U)
65253 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_MASK)
65254 
65255 #define MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_MASK     (0x800U)
65256 #define MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_SHIFT    (11U)
65257 #define MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_MASK)
65258 
65259 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_MASK     (0x1000U)
65260 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_SHIFT    (12U)
65261 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_MASK)
65262 
65263 #define MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_MASK      (0x2000U)
65264 #define MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_SHIFT     (13U)
65265 #define MIPI_DSI_DSI_FIFOCTRL_FULLLSUB(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_MASK)
65266 
65267 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_MASK     (0x4000U)
65268 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_SHIFT    (14U)
65269 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_MASK)
65270 
65271 #define MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_MASK      (0x8000U)
65272 #define MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_SHIFT     (15U)
65273 #define MIPI_DSI_DSI_FIFOCTRL_FULLHSUB(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_MASK)
65274 
65275 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_MASK     (0x10000U)
65276 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_SHIFT    (16U)
65277 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_MASK)
65278 
65279 #define MIPI_DSI_DSI_FIFOCTRL_FULLLI80_MASK      (0x20000U)
65280 #define MIPI_DSI_DSI_FIFOCTRL_FULLLI80_SHIFT     (17U)
65281 #define MIPI_DSI_DSI_FIFOCTRL_FULLLI80(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLI80_MASK)
65282 
65283 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_MASK     (0x40000U)
65284 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_SHIFT    (18U)
65285 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_MASK)
65286 
65287 #define MIPI_DSI_DSI_FIFOCTRL_FULLHI80_MASK      (0x80000U)
65288 #define MIPI_DSI_DSI_FIFOCTRL_FULLHI80_SHIFT     (19U)
65289 #define MIPI_DSI_DSI_FIFOCTRL_FULLHI80(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHI80_MASK)
65290 
65291 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_MASK     (0x100000U)
65292 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_SHIFT    (20U)
65293 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_MASK)
65294 
65295 #define MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_MASK      (0x200000U)
65296 #define MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_SHIFT     (21U)
65297 #define MIPI_DSI_DSI_FIFOCTRL_FULLLSFR(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_MASK)
65298 
65299 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_MASK     (0x400000U)
65300 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_SHIFT    (22U)
65301 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_MASK)
65302 
65303 #define MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_MASK      (0x800000U)
65304 #define MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_SHIFT     (23U)
65305 #define MIPI_DSI_DSI_FIFOCTRL_FULLHSFR(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_MASK)
65306 
65307 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_MASK       (0x1000000U)
65308 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_SHIFT      (24U)
65309 #define MIPI_DSI_DSI_FIFOCTRL_EMPTYRX(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_MASK)
65310 
65311 #define MIPI_DSI_DSI_FIFOCTRL_FULLRX_MASK        (0x2000000U)
65312 #define MIPI_DSI_DSI_FIFOCTRL_FULLRX_SHIFT       (25U)
65313 #define MIPI_DSI_DSI_FIFOCTRL_FULLRX(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLRX_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLRX_MASK)
65314 /*! @} */
65315 
65316 /*! @name DSI_MEMACCHR - Specifies the FIFO memory AC characteristic register. */
65317 /*! @{ */
65318 
65319 #define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK       (0x7U)
65320 #define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT      (0U)
65321 #define MIPI_DSI_DSI_MEMACCHR_EMAA_MD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK)
65322 
65323 #define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK       (0x38U)
65324 #define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT      (3U)
65325 #define MIPI_DSI_DSI_MEMACCHR_EMAB_MD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK)
65326 
65327 #define MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK       (0x40U)
65328 #define MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT      (6U)
65329 #define MIPI_DSI_DSI_MEMACCHR_RETN_MD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK)
65330 
65331 #define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK       (0x80U)
65332 #define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT      (7U)
65333 #define MIPI_DSI_DSI_MEMACCHR_PGEN_MD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK)
65334 
65335 #define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK       (0x700U)
65336 #define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT      (8U)
65337 #define MIPI_DSI_DSI_MEMACCHR_EMAA_SD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK)
65338 
65339 #define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK       (0x3800U)
65340 #define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT      (11U)
65341 #define MIPI_DSI_DSI_MEMACCHR_EMAB_SD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK)
65342 
65343 #define MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK       (0x4000U)
65344 #define MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT      (14U)
65345 #define MIPI_DSI_DSI_MEMACCHR_RETN_SD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK)
65346 
65347 #define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK       (0x8000U)
65348 #define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT      (15U)
65349 #define MIPI_DSI_DSI_MEMACCHR_PGEN_SD(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK)
65350 /*! @} */
65351 
65352 /*! @name DSI_MULTI_PKT - Specifies the Multi Packet, Packet Go register. */
65353 /*! @{ */
65354 
65355 #define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK (0xFFFFU)
65356 #define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT (0U)
65357 #define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK)
65358 
65359 #define MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK (0xFFF0000U)
65360 #define MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT (16U)
65361 #define MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK)
65362 
65363 #define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_MASK   (0x10000000U)
65364 #define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_SHIFT  (28U)
65365 #define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_MASK)
65366 
65367 #define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_MASK    (0x20000000U)
65368 #define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_SHIFT   (29U)
65369 #define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_MASK)
65370 
65371 #define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_MASK (0x40000000U)
65372 #define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_SHIFT (30U)
65373 #define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_MASK)
65374 /*! @} */
65375 
65376 /*! @name DSI_PLLCTRL_1G - Specifies the 1Gbps D-PHY PLL control register. */
65377 /*! @{ */
65378 
65379 #define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK  (0x7U)
65380 #define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT (0U)
65381 #define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK)
65382 
65383 #define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_MASK    (0x70U)
65384 #define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT   (4U)
65385 #define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_MASK)
65386 
65387 #define MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_MASK   (0xF00U)
65388 #define MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT  (8U)
65389 #define MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_MASK)
65390 
65391 #define MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_MASK   (0xF000U)
65392 #define MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT  (12U)
65393 #define MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_MASK)
65394 /*! @} */
65395 
65396 /*! @name DSI_PLLCTRL - Specifies the PLL control register. */
65397 /*! @{ */
65398 
65399 #define MIPI_DSI_DSI_PLLCTRL_PMS_MASK            (0xFFFFEU)
65400 #define MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT           (1U)
65401 #define MIPI_DSI_DSI_PLLCTRL_PMS(x)              (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PMS_MASK)
65402 
65403 #define MIPI_DSI_DSI_PLLCTRL_PLLEN_MASK          (0x800000U)
65404 #define MIPI_DSI_DSI_PLLCTRL_PLLEN_SHIFT         (23U)
65405 #define MIPI_DSI_DSI_PLLCTRL_PLLEN(x)            (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PLLEN_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PLLEN_MASK)
65406 
65407 #define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_MASK   (0x1000000U)
65408 #define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_SHIFT  (24U)
65409 #define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_MASK)
65410 
65411 #define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_MASK   (0x2000000U)
65412 #define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_SHIFT  (25U)
65413 #define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_MASK)
65414 /*! @} */
65415 
65416 /*! @name DSI_PLLCTRL1 - Specifies the PLL control register 1. */
65417 /*! @{ */
65418 
65419 #define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK     (0xFFFFFFFFU)
65420 #define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT    (0U)
65421 #define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT)) & MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK)
65422 /*! @} */
65423 
65424 /*! @name DSI_PLLCTRL2 - Specifies the PLL control register 2. */
65425 /*! @{ */
65426 
65427 #define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK     (0xFFU)
65428 #define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT    (0U)
65429 #define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT)) & MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK)
65430 /*! @} */
65431 
65432 /*! @name DSI_PLLTMR - Specifies the PLL timer register. */
65433 /*! @{ */
65434 
65435 #define MIPI_DSI_DSI_PLLTMR_PLLTIMER_MASK        (0xFFFFFFFFU)
65436 #define MIPI_DSI_DSI_PLLTMR_PLLTIMER_SHIFT       (0U)
65437 #define MIPI_DSI_DSI_PLLTMR_PLLTIMER(x)          (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLTMR_PLLTIMER_SHIFT)) & MIPI_DSI_DSI_PLLTMR_PLLTIMER_MASK)
65438 /*! @} */
65439 
65440 /*! @name DSI_PHYCTRL_B1 - Specifies the D-PHY control register 1. */
65441 /*! @{ */
65442 
65443 #define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK  (0xFFFFFFFFU)
65444 #define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT (0U)
65445 #define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK)
65446 /*! @} */
65447 
65448 /*! @name DSI_PHYCTRL_B2 - Specifies the D-PHY control register 2. */
65449 /*! @{ */
65450 
65451 #define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK  (0xFFFFFFFFU)
65452 #define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT (0U)
65453 #define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK)
65454 /*! @} */
65455 
65456 /*! @name DSI_PHYCTRL_M1 - Specifies the D-PHY control register 1. */
65457 /*! @{ */
65458 
65459 #define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK  (0xFFFFFFFFU)
65460 #define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT (0U)
65461 #define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK)
65462 /*! @} */
65463 
65464 /*! @name DSI_PHYCTRL_M2 - Specifies the D-PHY control register 2. */
65465 /*! @{ */
65466 
65467 #define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK  (0xFFFFFFFFU)
65468 #define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT (0U)
65469 #define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK)
65470 /*! @} */
65471 
65472 /*! @name DSI_PHYTIMING - Specifies the D-PHY timing register. */
65473 /*! @{ */
65474 
65475 #define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK (0xFFU)
65476 #define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT (0U)
65477 #define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK)
65478 
65479 #define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK    (0xFF00U)
65480 #define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT   (8U)
65481 #define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK)
65482 /*! @} */
65483 
65484 /*! @name DSI_PHYTIMING1 - Specifies the D-PHY timing register 1. */
65485 /*! @{ */
65486 
65487 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK (0xFFU)
65488 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT (0U)
65489 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK)
65490 
65491 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK (0xFF00U)
65492 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT (8U)
65493 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK)
65494 
65495 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK (0xFF0000U)
65496 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT (16U)
65497 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK)
65498 
65499 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK (0xFF000000U)
65500 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT (24U)
65501 #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK)
65502 /*! @} */
65503 
65504 /*! @name DSI_PHYTIMING2 - Specifies the D-PHY timing register 2. */
65505 /*! @{ */
65506 
65507 #define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK (0xFFU)
65508 #define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT (0U)
65509 #define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK)
65510 
65511 #define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK (0xFF00U)
65512 #define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT (8U)
65513 #define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK)
65514 
65515 #define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK (0xFF0000U)
65516 #define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT (16U)
65517 #define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK)
65518 /*! @} */
65519 
65520 
65521 /*!
65522  * @}
65523  */ /* end of group MIPI_DSI_Register_Masks */
65524 
65525 
65526 /* MIPI_DSI - Peripheral instance base addresses */
65527 /** Peripheral MIPI_DSI base address */
65528 #define MIPI_DSI_BASE                            (0x32E10000u)
65529 /** Peripheral MIPI_DSI base pointer */
65530 #define MIPI_DSI                                 ((MIPI_DSI_Type *)MIPI_DSI_BASE)
65531 /** Array initializer of MIPI_DSI peripheral base addresses */
65532 #define MIPI_DSI_BASE_ADDRS                      { MIPI_DSI_BASE }
65533 /** Array initializer of MIPI_DSI peripheral base pointers */
65534 #define MIPI_DSI_BASE_PTRS                       { MIPI_DSI }
65535 
65536 /*!
65537  * @}
65538  */ /* end of group MIPI_DSI_Peripheral_Access_Layer */
65539 
65540 /*!
65541  * @brief Power mode on the other side definition.
65542  */
65543 typedef enum _mu_power_mode
65544 {
65545     kMU_PowerModeRun  = 0x00U, /*!< Run mode.       */
65546     kMU_PowerModeWait = 0x01U, /*!< WAIT mode.      */
65547     kMU_PowerModeStop = 0x03U, /*!< STOP mode.      */
65548 } mu_power_mode_t;
65549 
65550 
65551 /* ----------------------------------------------------------------------------
65552    -- MU Peripheral Access Layer
65553    ---------------------------------------------------------------------------- */
65554 
65555 /*!
65556  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
65557  * @{
65558  */
65559 
65560 /** MU - Register Layout Typedef */
65561 typedef struct {
65562   __IO uint32_t TR[4];                             /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */
65563   __I  uint32_t RR[4];                             /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */
65564   __IO uint32_t SR;                                /**< Processor B Status Register, offset: 0x20 */
65565   __IO uint32_t CR;                                /**< Processor B Control Register, offset: 0x24 */
65566 } MU_Type;
65567 
65568 /* ----------------------------------------------------------------------------
65569    -- MU Register Masks
65570    ---------------------------------------------------------------------------- */
65571 
65572 /*!
65573  * @addtogroup MU_Register_Masks MU Register Masks
65574  * @{
65575  */
65576 
65577 /*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */
65578 /*! @{ */
65579 
65580 #define MU_TR_BTR0_MASK                          (0xFFFFFFFFU)
65581 #define MU_TR_BTR0_SHIFT                         (0U)
65582 #define MU_TR_BTR0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK)
65583 
65584 #define MU_TR_BTR1_MASK                          (0xFFFFFFFFU)
65585 #define MU_TR_BTR1_SHIFT                         (0U)
65586 #define MU_TR_BTR1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK)
65587 
65588 #define MU_TR_BTR2_MASK                          (0xFFFFFFFFU)
65589 #define MU_TR_BTR2_SHIFT                         (0U)
65590 #define MU_TR_BTR2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
65591 
65592 #define MU_TR_BTR3_MASK                          (0xFFFFFFFFU)
65593 #define MU_TR_BTR3_SHIFT                         (0U)
65594 #define MU_TR_BTR3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK)
65595 /*! @} */
65596 
65597 /* The count of MU_TR */
65598 #define MU_TR_COUNT                              (4U)
65599 
65600 /*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */
65601 /*! @{ */
65602 
65603 #define MU_RR_BRR0_MASK                          (0xFFFFFFFFU)
65604 #define MU_RR_BRR0_SHIFT                         (0U)
65605 #define MU_RR_BRR0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK)
65606 
65607 #define MU_RR_BRR1_MASK                          (0xFFFFFFFFU)
65608 #define MU_RR_BRR1_SHIFT                         (0U)
65609 #define MU_RR_BRR1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK)
65610 
65611 #define MU_RR_BRR2_MASK                          (0xFFFFFFFFU)
65612 #define MU_RR_BRR2_SHIFT                         (0U)
65613 #define MU_RR_BRR2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK)
65614 
65615 #define MU_RR_BRR3_MASK                          (0xFFFFFFFFU)
65616 #define MU_RR_BRR3_SHIFT                         (0U)
65617 #define MU_RR_BRR3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK)
65618 /*! @} */
65619 
65620 /* The count of MU_RR */
65621 #define MU_RR_COUNT                              (4U)
65622 
65623 /*! @name SR - Processor B Status Register */
65624 /*! @{ */
65625 
65626 #define MU_SR_Fn_MASK                            (0x7U)
65627 #define MU_SR_Fn_SHIFT                           (0U)
65628 /*! Fn
65629  *  0b000..ABFn bit in ACR register is written 0 (default).
65630  *  0b001..ABFn bit in ACR register is written 1.
65631  */
65632 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
65633 
65634 #define MU_SR_EP_MASK                            (0x10U)
65635 #define MU_SR_EP_SHIFT                           (4U)
65636 /*! EP
65637  *  0b0..The Processor B-side event is not pending (default).
65638  *  0b1..The Processor B-side event is pending.
65639  */
65640 #define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
65641 
65642 #define MU_SR_APM_MASK                           (0x60U)
65643 #define MU_SR_APM_SHIFT                          (5U)
65644 /*! APM
65645  *  0b00..The System is in Run Mode.
65646  *  0b01..The System is in WAIT Mode.
65647  *  0b10..Reserved.
65648  *  0b11..The System is in STOP Mode.
65649  */
65650 #define MU_SR_APM(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK)
65651 
65652 #define MU_SR_ARS_MASK                           (0x80U)
65653 #define MU_SR_ARS_SHIFT                          (7U)
65654 /*! ARS
65655  *  0b0..The Processor A or the Processor A-side of the MU is not in reset.
65656  *  0b1..The Processor A or the Processor A-side of the MU is in reset.
65657  */
65658 #define MU_SR_ARS(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK)
65659 
65660 #define MU_SR_FUP_MASK                           (0x100U)
65661 #define MU_SR_FUP_SHIFT                          (8U)
65662 /*! FUP
65663  *  0b0..No flags updated, initiated by the Processor B, in progress (default)
65664  *  0b1..Processor B initiated flags update, processing
65665  */
65666 #define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
65667 
65668 #define MU_SR_TEn_MASK                           (0xF00000U)
65669 #define MU_SR_TEn_SHIFT                          (20U)
65670 /*! TEn
65671  *  0b0000..BTRn register is not empty.
65672  *  0b0001..BTRn register is empty (default).
65673  */
65674 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
65675 
65676 #define MU_SR_RFn_MASK                           (0xF000000U)
65677 #define MU_SR_RFn_SHIFT                          (24U)
65678 /*! RFn
65679  *  0b0000..BRRn register is not full (default).
65680  *  0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B.
65681  */
65682 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
65683 
65684 #define MU_SR_GIPn_MASK                          (0xF0000000U)
65685 #define MU_SR_GIPn_SHIFT                         (28U)
65686 /*! GIPn
65687  *  0b0000..Processor B general purpose interrupt n is not pending. (default)
65688  *  0b0001..Processor B general purpose interrupt n is pending.
65689  */
65690 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
65691 /*! @} */
65692 
65693 /*! @name CR - Processor B Control Register */
65694 /*! @{ */
65695 
65696 #define MU_CR_BAFn_MASK                          (0x7U)
65697 #define MU_CR_BAFn_SHIFT                         (0U)
65698 /*! BAFn
65699  *  0b000..Clears the Fn bit in the ASR register.
65700  *  0b001..Sets the Fn bit in the ASR register.
65701  */
65702 #define MU_CR_BAFn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK)
65703 
65704 #define MU_CR_HRM_MASK                           (0x10U)
65705 #define MU_CR_HRM_SHIFT                          (4U)
65706 /*! HRM
65707  *  0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
65708  *  0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
65709  */
65710 #define MU_CR_HRM(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK)
65711 
65712 #define MU_CR_GIRn_MASK                          (0xF0000U)
65713 #define MU_CR_GIRn_SHIFT                         (16U)
65714 /*! GIRn
65715  *  0b0000..Processor B General Interrupt n is not requested to the Processor A (default).
65716  *  0b0001..Processor B General Interrupt n is requested to the Processor A.
65717  */
65718 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
65719 
65720 #define MU_CR_TIEn_MASK                          (0xF00000U)
65721 #define MU_CR_TIEn_SHIFT                         (20U)
65722 /*! TIEn
65723  *  0b0000..Disables Processor B Transmit Interrupt n. (default)
65724  *  0b0001..Enables Processor B Transmit Interrupt n.
65725  */
65726 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
65727 
65728 #define MU_CR_RIEn_MASK                          (0xF000000U)
65729 #define MU_CR_RIEn_SHIFT                         (24U)
65730 /*! RIEn
65731  *  0b0000..Disables Processor B Receive Interrupt n. (default)
65732  *  0b0001..Enables Processor B Receive Interrupt n.
65733  */
65734 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
65735 
65736 #define MU_CR_GIEn_MASK                          (0xF0000000U)
65737 #define MU_CR_GIEn_SHIFT                         (28U)
65738 /*! GIEn
65739  *  0b0000..Disables Processor B General Interrupt n. (default)
65740  *  0b0001..Enables Processor B General Interrupt n.
65741  */
65742 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
65743 /*! @} */
65744 
65745 
65746 /*!
65747  * @}
65748  */ /* end of group MU_Register_Masks */
65749 
65750 
65751 /* MU - Peripheral instance base addresses */
65752 /** Peripheral MUB base address */
65753 #define MUB_BASE                                 (0x30AB0000u)
65754 /** Peripheral MUB base pointer */
65755 #define MUB                                      ((MU_Type *)MUB_BASE)
65756 /** Array initializer of MU peripheral base addresses */
65757 #define MU_BASE_ADDRS                            { MUB_BASE }
65758 /** Array initializer of MU peripheral base pointers */
65759 #define MU_BASE_PTRS                             { MUB }
65760 /** Interrupt vectors for the MU peripheral type */
65761 #define MU_IRQS                                  { MU1_M7_IRQn }
65762 /* Backward compatibility */
65763 #define MU_SR_PM_MASK                             MU_SR_APM_MASK
65764 #define MU_SR_PM_SHIFT                            MU_SR_APM_SHIFT
65765 #define MU_SR_PM(x)                               MU_SR_APM(x)
65766 #define MU_SR_RS_MASK                             MU_SR_ARS_MASK
65767 #define MU_SR_RS_SHIFT                            MU_SR_ARS_SHIFT
65768 #define MU_SR_RS(x)                               MU_SR_ARS(x)
65769 #define MU_CR_Fn_MASK                             MU_CR_BAFn_MASK
65770 #define MU_CR_Fn_SHIFT                            MU_CR_BAFn_SHIFT
65771 #define MU_CR_Fn(x)                               MU_CR_BAFn(x)
65772 
65773 
65774 /*!
65775  * @}
65776  */ /* end of group MU_Peripheral_Access_Layer */
65777 
65778 
65779 /* ----------------------------------------------------------------------------
65780    -- NPU Peripheral Access Layer
65781    ---------------------------------------------------------------------------- */
65782 
65783 /*!
65784  * @addtogroup NPU_Peripheral_Access_Layer NPU Peripheral Access Layer
65785  * @{
65786  */
65787 
65788 /** NPU - Register Layout Typedef */
65789 typedef struct {
65790   __IO uint32_t AQHICLOCKCONTROL;                  /**< Clock Control Register, offset: 0x0 */
65791   __I  uint32_t AQHIIDLE;                          /**< Idle Status Register, offset: 0x4 */
65792        uint8_t RESERVED_0[4];
65793   __I  uint32_t AQAXISTATUS;                       /**< AXI Status Register, offset: 0xC */
65794   __I  uint32_t AQINTRACKNOWLEDGE;                 /**< Interrupt Acknowledge Register, offset: 0x10 */
65795   __IO uint32_t AQINTRENBL;                        /**< Interrupt Enable Register, offset: 0x14 */
65796        uint8_t RESERVED_1[96];
65797   __IO uint32_t GCTOTALCYCLES;                     /**< Total Cycles Register, offset: 0x78 */
65798        uint8_t RESERVED_2[132];
65799   __IO uint32_t GCMODULEPOWERCONTROLS;             /**< Module Power Level Control Register, offset: 0x100 */
65800        uint8_t RESERVED_3[8];
65801   __IO uint32_t GCPULSEEATER;                      /**< Pulse eater Control Register, offset: 0x10C */
65802        uint8_t RESERVED_4[632];
65803   __IO uint32_t GCREGMMUAHBCONTROL;                /**< MMU Control Register, offset: 0x388 */
65804   __IO uint32_t GCREGMMUAHBTABLEARRAYBASEADDRESSLOW; /**< MMU Table Array Base Lower 32-bit Address Register, offset: 0x38C */
65805   __IO uint32_t GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH; /**< MMU Table Array Base Higher 32-bit Address Register, offset: 0x390 */
65806   __IO uint32_t GCREGMMUAHBTABLEARRAYSIZE;         /**< MMU Table Array Size Control Register, offset: 0x394 */
65807   __IO uint32_t GCREGMMUAHBSAFENONSECUREADDRESS;   /**< MMU NonSecure Address Register, offset: 0x398 */
65808   __IO uint32_t GCREGMMUAHBSAFESECUREADDRESS;      /**< MMU Secure Address Register, offset: 0x39C */
65809        uint8_t RESERVED_5[4];
65810   __O  uint32_t GCREGCMDBUFFERAHBCTRL;             /**< Command Buffer Control Register, offset: 0x3A4 */
65811   __IO uint32_t GCREGHIAHBCONTROL;                 /**< MMU Host Interface Control Register, offset: 0x3A8 */
65812   __IO uint32_t GCREGAXIAHBCONFIG;                 /**< MMU AXI Configuration Register, offset: 0x3AC */
65813        uint8_t RESERVED_6[100];
65814   __IO uint32_t AQMEMORYDEBUG;                     /**< Memory Debug Register, offset: 0x414 */
65815        uint8_t RESERVED_7[20];
65816   __IO uint32_t AQREGISTERTIMINGCONTROL;           /**< Register Timing Control Register, offset: 0x42C */
65817        uint8_t RESERVED_8[548];
65818   __O  uint32_t AQCMDBUFFERADDR;                   /**< Command Buffer Base Address Register, offset: 0x654 */
65819        uint8_t RESERVED_9[12];
65820   __I  uint32_t AQFEDEBUGCURCMDADR;                /**< Command Decoder Address Register, offset: 0x664 */
65821 } NPU_Type;
65822 
65823 /* ----------------------------------------------------------------------------
65824    -- NPU Register Masks
65825    ---------------------------------------------------------------------------- */
65826 
65827 /*!
65828  * @addtogroup NPU_Register_Masks NPU Register Masks
65829  * @{
65830  */
65831 
65832 /*! @name AQHICLOCKCONTROL - Clock Control Register */
65833 /*! @{ */
65834 
65835 #define NPU_AQHICLOCKCONTROL_CLK3D_DIS_MASK      (0x1U)
65836 #define NPU_AQHICLOCKCONTROL_CLK3D_DIS_SHIFT     (0U)
65837 /*! CLK3D_DIS - Disable 3D clock
65838  *  0b1..The clock is frozen
65839  */
65840 #define NPU_AQHICLOCKCONTROL_CLK3D_DIS(x)        (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_CLK3D_DIS_SHIFT)) & NPU_AQHICLOCKCONTROL_CLK3D_DIS_MASK)
65841 
65842 #define NPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK      (0x2U)
65843 #define NPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT     (1U)
65844 /*! CLK2D_DIS - Disable 2D clock */
65845 #define NPU_AQHICLOCKCONTROL_CLK2D_DIS(x)        (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT)) & NPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK)
65846 
65847 #define NPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK     (0x1FCU)
65848 #define NPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT    (2U)
65849 /*! FSCALE_VAL - Core clock frequency scale value */
65850 #define NPU_AQHICLOCKCONTROL_FSCALE_VAL(x)       (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)) & NPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)
65851 
65852 #define NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK (0x200U)
65853 #define NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT (9U)
65854 /*! FSCALE_CMD_LOAD - Core clock frequency scale value enable
65855  *  0b1..The frequency scale factor is updated with the value FSCALE_VAL[6:0]. The bit sets back to 0 after that.
65856  */
65857 #define NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD(x)  (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT)) & NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK)
65858 
65859 #define NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_MASK (0x400U)
65860 #define NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_SHIFT (10U)
65861 /*! DIS_RAM_CLK_GATING - Disable clock gating for RAMs */
65862 #define NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_SHIFT)) & NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_MASK)
65863 
65864 #define NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_MASK (0x2000U)
65865 #define NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_SHIFT (13U)
65866 /*! DIS_RAM_PWR_OPT - Disable RAM power optimization */
65867 #define NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT(x)  (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_SHIFT)) & NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_MASK)
65868 
65869 #define NPU_AQHICLOCKCONTROL_IDLE3_D_MASK        (0x10000U)
65870 #define NPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT       (16U)
65871 /*! IDLE3_D - 3D pipe is idle */
65872 #define NPU_AQHICLOCKCONTROL_IDLE3_D(x)          (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT)) & NPU_AQHICLOCKCONTROL_IDLE3_D_MASK)
65873 
65874 #define NPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK    (0x80000U)
65875 #define NPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT   (19U)
65876 /*! ISOLATE_GPU - Isolate GPU */
65877 #define NPU_AQHICLOCKCONTROL_ISOLATE_GPU(x)      (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT)) & NPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK)
65878 
65879 #define NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_MASK (0xF00000U)
65880 #define NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_SHIFT (20U)
65881 /*! MULTI_PIPE_REG_SEL - Multiple Pipe Register Select */
65882 #define NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_SHIFT)) & NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_MASK)
65883 /*! @} */
65884 
65885 /*! @name AQHIIDLE - Idle Status Register */
65886 /*! @{ */
65887 
65888 #define NPU_AQHIIDLE_IDLE_FE_MASK                (0x1U)
65889 #define NPU_AQHIIDLE_IDLE_FE_SHIFT               (0U)
65890 /*! IDLE_FE - FE is idle */
65891 #define NPU_AQHIIDLE_IDLE_FE(x)                  (((uint32_t)(((uint32_t)(x)) << NPU_AQHIIDLE_IDLE_FE_SHIFT)) & NPU_AQHIIDLE_IDLE_FE_MASK)
65892 
65893 #define NPU_AQHIIDLE_IDLE_SH_MASK                (0x8U)
65894 #define NPU_AQHIIDLE_IDLE_SH_SHIFT               (3U)
65895 /*! IDLE_SH - SH is idle */
65896 #define NPU_AQHIIDLE_IDLE_SH(x)                  (((uint32_t)(((uint32_t)(x)) << NPU_AQHIIDLE_IDLE_SH_SHIFT)) & NPU_AQHIIDLE_IDLE_SH_MASK)
65897 
65898 #define NPU_AQHIIDLE_AXI_LP_MASK                 (0x80000000U)
65899 #define NPU_AQHIIDLE_AXI_LP_SHIFT                (31U)
65900 /*! AXI_LP - AXI is in low power mode */
65901 #define NPU_AQHIIDLE_AXI_LP(x)                   (((uint32_t)(((uint32_t)(x)) << NPU_AQHIIDLE_AXI_LP_SHIFT)) & NPU_AQHIIDLE_AXI_LP_MASK)
65902 /*! @} */
65903 
65904 /*! @name AQAXISTATUS - AXI Status Register */
65905 /*! @{ */
65906 
65907 #define NPU_AQAXISTATUS_WR_ERR_ID_MASK           (0xFU)
65908 #define NPU_AQAXISTATUS_WR_ERR_ID_SHIFT          (0U)
65909 /*! WR_ERR_ID - Write Error ID */
65910 #define NPU_AQAXISTATUS_WR_ERR_ID(x)             (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_WR_ERR_ID_SHIFT)) & NPU_AQAXISTATUS_WR_ERR_ID_MASK)
65911 
65912 #define NPU_AQAXISTATUS_RD_ERR_ID_MASK           (0xF0U)
65913 #define NPU_AQAXISTATUS_RD_ERR_ID_SHIFT          (4U)
65914 /*! RD_ERR_ID - Read Error ID */
65915 #define NPU_AQAXISTATUS_RD_ERR_ID(x)             (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_RD_ERR_ID_SHIFT)) & NPU_AQAXISTATUS_RD_ERR_ID_MASK)
65916 
65917 #define NPU_AQAXISTATUS_DET_WR_ERR_MASK          (0x100U)
65918 #define NPU_AQAXISTATUS_DET_WR_ERR_SHIFT         (8U)
65919 /*! DET_WR_ERR - Detect Write Error
65920  *  0b1..Detect write error
65921  */
65922 #define NPU_AQAXISTATUS_DET_WR_ERR(x)            (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_DET_WR_ERR_SHIFT)) & NPU_AQAXISTATUS_DET_WR_ERR_MASK)
65923 
65924 #define NPU_AQAXISTATUS_DET_RD_ERR_MASK          (0x200U)
65925 #define NPU_AQAXISTATUS_DET_RD_ERR_SHIFT         (9U)
65926 /*! DET_RD_ERR - Detect Read Error
65927  *  0b1..Detect read error
65928  */
65929 #define NPU_AQAXISTATUS_DET_RD_ERR(x)            (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_DET_RD_ERR_SHIFT)) & NPU_AQAXISTATUS_DET_RD_ERR_MASK)
65930 /*! @} */
65931 
65932 /*! @name AQINTRACKNOWLEDGE - Interrupt Acknowledge Register */
65933 /*! @{ */
65934 
65935 #define NPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK      (0xFFFFFFFFU)
65936 #define NPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT     (0U)
65937 /*! INTR_VEC - Interrupt Vector */
65938 #define NPU_AQINTRACKNOWLEDGE_INTR_VEC(x)        (((uint32_t)(((uint32_t)(x)) << NPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT)) & NPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK)
65939 /*! @} */
65940 
65941 /*! @name AQINTRENBL - Interrupt Enable Register */
65942 /*! @{ */
65943 
65944 #define NPU_AQINTRENBL_INTR_ENBL_VEC_MASK        (0xFFFFFFFFU)
65945 #define NPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT       (0U)
65946 /*! INTR_ENBL_VEC - Interrupt Vector Enable */
65947 #define NPU_AQINTRENBL_INTR_ENBL_VEC(x)          (((uint32_t)(((uint32_t)(x)) << NPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT)) & NPU_AQINTRENBL_INTR_ENBL_VEC_MASK)
65948 /*! @} */
65949 
65950 /*! @name GCTOTALCYCLES - Total Cycles Register */
65951 /*! @{ */
65952 
65953 #define NPU_GCTOTALCYCLES_CYCLES_MASK            (0xFFFFFFFFU)
65954 #define NPU_GCTOTALCYCLES_CYCLES_SHIFT           (0U)
65955 /*! CYCLES - Cycles */
65956 #define NPU_GCTOTALCYCLES_CYCLES(x)              (((uint32_t)(((uint32_t)(x)) << NPU_GCTOTALCYCLES_CYCLES_SHIFT)) & NPU_GCTOTALCYCLES_CYCLES_MASK)
65957 /*! @} */
65958 
65959 /*! @name GCMODULEPOWERCONTROLS - Module Power Level Control Register */
65960 /*! @{ */
65961 
65962 #define NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_MASK (0x1U)
65963 #define NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_SHIFT (0U)
65964 /*! EN_MOD_CLK_GATING - Enables module level clock gating */
65965 #define NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_MASK)
65966 
65967 #define NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_MASK (0x2U)
65968 #define NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_SHIFT (1U)
65969 /*! DIS_STALL_MOD_CLK_GATING - Disables module level clock gating for stall condition */
65970 #define NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_MASK)
65971 
65972 #define NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_MASK (0x4U)
65973 #define NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_SHIFT (2U)
65974 /*! DIS_STARVE_MOD_CLK_GATING - Disables module level clock gating for starve/idle condition */
65975 #define NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_MASK)
65976 
65977 #define NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK (0xF0U)
65978 #define NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT (4U)
65979 /*! TURN_ON_COUNTER - Number of clock cycles to wait after turning on the clock */
65980 #define NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK)
65981 
65982 #define NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK (0xFFFF0000U)
65983 #define NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT (16U)
65984 /*! TURN_OFF_COUNTER - Counter value for clock gating the module if the module is idle for this amount of clock cycles */
65985 #define NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK)
65986 /*! @} */
65987 
65988 /*! @name GCPULSEEATER - Pulse eater Control Register */
65989 /*! @{ */
65990 
65991 #define NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_MASK (0x1U)
65992 #define NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_SHIFT (0U)
65993 /*! FSCALE_CMD_LOAD_SH - Fscale_cmd_load for shader */
65994 #define NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH(x)   (((uint32_t)(((uint32_t)(x)) << NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_SHIFT)) & NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_MASK)
65995 
65996 #define NPU_GCPULSEEATER_FSCALE_VAL_SH_MASK      (0xFEU)
65997 #define NPU_GCPULSEEATER_FSCALE_VAL_SH_SHIFT     (1U)
65998 /*! FSCALE_VAL_SH - Fscale value for shader */
65999 #define NPU_GCPULSEEATER_FSCALE_VAL_SH(x)        (((uint32_t)(((uint32_t)(x)) << NPU_GCPULSEEATER_FSCALE_VAL_SH_SHIFT)) & NPU_GCPULSEEATER_FSCALE_VAL_SH_MASK)
66000 /*! @} */
66001 
66002 /*! @name GCREGMMUAHBCONTROL - MMU Control Register */
66003 /*! @{ */
66004 
66005 #define NPU_GCREGMMUAHBCONTROL_MMU_MASK          (0x1U)
66006 #define NPU_GCREGMMUAHBCONTROL_MMU_SHIFT         (0U)
66007 /*! MMU - Enable the MMU
66008  *  0b0..Disable
66009  *  0b1..Enable
66010  */
66011 #define NPU_GCREGMMUAHBCONTROL_MMU(x)            (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBCONTROL_MMU_SHIFT)) & NPU_GCREGMMUAHBCONTROL_MMU_MASK)
66012 /*! @} */
66013 
66014 /*! @name GCREGMMUAHBTABLEARRAYBASEADDRESSLOW - MMU Table Array Base Lower 32-bit Address Register */
66015 /*! @{ */
66016 
66017 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_MASK (0xFFFFFFFFU)
66018 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_SHIFT (0U)
66019 /*! ADDRESS - Address */
66020 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_MASK)
66021 /*! @} */
66022 
66023 /*! @name GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH - MMU Table Array Base Higher 32-bit Address Register */
66024 /*! @{ */
66025 
66026 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_MASK (0xFFU)
66027 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHIFT (0U)
66028 /*! MASTER_TLB - Upper 8-bits of the master TLB address to form a true 40-bit address */
66029 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_MASK)
66030 
66031 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_MASK (0x100U)
66032 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_SHIFT (8U)
66033 /*! MASTER_TLB_SECURE - Bit that defines whether the master TLB address is secure or not */
66034 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_MASK)
66035 
66036 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_MASK (0x200U)
66037 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_SHIFT (9U)
66038 /*! MASTER_TLB_SHAREABLE - Bit that defines whether the master TLB address is shareable or not */
66039 #define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_MASK)
66040 /*! @} */
66041 
66042 /*! @name GCREGMMUAHBTABLEARRAYSIZE - MMU Table Array Size Control Register */
66043 /*! @{ */
66044 
66045 #define NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_MASK  (0xFFFFU)
66046 #define NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_SHIFT (0U)
66047 /*! SIZE - Size */
66048 #define NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_MASK)
66049 /*! @} */
66050 
66051 /*! @name GCREGMMUAHBSAFENONSECUREADDRESS - MMU NonSecure Address Register */
66052 /*! @{ */
66053 
66054 #define NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_MASK (0xFFFFFFFFU)
66055 #define NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_SHIFT (0U)
66056 /*! ADDRESS - Address */
66057 #define NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_SHIFT)) & NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_MASK)
66058 /*! @} */
66059 
66060 /*! @name GCREGMMUAHBSAFESECUREADDRESS - MMU Secure Address Register */
66061 /*! @{ */
66062 
66063 #define NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_MASK (0xFFFFFFFFU)
66064 #define NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_SHIFT (0U)
66065 /*! ADDRESS - Address */
66066 #define NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_SHIFT)) & NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_MASK)
66067 /*! @} */
66068 
66069 /*! @name GCREGCMDBUFFERAHBCTRL - Command Buffer Control Register */
66070 /*! @{ */
66071 
66072 #define NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_MASK  (0xFFFFU)
66073 #define NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_SHIFT (0U)
66074 /*! PREFETCH - Prefetch */
66075 #define NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH(x)    (((uint32_t)(((uint32_t)(x)) << NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_SHIFT)) & NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_MASK)
66076 
66077 #define NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_MASK    (0x10000U)
66078 #define NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_SHIFT   (16U)
66079 /*! ENABLE - Enable the command parser
66080  *  0b0..Disable
66081  *  0b1..Enable
66082  */
66083 #define NPU_GCREGCMDBUFFERAHBCTRL_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_SHIFT)) & NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_MASK)
66084 /*! @} */
66085 
66086 /*! @name GCREGHIAHBCONTROL - MMU Host Interface Control Register */
66087 /*! @{ */
66088 
66089 #define NPU_GCREGHIAHBCONTROL_SOFT_RESET_MASK    (0x1U)
66090 #define NPU_GCREGHIAHBCONTROL_SOFT_RESET_SHIFT   (0U)
66091 /*! SOFT_RESET - Soft Reset
66092  *  0b0..Disable
66093  *  0b1..Enable
66094  */
66095 #define NPU_GCREGHIAHBCONTROL_SOFT_RESET(x)      (((uint32_t)(((uint32_t)(x)) << NPU_GCREGHIAHBCONTROL_SOFT_RESET_SHIFT)) & NPU_GCREGHIAHBCONTROL_SOFT_RESET_MASK)
66096 
66097 #define NPU_GCREGHIAHBCONTROL_DEBUG_MODE_MASK    (0x2U)
66098 #define NPU_GCREGHIAHBCONTROL_DEBUG_MODE_SHIFT   (1U)
66099 /*! DEBUG_MODE - Debug Mode
66100  *  0b0..Disable
66101  *  0b1..Enable
66102  */
66103 #define NPU_GCREGHIAHBCONTROL_DEBUG_MODE(x)      (((uint32_t)(((uint32_t)(x)) << NPU_GCREGHIAHBCONTROL_DEBUG_MODE_SHIFT)) & NPU_GCREGHIAHBCONTROL_DEBUG_MODE_MASK)
66104 /*! @} */
66105 
66106 /*! @name GCREGAXIAHBCONFIG - MMU AXI Configuration Register */
66107 /*! @{ */
66108 
66109 #define NPU_GCREGAXIAHBCONFIG_AWID_MASK          (0xFU)
66110 #define NPU_GCREGAXIAHBCONFIG_AWID_SHIFT         (0U)
66111 #define NPU_GCREGAXIAHBCONFIG_AWID(x)            (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AWID_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AWID_MASK)
66112 
66113 #define NPU_GCREGAXIAHBCONFIG_ARID_MASK          (0xF0U)
66114 #define NPU_GCREGAXIAHBCONFIG_ARID_SHIFT         (4U)
66115 #define NPU_GCREGAXIAHBCONFIG_ARID(x)            (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_ARID_SHIFT)) & NPU_GCREGAXIAHBCONFIG_ARID_MASK)
66116 
66117 #define NPU_GCREGAXIAHBCONFIG_AWCACHE_MASK       (0xF00U)
66118 #define NPU_GCREGAXIAHBCONFIG_AWCACHE_SHIFT      (8U)
66119 /*! AWCACHE - AW Cache value */
66120 #define NPU_GCREGAXIAHBCONFIG_AWCACHE(x)         (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AWCACHE_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AWCACHE_MASK)
66121 
66122 #define NPU_GCREGAXIAHBCONFIG_ARCACHE_MASK       (0xF000U)
66123 #define NPU_GCREGAXIAHBCONFIG_ARCACHE_SHIFT      (12U)
66124 /*! ARCACHE - AR Cache value */
66125 #define NPU_GCREGAXIAHBCONFIG_ARCACHE(x)         (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_ARCACHE_SHIFT)) & NPU_GCREGAXIAHBCONFIG_ARCACHE_MASK)
66126 
66127 #define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_MASK (0x30000U)
66128 #define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_SHIFT (16U)
66129 /*! AXDOMAIN_SHARED - Ax Domain value */
66130 #define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_MASK)
66131 
66132 #define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_MASK (0xC0000U)
66133 #define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_SHIFT (18U)
66134 /*! AXDOMAIN_NON_SHARED - Ax Domain value */
66135 #define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_MASK)
66136 
66137 #define NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_MASK (0xF00000U)
66138 #define NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_SHIFT (20U)
66139 /*! AXCACHE_OVERRIDE_SHARED - Ax Cache value */
66140 #define NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_MASK)
66141 /*! @} */
66142 
66143 /*! @name AQMEMORYDEBUG - Memory Debug Register */
66144 /*! @{ */
66145 
66146 #define NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK (0xFFU)
66147 #define NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT (0U)
66148 /*! MAX_OUTSTANDING_READS - Maximum Outstanding Reads */
66149 #define NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT)) & NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK)
66150 /*! @} */
66151 
66152 /*! @name AQREGISTERTIMINGCONTROL - Register Timing Control Register */
66153 /*! @{ */
66154 
66155 #define NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK (0xFFU)
66156 #define NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT (0U)
66157 /*! FOR_RF1P - For 1 port RAM */
66158 #define NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P(x)  (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK)
66159 
66160 #define NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK (0xFF00U)
66161 #define NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT (8U)
66162 /*! FOR_RF2P - For 2 port RAM */
66163 #define NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P(x)  (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK)
66164 
66165 #define NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK (0x30000U)
66166 #define NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT (16U)
66167 /*! FAST_RTC - RTC for fast RAM */
66168 #define NPU_AQREGISTERTIMINGCONTROL_FAST_RTC(x)  (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK)
66169 
66170 #define NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK (0xC0000U)
66171 #define NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT (18U)
66172 /*! FAST_WTC - WTC for fast RAM */
66173 #define NPU_AQREGISTERTIMINGCONTROL_FAST_WTC(x)  (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK)
66174 
66175 #define NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK (0x100000U)
66176 #define NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT (20U)
66177 /*! POWER_DOWN - Power Down Memory */
66178 #define NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK)
66179 
66180 #define NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_MASK (0x200000U)
66181 #define NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_SHIFT (21U)
66182 /*! DEEP_SLEEP - Deep sleep */
66183 #define NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_MASK)
66184 
66185 #define NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_MASK (0x400000U)
66186 #define NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_SHIFT (22U)
66187 /*! LIGHT_SLEEP - Light sleep */
66188 #define NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_MASK)
66189 /*! @} */
66190 
66191 /*! @name AQCMDBUFFERADDR - Command Buffer Base Address Register */
66192 /*! @{ */
66193 
66194 #define NPU_AQCMDBUFFERADDR_ADDRESS_MASK         (0x7FFFFFFFU)
66195 #define NPU_AQCMDBUFFERADDR_ADDRESS_SHIFT        (0U)
66196 /*! ADDRESS - Address */
66197 #define NPU_AQCMDBUFFERADDR_ADDRESS(x)           (((uint32_t)(((uint32_t)(x)) << NPU_AQCMDBUFFERADDR_ADDRESS_SHIFT)) & NPU_AQCMDBUFFERADDR_ADDRESS_MASK)
66198 
66199 #define NPU_AQCMDBUFFERADDR_TYPE_MASK            (0x80000000U)
66200 #define NPU_AQCMDBUFFERADDR_TYPE_SHIFT           (31U)
66201 /*! TYPE - Type
66202  *  0b0..System
66203  *  0b1..Virtual System
66204  */
66205 #define NPU_AQCMDBUFFERADDR_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << NPU_AQCMDBUFFERADDR_TYPE_SHIFT)) & NPU_AQCMDBUFFERADDR_TYPE_MASK)
66206 /*! @} */
66207 
66208 /*! @name AQFEDEBUGCURCMDADR - Command Decoder Address Register */
66209 /*! @{ */
66210 
66211 #define NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_MASK  (0xFFFFFFF8U)
66212 #define NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_SHIFT (3U)
66213 /*! CUR_CMD_ADR - Command decoder Address */
66214 #define NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR(x)    (((uint32_t)(((uint32_t)(x)) << NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_SHIFT)) & NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_MASK)
66215 /*! @} */
66216 
66217 
66218 /*!
66219  * @}
66220  */ /* end of group NPU_Register_Masks */
66221 
66222 
66223 /* NPU - Peripheral instance base addresses */
66224 /** Peripheral NPU base address */
66225 #define NPU_BASE                                 (0x38500000u)
66226 /** Peripheral NPU base pointer */
66227 #define NPU                                      ((NPU_Type *)NPU_BASE)
66228 /** Array initializer of NPU peripheral base addresses */
66229 #define NPU_BASE_ADDRS                           { NPU_BASE }
66230 /** Array initializer of NPU peripheral base pointers */
66231 #define NPU_BASE_PTRS                            { NPU }
66232 
66233 /*!
66234  * @}
66235  */ /* end of group NPU_Peripheral_Access_Layer */
66236 
66237 
66238 /* ----------------------------------------------------------------------------
66239    -- OCOTP Peripheral Access Layer
66240    ---------------------------------------------------------------------------- */
66241 
66242 /*!
66243  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
66244  * @{
66245  */
66246 
66247 /** OCOTP - Register Layout Typedef */
66248 typedef struct {
66249   __IO uint32_t HW_OCOTP_CTRL;                     /**< OTP Controller Control Register, offset: 0x0 */
66250   __IO uint32_t HW_OCOTP_CTRL_SET;                 /**< OTP Controller Control Register, offset: 0x4 */
66251   __IO uint32_t HW_OCOTP_CTRL_CLR;                 /**< OTP Controller Control Register, offset: 0x8 */
66252   __IO uint32_t HW_OCOTP_CTRL_TOG;                 /**< OTP Controller Control Register, offset: 0xC */
66253   __IO uint32_t HW_OCOTP_TIMING;                   /**< OTP Controller Timing Register, offset: 0x10 */
66254        uint8_t RESERVED_0[12];
66255   __IO uint32_t HW_OCOTP_DATA;                     /**< OTP Controller Write Data Register, offset: 0x20 */
66256        uint8_t RESERVED_1[12];
66257   __IO uint32_t HW_OCOTP_READ_CTRL;                /**< OTP Controller Write Data Register, offset: 0x30 */
66258        uint8_t RESERVED_2[12];
66259   __IO uint32_t HW_OCOTP_READ_FUSE_DATA;           /**< OTP Controller Read Data Register, offset: 0x40 */
66260        uint8_t RESERVED_3[28];
66261   __IO uint32_t HW_OCOTP_SCS;                      /**< Software Controllable Signals Register, offset: 0x60 */
66262   __IO uint32_t HW_OCOTP_SCS_SET;                  /**< Software Controllable Signals Register, offset: 0x64 */
66263   __IO uint32_t HW_OCOTP_SCS_CLR;                  /**< Software Controllable Signals Register, offset: 0x68 */
66264   __IO uint32_t HW_OCOTP_SCS_TOG;                  /**< Software Controllable Signals Register, offset: 0x6C */
66265        uint8_t RESERVED_4[32];
66266   __I  uint32_t HW_OCOTP_VERSION;                  /**< OTP Controller Version Register, offset: 0x90 */
66267        uint8_t RESERVED_5[876];
66268   __I  uint32_t HW_OCOTP_LOCK;                     /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
66269        uint8_t RESERVED_6[108];
66270   __IO uint32_t HW_OCOTP_BOOT_CFG0;                /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */
66271        uint8_t RESERVED_7[12];
66272   __IO uint32_t HW_OCOTP_BOOT_CFG1;                /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */
66273        uint8_t RESERVED_8[12];
66274   __IO uint32_t HW_OCOTP_BOOT_CFG2;                /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */
66275        uint8_t RESERVED_9[12];
66276   __IO uint32_t HW_OCOTP_BOOT_CFG3;                /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */
66277        uint8_t RESERVED_10[12];
66278   __IO uint32_t HW_OCOTP_BOOT_CFG4;                /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */
66279        uint8_t RESERVED_11[332];
66280   __IO uint32_t HW_OCOTP_SJC_RESP0;                /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */
66281        uint8_t RESERVED_12[12];
66282   __IO uint32_t HW_OCOTP_SJC_RESP1;                /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */
66283        uint8_t RESERVED_13[12];
66284   __IO uint32_t HW_OCOTP_USB_ID;                   /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */
66285        uint8_t RESERVED_14[28];
66286   __IO uint32_t HW_OCOTP_MAC_ADDR0;                /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */
66287        uint8_t RESERVED_15[12];
66288   __IO uint32_t HW_OCOTP_MAC_ADDR1;                /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */
66289        uint8_t RESERVED_16[12];
66290   __IO uint32_t HW_OCOTP_MAC_ADDR2;                /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */
66291        uint8_t RESERVED_17[284];
66292   __IO uint32_t HW_OCOTP_GP10;                     /**< Value of OTP Bank14 Word0 (), offset: 0x780 */
66293        uint8_t RESERVED_18[12];
66294   __IO uint32_t HW_OCOTP_GP11;                     /**< Value of OTP Bank14 Word1 (), offset: 0x790 */
66295        uint8_t RESERVED_19[12];
66296   __IO uint32_t HW_OCOTP_GP20;                     /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */
66297        uint8_t RESERVED_20[12];
66298   __IO uint32_t HW_OCOTP_GP21;                     /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */
66299 } OCOTP_Type;
66300 
66301 /* ----------------------------------------------------------------------------
66302    -- OCOTP Register Masks
66303    ---------------------------------------------------------------------------- */
66304 
66305 /*!
66306  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
66307  * @{
66308  */
66309 
66310 /*! @name HW_OCOTP_CTRL - OTP Controller Control Register */
66311 /*! @{ */
66312 
66313 #define OCOTP_HW_OCOTP_CTRL_ADDR_MASK            (0x1FFU)
66314 #define OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT           (0U)
66315 #define OCOTP_HW_OCOTP_CTRL_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ADDR_MASK)
66316 
66317 #define OCOTP_HW_OCOTP_CTRL_BUSY_MASK            (0x200U)
66318 #define OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT           (9U)
66319 #define OCOTP_HW_OCOTP_CTRL_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_BUSY_MASK)
66320 
66321 #define OCOTP_HW_OCOTP_CTRL_ERROR_MASK           (0x400U)
66322 #define OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT          (10U)
66323 #define OCOTP_HW_OCOTP_CTRL_ERROR(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ERROR_MASK)
66324 
66325 #define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK  (0x800U)
66326 #define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (11U)
66327 #define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK)
66328 
66329 #define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK       (0xFFFF0000U)
66330 #define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT      (16U)
66331 #define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK)
66332 /*! @} */
66333 
66334 /*! @name HW_OCOTP_CTRL_SET - OTP Controller Control Register */
66335 /*! @{ */
66336 
66337 #define OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK        (0xFFU)
66338 #define OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT       (0U)
66339 #define OCOTP_HW_OCOTP_CTRL_SET_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK)
66340 
66341 #define OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK        (0x100U)
66342 #define OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT       (8U)
66343 #define OCOTP_HW_OCOTP_CTRL_SET_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK)
66344 
66345 #define OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK       (0x200U)
66346 #define OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT      (9U)
66347 #define OCOTP_HW_OCOTP_CTRL_SET_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK)
66348 
66349 #define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
66350 #define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
66351 #define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
66352 
66353 #define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK   (0xFFFF0000U)
66354 #define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT  (16U)
66355 #define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK)
66356 /*! @} */
66357 
66358 /*! @name HW_OCOTP_CTRL_CLR - OTP Controller Control Register */
66359 /*! @{ */
66360 
66361 #define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK        (0xFFU)
66362 #define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT       (0U)
66363 #define OCOTP_HW_OCOTP_CTRL_CLR_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK)
66364 
66365 #define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK        (0x100U)
66366 #define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT       (8U)
66367 #define OCOTP_HW_OCOTP_CTRL_CLR_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK)
66368 
66369 #define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK       (0x200U)
66370 #define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT      (9U)
66371 #define OCOTP_HW_OCOTP_CTRL_CLR_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK)
66372 
66373 #define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
66374 #define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
66375 #define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
66376 
66377 #define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK   (0xFFFF0000U)
66378 #define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT  (16U)
66379 #define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
66380 /*! @} */
66381 
66382 /*! @name HW_OCOTP_CTRL_TOG - OTP Controller Control Register */
66383 /*! @{ */
66384 
66385 #define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK        (0xFFU)
66386 #define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT       (0U)
66387 #define OCOTP_HW_OCOTP_CTRL_TOG_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK)
66388 
66389 #define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK        (0x100U)
66390 #define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT       (8U)
66391 #define OCOTP_HW_OCOTP_CTRL_TOG_BUSY(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK)
66392 
66393 #define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK       (0x200U)
66394 #define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT      (9U)
66395 #define OCOTP_HW_OCOTP_CTRL_TOG_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK)
66396 
66397 #define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
66398 #define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
66399 #define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
66400 
66401 #define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK   (0xFFFF0000U)
66402 #define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT  (16U)
66403 #define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
66404 /*! @} */
66405 
66406 /*! @name HW_OCOTP_TIMING - OTP Controller Timing Register */
66407 /*! @{ */
66408 
66409 #define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK   (0xFFFU)
66410 #define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT  (0U)
66411 #define OCOTP_HW_OCOTP_TIMING_STROBE_PROG(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK)
66412 
66413 #define OCOTP_HW_OCOTP_TIMING_RELAX_MASK         (0xF000U)
66414 #define OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT        (12U)
66415 #define OCOTP_HW_OCOTP_TIMING_RELAX(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_HW_OCOTP_TIMING_RELAX_MASK)
66416 
66417 #define OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK   (0x3F0000U)
66418 #define OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT  (16U)
66419 #define OCOTP_HW_OCOTP_TIMING_STROBE_READ(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK)
66420 
66421 #define OCOTP_HW_OCOTP_TIMING_WAIT_MASK          (0xFC00000U)
66422 #define OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT         (22U)
66423 #define OCOTP_HW_OCOTP_TIMING_WAIT(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_HW_OCOTP_TIMING_WAIT_MASK)
66424 /*! @} */
66425 
66426 /*! @name HW_OCOTP_DATA - OTP Controller Write Data Register */
66427 /*! @{ */
66428 
66429 #define OCOTP_HW_OCOTP_DATA_DATA_MASK            (0xFFFFFFFFU)
66430 #define OCOTP_HW_OCOTP_DATA_DATA_SHIFT           (0U)
66431 #define OCOTP_HW_OCOTP_DATA_DATA(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_DATA_DATA_SHIFT)) & OCOTP_HW_OCOTP_DATA_DATA_MASK)
66432 /*! @} */
66433 
66434 /*! @name HW_OCOTP_READ_CTRL - OTP Controller Write Data Register */
66435 /*! @{ */
66436 
66437 #define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK  (0x1U)
66438 #define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
66439 #define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK)
66440 /*! @} */
66441 
66442 /*! @name HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register */
66443 /*! @{ */
66444 
66445 #define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK  (0xFFFFFFFFU)
66446 #define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
66447 #define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA(x)    (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK)
66448 /*! @} */
66449 
66450 /*! @name HW_OCOTP_SCS - Software Controllable Signals Register */
66451 /*! @{ */
66452 
66453 #define OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK          (0x1U)
66454 #define OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT         (0U)
66455 #define OCOTP_HW_OCOTP_SCS_HAB_JDE(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK)
66456 
66457 #define OCOTP_HW_OCOTP_SCS_SPARE_MASK            (0x7FFFFFFEU)
66458 #define OCOTP_HW_OCOTP_SCS_SPARE_SHIFT           (1U)
66459 #define OCOTP_HW_OCOTP_SCS_SPARE(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SPARE_MASK)
66460 
66461 #define OCOTP_HW_OCOTP_SCS_LOCK_MASK             (0x80000000U)
66462 #define OCOTP_HW_OCOTP_SCS_LOCK_SHIFT            (31U)
66463 #define OCOTP_HW_OCOTP_SCS_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_LOCK_MASK)
66464 /*! @} */
66465 
66466 /*! @name HW_OCOTP_SCS_SET - Software Controllable Signals Register */
66467 /*! @{ */
66468 
66469 #define OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK        (0x7FFFFFFEU)
66470 #define OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT       (1U)
66471 #define OCOTP_HW_OCOTP_SCS_SET_SPARE(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK)
66472 
66473 #define OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK         (0x80000000U)
66474 #define OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT        (31U)
66475 #define OCOTP_HW_OCOTP_SCS_SET_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK)
66476 /*! @} */
66477 
66478 /*! @name HW_OCOTP_SCS_CLR - Software Controllable Signals Register */
66479 /*! @{ */
66480 
66481 #define OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK        (0x7FFFFFFEU)
66482 #define OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT       (1U)
66483 #define OCOTP_HW_OCOTP_SCS_CLR_SPARE(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK)
66484 
66485 #define OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK         (0x80000000U)
66486 #define OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT        (31U)
66487 #define OCOTP_HW_OCOTP_SCS_CLR_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK)
66488 /*! @} */
66489 
66490 /*! @name HW_OCOTP_SCS_TOG - Software Controllable Signals Register */
66491 /*! @{ */
66492 
66493 #define OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK        (0x7FFFFFFEU)
66494 #define OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT       (1U)
66495 #define OCOTP_HW_OCOTP_SCS_TOG_SPARE(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK)
66496 
66497 #define OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK         (0x80000000U)
66498 #define OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT        (31U)
66499 #define OCOTP_HW_OCOTP_SCS_TOG_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK)
66500 /*! @} */
66501 
66502 /*! @name HW_OCOTP_VERSION - OTP Controller Version Register */
66503 /*! @{ */
66504 
66505 #define OCOTP_HW_OCOTP_VERSION_STEP_MASK         (0xFFFFU)
66506 #define OCOTP_HW_OCOTP_VERSION_STEP_SHIFT        (0U)
66507 #define OCOTP_HW_OCOTP_VERSION_STEP(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_STEP_SHIFT)) & OCOTP_HW_OCOTP_VERSION_STEP_MASK)
66508 
66509 #define OCOTP_HW_OCOTP_VERSION_MINOR_MASK        (0xFF0000U)
66510 #define OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT       (16U)
66511 #define OCOTP_HW_OCOTP_VERSION_MINOR(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MINOR_MASK)
66512 
66513 #define OCOTP_HW_OCOTP_VERSION_MAJOR_MASK        (0xFF000000U)
66514 #define OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT       (24U)
66515 #define OCOTP_HW_OCOTP_VERSION_MAJOR(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MAJOR_MASK)
66516 /*! @} */
66517 
66518 /*! @name HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) */
66519 /*! @{ */
66520 
66521 #define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK        (0xCU)
66522 #define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT       (2U)
66523 #define OCOTP_HW_OCOTP_LOCK_BOOT_CFG(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK)
66524 
66525 #define OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK        (0x400U)
66526 #define OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT       (10U)
66527 #define OCOTP_HW_OCOTP_LOCK_SJC_RESP(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK)
66528 
66529 #define OCOTP_HW_OCOTP_LOCK_USB_ID_MASK          (0x3000U)
66530 #define OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT         (12U)
66531 #define OCOTP_HW_OCOTP_LOCK_USB_ID(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_HW_OCOTP_LOCK_USB_ID_MASK)
66532 
66533 #define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK        (0xC000U)
66534 #define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT       (14U)
66535 #define OCOTP_HW_OCOTP_LOCK_MAC_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK)
66536 
66537 #define OCOTP_HW_OCOTP_LOCK_GP1_MASK             (0x300000U)
66538 #define OCOTP_HW_OCOTP_LOCK_GP1_SHIFT            (20U)
66539 #define OCOTP_HW_OCOTP_LOCK_GP1(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP1_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP1_MASK)
66540 
66541 #define OCOTP_HW_OCOTP_LOCK_GP2_MASK             (0xC00000U)
66542 #define OCOTP_HW_OCOTP_LOCK_GP2_SHIFT            (22U)
66543 #define OCOTP_HW_OCOTP_LOCK_GP2(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP2_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP2_MASK)
66544 /*! @} */
66545 
66546 /*! @name HW_OCOTP_BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */
66547 /*! @{ */
66548 
66549 #define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK       (0xFFFFFFFFU)
66550 #define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT      (0U)
66551 #define OCOTP_HW_OCOTP_BOOT_CFG0_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK)
66552 /*! @} */
66553 
66554 /*! @name HW_OCOTP_BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */
66555 /*! @{ */
66556 
66557 #define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK       (0xFFFFFFFFU)
66558 #define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT      (0U)
66559 #define OCOTP_HW_OCOTP_BOOT_CFG1_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK)
66560 /*! @} */
66561 
66562 /*! @name HW_OCOTP_BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */
66563 /*! @{ */
66564 
66565 #define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK       (0xFFFFFFFFU)
66566 #define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT      (0U)
66567 #define OCOTP_HW_OCOTP_BOOT_CFG2_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK)
66568 /*! @} */
66569 
66570 /*! @name HW_OCOTP_BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */
66571 /*! @{ */
66572 
66573 #define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK       (0xFFFFFFFFU)
66574 #define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT      (0U)
66575 #define OCOTP_HW_OCOTP_BOOT_CFG3_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK)
66576 /*! @} */
66577 
66578 /*! @name HW_OCOTP_BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */
66579 /*! @{ */
66580 
66581 #define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK       (0xFFFFFFFFU)
66582 #define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT      (0U)
66583 #define OCOTP_HW_OCOTP_BOOT_CFG4_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK)
66584 /*! @} */
66585 
66586 /*! @name HW_OCOTP_SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */
66587 /*! @{ */
66588 
66589 #define OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK       (0xFFFFFFFFU)
66590 #define OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT      (0U)
66591 #define OCOTP_HW_OCOTP_SJC_RESP0_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK)
66592 /*! @} */
66593 
66594 /*! @name HW_OCOTP_SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */
66595 /*! @{ */
66596 
66597 #define OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK       (0xFFFFFFFFU)
66598 #define OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT      (0U)
66599 #define OCOTP_HW_OCOTP_SJC_RESP1_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK)
66600 /*! @} */
66601 
66602 /*! @name HW_OCOTP_USB_ID - Value of OTP Bank8 Word2 (USB ID info) */
66603 /*! @{ */
66604 
66605 #define OCOTP_HW_OCOTP_USB_ID_BITS_MASK          (0xFFFFFFFFU)
66606 #define OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT         (0U)
66607 #define OCOTP_HW_OCOTP_USB_ID_BITS(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_HW_OCOTP_USB_ID_BITS_MASK)
66608 /*! @} */
66609 
66610 /*! @name HW_OCOTP_MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */
66611 /*! @{ */
66612 
66613 #define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK       (0xFFFFFFFFU)
66614 #define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT      (0U)
66615 #define OCOTP_HW_OCOTP_MAC_ADDR0_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK)
66616 /*! @} */
66617 
66618 /*! @name HW_OCOTP_MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */
66619 /*! @{ */
66620 
66621 #define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK       (0xFFFFFFFFU)
66622 #define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT      (0U)
66623 #define OCOTP_HW_OCOTP_MAC_ADDR1_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK)
66624 /*! @} */
66625 
66626 /*! @name HW_OCOTP_MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */
66627 /*! @{ */
66628 
66629 #define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK       (0xFFFFFFFFU)
66630 #define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT      (0U)
66631 #define OCOTP_HW_OCOTP_MAC_ADDR2_BITS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK)
66632 /*! @} */
66633 
66634 /*! @name HW_OCOTP_GP10 - Value of OTP Bank14 Word0 () */
66635 /*! @{ */
66636 
66637 #define OCOTP_HW_OCOTP_GP10_BITS_MASK            (0xFFFFFFFFU)
66638 #define OCOTP_HW_OCOTP_GP10_BITS_SHIFT           (0U)
66639 #define OCOTP_HW_OCOTP_GP10_BITS(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP10_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP10_BITS_MASK)
66640 /*! @} */
66641 
66642 /*! @name HW_OCOTP_GP11 - Value of OTP Bank14 Word1 () */
66643 /*! @{ */
66644 
66645 #define OCOTP_HW_OCOTP_GP11_BITS_MASK            (0xFFFFFFFFU)
66646 #define OCOTP_HW_OCOTP_GP11_BITS_SHIFT           (0U)
66647 #define OCOTP_HW_OCOTP_GP11_BITS(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP11_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP11_BITS_MASK)
66648 /*! @} */
66649 
66650 /*! @name HW_OCOTP_GP20 - Value of OTP Bank14 Word2 () */
66651 /*! @{ */
66652 
66653 #define OCOTP_HW_OCOTP_GP20_BITS_MASK            (0xFFFFFFFFU)
66654 #define OCOTP_HW_OCOTP_GP20_BITS_SHIFT           (0U)
66655 #define OCOTP_HW_OCOTP_GP20_BITS(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP20_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP20_BITS_MASK)
66656 /*! @} */
66657 
66658 /*! @name HW_OCOTP_GP21 - Value of OTP Bank14 Word3 () */
66659 /*! @{ */
66660 
66661 #define OCOTP_HW_OCOTP_GP21_BITS_MASK            (0xFFFFFFFFU)
66662 #define OCOTP_HW_OCOTP_GP21_BITS_SHIFT           (0U)
66663 #define OCOTP_HW_OCOTP_GP21_BITS(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP21_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP21_BITS_MASK)
66664 /*! @} */
66665 
66666 
66667 /*!
66668  * @}
66669  */ /* end of group OCOTP_Register_Masks */
66670 
66671 
66672 /* OCOTP - Peripheral instance base addresses */
66673 /** Peripheral OCOTP base address */
66674 #define OCOTP_BASE                               (0x30350000u)
66675 /** Peripheral OCOTP base pointer */
66676 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
66677 /** Array initializer of OCOTP peripheral base addresses */
66678 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
66679 /** Array initializer of OCOTP peripheral base pointers */
66680 #define OCOTP_BASE_PTRS                          { OCOTP }
66681 
66682 /*!
66683  * @}
66684  */ /* end of group OCOTP_Peripheral_Access_Layer */
66685 
66686 
66687 /* ----------------------------------------------------------------------------
66688    -- PCIE Peripheral Access Layer
66689    ---------------------------------------------------------------------------- */
66690 
66691 /*!
66692  * @addtogroup PCIE_Peripheral_Access_Layer PCIE Peripheral Access Layer
66693  * @{
66694  */
66695 
66696 /** PCIE - Register Layout Typedef */
66697 typedef struct {
66698   __IO uint32_t TYPE1_DEV_ID_VEND_ID_REG;          /**< Device ID and Vendor ID Register., offset: 0x0 */
66699   __IO uint32_t TYPE1_STATUS_COMMAND_REG;          /**< Status and Command Register., offset: 0x4 */
66700   __IO uint32_t TYPE1_CLASS_CODE_REV_ID_REG;       /**< Class Code and Revision ID Register., offset: 0x8 */
66701   __IO uint32_t TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG; /**< Header Type, Latency Timer, and Cache Line Size Register., offset: 0xC */
66702        uint8_t RESERVED_0[8];
66703   __IO uint32_t SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG; /**< Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register., offset: 0x18 */
66704   __IO uint32_t SEC_STAT_IO_LIMIT_IO_BASE_REG;     /**< Secondary Status, and I/O Limit and Base Register., offset: 0x1C */
66705   __IO uint32_t MEM_LIMIT_MEM_BASE_REG;            /**< Memory Limit and Base Register., offset: 0x20 */
66706   __IO uint32_t PREF_MEM_LIMIT_PREF_MEM_BASE_REG;  /**< Prefetchable Memory Limit and Base Register., offset: 0x24 */
66707   __I  uint32_t PREF_BASE_UPPER_REG;               /**< Prefetchable Base Upper 32 Bits Register., offset: 0x28 */
66708   __I  uint32_t PREF_LIMIT_UPPER_REG;              /**< Prefetchable Limit Upper 32 Bits Register., offset: 0x2C */
66709   __I  uint32_t IO_LIMIT_UPPER_IO_BASE_UPPER_REG;  /**< I/O Limit and Base Upper 16 Bits Register., offset: 0x30 */
66710   __IO uint32_t TYPE1_CAP_PTR_REG;                 /**< Capabilities Pointer Register., offset: 0x34 */
66711   __IO uint32_t TYPE1_EXP_ROM_BASE_REG;            /**< Expansion ROM Base Address Register., offset: 0x38 */
66712   __IO uint32_t BRIDGE_CTRL_INT_PIN_INT_LINE_REG;  /**< Bridge Control, Interrupt Pin, and Interrupt Line Register., offset: 0x3C */
66713   __IO uint32_t CAP_ID_NXT_PTR_REG;                /**< Power Management Capabilities Register., offset: 0x40 */
66714   __IO uint32_t CON_STATUS_REG;                    /**< Power Management Control and Status Register., offset: 0x44 */
66715        uint8_t RESERVED_1[8];
66716   __IO uint32_t PCI_MSI_CAP_ID_NEXT_CTRL_REG;      /**< MSI Capability ID, Next Pointer, Capability/Control Registers., offset: 0x50 */
66717   __IO uint32_t MSI_CAP_OFF_04H_REG;               /**< MSI Message Lower Address Register., offset: 0x54 */
66718   __IO uint32_t MSI_CAP_OFF_08H_REG;               /**< For a 32 bit MSI Message, this register contains Data., offset: 0x58 */
66719   __IO uint32_t MSI_CAP_OFF_0CH_REG;               /**< For a 64 bit MSI Message, this register contains Data., offset: 0x5C */
66720   __IO uint32_t MSI_CAP_OFF_10H_REG;               /**< Used for MSI when Vector Masking Capable., offset: 0x60 */
66721   __I  uint32_t MSI_CAP_OFF_14H_REG;               /**< Used for MSI 64 bit messaging when Vector Masking Capable., offset: 0x64 */
66722        uint8_t RESERVED_2[8];
66723   __IO uint32_t PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG; /**< PCI Express Capabilities, ID, Next Pointer Register., offset: 0x70 */
66724   __IO uint32_t DEVICE_CAPABILITIES_REG;           /**< Device Capabilities Register., offset: 0x74 */
66725   __IO uint32_t DEVICE_CONTROL_DEVICE_STATUS;      /**< Device Control and Status Register., offset: 0x78 */
66726   __IO uint32_t LINK_CAPABILITIES_REG;             /**< Link Capabilities Register., offset: 0x7C */
66727   __IO uint32_t LINK_CONTROL_LINK_STATUS_REG;      /**< Link Control and Status Register., offset: 0x80 */
66728   __IO uint32_t SLOT_CAPABILITIES_REG;             /**< Slot Capabilities Register., offset: 0x84 */
66729   __IO uint32_t SLOT_CONTROL_SLOT_STATUS;          /**< Slot Control and Status Register., offset: 0x88 */
66730   __IO uint32_t ROOT_CONTROL_ROOT_CAPABILITIES_REG; /**< Root Control and Capabilities Register., offset: 0x8C */
66731   __IO uint32_t ROOT_STATUS_REG;                   /**< Root Status Register., offset: 0x90 */
66732   __I  uint32_t DEVICE_CAPABILITIES2_REG;          /**< Device Capabilities 2 Register., offset: 0x94 */
66733   __IO uint32_t DEVICE_CONTROL2_DEVICE_STATUS2_REG; /**< Device Control 2 and Status 2 Register., offset: 0x98 */
66734   __I  uint32_t LINK_CAPABILITIES2_REG;            /**< Link Capabilities 2 Register., offset: 0x9C */
66735   __IO uint32_t LINK_CONTROL2_LINK_STATUS2_REG;    /**< Link Control 2 and Status 2 Register., offset: 0xA0 */
66736        uint8_t RESERVED_3[92];
66737   __IO uint32_t AER_EXT_CAP_HDR_OFF;               /**< Advanced Error Reporting Extended Capability Header., offset: 0x100 */
66738   __IO uint32_t UNCORR_ERR_STATUS_OFF;             /**< Uncorrectable Error Status Register., offset: 0x104 */
66739   __IO uint32_t UNCORR_ERR_MASK_OFF;               /**< Uncorrectable Error Mask Register., offset: 0x108 */
66740   __IO uint32_t UNCORR_ERR_SEV_OFF;                /**< Uncorrectable Error Severity Register., offset: 0x10C */
66741   __IO uint32_t CORR_ERR_STATUS_OFF;               /**< Correctable Error Status Register., offset: 0x110 */
66742   __IO uint32_t CORR_ERR_MASK_OFF;                 /**< Correctable Error Mask Register., offset: 0x114 */
66743   __IO uint32_t ADV_ERR_CAP_CTRL_OFF;              /**< Advanced Error Capabilities and Control Register., offset: 0x118 */
66744   __I  uint32_t HDR_LOG_0_OFF;                     /**< Header Log Register 0., offset: 0x11C */
66745   __I  uint32_t HDR_LOG_1_OFF;                     /**< Header Log Register 1., offset: 0x120 */
66746   __I  uint32_t HDR_LOG_2_OFF;                     /**< Header Log Register 2., offset: 0x124 */
66747   __I  uint32_t HDR_LOG_3_OFF;                     /**< Header Log Register 3., offset: 0x128 */
66748   __IO uint32_t ROOT_ERR_CMD_OFF;                  /**< Root Error Command Register., offset: 0x12C */
66749   __IO uint32_t ROOT_ERR_STATUS_OFF;               /**< Root Error Status Register., offset: 0x130 */
66750   __I  uint32_t ERR_SRC_ID_OFF;                    /**< Error Source Identification Register., offset: 0x134 */
66751   __I  uint32_t TLP_PREFIX_LOG_1_OFF;              /**< TLP Prefix Log Register 1., offset: 0x138 */
66752   __I  uint32_t TLP_PREFIX_LOG_2_OFF;              /**< TLP Prefix Log Register 2., offset: 0x13C */
66753   __I  uint32_t TLP_PREFIX_LOG_3_OFF;              /**< TLP Prefix Log Register 3., offset: 0x140 */
66754   __I  uint32_t TLP_PREFIX_LOG_4_OFF;              /**< TLP Prefix Log Register 4., offset: 0x144 */
66755        uint8_t RESERVED_4[16];
66756   __IO uint32_t L1SUB_CAP_HEADER_REG;              /**< L1 Substates Extended Capability Header., offset: 0x158 */
66757   __IO uint32_t L1SUB_CAPABILITY_REG;              /**< L1 Substates Capability Register., offset: 0x15C */
66758   __IO uint32_t L1SUB_CONTROL1_REG;                /**< L1 Substates Control 1 Register., offset: 0x160 */
66759   __IO uint32_t L1SUB_CONTROL2_REG;                /**< L1 Substates Control 2 Register., offset: 0x164 */
66760        uint8_t RESERVED_5[1432];
66761   __IO uint32_t ACK_LATENCY_TIMER_OFF;             /**< Ack Latency Timer and Replay Timer Register., offset: 0x700 */
66762   __IO uint32_t VENDOR_SPEC_DLLP_OFF;              /**< Vendor Specific DLLP Register., offset: 0x704 */
66763   __IO uint32_t PORT_FORCE_OFF;                    /**< Port Force Link Register., offset: 0x708 */
66764   __IO uint32_t ACK_F_ASPM_CTRL_OFF;               /**< Ack Frequency and L0-L1 ASPM Control Register., offset: 0x70C */
66765   __IO uint32_t PORT_LINK_CTRL_OFF;                /**< Port Link Control Register., offset: 0x710 */
66766   __IO uint32_t LANE_SKEW_OFF;                     /**< Lane Skew Register., offset: 0x714 */
66767   __IO uint32_t TIMER_CTRL_MAX_FUNC_NUM_OFF;       /**< Timer Control and Max Function Number Register., offset: 0x718 */
66768   __IO uint32_t SYMBOL_TIMER_FILTER_1_OFF;         /**< Symbol Timer Register and Filter Mask 1 Register., offset: 0x71C */
66769   __IO uint32_t FILTER_MASK_2_OFF;                 /**< Filter Mask 2 Register., offset: 0x720 */
66770   __IO uint32_t AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF; /**< AMBA Multiple Outbound Decomposed NP SubRequests Control Register., offset: 0x724 */
66771   __I  uint32_t PL_DEBUG0_OFF;                     /**< Debug Register 0, offset: 0x728 */
66772   __I  uint32_t PL_DEBUG1_OFF;                     /**< Debug Register 1, offset: 0x72C */
66773   __I  uint32_t TX_P_FC_CREDIT_STATUS_OFF;         /**< Transmit Posted FC Credit Status, offset: 0x730 */
66774   __I  uint32_t TX_NP_FC_CREDIT_STATUS_OFF;        /**< Transmit Non-Posted FC Credit Status, offset: 0x734 */
66775   __I  uint32_t TX_CPL_FC_CREDIT_STATUS_OFF;       /**< Transmit Completion FC Credit Status, offset: 0x738 */
66776   __IO uint32_t QUEUE_STATUS_OFF;                  /**< Queue Status, offset: 0x73C */
66777   __I  uint32_t VC_TX_ARBI_1_OFF;                  /**< VC Transmit Arbitration Register 1, offset: 0x740 */
66778        uint8_t RESERVED_6[4];
66779   __IO uint32_t VC0_P_RX_Q_CTRL_OFF;               /**< Segmented-Buffer VC0 Posted Receive Queue Control., offset: 0x748 */
66780   __IO uint32_t VC0_NP_RX_Q_CTRL_OFF;              /**< Segmented-Buffer VC0 Non-Posted Receive Queue Control., offset: 0x74C */
66781   __IO uint32_t VC0_CPL_RX_Q_CTRL_OFF;             /**< Segmented-Buffer VC0 Completion Receive Queue Control., offset: 0x750 */
66782        uint8_t RESERVED_7[184];
66783   __IO uint32_t GEN2_CTRL_OFF;                     /**< Link Width and Speed Change Control Register., offset: 0x80C */
66784   __I  uint32_t PHY_STATUS_OFF;                    /**< PHY Status Register., offset: 0x810 */
66785   __IO uint32_t PHY_CONTROL_OFF;                   /**< PHY Control Register., offset: 0x814 */
66786        uint8_t RESERVED_8[4];
66787   __IO uint32_t TRGT_MAP_CTRL_OFF;                 /**< Programmable Target Map Control Register., offset: 0x81C */
66788   __IO uint32_t MSI_CTRL_ADDR_OFF;                 /**< Integrated MSI Reception Module (iMRM) Address Register., offset: 0x820 */
66789   __IO uint32_t MSI_CTRL_UPPER_ADDR_OFF;           /**< Integrated MSI Reception Module Upper Address Register., offset: 0x824 */
66790   __IO uint32_t MSI_CTRL_INT_0_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x828 */
66791   __IO uint32_t MSI_CTRL_INT_0_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x82C */
66792   __IO uint32_t MSI_CTRL_INT_0_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x830 */
66793   __IO uint32_t MSI_CTRL_INT_1_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x834 */
66794   __IO uint32_t MSI_CTRL_INT_1_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x838 */
66795   __IO uint32_t MSI_CTRL_INT_1_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x83C */
66796   __IO uint32_t MSI_CTRL_INT_2_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x840 */
66797   __IO uint32_t MSI_CTRL_INT_2_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x844 */
66798   __IO uint32_t MSI_CTRL_INT_2_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x848 */
66799   __IO uint32_t MSI_CTRL_INT_3_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x84C */
66800   __IO uint32_t MSI_CTRL_INT_3_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x850 */
66801   __IO uint32_t MSI_CTRL_INT_3_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x854 */
66802   __IO uint32_t MSI_CTRL_INT_4_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x858 */
66803   __IO uint32_t MSI_CTRL_INT_4_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x85C */
66804   __IO uint32_t MSI_CTRL_INT_4_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x860 */
66805   __IO uint32_t MSI_CTRL_INT_5_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x864 */
66806   __IO uint32_t MSI_CTRL_INT_5_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x868 */
66807   __IO uint32_t MSI_CTRL_INT_5_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x86C */
66808   __IO uint32_t MSI_CTRL_INT_6_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x870 */
66809   __IO uint32_t MSI_CTRL_INT_6_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x874 */
66810   __IO uint32_t MSI_CTRL_INT_6_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x878 */
66811   __IO uint32_t MSI_CTRL_INT_7_EN_OFF;             /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x87C */
66812   __IO uint32_t MSI_CTRL_INT_7_MASK_OFF;           /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x880 */
66813   __IO uint32_t MSI_CTRL_INT_7_STATUS_OFF;         /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x884 */
66814   __IO uint32_t MSI_GPIO_IO_OFF;                   /**< Integrated MSI Reception Module General Purpose IO Register., offset: 0x888 */
66815   __IO uint32_t CLOCK_GATING_CTRL_OFF;             /**< RADM clock gating enable control register., offset: 0x88C */
66816        uint8_t RESERVED_9[36];
66817   __IO uint32_t ORDER_RULE_CTRL_OFF;               /**< Order Rule Control Register., offset: 0x8B4 */
66818   __IO uint32_t PIPE_LOOPBACK_CONTROL_OFF;         /**< PIPE Loopback Control Register., offset: 0x8B8 */
66819   __IO uint32_t MISC_CONTROL_1_OFF;                /**< DBI Read-Only Write Enable Register., offset: 0x8BC */
66820   __IO uint32_t MULTI_LANE_CONTROL_OFF;            /**< UpConfigure Multi-lane Control Register., offset: 0x8C0 */
66821   __IO uint32_t PHY_INTEROP_CTRL_OFF;              /**< PHY Interoperability Control Register., offset: 0x8C4 */
66822   __IO uint32_t TRGT_CPL_LUT_DELETE_ENTRY_OFF;     /**< TRGT_CPL_LUT Delete Entry Control register., offset: 0x8C8 */
66823   __IO uint32_t LINK_FLUSH_CONTROL_OFF;            /**< Link Reset Request Flush Control Register., offset: 0x8CC */
66824   __IO uint32_t AMBA_ERROR_RESPONSE_DEFAULT_OFF;   /**< AXI Bridge Slave Error Response Register., offset: 0x8D0 */
66825   __IO uint32_t AMBA_LINK_TIMEOUT_OFF;             /**< Link Down AXI Bridge Slave Timeout Register., offset: 0x8D4 */
66826   __IO uint32_t AMBA_ORDERING_CTRL_OFF;            /**< AMBA Ordering Control., offset: 0x8D8 */
66827        uint8_t RESERVED_10[20];
66828   __IO uint32_t AXI_MSTR_MSG_ADDR_LOW_OFF;         /**< Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to., offset: 0x8F0 */
66829   __IO uint32_t AXI_MSTR_MSG_ADDR_HIGH_OFF;        /**< Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to., offset: 0x8F4 */
66830   __I  uint32_t PCIE_VERSION_NUMBER_OFF;           /**< PCIe Controller IIP Release Version Number., offset: 0x8F8 */
66831   __I  uint32_t PCIE_VERSION_TYPE_OFF;             /**< PCIe Controller IIP Release Version Type., offset: 0x8FC */
66832        uint8_t RESERVED_11[576];
66833   __IO uint32_t AUX_CLK_FREQ_OFF;                  /**< Auxiliary Clock Frequency Control Register., offset: 0xB40 */
66834   __IO uint32_t L1_SUBSTATES_OFF;                  /**< L1 Substates Timing Register., offset: 0xB44 */
66835        uint8_t RESERVED_12[3142840];
66836   __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_0; /**< iATU Region Control 1 Register., offset: 0x300000 */
66837   __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_0; /**< iATU Region Control 2 Register., offset: 0x300004 */
66838   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0; /**< iATU Lower Base Address Register., offset: 0x300008 */
66839   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Base Address Register., offset: 0x30000C */
66840   __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_0;    /**< iATU Limit Address Register., offset: 0x300010 */
66841   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0; /**< iATU Lower Target Address Register., offset: 0x300014 */
66842   __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Target Address Register., offset: 0x300018 */
66843        uint8_t RESERVED_13[228];
66844   __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_0;  /**< iATU Region Control 1 Register., offset: 0x300100 */
66845   __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_0;  /**< iATU Region Control 2 Register., offset: 0x300104 */
66846   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_0;  /**< iATU Lower Base Address Register., offset: 0x300108 */
66847   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_0; /**< iATU Upper Base Address Register., offset: 0x30010C */
66848   __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_0;     /**< iATU Limit Address Register., offset: 0x300110 */
66849   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_0; /**< iATU Lower Target Address Register., offset: 0x300114 */
66850        uint8_t RESERVED_14[232];
66851   __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_1; /**< iATU Region Control 1 Register., offset: 0x300200 */
66852   __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_1; /**< iATU Region Control 2 Register., offset: 0x300204 */
66853   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1; /**< iATU Lower Base Address Register., offset: 0x300208 */
66854   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Base Address Register., offset: 0x30020C */
66855   __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_1;    /**< iATU Limit Address Register., offset: 0x300210 */
66856   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1; /**< iATU Lower Target Address Register., offset: 0x300214 */
66857   __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Target Address Register., offset: 0x300218 */
66858        uint8_t RESERVED_15[228];
66859   __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_1;  /**< iATU Region Control 1 Register., offset: 0x300300 */
66860   __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_1;  /**< iATU Region Control 2 Register., offset: 0x300304 */
66861   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_1;  /**< iATU Lower Base Address Register., offset: 0x300308 */
66862   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_1; /**< iATU Upper Base Address Register., offset: 0x30030C */
66863   __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_1;     /**< iATU Limit Address Register., offset: 0x300310 */
66864   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_1; /**< iATU Lower Target Address Register., offset: 0x300314 */
66865        uint8_t RESERVED_16[232];
66866   __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_2; /**< iATU Region Control 1 Register., offset: 0x300400 */
66867   __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_2; /**< iATU Region Control 2 Register., offset: 0x300404 */
66868   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2; /**< iATU Lower Base Address Register., offset: 0x300408 */
66869   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Base Address Register., offset: 0x30040C */
66870   __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_2;    /**< iATU Limit Address Register., offset: 0x300410 */
66871   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2; /**< iATU Lower Target Address Register., offset: 0x300414 */
66872   __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Target Address Register., offset: 0x300418 */
66873        uint8_t RESERVED_17[228];
66874   __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_2;  /**< iATU Region Control 1 Register., offset: 0x300500 */
66875   __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_2;  /**< iATU Region Control 2 Register., offset: 0x300504 */
66876   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_2;  /**< iATU Lower Base Address Register., offset: 0x300508 */
66877   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_2; /**< iATU Upper Base Address Register., offset: 0x30050C */
66878   __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_2;     /**< iATU Limit Address Register., offset: 0x300510 */
66879   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_2; /**< iATU Lower Target Address Register., offset: 0x300514 */
66880        uint8_t RESERVED_18[232];
66881   __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_3; /**< iATU Region Control 1 Register., offset: 0x300600 */
66882   __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_3; /**< iATU Region Control 2 Register., offset: 0x300604 */
66883   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3; /**< iATU Lower Base Address Register., offset: 0x300608 */
66884   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Base Address Register., offset: 0x30060C */
66885   __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_3;    /**< iATU Limit Address Register., offset: 0x300610 */
66886   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3; /**< iATU Lower Target Address Register., offset: 0x300614 */
66887   __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Target Address Register., offset: 0x300618 */
66888        uint8_t RESERVED_19[228];
66889   __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_3;  /**< iATU Region Control 1 Register., offset: 0x300700 */
66890   __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_3;  /**< iATU Region Control 2 Register., offset: 0x300704 */
66891   __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_3;  /**< iATU Lower Base Address Register., offset: 0x300708 */
66892   __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_3; /**< iATU Upper Base Address Register., offset: 0x30070C */
66893   __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_3;     /**< iATU Limit Address Register., offset: 0x300710 */
66894   __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_3; /**< iATU Lower Target Address Register., offset: 0x300714 */
66895        uint8_t RESERVED_20[522472];
66896   __IO uint32_t DMA_CTRL_DATA_ARB_PRIOR_OFF;       /**< DMA Arbitration Scheme for TRGT1 Interface., offset: 0x380000 */
66897        uint8_t RESERVED_21[4];
66898   __IO uint32_t DMA_CTRL_OFF;                      /**< DMA Number of Channels Register., offset: 0x380008 */
66899   __IO uint32_t DMA_WRITE_ENGINE_EN_OFF;           /**< DMA Write Engine Enable Register., offset: 0x38000C */
66900   __IO uint32_t DMA_WRITE_DOORBELL_OFF;            /**< DMA Write Doorbell Register., offset: 0x380010 */
66901        uint8_t RESERVED_22[4];
66902   __IO uint32_t DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF; /**< DMA Write Engine Channel Arbitration Weight Low Register., offset: 0x380018 */
66903   __IO uint32_t DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF; /**< DMA Write Engine Channel Arbitration Weight High Register., offset: 0x38001C */
66904        uint8_t RESERVED_23[12];
66905   __IO uint32_t DMA_READ_ENGINE_EN_OFF;            /**< DMA Read Engine Enable Register., offset: 0x38002C */
66906   __IO uint32_t DMA_READ_DOORBELL_OFF;             /**< DMA Read Doorbell Register., offset: 0x380030 */
66907        uint8_t RESERVED_24[4];
66908   __IO uint32_t DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF; /**< DMA Read Engine Channel Arbitration Weight Low Register., offset: 0x380038 */
66909   __IO uint32_t DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF; /**< DMA Read Engine Channel Arbitration Weight High Register., offset: 0x38003C */
66910        uint8_t RESERVED_25[12];
66911   __IO uint32_t DMA_WRITE_INT_STATUS_OFF;          /**< DMA Write Interrupt Status Register., offset: 0x38004C */
66912        uint8_t RESERVED_26[4];
66913   __IO uint32_t DMA_WRITE_INT_MASK_OFF;            /**< DMA Write Interrupt Mask Register., offset: 0x380054 */
66914   __IO uint32_t DMA_WRITE_INT_CLEAR_OFF;           /**< DMA Write Interrupt Clear Register., offset: 0x380058 */
66915   __I  uint32_t DMA_WRITE_ERR_STATUS_OFF;          /**< DMA Write Error Status Register, offset: 0x38005C */
66916   __IO uint32_t DMA_WRITE_DONE_IMWR_LOW_OFF;       /**< DMA Write Done IMWr Address Low Register., offset: 0x380060 */
66917   __IO uint32_t DMA_WRITE_DONE_IMWR_HIGH_OFF;      /**< DMA Write Done IMWr Interrupt Address High Register., offset: 0x380064 */
66918   __IO uint32_t DMA_WRITE_ABORT_IMWR_LOW_OFF;      /**< DMA Write Abort IMWr Address Low Register., offset: 0x380068 */
66919   __IO uint32_t DMA_WRITE_ABORT_IMWR_HIGH_OFF;     /**< DMA Write Abort IMWr Address High Register., offset: 0x38006C */
66920   __IO uint32_t DMA_WRITE_CH01_IMWR_DATA_OFF;      /**< DMA Write Channel 1 and 0 IMWr Data Register., offset: 0x380070 */
66921   __IO uint32_t DMA_WRITE_CH23_IMWR_DATA_OFF;      /**< DMA Write Channel 3 and 2 IMWr Data Register., offset: 0x380074 */
66922   __IO uint32_t DMA_WRITE_CH45_IMWR_DATA_OFF;      /**< DMA Write Channel 5 and 4 IMWr Data Register., offset: 0x380078 */
66923   __IO uint32_t DMA_WRITE_CH67_IMWR_DATA_OFF;      /**< DMA Write Channel 7 and 6 IMWr Data Register., offset: 0x38007C */
66924        uint8_t RESERVED_27[16];
66925   __IO uint32_t DMA_WRITE_LINKED_LIST_ERR_EN_OFF;  /**< DMA Write Linked List Error Enable Register., offset: 0x380090 */
66926        uint8_t RESERVED_28[12];
66927   __IO uint32_t DMA_READ_INT_STATUS_OFF;           /**< DMA Read Interrupt Status Register., offset: 0x3800A0 */
66928        uint8_t RESERVED_29[4];
66929   __IO uint32_t DMA_READ_INT_MASK_OFF;             /**< DMA Read Interrupt Mask Register., offset: 0x3800A8 */
66930   __IO uint32_t DMA_READ_INT_CLEAR_OFF;            /**< DMA Read Interrupt Clear Register., offset: 0x3800AC */
66931        uint8_t RESERVED_30[4];
66932   __I  uint32_t DMA_READ_ERR_STATUS_LOW_OFF;       /**< DMA Read Error Status Low Register., offset: 0x3800B4 */
66933   __I  uint32_t DMA_READ_ERR_STATUS_HIGH_OFF;      /**< DMA Read Error Status High Register., offset: 0x3800B8 */
66934        uint8_t RESERVED_31[8];
66935   __IO uint32_t DMA_READ_LINKED_LIST_ERR_EN_OFF;   /**< DMA Read Linked List Error Enable Register., offset: 0x3800C4 */
66936        uint8_t RESERVED_32[4];
66937   __IO uint32_t DMA_READ_DONE_IMWR_LOW_OFF;        /**< DMA Read Done IMWr Address Low Register., offset: 0x3800CC */
66938   __IO uint32_t DMA_READ_DONE_IMWR_HIGH_OFF;       /**< DMA Read Done IMWr Address High Register., offset: 0x3800D0 */
66939   __IO uint32_t DMA_READ_ABORT_IMWR_LOW_OFF;       /**< DMA Read Abort IMWr Address Low Register., offset: 0x3800D4 */
66940   __IO uint32_t DMA_READ_ABORT_IMWR_HIGH_OFF;      /**< DMA Read Abort IMWr Address High Register., offset: 0x3800D8 */
66941   __IO uint32_t DMA_READ_CH01_IMWR_DATA_OFF;       /**< DMA Read Channel 1 and 0 IMWr Data Register., offset: 0x3800DC */
66942   __IO uint32_t DMA_READ_CH23_IMWR_DATA_OFF;       /**< DMA Read Channel 3 and 2 IMWr Data Register., offset: 0x3800E0 */
66943   __IO uint32_t DMA_READ_CH45_IMWR_DATA_OFF;       /**< DMA Read Channel 5 and 4 IMWr Data Register., offset: 0x3800E4 */
66944   __IO uint32_t DMA_READ_CH67_IMWR_DATA_OFF;       /**< DMA Read Channel 7 and 6 IMWr Data Register., offset: 0x3800E8 */
66945        uint8_t RESERVED_33[276];
66946   __IO uint32_t DMA_CH_CONTROL1_OFF_WRCH_0;        /**< DMA Write Channel Control 1 Register., offset: 0x380200 */
66947        uint8_t RESERVED_34[4];
66948   __IO uint32_t DMA_TRANSFER_SIZE_OFF_WRCH_0;      /**< DMA Write Transfer Size Register., offset: 0x380208 */
66949   __IO uint32_t DMA_SAR_LOW_OFF_WRCH_0;            /**< DMA Write SAR Low Register., offset: 0x38020C */
66950   __IO uint32_t DMA_SAR_HIGH_OFF_WRCH_0;           /**< DMA Write SAR High Register., offset: 0x380210 */
66951   __IO uint32_t DMA_DAR_LOW_OFF_WRCH_0;            /**< DMA Write DAR Low Register., offset: 0x380214 */
66952   __IO uint32_t DMA_DAR_HIGH_OFF_WRCH_0;           /**< DMA Write DAR High Register., offset: 0x380218 */
66953   __IO uint32_t DMA_LLP_LOW_OFF_WRCH_0;            /**< DMA Write Linked List Pointer Low Register., offset: 0x38021C */
66954   __IO uint32_t DMA_LLP_HIGH_OFF_WRCH_0;           /**< DMA Write Linked List Pointer High Register., offset: 0x380220 */
66955        uint8_t RESERVED_35[220];
66956   __IO uint32_t DMA_CH_CONTROL1_OFF_RDCH_0;        /**< DMA Read Channel Control 1 Register., offset: 0x380300 */
66957        uint8_t RESERVED_36[4];
66958   __IO uint32_t DMA_TRANSFER_SIZE_OFF_RDCH_0;      /**< DMA Read Transfer Size Register., offset: 0x380308 */
66959   __IO uint32_t DMA_SAR_LOW_OFF_RDCH_0;            /**< DMA Read SAR Low Register., offset: 0x38030C */
66960   __IO uint32_t DMA_SAR_HIGH_OFF_RDCH_0;           /**< DMA Read SAR High Register., offset: 0x380310 */
66961   __IO uint32_t DMA_DAR_LOW_OFF_RDCH_0;            /**< DMA Read DAR Low Register., offset: 0x380314 */
66962   __IO uint32_t DMA_DAR_HIGH_OFF_RDCH_0;           /**< DMA Read DAR High Register., offset: 0x380318 */
66963   __IO uint32_t DMA_LLP_LOW_OFF_RDCH_0;            /**< DMA Read Linked List Pointer Low Register., offset: 0x38031C */
66964   __IO uint32_t DMA_LLP_HIGH_OFF_RDCH_0;           /**< DMA Read Linked List Pointer High Register., offset: 0x380320 */
66965 } PCIE_Type;
66966 
66967 /* ----------------------------------------------------------------------------
66968    -- PCIE Register Masks
66969    ---------------------------------------------------------------------------- */
66970 
66971 /*!
66972  * @addtogroup PCIE_Register_Masks PCIE Register Masks
66973  * @{
66974  */
66975 
66976 /*! @name TYPE1_DEV_ID_VEND_ID_REG - Device ID and Vendor ID Register. */
66977 /*! @{ */
66978 
66979 #define PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MASK (0xFFFFU)
66980 #define PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SHIFT (0U)
66981 /*! VENDOR_ID - Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid
66982  *    vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to
66983  *    populate this register with a value of FFFFh, which is an invalid value for Vendor ID. Note:
66984  *    The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then
66985  *    R/W(sticky) else R(sticky) Note: This register field is sticky.
66986  */
66987 #define PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SHIFT)) & PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MASK)
66988 
66989 #define PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MASK (0xFFFF0000U)
66990 #define PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SHIFT (16U)
66991 /*! DEVICE_ID - Device ID. The Device ID register identifies the particular Function. This
66992  *    identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Dbi:
66993  *    if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
66994  */
66995 #define PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SHIFT)) & PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MASK)
66996 /*! @} */
66997 
66998 /*! @name TYPE1_STATUS_COMMAND_REG - Status and Command Register. */
66999 /*! @{ */
67000 
67001 #define PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_MASK (0x1U)
67002 #define PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_SHIFT (0U)
67003 /*! IO_EN - IO Space Enable. This bit controls a Function's response to I/O Space accesses received
67004  *    on its primary side. - When set, the Function is enabled to decode the address and further
67005  *    process I/O Space accesses. - When clear, all received I/O accesses are caused to be handled as
67006  *    Unsupported Requests. You cannot write to this register if your configuration has no IO bars;
67007  *    that is, the internal signal has_io_bar =0. Note: The access attributes of this field are as
67008  *    follows: - Dbi: !has_io_bar ? RO : RW
67009  */
67010 #define PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_MASK)
67011 
67012 #define PCIE_TYPE1_STATUS_COMMAND_REG_MSE_MASK   (0x2U)
67013 #define PCIE_TYPE1_STATUS_COMMAND_REG_MSE_SHIFT  (1U)
67014 /*! MSE - Memory Space Enable. This bit controls a Function's response to Memory Space accesses
67015  *    received on its primary side. - When set, the Function is enabled to decode the address and
67016  *    further process Memory Space accesses. - When clear, all received Memory Space accesses are caused
67017  *    to be handled as Unsupported Requests. You cannot write to this register if your configuration
67018  *    has no MEM bars; that is, the internal signal has_mem_bar =0. Note: The access attributes of
67019  *    this field are as follows: - Dbi: !has_mem_bar ? RO : RW
67020  */
67021 #define PCIE_TYPE1_STATUS_COMMAND_REG_MSE(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_MSE_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_MSE_MASK)
67022 
67023 #define PCIE_TYPE1_STATUS_COMMAND_REG_BME_MASK   (0x4U)
67024 #define PCIE_TYPE1_STATUS_COMMAND_REG_BME_SHIFT  (2U)
67025 /*! BME - Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the
67026  *    Upstream direction. When this bit is 0b, Memory and I/O Requests received at a Root Port must
67027  *    be handled as Unsupported Requests (UR) For Non-Posted Requests a Completion with UR
67028  *    completion status must be returned. This bit does not affect forwarding of Completions in either the
67029  *    Upstream or Downstream direction. The forwarding of Requests other than Memory or I/O Requests
67030  *    is not controlled by this bit.
67031  */
67032 #define PCIE_TYPE1_STATUS_COMMAND_REG_BME(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_BME_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_BME_MASK)
67033 
67034 #define PCIE_TYPE1_STATUS_COMMAND_REG_SCO_MASK   (0x8U)
67035 #define PCIE_TYPE1_STATUS_COMMAND_REG_SCO_SHIFT  (3U)
67036 /*! SCO - Special Cycle Enable. This bit was originally described in the PCI Local Bus
67037  *    Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
67038  */
67039 #define PCIE_TYPE1_STATUS_COMMAND_REG_SCO(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SCO_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SCO_MASK)
67040 
67041 #define PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_MASK (0x10U)
67042 #define PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_SHIFT (4U)
67043 /*! MWI_EN - Memory Write and Invalidate. This bit was originally described in the PCI Local Bus
67044  *    Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not
67045  *    apply to PCI Express. The controller hardwires this bit to 0b. For PCI Express to PCI/PCI-X
67046  *    Bridges, refer to the PCI Express to PCI/PCI-X Bridge Specification for requirements for this
67047  *    register.
67048  */
67049 #define PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_MASK)
67050 
67051 #define PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_MASK (0x20U)
67052 #define PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_SHIFT (5U)
67053 /*! VGAPS - VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification
67054  *    and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI
67055  *    Express. The controller hardwires this bit to 0b.
67056  */
67057 #define PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_MASK)
67058 
67059 #define PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_MASK (0x40U)
67060 #define PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_SHIFT (6U)
67061 /*! PERREN - Parity Error Response. This bit controls the logging of poisoned TLPs in the Master
67062  *    Data Parity Error bit in the Status register. For more details see the "Error Registers" section
67063  *    of the PCI Express Specification.
67064  */
67065 #define PCIE_TYPE1_STATUS_COMMAND_REG_PERREN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_MASK)
67066 
67067 #define PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_MASK (0x80U)
67068 #define PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_SHIFT (7U)
67069 /*! IDSEL - IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local
67070  *    Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires
67071  *    this bit to 0b.
67072  */
67073 #define PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_MASK)
67074 
67075 #define PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_MASK (0x100U)
67076 #define PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_SHIFT (8U)
67077 /*! SERREN - SERR# Enable. When set, this bit enables reporting upstream of Non-fatal and Fatal
67078  *    errors detected by the Function. Note: The errors are reported if enabled either through this bit
67079  *    or through the PCI Express specific bits in the Device Control register. For more details see
67080  *    the "Error Registers" section of the PCI Express Specification. In addition, this bit controls
67081  *    transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error Messages forwarded
67082  *    from the secondary interface. This bit does not affect the transmission of forwarded ERR_COR
67083  *    messages.
67084  */
67085 #define PCIE_TYPE1_STATUS_COMMAND_REG_SERREN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_MASK)
67086 
67087 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_MASK (0x200U)
67088 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_SHIFT (9U)
67089 /*! RSVDP_9 - Reserved for future use. */
67090 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_MASK)
67091 
67092 #define PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_MASK (0x400U)
67093 #define PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_SHIFT (10U)
67094 /*! INT_EN - Interrupt Disable. Controls the ability of a Function to generate INTx emulation
67095  *    interrupts. When set, Functions are prevented from asserting INTx interrupts. Note: - Any INTx
67096  *    emulation interrupts already asserted by the Function must be deasserted when this bit is set. INTx
67097  *    interrupts use virtual wires that must, if asserted, be deasserted using the appropriate
67098  *    Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s)
67099  *    associated with the Function(s) for which this bit is set are affected. - For Functions that generate
67100  *    INTx interrupts on their own behalf, this bit is required. This bit has no effect on interrupts
67101  *    forwarded from the secondary side. For Functions that do not generate INTx interrupts on
67102  *    their own behalf this bit is optional. If this bit is not implemented, the controller hardwires it
67103  *    to 0b.
67104  */
67105 #define PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_MASK)
67106 
67107 #define PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_MASK (0xF800U)
67108 #define PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_SHIFT (11U)
67109 /*! RESERV - Reserved. */
67110 #define PCIE_TYPE1_STATUS_COMMAND_REG_RESERV(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_MASK)
67111 
67112 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_MASK (0x60000U)
67113 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_SHIFT (17U)
67114 /*! RSVDP_17 - Reserved for future use. */
67115 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_MASK)
67116 
67117 #define PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MASK (0x80000U)
67118 #define PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SHIFT (19U)
67119 /*! INT_STATUS - Interrupt Status. When set, indicates that an INTx emulation interrupt is pending
67120  *    internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary
67121  *    side are not reflected in this bit. Setting the Interrupt Disable bit has no effect on the
67122  *    state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires
67123  *    this bit to 0b.
67124  */
67125 #define PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MASK)
67126 
67127 #define PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MASK (0x100000U)
67128 #define PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SHIFT (20U)
67129 /*! CAP_LIST - Capabilities List. Indicates the presence of an Extended Capability list item. Since
67130  *    all PCI Express device Functions are required to implement the PCI Express Capability
67131  *    structure, the controller hardwires this bit to 1b.
67132  */
67133 #define PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MASK)
67134 
67135 #define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK (0x200000U)
67136 #define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT (21U)
67137 /*! FAST_66MHZ_CAP - 66 MHz Capable. This bit was originally described in the PCI Local Bus
67138  *    Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to
67139  *    0b.
67140  */
67141 #define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK)
67142 
67143 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_MASK (0x400000U)
67144 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_SHIFT (22U)
67145 /*! RSVDP_22 - Reserved for future use. */
67146 #define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_MASK)
67147 
67148 #define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK (0x800000U)
67149 #define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT (23U)
67150 /*! FAST_B2B_CAP - Fast Back-to-Back Transactions Capable. This bit was originally described in the
67151  *    PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller
67152  *    hardwires this bit to 0b.
67153  */
67154 #define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK)
67155 
67156 #define PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MASK (0x1000000U)
67157 #define PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SHIFT (24U)
67158 /*! MASTER_DPE - Master Data Parity Error. This bit is set by a Function if the Parity Error
67159  *    Response bit in the Command register is 1b and either of the following two conditions occurs: - Port
67160  *    receives a Poisoned Completion going downstream - Port transmits a Poisoned Request upstream
67161  *    If the Parity Error Response bit is 0b, this bit is never set.
67162  */
67163 #define PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MASK)
67164 
67165 #define PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK (0x6000000U)
67166 #define PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT (25U)
67167 /*! DEV_SEL_TIMING - DEVSEL Timing. This field was originally described in the PCI Local Bus
67168  *    Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b.
67169  */
67170 #define PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK)
67171 
67172 #define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK (0x8000000U)
67173 #define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT (27U)
67174 /*! SIGNALED_TARGET_ABORT - Signaled Target Abort. This bit is set when a Function completes a
67175  *    Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the
67176  *    Completer Abort was generated by its primary side.
67177  */
67178 #define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK)
67179 
67180 #define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK (0x10000000U)
67181 #define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT (28U)
67182 /*! RCVD_TARGET_ABORT - Received Target Abort. This bit is set when a Requester receives a
67183  *    Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received
67184  *    by a Function's primary side.
67185  */
67186 #define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK)
67187 
67188 #define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK (0x20000000U)
67189 #define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT (29U)
67190 /*! RCVD_MASTER_ABORT - Received Master Abort. This bit is set when a Requester receives a
67191  *    Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is
67192  *    received by a Function's primary side.
67193  */
67194 #define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK)
67195 
67196 #define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MASK (0x40000000U)
67197 #define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SHIFT (30U)
67198 /*! SIGNALED_SYS_ERROR - Signaled System Error. This bit is set when a Function sends an ERR_FATAL
67199  *    or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1b.
67200  */
67201 #define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MASK)
67202 
67203 #define PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MASK (0x80000000U)
67204 #define PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SHIFT (31U)
67205 /*! DETECTED_PARITY_ERROR - Detected Parity Error. This bit is set by a Function whenever it
67206  *    receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command
67207  *    register. The bit is set when the Poisoned TLP is received by a Function's primary side.
67208  */
67209 #define PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MASK)
67210 /*! @} */
67211 
67212 /*! @name TYPE1_CLASS_CODE_REV_ID_REG - Class Code and Revision ID Register. */
67213 /*! @{ */
67214 
67215 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MASK (0xFFU)
67216 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SHIFT (0U)
67217 /*! REVISION_ID - Revision ID. The value of this field specifies a Function specific revision
67218  *    identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should
67219  *    be viewed as a vendor defined extension to the Device ID. Note: The access attributes of this
67220  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This
67221  *    register field is sticky.
67222  */
67223 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MASK)
67224 
67225 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MASK (0xFF00U)
67226 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SHIFT (8U)
67227 /*! PROGRAM_INTERFACE - Programming Interface. This field identifies a specific register level
67228  *    programming interface (if any) so that device independent software can interact with the Function.
67229  *    Encodings for interface are provided in the PCI Code and ID Assignment Specification. All
67230  *    unspecified encodings are reserved. Note: The access attributes of this field are as follows: -
67231  *    Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
67232  */
67233 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MASK)
67234 
67235 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MASK (0xFF0000U)
67236 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SHIFT (16U)
67237 /*! SUBCLASS_CODE - Sub-Class Code. Specifies a base class sub-class, which identifies more
67238  *    specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and
67239  *    ID Assignment Specification. All unspecified encodings are reserved. Note: The access
67240  *    attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
67241  *    Note: This register field is sticky.
67242  */
67243 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MASK)
67244 
67245 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MASK (0xFF000000U)
67246 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SHIFT (24U)
67247 /*! BASE_CLASS_CODE - Base Class Code. A code that broadly classifies the type of operation the
67248  *    Function performs. Encodings for base class, are provided in the PCI Code and ID Assignment
67249  *    Specification. All unspecified encodings are reserved. Note: The access attributes of this field are
67250  *    as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register
67251  *    field is sticky.
67252  */
67253 #define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MASK)
67254 /*! @} */
67255 
67256 /*! @name TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG - Header Type, Latency Timer, and Cache Line Size Register. */
67257 /*! @{ */
67258 
67259 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK (0xFFU)
67260 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT (0U)
67261 /*! CACHE_LINE_SIZE - Cache Line Size. The Cache Line Size register is programmed by the system
67262  *    firmware or the operating system to system cache line size. However, legacy conventional PCI
67263  *    software may not always be able to program this register correctly especially in the case of
67264  *    Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has
67265  *    no effect on any PCI Express device behavior.
67266  */
67267 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK)
67268 
67269 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK (0xFF00U)
67270 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT (8U)
67271 /*! LATENCY_MASTER_TIMER - Latency Timer. This register is also referred to as Primary Latency
67272  *    Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the
67273  *    PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The
67274  *    controller hardwires this register to 00h.
67275  */
67276 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK)
67277 
67278 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK (0x7F0000U)
67279 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT (16U)
67280 /*! HEADER_TYPE - Header Layout. This field identifies the layout of the second part of the
67281  *    predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This
67282  *    encoding was originally described in the PC Card Standard Electrical Specification and is used
67283  *    in previous versions of the programming model. Careful consideration should be given to any
67284  *    attempt to repurpose it.
67285  */
67286 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK)
67287 
67288 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK (0x800000U)
67289 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT (23U)
67290 /*! MULTI_FUNC - Multi-Function Device. - When set, indicates that the device may contain multiple
67291  *    Functions, but not necessarily. Software is permitted to probe for Functions other than
67292  *    Function 0. - When clear, software must not probe for Functions other than Function 0 unless
67293  *    explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure. Except where
67294  *    stated otherwise, it is recommended that this bit be set if there are multiple Functions, and
67295  *    clear if there is only one Function. Note: This register field is sticky.
67296  */
67297 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK)
67298 
67299 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MASK (0xFF000000U)
67300 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SHIFT (24U)
67301 /*! BIST - BIST. This register is used for control and status of BIST. Functions that do not support
67302  *    BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent
67303  *    normal operation of the PCI Express Link. Bit descriptions: - [31]: BIST Capable. When set, this
67304  *    bit indicates that the Function supports BIST. When Clear, the Function does not support BIST.
67305  *    - [30]: Start BIST. If BIST Capable is set, set this bit to invoke BIST. The Function resets
67306  *    the bit when BIST is complete. Software is permitted to fail the device if this bit is not
67307  *    Clear (BIST is not complete) 2 seconds after it had been set. Writing this bit to 0b has no
67308  *    effect. The controller hardwires this bit to 0b if BIST Capable is clear. - [29:28]: Reserved. -
67309  *    [27:24]: Completion Code. This field encodes the status of the most recent test. A value of
67310  *    0000b means that the Function has passed its test. Non-zero values mean the Function failed.
67311  *    Function-specific failure codes can be encoded in the non-zero values. This field's value is only
67312  *    meaningful when BIST Capable is set and Start BIST is Clear. This field must be hardwired to
67313  *    0000b if BIST Capable is clear.
67314  */
67315 #define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MASK)
67316 /*! @} */
67317 
67318 /*! @name SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG - Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register. */
67319 /*! @{ */
67320 
67321 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MASK (0xFFU)
67322 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SHIFT (0U)
67323 /*! PRIM_BUS - Primary Bus Number. This register is not used by PCI Express Functions. It is
67324  *    implemented for compatibility with legacy software.
67325  */
67326 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MASK)
67327 
67328 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MASK (0xFF00U)
67329 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SHIFT (8U)
67330 /*! SEC_BUS - Secondary Bus Number. The Secondary Bus Number register is used to record the bus
67331  *    number of the PCI bus segment to which the secondary interface of the bridge is connected.
67332  *    Configuration software programs the value in this register. The bridge uses this register to
67333  *    determine when to respond to and convert a Type 1 configuration transaction on the primary interface
67334  *    into a Type 0 transaction on the secondary interface.
67335  */
67336 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MASK)
67337 
67338 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MASK (0xFF0000U)
67339 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SHIFT (16U)
67340 /*! SUB_BUS - Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus
67341  *    number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
67342  *    Configuration software programs the value in this register. The bridge uses this register in
67343  *    conjunction with the Secondary Bus Number register to determine when to respond to and pass on
67344  *    a Type 1 configuration transaction on the primary interface to the secondary interface.
67345  */
67346 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MASK)
67347 
67348 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MASK (0xFF000000U)
67349 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SHIFT (24U)
67350 /*! SEC_LAT_TIMER - Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h. */
67351 #define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MASK)
67352 /*! @} */
67353 
67354 /*! @name SEC_STAT_IO_LIMIT_IO_BASE_REG - Secondary Status, and I/O Limit and Base Register. */
67355 /*! @{ */
67356 
67357 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MASK (0x1U)
67358 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SHIFT (0U)
67359 /*! IO_DECODE - I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing
67360  *    capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O
67361  *    addressing (for ISA compatibility). For the purpose of address decoding, the bridge assumes
67362  *    that the upper 16 address bits, Address[31:16], of the I/O base address (not implemented in I/O
67363  *    base register) are zero. Note: The bridge must still perform a full 32-bit decode of the I/O
67364  *    address (that is, check that Address[31:16] are 0000h). In this case, the I/O address range
67365  *    supported by the bridge will be restricted to the first 64 KB of I/O Space (0000 0000h to 0000
67366  *    FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Base Upper 16 Bits
67367  *    hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Base address. In this
67368  *    case, system configuration software is permitted to locate the I/O address range supported by
67369  *    the bridge anywhere in the 4-GB I/O Space. Note: The 4-KB alignment and granularity restrictions
67370  *    still apply when the bridge supports 32-bit I/O addressing. Note: The access attributes of
67371  *    this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
67372  */
67373 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MASK)
67374 
67375 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MASK (0xEU)
67376 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SHIFT (1U)
67377 /*! IO_RESERV - Reserved. */
67378 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MASK)
67379 
67380 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MASK (0xF0U)
67381 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SHIFT (4U)
67382 /*! IO_BASE - I/O Base Address. These bits correspond to the address[15:12] of IO address range. For
67383  *    the purpose of address decoding, the bridge assumes that the lower 12 address bits,
67384  *    address[11:0], of the I/O base address (not implemented in the I/O Base register) are zero.
67385  */
67386 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MASK)
67387 
67388 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MASK (0x100U)
67389 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SHIFT (8U)
67390 /*! IO_DECODE_BIT8 - I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing
67391  *    capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only
67392  *    16-bit I/O addressing (for ISA compatibility). For the purpose of address decoding, the
67393  *    bridge assumes that the upper 16 address bits, Address[31:16], of the I/O limit address (not
67394  *    implemented in I/O Limit register) are zero. Note: The bridge must still perform a full 32-bit
67395  *    decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the I/O
67396  *    address range supported by the bridge will be restricted to the first 64 KB of I/O Space (0000
67397  *    0000h to 0000 FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Limit
67398  *    Upper 16 Bits hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Limit
67399  *    address. In this case, system configuration software is permitted to locate the I/O address range
67400  *    supported by the bridge anywhere in the 4-GB I/O Space. Note: The 4-KB alignment and
67401  *    granularity restrictions still apply when the bridge supports 32-bit I/O addressing. Note: The access
67402  *    attributes of this field are as follows: - Dbi: R
67403  */
67404 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MASK)
67405 
67406 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MASK (0xE00U)
67407 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SHIFT (9U)
67408 /*! IO_RESERV1 - Reserved. */
67409 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MASK)
67410 
67411 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MASK (0xF000U)
67412 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SHIFT (12U)
67413 /*! IO_LIMIT - I/O Limit Address. These bits correspond to the address[15:12] of IO address range.
67414  *    For the purpose of address decoding, the bridge assumes that the lower 12 address bits,
67415  *    address[11:0], of the I/O limit address (not implemented in the I/O Limit register) are FFFh. The I/O
67416  *    Limit register can be programmed to a smaller value than the I/O Base register, if there are
67417  *    no I/O addresses on the secondary side of the bridge. In this case, the bridge will not
67418  *    forward any I/O transactions from the primary bus to the secondary and will forward all I/O
67419  *    transactions from the secondary bus to the primary bus.
67420  */
67421 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MASK)
67422 
67423 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MASK (0x7F0000U)
67424 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SHIFT (16U)
67425 /*! SEC_STAT_RESERV - Reserved. */
67426 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MASK)
67427 
67428 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_MASK (0x800000U)
67429 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_SHIFT (23U)
67430 /*! RSVDP_23 - Reserved for future use. */
67431 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_MASK)
67432 
67433 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MASK (0x1000000U)
67434 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SHIFT (24U)
67435 /*! SEC_STAT_MDPE - Master Data Parity Error. This bit is set by a Function if the Parity Error
67436  *    Response Enable bit in the Bridge Control register is set, and either of the following two
67437  *    conditions occurs: - Port receives a Poisoned Completion coming Upstream - Port transmits a Poisoned
67438  *    Request Downstream If the Parity Error Response Enable bit is clear, this bit is never set.
67439  */
67440 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MASK)
67441 
67442 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_MASK (0x6000000U)
67443 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_SHIFT (25U)
67444 /*! RSVDP_25 - Reserved for future use. */
67445 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_MASK)
67446 
67447 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MASK (0x8000000U)
67448 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SHIFT (27U)
67449 /*! SEC_STAT_SIG_TRGT_ABRT - Signaled Target Abort. This bit is set when the secondary side of the
67450  *    Function (for Requests completed by the Type 1 header Function itself) completes a Posted or
67451  *    Non-Posted request as a Completer Abort error.
67452  */
67453 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MASK)
67454 
67455 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MASK (0x10000000U)
67456 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SHIFT (28U)
67457 /*! SEC_STAT_RCVD_TRGT_ABRT - Received Target Abort. This bit is set when the secondary side of a
67458  *    Function (for requests initiated by the Type 1 header Function itself) receives a Completion
67459  *    with Completer Abort Completion status.
67460  */
67461 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MASK)
67462 
67463 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MASK (0x20000000U)
67464 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SHIFT (29U)
67465 /*! SEC_STAT_RCVD_MSTR_ABRT - Received Master Abort. This bit is set when the secondary side of a
67466  *    Function (for requests initiated by the Type 1 header Function itself) receives a Completion
67467  *    with Unsupported Request Completion status.
67468  */
67469 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MASK)
67470 
67471 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MASK (0x40000000U)
67472 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SHIFT (30U)
67473 /*! SEC_STAT_RCVD_SYS_ERR - Received System Error. This bit is set when the secondary side of a
67474  *    Function receives an ERR_FATAL or ERR_NONFATAL message.
67475  */
67476 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MASK)
67477 
67478 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MASK (0x80000000U)
67479 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SHIFT (31U)
67480 /*! SEC_STAT_DPE - Detected Parity Error. This bit is set by a Function when a Poisoned TLP is
67481  *    received by its secondary side, regardless of the state the Parity Error Response Enable bit in the
67482  *    Bridge Control register.
67483  */
67484 #define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MASK)
67485 /*! @} */
67486 
67487 /*! @name MEM_LIMIT_MEM_BASE_REG - Memory Limit and Base Register. */
67488 /*! @{ */
67489 
67490 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MASK (0xFU)
67491 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SHIFT (0U)
67492 /*! MEM_BASE_RESERV - Reserved. */
67493 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MASK)
67494 
67495 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MASK (0xFFF0U)
67496 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SHIFT (4U)
67497 /*! MEM_BASE - Memory Base Address. These bits correspond to the upper 12 address bits,
67498  *    Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the
67499  *    lower 20 address bits, Address[19:0], of the memory base address (not implemented in the Memory
67500  *    Base register) are zero.
67501  */
67502 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MASK)
67503 
67504 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MASK (0xF0000U)
67505 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SHIFT (16U)
67506 /*! MEM_LIMIT_RESERV - Reserved. */
67507 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MASK)
67508 
67509 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MASK (0xFFF00000U)
67510 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SHIFT (20U)
67511 /*! MEM_LIMIT - Memory Limit Address. These bits correspond to the upper 12 address bits,
67512  *    Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the
67513  *    lower 20 address bits, Address[19:0], of the memory limit address (not implemented in the Memory
67514  *    Limit register) are F FFFFh. The Memory Limit register must be programmed to a smaller value
67515  *    than the Memory Base register if there is no memory-mapped address space on the secondary side
67516  *    of the bridge.
67517  */
67518 #define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MASK)
67519 /*! @} */
67520 
67521 /*! @name PREF_MEM_LIMIT_PREF_MEM_BASE_REG - Prefetchable Memory Limit and Base Register. */
67522 /*! @{ */
67523 
67524 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MASK (0x1U)
67525 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SHIFT (0U)
67526 /*! PREF_MEM_DECODE - Prefetchable Memory Base Decode. This bit encodes whether or not the bridge
67527  *    supports 64-bit addresses. The value of PREF_MEM_DECODE indicates the following: - 0b: Indicates
67528  *    that the bridge supports only 32 bit addresses. - 1b: Indicates that the bridge supports 64
67529  *    bit addresses. Prefetchable Base Upper 32 Bits registers holds the rest of the 64-bit
67530  *    prefetchable base address. Note: The access attributes of this field are as follows: - Dbi: if
67531  *    (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67532  */
67533 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MASK)
67534 
67535 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MASK (0xEU)
67536 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SHIFT (1U)
67537 /*! PREF_RESERV - Reserved. */
67538 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MASK)
67539 
67540 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MASK (0xFFF0U)
67541 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SHIFT (4U)
67542 /*! PREF_MEM_BASE - Prefetchable Memory Base Address. If the Prefetchable Memory Base register
67543  *    indicates support for 32-bit addressing, then the Prefetchable Base Upper 32 Bits register is
67544  *    implemented as a read-only register that returns zero when read. If the Prefetchable Memory Base
67545  *    register indicates support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits
67546  *    register is implemented as a read/write register which must be initialized by configuration
67547  *    software. If a 64-bit prefetchable memory address range is supported, the Prefetchable Base Upper 32
67548  *    Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit
67549  *    base addresses which specify the prefetchable memory address range.
67550  */
67551 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MASK)
67552 
67553 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MASK (0x10000U)
67554 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SHIFT (16U)
67555 /*! PREF_MEM_LIMIT_DECODE - Prefetchable Memory Limit Decode. This bit encodes whether or not the
67556  *    bridge supports 64-bit addresses. The value of PREF_MEM_LIMIT_DECODE indicates the following: -
67557  *    0b: Indicates that the bridge supports only 32 bit addresses - 1b: Indicates that the bridge
67558  *    supports 64 bit addresses. Prefetchable Limit Upper 32 Bits registers holds the rest of the
67559  *    64-bit prefetchable limit address.
67560  */
67561 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MASK)
67562 
67563 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MASK (0xE0000U)
67564 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SHIFT (17U)
67565 /*! PREF_RESERV1 - Reserved. */
67566 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MASK)
67567 
67568 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MASK (0xFFF00000U)
67569 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SHIFT (20U)
67570 /*! PREF_MEM_LIMIT - Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register
67571  *    indicates support for 32-bit addressing, then the Prefetchable Limit Upper 32 Bits register is
67572  *    implemented as a read-only register that returns zero when read. If the Prefetchable Memory
67573  *    Limit registers indicate support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits
67574  *    register is implemented as a read/write register which must be initialized by configuration
67575  *    software. If a 64-bit prefetchable memory address range is supported, the Prefetchable Limit
67576  *    Upper 32 Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the
67577  *    64-bit limit addresses which specify the prefetchable memory address range.
67578  */
67579 #define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MASK)
67580 /*! @} */
67581 
67582 /*! @name PREF_BASE_UPPER_REG - Prefetchable Base Upper 32 Bits Register. */
67583 /*! @{ */
67584 
67585 #define PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MASK (0xFFFFFFFFU)
67586 #define PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SHIFT (0U)
67587 /*! PREF_MEM_BASE_UPPER - Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register
67588  *    indicates support for 32-bit addressing, then this register is implemented as read-only
67589  *    register that returns zero when read. If the Prefetchable Memory Base register indicate support for
67590  *    64-bit addressing, then this register is implemented as read/write register which must be
67591  *    initialized by configuration software. This register specifies the upper 32 bits, corresponding to
67592  *    Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address
67593  *    range. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1)
67594  *    then R/W else R
67595  */
67596 #define PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SHIFT)) & PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MASK)
67597 /*! @} */
67598 
67599 /*! @name PREF_LIMIT_UPPER_REG - Prefetchable Limit Upper 32 Bits Register. */
67600 /*! @{ */
67601 
67602 #define PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MASK (0xFFFFFFFFU)
67603 #define PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SHIFT (0U)
67604 /*! PREF_MEM_LIMIT_UPPER - Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit
67605  *    register indicate support for 64-bit addressing, then this register is implemented as read/write
67606  *    register which must be initialized by configuration software. This register specifies the upper 32
67607  *    bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the
67608  *    prefetchable memory address range. Note: The access attributes of this field are as follows: - Dbi:
67609  *    if (DBI_RO_WR_EN == 1) then R/W else R
67610  */
67611 #define PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SHIFT)) & PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MASK)
67612 /*! @} */
67613 
67614 /*! @name IO_LIMIT_UPPER_IO_BASE_UPPER_REG - I/O Limit and Base Upper 16 Bits Register. */
67615 /*! @{ */
67616 
67617 #define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MASK (0xFFFFU)
67618 #define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SHIFT (0U)
67619 /*! IO_BASE_UPPER - I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit
67620  *    I/O address decoding, then this register is implemented as a read-only register which return
67621  *    zero when read. If the I/O base register indicates support for 32-bit I/O addressing, then this
67622  *    register must be initialized by configuration software. If 32-bit I/O address decoding is
67623  *    supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the
67624  *    32-bit base address, that specify the I/O address range. See the PCI-to-PCI Bridge Architecture
67625  *    Specification for additional details. Note: The access attributes of this field are as follows: -
67626  *    Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
67627  */
67628 #define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SHIFT)) & PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MASK)
67629 
67630 #define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MASK (0xFFFF0000U)
67631 #define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SHIFT (16U)
67632 /*! IO_LIMIT_UPPER - I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit
67633  *    I/O address decoding, then this register is implemented as a read-only register which return
67634  *    zero when read. If the I/O Limit register indicates support for 32-bit I/O addressing, then
67635  *    this register must be initialized by configuration software. If 32-bit I/O address decoding is
67636  *    supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the
67637  *    32-bit limit address, that specify the I/O address range. See the PCI-to-PCI Bridge
67638  *    Architecture Specification for additional details). Note: The access attributes of this field are as
67639  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
67640  */
67641 #define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SHIFT)) & PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MASK)
67642 /*! @} */
67643 
67644 /*! @name TYPE1_CAP_PTR_REG - Capabilities Pointer Register. */
67645 /*! @{ */
67646 
67647 #define PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_MASK  (0xFFU)
67648 #define PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_SHIFT (0U)
67649 /*! CAP_POINTER - Capabilities Pointer. This register is used to point to a linked list of
67650  *    capabilities implemented by this Function. Since all PCI Express Functions are required to implement
67651  *    the PCI Express Capability structure, this register must point to a valid capability structure
67652  *    and either this structure is the PCI Express Capability structure, or a subsequent list item
67653  *    points to the PCI Express Capability structure. The bottom two bits are Reserved and must be set
67654  *    to 00b. Software must mask these bits off before using this register as a pointer in
67655  *    Configuration Space to the first entry of a linked list of new capabilities. Note: The access
67656  *    attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
67657  *    Note: This register field is sticky.
67658  */
67659 #define PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_SHIFT)) & PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_MASK)
67660 
67661 #define PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_MASK      (0xFFFFFF00U)
67662 #define PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_SHIFT     (8U)
67663 /*! RSVDP_8 - Reserved for future use. */
67664 #define PCIE_TYPE1_CAP_PTR_REG_RSVDP_8(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_SHIFT)) & PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_MASK)
67665 /*! @} */
67666 
67667 /*! @name TYPE1_EXP_ROM_BASE_REG - Expansion ROM Base Address Register. */
67668 /*! @{ */
67669 
67670 #define PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MASK (0x1U)
67671 #define PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SHIFT (0U)
67672 /*! ROM_BAR_ENABLE - Expansion ROM Enable. This bit controls whether or not the Function accepts
67673  *    accesses to its expansion ROM. When this bit is 0b, the Function's expansion ROM address space is
67674  *    disabled. When the bit is 1b, address decoding is enabled using the parameters in the other
67675  *    part of the Expansion ROM Base Address register. The Memory Space Enable bit in the Command
67676  *    register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its
67677  *    expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are
67678  *    set. Note: The access attributes of this field are as follows: - Dbi: R/W
67679  */
67680 #define PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SHIFT)) & PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MASK)
67681 
67682 #define PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_MASK (0x7FEU)
67683 #define PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_SHIFT (1U)
67684 /*! RSVDP_1 - Reserved for future use. */
67685 #define PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_SHIFT)) & PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_MASK)
67686 
67687 #define PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MASK (0xFFFFF800U)
67688 #define PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SHIFT (11U)
67689 /*! EXP_ROM_BASE_ADDRESS - Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base
67690  *    address. The number of bits (out of these 21) that a Function actually implements depends on how
67691  *    much address space the Function requires. The mask for this ROM BAR exists (if implemented) as a
67692  *    shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or
67693  *    the CS2 address bit for the AXI bridge) is required to write to the second register at this
67694  *    address. Note: The access attributes of this field are as follows: - Dbi: R/W
67695  */
67696 #define PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SHIFT)) & PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MASK)
67697 /*! @} */
67698 
67699 /*! @name BRIDGE_CTRL_INT_PIN_INT_LINE_REG - Bridge Control, Interrupt Pin, and Interrupt Line Register. */
67700 /*! @{ */
67701 
67702 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MASK (0xFFU)
67703 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SHIFT (0U)
67704 /*! INT_LINE - Interrupt Line. The Interrupt Line register communicates interrupt line routing
67705  *    information. The register must be implemented by any Function that uses an interrupt pin. Values in
67706  *    this register are programmed by system software and are system architecture specific. The
67707  *    Function itself does not use this value; rather the value in this register is used by device
67708  *    drivers and operating systems.
67709  */
67710 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MASK)
67711 
67712 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MASK (0xFF00U)
67713 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SHIFT (8U)
67714 /*! INT_PIN - Interrupt PIN. The Interrupt Pin register register that identifies the legacy
67715  *    interrupt Message(s) the Function uses. Valid values are: - 01h, 02h, 03h, and 04h: map to legacy
67716  *    interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: indicates that the Function
67717  *    uses no legacy interrupt Message(s). - 05h through FFh: Reserved. PCI Express defines one
67718  *    legacy interrupt Message for a single Function device and up to four legacy interrupt Messages
67719  *    for a multi-Function device. For a single Function device, only INTA may be used. Any Function
67720  *    on a multi-Function device can use any of the INTx Messages. If a device implements a single
67721  *    legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they
67722  *    must be INTA and INTB; and so forth. For a multi-Function device, all Functions may use the
67723  *    same INTx Message or each may have its own (up to a maximum of four Functions) or any
67724  *    combination thereof. A single Function can never generate an interrupt request on more than one INTx
67725  *    Message. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1)
67726  *    then R/W else R Note: This register field is sticky.
67727  */
67728 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MASK)
67729 
67730 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MASK (0x10000U)
67731 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SHIFT (16U)
67732 /*! PERE - Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the
67733  *    Master Data Parity Error bit in the Secondary Status register.
67734  */
67735 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MASK)
67736 
67737 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MASK (0x20000U)
67738 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SHIFT (17U)
67739 /*! SERR_EN - SERR# Enable. This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL from secondary to primary. */
67740 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MASK)
67741 
67742 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MASK (0x40000U)
67743 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SHIFT (18U)
67744 /*! ISA_EN - ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only
67745  *    to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the
67746  *    first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge will
67747  *    block any forwarding from primary to secondary of I/O transactions addressing the last 768
67748  *    bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions will
67749  *    be forwarded if they address the last 768 bytes in each 1-KB block. The following actions are
67750  *    taken based on the value of the ISA_EN bit: - 0b: Forward downstream all I/O addresses in the
67751  *    address range defined by the I/O Base and I/O Limit registers - 1b: Forward upstream ISA I/O
67752  *    addresses in the address range defined by the I/O Base and I/O Limit registers that are in the
67753  *    first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block.
67754  */
67755 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MASK)
67756 
67757 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MASK (0x80000U)
67758 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SHIFT (19U)
67759 /*! VGA_EN - VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA
67760  *    Enable bit is set, the bridge will positively decode and forward the following accesses on
67761  *    the primary interface to the secondary interface (and, conversely, block the forwarding of these
67762  *    addresses from the secondary to primary interface): - Memory accesses in the range 000A 0000h
67763  *    to 000B FFFFh - I/O addresses in the first 64 KB of the I/O address space (Address[31:16] are
67764  *    0000h) where Address[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA
67765  *    address aliases determined by the setting of VGA 16-bit Decode ) If the VGA Enable bit is set,
67766  *    forwarding of these accesses is independent of the I/O address range and memory address ranges
67767  *    defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the
67768  *    Prefetchable Memory Base and Limit registers of the bridge. (Forwarding of these accesses is also
67769  *    independent of the setting of the ISA Enable bit (in the Bridge Control register) when the
67770  *    VGA Enable bit is set. Forwarding of these accesses is qualified by the I/O Space Enable and
67771  *    Memory Space Enable bits in the Command register.) The following actions are taken based on the
67772  *    value of the VGA_EN bit: - 0b: Do not forward VGA compatible memory and I/O addresses from the
67773  *    primary to the secondary interface (addresses defined above) unless they are enabled for
67774  *    forwarding by the defined I/O and memory address ranges - 1b: Forward VGA compatible memory and I/O
67775  *    addresses (addresses defined above) from the primary interface to the secondary interface (if
67776  *    the I/O Space Enable and Memory Space Enable bits are set) independent of the I/O and memory
67777  *    address ranges and independent of the ISA Enable bit For Functions that do not support VGA,
67778  *    the controller hardwires this bit to 0b. Note: The access attributes of this field are as
67779  *    follows: - Dbi: R
67780  */
67781 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MASK)
67782 
67783 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MASK (0x100000U)
67784 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SHIFT (20U)
67785 /*! VGA_16B_DEC - VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit
67786  *    enables system configuration software to select between 10-bit and 16-bit I/O address decoding
67787  *    for all VGA I/O register accesses that are forwarded from primary to secondary. The following
67788  *    actions are taken based on the value of the VGA_16B_DEC bit: - 0b: Execute 10-bit address
67789  *    decodes on VGA I/O accesses - 1b: Execute 16-bit address decodes on VGA I/O accesses For Functions
67790  *    that do not support VGA, the controller hardwires this bit to 0b. Note: The access attributes
67791  *    of this field are as follows: - Dbi: R
67792  */
67793 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MASK)
67794 
67795 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MASK (0x200000U)
67796 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SHIFT (21U)
67797 /*! MSTR_ABORT_MODE - Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge
67798  *    Architecture Specification. Its functionality does not apply to PCI Express. The controller
67799  *    hardwires this bit to 0b. Note: The access attributes of this field are as follows: - Dbi: R/W
67800  */
67801 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MASK)
67802 
67803 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MASK (0x400000U)
67804 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SHIFT (22U)
67805 /*! SBR - Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI
67806  *    Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus
67807  *    Specification. Software and systems must honor first-access-following-reset timing
67808  *    requirements, unless the Readiness Notifications mechanism is used or if the Immediate Readiness bit in
67809  *    the relevant Function's Status Register register is set. Port configuration registers must not
67810  *    be changed, except as required to update Port status.
67811  */
67812 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MASK)
67813 
67814 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MASK (0xFF800000U)
67815 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SHIFT (23U)
67816 /*! BRIDGE_CTRL_RESERV - Reserved. */
67817 #define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MASK)
67818 /*! @} */
67819 
67820 /*! @name CAP_ID_NXT_PTR_REG - Power Management Capabilities Register. */
67821 /*! @{ */
67822 
67823 #define PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK   (0xFFU)
67824 #define PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT  (0U)
67825 /*! PM_CAP_ID - Power Management Capability ID. For a description of this standard PCIe register
67826  *    field, see the PCI Express Specification.
67827  */
67828 #define PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK)
67829 
67830 #define PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK (0xFF00U)
67831 #define PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT (8U)
67832 /*! PM_NEXT_POINTER - Next Capability Pointer. For a description of this standard PCIe register
67833  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
67834  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67835  */
67836 #define PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK)
67837 
67838 #define PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK (0x70000U)
67839 #define PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT (16U)
67840 /*! PM_SPEC_VER - Power Management Spec Version. For a description of this standard PCIe register
67841  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
67842  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67843  */
67844 #define PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK)
67845 
67846 #define PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_MASK     (0x80000U)
67847 #define PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT    (19U)
67848 /*! PME_CLK - PCI Clock Requirement. For a description of this standard PCIe register field, see the
67849  *    PCI Express Specification. Note: This register field is sticky.
67850  */
67851 #define PCIE_CAP_ID_NXT_PTR_REG_PME_CLK(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_MASK)
67852 
67853 #define PCIE_CAP_ID_NXT_PTR_REG_DSI_MASK         (0x200000U)
67854 #define PCIE_CAP_ID_NXT_PTR_REG_DSI_SHIFT        (21U)
67855 /*! DSI - Device Specific Initialization Bit. For a description of this standard PCIe register
67856  *    field, see the PCI Express Specification. Note: The access attributes of this field are as follows:
67857  *    - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67858  */
67859 #define PCIE_CAP_ID_NXT_PTR_REG_DSI(x)           (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_DSI_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_DSI_MASK)
67860 
67861 #define PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK    (0x1C00000U)
67862 #define PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT   (22U)
67863 /*! AUX_CURR - Auxiliary Current Requirements. For a description of this standard PCIe register
67864  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
67865  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67866  */
67867 #define PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK)
67868 
67869 #define PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK  (0x2000000U)
67870 #define PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT (25U)
67871 /*! D1_SUPPORT - D1 State Support. For a description of this standard PCIe register field, see the
67872  *    PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi: if
67873  *    (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67874  */
67875 #define PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK)
67876 
67877 #define PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK  (0x4000000U)
67878 #define PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT (26U)
67879 /*! D2_SUPPORT - D2 State Support. For a description of this standard PCIe register field, see the
67880  *    PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi: if
67881  *    (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67882  */
67883 #define PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK)
67884 
67885 #define PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK (0xF8000000U)
67886 #define PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT (27U)
67887 /*! PME_SUPPORT - Power Management Event Support. For a description of this standard PCIe register
67888  *    field, see the PCI Express Specification. The read value from this field is the write value &&
67889  *    (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are
67890  *    fields in this register. The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT,
67891  *    D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter. Note: The access attributes
67892  *    of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This
67893  *    register field is sticky.
67894  */
67895 #define PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK)
67896 /*! @} */
67897 
67898 /*! @name CON_STATUS_REG - Power Management Control and Status Register. */
67899 /*! @{ */
67900 
67901 #define PCIE_CON_STATUS_REG_POWER_STATE_MASK     (0x3U)
67902 #define PCIE_CON_STATUS_REG_POWER_STATE_SHIFT    (0U)
67903 /*! POWER_STATE - Power State. For a description of this standard PCIe register field, see the PCI
67904  *    Express Specification. You can write to this register. However, the read-back value is the
67905  *    actual power state, not the write value. Note: The access attributes of this field are as follows:
67906  *    - Dbi: R/W
67907  */
67908 #define PCIE_CON_STATUS_REG_POWER_STATE(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_POWER_STATE_SHIFT)) & PCIE_CON_STATUS_REG_POWER_STATE_MASK)
67909 
67910 #define PCIE_CON_STATUS_REG_RSVDP_2_MASK         (0x4U)
67911 #define PCIE_CON_STATUS_REG_RSVDP_2_SHIFT        (2U)
67912 /*! RSVDP_2 - Reserved for future use. */
67913 #define PCIE_CON_STATUS_REG_RSVDP_2(x)           (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_RSVDP_2_SHIFT)) & PCIE_CON_STATUS_REG_RSVDP_2_MASK)
67914 
67915 #define PCIE_CON_STATUS_REG_NO_SOFT_RST_MASK     (0x8U)
67916 #define PCIE_CON_STATUS_REG_NO_SOFT_RST_SHIFT    (3U)
67917 /*! NO_SOFT_RST - No soft Reset. For a description of this standard PCIe register field, see the PCI
67918  *    Express Specification. Note: The access attributes of this field are as follows: - Dbi: if
67919  *    (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
67920  */
67921 #define PCIE_CON_STATUS_REG_NO_SOFT_RST(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_NO_SOFT_RST_SHIFT)) & PCIE_CON_STATUS_REG_NO_SOFT_RST_MASK)
67922 
67923 #define PCIE_CON_STATUS_REG_RSVDP_4_MASK         (0xF0U)
67924 #define PCIE_CON_STATUS_REG_RSVDP_4_SHIFT        (4U)
67925 /*! RSVDP_4 - Reserved for future use. */
67926 #define PCIE_CON_STATUS_REG_RSVDP_4(x)           (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_RSVDP_4_SHIFT)) & PCIE_CON_STATUS_REG_RSVDP_4_MASK)
67927 
67928 #define PCIE_CON_STATUS_REG_PME_ENABLE_MASK      (0x100U)
67929 #define PCIE_CON_STATUS_REG_PME_ENABLE_SHIFT     (8U)
67930 /*! PME_ENABLE - PME Enable. For a description of this standard PCIe register field, see the PCI
67931  *    Express Specification. The PMC registers this value under aux power. Sometimes it might remember
67932  *    the old value, even if you try to clear it by writing '0'. Note: This register field is sticky.
67933  */
67934 #define PCIE_CON_STATUS_REG_PME_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_PME_ENABLE_SHIFT)) & PCIE_CON_STATUS_REG_PME_ENABLE_MASK)
67935 
67936 #define PCIE_CON_STATUS_REG_DATA_SELECT_MASK     (0x1E00U)
67937 #define PCIE_CON_STATUS_REG_DATA_SELECT_SHIFT    (9U)
67938 /*! DATA_SELECT - Data Select. For a description of this standard PCIe register field, see the PCI Express Specification. */
67939 #define PCIE_CON_STATUS_REG_DATA_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_DATA_SELECT_SHIFT)) & PCIE_CON_STATUS_REG_DATA_SELECT_MASK)
67940 
67941 #define PCIE_CON_STATUS_REG_DATA_SCALE_MASK      (0x6000U)
67942 #define PCIE_CON_STATUS_REG_DATA_SCALE_SHIFT     (13U)
67943 /*! DATA_SCALE - Data Scaling Factor. For a description of this standard PCIe register field, see the PCI Express Specification. */
67944 #define PCIE_CON_STATUS_REG_DATA_SCALE(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_DATA_SCALE_SHIFT)) & PCIE_CON_STATUS_REG_DATA_SCALE_MASK)
67945 
67946 #define PCIE_CON_STATUS_REG_PME_STATUS_MASK      (0x8000U)
67947 #define PCIE_CON_STATUS_REG_PME_STATUS_SHIFT     (15U)
67948 /*! PME_STATUS - PME Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
67949 #define PCIE_CON_STATUS_REG_PME_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_PME_STATUS_SHIFT)) & PCIE_CON_STATUS_REG_PME_STATUS_MASK)
67950 
67951 #define PCIE_CON_STATUS_REG_RSVDP_16_MASK        (0x3F0000U)
67952 #define PCIE_CON_STATUS_REG_RSVDP_16_SHIFT       (16U)
67953 /*! RSVDP_16 - Reserved for future use. */
67954 #define PCIE_CON_STATUS_REG_RSVDP_16(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_RSVDP_16_SHIFT)) & PCIE_CON_STATUS_REG_RSVDP_16_MASK)
67955 
67956 #define PCIE_CON_STATUS_REG_B2_B3_SUPPORT_MASK   (0x400000U)
67957 #define PCIE_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT  (22U)
67958 /*! B2_B3_SUPPORT - B2B3 Support for D3hot. For a description of this standard PCIe register field, see the PCI Express Specification. */
67959 #define PCIE_CON_STATUS_REG_B2_B3_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT)) & PCIE_CON_STATUS_REG_B2_B3_SUPPORT_MASK)
67960 
67961 #define PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK (0x800000U)
67962 #define PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT (23U)
67963 /*! BUS_PWR_CLK_CON_EN - Bus Power/Clock Control Enable. For a description of this standard PCIe
67964  *    register field, see the PCI Express Specification.
67965  */
67966 #define PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT)) & PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK)
67967 
67968 #define PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK (0xFF000000U)
67969 #define PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT (24U)
67970 /*! DATA_REG_ADD_INFO - Power Data Information Register. For a description of this standard PCIe
67971  *    register field, see the PCI Express Specification.
67972  */
67973 #define PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT)) & PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK)
67974 /*! @} */
67975 
67976 /*! @name PCI_MSI_CAP_ID_NEXT_CTRL_REG - MSI Capability ID, Next Pointer, Capability/Control Registers. */
67977 /*! @{ */
67978 
67979 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK (0xFFU)
67980 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT (0U)
67981 /*! PCI_MSI_CAP_ID - MSI Capability ID. For a description of this standard PCIe register field, see the PCI Express Specification. */
67982 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK)
67983 
67984 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK (0xFF00U)
67985 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT (8U)
67986 /*! PCI_MSI_CAP_NEXT_OFFSET - MSI Capability Next Pointer. For a description of this standard PCIe
67987  *    register field, see the PCI Express Specification. Note: The access attributes of this field
67988  *    are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
67989  *    sticky.
67990  */
67991 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK)
67992 
67993 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK (0x10000U)
67994 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT (16U)
67995 /*! PCI_MSI_ENABLE - MSI Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
67996 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK)
67997 
67998 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK (0xE0000U)
67999 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT (17U)
68000 /*! PCI_MSI_MULTIPLE_MSG_CAP - MSI Multiple Message Capable. For a description of this standard PCIe
68001  *    register field, see the PCI Express Specification. Note: The access attributes of this field
68002  *    are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
68003  *    sticky.
68004  */
68005 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK)
68006 
68007 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK (0x700000U)
68008 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT (20U)
68009 /*! PCI_MSI_MULTIPLE_MSG_EN - MSI Multiple Message Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
68010 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK)
68011 
68012 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK (0x800000U)
68013 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT (23U)
68014 /*! PCI_MSI_64_BIT_ADDR_CAP - MSI 64-bit Address Capable. For a description of this standard PCIe
68015  *    register field, see the PCI Express Specification. Note: The access attributes of this field are
68016  *    as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
68017  */
68018 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK)
68019 
68020 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK (0x1000000U)
68021 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT (24U)
68022 /*! PCI_PVM_SUPPORT - MSI Per Vector Masking Capable. For a description of this standard PCIe
68023  *    register field, see the PCI Express Specification.
68024  */
68025 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK)
68026 
68027 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK (0x2000000U)
68028 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT (25U)
68029 /*! PCI_MSI_EXT_DATA_CAP - Extended Message Data Capable. For a description of this standard PCIe
68030  *    register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express
68031  *    Specification. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN ==
68032  *    1) then R/W else R Note: This register field is sticky.
68033  */
68034 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK)
68035 
68036 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK (0x4000000U)
68037 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT (26U)
68038 /*! PCI_MSI_EXT_DATA_EN - Extended Message Data Enable. For a description of this standard PCIe
68039  *    register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express
68040  *    Specification. Note: The access attributes of this field are as follows: - Dbi:
68041  *    PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO
68042  */
68043 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK)
68044 
68045 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MASK (0xF8000000U)
68046 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SHIFT (27U)
68047 /*! RSVDP_27 - Reserved for future use. */
68048 #define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MASK)
68049 /*! @} */
68050 
68051 /*! @name MSI_CAP_OFF_04H_REG - MSI Message Lower Address Register. */
68052 /*! @{ */
68053 
68054 #define PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_MASK    (0x3U)
68055 #define PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_SHIFT   (0U)
68056 /*! RSVDP_0 - Reserved for future use. */
68057 #define PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_SHIFT)) & PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_MASK)
68058 
68059 #define PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK (0xFFFFFFFCU)
68060 #define PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT (2U)
68061 /*! PCI_MSI_CAP_OFF_04H - MSI Message Lower Address Field. For a description of this standard PCIe
68062  *    register field, see the PCI Express Specification. Note: The access attributes of this field
68063  *    are as follows: - Dbi: R/W
68064  */
68065 #define PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT)) & PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK)
68066 /*! @} */
68067 
68068 /*! @name MSI_CAP_OFF_08H_REG - For a 32 bit MSI Message, this register contains Data. */
68069 /*! @{ */
68070 
68071 #define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK (0xFFFFU)
68072 #define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT (0U)
68073 /*! PCI_MSI_CAP_OFF_08H - For a 32-bit MSI Message, this field contains Data. For 64-bit it contains
68074  *    lower 16 bits of the Upper Address. For a description of this standard PCIe register field,
68075  *    see the PCI Express Specification. Note: The access attributes of this field are as follows: -
68076  *    Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R
68077  */
68078 #define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT)) & PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK)
68079 
68080 #define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK (0xFFFF0000U)
68081 #define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT (16U)
68082 /*! PCI_MSI_CAP_OFF_0AH - For a 32 bit MSI Message, this field contains Ext MSI Data. For 64-bit it
68083  *    contains upper 16 bits of the Upper Address. For a description of this standard PCIe register
68084  *    field, see the PCI Express Specification Note: The access attributes of this field are as
68085  *    follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R
68086  */
68087 #define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT)) & PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK)
68088 /*! @} */
68089 
68090 /*! @name MSI_CAP_OFF_0CH_REG - For a 64 bit MSI Message, this register contains Data. */
68091 /*! @{ */
68092 
68093 #define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK (0xFFFFU)
68094 #define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT (0U)
68095 /*! PCI_MSI_CAP_OFF_0CH - For a 64-bit MSI Message, this field contains Data. For 32-bit, it
68096  *    contains the lower Mask Bits if PVM is enabled. For a description of this standard PCIe register
68097  *    field, see the PCI Express Specification Note: The access attributes of this field are as follows:
68098  *    - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R
68099  */
68100 #define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT)) & PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK)
68101 
68102 #define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK (0xFFFF0000U)
68103 #define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT (16U)
68104 /*! PCI_MSI_CAP_OFF_0EH - For a 64-bit MSI Message, this field contains Data. For 32-bit, it
68105  *    contains the upper Mask Bits if PVM is enabled. For a description of this standard PCIe register
68106  *    field, see the PCI Express Specification Note: The access attributes of this field are as follows:
68107  *    - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW
68108  *    : RO
68109  */
68110 #define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT)) & PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK)
68111 /*! @} */
68112 
68113 /*! @name MSI_CAP_OFF_10H_REG - Used for MSI when Vector Masking Capable. */
68114 /*! @{ */
68115 
68116 #define PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK (0xFFFFFFFFU)
68117 #define PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT (0U)
68118 /*! PCI_MSI_CAP_OFF_10H - Used for MSI when Vector Masking Capable. For 32-bit contains Pending
68119  *    Bits. For 64-bit, contains Mask Bits. For a description of this standard PCIe register field, see
68120  *    the PCI Express Specification. Note: The access attributes of this field are as follows: -
68121  *    Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R
68122  */
68123 #define PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT)) & PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK)
68124 /*! @} */
68125 
68126 /*! @name MSI_CAP_OFF_14H_REG - Used for MSI 64 bit messaging when Vector Masking Capable. */
68127 /*! @{ */
68128 
68129 #define PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK (0xFFFFFFFFU)
68130 #define PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT (0U)
68131 /*! PCI_MSI_CAP_OFF_14H - Used for MSI 64-bit messaging when Vector Masking Capable. Contains
68132  *    Pending Bits. For a description of this standard PCIe register field, see the PCI Express
68133  *    Specification.
68134  */
68135 #define PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT)) & PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK)
68136 /*! @} */
68137 
68138 /*! @name PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG - PCI Express Capabilities, ID, Next Pointer Register. */
68139 /*! @{ */
68140 
68141 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK (0xFFU)
68142 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT (0U)
68143 /*! PCIE_CAP_ID - PCIE Capability ID. For a description of this standard PCIe register field, see the PCI Express Specification. */
68144 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK)
68145 
68146 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK (0xFF00U)
68147 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT (8U)
68148 /*! PCIE_CAP_NEXT_PTR - PCIE Next Capability Pointer. For a description of this standard PCIe
68149  *    register field, see the PCI Express Specification. Note: The access attributes of this field are as
68150  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
68151  */
68152 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK)
68153 
68154 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK (0xF0000U)
68155 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT (16U)
68156 /*! PCIE_CAP_REG - PCIE Capability Version Number. For a description of this standard PCIe register
68157  *    field, see the PCI Express Specification. Note: This register field is sticky.
68158  */
68159 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK)
68160 
68161 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK (0xF00000U)
68162 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT (20U)
68163 /*! PCIE_DEV_PORT_TYPE - PCIE Device/PortType. For a description of this standard PCIe register field, see the PCI Express Specification. */
68164 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK)
68165 
68166 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK (0x1000000U)
68167 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT (24U)
68168 /*! PCIE_SLOT_IMP - PCIe Slot Implemented Valid. For a description of this standard PCIe register
68169  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
68170  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68171  */
68172 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK)
68173 
68174 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK (0x3E000000U)
68175 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT (25U)
68176 /*! PCIE_INT_MSG_NUM - PCIE Interrupt Message Number. For a description of this standard PCIe
68177  *    register field, see the PCI Express Specification. Note: The access attributes of this field are as
68178  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
68179  */
68180 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK)
68181 
68182 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK (0x40000000U)
68183 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT (30U)
68184 /*! RSVD - Reserved. For a description of this standard PCIe register field, see the PCI Express Specification. */
68185 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK)
68186 
68187 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MASK (0x80000000U)
68188 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SHIFT (31U)
68189 /*! RSVDP_31 - Reserved for future use. */
68190 #define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MASK)
68191 /*! @} */
68192 
68193 /*! @name DEVICE_CAPABILITIES_REG - Device Capabilities Register. */
68194 /*! @{ */
68195 
68196 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK (0x7U)
68197 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT (0U)
68198 /*! PCIE_CAP_MAX_PAYLOAD_SIZE - Max Payload Size Supported. For a description of this standard PCIe
68199  *    register field, see the PCI Express Specification. Note: The access attributes of this field
68200  *    are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
68201  *    sticky.
68202  */
68203 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK)
68204 
68205 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK (0x18U)
68206 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT (3U)
68207 /*! PCIE_CAP_PHANTOM_FUNC_SUPPORT - Phantom Functions Supported. For a description of this standard
68208  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68209  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
68210  *    sticky.
68211  */
68212 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK)
68213 
68214 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK (0x20U)
68215 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT (5U)
68216 /*! PCIE_CAP_EXT_TAG_SUPP - Extended Tag Field Supported. For a description of this standard PCIe
68217  *    register field, see the PCI Express Specification. Note: The access attributes of this field are
68218  *    as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
68219  */
68220 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK)
68221 
68222 #define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_MASK (0x7FC0U)
68223 #define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_SHIFT (6U)
68224 /*! RSVDP_6 - Reserved for future use. */
68225 #define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_MASK)
68226 
68227 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK (0x8000U)
68228 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT (15U)
68229 /*! PCIE_CAP_ROLE_BASED_ERR_REPORT - Role-based Error Reporting Implemented. For a description of
68230  *    this standard PCIe register field, see the PCI Express Specification. Note: The access
68231  *    attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This
68232  *    register field is sticky.
68233  */
68234 #define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK)
68235 
68236 #define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_MASK (0xFFFF0000U)
68237 #define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_SHIFT (16U)
68238 /*! RSVDP_16 - Reserved for future use. */
68239 #define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_MASK)
68240 /*! @} */
68241 
68242 /*! @name DEVICE_CONTROL_DEVICE_STATUS - Device Control and Status Register. */
68243 /*! @{ */
68244 
68245 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK (0x1U)
68246 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT (0U)
68247 /*! PCIE_CAP_CORR_ERR_REPORT_EN - Correctable Error Reporting Enable. For a description of this
68248  *    standard PCIe register field, see the PCI Express Specification.
68249  */
68250 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK)
68251 
68252 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK (0x2U)
68253 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT (1U)
68254 /*! PCIE_CAP_NON_FATAL_ERR_REPORT_EN - Non-fatal Error Reporting Enable. For a description of this
68255  *    standard PCIe register field, see the PCI Express Specification.
68256  */
68257 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK)
68258 
68259 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK (0x4U)
68260 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT (2U)
68261 /*! PCIE_CAP_FATAL_ERR_REPORT_EN - Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
68262 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK)
68263 
68264 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK (0x8U)
68265 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT (3U)
68266 /*! PCIE_CAP_UNSUPPORT_REQ_REP_EN - Unsupported Request Reporting Enable. For a description of this
68267  *    standard PCIe register field, see the PCI Express Specification.
68268  */
68269 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK)
68270 
68271 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK (0x10U)
68272 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT (4U)
68273 /*! PCIE_CAP_EN_REL_ORDER - Enable Relaxed Ordering. For a description of this standard PCIe
68274  *    register field, see the PCI Express Specification. Note: The access attributes of this field are as
68275  *    follows: - Dbi: R/W
68276  */
68277 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK)
68278 
68279 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK (0xE0U)
68280 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT (5U)
68281 /*! PCIE_CAP_MAX_PAYLOAD_SIZE_CS - Max Payload Size. Max_Payload_Size . This field sets maximum TLP
68282  *    payload size for the Function. Permissible values that can be programmed are indicated by the
68283  *    Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities
68284  *    register (DEVICE_CAPABILITIES_REG).
68285  */
68286 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK)
68287 
68288 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK (0x100U)
68289 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT (8U)
68290 /*! PCIE_CAP_EXT_TAG_EN - Extended Tag Field Enable. For a description of this standard PCIe
68291  *    register field, see the PCI Express Specification. The write value is gated with the
68292  *    PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as
68293  *    follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
68294  */
68295 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK)
68296 
68297 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MASK (0x200U)
68298 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT (9U)
68299 /*! PCIE_CAP_PHANTOM_FUNC_EN - Phantom Functions Enable. For a description of this standard PCIe
68300  *    register field, see the PCI Express Specification. The write value is gated with the
68301  *    PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field
68302  *    are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
68303  */
68304 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MASK)
68305 
68306 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK (0x400U)
68307 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT (10U)
68308 /*! PCIE_CAP_AUX_POWER_PM_EN - Aux Power PM Enable. For a description of this standard PCIe register
68309  *    field, see the PCI Express Specification. This bit is derived by sampling the sys_aux_pwr_det
68310  *    input. Note: This register field is sticky.
68311  */
68312 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK)
68313 
68314 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK (0x800U)
68315 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT (11U)
68316 /*! PCIE_CAP_EN_NO_SNOOP - Enable No Snoop. For a description of this standard PCIe register field,
68317  *    see the PCI Express Specification. Note: The access attributes of this field are as follows: -
68318  *    Dbi: R
68319  */
68320 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK)
68321 
68322 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK (0x7000U)
68323 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT (12U)
68324 /*! PCIE_CAP_MAX_READ_REQ_SIZE - Max Read Request Size. For a description of this standard PCIe register field, see the PCI Express Specification. */
68325 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK)
68326 
68327 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK (0x8000U)
68328 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT (15U)
68329 /*! PCIE_CAP_INITIATE_FLR - Initiate Function Level Reset (for endpoints). For a description of this
68330  *    standard PCIe register field, see the PCI Express Specification.
68331  */
68332 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK)
68333 
68334 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK (0x10000U)
68335 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT (16U)
68336 /*! PCIE_CAP_CORR_ERR_DETECTED - Correctable Error Detected Status. For a description of this
68337  *    standard PCIe register field, see the PCI Express Specification.
68338  */
68339 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK)
68340 
68341 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK (0x20000U)
68342 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT (17U)
68343 /*! PCIE_CAP_NON_FATAL_ERR_DETECTED - Non-Fatal Error Detected Status. For a description of this
68344  *    standard PCIe register field, see the PCI Express Specification.
68345  */
68346 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK)
68347 
68348 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK (0x40000U)
68349 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT (18U)
68350 /*! PCIE_CAP_FATAL_ERR_DETECTED - Fatal Error Detected Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
68351 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK)
68352 
68353 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK (0x80000U)
68354 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT (19U)
68355 /*! PCIE_CAP_UNSUPPORTED_REQ_DETECTED - Unsupported Request Detected Status. For a description of
68356  *    this standard PCIe register field, see the PCI Express Specification.
68357  */
68358 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK)
68359 
68360 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK (0x100000U)
68361 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT (20U)
68362 /*! PCIE_CAP_AUX_POWER_DETECTED - Aux Power Detected Status. For a description of this standard PCIe
68363  *    register field, see the PCI Express Specification. This bit is derived by sampling the
68364  *    sys_aux_pwr_det input.
68365  */
68366 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK)
68367 
68368 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK (0x200000U)
68369 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT (21U)
68370 /*! PCIE_CAP_TRANS_PENDING - Transactions Pending Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
68371 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK)
68372 
68373 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MASK (0xFFC00000U)
68374 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SHIFT (22U)
68375 /*! RSVDP_22 - Reserved for future use. */
68376 #define PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MASK)
68377 /*! @} */
68378 
68379 /*! @name LINK_CAPABILITIES_REG - Link Capabilities Register. */
68380 /*! @{ */
68381 
68382 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK (0xFU)
68383 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT (0U)
68384 /*! PCIE_CAP_MAX_LINK_SPEED - Maximum Link Speed. For a description of this standard PCIe register
68385  *    field, see the PCI Express Specification. In M-PCIe mode, the reset and dynamic values of this
68386  *    field are calculated by the controller. Note: The access attributes of this field are as
68387  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
68388  */
68389 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK)
68390 
68391 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK (0x3F0U)
68392 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT (4U)
68393 /*! PCIE_CAP_MAX_LINK_WIDTH - Maximum Link Width. For a description of this standard PCIe register
68394  *    field, see the PCI Express Specification. In M-PCIe mode, the reset and dynamic values of this
68395  *    field are calculated by the controller. Note: The access attributes of this field are as
68396  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
68397  */
68398 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK)
68399 
68400 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK (0xC00U)
68401 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT (10U)
68402 /*! PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT - Level of ASPM (Active State Power Management) Support.
68403  *    For a description of this standard PCIe register field, see the PCI Express Specification.
68404  *    Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W
68405  *    else R Note: This register field is sticky.
68406  */
68407 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK)
68408 
68409 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK (0x7000U)
68410 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT (12U)
68411 /*! PCIE_CAP_L0S_EXIT_LATENCY - LOs Exit Latency. For a description of this standard PCIe register
68412  *    field, see the PCI Express Specification. There are two each of these register fields, this one
68413  *    and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of
68414  *    the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the
68415  *    controller and which one is accessed by a read request. Common Clock operation is supported
68416  *    (possible) in the controller when one or more of the following expressions is true: - CX_NFTS
68417  *    !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY
68418  *    !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the controller when you
68419  *    set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
68420  *    (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2
68421  *    address bit for the AXI bridge) is required to write to the shadow field at this location. Note: The
68422  *    access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68423  *    Note: This register field is sticky.
68424  */
68425 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK)
68426 
68427 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK (0x38000U)
68428 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT (15U)
68429 /*! PCIE_CAP_L1_EXIT_LATENCY - L1 Exit Latency. For a description of this standard PCIe register
68430  *    field, see the PCI Express Specification. There are two each of these register fields, this one
68431  *    and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the
68432  *    Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the
68433  *    controller and which one is accessed by a read request. Common Clock operation is supported
68434  *    (possible) in the controller when one or more of the following expressions is true: - CX_NFTS
68435  *    !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY
68436  *    !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the controller when you set
68437  *    the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
68438  *    (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address
68439  *    bit for the AXI bridge) is required to write to the shadow field at this location. Note: The
68440  *    access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68441  *    Note: This register field is sticky.
68442  */
68443 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK)
68444 
68445 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK (0x40000U)
68446 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT (18U)
68447 /*! PCIE_CAP_CLOCK_POWER_MAN - Clock Power Management. For a description of this standard PCIe
68448  *    register field, see the PCI Express Specification. Note: This register field is sticky.
68449  */
68450 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK)
68451 
68452 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK (0x80000U)
68453 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT (19U)
68454 /*! PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP - Surprise Down Error Reporting Capable. For a description of
68455  *    this standard PCIe register field, see the PCI Express Specification. Note: The access
68456  *    attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This
68457  *    register field is sticky.
68458  */
68459 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK)
68460 
68461 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK (0x100000U)
68462 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT (20U)
68463 /*! PCIE_CAP_DLL_ACTIVE_REP_CAP - Data Link Layer Link Active Reporting Capable. For a description
68464  *    of this standard PCIe register field, see the PCI Express Specification.
68465  */
68466 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK)
68467 
68468 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK (0x200000U)
68469 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT (21U)
68470 /*! PCIE_CAP_LINK_BW_NOT_CAP - Link Bandwidth Notification Capable. For a description of this
68471  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68472  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field
68473  *    is sticky.
68474  */
68475 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK)
68476 
68477 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK (0x400000U)
68478 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT (22U)
68479 /*! PCIE_CAP_ASPM_OPT_COMPLIANCE - ASPM Optionality Compliance. For a description of this standard
68480  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68481  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68482  */
68483 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK)
68484 
68485 #define PCIE_LINK_CAPABILITIES_REG_RSVDP_23_MASK (0x800000U)
68486 #define PCIE_LINK_CAPABILITIES_REG_RSVDP_23_SHIFT (23U)
68487 /*! RSVDP_23 - Reserved for future use. */
68488 #define PCIE_LINK_CAPABILITIES_REG_RSVDP_23(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_RSVDP_23_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_RSVDP_23_MASK)
68489 
68490 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK (0xFF000000U)
68491 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT (24U)
68492 /*! PCIE_CAP_PORT_NUM - Port Number. For a description of this standard PCIe register field, see the
68493  *    PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
68494  *    if (DBI_RO_WR_EN == 1) then R/W else R
68495  */
68496 #define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK)
68497 /*! @} */
68498 
68499 /*! @name LINK_CONTROL_LINK_STATUS_REG - Link Control and Status Register. */
68500 /*! @{ */
68501 
68502 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK (0x3U)
68503 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT (0U)
68504 /*! PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL - Active State Power Management (ASPM) Control. Software
68505  *    must not enable L0s in either direction on a given Link unless components on both sides of the
68506  *    Link each support L0s; otherwise, the result is undefined. For a description of this standard
68507  *    PCIe register field, see the PCI Express Specification.
68508  */
68509 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK)
68510 
68511 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MASK (0x4U)
68512 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SHIFT (2U)
68513 /*! RSVDP_2 - Reserved for future use. */
68514 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MASK)
68515 
68516 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK (0x8U)
68517 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT (3U)
68518 /*! PCIE_CAP_RCB - Read Completion Boundary (RCB). Note: The access attributes of this field are as
68519  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68520  */
68521 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK)
68522 
68523 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK (0x10U)
68524 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT (4U)
68525 /*! PCIE_CAP_LINK_DISABLE - Initiate Link Disable. For a description of this standard PCIe register
68526  *    field, see the PCI Express Specification. In a DSP that supports crosslink, the controller
68527  *    gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access
68528  *    attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 &&
68529  *    PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
68530  */
68531 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK)
68532 
68533 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK (0x20U)
68534 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT (5U)
68535 /*! PCIE_CAP_RETRAIN_LINK - Initiate Link Retrain. For a description of this standard PCIe register
68536  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
68537  *    follows: - Dbi: see description
68538  */
68539 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK)
68540 
68541 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK (0x40U)
68542 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT (6U)
68543 /*! PCIE_CAP_COMMON_CLK_CONFIG - Common Clock Configuration. For a description of this standard PCIe register field, see the PCI Express Specification. */
68544 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK)
68545 
68546 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK (0x80U)
68547 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT (7U)
68548 /*! PCIE_CAP_EXTENDED_SYNCH - Extended Synch. For a description of this standard PCIe register field, see the PCI Express Specification. */
68549 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK)
68550 
68551 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK (0x100U)
68552 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT (8U)
68553 /*! PCIE_CAP_EN_CLK_POWER_MAN - Enable Clock Power Management. For a description of this standard
68554  *    PCIe register field, see the PCI Express Specification. The write value is gated with the
68555  *    PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field
68556  *    are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This
68557  *    register field is sticky.
68558  */
68559 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK)
68560 
68561 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK (0x200U)
68562 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT (9U)
68563 /*! PCIE_CAP_HW_AUTO_WIDTH_DISABLE - Hardware Autonomous Width Disable. For a description of this
68564  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of
68565  *    this field are as follows: - Dbi: R/W
68566  */
68567 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK)
68568 
68569 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK (0x400U)
68570 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT (10U)
68571 /*! PCIE_CAP_LINK_BW_MAN_INT_EN - Link Bandwidth Management Interrupt Enable. For a description of
68572  *    this standard PCIe register field, see the PCI Express Specification. The write value is gated
68573  *    with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes
68574  *    of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
68575  */
68576 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK)
68577 
68578 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK (0x800U)
68579 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT (11U)
68580 /*! PCIE_CAP_LINK_AUTO_BW_INT_EN - Link Autonomous Bandwidth Management Interrupt Enable. For a
68581  *    description of this standard PCIe register field, see the PCI Express Specification. The write
68582  *    value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access
68583  *    attributes of this field are as follows: - Dbi:
68584  *    LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
68585  */
68586 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK)
68587 
68588 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MASK (0x3000U)
68589 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SHIFT (12U)
68590 /*! RSVDP_12 - Reserved for future use. */
68591 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MASK)
68592 
68593 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK (0xC000U)
68594 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT (14U)
68595 /*! PCIE_CAP_DRS_SIGNALING_CONTROL - DRS Signaling Control. For a description of this standard PCIe
68596  *    register field, see the PCI Express Specification. Note: The access attributes of this field
68597  *    are as follows: - Dbi: LINK_CAPABILITIES2_REG.DRS_SUPPORTED ? RW : RO
68598  */
68599 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK)
68600 
68601 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK (0xF0000U)
68602 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT (16U)
68603 /*! PCIE_CAP_LINK_SPEED - Current Link Speed. For a description of this standard PCIe register field, see the PCI Express Specification. */
68604 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK)
68605 
68606 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK (0x3F00000U)
68607 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT (20U)
68608 /*! PCIE_CAP_NEGO_LINK_WIDTH - Negotiated Link Width. For a description of this standard PCIe register field, see the PCI Express Specification. */
68609 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK)
68610 
68611 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MASK (0x4000000U)
68612 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SHIFT (26U)
68613 /*! RSVDP_26 - Reserved for future use. */
68614 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MASK)
68615 
68616 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK (0x8000000U)
68617 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT (27U)
68618 /*! PCIE_CAP_LINK_TRAINING - LTSSM is in Configuration or Recovery State. For a description of this
68619  *    standard PCIe register field, see the PCI Express Specification.
68620  */
68621 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK)
68622 
68623 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK (0x10000000U)
68624 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT (28U)
68625 /*! PCIE_CAP_SLOT_CLK_CONFIG - Slot Clock Configuration. For a description of this standard PCIe
68626  *    register field, see the PCI Express Specification. Note: The access attributes of this field are
68627  *    as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68628  */
68629 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK)
68630 
68631 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK (0x20000000U)
68632 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT (29U)
68633 /*! PCIE_CAP_DLL_ACTIVE - Data Link Layer Active. For a description of this standard PCIe register field, see the PCI Express Specification. */
68634 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK)
68635 
68636 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK (0x40000000U)
68637 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT (30U)
68638 /*! PCIE_CAP_LINK_BW_MAN_STATUS - Link Bandwidth Management Status. For a description of this
68639  *    standard PCIe register field, see the PCI Express Specification. The write value is gated with the
68640  *    PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
68641  */
68642 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK)
68643 
68644 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK (0x80000000U)
68645 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT (31U)
68646 /*! PCIE_CAP_LINK_AUTO_BW_STATUS - Link Autonomous Bandwidth Status. For a description of this
68647  *    standard PCIe register field, see the PCI Express Specification. The write value is gated with the
68648  *    PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
68649  */
68650 #define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK)
68651 /*! @} */
68652 
68653 /*! @name SLOT_CAPABILITIES_REG - Slot Capabilities Register. */
68654 /*! @{ */
68655 
68656 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MASK (0x1U)
68657 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SHIFT (0U)
68658 /*! PCIE_CAP_ATTENTION_INDICATOR_BUTTON - Attention Button Present. For a description of this
68659  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68660  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68661  */
68662 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MASK)
68663 
68664 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MASK (0x2U)
68665 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SHIFT (1U)
68666 /*! PCIE_CAP_POWER_CONTROLLER - Power Controller Present. For a description of this standard PCIe
68667  *    register field, see the PCI Express Specification. Note: The access attributes of this field are
68668  *    as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68669  */
68670 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MASK)
68671 
68672 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MASK (0x4U)
68673 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SHIFT (2U)
68674 /*! PCIE_CAP_MRL_SENSOR - MRL Present. For a description of this standard PCIe register field, see
68675  *    the PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
68676  *    if (DBI_RO_WR_EN == 1) then R/W else R
68677  */
68678 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MASK)
68679 
68680 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MASK (0x8U)
68681 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SHIFT (3U)
68682 /*! PCIE_CAP_ATTENTION_INDICATOR - Attention Indicator Present. For a description of this standard
68683  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68684  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68685  */
68686 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MASK)
68687 
68688 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MASK (0x10U)
68689 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SHIFT (4U)
68690 /*! PCIE_CAP_POWER_INDICATOR - Power Indicator Present. For a description of this standard PCIe
68691  *    register field, see the PCI Express Specification. Note: The access attributes of this field are
68692  *    as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68693  */
68694 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MASK)
68695 
68696 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MASK (0x20U)
68697 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SHIFT (5U)
68698 /*! PCIE_CAP_HOT_PLUG_SURPRISE - Hot Plug Surprise possible. For a description of this standard PCIe
68699  *    register field, see the PCI Express Specification. Note: The access attributes of this field
68700  *    are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68701  */
68702 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MASK)
68703 
68704 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MASK (0x40U)
68705 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SHIFT (6U)
68706 /*! PCIE_CAP_HOT_PLUG_CAPABLE - Hot Plug Capable. For a description of this standard PCIe register
68707  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
68708  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68709  */
68710 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MASK)
68711 
68712 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MASK (0x7F80U)
68713 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SHIFT (7U)
68714 /*! PCIE_CAP_SLOT_POWER_LIMIT_VALUE - Slot Power Limit Value. For a description of this standard
68715  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this field
68716  *    are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68717  */
68718 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MASK)
68719 
68720 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MASK (0x18000U)
68721 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SHIFT (15U)
68722 /*! PCIE_CAP_SLOT_POWER_LIMIT_SCALE - Slot Power Limit Scale. For a description of this standard
68723  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this field
68724  *    are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68725  */
68726 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MASK)
68727 
68728 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MASK (0x20000U)
68729 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SHIFT (17U)
68730 /*! PCIE_CAP_ELECTROMECH_INTERLOCK - Electromechanical Interlock Present. For a description of this
68731  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes
68732  *    of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68733  */
68734 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MASK)
68735 
68736 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MASK (0x40000U)
68737 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SHIFT (18U)
68738 /*! PCIE_CAP_NO_CMD_CPL_SUPPORT - No Command Completed Support. For a description of this standard
68739  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68740  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68741  */
68742 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MASK)
68743 
68744 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MASK (0xFFF80000U)
68745 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SHIFT (19U)
68746 /*! PCIE_CAP_PHY_SLOT_NUM - Physical Slot Number. For a description of this standard PCIe register
68747  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
68748  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
68749  */
68750 #define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MASK)
68751 /*! @} */
68752 
68753 /*! @name SLOT_CONTROL_SLOT_STATUS - Slot Control and Status Register. */
68754 /*! @{ */
68755 
68756 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MASK (0x1U)
68757 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SHIFT (0U)
68758 /*! PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN - Attention Button Pressed Enable. For a description of
68759  *    this standard PCIe register field, see the PCI Express Specification.
68760  */
68761 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MASK)
68762 
68763 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MASK (0x2U)
68764 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SHIFT (1U)
68765 /*! PCIE_CAP_POWER_FAULT_DETECTED_EN - Power Fault Detected Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
68766 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MASK)
68767 
68768 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MASK (0x4U)
68769 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SHIFT (2U)
68770 /*! PCIE_CAP_MRL_SENSOR_CHANGED_EN - MRL Sensor Changed Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
68771 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MASK)
68772 
68773 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MASK (0x8U)
68774 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SHIFT (3U)
68775 /*! PCIE_CAP_PRESENCE_DETECT_CHANGE_EN - Presence Detect Changed Enable. For a description of this
68776  *    standard PCIe register field, see the PCI Express Specification.
68777  */
68778 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MASK)
68779 
68780 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MASK (0x10U)
68781 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SHIFT (4U)
68782 /*! PCIE_CAP_CMD_CPL_INT_EN - Command Completed Interrupt Enable. For a description of this standard
68783  *    PCIe register field, see the PCI Express Specification. Write value is gated with
68784  *    PCIE_CAP_NO_CMD_CPL_SUPPORT field in SLOT_CAPABILITIES_REG. Note: The access attributes of this field are
68785  *    as follows: - Dbi: SLOT_CAPABILITIES_REG.PCIE_CAP_NO_CMD_CPL_SUPPORT ? RO : RW
68786  */
68787 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MASK)
68788 
68789 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MASK (0x20U)
68790 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SHIFT (5U)
68791 /*! PCIE_CAP_HOT_PLUG_INT_EN - Hot Plug Interrupt Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
68792 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MASK)
68793 
68794 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MASK (0xC0U)
68795 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SHIFT (6U)
68796 /*! PCIE_CAP_ATTENTION_INDICATOR_CTRL - Attention Indicator Control. For a description of this standard PCIe register field, see the PCI Express Specification. */
68797 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MASK)
68798 
68799 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MASK (0x300U)
68800 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SHIFT (8U)
68801 /*! PCIE_CAP_POWER_INDICATOR_CTRL - Power Indicator Control. For a description of this standard PCIe register field, see the PCI Express Specification. */
68802 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MASK)
68803 
68804 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MASK (0x400U)
68805 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SHIFT (10U)
68806 /*! PCIE_CAP_POWER_CONTROLLER_CTRL - Power Controller Control. For a description of this standard PCIe register field, see the PCI Express Specification. */
68807 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MASK)
68808 
68809 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MASK (0x800U)
68810 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SHIFT (11U)
68811 /*! PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL - Electromechanical Interlock Control. For a description of
68812  *    this standard PCIe register field, see the PCI Express Specification.
68813  */
68814 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MASK)
68815 
68816 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MASK (0x1000U)
68817 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SHIFT (12U)
68818 /*! PCIE_CAP_DLL_STATE_CHANGED_EN - Data Link Layer State Changed Enable. For a description of this
68819  *    standard PCIe register field, see the PCI Express Specification.
68820  */
68821 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MASK)
68822 
68823 #define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_MASK (0xE000U)
68824 #define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_SHIFT (13U)
68825 /*! RSVDP_13 - Reserved for future use. */
68826 #define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_MASK)
68827 
68828 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MASK (0x10000U)
68829 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SHIFT (16U)
68830 /*! PCIE_CAP_ATTENTION_BUTTON_PRESSED - Attention Button Pressed. For a description of this standard PCIe register field, see the PCI Express Specification. */
68831 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MASK)
68832 
68833 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MASK (0x20000U)
68834 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SHIFT (17U)
68835 /*! PCIE_CAP_POWER_FAULT_DETECTED - Power Fault Detected. For a description of this standard PCIe register field, see the PCI Express Specification. */
68836 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MASK)
68837 
68838 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MASK (0x40000U)
68839 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SHIFT (18U)
68840 /*! PCIE_CAP_MRL_SENSOR_CHANGED - MRL Sensor Changed. For a description of this standard PCIe register field, see the PCI Express Specification. */
68841 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MASK)
68842 
68843 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MASK (0x80000U)
68844 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SHIFT (19U)
68845 /*! PCIE_CAP_PRESENCE_DETECTED_CHANGED - Presence Detect Changed. For a description of this standard PCIe register field, see the PCI Express Specification. */
68846 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MASK)
68847 
68848 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MASK (0x100000U)
68849 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SHIFT (20U)
68850 /*! PCIE_CAP_CMD_CPLD - Command Completed. For a description of this standard PCIe register field, see the PCI Express Specification. */
68851 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MASK)
68852 
68853 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MASK (0x200000U)
68854 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SHIFT (21U)
68855 /*! PCIE_CAP_MRL_SENSOR_STATE - MRL Sensor State. For a description of this standard PCIe register field, see the PCI Express Specification. */
68856 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MASK)
68857 
68858 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MASK (0x400000U)
68859 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SHIFT (22U)
68860 /*! PCIE_CAP_PRESENCE_DETECT_STATE - Presence Detect State. For a description of this standard PCIe
68861  *    register field, see the PCI Express Specification. Note: The access attributes of this field
68862  *    are as follows: - Dbi: R
68863  */
68864 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MASK)
68865 
68866 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MASK (0x800000U)
68867 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SHIFT (23U)
68868 /*! PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS - Electromechanical Interlock Status. For a description of
68869  *    this standard PCIe register field, see the PCI Express Specification.
68870  */
68871 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MASK)
68872 
68873 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MASK (0x1000000U)
68874 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SHIFT (24U)
68875 /*! PCIE_CAP_DLL_STATE_CHANGED - Data Link Layer State Changed. For a description of this standard
68876  *    PCIe register field, see the PCI Express Specification.
68877  */
68878 #define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MASK)
68879 
68880 #define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_MASK (0xFE000000U)
68881 #define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_SHIFT (25U)
68882 /*! RSVDP_25 - Reserved for future use. */
68883 #define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_MASK)
68884 /*! @} */
68885 
68886 /*! @name ROOT_CONTROL_ROOT_CAPABILITIES_REG - Root Control and Capabilities Register. */
68887 /*! @{ */
68888 
68889 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MASK (0x1U)
68890 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SHIFT (0U)
68891 /*! PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN - System Error on Correctable Error Enable. For a description of
68892  *    this standard PCIe register field, see the PCI Express Specification.
68893  */
68894 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MASK)
68895 
68896 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MASK (0x2U)
68897 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SHIFT (1U)
68898 /*! PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN - System Error on Non-fatal Error Enable. For a description
68899  *    of this standard PCIe register field, see the PCI Express Specification.
68900  */
68901 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MASK)
68902 
68903 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MASK (0x4U)
68904 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SHIFT (2U)
68905 /*! PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN - System Error on Fatal Error Enable. For a description of this
68906  *    standard PCIe register field, see the PCI Express Specification.
68907  */
68908 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MASK)
68909 
68910 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MASK (0x8U)
68911 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SHIFT (3U)
68912 /*! PCIE_CAP_PME_INT_EN - PME Interrupt Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
68913 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MASK)
68914 
68915 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MASK (0x10U)
68916 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SHIFT (4U)
68917 /*! PCIE_CAP_CRS_SW_VISIBILITY_EN - Configuration Request Retry Status (CRS) Software Visibility
68918  *    Enable. For a description of this standard PCIe register field, see the PCI Express
68919  *    Specification. Note: The access attributes of this field are as follows: - Dbi:
68920  *    ROOT_CONTROL_ROOT_CAPABILITIES_REG.PCIE_CAP_CRS_SW_VISIBILITY ? RW : RO
68921  */
68922 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MASK)
68923 
68924 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_MASK (0xFFE0U)
68925 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_SHIFT (5U)
68926 /*! RSVDP_5 - Reserved for future use. */
68927 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_MASK)
68928 
68929 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MASK (0x10000U)
68930 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SHIFT (16U)
68931 /*! PCIE_CAP_CRS_SW_VISIBILITY - CRS Software Visibility Capable. For a description of this standard
68932  *    PCIe register field, see the PCI Express Specification. Note: The access attributes of this
68933  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R (Sticky) Note:
68934  *    This register field is sticky.
68935  */
68936 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MASK)
68937 
68938 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_MASK (0xFFFE0000U)
68939 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_SHIFT (17U)
68940 /*! RSVDP_17 - Reserved for future use. */
68941 #define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_MASK)
68942 /*! @} */
68943 
68944 /*! @name ROOT_STATUS_REG - Root Status Register. */
68945 /*! @{ */
68946 
68947 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MASK (0xFFFFU)
68948 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SHIFT (0U)
68949 /*! PCIE_CAP_PME_REQ_ID - PME Requester ID. For a description of this standard PCIe register field, see the PCI Express Specification. */
68950 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SHIFT)) & PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MASK)
68951 
68952 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MASK (0x10000U)
68953 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SHIFT (16U)
68954 /*! PCIE_CAP_PME_STATUS - PME Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
68955 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SHIFT)) & PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MASK)
68956 
68957 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MASK (0x20000U)
68958 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SHIFT (17U)
68959 /*! PCIE_CAP_PME_PENDING - PME Pending. For a description of this standard PCIe register field, see the PCI Express Specification. */
68960 #define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SHIFT)) & PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MASK)
68961 
68962 #define PCIE_ROOT_STATUS_REG_RSVDP_18_MASK       (0xFFFC0000U)
68963 #define PCIE_ROOT_STATUS_REG_RSVDP_18_SHIFT      (18U)
68964 /*! RSVDP_18 - Reserved for future use. */
68965 #define PCIE_ROOT_STATUS_REG_RSVDP_18(x)         (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_RSVDP_18_SHIFT)) & PCIE_ROOT_STATUS_REG_RSVDP_18_MASK)
68966 /*! @} */
68967 
68968 /*! @name DEVICE_CAPABILITIES2_REG - Device Capabilities 2 Register. */
68969 /*! @{ */
68970 
68971 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK (0xFU)
68972 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT (0U)
68973 /*! PCIE_CAP_CPL_TIMEOUT_RANGE - Completion Timeout Ranges Supported. For a description of this
68974  *    standard PCIe register field, see the PCI Express Specification.
68975  */
68976 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK)
68977 
68978 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK (0x10U)
68979 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT (4U)
68980 /*! PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT - Completion Timeout Disable Supported. For a description
68981  *    of this standard PCIe register field, see the PCI Express Specification.
68982  */
68983 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK)
68984 
68985 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK (0x20U)
68986 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT (5U)
68987 /*! PCIE_CAP_ARI_FORWARD_SUPPORT - ARI Forwarding Supported. For a description of this standard PCIe register field, see the PCI Express Specification. */
68988 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK)
68989 
68990 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK (0x40U)
68991 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT (6U)
68992 /*! PCIE_CAP_ATOMIC_ROUTING_SUPP - Atomic Operation Routing Supported. For a description of this
68993  *    standard PCIe register field, see the PCI Express Specification.
68994  */
68995 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK)
68996 
68997 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK (0x80U)
68998 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT (7U)
68999 /*! PCIE_CAP_32_ATOMIC_CPL_SUPP - 32 Bit AtomicOp Completer Supported. For a description of this
69000  *    standard PCIe register field, see the PCI Express Specification.
69001  */
69002 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK)
69003 
69004 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK (0x100U)
69005 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT (8U)
69006 /*! PCIE_CAP_64_ATOMIC_CPL_SUPP - 64 Bit AtomicOp Completer Supported. For a description of this
69007  *    standard PCIe register field, see the PCI Express Specification.
69008  */
69009 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK)
69010 
69011 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK (0x200U)
69012 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT (9U)
69013 /*! PCIE_CAP_128_CAS_CPL_SUPP - 128 Bit CAS Completer Supported. For a description of this standard
69014  *    PCIe register field, see the PCI Express Specification.
69015  */
69016 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK)
69017 
69018 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK (0x400U)
69019 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT (10U)
69020 /*! PCIE_CAP_NO_RO_EN_PR2PR_PAR - No Relaxed Ordering Enabled PR-PR Passing. For a description of
69021  *    this standard PCIe register field, see the PCI Express Specification.
69022  */
69023 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK)
69024 
69025 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK (0x800U)
69026 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT (11U)
69027 /*! PCIE_CAP_LTR_SUPP - LTR Mechanism Supported. For a description of this standard PCIe register field, see the PCI Express Specification. */
69028 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK)
69029 
69030 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK (0x1000U)
69031 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT (12U)
69032 /*! PCIE_CAP_TPH_CMPLT_SUPPORT_0 - TPH Completer Supported Bit 0. For a description of this standard
69033  *    PCIe register field, see the PCI Express Specification.
69034  */
69035 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK)
69036 
69037 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK (0x2000U)
69038 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT (13U)
69039 /*! PCIE_CAP_TPH_CMPLT_SUPPORT_1 - TPH Completer Supported Bit 1. For a description of this standard
69040  *    PCIe register field, see the PCI Express Specification.
69041  */
69042 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK)
69043 
69044 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK (0x10000U)
69045 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT (16U)
69046 /*! PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT - 10-Bit Tag Completer Supported. For a description of this
69047  *    standard PCIe register field, see the PCI Express Base Specification 4.0.
69048  */
69049 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK)
69050 
69051 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK (0x20000U)
69052 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT (17U)
69053 /*! PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT - 10-Bit Tag Requester Supported. For a description of this
69054  *    standard PCIe register field, see the PCI Express Base Specification 4.0.
69055  */
69056 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK)
69057 
69058 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_MASK (0xC0000U)
69059 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_SHIFT (18U)
69060 /*! PCIE_CAP_OBFF_SUPPORT - (OBFF) Optimized Buffer Flush/fill Supported. For a description of this
69061  *    standard PCIe register field, see the PCI Express Specification.
69062  */
69063 #define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_MASK)
69064 
69065 #define PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_MASK (0x7F000000U)
69066 #define PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_SHIFT (24U)
69067 /*! RSVDP_24 - Reserved for future use. */
69068 #define PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_MASK)
69069 /*! @} */
69070 
69071 /*! @name DEVICE_CONTROL2_DEVICE_STATUS2_REG - Device Control 2 and Status 2 Register. */
69072 /*! @{ */
69073 
69074 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK (0xFU)
69075 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT (0U)
69076 /*! PCIE_CAP_CPL_TIMEOUT_VALUE - Completion Timeout Value. For a description of this standard PCIe
69077  *    register field, see the PCI Express Specification. Note: The access attributes of this field
69078  *    are as follows: - Dbi: R/W
69079  */
69080 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT)) & PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK)
69081 
69082 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK (0x10U)
69083 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT (4U)
69084 /*! PCIE_CAP_CPL_TIMEOUT_DISABLE - Completion Timeout Disable. For a description of this standard PCIe register field, see the PCI Express Specification. */
69085 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT)) & PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK)
69086 
69087 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK (0x20U)
69088 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT (5U)
69089 /*! PCIE_CAP_ARI_FORWARD_SUPPORT_CS - ARI Forwarding Enable. For a description of this standard PCIe
69090  *    register field, see the PCI Express Specification. Note: The access attributes of this field
69091  *    are as follows: - Dbi: R/W
69092  */
69093 #define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT)) & PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK)
69094 /*! @} */
69095 
69096 /*! @name LINK_CAPABILITIES2_REG - Link Capabilities 2 Register. */
69097 /*! @{ */
69098 
69099 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_MASK (0x1U)
69100 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_SHIFT (0U)
69101 /*! RSVDP_0 - Reserved for future use. */
69102 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_0(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_MASK)
69103 
69104 #define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK (0xFEU)
69105 #define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT (1U)
69106 /*! PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR - Supported Link Speeds Vector. For a description of this
69107  *    standard PCIe register field, see the PCI Express Specification. This field has a default of
69108  *    (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 :
69109  *    (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in
69110  *    the LINK_CAPABILITIES_REG register.
69111  */
69112 #define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK)
69113 
69114 #define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK (0x100U)
69115 #define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT (8U)
69116 /*! PCIE_CAP_CROSS_LINK_SUPPORT - Cross Link Supported. For a description of this standard PCIe register field, see the PCI Express Specification. */
69117 #define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK)
69118 
69119 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_MASK (0x7FFE00U)
69120 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_SHIFT (9U)
69121 /*! RSVDP_9 - Reserved for future use. */
69122 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_9(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_MASK)
69123 
69124 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_MASK (0x7E000000U)
69125 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_SHIFT (25U)
69126 /*! RSVDP_25 - Reserved for future use. */
69127 #define PCIE_LINK_CAPABILITIES2_REG_RSVDP_25(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_MASK)
69128 /*! @} */
69129 
69130 /*! @name LINK_CONTROL2_LINK_STATUS2_REG - Link Control 2 and Status 2 Register. */
69131 /*! @{ */
69132 
69133 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK (0xFU)
69134 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT (0U)
69135 /*! PCIE_CAP_TARGET_LINK_SPEED - Target Link Speed. For a description of this standard PCIe register
69136  *    field, see the PCI Express Specification. In M-PCIe mode, the contents of this field are
69137  *    derived from other registers. Note: This register field is sticky.
69138  */
69139 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK)
69140 
69141 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK (0x10U)
69142 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT (4U)
69143 /*! PCIE_CAP_ENTER_COMPLIANCE - Enter Compliance Mode. For a description of this standard PCIe
69144  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69145  */
69146 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK)
69147 
69148 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK (0x20U)
69149 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT (5U)
69150 /*! PCIE_CAP_HW_AUTO_SPEED_DISABLE - Hardware Autonomous Speed Disable. For a description of this
69151  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of
69152  *    this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69153  */
69154 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK)
69155 
69156 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK (0x40U)
69157 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT (6U)
69158 /*! PCIE_CAP_SEL_DEEMPHASIS - Controls Selectable De-emphasis for 5 GT/s. For a description of this
69159  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes
69160  *    of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
69161  *    Note: This register field is sticky.
69162  */
69163 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK)
69164 
69165 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK (0x380U)
69166 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT (7U)
69167 /*! PCIE_CAP_TX_MARGIN - Controls Transmit Margin for Debug or Compliance. For a description of this
69168  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69169  *    sticky.
69170  */
69171 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK)
69172 
69173 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK (0x400U)
69174 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT (10U)
69175 /*! PCIE_CAP_ENTER_MODIFIED_COMPLIANCE - Enter Modified Compliance. For a description of this
69176  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
69177  *    field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69178  */
69179 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK)
69180 
69181 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK (0x800U)
69182 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT (11U)
69183 /*! PCIE_CAP_COMPLIANCE_SOS - Sets Compliance Skip Ordered Sets transmission. For a description of
69184  *    this standard PCIe register field, see the PCI Express Specification. Note: The access
69185  *    attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69186  */
69187 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK)
69188 
69189 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK (0xF000U)
69190 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT (12U)
69191 /*! PCIE_CAP_COMPLIANCE_PRESET - Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. For a
69192  *    description of this standard PCIe register field, see the PCI Express Specification. Note: The
69193  *    access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is
69194  *    sticky.
69195  */
69196 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK)
69197 
69198 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK (0x10000U)
69199 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT (16U)
69200 /*! PCIE_CAP_CURR_DEEMPHASIS - Current De-emphasis Level. For a description of this standard PCIe
69201  *    register field, see the PCI Express Specification. In M-PCIe mode this register is always 0x0.
69202  *    In C-PCIe mode, its contents are derived by sampling the PIPE
69203  */
69204 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK)
69205 
69206 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MASK (0xC000000U)
69207 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SHIFT (26U)
69208 /*! RSVDP_26 - Reserved for future use. */
69209 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MASK)
69210 
69211 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MASK (0x70000000U)
69212 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SHIFT (28U)
69213 /*! DOWNSTREAM_COMPO_PRESENCE - Downstream Component Presence. For a description of this standard
69214  *    PCIe register field, see the PCI Express Base Specification 4.0.
69215  */
69216 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MASK)
69217 
69218 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MASK (0x80000000U)
69219 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SHIFT (31U)
69220 /*! DRS_MESSAGE_RECEIVED - DRS Message Received. For a description of this standard PCIe register
69221  *    field, see the PCI Express Base Specification 4.0. Note: The access attributes of this field are
69222  *    as follows: - Dbi: RW1C
69223  */
69224 #define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MASK)
69225 /*! @} */
69226 
69227 /*! @name AER_EXT_CAP_HDR_OFF - Advanced Error Reporting Extended Capability Header. */
69228 /*! @{ */
69229 
69230 #define PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK     (0xFFFFU)
69231 #define PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT    (0U)
69232 /*! CAP_ID - AER Extended Capability ID. For a description of this standard PCIe register field, see
69233  *    the PCI Express Specification. Note: The access attributes of this field are as follows: -
69234  *    Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
69235  */
69236 #define PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT)) & PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK)
69237 
69238 #define PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK (0xF0000U)
69239 #define PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT (16U)
69240 /*! CAP_VERSION - Capability Version. For a description of this standard PCIe register field, see
69241  *    the PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
69242  *    if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
69243  */
69244 #define PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT)) & PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK)
69245 
69246 #define PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK (0xFFF00000U)
69247 #define PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT (20U)
69248 /*! NEXT_OFFSET - Next Capability Offset. For a description of this standard PCIe register field,
69249  *    see the PCI Express Specification. Note: The access attributes of this field are as follows: -
69250  *    Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
69251  */
69252 #define PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT)) & PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK)
69253 /*! @} */
69254 
69255 /*! @name UNCORR_ERR_STATUS_OFF - Uncorrectable Error Status Register. */
69256 /*! @{ */
69257 
69258 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_MASK  (0xFU)
69259 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_SHIFT (0U)
69260 /*! RSVDP_0 - Reserved for future use. */
69261 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_MASK)
69262 
69263 #define PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK (0x10U)
69264 #define PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT (4U)
69265 /*! DL_PROTOCOL_ERR_STATUS - Data Link Protocol Error Status. For a description of this standard
69266  *    PCIe register field, see the PCI Express Specification.
69267  */
69268 #define PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK)
69269 
69270 #define PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK (0x20U)
69271 #define PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT (5U)
69272 /*! SURPRISE_DOWN_ERR_STATUS - Surprise Down Error Status (Optional). For a description of this
69273  *    standard PCIe register field, see the PCI Express Specification.
69274  */
69275 #define PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK)
69276 
69277 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_MASK  (0xFC0U)
69278 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_SHIFT (6U)
69279 /*! RSVDP_6 - Reserved for future use. */
69280 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_MASK)
69281 
69282 #define PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK (0x1000U)
69283 #define PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT (12U)
69284 /*! POIS_TLP_ERR_STATUS - Poisoned TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69285 #define PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK)
69286 
69287 #define PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK (0x2000U)
69288 #define PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT (13U)
69289 /*! FC_PROTOCOL_ERR_STATUS - Flow Control Protocol Error Status. For a description of this standard
69290  *    PCIe register field, see the PCI Express Specification.
69291  */
69292 #define PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK)
69293 
69294 #define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK (0x4000U)
69295 #define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT (14U)
69296 /*! CMPLT_TIMEOUT_ERR_STATUS - Completion Timeout Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69297 #define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK)
69298 
69299 #define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK (0x8000U)
69300 #define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT (15U)
69301 /*! CMPLT_ABORT_ERR_STATUS - Completer Abort Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69302 #define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK)
69303 
69304 #define PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK (0x10000U)
69305 #define PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT (16U)
69306 /*! UNEXP_CMPLT_ERR_STATUS - Unexpected Completion Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69307 #define PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK)
69308 
69309 #define PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK (0x20000U)
69310 #define PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT (17U)
69311 /*! REC_OVERFLOW_ERR_STATUS - Receiver Overflow Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69312 #define PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK)
69313 
69314 #define PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK (0x40000U)
69315 #define PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT (18U)
69316 /*! MALF_TLP_ERR_STATUS - Malformed TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69317 #define PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK)
69318 
69319 #define PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK (0x80000U)
69320 #define PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT (19U)
69321 /*! ECRC_ERR_STATUS - ECRC Error Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69322 #define PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK)
69323 
69324 #define PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK (0x100000U)
69325 #define PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT (20U)
69326 /*! UNSUPPORTED_REQ_ERR_STATUS - Unsupported Request Error Status. For a description of this
69327  *    standard PCIe register field, see the PCI Express Specification.
69328  */
69329 #define PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK)
69330 
69331 #define PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK (0x400000U)
69332 #define PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT (22U)
69333 /*! INTERNAL_ERR_STATUS - Uncorrectable Internal Error Status. For a description of this standard
69334  *    PCIe register field, see the PCI Express Specification. The controller sets this bit when your
69335  *    application asserts app_err_bus[9]. It does not set this bit when it detects internal
69336  *    uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these
69337  *    errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire,
69338  *    Datapath, and RAM Protection)" section in the Databook.
69339  */
69340 #define PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK)
69341 
69342 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_MASK (0x800000U)
69343 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_SHIFT (23U)
69344 /*! RSVDP_23 - Reserved for future use. */
69345 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_MASK)
69346 
69347 #define PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_MASK (0x2000000U)
69348 #define PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_SHIFT (25U)
69349 /*! TLP_PRFX_BLOCKED_ERR_STATUS - TLP Prefix Blocked Error Status. For a description of this
69350  *    standard PCIe register field, see the PCI Express Specification. Note: Not supported.
69351  */
69352 #define PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_MASK)
69353 
69354 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_MASK (0xFC000000U)
69355 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_SHIFT (26U)
69356 /*! RSVDP_26 - Reserved for future use. */
69357 #define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_MASK)
69358 /*! @} */
69359 
69360 /*! @name UNCORR_ERR_MASK_OFF - Uncorrectable Error Mask Register. */
69361 /*! @{ */
69362 
69363 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_MASK    (0xFU)
69364 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_SHIFT   (0U)
69365 /*! RSVDP_0 - Reserved for future use. */
69366 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_MASK)
69367 
69368 #define PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK (0x10U)
69369 #define PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT (4U)
69370 /*! DL_PROTOCOL_ERR_MASK - Data Link Protocol Error Mask. For a description of this standard PCIe
69371  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69372  */
69373 #define PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK)
69374 
69375 #define PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK (0x20U)
69376 #define PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT (5U)
69377 /*! SURPRISE_DOWN_ERR_MASK - Surprise Down Error Mask. For a description of this standard PCIe
69378  *    register field, see the PCI Express Specification. Note: The access attributes of this field are as
69379  *    follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This
69380  *    register field is sticky.
69381  */
69382 #define PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK)
69383 
69384 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_MASK    (0xFC0U)
69385 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_SHIFT   (6U)
69386 /*! RSVDP_6 - Reserved for future use. */
69387 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_MASK)
69388 
69389 #define PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK (0x1000U)
69390 #define PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT (12U)
69391 /*! POIS_TLP_ERR_MASK - Poisoned TLP Error Mask. For a description of this standard PCIe register
69392  *    field, see the PCI Express Specification. Note: This register field is sticky.
69393  */
69394 #define PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK)
69395 
69396 #define PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK (0x2000U)
69397 #define PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT (13U)
69398 /*! FC_PROTOCOL_ERR_MASK - Flow Control Protocol Error Mask. For a description of this standard PCIe
69399  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69400  */
69401 #define PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK)
69402 
69403 #define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK (0x4000U)
69404 #define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT (14U)
69405 /*! CMPLT_TIMEOUT_ERR_MASK - Completion Timeout Error Mask. For a description of this standard PCIe
69406  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69407  */
69408 #define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK)
69409 
69410 #define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK (0x8000U)
69411 #define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT (15U)
69412 /*! CMPLT_ABORT_ERR_MASK - Completer Abort Error Mask (Optional). For a description of this standard
69413  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
69414  */
69415 #define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK)
69416 
69417 #define PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK (0x10000U)
69418 #define PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT (16U)
69419 /*! UNEXP_CMPLT_ERR_MASK - Unexpected Completion Mask. For a description of this standard PCIe
69420  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69421  */
69422 #define PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK)
69423 
69424 #define PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK (0x20000U)
69425 #define PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT (17U)
69426 /*! REC_OVERFLOW_ERR_MASK - Receiver Overflow Mask (Optional). For a description of this standard
69427  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
69428  */
69429 #define PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK)
69430 
69431 #define PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK (0x40000U)
69432 #define PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT (18U)
69433 /*! MALF_TLP_ERR_MASK - Malformed TLP Mask. For a description of this standard PCIe register field,
69434  *    see the PCI Express Specification. Note: This register field is sticky.
69435  */
69436 #define PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK)
69437 
69438 #define PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK (0x80000U)
69439 #define PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT (19U)
69440 /*! ECRC_ERR_MASK - ECRC Error Mask (Optional). For a description of this standard PCIe register
69441  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
69442  *    follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69443  */
69444 #define PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK)
69445 
69446 #define PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK (0x100000U)
69447 #define PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT (20U)
69448 /*! UNSUPPORTED_REQ_ERR_MASK - Unsupported Request Error Mask. For a description of this standard
69449  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
69450  */
69451 #define PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK)
69452 
69453 #define PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK (0x400000U)
69454 #define PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT (22U)
69455 /*! INTERNAL_ERR_MASK - Uncorrectable Internal Error Mask (Optional). For a description of this
69456  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69457  *    sticky.
69458  */
69459 #define PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK)
69460 
69461 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_MASK   (0x800000U)
69462 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_SHIFT  (23U)
69463 /*! RSVDP_23 - Reserved for future use. */
69464 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_MASK)
69465 
69466 #define PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MASK (0x1000000U)
69467 #define PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT (24U)
69468 /*! ATOMIC_EGRESS_BLOCKED_ERR_MASK - AtomicOp Egress Block Mask (Optional). For a description of
69469  *    this standard PCIe register field, see the PCI Express Specification. Note: The access attributes
69470  *    of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69471  */
69472 #define PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MASK)
69473 
69474 #define PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_MASK (0x2000000U)
69475 #define PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT (25U)
69476 /*! TLP_PRFX_BLOCKED_ERR_MASK - TLP Prefix Blocked Error Mask. For a description of this standard
69477  *    PCIe register field, see the PCI Express Specification. Note: Not supported. Note: The access
69478  *    attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69479  */
69480 #define PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_MASK)
69481 
69482 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_MASK   (0xFC000000U)
69483 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_SHIFT  (26U)
69484 /*! RSVDP_26 - Reserved for future use. */
69485 #define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_MASK)
69486 /*! @} */
69487 
69488 /*! @name UNCORR_ERR_SEV_OFF - Uncorrectable Error Severity Register. */
69489 /*! @{ */
69490 
69491 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_MASK     (0xFU)
69492 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_SHIFT    (0U)
69493 /*! RSVDP_0 - Reserved for future use. */
69494 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_MASK)
69495 
69496 #define PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK (0x10U)
69497 #define PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT (4U)
69498 /*! DL_PROTOCOL_ERR_SEVERITY - Data Link Protocol Error Severity. For a description of this standard
69499  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
69500  */
69501 #define PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK)
69502 
69503 #define PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK (0x20U)
69504 #define PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT (5U)
69505 /*! SURPRISE_DOWN_ERR_SVRITY - Surprise Down Error Severity (Optional). For a description of this
69506  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of
69507  *    this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ?
69508  *    RW : RO Note: This register field is sticky.
69509  */
69510 #define PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK)
69511 
69512 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_MASK     (0xFC0U)
69513 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_SHIFT    (6U)
69514 /*! RSVDP_6 - Reserved for future use. */
69515 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_MASK)
69516 
69517 #define PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK (0x1000U)
69518 #define PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT (12U)
69519 /*! POIS_TLP_ERR_SEVERITY - Poisoned TLP Severity. For a description of this standard PCIe register
69520  *    field, see the PCI Express Specification. Note: This register field is sticky.
69521  */
69522 #define PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK)
69523 
69524 #define PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK (0x2000U)
69525 #define PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT (13U)
69526 /*! FC_PROTOCOL_ERR_SEVERITY - Flow Control Protocol Error Severity (Optional). For a description of
69527  *    this standard PCIe register field, see the PCI Express Specification. Note: This register
69528  *    field is sticky.
69529  */
69530 #define PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK)
69531 
69532 #define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK (0x4000U)
69533 #define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT (14U)
69534 /*! CMPLT_TIMEOUT_ERR_SEVERITY - Completion Timeout Error Severity. For a description of this
69535  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
69536  */
69537 #define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK)
69538 
69539 #define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK (0x8000U)
69540 #define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT (15U)
69541 /*! CMPLT_ABORT_ERR_SEVERITY - Completer Abort Error Severity (Optional). For a description of this
69542  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69543  *    sticky.
69544  */
69545 #define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK)
69546 
69547 #define PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK (0x10000U)
69548 #define PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT (16U)
69549 /*! UNEXP_CMPLT_ERR_SEVERITY - Unexpected Completion Error Severity. For a description of this
69550  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69551  *    sticky.
69552  */
69553 #define PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK)
69554 
69555 #define PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK (0x20000U)
69556 #define PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT (17U)
69557 /*! REC_OVERFLOW_ERR_SEVERITY - Receiver Overflow Error Severity (Optional). For a description of
69558  *    this standard PCIe register field, see the PCI Express Specification. Note: This register field
69559  *    is sticky.
69560  */
69561 #define PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK)
69562 
69563 #define PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK (0x40000U)
69564 #define PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT (18U)
69565 /*! MALF_TLP_ERR_SEVERITY - Malformed TLP Severity. For a description of this standard PCIe register
69566  *    field, see the PCI Express Specification. Note: This register field is sticky.
69567  */
69568 #define PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK)
69569 
69570 #define PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK (0x80000U)
69571 #define PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT (19U)
69572 /*! ECRC_ERR_SEVERITY - ECRC Error Severity (Optional). For a description of this standard PCIe
69573  *    register field, see the PCI Express Specification. Note: The access attributes of this field are
69574  *    as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
69575  */
69576 #define PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK)
69577 
69578 #define PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK (0x100000U)
69579 #define PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT (20U)
69580 /*! UNSUPPORTED_REQ_ERR_SEVERITY - Unsupported Request Error Severity. For a description of this
69581  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69582  *    sticky.
69583  */
69584 #define PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK)
69585 
69586 #define PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK (0x400000U)
69587 #define PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT (22U)
69588 /*! INTERNAL_ERR_SEVERITY - Uncorrectable Internal Error Severity (Optional). For a description of
69589  *    this standard PCIe register field, see the PCI Express Specification. Note: This register field
69590  *    is sticky.
69591  */
69592 #define PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK)
69593 
69594 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_MASK    (0x800000U)
69595 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_SHIFT   (23U)
69596 /*! RSVDP_23 - Reserved for future use. */
69597 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_MASK)
69598 
69599 #define PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MASK (0x1000000U)
69600 #define PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT (24U)
69601 /*! ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY - AtomicOp Egress Blocked Severity (Optional). For a
69602  *    description of this standard PCIe register field, see the PCI Express Specification. Note: The access
69603  *    attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is
69604  *    sticky.
69605  */
69606 #define PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MASK)
69607 
69608 #define PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_MASK (0x2000000U)
69609 #define PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT (25U)
69610 /*! TLP_PRFX_BLOCKED_ERR_SEVERITY - TLP Prefix Blocked Error Severity (Optional). For a description
69611  *    of this standard PCIe register field, see the PCI Express Specification. Note: Not supported.
69612  *    Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This
69613  *    register field is sticky.
69614  */
69615 #define PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_MASK)
69616 
69617 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_MASK    (0xFC000000U)
69618 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_SHIFT   (26U)
69619 /*! RSVDP_26 - Reserved for future use. */
69620 #define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_MASK)
69621 /*! @} */
69622 
69623 /*! @name CORR_ERR_STATUS_OFF - Correctable Error Status Register. */
69624 /*! @{ */
69625 
69626 #define PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK (0x1U)
69627 #define PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT (0U)
69628 /*! RX_ERR_STATUS - Receiver Error Status (Optional). For a description of this standard PCIe
69629  *    register field, see the PCI Express Specification.
69630  */
69631 #define PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK)
69632 
69633 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_MASK    (0x3EU)
69634 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_SHIFT   (1U)
69635 /*! RSVDP_1 - Reserved for future use. */
69636 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_1(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_MASK)
69637 
69638 #define PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK (0x40U)
69639 #define PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT (6U)
69640 /*! BAD_TLP_STATUS - Bad TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69641 #define PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK)
69642 
69643 #define PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK (0x80U)
69644 #define PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT (7U)
69645 /*! BAD_DLLP_STATUS - Bad DLLP Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69646 #define PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK)
69647 
69648 #define PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK (0x100U)
69649 #define PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT (8U)
69650 /*! REPLAY_NO_ROLEOVER_STATUS - REPLAY_NUM Rollover Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69651 #define PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK)
69652 
69653 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_MASK    (0xE00U)
69654 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_SHIFT   (9U)
69655 /*! RSVDP_9 - Reserved for future use. */
69656 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_9(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_MASK)
69657 
69658 #define PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK (0x1000U)
69659 #define PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT (12U)
69660 /*! RPL_TIMER_TIMEOUT_STATUS - Replay Timer Timeout Status. For a description of this standard PCIe register field, see the PCI Express Specification. */
69661 #define PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK)
69662 
69663 #define PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK (0x2000U)
69664 #define PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT (13U)
69665 /*! ADVISORY_NON_FATAL_ERR_STATUS - Advisory Non-Fatal Error Status. For a description of this
69666  *    standard PCIe register field, see the PCI Express Specification.
69667  */
69668 #define PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK)
69669 
69670 #define PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK (0x4000U)
69671 #define PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT (14U)
69672 /*! CORRECTED_INT_ERR_STATUS - Corrected Internal Error Status (Optional). For a description of this
69673  *    standard PCIe register field, see the PCI Express Specification.
69674  */
69675 #define PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK)
69676 
69677 #define PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK (0x8000U)
69678 #define PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT (15U)
69679 /*! HEADER_LOG_OVERFLOW_STATUS - Header Log Overflow Error Status (Optional). For a description of
69680  *    this standard PCIe register field, see the PCI Express Specification.
69681  */
69682 #define PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK)
69683 
69684 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_MASK   (0xFFFF0000U)
69685 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_SHIFT  (16U)
69686 /*! RSVDP_16 - Reserved for future use. */
69687 #define PCIE_CORR_ERR_STATUS_OFF_RSVDP_16(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_MASK)
69688 /*! @} */
69689 
69690 /*! @name CORR_ERR_MASK_OFF - Correctable Error Mask Register. */
69691 /*! @{ */
69692 
69693 #define PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK  (0x1U)
69694 #define PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT (0U)
69695 /*! RX_ERR_MASK - Receiver Error Mask (Optional). For a description of this standard PCIe register
69696  *    field, see the PCI Express Specification. Note: This register field is sticky.
69697  */
69698 #define PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK)
69699 
69700 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_1_MASK      (0x3EU)
69701 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_1_SHIFT     (1U)
69702 /*! RSVDP_1 - Reserved for future use. */
69703 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_1(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RSVDP_1_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RSVDP_1_MASK)
69704 
69705 #define PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK (0x40U)
69706 #define PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT (6U)
69707 /*! BAD_TLP_MASK - Bad TLP Mask. For a description of this standard PCIe register field, see the PCI
69708  *    Express Specification. Note: This register field is sticky.
69709  */
69710 #define PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK)
69711 
69712 #define PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK (0x80U)
69713 #define PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT (7U)
69714 /*! BAD_DLLP_MASK - Bad DLLP Mask. For a description of this standard PCIe register field, see the
69715  *    PCI Express Specification. Note: This register field is sticky.
69716  */
69717 #define PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK)
69718 
69719 #define PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK (0x100U)
69720 #define PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT (8U)
69721 /*! REPLAY_NO_ROLEOVER_MASK - REPLAY_NUM Rollover Mask. For a description of this standard PCIe
69722  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69723  */
69724 #define PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK)
69725 
69726 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_9_MASK      (0xE00U)
69727 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_9_SHIFT     (9U)
69728 /*! RSVDP_9 - Reserved for future use. */
69729 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_9(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RSVDP_9_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RSVDP_9_MASK)
69730 
69731 #define PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK (0x1000U)
69732 #define PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT (12U)
69733 /*! RPL_TIMER_TIMEOUT_MASK - Replay Timer Timeout Mask. For a description of this standard PCIe
69734  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69735  */
69736 #define PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK)
69737 
69738 #define PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK (0x2000U)
69739 #define PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT (13U)
69740 /*! ADVISORY_NON_FATAL_ERR_MASK - Advisory Non-Fatal Error Mask. For a description of this standard
69741  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
69742  */
69743 #define PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK)
69744 
69745 #define PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK (0x4000U)
69746 #define PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT (14U)
69747 /*! CORRECTED_INT_ERR_MASK - Corrected Internal Error Mask (Optional). For a description of this
69748  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69749  *    sticky.
69750  */
69751 #define PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK)
69752 
69753 #define PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK (0x8000U)
69754 #define PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT (15U)
69755 /*! HEADER_LOG_OVERFLOW_MASK - Header Log Overflow Error Mask (Optional). For a description of this
69756  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
69757  *    sticky.
69758  */
69759 #define PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK)
69760 
69761 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_16_MASK     (0xFFFF0000U)
69762 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_16_SHIFT    (16U)
69763 /*! RSVDP_16 - Reserved for future use. */
69764 #define PCIE_CORR_ERR_MASK_OFF_RSVDP_16(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RSVDP_16_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RSVDP_16_MASK)
69765 /*! @} */
69766 
69767 /*! @name ADV_ERR_CAP_CTRL_OFF - Advanced Error Capabilities and Control Register. */
69768 /*! @{ */
69769 
69770 #define PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK (0x1FU)
69771 #define PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT (0U)
69772 /*! FIRST_ERR_POINTER - First Error Pointer. For a description of this standard PCIe register field,
69773  *    see the PCI Express Specification. Note: This register field is sticky.
69774  */
69775 #define PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK)
69776 
69777 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK (0x20U)
69778 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT (5U)
69779 /*! ECRC_GEN_CAP - ECRC Generation Capable. For a description of this standard PCIe register field,
69780  *    see the PCI Express Specification. Note: This register field is sticky.
69781  */
69782 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK)
69783 
69784 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK (0x40U)
69785 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT (6U)
69786 /*! ECRC_GEN_EN - ECRC Generation Enable. For a description of this standard PCIe register field,
69787  *    see the PCI Express Specification. Note: This register field is sticky.
69788  */
69789 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK)
69790 
69791 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK (0x80U)
69792 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT (7U)
69793 /*! ECRC_CHECK_CAP - ECRC Check Capable. For a description of this standard PCIe register field, see
69794  *    the PCI Express Specification. Note: This register field is sticky.
69795  */
69796 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK)
69797 
69798 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK (0x100U)
69799 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT (8U)
69800 /*! ECRC_CHECK_EN - ECRC Check Enable. For a description of this standard PCIe register field, see
69801  *    the PCI Express Specification. Note: This register field is sticky.
69802  */
69803 #define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK)
69804 
69805 #define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK (0x200U)
69806 #define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT (9U)
69807 /*! MULTIPLE_HEADER_CAP - Multiple Header Recording Capable. For a description of this standard PCIe
69808  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69809  */
69810 #define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK)
69811 
69812 #define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK (0x400U)
69813 #define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT (10U)
69814 /*! MULTIPLE_HEADER_EN - Multiple Header Recording Enable. For a description of this standard PCIe
69815  *    register field, see the PCI Express Specification. Note: This register field is sticky.
69816  */
69817 #define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK)
69818 
69819 #define PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_MASK  (0xFFFFF000U)
69820 #define PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_SHIFT (12U)
69821 /*! RSVDP_12 - Reserved for future use. */
69822 #define PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_MASK)
69823 /*! @} */
69824 
69825 /*! @name HDR_LOG_0_OFF - Header Log Register 0. */
69826 /*! @{ */
69827 
69828 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK (0xFFU)
69829 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT (0U)
69830 /*! FIRST_DWORD_FIRST_BYTE - Byte 0 of Header log register of First 32 bit Data Word. For a
69831  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69832  *    register field is sticky.
69833  */
69834 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK)
69835 
69836 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK (0xFF00U)
69837 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT (8U)
69838 /*! FIRST_DWORD_SECOND_BYTE - Byte 1 of Header log register of First 32 bit Data Word. For a
69839  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69840  *    register field is sticky.
69841  */
69842 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK)
69843 
69844 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK (0xFF0000U)
69845 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT (16U)
69846 /*! FIRST_DWORD_THIRD_BYTE - Byte 2 of Header log register of First 32 bit Data Word. For a
69847  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69848  *    register field is sticky.
69849  */
69850 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK)
69851 
69852 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
69853 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT (24U)
69854 /*! FIRST_DWORD_FOURTH_BYTE - Byte 3 of Header log register of First 32 bit Data Word. For a
69855  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69856  *    register field is sticky.
69857  */
69858 #define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK)
69859 /*! @} */
69860 
69861 /*! @name HDR_LOG_1_OFF - Header Log Register 1. */
69862 /*! @{ */
69863 
69864 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK (0xFFU)
69865 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT (0U)
69866 /*! SECOND_DWORD_FIRST_BYTE - Byte 0 of Header log register of Second 32 bit Data Word. For a
69867  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69868  *    register field is sticky.
69869  */
69870 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK)
69871 
69872 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK (0xFF00U)
69873 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT (8U)
69874 /*! SECOND_DWORD_SECOND_BYTE - Byte 1 of Header log register of Second 32 bit Data Word. For a
69875  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69876  *    register field is sticky.
69877  */
69878 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK)
69879 
69880 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK (0xFF0000U)
69881 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT (16U)
69882 /*! SECOND_DWORD_THIRD_BYTE - Byte 2 of Header log register of Second 32 bit Data Word. For a
69883  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69884  *    register field is sticky.
69885  */
69886 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK)
69887 
69888 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
69889 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT (24U)
69890 /*! SECOND_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Second 32 bit Data Word. For a
69891  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69892  *    register field is sticky.
69893  */
69894 #define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK)
69895 /*! @} */
69896 
69897 /*! @name HDR_LOG_2_OFF - Header Log Register 2. */
69898 /*! @{ */
69899 
69900 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK (0xFFU)
69901 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT (0U)
69902 /*! THIRD_DWORD_FIRST_BYTE - Byte 0 of Header log register of Third 32 bit Data Word. For a
69903  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69904  *    register field is sticky.
69905  */
69906 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK)
69907 
69908 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK (0xFF00U)
69909 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT (8U)
69910 /*! THIRD_DWORD_SECOND_BYTE - Byte 1 of Header log register of Third 32 bit Data Word. For a
69911  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69912  *    register field is sticky.
69913  */
69914 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK)
69915 
69916 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK (0xFF0000U)
69917 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT (16U)
69918 /*! THIRD_DWORD_THIRD_BYTE - Byte 2 of Header log register of Third 32 bit Data Word. For a
69919  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69920  *    register field is sticky.
69921  */
69922 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK)
69923 
69924 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
69925 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT (24U)
69926 /*! THIRD_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Third 32 bit Data Word. For a
69927  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69928  *    register field is sticky.
69929  */
69930 #define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK)
69931 /*! @} */
69932 
69933 /*! @name HDR_LOG_3_OFF - Header Log Register 3. */
69934 /*! @{ */
69935 
69936 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK (0xFFU)
69937 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT (0U)
69938 /*! FOURTH_DWORD_FIRST_BYTE - Byte 0 of Header log register of Fourth 32 bit Data Word. For a
69939  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69940  *    register field is sticky.
69941  */
69942 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK)
69943 
69944 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK (0xFF00U)
69945 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT (8U)
69946 /*! FOURTH_DWORD_SECOND_BYTE - Byte 1 of Header log register of Fourth 32 bit Data Word. For a
69947  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69948  *    register field is sticky.
69949  */
69950 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK)
69951 
69952 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK (0xFF0000U)
69953 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT (16U)
69954 /*! FOURTH_DWORD_THIRD_BYTE - Byte 2 of Header log register of Fourth 32 bit Data Word. For a
69955  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69956  *    register field is sticky.
69957  */
69958 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK)
69959 
69960 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
69961 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT (24U)
69962 /*! FOURTH_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Fourth 32 bit Data Word. For a
69963  *    description of this standard PCIe register field, see the PCI Express Specification. Note: This
69964  *    register field is sticky.
69965  */
69966 #define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK)
69967 /*! @} */
69968 
69969 /*! @name ROOT_ERR_CMD_OFF - Root Error Command Register. */
69970 /*! @{ */
69971 
69972 #define PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MASK (0x1U)
69973 #define PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SHIFT (0U)
69974 /*! CORR_ERR_REPORTING_EN - Correctable Error Reporting Enable. For a description of this standard
69975  *    PCIe register field, see the PCI Express Specification.
69976  */
69977 #define PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MASK)
69978 
69979 #define PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MASK (0x2U)
69980 #define PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SHIFT (1U)
69981 /*! NON_FATAL_ERR_REPORTING_EN - Non-Fatal Error Reporting Enable. For a description of this
69982  *    standard PCIe register field, see the PCI Express Specification.
69983  */
69984 #define PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MASK)
69985 
69986 #define PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MASK (0x4U)
69987 #define PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SHIFT (2U)
69988 /*! FATAL_ERR_REPORTING_EN - Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
69989 #define PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MASK)
69990 
69991 #define PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_MASK       (0xFFFFFFF8U)
69992 #define PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_SHIFT      (3U)
69993 /*! RSVDP_3 - Reserved for future use. */
69994 #define PCIE_ROOT_ERR_CMD_OFF_RSVDP_3(x)         (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_MASK)
69995 /*! @} */
69996 
69997 /*! @name ROOT_ERR_STATUS_OFF - Root Error Status Register. */
69998 /*! @{ */
69999 
70000 #define PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MASK (0x1U)
70001 #define PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SHIFT (0U)
70002 /*! ERR_COR_RX - Correctable Error Received. For a description of this standard PCIe register field, see the PCI Express Specification. */
70003 #define PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MASK)
70004 
70005 #define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MASK (0x2U)
70006 #define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SHIFT (1U)
70007 /*! MUL_ERR_COR_RX - Multiple Correctable Errors Received. For a description of this standard PCIe
70008  *    register field, see the PCI Express Specification.
70009  */
70010 #define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MASK)
70011 
70012 #define PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MASK (0x4U)
70013 #define PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SHIFT (2U)
70014 /*! ERR_FATAL_NON_FATAL_RX - Fatal or Non-Fatal Error Received. For a description of this standard
70015  *    PCIe register field, see the PCI Express Specification.
70016  */
70017 #define PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MASK)
70018 
70019 #define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MASK (0x8U)
70020 #define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SHIFT (3U)
70021 /*! MUL_ERR_FATAL_NON_FATAL_RX - Multiple Fatal or Non-Fatal Errors Received. For a description of
70022  *    this standard PCIe register field, see the PCI Express Specification.
70023  */
70024 #define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MASK)
70025 
70026 #define PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MASK (0x10U)
70027 #define PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SHIFT (4U)
70028 /*! FIRST_UNCORR_FATAL - First Uncorrectable Error is Fatal. For a description of this standard PCIe
70029  *    register field, see the PCI Express Specification.
70030  */
70031 #define PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MASK)
70032 
70033 #define PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MASK (0x20U)
70034 #define PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SHIFT (5U)
70035 /*! NON_FATAL_ERR_MSG_RX - One or more Non-Fatal Error Messages Received. For a description of this
70036  *    standard PCIe register field, see the PCI Express Specification.
70037  */
70038 #define PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MASK)
70039 
70040 #define PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MASK (0x40U)
70041 #define PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SHIFT (6U)
70042 /*! FATAL_ERR_MSG_RX - One or more Fatal Error Messages Received. For a description of this standard
70043  *    PCIe register field, see the PCI Express Specification.
70044  */
70045 #define PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MASK)
70046 
70047 #define PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_MASK    (0x7FFFF80U)
70048 #define PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_SHIFT   (7U)
70049 /*! RSVDP_7 - Reserved for future use. */
70050 #define PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_MASK)
70051 
70052 #define PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MASK (0xF8000000U)
70053 #define PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SHIFT (27U)
70054 /*! ADV_ERR_INT_MSG_NUM - Advanced Error Interrupt Message Number. For a description of this
70055  *    standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
70056  *    field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This
70057  *    register field is sticky.
70058  */
70059 #define PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MASK)
70060 /*! @} */
70061 
70062 /*! @name ERR_SRC_ID_OFF - Error Source Identification Register. */
70063 /*! @{ */
70064 
70065 #define PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MASK (0xFFFFU)
70066 #define PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SHIFT (0U)
70067 /*! ERR_COR_SOURCE_ID - Source of Correctable Error. For a description of this standard PCIe
70068  *    register field, see the PCI Express Specification. Note: This register field is sticky.
70069  */
70070 #define PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SHIFT)) & PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MASK)
70071 
70072 #define PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MASK (0xFFFF0000U)
70073 #define PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SHIFT (16U)
70074 /*! ERR_FATAL_NON_FATAL_SOURCE_ID - Source of Fatal/Non-Fatal Error. For a description of this
70075  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
70076  *    sticky.
70077  */
70078 #define PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SHIFT)) & PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MASK)
70079 /*! @} */
70080 
70081 /*! @name TLP_PREFIX_LOG_1_OFF - TLP Prefix Log Register 1. */
70082 /*! @{ */
70083 
70084 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK (0xFFU)
70085 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT (0U)
70086 /*! CFG_TLP_PFX_LOG_1_FIRST_BYTE - Byte 0 of Error TLP Prefix Log 1. For a description of this
70087  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
70088  *    sticky.
70089  */
70090 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK)
70091 
70092 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK (0xFF00U)
70093 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT (8U)
70094 /*! CFG_TLP_PFX_LOG_1_SECOND_BYTE - Byte 1 of Error TLP Prefix Log 1. For a description of this
70095  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
70096  *    sticky.
70097  */
70098 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK)
70099 
70100 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK (0xFF0000U)
70101 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT (16U)
70102 /*! CFG_TLP_PFX_LOG_1_THIRD_BYTE - Byte 2 of Error TLP Prefix Log 1. For a description of this
70103  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
70104  *    sticky.
70105  */
70106 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK)
70107 
70108 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK (0xFF000000U)
70109 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT (24U)
70110 /*! CFG_TLP_PFX_LOG_1_FOURTH_BYTE - Byte 3 of Error TLP Prefix Log 1. For a description of this
70111  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is
70112  *    sticky.
70113  */
70114 #define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK)
70115 /*! @} */
70116 
70117 /*! @name TLP_PREFIX_LOG_2_OFF - TLP Prefix Log Register 2. */
70118 /*! @{ */
70119 
70120 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK (0xFFU)
70121 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT (0U)
70122 /*! CFG_TLP_PFX_LOG_2_FIRST_BYTE - Byte 0 Error TLP Prefix Log 2. For a description of this standard
70123  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70124  */
70125 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK)
70126 
70127 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK (0xFF00U)
70128 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT (8U)
70129 /*! CFG_TLP_PFX_LOG_2_SECOND_BYTE - Byte 1 Error TLP Prefix Log 2. For a description of this
70130  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70131  */
70132 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK)
70133 
70134 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK (0xFF0000U)
70135 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT (16U)
70136 /*! CFG_TLP_PFX_LOG_2_THIRD_BYTE - Byte 2 Error TLP Prefix Log 2. For a description of this standard
70137  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70138  */
70139 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK)
70140 
70141 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK (0xFF000000U)
70142 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT (24U)
70143 /*! CFG_TLP_PFX_LOG_2_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 2. For a description of this
70144  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70145  */
70146 #define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK)
70147 /*! @} */
70148 
70149 /*! @name TLP_PREFIX_LOG_3_OFF - TLP Prefix Log Register 3. */
70150 /*! @{ */
70151 
70152 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK (0xFFU)
70153 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT (0U)
70154 /*! CFG_TLP_PFX_LOG_3_FIRST_BYTE - Byte 0 Error TLP Prefix Log 3. For a description of this standard
70155  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70156  */
70157 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK)
70158 
70159 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK (0xFF00U)
70160 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT (8U)
70161 /*! CFG_TLP_PFX_LOG_3_SECOND_BYTE - Byte 1 Error TLP Prefix Log 3. For a description of this
70162  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70163  */
70164 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK)
70165 
70166 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK (0xFF0000U)
70167 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT (16U)
70168 /*! CFG_TLP_PFX_LOG_3_THIRD_BYTE - Byte 2 Error TLP Prefix Log 3. For a description of this standard
70169  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70170  */
70171 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK)
70172 
70173 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK (0xFF000000U)
70174 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT (24U)
70175 /*! CFG_TLP_PFX_LOG_3_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 3. For a description of this
70176  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70177  */
70178 #define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK)
70179 /*! @} */
70180 
70181 /*! @name TLP_PREFIX_LOG_4_OFF - TLP Prefix Log Register 4. */
70182 /*! @{ */
70183 
70184 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK (0xFFU)
70185 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT (0U)
70186 /*! CFG_TLP_PFX_LOG_4_FIRST_BYTE - Byte 0 Error TLP Prefix Log 4. For a description of this standard
70187  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70188  */
70189 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK)
70190 
70191 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK (0xFF00U)
70192 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT (8U)
70193 /*! CFG_TLP_PFX_LOG_4_SECOND_BYTE - Byte 1 Error TLP Prefix Log 4. For a description of this
70194  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70195  */
70196 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK)
70197 
70198 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK (0xFF0000U)
70199 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT (16U)
70200 /*! CFG_TLP_PFX_LOG_4_THIRD_BYTE - Byte 2 Error TLP Prefix Log 4. For a description of this standard
70201  *    PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70202  */
70203 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK)
70204 
70205 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK (0xFF000000U)
70206 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT (24U)
70207 /*! CFG_TLP_PFX_LOG_4_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 4. For a description of this
70208  *    standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
70209  */
70210 #define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK)
70211 /*! @} */
70212 
70213 /*! @name L1SUB_CAP_HEADER_REG - L1 Substates Extended Capability Header. */
70214 /*! @{ */
70215 
70216 #define PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK (0xFFFFU)
70217 #define PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT (0U)
70218 /*! EXTENDED_CAP_ID - L1SUB Extended Capability ID. For a description of this standard PCIe register
70219  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
70220  *    follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field
70221  *    is sticky.
70222  */
70223 #define PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT)) & PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK)
70224 
70225 #define PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK (0xF0000U)
70226 #define PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT (16U)
70227 /*! CAP_VERSION - Capability Version. For a description of this standard PCIe register field, see
70228  *    the PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
70229  *    if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
70230  */
70231 #define PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT)) & PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK)
70232 
70233 #define PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK (0xFFF00000U)
70234 #define PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT (20U)
70235 /*! NEXT_OFFSET - Next Capability Offset. For a description of this standard PCIe register field,
70236  *    see the PCI Express Specification. Note: The access attributes of this field are as follows: -
70237  *    Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
70238  */
70239 #define PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT)) & PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK)
70240 /*! @} */
70241 
70242 /*! @name L1SUB_CAPABILITY_REG - L1 Substates Capability Register. */
70243 /*! @{ */
70244 
70245 #define PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK (0x1U)
70246 #define PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT (0U)
70247 /*! L1_2_PCIPM_SUPPORT - PCI-PM L12 Supported. For a description of this standard PCIe register
70248  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
70249  *    follows: - Dbi: R/W
70250  */
70251 #define PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK)
70252 
70253 #define PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK (0x2U)
70254 #define PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT (1U)
70255 /*! L1_1_PCIPM_SUPPORT - PCI-PM L11 Supported. For a description of this standard PCIe register
70256  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
70257  *    follows: - Dbi: R/W
70258  */
70259 #define PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK)
70260 
70261 #define PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK (0x4U)
70262 #define PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT (2U)
70263 /*! L1_2_ASPM_SUPPORT - ASPM L12 Supported. For a description of this standard PCIe register field,
70264  *    see the PCI Express Specification. Note: The access attributes of this field are as follows: -
70265  *    Dbi: R/W
70266  */
70267 #define PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK)
70268 
70269 #define PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK (0x8U)
70270 #define PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT (3U)
70271 /*! L1_1_ASPM_SUPPORT - ASPM L11 Supported. For a description of this standard PCIe register field,
70272  *    see the PCI Express Specification. Note: The access attributes of this field are as follows: -
70273  *    Dbi: R/W
70274  */
70275 #define PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK)
70276 
70277 #define PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK (0x10U)
70278 #define PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT (4U)
70279 /*! L1_PMSUB_SUPPORT - L1 PM Substates ECN Supported. For a description of this standard PCIe
70280  *    register field, see the PCI Express Specification. Note: The access attributes of this field are as
70281  *    follows: - Dbi: R/W
70282  */
70283 #define PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK)
70284 
70285 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_MASK   (0xE0U)
70286 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_SHIFT  (5U)
70287 /*! RSVDP_5 - Reserved for future use. */
70288 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_5(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_MASK)
70289 
70290 #define PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK (0xFF00U)
70291 #define PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT (8U)
70292 /*! COMM_MODE_SUPPORT - Port Common Mode Restore Time. For a description of this standard PCIe
70293  *    register field, see the PCI Express Specification. Note: The access attributes of this field are as
70294  *    follows: - Dbi: R/W
70295  */
70296 #define PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK)
70297 
70298 #define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK (0x30000U)
70299 #define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT (16U)
70300 /*! PWR_ON_SCALE_SUPPORT - Port T Power On Scale. For a description of this standard PCIe register
70301  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
70302  *    follows: - Dbi: R/W
70303  */
70304 #define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK)
70305 
70306 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_MASK  (0x40000U)
70307 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_SHIFT (18U)
70308 /*! RSVDP_18 - Reserved for future use. */
70309 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_18(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_MASK)
70310 
70311 #define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK (0xF80000U)
70312 #define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT (19U)
70313 /*! PWR_ON_VALUE_SUPPORT - Port T Power On Value. For a description of this standard PCIe register
70314  *    field, see the PCI Express Specification. Note: The access attributes of this field are as
70315  *    follows: - Dbi: R/W
70316  */
70317 #define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK)
70318 
70319 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_MASK  (0xFF000000U)
70320 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_SHIFT (24U)
70321 /*! RSVDP_24 - Reserved for future use. */
70322 #define PCIE_L1SUB_CAPABILITY_REG_RSVDP_24(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_MASK)
70323 /*! @} */
70324 
70325 /*! @name L1SUB_CONTROL1_REG - L1 Substates Control 1 Register. */
70326 /*! @{ */
70327 
70328 #define PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK (0x1U)
70329 #define PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT (0U)
70330 /*! L1_2_PCIPM_EN - PCI-PM L12 Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
70331 #define PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK)
70332 
70333 #define PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK (0x2U)
70334 #define PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT (1U)
70335 /*! L1_1_PCIPM_EN - PCI-PM L11 Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
70336 #define PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK)
70337 
70338 #define PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK (0x4U)
70339 #define PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT (2U)
70340 /*! L1_2_ASPM_EN - ASPM L12 Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
70341 #define PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK)
70342 
70343 #define PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK (0x8U)
70344 #define PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT (3U)
70345 /*! L1_1_ASPM_EN - ASPM L11 Enable. For a description of this standard PCIe register field, see the PCI Express Specification. */
70346 #define PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK)
70347 
70348 #define PCIE_L1SUB_CONTROL1_REG_RSVDP_4_MASK     (0xF0U)
70349 #define PCIE_L1SUB_CONTROL1_REG_RSVDP_4_SHIFT    (4U)
70350 /*! RSVDP_4 - Reserved for future use. */
70351 #define PCIE_L1SUB_CONTROL1_REG_RSVDP_4(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_RSVDP_4_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_RSVDP_4_MASK)
70352 
70353 #define PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK (0xFF00U)
70354 #define PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT (8U)
70355 /*! T_COMMON_MODE - Common Mode Restore Time. For a description of this standard PCIe register
70356  *    field, see the PCI Express Specification. Note: The access attributes of this field are as follows:
70357  *    - Dbi: R/W
70358  */
70359 #define PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK)
70360 
70361 #define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK (0x3FF0000U)
70362 #define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT (16U)
70363 /*! L1_2_TH_VAL - LTR L12 Threshold Value. For a description of this standard PCIe register field, see the PCI Express Specification. */
70364 #define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK)
70365 
70366 #define PCIE_L1SUB_CONTROL1_REG_RSVDP_26_MASK    (0x1C000000U)
70367 #define PCIE_L1SUB_CONTROL1_REG_RSVDP_26_SHIFT   (26U)
70368 /*! RSVDP_26 - Reserved for future use. */
70369 #define PCIE_L1SUB_CONTROL1_REG_RSVDP_26(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_RSVDP_26_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_RSVDP_26_MASK)
70370 
70371 #define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK (0xE0000000U)
70372 #define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT (29U)
70373 /*! L1_2_TH_SCA - LTR L12 Threshold Scale. For a description of this standard PCIe register field, see the PCI Express Specification. */
70374 #define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK)
70375 /*! @} */
70376 
70377 /*! @name L1SUB_CONTROL2_REG - L1 Substates Control 2 Register. */
70378 /*! @{ */
70379 
70380 #define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK (0x3U)
70381 #define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT (0U)
70382 /*! T_POWER_ON_SCALE - T Power On Scale. For a description of this standard PCIe register field, see the PCI Express Specification. */
70383 #define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK)
70384 
70385 #define PCIE_L1SUB_CONTROL2_REG_RSVDP_2_MASK     (0x4U)
70386 #define PCIE_L1SUB_CONTROL2_REG_RSVDP_2_SHIFT    (2U)
70387 /*! RSVDP_2 - Reserved for future use. */
70388 #define PCIE_L1SUB_CONTROL2_REG_RSVDP_2(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_RSVDP_2_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_RSVDP_2_MASK)
70389 
70390 #define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK (0xF8U)
70391 #define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT (3U)
70392 /*! T_POWER_ON_VALUE - T Power On Value. For a description of this standard PCIe register field, see the PCI Express Specification. */
70393 #define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK)
70394 
70395 #define PCIE_L1SUB_CONTROL2_REG_RSVDP_8_MASK     (0xFFFFFF00U)
70396 #define PCIE_L1SUB_CONTROL2_REG_RSVDP_8_SHIFT    (8U)
70397 /*! RSVDP_8 - Reserved for future use. */
70398 #define PCIE_L1SUB_CONTROL2_REG_RSVDP_8(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_RSVDP_8_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_RSVDP_8_MASK)
70399 /*! @} */
70400 
70401 /*! @name ACK_LATENCY_TIMER_OFF - Ack Latency Timer and Replay Timer Register. */
70402 /*! @{ */
70403 
70404 #define PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK (0xFFFFU)
70405 #define PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT (0U)
70406 /*! ROUND_TRIP_LATENCY_TIME_LIMIT - Ack Latency Timer Limit. The Ack latency timer expires when it
70407  *    reaches this limit. For more details, see "Ack Scheduling". You can modify the effective timer
70408  *    limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After
70409  *    reset, the controller updates the default according to the Negotiated Link Width,
70410  *    Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0
70411  *    specification. The limit must reflect the round trip latency from requester to completer. If there is a
70412  *    change in the payload size or link width, the controller will override any value that you have
70413  *    written to this register field, and reset the field back to the specification-defined value.
70414  *    It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF
70415  *    register.
70416  */
70417 #define PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT)) & PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK)
70418 
70419 #define PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK (0xFFFF0000U)
70420 #define PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT (16U)
70421 /*! REPLAY_TIME_LIMIT - Replay Timer Limit. The replay timer expires when it reaches this limit. The
70422  *    controller initiates a replay upon reception of a NAK or when the replay timer expires. For
70423  *    more details, see "Transmit Replay". You can modify the effective timer limit with the
70424  *    TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the controller
70425  *    updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The
70426  *    value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a
70427  *    change in the payload size or link speed, the controller will override any value that you have
70428  *    written to this register field, and reset the field back to the specification-defined value.
70429  *    It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the
70430  *    TIMER_CTRL_MAX_FUNC_NUM_OFF register.
70431  */
70432 #define PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT)) & PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK)
70433 /*! @} */
70434 
70435 /*! @name VENDOR_SPEC_DLLP_OFF - Vendor Specific DLLP Register. */
70436 /*! @{ */
70437 
70438 #define PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK (0xFFFFFFFFU)
70439 #define PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT (0U)
70440 /*! VENDOR_SPEC_DLLP - Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your
70441  *    application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then
70442  *    sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type
70443  *    - [31:8] = Payload (24 bits) The dllp type is in bits [7:0] while the remainder is the vendor
70444  *    defined payload. Note: This register field is sticky.
70445  */
70446 #define PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT)) & PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK)
70447 /*! @} */
70448 
70449 /*! @name PORT_FORCE_OFF - Port Force Link Register. */
70450 /*! @{ */
70451 
70452 #define PCIE_PORT_FORCE_OFF_LINK_NUM_MASK        (0xFFU)
70453 #define PCIE_PORT_FORCE_OFF_LINK_NUM_SHIFT       (0U)
70454 /*! LINK_NUM - Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky. */
70455 #define PCIE_PORT_FORCE_OFF_LINK_NUM(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_LINK_NUM_SHIFT)) & PCIE_PORT_FORCE_OFF_LINK_NUM_MASK)
70456 
70457 #define PCIE_PORT_FORCE_OFF_FORCED_LTSSM_MASK    (0xF00U)
70458 #define PCIE_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT   (8U)
70459 /*! FORCED_LTSSM - Forced Link Command. The link command that the controller is forced to transmit
70460  *    when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd
70461  *    variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky.
70462  */
70463 #define PCIE_PORT_FORCE_OFF_FORCED_LTSSM(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT)) & PCIE_PORT_FORCE_OFF_FORCED_LTSSM_MASK)
70464 
70465 #define PCIE_PORT_FORCE_OFF_RSVDP_12_MASK        (0x7000U)
70466 #define PCIE_PORT_FORCE_OFF_RSVDP_12_SHIFT       (12U)
70467 /*! RSVDP_12 - Reserved for future use. */
70468 #define PCIE_PORT_FORCE_OFF_RSVDP_12(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_RSVDP_12_SHIFT)) & PCIE_PORT_FORCE_OFF_RSVDP_12_MASK)
70469 
70470 #define PCIE_PORT_FORCE_OFF_FORCE_EN_MASK        (0x8000U)
70471 #define PCIE_PORT_FORCE_OFF_FORCE_EN_SHIFT       (15U)
70472 /*! FORCE_EN - Force Link. The controller supports a testing and debug capability to allow your
70473  *    software to force the LTSSM state machine into a specific state, and to force the controller to
70474  *    transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces
70475  *    the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to
70476  *    transmit the command specified by the Forced Link Command field. This is a self-clearing register
70477  *    field. Reading from this register field always returns a "0".
70478  */
70479 #define PCIE_PORT_FORCE_OFF_FORCE_EN(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_FORCE_EN_SHIFT)) & PCIE_PORT_FORCE_OFF_FORCE_EN_MASK)
70480 
70481 #define PCIE_PORT_FORCE_OFF_LINK_STATE_MASK      (0x3F0000U)
70482 #define PCIE_PORT_FORCE_OFF_LINK_STATE_SHIFT     (16U)
70483 /*! LINK_STATE - Forced LTSSM State. The LTSSM state that the controller is forced to when you set
70484  *    the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in
70485  *    workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky.
70486  */
70487 #define PCIE_PORT_FORCE_OFF_LINK_STATE(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_LINK_STATE_SHIFT)) & PCIE_PORT_FORCE_OFF_LINK_STATE_MASK)
70488 
70489 #define PCIE_PORT_FORCE_OFF_RSVDP_22_MASK        (0x400000U)
70490 #define PCIE_PORT_FORCE_OFF_RSVDP_22_SHIFT       (22U)
70491 /*! RSVDP_22 - Reserved for future use. */
70492 #define PCIE_PORT_FORCE_OFF_RSVDP_22(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_RSVDP_22_SHIFT)) & PCIE_PORT_FORCE_OFF_RSVDP_22_MASK)
70493 
70494 #define PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK (0x800000U)
70495 #define PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT (23U)
70496 /*! DO_DESKEW_FOR_SRIS - Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle
70497  *    Symbol, and FTS Sequence to SKP OS to do deskew for SRIS instead of using received SKP OS if
70498  *    DO_DESKEW_FOR_SRIS is set to 1. Note: This register field is sticky.
70499  */
70500 #define PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT)) & PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK)
70501 
70502 #define PCIE_PORT_FORCE_OFF_RSVDP_24_MASK        (0xFF000000U)
70503 #define PCIE_PORT_FORCE_OFF_RSVDP_24_SHIFT       (24U)
70504 /*! RSVDP_24 - Reserved for future use. */
70505 #define PCIE_PORT_FORCE_OFF_RSVDP_24(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_RSVDP_24_SHIFT)) & PCIE_PORT_FORCE_OFF_RSVDP_24_MASK)
70506 /*! @} */
70507 
70508 /*! @name ACK_F_ASPM_CTRL_OFF - Ack Frequency and L0-L1 ASPM Control Register. */
70509 /*! @{ */
70510 
70511 #define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK   (0xFFU)
70512 #define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT  (0U)
70513 /*! ACK_FREQ - Ack Frequency. The controller accumulates the number of pending ACKs specified here
70514  *    (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature
70515  *    is turned off. The controller schedules a low-priority ACK DLLP for every TLP that it
70516  *    receives. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving
70517  *    this number of TLPs. It might schedule the ACK before receiving this number of TLPs, but never
70518  *    later. For a typical system, you do not have to modify the default setting. For more details,
70519  *    see "ACK/NAK Scheduling". Note: This register field is sticky.
70520  */
70521 #define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK)
70522 
70523 #define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK  (0xFF00U)
70524 #define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT (8U)
70525 /*! ACK_N_FTS - N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when
70526  *    transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request
70527  *    is 255. The controller does not support a value of zero; a value of zero can cause the LTSSM
70528  *    to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for
70529  *    M-PCIe. Note: This register field is sticky.
70530  */
70531 #define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK)
70532 
70533 #define PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK (0xFF0000U)
70534 #define PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT (16U)
70535 /*! COMMON_CLK_N_FTS - Common Clock N_FTS. This is the N_FTS when common clock is used. The number
70536  *    of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The
70537  *    maximum number of FTS ordered-sets that a component can request is 255. This field is only
70538  *    writable (sticky) when all of the following configuration parameter equations are true: -
70539  *    CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY -
70540  *    DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The controller does not support a value of zero; a
70541  *    value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field
70542  *    is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as
70543  *    follows: - Dbi: R
70544  */
70545 #define PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK)
70546 
70547 #define PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK (0x7000000U)
70548 #define PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT (24U)
70549 /*! L0S_ENTRANCE_LATENCY - L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us -
70550  *    010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to
70551  *    STALL while in L0 for M-PCIe. Note: This register field is sticky.
70552  */
70553 #define PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK)
70554 
70555 #define PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK (0x38000000U)
70556 #define PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT (27U)
70557 /*! L1_ENTRANCE_LATENCY - L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us -
70558  *    011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a
70559  *    value greater that 32us has no effect unless extended sync is used, or all of the credits are
70560  *    infinite. Note: This register field is sticky.
70561  */
70562 #define PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK)
70563 
70564 #define PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK (0x40000000U)
70565 #define PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT (30U)
70566 /*! ENTER_ASPM - ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been
70567  *    idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit
70568  *    are in L0s. Note: This register field is sticky.
70569  */
70570 #define PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK)
70571 
70572 #define PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MASK   (0x80000000U)
70573 #define PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SHIFT  (31U)
70574 /*! RSVDP_31 - Reserved for future use. */
70575 #define PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MASK)
70576 /*! @} */
70577 
70578 /*! @name PORT_LINK_CTRL_OFF - Port Link Control Register. */
70579 /*! @{ */
70580 
70581 #define PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK (0x1U)
70582 #define PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT (0U)
70583 /*! VENDOR_SPECIFIC_DLLP_REQ - Vendor Specific DLLP Request. When software writes a '1' to this bit,
70584  *    the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of
70585  *    VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always returns a '0'.
70586  */
70587 #define PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK)
70588 
70589 #define PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK (0x2U)
70590 #define PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT (1U)
70591 /*! SCRAMBLE_DISABLE - Scramble Disable. Turns off data scrambling. Note: This register field is sticky. */
70592 #define PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK)
70593 
70594 #define PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK (0x4U)
70595 #define PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT (2U)
70596 /*! LOOPBACK_ENABLE - Loopback Enable. Turns on loopback. For more details, see "Loopback". For
70597  *    M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during
70598  *    Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback
70599  *    mode from L0 state - only from Configuration.start. Note: This register field is sticky.
70600  */
70601 #define PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK)
70602 
70603 #define PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK (0x8U)
70604 #define PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT (3U)
70605 /*! RESET_ASSERT - Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state
70606  *    (downstream port only). Note: This register field is sticky.
70607  */
70608 #define PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK)
70609 
70610 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_MASK     (0x10U)
70611 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_SHIFT    (4U)
70612 /*! RSVDP_4 - Reserved for future use. */
70613 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_4(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_MASK)
70614 
70615 #define PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK (0x20U)
70616 #define PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT (5U)
70617 /*! DLL_LINK_EN - DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the
70618  *    controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is
70619  *    sticky.
70620  */
70621 #define PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK)
70622 
70623 #define PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK (0x40U)
70624 #define PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT (6U)
70625 /*! LINK_DISABLE - LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky. */
70626 #define PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK)
70627 
70628 #define PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK (0x80U)
70629 #define PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT (7U)
70630 /*! FAST_LINK_MODE - Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for
70631  *    speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs
70632  *    and to link up faster. The default scaling factor can be changed using the
70633  *    DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the
70634  *    TIMER_CTRL_MAX_FUNC_NUM_OFF register. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin
70635  *    to '1'. For more details, see the "Fast Link Simulation Mode" section in the "Integrating the
70636  *    Core with the PHY or Application RTL or Verification IP" chapter of the User Guide. For
70637  *    M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If
70638  *    this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32). Note: This register
70639  *    field is sticky.
70640  */
70641 #define PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK)
70642 
70643 #define PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_MASK   (0xF00U)
70644 #define PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT  (8U)
70645 /*! LINK_RATE - LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky. */
70646 #define PCIE_PORT_LINK_CTRL_OFF_LINK_RATE(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_MASK)
70647 
70648 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_MASK    (0xF000U)
70649 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_SHIFT   (12U)
70650 /*! RSVDP_12 - Reserved for future use. */
70651 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_12(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_MASK)
70652 
70653 #define PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK (0x3F0000U)
70654 #define PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT (16U)
70655 /*! LINK_CAPABLE - Link Mode Enable. Sets the number of lanes in the link that you want to connect
70656  *    to the link partner. When you have unused lanes in your system, then you must change the value
70657  *    in this register to reflect the number of lanes. You must also change the value in the
70658  *    "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more
70659  *    information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing
70660  *    the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 -
70661  *    011111: x16 - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe.
70662  *    Note: This register field is sticky.
70663  */
70664 #define PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK)
70665 
70666 #define PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK (0x1000000U)
70667 #define PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT (24U)
70668 /*! BEACON_ENABLE - BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. */
70669 #define PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK)
70670 
70671 #define PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK (0x2000000U)
70672 #define PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT (25U)
70673 /*! CORRUPT_LCRC_ENABLE - CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. */
70674 #define PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK)
70675 
70676 #define PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK (0x4000000U)
70677 #define PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT (26U)
70678 /*! EXTENDED_SYNCH - EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky. */
70679 #define PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK)
70680 
70681 #define PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK (0x8000000U)
70682 #define PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT (27U)
70683 /*! TRANSMIT_LANE_REVERSALE_ENABLE - TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. */
70684 #define PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK)
70685 
70686 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_MASK    (0xF0000000U)
70687 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_SHIFT   (28U)
70688 /*! RSVDP_28 - Reserved for future use. */
70689 #define PCIE_PORT_LINK_CTRL_OFF_RSVDP_28(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_MASK)
70690 /*! @} */
70691 
70692 /*! @name LANE_SKEW_OFF - Lane Skew Register. */
70693 /*! @{ */
70694 
70695 #define PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_MASK (0xFFFFFFU)
70696 #define PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT (0U)
70697 /*! INSERT_LANE_SKEW - INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky. */
70698 #define PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT)) & PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_MASK)
70699 
70700 #define PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MASK (0x1000000U)
70701 #define PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT (24U)
70702 /*! FLOW_CTRL_DISABLE - Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky. */
70703 #define PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT)) & PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MASK)
70704 
70705 #define PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_MASK  (0x2000000U)
70706 #define PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT (25U)
70707 /*! ACK_NAK_DISABLE - Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky. */
70708 #define PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT)) & PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_MASK)
70709 
70710 #define PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_MASK (0x4000000U)
70711 #define PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_SHIFT (26U)
70712 /*! GEN34_ELASTIC_BUFFER_MODE - Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0:
70713  *    Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode This register bit only affects Gen3
70714  *    or Gen4 operating rate. For Gen1 or Gen2 operating rate the Elasticity Buffer operating mode is
70715  *    always the Nominal Half Full Buffer mode. Note: This register field is sticky.
70716  */
70717 #define PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_SHIFT)) & PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_MASK)
70718 
70719 #define PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MASK (0x78000000U)
70720 #define PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SHIFT (27U)
70721 /*! IMPLEMENT_NUM_LANES - Implementation-specific Number of Lanes. Set the implementation-specific
70722  *    number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes -
70723  *    4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be used when in Loopback Master.
70724  *    The number of lanes programmed must be equal to or less than the valid number of lanes set in
70725  *    LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the
70726  *    LOOPBACK_ENABLE field. The controller will transition from Loopback.Entry to Loopback.Active
70727  *    after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the
70728  *    implementation specific number of lanes configured in this field. Note: This register field is sticky.
70729  */
70730 #define PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SHIFT)) & PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MASK)
70731 
70732 #define PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MASK (0x80000000U)
70733 #define PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT (31U)
70734 /*! DISABLE_LANE_TO_LANE_DESKEW - Disable Lane-to-Lane Deskew. Causes the controller to disable the
70735  *    internal Lane-to-Lane deskew logic. Note: This register field is sticky.
70736  */
70737 #define PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT)) & PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MASK)
70738 /*! @} */
70739 
70740 /*! @name TIMER_CTRL_MAX_FUNC_NUM_OFF - Timer Control and Max Function Number Register. */
70741 /*! @{ */
70742 
70743 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK (0xFFU)
70744 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT (0U)
70745 /*! MAX_FUNC_NUM - Maximum function number that can be used in a request. Configuration requests
70746  *    targeted at function numbers above this value are returned with UR (unsupported request). Note:
70747  *    This register field is sticky.
70748  */
70749 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK)
70750 
70751 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MASK (0x3F00U)
70752 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SHIFT (8U)
70753 /*! RSVDP_8 - Reserved for future use. */
70754 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MASK)
70755 
70756 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK (0x7C000U)
70757 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT (14U)
70758 /*! TIMER_MOD_REPLAY_TIMER - Replay Timer Limit Modifier. Increases the time-out value for the
70759  *    replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock
70760  *    cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more
70761  *    details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed,
70762  *    the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ. For
70763  *    M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock
70764  *    cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed. Note: This register field is sticky.
70765  */
70766 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK)
70767 
70768 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK (0xF80000U)
70769 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT (19U)
70770 /*! TIMER_MOD_ACK_NAK - Ack Latency Timer Modifier. Increases the timer value for the Ack latency
70771  *    timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer
70772  *    value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the
70773  *    ACK_LATENCY_TIMER_OFF register. Note: This register field is sticky.
70774  */
70775 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK)
70776 
70777 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK (0x1F000000U)
70778 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT (24U)
70779 /*! UPDATE_FREQ_TIMER - UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky. */
70780 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK)
70781 
70782 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK (0x60000000U)
70783 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT (29U)
70784 /*! FAST_LINK_SCALING_FACTOR - Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM
70785  *    timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024
70786  *    (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) -
70787  *    3: Scaling Factor is 16 (1ms is 64us) Default is set by the hidden configuration parameter
70788  *    DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'. Not used for M-PCIe. Note: This register
70789  *    field is sticky.
70790  */
70791 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK)
70792 
70793 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MASK (0x80000000U)
70794 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SHIFT (31U)
70795 /*! RSVDP_31 - Reserved for future use. */
70796 #define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MASK)
70797 /*! @} */
70798 
70799 /*! @name SYMBOL_TIMER_FILTER_1_OFF - Symbol Timer Register and Filter Mask 1 Register. */
70800 /*! @{ */
70801 
70802 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK (0x7FFU)
70803 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT (0U)
70804 /*! SKP_INT_VAL - SKP Interval Value. The number of symbol times to wait between transmitting SKP
70805  *    ordered sets. Note that the controller actually waits the number of symbol times in this
70806  *    register plus 1 between transmitting SKP ordered sets. Your application must program this register
70807  *    accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller),
70808  *    then the controller actually transmits SKP ordered sets once every 1537 symbol times. The
70809  *    value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz
70810  *    controller, programming the value programmed to this register should be scaled down by a factor of
70811  *    2 (because one clock tick = two symbol times in this case). Note: This value is not used at
70812  *    Gen3 speed; the skip interval is hardcoded to 370 blocks. For M-PCIe configurations, if the
70813  *    2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed
70814  *    automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NB
70815  *    You need to set this field again if necessary when 2K_PPM_DISABLED is changed. Note: This
70816  *    register field is sticky.
70817  */
70818 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK)
70819 
70820 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK (0x7800U)
70821 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT (11U)
70822 /*! EIDLE_TIMER - EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky. */
70823 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK)
70824 
70825 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK (0x8000U)
70826 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT (15U)
70827 /*! DISABLE_FC_WD_TIMER - Disable FC Watchdog Timer. Note: This register field is sticky. */
70828 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK)
70829 
70830 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK (0xFFFF0000U)
70831 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT (16U)
70832 /*! MASK_RADM_1 - Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error
70833  *    handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies
70834  *    the associated filtering rule and '1' masks the associated filtering rule. [31]:
70835  *    CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For
70836  *    RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For
70837  *    RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO
70838  *    transaction being received [29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor
70839  *    MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message
70840  *    TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this
70841  *    bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit
70842  *    is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs.
70843  *    Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS
70844  *    Invalidate messages to the SII interface regardless of this filter rule setting. The controller
70845  *    passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for
70846  *    the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised
70847  *    with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors
70848  *    - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW. [27]:
70849  *    CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be
70850  *    passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a
70851  *    violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for
70852  *    completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation
70853  *    results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca
70854  *    - 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic
70855  *    Class match for completions; a violation results in a malformed TLP error, and possibly AER of
70856  *    unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions [23]:
70857  *    CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in
70858  *    cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function
70859  *    match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for
70860  *    completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca
70861  *    - 1: Mask Req. Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag
70862  *    Error Rules for completions; a violation result in cpl_abort, and possibly AER of
70863  *    unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions [20]:
70864  *    CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read
70865  *    TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1
70866  *    TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC -
70867  *    When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config
70868  *    requests if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0:
70869  *    Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS -
70870  *    0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native
70871  *    controller always passes poisoned completions to your application except when you are using
70872  *    the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as
70873  *    UR - 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky.
70874  */
70875 #define PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK)
70876 /*! @} */
70877 
70878 /*! @name FILTER_MASK_2_OFF - Filter Mask 2 Register. */
70879 /*! @{ */
70880 
70881 #define PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_MASK  (0xFFFFFFFFU)
70882 #define PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT (0U)
70883 /*! MASK_RADM_2 - Filter Mask 2. This field modifies the RADM filtering and error handling rules.
70884  *    For more details, see the "Receive Filtering" section. In each case, '0' applies the associated
70885  *    filtering rule and '1' masks the associated filtering rule. [31:8]: Reserved [7]:
70886  *    CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is
70887  *    ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the
70888  *    SYMBOL_TIMER_FILTER_1_OFF register is set to '1'. [6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if
70889  *    CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE [5]: CX_FLT_UNMASK_UR_POIS_TRGT0 -
70890  *    0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask
70891  *    CX_FLT_MASK_UR_POIS with TRGT0 destination [4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass
70892  *    through - 1: Drop LN Messages silently [3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller
70893  *    Filter to handle flush request - 1: Enable controller Filter to handle flush request [2]:
70894  *    CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP
70895  *    abort for unexpected completion [1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped
70896  *    silently - 1: Vendor MSG Type 1 not dropped [0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0
70897  *    dropped with UR error reporting - 1: Vendor MSG Type 0 not dropped Note: This register field is
70898  *    sticky.
70899  */
70900 #define PCIE_FILTER_MASK_2_OFF_MASK_RADM_2(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT)) & PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_MASK)
70901 /*! @} */
70902 
70903 /*! @name AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF - AMBA Multiple Outbound Decomposed NP SubRequests Control Register. */
70904 /*! @{ */
70905 
70906 #define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MASK (0x1U)
70907 #define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SHIFT (0U)
70908 /*! OB_RD_SPLIT_BURST_EN - Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when
70909  *    set to "0" disables the possibility of having multiple outstanding non-posted requests that were
70910  *    derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge
70911  *    Ordering" in the AXI chapter of the Databook. You should not clear this register unless your
70912  *    application master is requesting an amount of read data greater than Max_Read_Request_Size, and
70913  *    the remote device (or switch) is reordering completions that have different tags. Note: The
70914  *    access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is
70915  *    sticky.
70916  */
70917 #define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SHIFT)) & PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MASK)
70918 
70919 #define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MASK (0xFFFFFFFEU)
70920 #define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SHIFT (1U)
70921 /*! RSVDP_1 - Reserved for future use. */
70922 #define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SHIFT)) & PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MASK)
70923 /*! @} */
70924 
70925 /*! @name PL_DEBUG0_OFF - Debug Register 0 */
70926 /*! @{ */
70927 
70928 #define PCIE_PL_DEBUG0_OFF_DEB_REG_0_MASK        (0xFFFFFFFFU)
70929 #define PCIE_PL_DEBUG0_OFF_DEB_REG_0_SHIFT       (0U)
70930 /*! DEB_REG_0 - The value on cxpl_debug_info[31:0]. */
70931 #define PCIE_PL_DEBUG0_OFF_DEB_REG_0(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PL_DEBUG0_OFF_DEB_REG_0_SHIFT)) & PCIE_PL_DEBUG0_OFF_DEB_REG_0_MASK)
70932 /*! @} */
70933 
70934 /*! @name PL_DEBUG1_OFF - Debug Register 1 */
70935 /*! @{ */
70936 
70937 #define PCIE_PL_DEBUG1_OFF_DEB_REG_1_MASK        (0xFFFFFFFFU)
70938 #define PCIE_PL_DEBUG1_OFF_DEB_REG_1_SHIFT       (0U)
70939 /*! DEB_REG_1 - The value on cxpl_debug_info[63:32]. */
70940 #define PCIE_PL_DEBUG1_OFF_DEB_REG_1(x)          (((uint32_t)(((uint32_t)(x)) << PCIE_PL_DEBUG1_OFF_DEB_REG_1_SHIFT)) & PCIE_PL_DEBUG1_OFF_DEB_REG_1_MASK)
70941 /*! @} */
70942 
70943 /*! @name TX_P_FC_CREDIT_STATUS_OFF - Transmit Posted FC Credit Status */
70944 /*! @{ */
70945 
70946 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK (0xFFFU)
70947 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT (0U)
70948 /*! TX_P_DATA_FC_CREDIT - Transmit Posted Data FC Credits. The posted Data credits advertised by the
70949  *    receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends
70950  *    on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts,
70951  *    xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are
70952  *    infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
70953  */
70954 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT)) & PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK)
70955 
70956 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK (0xFF000U)
70957 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT (12U)
70958 /*! TX_P_HEADER_FC_CREDIT - Transmit Posted Header FC Credits. The posted Header credits advertised
70959  *    by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value
70960  *    depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts,
70961  *    xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are
70962  *    infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
70963  */
70964 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT)) & PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK)
70965 
70966 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK (0xFFF00000U)
70967 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT (20U)
70968 /*! RSVDP_20 - Reserved for future use. */
70969 #define PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT)) & PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK)
70970 /*! @} */
70971 
70972 /*! @name TX_NP_FC_CREDIT_STATUS_OFF - Transmit Non-Posted FC Credit Status */
70973 /*! @{ */
70974 
70975 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK (0xFFFU)
70976 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT (0U)
70977 /*! TX_NP_DATA_FC_CREDIT - Transmit Non-Posted Data FC Credits. The non-posted Data credits
70978  *    advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default
70979  *    value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts,
70980  *    xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data)
70981  *    are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
70982  */
70983 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT)) & PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK)
70984 
70985 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK (0xFF000U)
70986 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT (12U)
70987 /*! TX_NP_HEADER_FC_CREDIT - Transmit Non-Posted Header FC Credits. The non-posted Header credits
70988  *    advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.
70989  *    Default value depends on the number of advertised credits for header and data [12'b0,
70990  *    xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and
70991  *    data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
70992  */
70993 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT)) & PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK)
70994 
70995 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK (0xFFF00000U)
70996 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT (20U)
70997 /*! RSVDP_20 - Reserved for future use. */
70998 #define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT)) & PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK)
70999 /*! @} */
71000 
71001 /*! @name TX_CPL_FC_CREDIT_STATUS_OFF - Transmit Completion FC Credit Status */
71002 /*! @{ */
71003 
71004 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK (0xFFFU)
71005 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT (0U)
71006 /*! TX_CPL_DATA_FC_CREDIT - Transmit Completion Data FC Credits. The Completion Data credits
71007  *    advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default
71008  *    value depends on the number of advertised credits for header and data [12'b0,
71009  *    xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and
71010  *    data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
71011  */
71012 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT)) & PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK)
71013 
71014 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK (0xFF000U)
71015 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT (12U)
71016 /*! TX_CPL_HEADER_FC_CREDIT - Transmit Completion Header FC Credits. The Completion Header credits
71017  *    advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.
71018  *    Default value depends on the number of advertised credits for header and data [12'b0,
71019  *    xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header
71020  *    and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
71021  */
71022 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT)) & PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK)
71023 
71024 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK (0xFFF00000U)
71025 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT (20U)
71026 /*! RSVDP_20 - Reserved for future use. */
71027 #define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT)) & PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK)
71028 /*! @} */
71029 
71030 /*! @name QUEUE_STATUS_OFF - Queue Status */
71031 /*! @{ */
71032 
71033 #define PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK (0x1U)
71034 #define PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT (0U)
71035 /*! RX_TLP_FC_CREDIT_NON_RETURN - Received TLP FC Credits Not Returned. Indicates that the
71036  *    controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for
71037  *    that TLP have been restored by the receiver at the other end of the link.
71038  */
71039 #define PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK)
71040 
71041 #define PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK (0x2U)
71042 #define PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT (1U)
71043 /*! TX_RETRY_BUFFER_NE - Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer. */
71044 #define PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT)) & PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK)
71045 
71046 #define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK (0x4U)
71047 #define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT (2U)
71048 /*! RX_QUEUE_NON_EMPTY - Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers. */
71049 #define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK)
71050 
71051 #define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK (0x8U)
71052 #define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT (3U)
71053 /*! RX_QUEUE_OVERFLOW - Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue. */
71054 #define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK)
71055 
71056 #define PCIE_QUEUE_STATUS_OFF_RSVDP_4_MASK       (0x1FF0U)
71057 #define PCIE_QUEUE_STATUS_OFF_RSVDP_4_SHIFT      (4U)
71058 /*! RSVDP_4 - Reserved for future use. */
71059 #define PCIE_QUEUE_STATUS_OFF_RSVDP_4(x)         (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RSVDP_4_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RSVDP_4_MASK)
71060 
71061 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK (0x2000U)
71062 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT (13U)
71063 /*! RX_SERIALIZATION_Q_NON_EMPTY - Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue. */
71064 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK)
71065 
71066 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_MASK (0x4000U)
71067 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_SHIFT (14U)
71068 /*! RX_SERIALIZATION_Q_WRITE_ERR - Receive Serialization Queue Write Error. Indicates insufficient
71069  *    buffer space available to write to the serialization queue.
71070  */
71071 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_MASK)
71072 
71073 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_MASK (0x8000U)
71074 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_SHIFT (15U)
71075 /*! RX_SERIALIZATION_Q_READ_ERR - Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP. */
71076 #define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_MASK)
71077 
71078 #define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK (0x1FFF0000U)
71079 #define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT (16U)
71080 /*! TIMER_MOD_FLOW_CONTROL - FC Latency Timer Override Value. When you set the "FC Latency Timer
71081  *    Override Enable" in this register, the value in this field will override the FC latency timer
71082  *    value that the controller calculates according to the PCIe specification. For more details, see
71083  *    "Flow Control". Note: This register field is sticky.
71084  */
71085 #define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT)) & PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK)
71086 
71087 #define PCIE_QUEUE_STATUS_OFF_RSVDP_29_MASK      (0x60000000U)
71088 #define PCIE_QUEUE_STATUS_OFF_RSVDP_29_SHIFT     (29U)
71089 /*! RSVDP_29 - Reserved for future use. */
71090 #define PCIE_QUEUE_STATUS_OFF_RSVDP_29(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RSVDP_29_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RSVDP_29_MASK)
71091 
71092 #define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK (0x80000000U)
71093 #define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT (31U)
71094 /*! TIMER_MOD_FLOW_CONTROL_EN - FC Latency Timer Override Enable. When this bit is set, the value
71095  *    from the "FC Latency Timer Override Value" field in this register will override the FC latency
71096  *    timer value that the controller calculates according to the PCIe specification. Note: This
71097  *    register field is sticky.
71098  */
71099 #define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT)) & PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK)
71100 /*! @} */
71101 
71102 /*! @name VC_TX_ARBI_1_OFF - VC Transmit Arbitration Register 1 */
71103 /*! @{ */
71104 
71105 #define PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK (0xFFU)
71106 #define PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT (0U)
71107 /*! WRR_WEIGHT_VC_0 - WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R */
71108 #define PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT)) & PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK)
71109 /*! @} */
71110 
71111 /*! @name VC0_P_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Posted Receive Queue Control. */
71112 /*! @{ */
71113 
71114 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK (0xFFFU)
71115 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT (0U)
71116 /*! VC0_P_DATA_CREDIT - VC0 Posted Data Credits. The number of initial posted data credits for VC0,
71117  *    used only in the segmented-buffer configuration. Note: The access attributes of this field are
71118  *    as follows: - Dbi: R (sticky) Note: This register field is sticky.
71119  */
71120 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK)
71121 
71122 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK (0xFF000U)
71123 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT (12U)
71124 /*! VC0_P_HEADER_CREDIT - VC0 Posted Header Credits. The number of initial posted header credits for
71125  *    VC0, used only in the segmented-buffer configuration. Note: The access attributes of this
71126  *    field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
71127  */
71128 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK)
71129 
71130 #define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK  (0x100000U)
71131 #define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT (20U)
71132 /*! RESERVED4 - Reserved. Note: This register field is sticky. */
71133 #define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK)
71134 
71135 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK (0xE00000U)
71136 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT (21U)
71137 /*! VC0_P_TLP_Q_MODE - Reserved. Note: This register field is sticky. */
71138 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK)
71139 
71140 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK (0x3000000U)
71141 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT (24U)
71142 /*! VC0_P_HDR_SCALE - VC0 Scale Posted Header Credites. Note: This register field is sticky. */
71143 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK)
71144 
71145 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK (0xC000000U)
71146 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT (26U)
71147 /*! VC0_P_DATA_SCALE - VC0 Scale Posted Data Credites. Note: This register field is sticky. */
71148 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK)
71149 
71150 #define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK  (0x30000000U)
71151 #define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT (28U)
71152 /*! RESERVED5 - Reserved. Note: This register field is sticky. */
71153 #define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK)
71154 
71155 #define PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK (0x40000000U)
71156 #define PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT (30U)
71157 /*! TLP_TYPE_ORDERING_VC0 - TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0
71158  *    receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules
71159  *    (recommended) - 0: Strict ordering: posted, completion, then non-posted Note: This register field
71160  *    is sticky.
71161  */
71162 #define PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK)
71163 
71164 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK (0x80000000U)
71165 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT (31U)
71166 /*! VC_ORDERING_RX_Q - VC Ordering for Receive Queues. Determines the VC ordering rule for the
71167  *    receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher
71168  *    numbered VCs have higher priority - 0: Round robin Note: This register field is sticky.
71169  */
71170 #define PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK)
71171 /*! @} */
71172 
71173 /*! @name VC0_NP_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Non-Posted Receive Queue Control. */
71174 /*! @{ */
71175 
71176 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK (0xFFFU)
71177 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT (0U)
71178 /*! VC0_NP_DATA_CREDIT - VC0 Non-Posted Data Credits. The number of initial non-posted data credits
71179  *    for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this
71180  *    field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
71181  */
71182 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK)
71183 
71184 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK (0xFF000U)
71185 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT (12U)
71186 /*! VC0_NP_HEADER_CREDIT - VC0 Non-Posted Header Credits. The number of initial non-posted header
71187  *    credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of
71188  *    this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
71189  */
71190 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK)
71191 
71192 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK (0x100000U)
71193 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT (20U)
71194 /*! RESERVED6 - Reserved. Note: This register field is sticky. */
71195 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK)
71196 
71197 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK (0xE00000U)
71198 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT (21U)
71199 /*! VC0_NP_TLP_Q_MODE - Reserved. Note: This register field is sticky. */
71200 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK)
71201 
71202 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK (0x3000000U)
71203 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT (24U)
71204 /*! VC0_NP_HDR_SCALE - VC0 Scale Non-Posted Header Credites. Note: This register field is sticky. */
71205 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK)
71206 
71207 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK (0xC000000U)
71208 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT (26U)
71209 /*! VC0_NP_DATA_SCALE - VC0 Scale Non-Posted Data Credites. Note: This register field is sticky. */
71210 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK)
71211 
71212 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK (0xF0000000U)
71213 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT (28U)
71214 /*! RESERVED7 - Reserved. Note: This register field is sticky. */
71215 #define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK)
71216 /*! @} */
71217 
71218 /*! @name VC0_CPL_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Completion Receive Queue Control. */
71219 /*! @{ */
71220 
71221 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK (0xFFFU)
71222 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT (0U)
71223 /*! VC0_CPL_DATA_CREDIT - VC0 Completion Data Credits. The number of initial Completion data credits
71224  *    for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this
71225  *    field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
71226  */
71227 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK)
71228 
71229 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK (0xFF000U)
71230 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT (12U)
71231 /*! VC0_CPL_HEADER_CREDIT - VC0 Completion Header Credits. The number of initial Completion header
71232  *    credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes
71233  *    of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
71234  */
71235 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK)
71236 
71237 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK (0x100000U)
71238 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT (20U)
71239 /*! RESERVED8 - Reserved. Note: This register field is sticky. */
71240 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK)
71241 
71242 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK (0xE00000U)
71243 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT (21U)
71244 /*! VC0_CPL_TLP_Q_MODE - Reserved. Note: This register field is sticky. */
71245 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK)
71246 
71247 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK (0x3000000U)
71248 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT (24U)
71249 /*! VC0_CPL_HDR_SCALE - VC0 Scale CPL Header Credites. Note: This register field is sticky. */
71250 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK)
71251 
71252 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK (0xC000000U)
71253 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT (26U)
71254 /*! VC0_CPL_DATA_SCALE - VC0 Scale CPL Data Credites. Note: This register field is sticky. */
71255 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK)
71256 
71257 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK (0xF0000000U)
71258 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT (28U)
71259 /*! RESERVED9 - Reserved. Note: This register field is sticky. */
71260 #define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK)
71261 /*! @} */
71262 
71263 /*! @name GEN2_CTRL_OFF - Link Width and Speed Change Control Register. */
71264 /*! @{ */
71265 
71266 #define PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK (0xFFU)
71267 #define PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT (0U)
71268 /*! FAST_TRAINING_SEQ - Sets the Number of Fast Training Sequences (N_FTS) that the controller
71269  *    advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link
71270  *    partner about the PHY's ability to recover synchronization after a low power state. The number
71271  *    should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to
71272  *    go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for
71273  *    M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note:
71274  *    This register field is sticky.
71275  */
71276 #define PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT)) & PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK)
71277 
71278 #define PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_MASK     (0x1F00U)
71279 #define PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT    (8U)
71280 /*! NUM_OF_LANES - Predetermined Number of Lanes. Defines the number of lanes which are connected
71281  *    and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that
71282  *    detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in
71283  *    Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or
71284  *    broken lane during the Detect Substate. However, it is also possible that such a lane might also
71285  *    fail to exit Electrical Idle and therefore prevent a valid link from being configured. This
71286  *    value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI
71287  *    Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes
71288  *    - 0x03: 3 lanes - .. When you have unused lanes in your system, then you must change the
71289  *    value in this register to reflect the number of lanes. You must also change the value in the "Link
71290  *    Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as
71291  *    the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then
71292  *    you must reduce the value in this register. For more information, see "How to Tie Off Unused
71293  *    Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."
71294  *    This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are
71295  *    as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
71296  */
71297 #define PCIE_GEN2_CTRL_OFF_NUM_OF_LANES(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT)) & PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_MASK)
71298 
71299 #define PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_MASK     (0xE000U)
71300 #define PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT    (13U)
71301 /*! PRE_DET_LANE - Predetermined Lane for Auto Flip. This field defines which physical lane is
71302  *    connected to logical Lane0 by the flip operation performed in Detect. Allowed values are: - 3'b000:
71303  *    Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1,
71304  *    depending on which lane is detected - 3'b001: Connect logical Lane0 to physical lane 1 -
71305  *    3'b010: Connect logical Lane0 to physical lane 3 - 3'b011: Connect logical Lane0 to physical lane 7
71306  *    - 3'b100: Connect logical Lane0 to physical lane 15 This field is used to restrict the
71307  *    receiver detect procedure to a particular lane when the default detect and polling procedure
71308  *    performed on all lanes cannot be successful. A notable example of when it is useful to program this
71309  *    field to a value different from the default, is when a lane is asymmetrically broken, that is,
71310  *    it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.
71311  *    Note: This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this
71312  *    field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
71313  */
71314 #define PCIE_GEN2_CTRL_OFF_PRE_DET_LANE(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT)) & PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_MASK)
71315 
71316 #define PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK (0x10000U)
71317 #define PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT (16U)
71318 /*! AUTO_LANE_FLIP_CTRL_EN - Enable Auto flipping of the lanes. You must set the
71319  *    CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For
71320  *    more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed
71321  *    to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
71322  *    (sticky) Note: This register field is sticky.
71323  */
71324 #define PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT)) & PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK)
71325 
71326 #define PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK (0x20000U)
71327 #define PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT (17U)
71328 /*! DIRECT_SPEED_CHANGE - Directed Speed Change. Writing "1" to this field instructs the LTSSM to
71329  *    initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the
71330  *    speed change occurs, the controller will clear the contents of this field; and a read to this
71331  *    field by your software will return a "0". To manually initiate the speed change: - Write to
71332  *    LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this
71333  *    field - Assert this field If you set the default of this field using the
71334  *    DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link
71335  *    up, and the controller clears the contents of this field. If you want to prevent this
71336  *    automatic speed change, then write a lower speed value to the Target Link Speed field of the Link
71337  *    Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI
71338  *    before link up. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes
71339  *    of this field are as follows: - Dbi: R/W
71340  */
71341 #define PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT)) & PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK)
71342 
71343 #define PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK (0x40000U)
71344 #define PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT (18U)
71345 /*! CONFIG_PHY_TX_CHANGE - Config PHY Tx Swing. Controls the PHY transmitter voltage swing level.
71346  *    The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing -
71347  *    1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of
71348  *    this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
71349  */
71350 #define PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT)) & PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK)
71351 
71352 #define PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK (0x80000U)
71353 #define PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT (19U)
71354 /*! CONFIG_TX_COMP_RX - Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit
71355  *    TS ordered sets with the compliance receive bit assert (equal to "1"). This field is reserved
71356  *    (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
71357  *    (sticky) Note: This register field is sticky.
71358  */
71359 #define PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT)) & PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK)
71360 
71361 #define PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK   (0x100000U)
71362 #define PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT  (20U)
71363 /*! SEL_DEEMPHASIS - Used to set the de-emphasis level for upstream ports. This bit selects the
71364  *    level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed
71365  *    to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
71366  *    (sticky) Note: This register field is sticky.
71367  */
71368 #define PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT)) & PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK)
71369 
71370 #define PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK (0x200000U)
71371 #define PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT (21U)
71372 /*! GEN1_EI_INFERENCE - Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine
71373  *    inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1
71374  *    speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the
71375  *    PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of
71376  *    corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just
71377  *    detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use
71378  *    RxValid signal to infer Electrical Idle Note: This register field is sticky.
71379  */
71380 #define PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT)) & PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK)
71381 
71382 #define PCIE_GEN2_CTRL_OFF_RSVDP_22_MASK         (0xFFC00000U)
71383 #define PCIE_GEN2_CTRL_OFF_RSVDP_22_SHIFT        (22U)
71384 /*! RSVDP_22 - Reserved for future use. */
71385 #define PCIE_GEN2_CTRL_OFF_RSVDP_22(x)           (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_RSVDP_22_SHIFT)) & PCIE_GEN2_CTRL_OFF_RSVDP_22_MASK)
71386 /*! @} */
71387 
71388 /*! @name PHY_STATUS_OFF - PHY Status Register. */
71389 /*! @{ */
71390 
71391 #define PCIE_PHY_STATUS_OFF_PHY_STATUS_MASK      (0xFFFFFFFFU)
71392 #define PCIE_PHY_STATUS_OFF_PHY_STATUS_SHIFT     (0U)
71393 /*! PHY_STATUS - PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO
71394  *    register reflecting the values on the static phy_cfg_status input signals. The usage is left
71395  *    completely to the user and does not in any way influence controller functionality. You can use it
71396  *    for any static sideband status signalling requirements that you have for your PHY. This field
71397  *    is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
71398  */
71399 #define PCIE_PHY_STATUS_OFF_PHY_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_STATUS_OFF_PHY_STATUS_SHIFT)) & PCIE_PHY_STATUS_OFF_PHY_STATUS_MASK)
71400 /*! @} */
71401 
71402 /*! @name PHY_CONTROL_OFF - PHY Control Register. */
71403 /*! @{ */
71404 
71405 #define PCIE_PHY_CONTROL_OFF_PHY_CONTROL_MASK    (0xFFFFFFFFU)
71406 #define PCIE_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT   (0U)
71407 /*! PHY_CONTROL - PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO
71408  *    register driving the values on the static cfg_phy_control output signals. The usage is left
71409  *    completely to the user and does not in any way influence controller functionality. You can use it for
71410  *    any static sideband control signalling requirements that you have for your PHY. This field is
71411  *    reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
71412  */
71413 #define PCIE_PHY_CONTROL_OFF_PHY_CONTROL(x)      (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT)) & PCIE_PHY_CONTROL_OFF_PHY_CONTROL_MASK)
71414 /*! @} */
71415 
71416 /*! @name TRGT_MAP_CTRL_OFF - Programmable Target Map Control Register. */
71417 /*! @{ */
71418 
71419 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK (0x3FU)
71420 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT (0U)
71421 /*! TARGET_MAP_PF - Target Values for each BAR on the PF Function selected by the index number. This
71422  *    register does not respect the Byte Enable setting. any write will affect all register bits.
71423  */
71424 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK)
71425 
71426 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK (0x40U)
71427 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT (6U)
71428 /*! TARGET_MAP_ROM - Target Value for the ROM page of the PF Function selected by the index number.
71429  *    This register does not respect the Byte Enable setting. any write will affect all register
71430  *    bits.
71431  */
71432 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK)
71433 
71434 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK (0xE000U)
71435 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT (13U)
71436 /*! TARGET_MAP_RESERVED_13_15 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R (sticky) */
71437 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK)
71438 
71439 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK (0x1F0000U)
71440 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT (16U)
71441 /*! TARGET_MAP_INDEX - The number of the PF Function on which the Target Values are set. This
71442  *    register does not respect the Byte Enable setting. any write will affect all register bits.
71443  */
71444 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK)
71445 
71446 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK (0xFFE00000U)
71447 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT (21U)
71448 /*! TARGET_MAP_RESERVED_21_31 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R (sticky) */
71449 #define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK)
71450 /*! @} */
71451 
71452 /*! @name MSI_CTRL_ADDR_OFF - Integrated MSI Reception Module (iMRM) Address Register. */
71453 /*! @{ */
71454 
71455 #define PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MASK (0xFFFFFFFFU)
71456 #define PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SHIFT (0U)
71457 /*! MSI_CTRL_ADDR - Integrated MSI Reception Module Address. System specified address for MSI memory
71458  *    write transaction termination. Within the AXI Bridge, every received Memory Write request is
71459  *    examined to see if it targets the MSI Address that has been specified in this register; and
71460  *    also to see if it satisfies the definition of an MSI interrupt request. When these conditions
71461  *    are satisfied the Memory Write request is marked as an MSI request. Note: This register field is
71462  *    sticky.
71463  */
71464 #define PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SHIFT)) & PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MASK)
71465 /*! @} */
71466 
71467 /*! @name MSI_CTRL_UPPER_ADDR_OFF - Integrated MSI Reception Module Upper Address Register. */
71468 /*! @{ */
71469 
71470 #define PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MASK (0xFFFFFFFFU)
71471 #define PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SHIFT (0U)
71472 /*! MSI_CTRL_UPPER_ADDR - Integrated MSI Reception Module Upper Address. System specified upper
71473  *    address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI
71474  *    address. Note: This register field is sticky.
71475  */
71476 #define PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SHIFT)) & PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MASK)
71477 /*! @} */
71478 
71479 /*! @name MSI_CTRL_INT_0_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71480 /*! @{ */
71481 
71482 #define PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MASK (0xFFFFFFFFU)
71483 #define PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SHIFT (0U)
71484 /*! MSI_CTRL_INT_0_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71485  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71486  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71487  *    is sticky.
71488  */
71489 #define PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SHIFT)) & PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MASK)
71490 /*! @} */
71491 
71492 /*! @name MSI_CTRL_INT_0_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71493 /*! @{ */
71494 
71495 #define PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MASK (0xFFFFFFFFU)
71496 #define PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SHIFT (0U)
71497 /*! MSI_CTRL_INT_0_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71498  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71499  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71500  *    Interrupt Vector. Note: This register field is sticky.
71501  */
71502 #define PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MASK)
71503 /*! @} */
71504 
71505 /*! @name MSI_CTRL_INT_0_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71506 /*! @{ */
71507 
71508 #define PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MASK (0xFFFFFFFFU)
71509 #define PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SHIFT (0U)
71510 /*! MSI_CTRL_INT_0_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71511  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71512  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71513  *    corresponds to a single MSI Interrupt Vector.
71514  */
71515 #define PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MASK)
71516 /*! @} */
71517 
71518 /*! @name MSI_CTRL_INT_1_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71519 /*! @{ */
71520 
71521 #define PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MASK (0xFFFFFFFFU)
71522 #define PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SHIFT (0U)
71523 /*! MSI_CTRL_INT_1_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71524  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71525  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71526  *    is sticky.
71527  */
71528 #define PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SHIFT)) & PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MASK)
71529 /*! @} */
71530 
71531 /*! @name MSI_CTRL_INT_1_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71532 /*! @{ */
71533 
71534 #define PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MASK (0xFFFFFFFFU)
71535 #define PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SHIFT (0U)
71536 /*! MSI_CTRL_INT_1_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71537  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71538  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71539  *    Interrupt Vector. Note: This register field is sticky.
71540  */
71541 #define PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MASK)
71542 /*! @} */
71543 
71544 /*! @name MSI_CTRL_INT_1_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71545 /*! @{ */
71546 
71547 #define PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MASK (0xFFFFFFFFU)
71548 #define PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SHIFT (0U)
71549 /*! MSI_CTRL_INT_1_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71550  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71551  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71552  *    corresponds to a single MSI Interrupt Vector.
71553  */
71554 #define PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MASK)
71555 /*! @} */
71556 
71557 /*! @name MSI_CTRL_INT_2_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71558 /*! @{ */
71559 
71560 #define PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MASK (0xFFFFFFFFU)
71561 #define PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SHIFT (0U)
71562 /*! MSI_CTRL_INT_2_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71563  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71564  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71565  *    is sticky.
71566  */
71567 #define PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SHIFT)) & PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MASK)
71568 /*! @} */
71569 
71570 /*! @name MSI_CTRL_INT_2_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71571 /*! @{ */
71572 
71573 #define PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MASK (0xFFFFFFFFU)
71574 #define PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SHIFT (0U)
71575 /*! MSI_CTRL_INT_2_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71576  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71577  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71578  *    Interrupt Vector. Note: This register field is sticky.
71579  */
71580 #define PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MASK)
71581 /*! @} */
71582 
71583 /*! @name MSI_CTRL_INT_2_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71584 /*! @{ */
71585 
71586 #define PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MASK (0xFFFFFFFFU)
71587 #define PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SHIFT (0U)
71588 /*! MSI_CTRL_INT_2_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71589  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71590  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71591  *    corresponds to a single MSI Interrupt Vector.
71592  */
71593 #define PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MASK)
71594 /*! @} */
71595 
71596 /*! @name MSI_CTRL_INT_3_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71597 /*! @{ */
71598 
71599 #define PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MASK (0xFFFFFFFFU)
71600 #define PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SHIFT (0U)
71601 /*! MSI_CTRL_INT_3_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71602  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71603  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71604  *    is sticky.
71605  */
71606 #define PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SHIFT)) & PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MASK)
71607 /*! @} */
71608 
71609 /*! @name MSI_CTRL_INT_3_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71610 /*! @{ */
71611 
71612 #define PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MASK (0xFFFFFFFFU)
71613 #define PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SHIFT (0U)
71614 /*! MSI_CTRL_INT_3_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71615  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71616  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71617  *    Interrupt Vector. Note: This register field is sticky.
71618  */
71619 #define PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MASK)
71620 /*! @} */
71621 
71622 /*! @name MSI_CTRL_INT_3_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71623 /*! @{ */
71624 
71625 #define PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MASK (0xFFFFFFFFU)
71626 #define PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SHIFT (0U)
71627 /*! MSI_CTRL_INT_3_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71628  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71629  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71630  *    corresponds to a single MSI Interrupt Vector.
71631  */
71632 #define PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MASK)
71633 /*! @} */
71634 
71635 /*! @name MSI_CTRL_INT_4_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71636 /*! @{ */
71637 
71638 #define PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MASK (0xFFFFFFFFU)
71639 #define PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SHIFT (0U)
71640 /*! MSI_CTRL_INT_4_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71641  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71642  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71643  *    is sticky.
71644  */
71645 #define PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SHIFT)) & PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MASK)
71646 /*! @} */
71647 
71648 /*! @name MSI_CTRL_INT_4_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71649 /*! @{ */
71650 
71651 #define PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MASK (0xFFFFFFFFU)
71652 #define PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SHIFT (0U)
71653 /*! MSI_CTRL_INT_4_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71654  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71655  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71656  *    Interrupt Vector. Note: This register field is sticky.
71657  */
71658 #define PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MASK)
71659 /*! @} */
71660 
71661 /*! @name MSI_CTRL_INT_4_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71662 /*! @{ */
71663 
71664 #define PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MASK (0xFFFFFFFFU)
71665 #define PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SHIFT (0U)
71666 /*! MSI_CTRL_INT_4_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71667  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71668  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71669  *    corresponds to a single MSI Interrupt Vector.
71670  */
71671 #define PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MASK)
71672 /*! @} */
71673 
71674 /*! @name MSI_CTRL_INT_5_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71675 /*! @{ */
71676 
71677 #define PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MASK (0xFFFFFFFFU)
71678 #define PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SHIFT (0U)
71679 /*! MSI_CTRL_INT_5_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71680  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71681  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71682  *    is sticky.
71683  */
71684 #define PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SHIFT)) & PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MASK)
71685 /*! @} */
71686 
71687 /*! @name MSI_CTRL_INT_5_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71688 /*! @{ */
71689 
71690 #define PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MASK (0xFFFFFFFFU)
71691 #define PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SHIFT (0U)
71692 /*! MSI_CTRL_INT_5_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71693  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71694  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71695  *    Interrupt Vector. Note: This register field is sticky.
71696  */
71697 #define PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MASK)
71698 /*! @} */
71699 
71700 /*! @name MSI_CTRL_INT_5_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71701 /*! @{ */
71702 
71703 #define PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MASK (0xFFFFFFFFU)
71704 #define PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SHIFT (0U)
71705 /*! MSI_CTRL_INT_5_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71706  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71707  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71708  *    corresponds to a single MSI Interrupt Vector.
71709  */
71710 #define PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MASK)
71711 /*! @} */
71712 
71713 /*! @name MSI_CTRL_INT_6_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71714 /*! @{ */
71715 
71716 #define PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MASK (0xFFFFFFFFU)
71717 #define PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SHIFT (0U)
71718 /*! MSI_CTRL_INT_6_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71719  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71720  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71721  *    is sticky.
71722  */
71723 #define PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SHIFT)) & PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MASK)
71724 /*! @} */
71725 
71726 /*! @name MSI_CTRL_INT_6_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71727 /*! @{ */
71728 
71729 #define PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MASK (0xFFFFFFFFU)
71730 #define PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SHIFT (0U)
71731 /*! MSI_CTRL_INT_6_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71732  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71733  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71734  *    Interrupt Vector. Note: This register field is sticky.
71735  */
71736 #define PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MASK)
71737 /*! @} */
71738 
71739 /*! @name MSI_CTRL_INT_6_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71740 /*! @{ */
71741 
71742 #define PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MASK (0xFFFFFFFFU)
71743 #define PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SHIFT (0U)
71744 /*! MSI_CTRL_INT_6_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71745  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71746  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71747  *    corresponds to a single MSI Interrupt Vector.
71748  */
71749 #define PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MASK)
71750 /*! @} */
71751 
71752 /*! @name MSI_CTRL_INT_7_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
71753 /*! @{ */
71754 
71755 #define PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MASK (0xFFFFFFFFU)
71756 #define PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SHIFT (0U)
71757 /*! MSI_CTRL_INT_7_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
71758  *    is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
71759  *    status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
71760  *    is sticky.
71761  */
71762 #define PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SHIFT)) & PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MASK)
71763 /*! @} */
71764 
71765 /*! @name MSI_CTRL_INT_7_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
71766 /*! @{ */
71767 
71768 #define PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MASK (0xFFFFFFFFU)
71769 #define PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SHIFT (0U)
71770 /*! MSI_CTRL_INT_7_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
71771  *    is received for a masked interrupt, the corresponding status bit gets set in the interrupt
71772  *    status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
71773  *    Interrupt Vector. Note: This register field is sticky.
71774  */
71775 #define PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MASK)
71776 /*! @} */
71777 
71778 /*! @name MSI_CTRL_INT_7_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
71779 /*! @{ */
71780 
71781 #define PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MASK (0xFFFFFFFFU)
71782 #define PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SHIFT (0U)
71783 /*! MSI_CTRL_INT_7_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
71784  *    this register is set. The decoding of the data payload of the MSI Memory Write request determines
71785  *    which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
71786  *    corresponds to a single MSI Interrupt Vector.
71787  */
71788 #define PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MASK)
71789 /*! @} */
71790 
71791 /*! @name MSI_GPIO_IO_OFF - Integrated MSI Reception Module General Purpose IO Register. */
71792 /*! @{ */
71793 
71794 #define PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MASK   (0xFFFFFFFFU)
71795 #define PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SHIFT  (0U)
71796 /*! MSI_GPIO_REG - MSI GPIO Register. The contents of this register drives the top-level GPIO
71797  *    msi_ctrl_io[31:0] Note: This register field is sticky.
71798  */
71799 #define PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SHIFT)) & PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MASK)
71800 /*! @} */
71801 
71802 /*! @name CLOCK_GATING_CTRL_OFF - RADM clock gating enable control register. */
71803 /*! @{ */
71804 
71805 #define PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK (0x1U)
71806 #define PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT (0U)
71807 /*! RADM_CLK_GATING_EN - Enable Radm clock gating feature. - 0: Disable - 1: Enable(default) */
71808 #define PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT)) & PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK)
71809 
71810 #define PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_MASK  (0xFFFFFFFEU)
71811 #define PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_SHIFT (1U)
71812 /*! RSVDP_1 - Reserved for future use. */
71813 #define PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_SHIFT)) & PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_MASK)
71814 /*! @} */
71815 
71816 /*! @name ORDER_RULE_CTRL_OFF - Order Rule Control Register. */
71817 /*! @{ */
71818 
71819 #define PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK  (0xFFU)
71820 #define PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT (0U)
71821 /*! NP_PASS_P - Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P
71822  *    queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P
71823  */
71824 #define PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT)) & PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK)
71825 
71826 #define PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK (0xFF00U)
71827 #define PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT (8U)
71828 /*! CPL_PASS_P - Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted
71829  *    P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P
71830  */
71831 #define PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT)) & PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK)
71832 
71833 #define PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_MASK   (0xFFFF0000U)
71834 #define PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_SHIFT  (16U)
71835 /*! RSVDP_16 - Reserved for future use. */
71836 #define PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_SHIFT)) & PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_MASK)
71837 /*! @} */
71838 
71839 /*! @name PIPE_LOOPBACK_CONTROL_OFF - PIPE Loopback Control Register. */
71840 /*! @{ */
71841 
71842 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK (0xFFFFU)
71843 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT (0U)
71844 /*! LPBK_RXVALID - LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky. */
71845 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK)
71846 
71847 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK (0x3F0000U)
71848 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT (16U)
71849 /*! RXSTATUS_LANE - RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky. */
71850 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK)
71851 
71852 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MASK (0xC00000U)
71853 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SHIFT (22U)
71854 /*! RSVDP_22 - Reserved for future use. */
71855 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MASK)
71856 
71857 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK (0x7000000U)
71858 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT (24U)
71859 /*! RXSTATUS_VALUE - RXSTATUS_VALUE is an internally reserved field. Do not use. */
71860 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK)
71861 
71862 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MASK (0x78000000U)
71863 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SHIFT (27U)
71864 /*! RSVDP_27 - Reserved for future use. */
71865 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MASK)
71866 
71867 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK (0x80000000U)
71868 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT (31U)
71869 /*! PIPE_LOOPBACK - PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky. */
71870 #define PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK)
71871 /*! @} */
71872 
71873 /*! @name MISC_CONTROL_1_OFF - DBI Read-Only Write Enable Register. */
71874 /*! @{ */
71875 
71876 #define PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK (0x1U)
71877 #define PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT (0U)
71878 /*! DBI_RO_WR_EN - Write to RO Registers Using DBI. When you set this field to "1", then some RO and
71879  *    HwInit bits are writable from the local application through the DBI. For more details, see
71880  *    "Writing to Read-Only Registers." Note: This register field is sticky.
71881  */
71882 #define PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK)
71883 
71884 #define PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK (0x2U)
71885 #define PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT (1U)
71886 /*! DEFAULT_TARGET - Default target a received IO or MEM request with UR/CA/CRS is sent to by the
71887  *    controller. - 0: The controller drops all incoming I/O or MEM requests (after corresponding
71888  *    error reporting). A completion with UR status will be generated for non-posted requests. - 1: The
71889  *    controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application
71890  *    For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing"
71891  *    section of the "Controller Operations" chapter of the Databook. Default value is DEFAULT_TARGET
71892  *    configuration parameter. Note: This register field is sticky.
71893  */
71894 #define PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK)
71895 
71896 #define PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK (0x4U)
71897 #define PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT (2U)
71898 /*! UR_CA_MASK_4_TRGT1 - This field only applies to request TLPs (with UR filtering status) that you
71899  *    have chosen to forward to the application (when you set DEFAULT_TARGET in this register). -
71900  *    When you set this field to '1', the core suppresses error logging, Error Message generation,
71901  *    and CPL generation (for non-posted requests). - For more details, refer to the "Advanced Error
71902  *    Handling For Received TLPs" chapter of the Databook. You should set this if you have set the
71903  *    Default Target port logic register to '1'. Default is CX_MASK_UR_CA_4_TRGT1 configuration
71904  *    parameter. Note: This register field is sticky.
71905  */
71906 #define PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK)
71907 
71908 #define PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK (0x8U)
71909 #define PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT (3U)
71910 /*! SIMPLIFIED_REPLAY_TIMER - Enables Simplified Replay Timer (Gen4). For more details, see
71911  *    "Transmit Replay" in the Controller Operations chapter of the Databook. Simplified Replay Timer Values
71912  *    are: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from
71913  *    80,000 to 100,000 Symbol Times when Extended Synch is 1b. Must not be changed while link is in
71914  *    use. Note: This register field is sticky.
71915  */
71916 #define PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK)
71917 
71918 #define PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK (0x20U)
71919 #define PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT (5U)
71920 /*! ARI_DEVICE_NUMBER - When ARI is enabled, this field enables use of the device ID. Note: This register field is sticky. */
71921 #define PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK)
71922 
71923 #define PCIE_MISC_CONTROL_1_OFF_RSVDP_6_MASK     (0xFFFFFFC0U)
71924 #define PCIE_MISC_CONTROL_1_OFF_RSVDP_6_SHIFT    (6U)
71925 /*! RSVDP_6 - Reserved for future use. */
71926 #define PCIE_MISC_CONTROL_1_OFF_RSVDP_6(x)       (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_RSVDP_6_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_RSVDP_6_MASK)
71927 /*! @} */
71928 
71929 /*! @name MULTI_LANE_CONTROL_OFF - UpConfigure Multi-lane Control Register. */
71930 /*! @{ */
71931 
71932 #define PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK (0x3FU)
71933 #define PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT (0U)
71934 /*! TARGET_LINK_WIDTH - Target Link Width. Values correspond to: - 6'b000000: Core does not start
71935  *    upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 -
71936  *    6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32 This field is
71937  *    reserved (fixed to '0') for M-PCIe.
71938  */
71939 #define PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK)
71940 
71941 #define PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK (0x40U)
71942 #define PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT (6U)
71943 /*! DIRECT_LINK_WIDTH_CHANGE - Directed Link Width Change. The controller always moves to
71944  *    Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable
71945  *    variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is
71946  *    '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH
71947  *    value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not
71948  *    start upconfigure or autonomous width downsizing in the Configuration state. The controller
71949  *    self-clears this field when the controller accepts this request. This field is reserved (fixed
71950  *    to '0') for M-PCIe.
71951  */
71952 #define PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK)
71953 
71954 #define PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK (0x80U)
71955 #define PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT (7U)
71956 /*! UPCONFIGURE_SUPPORT - Upconfigure Support. The controller sends this value as the Link
71957  *    Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved
71958  *    (fixed to '0') for M-PCIe. Note: This register field is sticky.
71959  */
71960 #define PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK)
71961 
71962 #define PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_MASK (0xFFFFFF00U)
71963 #define PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_SHIFT (8U)
71964 /*! RSVDP_8 - Reserved for future use. */
71965 #define PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_MASK)
71966 /*! @} */
71967 
71968 /*! @name PHY_INTEROP_CTRL_OFF - PHY Interoperability Control Register. */
71969 /*! @{ */
71970 
71971 #define PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK (0x7FU)
71972 #define PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT (0U)
71973 /*! RXSTANDBY_CONTROL - Rxstandby Control. Bits 0..5 determine if the controller asserts the
71974  *    RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to
71975  *    perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN -
71976  *    [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 -
71977  *    [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This
71978  *    field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
71979  */
71980 #define PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK)
71981 
71982 #define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_MASK   (0x80U)
71983 #define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_SHIFT  (7U)
71984 /*! RSVDP_7 - Reserved for future use. */
71985 #define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_MASK)
71986 
71987 #define PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK (0x100U)
71988 #define PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT (8U)
71989 /*! L1SUB_EXIT_MODE - L1 Exit Control Using phy_mac_pclkack_n. - 1: Core exits L1 without waiting
71990  *    for the PHY to assert phy_mac_pclkack_n. - 0: Core waits for the PHY to assert phy_mac_pclkack_n
71991  *    before exiting L1. Note: This register field is sticky.
71992  */
71993 #define PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK)
71994 
71995 #define PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK (0x200U)
71996 #define PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT (9U)
71997 /*! L1_NOWAIT_P1 - L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition
71998  *    to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before
71999  *    entering L1. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note:
72000  *    This register field is sticky.
72001  */
72002 #define PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK)
72003 
72004 #define PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK (0x400U)
72005 #define PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT (10U)
72006 /*! L1_CLK_SEL - L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk
72007  *    gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1. Note: This
72008  *    register field is sticky.
72009  */
72010 #define PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK)
72011 
72012 #define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_MASK  (0xFFFFF800U)
72013 #define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_SHIFT (11U)
72014 /*! RSVDP_11 - Reserved for future use. */
72015 #define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_MASK)
72016 /*! @} */
72017 
72018 /*! @name TRGT_CPL_LUT_DELETE_ENTRY_OFF - TRGT_CPL_LUT Delete Entry Control register. */
72019 /*! @{ */
72020 
72021 #define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK (0x7FFFFFFFU)
72022 #define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT (0U)
72023 /*! LOOK_UP_ID - This number selects one entry to delete of the TRGT_CPL_LUT. */
72024 #define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT)) & PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK)
72025 
72026 #define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK (0x80000000U)
72027 #define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT (31U)
72028 /*! DELETE_EN - This is a one-shot bit. A '1' write to this bit triggers the deletion of the target
72029  *    completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing
72030  *    register field. Reading from this register field always returns a '0'.
72031  */
72032 #define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT)) & PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK)
72033 /*! @} */
72034 
72035 /*! @name LINK_FLUSH_CONTROL_OFF - Link Reset Request Flush Control Register. */
72036 /*! @{ */
72037 
72038 #define PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK (0x1U)
72039 #define PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT (0U)
72040 /*! AUTO_FLUSH_EN - Enables automatic flushing of pending requests before sending the reset request
72041  *    to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process
72042  *    is initiated if any of the following events occur: - Hot reset request. A downstream port
72043  *    (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the
72044  *    hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and
72045  *    cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not
72046  *    indicates the link has gone down and the controller is requesting a reset. If you disable
72047  *    automatic flushing, your application is responsible for resetting the PCIe controller and the AXI
72048  *    Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the
72049  *    Databook. Note: This register field is sticky.
72050  */
72051 #define PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT)) & PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK)
72052 
72053 #define PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MASK (0xFFFFFEU)
72054 #define PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SHIFT (1U)
72055 /*! RSVDP_1 - Reserved for future use. */
72056 #define PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SHIFT)) & PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MASK)
72057 
72058 #define PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MASK (0xFF000000U)
72059 #define PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SHIFT (24U)
72060 /*! RSVD_I_8 - This is an internally reserved field. Do not use. Note: This register field is sticky. */
72061 #define PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SHIFT)) & PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MASK)
72062 /*! @} */
72063 
72064 /*! @name AMBA_ERROR_RESPONSE_DEFAULT_OFF - AXI Bridge Slave Error Response Register. */
72065 /*! @{ */
72066 
72067 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK (0x1U)
72068 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT (0U)
72069 /*! AMBA_ERROR_RESPONSE_GLOBAL - Global Slave Error Response Mapping. Determines the AXI slave
72070  *    response for all error scenarios on non-posted requests. For more details see "Error Handling" in
72071  *    the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for non-posted requests) and
72072  *    ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and
72073  *    look at bit [2] for other scenarios. AXI: - 0: OKAY (with FFFF data for non-posted requests) -
72074  *    1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error
72075  *    response mapping) The error response mapping is not applicable to Non-existent Vendor ID register
72076  *    reads. Note: This register field is sticky.
72077  */
72078 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK)
72079 
72080 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MASK (0x2U)
72081 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SHIFT (1U)
72082 /*! RSVDP_1 - Reserved for future use. */
72083 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MASK)
72084 
72085 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK (0x4U)
72086 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT (2U)
72087 /*! AMBA_ERROR_RESPONSE_VENDORID - Vendor ID Non-existent Slave Error Response Mapping. Determines
72088  *    the AXI slave response for errors on reads to non-existent Vendor ID register. For more details
72089  *    see "Error Handling" in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data). The
72090  *    controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERROR AXI:
72091  *    - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines
72092  *    the PCIe-to-AXI Slave error response mapping) Note: This register field is sticky.
72093  */
72094 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK)
72095 
72096 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK (0x18U)
72097 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT (3U)
72098 /*! AMBA_ERROR_RESPONSE_CRS - CRS Slave Error Response Mapping. Determines the AXI slave response
72099  *    for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.
72100  *    AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS
72101  *    completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY
72102  *    with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP
72103  *    field determines the PCIe-to-AXI Slave error response mapping) Note: This register field is
72104  *    sticky.
72105  */
72106 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK)
72107 
72108 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MASK (0x3E0U)
72109 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SHIFT (5U)
72110 /*! RSVDP_5 - Reserved for future use. */
72111 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MASK)
72112 
72113 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK (0xFC00U)
72114 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT (10U)
72115 /*! AMBA_ERROR_RESPONSE_MAP - AXI Slave Response Error Map. Allows you to selectively map the errors
72116  *    received from the PCIe completion (for non-posted requests) to the AXI slave responses,
72117  *    slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] - 0:
72118  *    UR (unsupported request) -> DECERR - 1: UR (unsupported request) -> SLVERR - [1] - 0: CRS
72119  *    (configuration retry status) -> DECERR - 1: CRS (configuration retry status) -> SLVERR - [2] - 0:
72120  *    CA (completer abort) -> DECERR - 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]:
72121  *    Reserved - [5]: - 0: Completion Timeout -> DECERR - 1: Completion Timeout -> SLVERR The AXI
72122  *    bridge internally drops (processes internally but not passed to your application) a completion that
72123  *    has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to
72124  *    the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave
72125  *    interface. The controller sets the AXI slave read databus to 0xFFFF for all error responses.
72126  *    Note: This register field is sticky.
72127  */
72128 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK)
72129 
72130 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MASK (0xFFFF0000U)
72131 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SHIFT (16U)
72132 /*! RSVDP_16 - Reserved for future use. */
72133 #define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MASK)
72134 /*! @} */
72135 
72136 /*! @name AMBA_LINK_TIMEOUT_OFF - Link Down AXI Bridge Slave Timeout Register. */
72137 /*! @{ */
72138 
72139 #define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK (0xFFU)
72140 #define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT (0U)
72141 /*! LINK_TIMEOUT_PERIOD_DEFAULT - Timeout Value (ms). The timer will timeout and then flush the
72142  *    bridge TX request queues after this amount of time. The timer counts when there are pending
72143  *    outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these
72144  *    requests. The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is
72145  *    4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between
72146  *    16% and 17%. Note: This register field is sticky.
72147  */
72148 #define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT)) & PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK)
72149 
72150 #define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK (0x100U)
72151 #define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT (8U)
72152 /*! LINK_TIMEOUT_ENABLE_DEFAULT - Disable Flush. You can disable the flush feature by setting this field to "1". Note: This register field is sticky. */
72153 #define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT)) & PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK)
72154 
72155 #define PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MASK  (0xFFFFFE00U)
72156 #define PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SHIFT (9U)
72157 /*! RSVDP_9 - Reserved for future use. */
72158 #define PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SHIFT)) & PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MASK)
72159 /*! @} */
72160 
72161 /*! @name AMBA_ORDERING_CTRL_OFF - AMBA Ordering Control. */
72162 /*! @{ */
72163 
72164 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MASK (0x1U)
72165 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SHIFT (0U)
72166 /*! RSVDP_0 - Reserved for future use. */
72167 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MASK)
72168 
72169 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK (0x2U)
72170 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT (1U)
72171 /*! AX_SNP_EN - AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to
72172  *    serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding
72173  *    same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote
72174  *    link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted
72175  *    Requests" section in the AXI chapter of the Databook.
72176  */
72177 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK)
72178 
72179 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MASK (0x4U)
72180 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SHIFT (2U)
72181 /*! RSVDP_2 - Reserved for future use. */
72182 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MASK)
72183 
72184 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK (0x18U)
72185 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT (3U)
72186 /*! AX_MSTR_ORDR_P_EVENT_SEL - AXI Master Posted Ordering Event Selector. This field selects how the
72187  *    master interface determines when a P write is completed when enforcing the PCIe ordering
72188  *    rule, "NP must not pass P" at the AXI Master Interface. The AXI protocol does not support ordering
72189  *    between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in
72190  *    an ordering violation when the read overtakes a P that is going to the same address. Therefore,
72191  *    the bridge master does not issue any NP requests until all outstanding P writes reach their
72192  *    destination. It does this by waiting for the all of the write responses on the B channel. This
72193  *    can affect the performance of the master read channel. For scenarios where the interconnect
72194  *    serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by
72195  *    reducing the need to wait until the complete Posted transaction has effectively reached the
72196  *    application slave. - 00: B'last event: wait for the all of the write responses on the B channel
72197  *    thereby ensuring that the complete Posted transaction has effectively reached the application slave
72198  *    (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI
72199  *    address channel at the bridge master. - 10: W'last event: wait until the complete Posted
72200  *    transaction has left the AXI data channel at the bridge master. - 11: Reserved Note 2: This setting
72201  *    will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the
72202  *    B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP
72203  *    write transactions which are always serialized with P write transactions.
72204  */
72205 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK)
72206 
72207 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MASK (0x60U)
72208 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SHIFT (5U)
72209 /*! RSVDP_5 - Reserved for future use. */
72210 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MASK)
72211 
72212 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK (0x80U)
72213 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT (7U)
72214 /*! AX_MSTR_ZEROLREAD_FW - AXI Master Zero Length Read Forward to the application. The DW PCIe
72215  *    controller AXI bridge is able to terminate in order with the Posted transactions the zero length
72216  *    read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero
72217  *    length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is
72218  *    forward to the application.
72219  */
72220 #define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK)
72221 
72222 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MASK (0xFFFFFF00U)
72223 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SHIFT (8U)
72224 /*! RSVDP_8 - Reserved for future use. */
72225 #define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MASK)
72226 /*! @} */
72227 
72228 /*! @name AXI_MSTR_MSG_ADDR_LOW_OFF - Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. */
72229 /*! @{ */
72230 
72231 #define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK (0xFFFU)
72232 #define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT (0U)
72233 /*! CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED - Reserved for future use. Note: This register field is sticky. */
72234 #define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT)) & PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK)
72235 
72236 #define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK (0xFFFFF000U)
72237 #define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT (12U)
72238 /*! CFG_AXIMSTR_MSG_ADDR_LOW - Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky. */
72239 #define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT)) & PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK)
72240 /*! @} */
72241 
72242 /*! @name AXI_MSTR_MSG_ADDR_HIGH_OFF - Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to. */
72243 /*! @{ */
72244 
72245 #define PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK (0xFFFFFFFFU)
72246 #define PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT (0U)
72247 /*! CFG_AXIMSTR_MSG_ADDR_HIGH - Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky. */
72248 #define PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT)) & PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK)
72249 /*! @} */
72250 
72251 /*! @name PCIE_VERSION_NUMBER_OFF - PCIe Controller IIP Release Version Number. */
72252 /*! @{ */
72253 
72254 #define PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK (0xFFFFFFFFU)
72255 #define PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT (0U)
72256 /*! VERSION_NUMBER - Version Number. */
72257 #define PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT)) & PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK)
72258 /*! @} */
72259 
72260 /*! @name PCIE_VERSION_TYPE_OFF - PCIe Controller IIP Release Version Type. */
72261 /*! @{ */
72262 
72263 #define PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK (0xFFFFFFFFU)
72264 #define PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT (0U)
72265 /*! VERSION_TYPE - Version Type. */
72266 #define PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT)) & PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK)
72267 /*! @} */
72268 
72269 /*! @name AUX_CLK_FREQ_OFF - Auxiliary Clock Frequency Control Register. */
72270 /*! @{ */
72271 
72272 #define PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK  (0x3FFU)
72273 #define PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT (0U)
72274 /*! AUX_CLK_FREQ - The aux_clk frequency in MHz. This value is used to provide a 1 us reference for
72275  *    counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.
72276  *    Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the
72277  *    actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then
72278  *    there is an error in the time counted by the controller that can be expressed in percentage
72279  *    as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err%
72280  *    =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than
72281  *    the time in us programmed in the corresponding time register (for example T_POWER_ON). Note:
72282  *    This register field is sticky.
72283  */
72284 #define PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT)) & PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK)
72285 
72286 #define PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_MASK      (0xFFFFFC00U)
72287 #define PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_SHIFT     (10U)
72288 /*! RSVDP_10 - Reserved for future use. */
72289 #define PCIE_AUX_CLK_FREQ_OFF_RSVDP_10(x)        (((uint32_t)(((uint32_t)(x)) << PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_SHIFT)) & PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_MASK)
72290 /*! @} */
72291 
72292 /*! @name L1_SUBSTATES_OFF - L1 Substates Timing Register. */
72293 /*! @{ */
72294 
72295 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK (0x3U)
72296 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT (0U)
72297 /*! L1SUB_T_POWER_OFF - Duration (in 1us units) of L1.2.Entry. Range is 0.3. Note: The timeout value
72298  *    can vary by 50%. Note: This register field is sticky.
72299  */
72300 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT)) & PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK)
72301 
72302 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK  (0x3CU)
72303 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT (2U)
72304 /*! L1SUB_T_L1_2 - Duration (in 1us units) of L1.2. Range is 0.15. Note: The timeout value can vary
72305  *    by 50%. Note: This register field is sticky.
72306  */
72307 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT)) & PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK)
72308 
72309 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MASK (0xC0U)
72310 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SHIFT (6U)
72311 /*! L1SUB_T_PCLKACK - Max delay (in 1us units) between a MAC request to remove the clock on
72312  *    mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this
72313  *    time the request is aborted. Range is 0..3 Note: This register field is sticky.
72314  */
72315 #define PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SHIFT)) & PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MASK)
72316 
72317 #define PCIE_L1_SUBSTATES_OFF_RSVDP_8_MASK       (0xFFFFFF00U)
72318 #define PCIE_L1_SUBSTATES_OFF_RSVDP_8_SHIFT      (8U)
72319 /*! RSVDP_8 - Reserved for future use. */
72320 #define PCIE_L1_SUBSTATES_OFF_RSVDP_8(x)         (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_RSVDP_8_SHIFT)) & PCIE_L1_SUBSTATES_OFF_RSVDP_8_MASK)
72321 /*! @} */
72322 
72323 /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_0 - iATU Region Control 1 Register. */
72324 /*! @{ */
72325 
72326 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MASK (0x1FU)
72327 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SHIFT (0U)
72328 /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
72329  *    TLP is changed to the value in this register. Note: This register field is sticky.
72330  */
72331 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MASK)
72332 
72333 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MASK (0xE0U)
72334 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SHIFT (5U)
72335 /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
72336  *    is changed to the value in this register. Note: This register field is sticky.
72337  */
72338 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MASK)
72339 
72340 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MASK (0x100U)
72341 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SHIFT (8U)
72342 /*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
72343  *    is changed to the value in this register. Note: This register field is sticky.
72344  */
72345 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MASK)
72346 
72347 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MASK (0x600U)
72348 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SHIFT (9U)
72349 /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
72350  *    TLP is changed to the value in this register. Note: This register field is sticky.
72351  */
72352 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MASK)
72353 
72354 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MASK (0x2000U)
72355 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SHIFT (13U)
72356 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
72357  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
72358  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
72359  */
72360 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MASK)
72361 
72362 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MASK (0x700000U)
72363 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SHIFT (20U)
72364 /*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
72365  *    region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
72366  *    used in generating the function part of the requester ID (RID) field of the TLP is taken from
72367  *    this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
72368  *    the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
72369  *    field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
72370  *    "Max_Payload_Size" values are used. Note: This register field is sticky.
72371  */
72372 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MASK)
72373 /*! @} */
72374 
72375 /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_0 - iATU Region Control 2 Register. */
72376 /*! @{ */
72377 
72378 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MASK (0xFFU)
72379 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SHIFT (0U)
72380 /*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
72381  *    region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
72382  *    changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
72383  *    outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
72384  *    then the ST field of the TLP is changed to the value in this register. Only Valid when the
72385  *    CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
72386  */
72387 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MASK)
72388 
72389 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MASK (0xFF00U)
72390 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SHIFT (8U)
72391 /*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
72392  *    is set. Note: This register field is sticky.
72393  */
72394 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MASK)
72395 
72396 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MASK (0x10000U)
72397 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SHIFT (16U)
72398 /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
72399  *    substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
72400  *    this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
72401  *    Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
72402  *    in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
72403  *    field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
72404  */
72405 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MASK)
72406 
72407 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MASK (0x80000U)
72408 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SHIFT (19U)
72409 /*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
72410  *    translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
72411  *    field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
72412  *    Note: This register field is sticky.
72413  */
72414 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MASK)
72415 
72416 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MASK (0x100000U)
72417 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SHIFT (20U)
72418 /*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
72419  *    Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
72420  *    Non-Posted Requests outstanding. Note: This register field is sticky.
72421  */
72422 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MASK)
72423 
72424 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MASK (0x400000U)
72425 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SHIFT (22U)
72426 /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
72427  *    TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
72428  *    having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
72429  *    inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
72430  *    a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
72431  *    sent. Note: This register field is sticky.
72432  */
72433 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MASK)
72434 
72435 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
72436 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SHIFT (23U)
72437 /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
72438  *    iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
72439  *    the outbound TLP header with the contents of the LWR_TARGET_RW field in
72440  *    IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
72441  *    to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
72442  *    translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
72443  *    forms the new address of the translated region. Note: This register field is sticky.
72444  */
72445 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MASK)
72446 
72447 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MASK (0x8000000U)
72448 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SHIFT (27U)
72449 /*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
72450  *    pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
72451  *    set it to '0'. Note: This register field is sticky.
72452  */
72453 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MASK)
72454 
72455 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MASK (0x10000000U)
72456 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SHIFT (28U)
72457 /*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
72458  *    XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
72459  *    TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
72460  *    of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
72461  *    TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
72462  *    of the PCIe configuration space. Note: This register field is sticky.
72463  */
72464 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MASK)
72465 
72466 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MASK (0x20000000U)
72467 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SHIFT (29U)
72468 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
72469  *    address match occurs when the untranslated address is in the region outside the defined range (Base
72470  *    Address to Limit Address). Note: This register field is sticky.
72471  */
72472 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MASK)
72473 
72474 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MASK (0x80000000U)
72475 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SHIFT (31U)
72476 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
72477 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MASK)
72478 /*! @} */
72479 
72480 /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 - iATU Lower Base Address Register. */
72481 /*! @{ */
72482 
72483 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MASK (0xFFFFU)
72484 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SHIFT (0U)
72485 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
72486  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
72487  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
72488  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
72489  */
72490 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MASK)
72491 
72492 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MASK (0xFFFF0000U)
72493 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SHIFT (16U)
72494 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
72495  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
72496  */
72497 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MASK)
72498 /*! @} */
72499 
72500 /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 - iATU Upper Base Address Register. */
72501 /*! @{ */
72502 
72503 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
72504 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SHIFT (0U)
72505 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
72506  *    translated. In systems with a 32-bit address space, this register is not used and therefore
72507  *    writing to this register has no effect. Note: This register field is sticky.
72508  */
72509 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MASK)
72510 /*! @} */
72511 
72512 /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_0 - iATU Limit Address Register. */
72513 /*! @{ */
72514 
72515 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MASK (0xFFFFU)
72516 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SHIFT (0U)
72517 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
72518  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
72519  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
72520  */
72521 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MASK)
72522 
72523 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
72524 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SHIFT (16U)
72525 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
72526  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
72527  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
72528  *    Note: This register field is sticky.
72529  */
72530 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MASK)
72531 /*! @} */
72532 
72533 /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 - iATU Lower Target Address Register. */
72534 /*! @{ */
72535 
72536 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
72537 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
72538 /*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
72539  *    (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
72540  *    address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
72541  *    aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
72542  *    the start address of the new address of the translated region (bits n-1:0) are always '0'). -
72543  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
72544  *    IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
72545  *    header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
72546  *    the transmission of Vendor Defined Messages where the controller determines the content of
72547  *    bytes 12 to 15 of the TLP header. Note: This register field is sticky.
72548  */
72549 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MASK)
72550 /*! @} */
72551 
72552 /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 - iATU Upper Target Address Register. */
72553 /*! @{ */
72554 
72555 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
72556 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SHIFT (0U)
72557 /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
72558  *    of the translated region. Note: This register field is sticky.
72559  */
72560 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MASK)
72561 /*! @} */
72562 
72563 /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_0 - iATU Region Control 1 Register. */
72564 /*! @{ */
72565 
72566 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MASK (0x1FU)
72567 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SHIFT (0U)
72568 /*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
72569  *    proceeds (when all other enabled field-matches are successful). Note: This register field is
72570  *    sticky.
72571  */
72572 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MASK)
72573 
72574 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MASK (0xE0U)
72575 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SHIFT (5U)
72576 /*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
72577  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
72578  *    the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
72579  *    sticky.
72580  */
72581 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MASK)
72582 
72583 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MASK (0x100U)
72584 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SHIFT (8U)
72585 /*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
72586  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
72587  *    the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
72588  *    sticky.
72589  */
72590 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MASK)
72591 
72592 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MASK (0x600U)
72593 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SHIFT (9U)
72594 /*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
72595  *    proceeds (when all other enabled field-matches are successful). This check is only performed
72596  *    if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
72597  *    field is sticky.
72598  */
72599 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MASK)
72600 
72601 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MASK (0x2000U)
72602 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SHIFT (13U)
72603 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
72604  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
72605  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
72606  */
72607 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MASK)
72608 
72609 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MASK (0x700000U)
72610 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SHIFT (20U)
72611 /*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
72612  *    controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
72613  *    this value, then address translation proceeds. This check is only performed if the "Function
72614  *    Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
72615  *    destination function number as specified in the routing ID of the TLP header matches the function, then
72616  *    address translation proceeds. This check is only performed if the "Function Number Match
72617  *    Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
72618  */
72619 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MASK)
72620 /*! @} */
72621 
72622 /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_0 - iATU Region Control 2 Register. */
72623 /*! @{ */
72624 
72625 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MASK (0xFFU)
72626 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SHIFT (0U)
72627 /*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
72628  *    to this value, then address translation proceeds (when all other enabled field-matches are
72629  *    successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
72630  *    Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
72631  *    matched to this value, then address translation proceeds. This check is only performed if the
72632  *    "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
72633  *    the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
72634  *    Note: This register field is sticky.
72635  */
72636 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MASK)
72637 
72638 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MASK (0x700U)
72639 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SHIFT (8U)
72640 /*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
72641  *    normal internal BAR address matching mechanism " is the same as this field, address translation
72642  *    proceeds (when all other enabled field-matches are successful). This check is only performed
72643  *    if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
72644  *    010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
72645  *    translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
72646  *    the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
72647  *    sticky.
72648  */
72649 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MASK)
72650 
72651 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
72652 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SHIFT (13U)
72653 /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
72654  *    translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
72655  *    iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
72656  *    mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
72657  *    translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
72658  *    This register field is sticky.
72659  */
72660 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MASK)
72661 
72662 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MASK (0x4000U)
72663 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SHIFT (14U)
72664 /*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
72665  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
72666  *    register field is sticky.
72667  */
72668 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MASK)
72669 
72670 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MASK (0x8000U)
72671 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SHIFT (15U)
72672 /*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
72673  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
72674  *    register field is sticky.
72675  */
72676 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MASK)
72677 
72678 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MASK (0x10000U)
72679 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SHIFT (16U)
72680 /*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
72681  *    (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
72682  *    Note: This register field is sticky.
72683  */
72684 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MASK)
72685 
72686 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MASK (0x80000U)
72687 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SHIFT (19U)
72688 /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
72689  *    field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
72690  *    MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
72691  *    field is sticky.
72692  */
72693 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MASK)
72694 
72695 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MASK (0x200000U)
72696 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SHIFT (21U)
72697 /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
72698  *    TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
72699  *    (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
72700  *    that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
72701  *    occurs (in MEM transactions) for address translation to proceed. Only Valid when the
72702  *    CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
72703  */
72704 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MASK)
72705 
72706 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
72707 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
72708 /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
72709  *    be translated to a single address location as determined by the target address register of the
72710  *    iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
72711  *    Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
72712  */
72713 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MASK)
72714 
72715 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MASK (0x3000000U)
72716 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SHIFT (24U)
72717 /*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
72718  *    region. This overrides the normal RADM filter response. Note that this feature is not available
72719  *    for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
72720  *    response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
72721  *    / undefined / reserved. Note: This register field is sticky.
72722  */
72723 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MASK)
72724 
72725 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
72726 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
72727 /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
72728  *    the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
72729  *    identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
72730  *    The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
72731  *    For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
72732  *    inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
72733  */
72734 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MASK)
72735 
72736 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MASK (0x10000000U)
72737 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SHIFT (28U)
72738 /*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
72739  *    configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
72740  *    allows a CFG configuration space to be located in any 256MB window of your application memory space
72741  *    using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
72742  *    bits [27:12] of the translated address. Note: This register field is sticky.
72743  */
72744 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MASK)
72745 
72746 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MASK (0x20000000U)
72747 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SHIFT (29U)
72748 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
72749  *    address match occurs when the untranslated address is in the region outside the defined range (Base
72750  *    Address to Limit Address). Note: This register field is sticky.
72751  */
72752 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MASK)
72753 
72754 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MASK (0x40000000U)
72755 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SHIFT (30U)
72756 /*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
72757  *    of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
72758  *    0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
72759  *    Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
72760  *    "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
72761  *    follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
72762  *    header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
72763  *    transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
72764  *    to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
72765  *    routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
72766  *    processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
72767  *    0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
72768  *    MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
72769  *    Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
72770  *    the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
72771  *    but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
72772  *    [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
72773  *    lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
72774  *    information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
72775  *    1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
72776  */
72777 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MASK)
72778 
72779 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MASK (0x80000000U)
72780 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SHIFT (31U)
72781 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
72782 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MASK)
72783 /*! @} */
72784 
72785 /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_0 - iATU Lower Base Address Register. */
72786 /*! @{ */
72787 
72788 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MASK (0xFFFFU)
72789 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SHIFT (0U)
72790 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
72791  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
72792  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
72793  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
72794  */
72795 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MASK)
72796 
72797 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MASK (0xFFFF0000U)
72798 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SHIFT (16U)
72799 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
72800  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
72801  */
72802 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MASK)
72803 /*! @} */
72804 
72805 /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_0 - iATU Upper Base Address Register. */
72806 /*! @{ */
72807 
72808 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
72809 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SHIFT (0U)
72810 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
72811  *    translated. Note: This register field is sticky.
72812  */
72813 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MASK)
72814 /*! @} */
72815 
72816 /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_0 - iATU Limit Address Register. */
72817 /*! @{ */
72818 
72819 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MASK (0xFFFFU)
72820 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SHIFT (0U)
72821 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
72822  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
72823  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
72824  */
72825 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MASK)
72826 
72827 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
72828 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SHIFT (16U)
72829 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
72830  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
72831  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
72832  *    Note: This register field is sticky.
72833  */
72834 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MASK)
72835 /*! @} */
72836 
72837 /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 - iATU Lower Target Address Register. */
72838 /*! @{ */
72839 
72840 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MASK (0xFFFFU)
72841 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SHIFT (0U)
72842 /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
72843  *    region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
72844  *    kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
72845  *    these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
72846  *    target address must align to the iATU region size; otherwise it must align to the BAR size. A
72847  *    write to this location is ignored by the PCIe controller. - Field size depends on
72848  *    log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
72849  *    log2(BAR_MASK+1) in BAR match mode.
72850  */
72851 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MASK)
72852 
72853 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MASK (0xFFFF0000U)
72854 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SHIFT (16U)
72855 /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
72856  *    region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
72857  *    of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
72858  *    mode. Note: This register field is sticky.
72859  */
72860 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MASK)
72861 /*! @} */
72862 
72863 /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_1 - iATU Region Control 1 Register. */
72864 /*! @{ */
72865 
72866 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MASK (0x1FU)
72867 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SHIFT (0U)
72868 /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
72869  *    TLP is changed to the value in this register. Note: This register field is sticky.
72870  */
72871 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MASK)
72872 
72873 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MASK (0xE0U)
72874 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SHIFT (5U)
72875 /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
72876  *    is changed to the value in this register. Note: This register field is sticky.
72877  */
72878 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MASK)
72879 
72880 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MASK (0x100U)
72881 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SHIFT (8U)
72882 /*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
72883  *    is changed to the value in this register. Note: This register field is sticky.
72884  */
72885 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MASK)
72886 
72887 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MASK (0x600U)
72888 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SHIFT (9U)
72889 /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
72890  *    TLP is changed to the value in this register. Note: This register field is sticky.
72891  */
72892 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MASK)
72893 
72894 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MASK (0x2000U)
72895 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SHIFT (13U)
72896 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
72897  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
72898  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
72899  */
72900 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MASK)
72901 
72902 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MASK (0x700000U)
72903 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SHIFT (20U)
72904 /*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
72905  *    region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
72906  *    used in generating the function part of the requester ID (RID) field of the TLP is taken from
72907  *    this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
72908  *    the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
72909  *    field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
72910  *    "Max_Payload_Size" values are used. Note: This register field is sticky.
72911  */
72912 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MASK)
72913 /*! @} */
72914 
72915 /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_1 - iATU Region Control 2 Register. */
72916 /*! @{ */
72917 
72918 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MASK (0xFFU)
72919 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SHIFT (0U)
72920 /*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
72921  *    region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
72922  *    changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
72923  *    outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
72924  *    then the ST field of the TLP is changed to the value in this register. Only Valid when the
72925  *    CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
72926  */
72927 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MASK)
72928 
72929 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MASK (0xFF00U)
72930 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SHIFT (8U)
72931 /*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
72932  *    is set. Note: This register field is sticky.
72933  */
72934 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MASK)
72935 
72936 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MASK (0x10000U)
72937 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SHIFT (16U)
72938 /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
72939  *    substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
72940  *    this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
72941  *    Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
72942  *    in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
72943  *    field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
72944  */
72945 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MASK)
72946 
72947 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MASK (0x80000U)
72948 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SHIFT (19U)
72949 /*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
72950  *    translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
72951  *    field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
72952  *    Note: This register field is sticky.
72953  */
72954 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MASK)
72955 
72956 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MASK (0x100000U)
72957 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SHIFT (20U)
72958 /*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
72959  *    Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
72960  *    Non-Posted Requests outstanding. Note: This register field is sticky.
72961  */
72962 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MASK)
72963 
72964 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MASK (0x400000U)
72965 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SHIFT (22U)
72966 /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
72967  *    TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
72968  *    having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
72969  *    inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
72970  *    a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
72971  *    sent. Note: This register field is sticky.
72972  */
72973 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MASK)
72974 
72975 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
72976 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SHIFT (23U)
72977 /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
72978  *    iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
72979  *    the outbound TLP header with the contents of the LWR_TARGET_RW field in
72980  *    IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
72981  *    to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
72982  *    translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
72983  *    forms the new address of the translated region. Note: This register field is sticky.
72984  */
72985 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MASK)
72986 
72987 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MASK (0x8000000U)
72988 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SHIFT (27U)
72989 /*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
72990  *    pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
72991  *    set it to '0'. Note: This register field is sticky.
72992  */
72993 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MASK)
72994 
72995 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MASK (0x10000000U)
72996 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SHIFT (28U)
72997 /*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
72998  *    XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
72999  *    TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
73000  *    of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
73001  *    TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
73002  *    of the PCIe configuration space. Note: This register field is sticky.
73003  */
73004 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MASK)
73005 
73006 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MASK (0x20000000U)
73007 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SHIFT (29U)
73008 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
73009  *    address match occurs when the untranslated address is in the region outside the defined range (Base
73010  *    Address to Limit Address). Note: This register field is sticky.
73011  */
73012 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MASK)
73013 
73014 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MASK (0x80000000U)
73015 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SHIFT (31U)
73016 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
73017 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MASK)
73018 /*! @} */
73019 
73020 /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1 - iATU Lower Base Address Register. */
73021 /*! @{ */
73022 
73023 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MASK (0xFFFFU)
73024 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SHIFT (0U)
73025 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
73026  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73027  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73028  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
73029  */
73030 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MASK)
73031 
73032 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MASK (0xFFFF0000U)
73033 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SHIFT (16U)
73034 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
73035  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
73036  */
73037 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MASK)
73038 /*! @} */
73039 
73040 /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1 - iATU Upper Base Address Register. */
73041 /*! @{ */
73042 
73043 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
73044 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SHIFT (0U)
73045 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
73046  *    translated. In systems with a 32-bit address space, this register is not used and therefore
73047  *    writing to this register has no effect. Note: This register field is sticky.
73048  */
73049 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MASK)
73050 /*! @} */
73051 
73052 /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_1 - iATU Limit Address Register. */
73053 /*! @{ */
73054 
73055 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MASK (0xFFFFU)
73056 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SHIFT (0U)
73057 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
73058  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73059  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73060  */
73061 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MASK)
73062 
73063 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
73064 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SHIFT (16U)
73065 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
73066  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73067  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73068  *    Note: This register field is sticky.
73069  */
73070 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MASK)
73071 /*! @} */
73072 
73073 /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1 - iATU Lower Target Address Register. */
73074 /*! @{ */
73075 
73076 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
73077 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
73078 /*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
73079  *    (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
73080  *    address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
73081  *    aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
73082  *    the start address of the new address of the translated region (bits n-1:0) are always '0'). -
73083  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
73084  *    IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
73085  *    header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
73086  *    the transmission of Vendor Defined Messages where the controller determines the content of
73087  *    bytes 12 to 15 of the TLP header. Note: This register field is sticky.
73088  */
73089 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MASK)
73090 /*! @} */
73091 
73092 /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1 - iATU Upper Target Address Register. */
73093 /*! @{ */
73094 
73095 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
73096 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SHIFT (0U)
73097 /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
73098  *    of the translated region. Note: This register field is sticky.
73099  */
73100 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MASK)
73101 /*! @} */
73102 
73103 /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_1 - iATU Region Control 1 Register. */
73104 /*! @{ */
73105 
73106 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MASK (0x1FU)
73107 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SHIFT (0U)
73108 /*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
73109  *    proceeds (when all other enabled field-matches are successful). Note: This register field is
73110  *    sticky.
73111  */
73112 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MASK)
73113 
73114 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MASK (0xE0U)
73115 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SHIFT (5U)
73116 /*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
73117  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
73118  *    the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
73119  *    sticky.
73120  */
73121 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MASK)
73122 
73123 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MASK (0x100U)
73124 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SHIFT (8U)
73125 /*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
73126  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
73127  *    the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
73128  *    sticky.
73129  */
73130 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MASK)
73131 
73132 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MASK (0x600U)
73133 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SHIFT (9U)
73134 /*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
73135  *    proceeds (when all other enabled field-matches are successful). This check is only performed
73136  *    if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
73137  *    field is sticky.
73138  */
73139 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MASK)
73140 
73141 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MASK (0x2000U)
73142 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SHIFT (13U)
73143 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
73144  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
73145  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
73146  */
73147 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MASK)
73148 
73149 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MASK (0x700000U)
73150 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SHIFT (20U)
73151 /*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
73152  *    controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
73153  *    this value, then address translation proceeds. This check is only performed if the "Function
73154  *    Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
73155  *    destination function number as specified in the routing ID of the TLP header matches the function, then
73156  *    address translation proceeds. This check is only performed if the "Function Number Match
73157  *    Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
73158  */
73159 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MASK)
73160 /*! @} */
73161 
73162 /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_1 - iATU Region Control 2 Register. */
73163 /*! @{ */
73164 
73165 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MASK (0xFFU)
73166 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SHIFT (0U)
73167 /*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
73168  *    to this value, then address translation proceeds (when all other enabled field-matches are
73169  *    successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
73170  *    Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
73171  *    matched to this value, then address translation proceeds. This check is only performed if the
73172  *    "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
73173  *    the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
73174  *    Note: This register field is sticky.
73175  */
73176 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MASK)
73177 
73178 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MASK (0x700U)
73179 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SHIFT (8U)
73180 /*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
73181  *    normal internal BAR address matching mechanism " is the same as this field, address translation
73182  *    proceeds (when all other enabled field-matches are successful). This check is only performed
73183  *    if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
73184  *    010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
73185  *    translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
73186  *    the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
73187  *    sticky.
73188  */
73189 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MASK)
73190 
73191 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
73192 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SHIFT (13U)
73193 /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
73194  *    translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
73195  *    iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
73196  *    mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
73197  *    translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
73198  *    This register field is sticky.
73199  */
73200 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MASK)
73201 
73202 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MASK (0x4000U)
73203 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SHIFT (14U)
73204 /*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
73205  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
73206  *    register field is sticky.
73207  */
73208 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MASK)
73209 
73210 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MASK (0x8000U)
73211 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SHIFT (15U)
73212 /*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
73213  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
73214  *    register field is sticky.
73215  */
73216 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MASK)
73217 
73218 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MASK (0x10000U)
73219 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SHIFT (16U)
73220 /*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
73221  *    (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
73222  *    Note: This register field is sticky.
73223  */
73224 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MASK)
73225 
73226 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MASK (0x80000U)
73227 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SHIFT (19U)
73228 /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
73229  *    field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
73230  *    MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
73231  *    field is sticky.
73232  */
73233 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MASK)
73234 
73235 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MASK (0x200000U)
73236 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SHIFT (21U)
73237 /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
73238  *    TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
73239  *    (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
73240  *    that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
73241  *    occurs (in MEM transactions) for address translation to proceed. Only Valid when the
73242  *    CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
73243  */
73244 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MASK)
73245 
73246 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
73247 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
73248 /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
73249  *    be translated to a single address location as determined by the target address register of the
73250  *    iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
73251  *    Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
73252  */
73253 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MASK)
73254 
73255 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MASK (0x3000000U)
73256 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SHIFT (24U)
73257 /*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
73258  *    region. This overrides the normal RADM filter response. Note that this feature is not available
73259  *    for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
73260  *    response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
73261  *    / undefined / reserved. Note: This register field is sticky.
73262  */
73263 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MASK)
73264 
73265 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
73266 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
73267 /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
73268  *    the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
73269  *    identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
73270  *    The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
73271  *    For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
73272  *    inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
73273  */
73274 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MASK)
73275 
73276 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MASK (0x10000000U)
73277 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SHIFT (28U)
73278 /*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
73279  *    configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
73280  *    allows a CFG configuration space to be located in any 256MB window of your application memory space
73281  *    using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
73282  *    bits [27:12] of the translated address. Note: This register field is sticky.
73283  */
73284 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MASK)
73285 
73286 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MASK (0x20000000U)
73287 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SHIFT (29U)
73288 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
73289  *    address match occurs when the untranslated address is in the region outside the defined range (Base
73290  *    Address to Limit Address). Note: This register field is sticky.
73291  */
73292 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MASK)
73293 
73294 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MASK (0x40000000U)
73295 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SHIFT (30U)
73296 /*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
73297  *    of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
73298  *    0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
73299  *    Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
73300  *    "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
73301  *    follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
73302  *    header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
73303  *    transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
73304  *    to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
73305  *    routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
73306  *    processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
73307  *    0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
73308  *    MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
73309  *    Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
73310  *    the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
73311  *    but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
73312  *    [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
73313  *    lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
73314  *    information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
73315  *    1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
73316  */
73317 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MASK)
73318 
73319 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MASK (0x80000000U)
73320 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SHIFT (31U)
73321 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
73322 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MASK)
73323 /*! @} */
73324 
73325 /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_1 - iATU Lower Base Address Register. */
73326 /*! @{ */
73327 
73328 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MASK (0xFFFFU)
73329 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SHIFT (0U)
73330 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
73331  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73332  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73333  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
73334  */
73335 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MASK)
73336 
73337 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MASK (0xFFFF0000U)
73338 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SHIFT (16U)
73339 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
73340  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
73341  */
73342 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MASK)
73343 /*! @} */
73344 
73345 /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_1 - iATU Upper Base Address Register. */
73346 /*! @{ */
73347 
73348 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
73349 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SHIFT (0U)
73350 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
73351  *    translated. Note: This register field is sticky.
73352  */
73353 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MASK)
73354 /*! @} */
73355 
73356 /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_1 - iATU Limit Address Register. */
73357 /*! @{ */
73358 
73359 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MASK (0xFFFFU)
73360 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SHIFT (0U)
73361 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
73362  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73363  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73364  */
73365 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MASK)
73366 
73367 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
73368 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SHIFT (16U)
73369 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
73370  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73371  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73372  *    Note: This register field is sticky.
73373  */
73374 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MASK)
73375 /*! @} */
73376 
73377 /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_1 - iATU Lower Target Address Register. */
73378 /*! @{ */
73379 
73380 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MASK (0xFFFFU)
73381 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SHIFT (0U)
73382 /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
73383  *    region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
73384  *    kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
73385  *    these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
73386  *    target address must align to the iATU region size; otherwise it must align to the BAR size. A
73387  *    write to this location is ignored by the PCIe controller. - Field size depends on
73388  *    log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
73389  *    log2(BAR_MASK+1) in BAR match mode.
73390  */
73391 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MASK)
73392 
73393 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MASK (0xFFFF0000U)
73394 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SHIFT (16U)
73395 /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
73396  *    region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
73397  *    of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
73398  *    mode. Note: This register field is sticky.
73399  */
73400 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MASK)
73401 /*! @} */
73402 
73403 /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_2 - iATU Region Control 1 Register. */
73404 /*! @{ */
73405 
73406 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MASK (0x1FU)
73407 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SHIFT (0U)
73408 /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
73409  *    TLP is changed to the value in this register. Note: This register field is sticky.
73410  */
73411 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MASK)
73412 
73413 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MASK (0xE0U)
73414 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SHIFT (5U)
73415 /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
73416  *    is changed to the value in this register. Note: This register field is sticky.
73417  */
73418 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MASK)
73419 
73420 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MASK (0x100U)
73421 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SHIFT (8U)
73422 /*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
73423  *    is changed to the value in this register. Note: This register field is sticky.
73424  */
73425 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MASK)
73426 
73427 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MASK (0x600U)
73428 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SHIFT (9U)
73429 /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
73430  *    TLP is changed to the value in this register. Note: This register field is sticky.
73431  */
73432 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MASK)
73433 
73434 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MASK (0x2000U)
73435 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SHIFT (13U)
73436 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
73437  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
73438  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
73439  */
73440 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MASK)
73441 
73442 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MASK (0x700000U)
73443 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SHIFT (20U)
73444 /*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
73445  *    region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
73446  *    used in generating the function part of the requester ID (RID) field of the TLP is taken from
73447  *    this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
73448  *    the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
73449  *    field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
73450  *    "Max_Payload_Size" values are used. Note: This register field is sticky.
73451  */
73452 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MASK)
73453 /*! @} */
73454 
73455 /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_2 - iATU Region Control 2 Register. */
73456 /*! @{ */
73457 
73458 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MASK (0xFFU)
73459 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SHIFT (0U)
73460 /*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
73461  *    region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
73462  *    changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
73463  *    outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
73464  *    then the ST field of the TLP is changed to the value in this register. Only Valid when the
73465  *    CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
73466  */
73467 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MASK)
73468 
73469 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MASK (0xFF00U)
73470 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SHIFT (8U)
73471 /*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
73472  *    is set. Note: This register field is sticky.
73473  */
73474 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MASK)
73475 
73476 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MASK (0x10000U)
73477 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SHIFT (16U)
73478 /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
73479  *    substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
73480  *    this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
73481  *    Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
73482  *    in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
73483  *    field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
73484  */
73485 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MASK)
73486 
73487 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MASK (0x80000U)
73488 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SHIFT (19U)
73489 /*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
73490  *    translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
73491  *    field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
73492  *    Note: This register field is sticky.
73493  */
73494 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MASK)
73495 
73496 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MASK (0x100000U)
73497 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SHIFT (20U)
73498 /*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
73499  *    Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
73500  *    Non-Posted Requests outstanding. Note: This register field is sticky.
73501  */
73502 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MASK)
73503 
73504 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MASK (0x400000U)
73505 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SHIFT (22U)
73506 /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
73507  *    TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
73508  *    having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
73509  *    inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
73510  *    a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
73511  *    sent. Note: This register field is sticky.
73512  */
73513 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MASK)
73514 
73515 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
73516 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SHIFT (23U)
73517 /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
73518  *    iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
73519  *    the outbound TLP header with the contents of the LWR_TARGET_RW field in
73520  *    IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
73521  *    to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
73522  *    translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
73523  *    forms the new address of the translated region. Note: This register field is sticky.
73524  */
73525 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MASK)
73526 
73527 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MASK (0x8000000U)
73528 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SHIFT (27U)
73529 /*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
73530  *    pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
73531  *    set it to '0'. Note: This register field is sticky.
73532  */
73533 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MASK)
73534 
73535 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MASK (0x10000000U)
73536 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SHIFT (28U)
73537 /*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
73538  *    XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
73539  *    TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
73540  *    of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
73541  *    TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
73542  *    of the PCIe configuration space. Note: This register field is sticky.
73543  */
73544 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MASK)
73545 
73546 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MASK (0x20000000U)
73547 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SHIFT (29U)
73548 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
73549  *    address match occurs when the untranslated address is in the region outside the defined range (Base
73550  *    Address to Limit Address). Note: This register field is sticky.
73551  */
73552 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MASK)
73553 
73554 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MASK (0x80000000U)
73555 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SHIFT (31U)
73556 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
73557 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MASK)
73558 /*! @} */
73559 
73560 /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2 - iATU Lower Base Address Register. */
73561 /*! @{ */
73562 
73563 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MASK (0xFFFFU)
73564 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SHIFT (0U)
73565 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
73566  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73567  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73568  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
73569  */
73570 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MASK)
73571 
73572 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MASK (0xFFFF0000U)
73573 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SHIFT (16U)
73574 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
73575  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
73576  */
73577 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MASK)
73578 /*! @} */
73579 
73580 /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2 - iATU Upper Base Address Register. */
73581 /*! @{ */
73582 
73583 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
73584 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SHIFT (0U)
73585 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
73586  *    translated. In systems with a 32-bit address space, this register is not used and therefore
73587  *    writing to this register has no effect. Note: This register field is sticky.
73588  */
73589 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MASK)
73590 /*! @} */
73591 
73592 /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_2 - iATU Limit Address Register. */
73593 /*! @{ */
73594 
73595 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MASK (0xFFFFU)
73596 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SHIFT (0U)
73597 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
73598  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73599  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73600  */
73601 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MASK)
73602 
73603 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
73604 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SHIFT (16U)
73605 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
73606  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73607  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73608  *    Note: This register field is sticky.
73609  */
73610 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MASK)
73611 /*! @} */
73612 
73613 /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2 - iATU Lower Target Address Register. */
73614 /*! @{ */
73615 
73616 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
73617 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
73618 /*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
73619  *    (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
73620  *    address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
73621  *    aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
73622  *    the start address of the new address of the translated region (bits n-1:0) are always '0'). -
73623  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
73624  *    IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
73625  *    header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
73626  *    the transmission of Vendor Defined Messages where the controller determines the content of
73627  *    bytes 12 to 15 of the TLP header. Note: This register field is sticky.
73628  */
73629 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MASK)
73630 /*! @} */
73631 
73632 /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2 - iATU Upper Target Address Register. */
73633 /*! @{ */
73634 
73635 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
73636 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SHIFT (0U)
73637 /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
73638  *    of the translated region. Note: This register field is sticky.
73639  */
73640 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MASK)
73641 /*! @} */
73642 
73643 /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_2 - iATU Region Control 1 Register. */
73644 /*! @{ */
73645 
73646 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MASK (0x1FU)
73647 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SHIFT (0U)
73648 /*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
73649  *    proceeds (when all other enabled field-matches are successful). Note: This register field is
73650  *    sticky.
73651  */
73652 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MASK)
73653 
73654 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MASK (0xE0U)
73655 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SHIFT (5U)
73656 /*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
73657  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
73658  *    the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
73659  *    sticky.
73660  */
73661 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MASK)
73662 
73663 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MASK (0x100U)
73664 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SHIFT (8U)
73665 /*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
73666  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
73667  *    the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
73668  *    sticky.
73669  */
73670 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MASK)
73671 
73672 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MASK (0x600U)
73673 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SHIFT (9U)
73674 /*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
73675  *    proceeds (when all other enabled field-matches are successful). This check is only performed
73676  *    if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
73677  *    field is sticky.
73678  */
73679 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MASK)
73680 
73681 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MASK (0x2000U)
73682 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SHIFT (13U)
73683 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
73684  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
73685  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
73686  */
73687 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MASK)
73688 
73689 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MASK (0x700000U)
73690 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SHIFT (20U)
73691 /*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
73692  *    controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
73693  *    this value, then address translation proceeds. This check is only performed if the "Function
73694  *    Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
73695  *    destination function number as specified in the routing ID of the TLP header matches the function, then
73696  *    address translation proceeds. This check is only performed if the "Function Number Match
73697  *    Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
73698  */
73699 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MASK)
73700 /*! @} */
73701 
73702 /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_2 - iATU Region Control 2 Register. */
73703 /*! @{ */
73704 
73705 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MASK (0xFFU)
73706 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SHIFT (0U)
73707 /*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
73708  *    to this value, then address translation proceeds (when all other enabled field-matches are
73709  *    successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
73710  *    Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
73711  *    matched to this value, then address translation proceeds. This check is only performed if the
73712  *    "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
73713  *    the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
73714  *    Note: This register field is sticky.
73715  */
73716 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MASK)
73717 
73718 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MASK (0x700U)
73719 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SHIFT (8U)
73720 /*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
73721  *    normal internal BAR address matching mechanism " is the same as this field, address translation
73722  *    proceeds (when all other enabled field-matches are successful). This check is only performed
73723  *    if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
73724  *    010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
73725  *    translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
73726  *    the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
73727  *    sticky.
73728  */
73729 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MASK)
73730 
73731 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
73732 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SHIFT (13U)
73733 /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
73734  *    translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
73735  *    iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
73736  *    mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
73737  *    translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
73738  *    This register field is sticky.
73739  */
73740 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MASK)
73741 
73742 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MASK (0x4000U)
73743 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SHIFT (14U)
73744 /*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
73745  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
73746  *    register field is sticky.
73747  */
73748 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MASK)
73749 
73750 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MASK (0x8000U)
73751 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SHIFT (15U)
73752 /*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
73753  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
73754  *    register field is sticky.
73755  */
73756 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MASK)
73757 
73758 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MASK (0x10000U)
73759 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SHIFT (16U)
73760 /*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
73761  *    (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
73762  *    Note: This register field is sticky.
73763  */
73764 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MASK)
73765 
73766 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MASK (0x80000U)
73767 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SHIFT (19U)
73768 /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
73769  *    field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
73770  *    MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
73771  *    field is sticky.
73772  */
73773 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MASK)
73774 
73775 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MASK (0x200000U)
73776 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SHIFT (21U)
73777 /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
73778  *    TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
73779  *    (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
73780  *    that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
73781  *    occurs (in MEM transactions) for address translation to proceed. Only Valid when the
73782  *    CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
73783  */
73784 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MASK)
73785 
73786 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
73787 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
73788 /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
73789  *    be translated to a single address location as determined by the target address register of the
73790  *    iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
73791  *    Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
73792  */
73793 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MASK)
73794 
73795 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MASK (0x3000000U)
73796 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SHIFT (24U)
73797 /*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
73798  *    region. This overrides the normal RADM filter response. Note that this feature is not available
73799  *    for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
73800  *    response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
73801  *    / undefined / reserved. Note: This register field is sticky.
73802  */
73803 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MASK)
73804 
73805 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
73806 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
73807 /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
73808  *    the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
73809  *    identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
73810  *    The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
73811  *    For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
73812  *    inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
73813  */
73814 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MASK)
73815 
73816 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MASK (0x10000000U)
73817 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SHIFT (28U)
73818 /*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
73819  *    configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
73820  *    allows a CFG configuration space to be located in any 256MB window of your application memory space
73821  *    using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
73822  *    bits [27:12] of the translated address. Note: This register field is sticky.
73823  */
73824 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MASK)
73825 
73826 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MASK (0x20000000U)
73827 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SHIFT (29U)
73828 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
73829  *    address match occurs when the untranslated address is in the region outside the defined range (Base
73830  *    Address to Limit Address). Note: This register field is sticky.
73831  */
73832 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MASK)
73833 
73834 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MASK (0x40000000U)
73835 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SHIFT (30U)
73836 /*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
73837  *    of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
73838  *    0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
73839  *    Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
73840  *    "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
73841  *    follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
73842  *    header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
73843  *    transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
73844  *    to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
73845  *    routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
73846  *    processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
73847  *    0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
73848  *    MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
73849  *    Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
73850  *    the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
73851  *    but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
73852  *    [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
73853  *    lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
73854  *    information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
73855  *    1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
73856  */
73857 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MASK)
73858 
73859 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MASK (0x80000000U)
73860 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SHIFT (31U)
73861 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
73862 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MASK)
73863 /*! @} */
73864 
73865 /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_2 - iATU Lower Base Address Register. */
73866 /*! @{ */
73867 
73868 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MASK (0xFFFFU)
73869 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SHIFT (0U)
73870 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
73871  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73872  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73873  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
73874  */
73875 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MASK)
73876 
73877 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MASK (0xFFFF0000U)
73878 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SHIFT (16U)
73879 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
73880  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
73881  */
73882 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MASK)
73883 /*! @} */
73884 
73885 /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_2 - iATU Upper Base Address Register. */
73886 /*! @{ */
73887 
73888 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
73889 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SHIFT (0U)
73890 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
73891  *    translated. Note: This register field is sticky.
73892  */
73893 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MASK)
73894 /*! @} */
73895 
73896 /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_2 - iATU Limit Address Register. */
73897 /*! @{ */
73898 
73899 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MASK (0xFFFFU)
73900 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SHIFT (0U)
73901 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
73902  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73903  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73904  */
73905 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MASK)
73906 
73907 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
73908 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SHIFT (16U)
73909 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
73910  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
73911  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
73912  *    Note: This register field is sticky.
73913  */
73914 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MASK)
73915 /*! @} */
73916 
73917 /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_2 - iATU Lower Target Address Register. */
73918 /*! @{ */
73919 
73920 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MASK (0xFFFFU)
73921 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SHIFT (0U)
73922 /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
73923  *    region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
73924  *    kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
73925  *    these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
73926  *    target address must align to the iATU region size; otherwise it must align to the BAR size. A
73927  *    write to this location is ignored by the PCIe controller. - Field size depends on
73928  *    log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
73929  *    log2(BAR_MASK+1) in BAR match mode.
73930  */
73931 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MASK)
73932 
73933 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MASK (0xFFFF0000U)
73934 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SHIFT (16U)
73935 /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
73936  *    region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
73937  *    of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
73938  *    mode. Note: This register field is sticky.
73939  */
73940 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MASK)
73941 /*! @} */
73942 
73943 /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_3 - iATU Region Control 1 Register. */
73944 /*! @{ */
73945 
73946 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MASK (0x1FU)
73947 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SHIFT (0U)
73948 /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
73949  *    TLP is changed to the value in this register. Note: This register field is sticky.
73950  */
73951 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MASK)
73952 
73953 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MASK (0xE0U)
73954 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SHIFT (5U)
73955 /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
73956  *    is changed to the value in this register. Note: This register field is sticky.
73957  */
73958 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MASK)
73959 
73960 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MASK (0x100U)
73961 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SHIFT (8U)
73962 /*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
73963  *    is changed to the value in this register. Note: This register field is sticky.
73964  */
73965 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MASK)
73966 
73967 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MASK (0x600U)
73968 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SHIFT (9U)
73969 /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
73970  *    TLP is changed to the value in this register. Note: This register field is sticky.
73971  */
73972 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MASK)
73973 
73974 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MASK (0x2000U)
73975 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SHIFT (13U)
73976 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
73977  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
73978  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
73979  */
73980 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MASK)
73981 
73982 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MASK (0x700000U)
73983 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SHIFT (20U)
73984 /*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
73985  *    region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
73986  *    used in generating the function part of the requester ID (RID) field of the TLP is taken from
73987  *    this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
73988  *    the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
73989  *    field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
73990  *    "Max_Payload_Size" values are used. Note: This register field is sticky.
73991  */
73992 #define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MASK)
73993 /*! @} */
73994 
73995 /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_3 - iATU Region Control 2 Register. */
73996 /*! @{ */
73997 
73998 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MASK (0xFFU)
73999 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SHIFT (0U)
74000 /*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
74001  *    region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
74002  *    changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
74003  *    outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
74004  *    then the ST field of the TLP is changed to the value in this register. Only Valid when the
74005  *    CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
74006  */
74007 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MASK)
74008 
74009 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MASK (0xFF00U)
74010 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SHIFT (8U)
74011 /*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
74012  *    is set. Note: This register field is sticky.
74013  */
74014 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MASK)
74015 
74016 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MASK (0x10000U)
74017 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SHIFT (16U)
74018 /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
74019  *    substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
74020  *    this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
74021  *    Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
74022  *    in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
74023  *    field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
74024  */
74025 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MASK)
74026 
74027 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MASK (0x80000U)
74028 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SHIFT (19U)
74029 /*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
74030  *    translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
74031  *    field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
74032  *    Note: This register field is sticky.
74033  */
74034 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MASK)
74035 
74036 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MASK (0x100000U)
74037 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SHIFT (20U)
74038 /*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
74039  *    Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
74040  *    Non-Posted Requests outstanding. Note: This register field is sticky.
74041  */
74042 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MASK)
74043 
74044 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MASK (0x400000U)
74045 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SHIFT (22U)
74046 /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
74047  *    TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
74048  *    having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
74049  *    inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
74050  *    a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
74051  *    sent. Note: This register field is sticky.
74052  */
74053 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MASK)
74054 
74055 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
74056 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SHIFT (23U)
74057 /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
74058  *    iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
74059  *    the outbound TLP header with the contents of the LWR_TARGET_RW field in
74060  *    IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
74061  *    to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
74062  *    translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
74063  *    forms the new address of the translated region. Note: This register field is sticky.
74064  */
74065 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MASK)
74066 
74067 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MASK (0x8000000U)
74068 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SHIFT (27U)
74069 /*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
74070  *    pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
74071  *    set it to '0'. Note: This register field is sticky.
74072  */
74073 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MASK)
74074 
74075 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MASK (0x10000000U)
74076 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SHIFT (28U)
74077 /*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
74078  *    XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
74079  *    TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
74080  *    of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
74081  *    TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
74082  *    of the PCIe configuration space. Note: This register field is sticky.
74083  */
74084 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MASK)
74085 
74086 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MASK (0x20000000U)
74087 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SHIFT (29U)
74088 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
74089  *    address match occurs when the untranslated address is in the region outside the defined range (Base
74090  *    Address to Limit Address). Note: This register field is sticky.
74091  */
74092 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MASK)
74093 
74094 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MASK (0x80000000U)
74095 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SHIFT (31U)
74096 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
74097 #define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MASK)
74098 /*! @} */
74099 
74100 /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3 - iATU Lower Base Address Register. */
74101 /*! @{ */
74102 
74103 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MASK (0xFFFFU)
74104 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SHIFT (0U)
74105 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
74106  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
74107  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
74108  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
74109  */
74110 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MASK)
74111 
74112 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MASK (0xFFFF0000U)
74113 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SHIFT (16U)
74114 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
74115  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
74116  */
74117 #define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MASK)
74118 /*! @} */
74119 
74120 /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3 - iATU Upper Base Address Register. */
74121 /*! @{ */
74122 
74123 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
74124 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SHIFT (0U)
74125 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
74126  *    translated. In systems with a 32-bit address space, this register is not used and therefore
74127  *    writing to this register has no effect. Note: This register field is sticky.
74128  */
74129 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MASK)
74130 /*! @} */
74131 
74132 /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_3 - iATU Limit Address Register. */
74133 /*! @{ */
74134 
74135 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MASK (0xFFFFU)
74136 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SHIFT (0U)
74137 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
74138  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
74139  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
74140  */
74141 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MASK)
74142 
74143 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
74144 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SHIFT (16U)
74145 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
74146  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
74147  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
74148  *    Note: This register field is sticky.
74149  */
74150 #define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MASK)
74151 /*! @} */
74152 
74153 /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3 - iATU Lower Target Address Register. */
74154 /*! @{ */
74155 
74156 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
74157 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
74158 /*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
74159  *    (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
74160  *    address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
74161  *    aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
74162  *    the start address of the new address of the translated region (bits n-1:0) are always '0'). -
74163  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
74164  *    IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
74165  *    header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
74166  *    the transmission of Vendor Defined Messages where the controller determines the content of
74167  *    bytes 12 to 15 of the TLP header. Note: This register field is sticky.
74168  */
74169 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MASK)
74170 /*! @} */
74171 
74172 /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3 - iATU Upper Target Address Register. */
74173 /*! @{ */
74174 
74175 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
74176 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SHIFT (0U)
74177 /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
74178  *    of the translated region. Note: This register field is sticky.
74179  */
74180 #define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MASK)
74181 /*! @} */
74182 
74183 /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_3 - iATU Region Control 1 Register. */
74184 /*! @{ */
74185 
74186 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MASK (0x1FU)
74187 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SHIFT (0U)
74188 /*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
74189  *    proceeds (when all other enabled field-matches are successful). Note: This register field is
74190  *    sticky.
74191  */
74192 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MASK)
74193 
74194 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MASK (0xE0U)
74195 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SHIFT (5U)
74196 /*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
74197  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
74198  *    the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
74199  *    sticky.
74200  */
74201 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MASK)
74202 
74203 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MASK (0x100U)
74204 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SHIFT (8U)
74205 /*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
74206  *    proceeds (when all other enabled field-matches are successful). This check is only performed if
74207  *    the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
74208  *    sticky.
74209  */
74210 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MASK)
74211 
74212 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MASK (0x600U)
74213 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SHIFT (9U)
74214 /*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
74215  *    proceeds (when all other enabled field-matches are successful). This check is only performed
74216  *    if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
74217  *    field is sticky.
74218  */
74219 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MASK)
74220 
74221 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MASK (0x2000U)
74222 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SHIFT (13U)
74223 /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
74224  *    size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
74225  *    ATU Region size is 4 GB (default). Note: This register field is sticky.
74226  */
74227 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MASK)
74228 
74229 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MASK (0x700000U)
74230 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SHIFT (20U)
74231 /*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
74232  *    controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
74233  *    this value, then address translation proceeds. This check is only performed if the "Function
74234  *    Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
74235  *    destination function number as specified in the routing ID of the TLP header matches the function, then
74236  *    address translation proceeds. This check is only performed if the "Function Number Match
74237  *    Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
74238  */
74239 #define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MASK)
74240 /*! @} */
74241 
74242 /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_3 - iATU Region Control 2 Register. */
74243 /*! @{ */
74244 
74245 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MASK (0xFFU)
74246 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SHIFT (0U)
74247 /*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
74248  *    to this value, then address translation proceeds (when all other enabled field-matches are
74249  *    successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
74250  *    Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
74251  *    matched to this value, then address translation proceeds. This check is only performed if the
74252  *    "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
74253  *    the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
74254  *    Note: This register field is sticky.
74255  */
74256 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MASK)
74257 
74258 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MASK (0x700U)
74259 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SHIFT (8U)
74260 /*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
74261  *    normal internal BAR address matching mechanism " is the same as this field, address translation
74262  *    proceeds (when all other enabled field-matches are successful). This check is only performed
74263  *    if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
74264  *    010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
74265  *    translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
74266  *    the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
74267  *    sticky.
74268  */
74269 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MASK)
74270 
74271 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
74272 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SHIFT (13U)
74273 /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
74274  *    translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
74275  *    iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
74276  *    mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
74277  *    translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
74278  *    This register field is sticky.
74279  */
74280 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MASK)
74281 
74282 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MASK (0x4000U)
74283 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SHIFT (14U)
74284 /*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
74285  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
74286  *    register field is sticky.
74287  */
74288 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MASK)
74289 
74290 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MASK (0x8000U)
74291 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SHIFT (15U)
74292 /*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
74293  *    field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
74294  *    register field is sticky.
74295  */
74296 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MASK)
74297 
74298 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MASK (0x10000U)
74299 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SHIFT (16U)
74300 /*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
74301  *    (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
74302  *    Note: This register field is sticky.
74303  */
74304 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MASK)
74305 
74306 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MASK (0x80000U)
74307 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SHIFT (19U)
74308 /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
74309  *    field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
74310  *    MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
74311  *    field is sticky.
74312  */
74313 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MASK)
74314 
74315 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MASK (0x200000U)
74316 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SHIFT (21U)
74317 /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
74318  *    TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
74319  *    (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
74320  *    that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
74321  *    occurs (in MEM transactions) for address translation to proceed. Only Valid when the
74322  *    CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
74323  */
74324 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MASK)
74325 
74326 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
74327 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
74328 /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
74329  *    be translated to a single address location as determined by the target address register of the
74330  *    iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
74331  *    Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
74332  */
74333 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MASK)
74334 
74335 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MASK (0x3000000U)
74336 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SHIFT (24U)
74337 /*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
74338  *    region. This overrides the normal RADM filter response. Note that this feature is not available
74339  *    for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
74340  *    response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
74341  *    / undefined / reserved. Note: This register field is sticky.
74342  */
74343 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MASK)
74344 
74345 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
74346 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
74347 /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
74348  *    the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
74349  *    identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
74350  *    The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
74351  *    For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
74352  *    inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
74353  */
74354 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MASK)
74355 
74356 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MASK (0x10000000U)
74357 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SHIFT (28U)
74358 /*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
74359  *    configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
74360  *    allows a CFG configuration space to be located in any 256MB window of your application memory space
74361  *    using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
74362  *    bits [27:12] of the translated address. Note: This register field is sticky.
74363  */
74364 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MASK)
74365 
74366 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MASK (0x20000000U)
74367 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SHIFT (29U)
74368 /*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
74369  *    address match occurs when the untranslated address is in the region outside the defined range (Base
74370  *    Address to Limit Address). Note: This register field is sticky.
74371  */
74372 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MASK)
74373 
74374 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MASK (0x40000000U)
74375 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SHIFT (30U)
74376 /*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
74377  *    of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
74378  *    0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
74379  *    Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
74380  *    "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
74381  *    follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
74382  *    header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
74383  *    transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
74384  *    to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
74385  *    routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
74386  *    processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
74387  *    0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
74388  *    MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
74389  *    Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
74390  *    the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
74391  *    but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
74392  *    [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
74393  *    lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
74394  *    information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
74395  *    1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
74396  */
74397 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MASK)
74398 
74399 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MASK (0x80000000U)
74400 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SHIFT (31U)
74401 /*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky. */
74402 #define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MASK)
74403 /*! @} */
74404 
74405 /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_3 - iATU Lower Base Address Register. */
74406 /*! @{ */
74407 
74408 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MASK (0xFFFFU)
74409 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SHIFT (0U)
74410 /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
74411  *    The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
74412  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
74413  *    n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
74414  */
74415 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MASK)
74416 
74417 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MASK (0xFFFF0000U)
74418 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SHIFT (16U)
74419 /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
74420  *    is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
74421  */
74422 #define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MASK)
74423 /*! @} */
74424 
74425 /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_3 - iATU Upper Base Address Register. */
74426 /*! @{ */
74427 
74428 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
74429 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SHIFT (0U)
74430 /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
74431  *    translated. Note: This register field is sticky.
74432  */
74433 #define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MASK)
74434 /*! @} */
74435 
74436 /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_3 - iATU Limit Address Register. */
74437 /*! @{ */
74438 
74439 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MASK (0xFFFFU)
74440 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SHIFT (0U)
74441 /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
74442  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
74443  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
74444  */
74445 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MASK)
74446 
74447 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
74448 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SHIFT (16U)
74449 /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
74450  *    end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
74451  *    boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
74452  *    Note: This register field is sticky.
74453  */
74454 #define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MASK)
74455 /*! @} */
74456 
74457 /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_3 - iATU Lower Target Address Register. */
74458 /*! @{ */
74459 
74460 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MASK (0xFFFFU)
74461 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SHIFT (0U)
74462 /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
74463  *    region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
74464  *    kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
74465  *    these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
74466  *    target address must align to the iATU region size; otherwise it must align to the BAR size. A
74467  *    write to this location is ignored by the PCIe controller. - Field size depends on
74468  *    log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
74469  *    log2(BAR_MASK+1) in BAR match mode.
74470  */
74471 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MASK)
74472 
74473 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MASK (0xFFFF0000U)
74474 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SHIFT (16U)
74475 /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
74476  *    region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
74477  *    of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
74478  *    mode. Note: This register field is sticky.
74479  */
74480 #define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MASK)
74481 /*! @} */
74482 
74483 /*! @name DMA_CTRL_DATA_ARB_PRIOR_OFF - DMA Arbitration Scheme for TRGT1 Interface. */
74484 /*! @{ */
74485 
74486 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MASK (0x7U)
74487 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SHIFT (0U)
74488 /*! RTRGT1_WEIGHT - Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Dbi: R/W */
74489 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MASK)
74490 
74491 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MASK (0x38U)
74492 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SHIFT (3U)
74493 /*! WR_CTRL_TRGT_WEIGHT - DMA Write Channel MRd Requests. For DMA data requests and LL
74494  *    element/descriptor access. Note: The access attributes of this field are as follows: - Dbi: R/W
74495  */
74496 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MASK)
74497 
74498 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MASK (0x1C0U)
74499 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SHIFT (6U)
74500 /*! RD_CTRL_TRGT_WEIGHT - DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The
74501  *    access attributes of this field are as follows: - Dbi: R/W
74502  */
74503 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MASK)
74504 
74505 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MASK (0xE00U)
74506 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SHIFT (9U)
74507 /*! RDBUFF_TRGT_WEIGHT - DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Dbi: R/W */
74508 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MASK)
74509 
74510 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MASK (0xFFFFF000U)
74511 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SHIFT (12U)
74512 /*! RSVDP_12 - Reserved for future use. */
74513 #define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MASK)
74514 /*! @} */
74515 
74516 /*! @name DMA_CTRL_OFF - DMA Number of Channels Register. */
74517 /*! @{ */
74518 
74519 #define PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MASK   (0xFU)
74520 #define PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SHIFT  (0U)
74521 /*! NUM_DMA_WR_CHAN - Number of Write Channels. You can read this register to determine the number
74522  *    of write channels the DMA controller has been configured to support.
74523  */
74524 #define PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SHIFT)) & PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MASK)
74525 
74526 #define PCIE_DMA_CTRL_OFF_RSVDP_4_MASK           (0xFFF0U)
74527 #define PCIE_DMA_CTRL_OFF_RSVDP_4_SHIFT          (4U)
74528 /*! RSVDP_4 - Reserved for future use. */
74529 #define PCIE_DMA_CTRL_OFF_RSVDP_4(x)             (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_RSVDP_4_SHIFT)) & PCIE_DMA_CTRL_OFF_RSVDP_4_MASK)
74530 
74531 #define PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MASK   (0xF0000U)
74532 #define PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SHIFT  (16U)
74533 /*! NUM_DMA_RD_CHAN - Number of Read Channels. You can read this register to determine the number of
74534  *    read channels the DMA controller has been configured to support.
74535  */
74536 #define PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN(x)     (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SHIFT)) & PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MASK)
74537 
74538 #define PCIE_DMA_CTRL_OFF_RSVDP_20_MASK          (0xF00000U)
74539 #define PCIE_DMA_CTRL_OFF_RSVDP_20_SHIFT         (20U)
74540 /*! RSVDP_20 - Reserved for future use. */
74541 #define PCIE_DMA_CTRL_OFF_RSVDP_20(x)            (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_CTRL_OFF_RSVDP_20_MASK)
74542 
74543 #define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MASK  (0x1000000U)
74544 #define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SHIFT (24U)
74545 /*! DIS_C2W_CACHE_WR - Disable DMA Write Channels "completion to memory write" context cache
74546  *    pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are
74547  *    as follows: - Dbi: R/W
74548  */
74549 #define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SHIFT)) & PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MASK)
74550 
74551 #define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MASK  (0x2000000U)
74552 #define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SHIFT (25U)
74553 /*! DIS_C2W_CACHE_RD - Disable DMA Read Channels "completion to memory write" context cache
74554  *    pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are
74555  *    as follows: - Dbi: R/W
74556  */
74557 #define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SHIFT)) & PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MASK)
74558 
74559 #define PCIE_DMA_CTRL_OFF_RSVDP_26_MASK          (0xFC000000U)
74560 #define PCIE_DMA_CTRL_OFF_RSVDP_26_SHIFT         (26U)
74561 /*! RSVDP_26 - Reserved for future use. */
74562 #define PCIE_DMA_CTRL_OFF_RSVDP_26(x)            (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_RSVDP_26_SHIFT)) & PCIE_DMA_CTRL_OFF_RSVDP_26_MASK)
74563 /*! @} */
74564 
74565 /*! @name DMA_WRITE_ENGINE_EN_OFF - DMA Write Engine Enable Register. */
74566 /*! @{ */
74567 
74568 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MASK (0x1U)
74569 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SHIFT (0U)
74570 /*! DMA_WRITE_ENGINE - DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal
74571  *    operation, you must initially set this bit to "1", before any other software setup actions. You
74572  *    do not need to toggle or rewrite to this bit during normal operation. You should set this bit
74573  *    to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible
74574  *    reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set
74575  *    (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits
74576  *    is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the
74577  *    DMA controller write logic re-initializes the control logic, ensuring that the next DMA write
74578  *    transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" ,
74579  *    after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the
74580  *    DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped."
74581  *    Resetting the DMA controller write logic re-initializes the control logic ensuring that the
74582  *    next DMA write transfer is executed successfully. - During software development, when you
74583  *    incorrectly program the DMA write engine. To "Soft Reset" the DMA controller write logic, you must:
74584  *    - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress
74585  *    TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert
74586  *    the DMA write engine enable bit. This "Soft Reset" does not clear the DMA configuration
74587  *    registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell
74588  *    Register" (DMA_WRITE_DOORBELL_OFF). Note: The access attributes of this field are as follows: - Dbi:
74589  *    R/W
74590  */
74591 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SHIFT)) & PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MASK)
74592 
74593 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MASK (0xFFFEU)
74594 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SHIFT (1U)
74595 /*! RSVDP_1 - Reserved for future use. */
74596 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SHIFT)) & PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MASK)
74597 
74598 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MASK (0xFF000000U)
74599 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SHIFT (24U)
74600 /*! RSVDP_24 - Reserved for future use. */
74601 #define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MASK)
74602 /*! @} */
74603 
74604 /*! @name DMA_WRITE_DOORBELL_OFF - DMA Write Doorbell Register. */
74605 /*! @{ */
74606 
74607 #define PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MASK (0x7U)
74608 #define PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SHIFT (0U)
74609 /*! WR_DOORBELL_NUM - Doorbell Number. You must write the channel number to this register to start
74610  *    the DMA write transfer for that channel. The DMA detects a write to this register field even if
74611  *    the value of this field does not change. You do not need to toggle or write any other value
74612  *    to this register to start a new transfer. The range of this field is 0x0 to 0x7, and 0x0
74613  *    corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1
74614  *    substates. Note: The access attributes of this field are as follows: - Dbi: R/W
74615  */
74616 #define PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SHIFT)) & PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MASK)
74617 
74618 #define PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MASK (0x7FFFFFF8U)
74619 #define PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SHIFT (3U)
74620 /*! RSVDP_3 - Reserved for future use. */
74621 #define PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SHIFT)) & PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MASK)
74622 
74623 #define PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_MASK (0x80000000U)
74624 #define PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_SHIFT (31U)
74625 /*! WR_STOP - Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops
74626  *    issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it
74627  *    is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the
74628  *    "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel
74629  *    is "Running" (transferring data). For more information, see "Stopping the DMA Transfer
74630  *    (Software Stop)." Note: The access attributes of this field are as follows: - Dbi: R/W
74631  */
74632 #define PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_SHIFT)) & PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_MASK)
74633 /*! @} */
74634 
74635 /*! @name DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF - DMA Write Engine Channel Arbitration Weight Low Register. */
74636 /*! @{ */
74637 
74638 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MASK (0x1FU)
74639 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SHIFT (0U)
74640 /*! WRITE_CHANNEL0_WEIGHT - Channel 0 Weight. The weight is initialized by software before ringing
74641  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74642  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74643  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74644  */
74645 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MASK)
74646 
74647 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MASK (0x3E0U)
74648 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SHIFT (5U)
74649 /*! WRITE_CHANNEL1_WEIGHT - Channel 1 Weight. The weight is initialized by software before ringing
74650  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74651  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74652  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74653  */
74654 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MASK)
74655 
74656 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MASK (0x7C00U)
74657 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SHIFT (10U)
74658 /*! WRITE_CHANNEL2_WEIGHT - Channel 2 Weight. The weight is initialized by software before ringing
74659  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74660  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74661  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74662  */
74663 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MASK)
74664 
74665 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MASK (0xF8000U)
74666 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SHIFT (15U)
74667 /*! WRITE_CHANNEL3_WEIGHT - Channel 3 Weight. The weight is initialized by software before ringing
74668  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74669  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74670  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74671  */
74672 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MASK)
74673 
74674 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK (0xFFF00000U)
74675 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT (20U)
74676 /*! RSVDP_20 - Reserved for future use. */
74677 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK)
74678 /*! @} */
74679 
74680 /*! @name DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF - DMA Write Engine Channel Arbitration Weight High Register. */
74681 /*! @{ */
74682 
74683 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MASK (0x1FU)
74684 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SHIFT (0U)
74685 /*! WRITE_CHANNEL4_WEIGHT - Channel 4 Weight. The weight is initialized by software before ringing
74686  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74687  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74688  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74689  */
74690 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MASK)
74691 
74692 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MASK (0x3E0U)
74693 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SHIFT (5U)
74694 /*! WRITE_CHANNEL5_WEIGHT - Channel 5 Weight. The weight is initialized by software before ringing
74695  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74696  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74697  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74698  */
74699 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MASK)
74700 
74701 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MASK (0x7C00U)
74702 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SHIFT (10U)
74703 /*! WRITE_CHANNEL6_WEIGHT - Channel 6 Weight. The weight is initialized by software before ringing
74704  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74705  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74706  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74707  */
74708 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MASK)
74709 
74710 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MASK (0xF8000U)
74711 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SHIFT (15U)
74712 /*! WRITE_CHANNEL7_WEIGHT - Channel 7 Weight. The weight is initialized by software before ringing
74713  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74714  *    channel read request. A value of '0' means that one TLP is issued before moving to the next
74715  *    channel. Note: The access attributes of this field are as follows: - Dbi: R/W
74716  */
74717 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MASK)
74718 
74719 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK (0xFFF00000U)
74720 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT (20U)
74721 /*! RSVDP_20 - Reserved for future use. */
74722 #define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK)
74723 /*! @} */
74724 
74725 /*! @name DMA_READ_ENGINE_EN_OFF - DMA Read Engine Enable Register. */
74726 /*! @{ */
74727 
74728 #define PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MASK (0x1U)
74729 #define PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SHIFT (0U)
74730 /*! DMA_READ_ENGINE - DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal
74731  *    operation, you must initially set this bit to "1", before any other software setup actions. You do
74732  *    not need to toggle or rewrite to this bit during normal operation. You should set this field
74733  *    to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible
74734  *    reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set
74735  *    (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in
74736  *    the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the
74737  *    DMA controller read logic re-initializes the control logic, ensuring that the next DMA read
74738  *    transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit",
74739  *    after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA
74740  *    read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped".
74741  *    Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA
74742  *    read transfer is executed successfully. - During software development, when you incorrectly
74743  *    program the DMA read engine. To "Soft Reset" the DMA controller read logic, you must: -
74744  *    De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP
74745  *    transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA
74746  *    read engine enable bit. This "Soft Reset" does not clear the DMA configuration registers. The
74747  *    DMA read transfer does not start until you write to the "DMA Read Doorbell Register"
74748  *    (DMA_READ_DOORBELL_OFF). Note: The access attributes of this field are as follows: - Dbi: R/W
74749  */
74750 #define PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SHIFT)) & PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MASK)
74751 
74752 #define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MASK (0xFFFEU)
74753 #define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SHIFT (1U)
74754 /*! RSVDP_1 - Reserved for future use. */
74755 #define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SHIFT)) & PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MASK)
74756 
74757 #define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MASK (0xFF000000U)
74758 #define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SHIFT (24U)
74759 /*! RSVDP_24 - Reserved for future use. */
74760 #define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MASK)
74761 /*! @} */
74762 
74763 /*! @name DMA_READ_DOORBELL_OFF - DMA Read Doorbell Register. */
74764 /*! @{ */
74765 
74766 #define PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MASK (0x7U)
74767 #define PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SHIFT (0U)
74768 /*! RD_DOORBELL_NUM - Doorbell Number. You must write 0x0 to this register to start the DMA read
74769  *    transfer for that channel. The DMA detects a write to this register field even if the value of
74770  *    this field does not change. The range of this field is 0x0 to 0x7, and 0x0 corresponds to
74771  *    channel 0. Also note that a write to this field triggers the controller to exit L1 substates. Note:
74772  *    The access attributes of this field are as follows: - Dbi: R/W
74773  */
74774 #define PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SHIFT)) & PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MASK)
74775 
74776 #define PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_MASK  (0x7FFFFFF8U)
74777 #define PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_SHIFT (3U)
74778 /*! RSVDP_3 - Reserved for future use. */
74779 #define PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_SHIFT)) & PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_MASK)
74780 
74781 #define PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_MASK  (0x80000000U)
74782 #define PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_SHIFT (31U)
74783 /*! RD_STOP - Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops
74784  *    issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it
74785  *    is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the
74786  *    "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel
74787  *    is "Running" (transferring data). For more information, see "Stopping the DMA Transfer
74788  *    (Software Stop)". Note: The access attributes of this field are as follows: - Dbi: R/W
74789  */
74790 #define PCIE_DMA_READ_DOORBELL_OFF_RD_STOP(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_SHIFT)) & PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_MASK)
74791 /*! @} */
74792 
74793 /*! @name DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF - DMA Read Engine Channel Arbitration Weight Low Register. */
74794 /*! @{ */
74795 
74796 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MASK (0x1FU)
74797 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SHIFT (0U)
74798 /*! READ_CHANNEL0_WEIGHT - Channel 0 Weight. The weight is initialized by software before ringing
74799  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74800  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74801  */
74802 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MASK)
74803 
74804 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MASK (0x3E0U)
74805 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SHIFT (5U)
74806 /*! READ_CHANNEL1_WEIGHT - Channel 1 Weight. The weight is initialized by software before ringing
74807  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74808  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74809  */
74810 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MASK)
74811 
74812 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MASK (0x7C00U)
74813 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SHIFT (10U)
74814 /*! READ_CHANNEL2_WEIGHT - Channel 2 Weight. The weight is initialized by software before ringing
74815  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74816  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74817  */
74818 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MASK)
74819 
74820 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MASK (0xF8000U)
74821 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SHIFT (15U)
74822 /*! READ_CHANNEL3_WEIGHT - Channel 3 Weight. The weight is initialized by software before ringing
74823  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74824  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74825  */
74826 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MASK)
74827 
74828 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK (0xFFF00000U)
74829 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT (20U)
74830 /*! RSVDP_20 - Reserved for future use. */
74831 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK)
74832 /*! @} */
74833 
74834 /*! @name DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF - DMA Read Engine Channel Arbitration Weight High Register. */
74835 /*! @{ */
74836 
74837 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MASK (0x1FU)
74838 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SHIFT (0U)
74839 /*! READ_CHANNEL4_WEIGHT - Channel 4 Weight. The weight is initialized by software before ringing
74840  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74841  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74842  */
74843 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MASK)
74844 
74845 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MASK (0x3E0U)
74846 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SHIFT (5U)
74847 /*! READ_CHANNEL5_WEIGHT - Channel 5 Weight. The weight is initialized by software before ringing
74848  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74849  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74850  */
74851 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MASK)
74852 
74853 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MASK (0x7C00U)
74854 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SHIFT (10U)
74855 /*! READ_CHANNEL6_WEIGHT - Channel 6 Weight. The weight is initialized by software before ringing
74856  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74857  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74858  */
74859 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MASK)
74860 
74861 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MASK (0xF8000U)
74862 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SHIFT (15U)
74863 /*! READ_CHANNEL7_WEIGHT - Channel 7 Weight. The weight is initialized by software before ringing
74864  *    the doorbell. The value is used by the channel weighted round robin arbiter to select the next
74865  *    channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
74866  */
74867 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MASK)
74868 
74869 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK (0xFFF00000U)
74870 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT (20U)
74871 /*! RSVDP_20 - Reserved for future use. */
74872 #define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK)
74873 /*! @} */
74874 
74875 /*! @name DMA_WRITE_INT_STATUS_OFF - DMA Write Interrupt Status Register. */
74876 /*! @{ */
74877 
74878 #define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MASK (0xFFU)
74879 #define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SHIFT (0U)
74880 /*! WR_DONE_INT_STATUS - Done Interrupt Status. The DMA write channel has successfully completed the
74881  *    DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to
74882  *    a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and
74883  *    Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this
74884  *    register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write
74885  *    interrupt Clear register to clear this interrupt bit. Note: You can write to this register to
74886  *    emulate interrupt generation, during software or hardware testing. A write to the address triggers
74887  *    an interrupt, but the DMA does not set the Done or Abort bits in this register. Note: The
74888  *    access attributes of this field are as follows: - Dbi: R/W
74889  */
74890 #define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MASK)
74891 
74892 #define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MASK (0xFF00U)
74893 #define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SHIFT (8U)
74894 /*! RSVDP_8 - Reserved for future use. */
74895 #define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MASK)
74896 
74897 #define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MASK (0xFF0000U)
74898 #define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SHIFT (16U)
74899 /*! WR_ABORT_INT_STATUS - Abort Interrupt Status. The DMA write channel has detected an error, or
74900  *    you manually stopped the transfer as described in "Error Handling Assistance by Remote
74901  *    Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For
74902  *    details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register
74903  *    has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel
74904  *    bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write
74905  *    to this register to emulate interrupt generation, during software or hardware testing. A write
74906  *    to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this
74907  *    register. Note: The access attributes of this field are as follows: - Dbi: R/W
74908  */
74909 #define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MASK)
74910 
74911 #define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MASK (0xFF000000U)
74912 #define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SHIFT (24U)
74913 /*! RSVDP_24 - Reserved for future use. */
74914 #define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MASK)
74915 /*! @} */
74916 
74917 /*! @name DMA_WRITE_INT_MASK_OFF - DMA Write Interrupt Mask Register. */
74918 /*! @{ */
74919 
74920 #define PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MASK (0x1U)
74921 #define PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SHIFT (0U)
74922 /*! WR_DONE_INT_MASK - Done Interrupt Mask. Prevents the Done interrupt status field in the DMA
74923  *    write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA
74924  *    channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
74925  *    follows: - Dbi: R/W
74926  */
74927 #define PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MASK)
74928 
74929 #define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MASK (0xFF00U)
74930 #define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SHIFT (8U)
74931 /*! RSVDP_8 - Reserved for future use. */
74932 #define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MASK)
74933 
74934 #define PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MASK (0x10000U)
74935 #define PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SHIFT (16U)
74936 /*! WR_ABORT_INT_MASK - Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA
74937  *    write interrupt status register from asserting the edma_int output. Each bit corresponds to a
74938  *    DMA channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
74939  *    follows: - Dbi: R/W
74940  */
74941 #define PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MASK)
74942 
74943 #define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MASK (0xFF000000U)
74944 #define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SHIFT (24U)
74945 /*! RSVDP_24 - Reserved for future use. */
74946 #define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MASK)
74947 /*! @} */
74948 
74949 /*! @name DMA_WRITE_INT_CLEAR_OFF - DMA Write Interrupt Clear Register. */
74950 /*! @{ */
74951 
74952 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MASK (0x1U)
74953 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SHIFT (0U)
74954 /*! WR_DONE_INT_CLEAR - Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
74955  *    in the Done interrupt status field of the DMA write interrupt status register. Each bit
74956  *    corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this self-clearing
74957  *    register field always returns a "0".
74958  */
74959 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MASK)
74960 
74961 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MASK (0xFF00U)
74962 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SHIFT (8U)
74963 /*! RSVDP_8 - Reserved for future use. */
74964 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MASK)
74965 
74966 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MASK (0x10000U)
74967 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SHIFT (16U)
74968 /*! WR_ABORT_INT_CLEAR - Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
74969  *    in the Abort interrupt status field of the DMA write interrupt status register. Each bit
74970  *    corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this
74971  *    self-clearing register field always returns a "0".
74972  */
74973 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MASK)
74974 
74975 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MASK (0xFF000000U)
74976 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SHIFT (24U)
74977 /*! RSVDP_24 - Reserved for future use. */
74978 #define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MASK)
74979 /*! @} */
74980 
74981 /*! @name DMA_WRITE_ERR_STATUS_OFF - DMA Write Error Status Register */
74982 /*! @{ */
74983 
74984 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MASK (0xFFU)
74985 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SHIFT (0U)
74986 /*! APP_READ_ERR_DETECT - Application Read Error Detected. The DMA write channel has received an
74987  *    error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while
74988  *    reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
74989  *    Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt
74990  *    Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
74991  *    corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register"
74992  *    (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.
74993  */
74994 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MASK)
74995 
74996 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MASK (0xFF00U)
74997 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SHIFT (8U)
74998 /*! RSVDP_8 - Reserved for future use. */
74999 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MASK)
75000 
75001 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MASK (0xFF0000U)
75002 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SHIFT (16U)
75003 /*! LINKLIST_ELEMENT_FETCH_ERR_DETECT - Linked List Element Fetch Error Detected. The DMA write
75004  *    channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is
75005  *    not used) while reading a linked list element from local memory. Each bit corresponds to a
75006  *    DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and
75007  *    Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register.
75008  *    - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt
75009  *    field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error
75010  *    bit.
75011  */
75012 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MASK)
75013 
75014 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MASK (0xFF000000U)
75015 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SHIFT (24U)
75016 /*! RSVDP_24 - Reserved for future use. */
75017 #define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MASK)
75018 /*! @} */
75019 
75020 /*! @name DMA_WRITE_DONE_IMWR_LOW_OFF - DMA Write Done IMWr Address Low Register. */
75021 /*! @{ */
75022 
75023 #define PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MASK (0xFFFFFFFFU)
75024 #define PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SHIFT (0U)
75025 /*! DMA_WRITE_DONE_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field
75026  *    for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned. Note: The
75027  *    access attributes of this field are as follows: - Dbi: R/W
75028  */
75029 #define PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SHIFT)) & PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MASK)
75030 /*! @} */
75031 
75032 /*! @name DMA_WRITE_DONE_IMWR_HIGH_OFF - DMA Write Done IMWr Interrupt Address High Register. */
75033 /*! @{ */
75034 
75035 #define PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MASK (0xFFFFFFFFU)
75036 #define PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SHIFT (0U)
75037 /*! DMA_WRITE_DONE_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
75038  *    for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
75039  */
75040 #define PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SHIFT)) & PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MASK)
75041 /*! @} */
75042 
75043 /*! @name DMA_WRITE_ABORT_IMWR_LOW_OFF - DMA Write Abort IMWr Address Low Register. */
75044 /*! @{ */
75045 
75046 #define PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MASK (0xFFFFFFFFU)
75047 #define PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SHIFT (0U)
75048 /*! DMA_WRITE_ABORT_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field
75049  *    for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword
75050  *    aligned. Note: The access attributes of this field are as follows: - Dbi: R/W
75051  */
75052 #define PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SHIFT)) & PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MASK)
75053 /*! @} */
75054 
75055 /*! @name DMA_WRITE_ABORT_IMWR_HIGH_OFF - DMA Write Abort IMWr Address High Register. */
75056 /*! @{ */
75057 
75058 #define PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MASK (0xFFFFFFFFU)
75059 #define PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SHIFT (0U)
75060 /*! DMA_WRITE_ABORT_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
75061  *    for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
75062  */
75063 #define PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SHIFT)) & PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MASK)
75064 /*! @} */
75065 
75066 /*! @name DMA_WRITE_CH01_IMWR_DATA_OFF - DMA Write Channel 1 and 0 IMWr Data Register. */
75067 /*! @{ */
75068 
75069 #define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MASK (0xFFFFU)
75070 #define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SHIFT (0U)
75071 /*! WR_CHANNEL_0_DATA - The DMA uses this field to generate the data field for the Done or Abort
75072  *    IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as
75073  *    follows: - Dbi: R/W
75074  */
75075 #define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SHIFT)) & PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MASK)
75076 
75077 #define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MASK (0xFFFF0000U)
75078 #define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SHIFT (16U)
75079 /*! WR_CHANNEL_1_DATA - The DMA uses this field to generate the data field for the Done or Abort
75080  *    IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as
75081  *    follows: - Dbi: R/W
75082  */
75083 #define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SHIFT)) & PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MASK)
75084 /*! @} */
75085 
75086 /*! @name DMA_WRITE_CH23_IMWR_DATA_OFF - DMA Write Channel 3 and 2 IMWr Data Register. */
75087 /*! @{ */
75088 
75089 #define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MASK (0xFFFFU)
75090 #define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SHIFT (0U)
75091 /*! WR_CHANNEL_2_DATA - The DMA uses this field to generate the data field for the Done or Abort
75092  *    IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as
75093  *    follows: - Dbi: R/W
75094  */
75095 #define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SHIFT)) & PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MASK)
75096 
75097 #define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MASK (0xFFFF0000U)
75098 #define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SHIFT (16U)
75099 /*! WR_CHANNEL_3_DATA - The DMA uses this field to generate the data field for the Done or Abort
75100  *    IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as
75101  *    follows: - Dbi: R/W
75102  */
75103 #define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SHIFT)) & PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MASK)
75104 /*! @} */
75105 
75106 /*! @name DMA_WRITE_CH45_IMWR_DATA_OFF - DMA Write Channel 5 and 4 IMWr Data Register. */
75107 /*! @{ */
75108 
75109 #define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MASK (0xFFFFU)
75110 #define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SHIFT (0U)
75111 /*! WR_CHANNEL_4_DATA - The DMA uses this field to generate the data field for the Done or Abort
75112  *    IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as
75113  *    follows: - Dbi: R/W
75114  */
75115 #define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SHIFT)) & PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MASK)
75116 
75117 #define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MASK (0xFFFF0000U)
75118 #define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SHIFT (16U)
75119 /*! WR_CHANNEL_5_DATA - The DMA uses this field to generate the data field for the Done or Abort
75120  *    IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as
75121  *    follows: - Dbi: R/W
75122  */
75123 #define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SHIFT)) & PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MASK)
75124 /*! @} */
75125 
75126 /*! @name DMA_WRITE_CH67_IMWR_DATA_OFF - DMA Write Channel 7 and 6 IMWr Data Register. */
75127 /*! @{ */
75128 
75129 #define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MASK (0xFFFFU)
75130 #define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SHIFT (0U)
75131 /*! WR_CHANNEL_6_DATA - The DMA uses this field to generate the data field for the Done or Abort
75132  *    IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as
75133  *    follows: - Dbi: R/W
75134  */
75135 #define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SHIFT)) & PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MASK)
75136 
75137 #define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MASK (0xFFFF0000U)
75138 #define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SHIFT (16U)
75139 /*! WR_CHANNEL_7_DATA - The DMA uses this field to generate the data field for the Done or Abort
75140  *    IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as
75141  *    follows: - Dbi: R/W
75142  */
75143 #define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SHIFT)) & PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MASK)
75144 /*! @} */
75145 
75146 /*! @name DMA_WRITE_LINKED_LIST_ERR_EN_OFF - DMA Write Linked List Error Enable Register. */
75147 /*! @{ */
75148 
75149 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MASK (0x1U)
75150 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SHIFT (0U)
75151 /*! WR_CHANNEL_LLRAIE - Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the
75152  *    write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element
75153  *    enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0]
75154  *    corresponds to channel 0. Used in linked list mode only. For more details, see "Interrupt Handling".
75155  *    Note: The access attributes of this field are as follows: - Dbi: R/W
75156  */
75157 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MASK)
75158 
75159 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK (0xFF00U)
75160 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT (8U)
75161 /*! RSVDP_8 - Reserved for future use. */
75162 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK)
75163 
75164 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MASK (0x10000U)
75165 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SHIFT (16U)
75166 /*! WR_CHANNEL_LLLAIE - Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write
75167  *    channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable
75168  *    the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds
75169  *    to channel 0. Used in linked list mode only. For more details, see "Interrupt Handling".
75170  *    Note: The access attributes of this field are as follows: - Dbi: R/W
75171  */
75172 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MASK)
75173 
75174 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK (0xFF000000U)
75175 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT (24U)
75176 /*! RSVDP_24 - Reserved for future use. */
75177 #define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK)
75178 /*! @} */
75179 
75180 /*! @name DMA_READ_INT_STATUS_OFF - DMA Read Interrupt Status Register. */
75181 /*! @{ */
75182 
75183 #define PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MASK (0xFFU)
75184 #define PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SHIFT (0U)
75185 /*! RD_DONE_INT_STATUS - Done Interrupt Status. The DMA read channel has successfully completed the
75186  *    DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
75187  *    Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt
75188  *    Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
75189  *    corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note:
75190  *    You can write to this register to emulate interrupt generation, during software or hardware
75191  *    testing. A write to the address triggers an interrupt, but the DMA does not set the Done or
75192  *    Abort bits in this register. Note: The access attributes of this field are as follows: - Dbi: R/W
75193  */
75194 #define PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MASK)
75195 
75196 #define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_MASK (0xFF00U)
75197 #define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_SHIFT (8U)
75198 /*! RSVDP_8 - Reserved for future use. */
75199 #define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_MASK)
75200 
75201 #define PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MASK (0xFF0000U)
75202 #define PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SHIFT (16U)
75203 /*! RD_ABORT_INT_STATUS - Abort Interrupt Status. The DMA read channel has detected an error, or you
75204  *    manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)".
75205  *    Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. You can read the "DMA
75206  *    Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High
75207  *    Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For
75208  *    details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register
75209  *    has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel
75210  *    bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write
75211  *    to this register to emulate interrupt generation, during software or hardware testing. A
75212  *    write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in
75213  *    this register. Note: The access attributes of this field are as follows: - Dbi: R/W
75214  */
75215 #define PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MASK)
75216 
75217 #define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_MASK (0xFF000000U)
75218 #define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_SHIFT (24U)
75219 /*! RSVDP_24 - Reserved for future use. */
75220 #define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_MASK)
75221 /*! @} */
75222 
75223 /*! @name DMA_READ_INT_MASK_OFF - DMA Read Interrupt Mask Register. */
75224 /*! @{ */
75225 
75226 #define PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MASK (0x1U)
75227 #define PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SHIFT (0U)
75228 /*! RD_DONE_INT_MASK - Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read
75229  *    interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA
75230  *    channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
75231  *    follows: - Dbi: R/W
75232  */
75233 #define PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MASK)
75234 
75235 #define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_MASK  (0xFF00U)
75236 #define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_SHIFT (8U)
75237 /*! RSVDP_8 - Reserved for future use. */
75238 #define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_MASK)
75239 
75240 #define PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MASK (0x10000U)
75241 #define PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SHIFT (16U)
75242 /*! RD_ABORT_INT_MASK - Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA
75243  *    read interrupt status register from asserting the edma_int output. Each bit corresponds to a
75244  *    DMA channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
75245  *    follows: - Dbi: R/W
75246  */
75247 #define PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MASK)
75248 
75249 #define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_MASK (0xFF000000U)
75250 #define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_SHIFT (24U)
75251 /*! RSVDP_24 - Reserved for future use. */
75252 #define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_MASK)
75253 /*! @} */
75254 
75255 /*! @name DMA_READ_INT_CLEAR_OFF - DMA Read Interrupt Clear Register. */
75256 /*! @{ */
75257 
75258 #define PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MASK (0xFFU)
75259 #define PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SHIFT (0U)
75260 /*! RD_DONE_INT_CLEAR - Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
75261  *    in the Done interrupt status field of the DMA read interrupt status register. Each bit
75262  *    corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this self-clearing
75263  *    register field always returns a "0".
75264  */
75265 #define PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MASK)
75266 
75267 #define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MASK (0xFF00U)
75268 #define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SHIFT (8U)
75269 /*! RSVDP_8 - Reserved for future use. */
75270 #define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MASK)
75271 
75272 #define PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MASK (0xFF0000U)
75273 #define PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SHIFT (16U)
75274 /*! RD_ABORT_INT_CLEAR - Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
75275  *    in the Abort interrupt status field of the DMA read interrupt status register. Each bit
75276  *    corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this
75277  *    self-clearing register field always returns a "0".
75278  */
75279 #define PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MASK)
75280 
75281 #define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MASK (0xFF000000U)
75282 #define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SHIFT (24U)
75283 /*! RSVDP_24 - Reserved for future use. */
75284 #define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24(x)  (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MASK)
75285 /*! @} */
75286 
75287 /*! @name DMA_READ_ERR_STATUS_LOW_OFF - DMA Read Error Status Low Register. */
75288 /*! @{ */
75289 
75290 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MASK (0xFFU)
75291 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SHIFT (0U)
75292 /*! APP_WR_ERR_DETECT - Application Write Error Detected. The DMA read channel has received an error
75293  *    response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing
75294  *    data to it. This error is fatal. You must restart the transfer from the beginning, as the
75295  *    channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked
75296  *    List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
75297  *    Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
75298  *    register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding
75299  *    channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
75300  *    (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also
75301  *    the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).
75302  */
75303 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MASK)
75304 
75305 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MASK (0xFF00U)
75306 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SHIFT (8U)
75307 /*! RSVDP_8 - Reserved for future use. */
75308 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MASK)
75309 
75310 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MASK (0xFF0000U)
75311 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SHIFT (16U)
75312 /*! LINK_LIST_ELEMENT_FETCH_ERR_DETECT - Linked List Element Fetch Error Detected. - The DMA read
75313  *    channel has received an error response from the AXI bus while reading a linked list element from
75314  *    local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
75315  *    Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
75316  *    register has no effect on this register. - Clearing: You must write a 1'b1 to the
75317  *    corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
75318  *    (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and
75319  *    also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).
75320  */
75321 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MASK)
75322 
75323 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MASK (0xFF000000U)
75324 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SHIFT (24U)
75325 /*! RSVDP_24 - Reserved for future use. */
75326 #define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MASK)
75327 /*! @} */
75328 
75329 /*! @name DMA_READ_ERR_STATUS_HIGH_OFF - DMA Read Error Status High Register. */
75330 /*! @{ */
75331 
75332 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MASK (0xFFU)
75333 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SHIFT (0U)
75334 /*! UNSUPPORTED_REQ - Unsupported Request. The DMA read channel has received a PCIe unsupported
75335  *    request completion status from the remote device in response to the MRd request. For more details,
75336  *    see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel
75337  *    0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read
75338  *    interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
75339  *    corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear
75340  *    Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error
75341  *    bits for the same channel in this register and in the DMA Read Error Status Low register.
75342  */
75343 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MASK)
75344 
75345 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MASK (0xFF00U)
75346 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SHIFT (8U)
75347 /*! CPL_ABORT - Completer Abort. The DMA read channel has received a PCIe completer abort completion
75348  *    status from the remote device in response to the MRd request. For more details, see "Linked
75349  *    List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
75350  *    Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
75351  *    register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding
75352  *    channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
75353  *    (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the
75354  *    same channel in this register and in the DMA Read Error Status Low register.
75355  */
75356 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MASK)
75357 
75358 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MASK (0xFF0000U)
75359 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SHIFT (16U)
75360 /*! CPL_TIMEOUT - Completion Time Out. The DMA read channel has timed-out while waiting for the
75361  *    remote device to respond to the MRd request, or a malformed CplD has been received. For more
75362  *    details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to
75363  *    channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read
75364  *    interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to
75365  *    the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear
75366  *    Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other
75367  *    error bits for the same channel in this register and in the DMA Read Error Status Low register.
75368  */
75369 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MASK)
75370 
75371 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MASK (0xFF000000U)
75372 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SHIFT (24U)
75373 /*! DATA_POISIONING - Data Poisoning. The DMA read channel has detected data poisoning in the
75374  *    completion from the remote device (in response to the MRd request). The DMA read channel will drop
75375  *    the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this
75376  *    behavior. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling:
75377  *    For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
75378  *    register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding
75379  *    channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
75380  *    (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same
75381  *    channel in this register and in the DMA Read Error Status Low register.
75382  */
75383 #define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MASK)
75384 /*! @} */
75385 
75386 /*! @name DMA_READ_LINKED_LIST_ERR_EN_OFF - DMA Read Linked List Error Enable Register. */
75387 /*! @{ */
75388 
75389 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MASK (0x1U)
75390 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SHIFT (0U)
75391 /*! RD_CHANNEL_LLRAIE - Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read
75392  *    channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable
75393  *    the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds
75394  *    to channel 0. Used in linked list mode only. For more details, see "Interrupt Handling". Note:
75395  *    The access attributes of this field are as follows: - Dbi: R/W
75396  */
75397 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MASK)
75398 
75399 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK (0xFF00U)
75400 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT (8U)
75401 /*! RSVDP_8 - Reserved for future use. */
75402 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK)
75403 
75404 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MASK (0x10000U)
75405 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SHIFT (16U)
75406 /*! RD_CHANNEL_LLLAIE - Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read
75407  *    channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable
75408  *    the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to
75409  *    channel 0. Used in linked list mode only. For more details, see "Interrupt Handling". Note:
75410  *    The access attributes of this field are as follows: - Dbi: R/W
75411  */
75412 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MASK)
75413 
75414 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK (0xFF000000U)
75415 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT (24U)
75416 /*! RSVDP_24 - Reserved for future use. */
75417 #define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK)
75418 /*! @} */
75419 
75420 /*! @name DMA_READ_DONE_IMWR_LOW_OFF - DMA Read Done IMWr Address Low Register. */
75421 /*! @{ */
75422 
75423 #define PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MASK (0xFFFFFFFFU)
75424 #define PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SHIFT (0U)
75425 /*! DMA_READ_DONE_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field for
75426  *    the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned. Note: The
75427  *    access attributes of this field are as follows: - Dbi: R/W
75428  */
75429 #define PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SHIFT)) & PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MASK)
75430 /*! @} */
75431 
75432 /*! @name DMA_READ_DONE_IMWR_HIGH_OFF - DMA Read Done IMWr Address High Register. */
75433 /*! @{ */
75434 
75435 #define PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MASK (0xFFFFFFFFU)
75436 #define PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SHIFT (0U)
75437 /*! DMA_READ_DONE_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
75438  *    for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
75439  */
75440 #define PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SHIFT)) & PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MASK)
75441 /*! @} */
75442 
75443 /*! @name DMA_READ_ABORT_IMWR_LOW_OFF - DMA Read Abort IMWr Address Low Register. */
75444 /*! @{ */
75445 
75446 #define PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MASK (0xFFFFFFFFU)
75447 #define PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SHIFT (0U)
75448 /*! DMA_READ_ABORT_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field
75449  *    for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned. Note: The
75450  *    access attributes of this field are as follows: - Dbi: R/W
75451  */
75452 #define PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SHIFT)) & PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MASK)
75453 /*! @} */
75454 
75455 /*! @name DMA_READ_ABORT_IMWR_HIGH_OFF - DMA Read Abort IMWr Address High Register. */
75456 /*! @{ */
75457 
75458 #define PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MASK (0xFFFFFFFFU)
75459 #define PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SHIFT (0U)
75460 /*! DMA_READ_ABORT_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
75461  *    for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
75462  */
75463 #define PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SHIFT)) & PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MASK)
75464 /*! @} */
75465 
75466 /*! @name DMA_READ_CH01_IMWR_DATA_OFF - DMA Read Channel 1 and 0 IMWr Data Register. */
75467 /*! @{ */
75468 
75469 #define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MASK (0xFFFFU)
75470 #define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SHIFT (0U)
75471 /*! RD_CHANNEL_0_DATA - The DMA uses this field to generate the data field for the Done or Abort
75472  *    IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as
75473  *    follows: - Dbi: R/W
75474  */
75475 #define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SHIFT)) & PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MASK)
75476 
75477 #define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MASK (0xFFFF0000U)
75478 #define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SHIFT (16U)
75479 /*! RD_CHANNEL_1_DATA - The DMA uses this field to generate the data field for the Done or Abort
75480  *    IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as
75481  *    follows: - Dbi: R/W
75482  */
75483 #define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SHIFT)) & PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MASK)
75484 /*! @} */
75485 
75486 /*! @name DMA_READ_CH23_IMWR_DATA_OFF - DMA Read Channel 3 and 2 IMWr Data Register. */
75487 /*! @{ */
75488 
75489 #define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MASK (0xFFFFU)
75490 #define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SHIFT (0U)
75491 /*! RD_CHANNEL_2_DATA - The DMA uses this field to generate the data field for the Done or Abort
75492  *    IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as
75493  *    follows: - Dbi: R/W
75494  */
75495 #define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SHIFT)) & PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MASK)
75496 
75497 #define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MASK (0xFFFF0000U)
75498 #define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SHIFT (16U)
75499 /*! RD_CHANNEL_3_DATA - The DMA uses this field to generate the data field for the Done or Abort
75500  *    IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as
75501  *    follows: - Dbi: R/W
75502  */
75503 #define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SHIFT)) & PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MASK)
75504 /*! @} */
75505 
75506 /*! @name DMA_READ_CH45_IMWR_DATA_OFF - DMA Read Channel 5 and 4 IMWr Data Register. */
75507 /*! @{ */
75508 
75509 #define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MASK (0xFFFFU)
75510 #define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SHIFT (0U)
75511 /*! RD_CHANNEL_4_DATA - The DMA uses this field to generate the data field for the Done or Abort
75512  *    IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as
75513  *    follows: - Dbi: R/W
75514  */
75515 #define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SHIFT)) & PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MASK)
75516 
75517 #define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MASK (0xFFFF0000U)
75518 #define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SHIFT (16U)
75519 /*! RD_CHANNEL_5_DATA - The DMA uses this field to generate the data field for the Done or Abort
75520  *    IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as
75521  *    follows: - Dbi: R/W
75522  */
75523 #define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SHIFT)) & PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MASK)
75524 /*! @} */
75525 
75526 /*! @name DMA_READ_CH67_IMWR_DATA_OFF - DMA Read Channel 7 and 6 IMWr Data Register. */
75527 /*! @{ */
75528 
75529 #define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MASK (0xFFFFU)
75530 #define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SHIFT (0U)
75531 /*! RD_CHANNEL_6_DATA - The DMA uses this field to generate the data field for the Done or Abort
75532  *    IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as
75533  *    follows: - Dbi: R/W
75534  */
75535 #define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SHIFT)) & PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MASK)
75536 
75537 #define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MASK (0xFFFF0000U)
75538 #define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SHIFT (16U)
75539 /*! RD_CHANNEL_7_DATA - The DMA uses this field to generate the data field for the Done or Abort
75540  *    IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as
75541  *    follows: - Dbi: R/W
75542  */
75543 #define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SHIFT)) & PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MASK)
75544 /*! @} */
75545 
75546 /*! @name DMA_CH_CONTROL1_OFF_WRCH_0 - DMA Write Channel Control 1 Register. */
75547 /*! @{ */
75548 
75549 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MASK  (0x1U)
75550 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SHIFT (0U)
75551 /*! CB - Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer
75552  *    (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer
75553  *    Synchronization". The DMA loads this field with the CB of the linked list element. Note: The access
75554  *    attributes of this field are as follows: - Dbi: R/W
75555  */
75556 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MASK)
75557 
75558 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MASK (0x2U)
75559 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SHIFT (1U)
75560 /*! TCB - Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used
75561  *    in linked list mode only. It is used to synchronize the producer (software) and the consumer
75562  *    (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The DMA loads
75563  *    this field with the TCB of the linked list element. this field is not defined in a data LL
75564  *    element. Note: The access attributes of this field are as follows: - Dbi: R/W
75565  */
75566 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MASK)
75567 
75568 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MASK (0x4U)
75569 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SHIFT (2U)
75570 /*! LLP - Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list
75571  *    element is a link element, and its LL element pointer dwords are pointing to the next
75572  *    (non-contiguous) element. The DMA loads this field with the LLP of the linked list element. Note: The
75573  *    access attributes of this field are as follows: - Dbi: R/W
75574  */
75575 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MASK)
75576 
75577 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MASK (0x8U)
75578 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SHIFT (3U)
75579 /*! LIE - Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done
75580  *    or Abort Local interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
75581  *    the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only
75582  *    enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts. This
75583  *    field is not defined in a link LL element. Note: The access attributes of this field are as
75584  *    follows: - Dbi: R/W
75585  */
75586 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MASK)
75587 
75588 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MASK (0x10U)
75589 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SHIFT (4U)
75590 /*! RIE - Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done
75591  *    or Abort Remote interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
75592  *    the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only
75593  *    enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.
75594  *    This field is not defined in a link LL element. Note: The access attributes of this field are as
75595  *    follows: - Dbi: R/W
75596  */
75597 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MASK)
75598 
75599 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MASK  (0x60U)
75600 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SHIFT (5U)
75601 /*! CS - Channel Status (CS). The channel status bits identify the current operational state of the
75602  *    DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved
75603  *    - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition
75604  *    has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has
75605  *    transferred all data for this channel, or you have prematurely stopped this channel by writing to the
75606  *    Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell
75607  *    Register" (DMA_READ_DOORBELL_OFF).
75608  */
75609 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MASK)
75610 
75611 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MASK (0x80U)
75612 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SHIFT (7U)
75613 /*! DMA_RESERVED0 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75614 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MASK)
75615 
75616 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MASK (0x100U)
75617 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SHIFT (8U)
75618 /*! CCS - Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the
75619  *    producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB
75620  *    Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked
75621  *    list operation. Note: The access attributes of this field are as follows: - Dbi: R/W
75622  */
75623 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MASK)
75624 
75625 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MASK (0x200U)
75626 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SHIFT (9U)
75627 /*! LLE - Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list
75628  *    operation Note: The access attributes of this field are as follows: - Dbi: R/W
75629  */
75630 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MASK)
75631 
75632 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MASK (0xC00U)
75633 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SHIFT (10U)
75634 /*! DMA_RESERVED1 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75635 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MASK)
75636 
75637 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MASK (0x1F000U)
75638 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SHIFT (12U)
75639 /*! DMA_FUNC_NUM - Function Number (FN). The controller uses this field when generating the
75640  *    requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you
75641  *    have set the VFE field in the "DMA Write Channel Control 2 Register"
75642  *    (DMA_CH_CONTROL2_OFF_WRCH_0). Note: The access attributes of this field are as follows: - Dbi: R/W
75643  */
75644 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MASK)
75645 
75646 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MASK (0x7E0000U)
75647 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SHIFT (17U)
75648 /*! DMA_RESERVED2 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75649 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MASK)
75650 
75651 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MASK (0x800000U)
75652 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SHIFT (23U)
75653 /*! DMA_NS_DST - Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header
75654  *    field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of
75655  *    this field are as follows: - Dbi: R/W
75656  */
75657 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MASK)
75658 
75659 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MASK (0x1000000U)
75660 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SHIFT (24U)
75661 /*! DMA_NS_SRC - Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field
75662  *    when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this
75663  *    field are as follows: - Dbi: R/W
75664  */
75665 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MASK)
75666 
75667 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MASK (0x2000000U)
75668 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SHIFT (25U)
75669 /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating
75670  *    MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
75671  */
75672 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MASK)
75673 
75674 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MASK (0x4000000U)
75675 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SHIFT (26U)
75676 /*! DMA_RESERVED5 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75677 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MASK)
75678 
75679 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MASK (0x38000000U)
75680 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SHIFT (27U)
75681 /*! DMA_TC - Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating
75682  *    MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
75683  */
75684 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MASK)
75685 
75686 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MASK (0xC0000000U)
75687 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SHIFT (30U)
75688 /*! DMA_AT - Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when
75689  *    generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi:
75690  *    R/W
75691  */
75692 #define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MASK)
75693 /*! @} */
75694 
75695 /*! @name DMA_TRANSFER_SIZE_OFF_WRCH_0 - DMA Write Transfer Size Register. */
75696 /*! @{ */
75697 
75698 #define PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU)
75699 #define PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SHIFT (0U)
75700 /*! DMA_TRANSFER_SIZE - DMA Transfer Size. You program this register with the size of the DMA
75701  *    transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1).
75702  *    This field is automatically decremented by the DMA as the DMA write channel transfer progresses.
75703  *    This field indicates the number bytes remaining to be transferred. When all bytes are
75704  *    successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this
75705  *    register with the corresponding dword of the LL element. You can read this register to monitor the
75706  *    transfer progress, however in some scenarios this register is updated after a delay. For
75707  *    example, when less than 3 channels are doorbelled, this register is updated only after a descriptor
75708  *    finishes(linked list mode), or the transfer ends (non-linked list mode). Note: The access
75709  *    attributes of this field are as follows: - Dbi: R/W
75710  */
75711 #define PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MASK)
75712 /*! @} */
75713 
75714 /*! @name DMA_SAR_LOW_OFF_WRCH_0 - DMA Write SAR Low Register. */
75715 /*! @{ */
75716 
75717 #define PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
75718 #define PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SHIFT (0U)
75719 /*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). Indicates the next address to be
75720  *    read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA
75721  *    overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of
75722  *    the remote memory. - DMA Write: The SAR is the address of the local memory. Note: The access
75723  *    attributes of this field are as follows: - Dbi: R/W
75724  */
75725 #define PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MASK)
75726 /*! @} */
75727 
75728 /*! @name DMA_SAR_HIGH_OFF_WRCH_0 - DMA Write SAR High Register. */
75729 /*! @{ */
75730 
75731 #define PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
75732 #define PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SHIFT (0U)
75733 /*! SRC_ADDR_REG_HIGH - Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites
75734  *    this with the corresponding dword of the LL element. Note: The access attributes of this field
75735  *    are as follows: - Dbi: R/W
75736  */
75737 #define PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MASK)
75738 /*! @} */
75739 
75740 /*! @name DMA_DAR_LOW_OFF_WRCH_0 - DMA Write DAR Low Register. */
75741 /*! @{ */
75742 
75743 #define PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
75744 #define PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SHIFT (0U)
75745 /*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). Indicates the next address to
75746  *    be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA
75747  *    overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the
75748  *    address of the local memory. - DMA Write: The DAR is the address of the remote memory. Note: The
75749  *    access attributes of this field are as follows: - Dbi: R/W
75750  */
75751 #define PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MASK)
75752 /*! @} */
75753 
75754 /*! @name DMA_DAR_HIGH_OFF_WRCH_0 - DMA Write DAR High Register. */
75755 /*! @{ */
75756 
75757 #define PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
75758 #define PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SHIFT (0U)
75759 /*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). In LL mode, the DMA
75760  *    overwrites this with the corresponding dword of the LL element. Note: The access attributes of this
75761  *    field are as follows: - Dbi: R/W
75762  */
75763 #define PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MASK)
75764 /*! @} */
75765 
75766 /*! @name DMA_LLP_LOW_OFF_WRCH_0 - DMA Write Linked List Pointer Low Register. */
75767 /*! @{ */
75768 
75769 #define PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MASK (0xFFFFFFFFU)
75770 #define PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SHIFT (0U)
75771 /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. Used in
75772  *    linked list mode only. Updated by the DMA to point to the next element in the transfer list
75773  *    after the previous element is consumed. - When the current element is a data element; this field
75774  *    is incremented by 6. - When the current element is a link element; this field is overwritten by
75775  *    the LL Element Pointer of the element. Note: The access attributes of this field are as
75776  *    follows: - Dbi: R/W
75777  */
75778 #define PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SHIFT)) & PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MASK)
75779 /*! @} */
75780 
75781 /*! @name DMA_LLP_HIGH_OFF_WRCH_0 - DMA Write Linked List Pointer High Register. */
75782 /*! @{ */
75783 
75784 #define PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MASK (0xFFFFFFFFU)
75785 #define PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SHIFT (0U)
75786 /*! LLP_HIGH - Upper 32 bits of the address of the linked list transfer list in local memory. Used
75787  *    in linked list mode only. Updated by the DMA to point to the next element in the transfer list
75788  *    as elements are consumed. Note: The access attributes of this field are as follows: - Dbi: R/W
75789  */
75790 #define PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SHIFT)) & PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MASK)
75791 /*! @} */
75792 
75793 /*! @name DMA_CH_CONTROL1_OFF_RDCH_0 - DMA Read Channel Control 1 Register. */
75794 /*! @{ */
75795 
75796 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MASK  (0x1U)
75797 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SHIFT (0U)
75798 /*! CB - Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer
75799  *    (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer
75800  *    Synchronization". The DMA loads this field with the CB of the linked list element. Note: The access
75801  *    attributes of this field are as follows: - Dbi: R/W
75802  */
75803 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MASK)
75804 
75805 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MASK (0x2U)
75806 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SHIFT (1U)
75807 /*! TCB - Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used
75808  *    in linked list mode only. It is used to synchronize the producer (software) and the consumer
75809  *    (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The DMA loads
75810  *    this field with the TCB of the linked list element. this field is not defined in a data LL
75811  *    element. Note: The access attributes of this field are as follows: - Dbi: R/W
75812  */
75813 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MASK)
75814 
75815 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MASK (0x4U)
75816 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SHIFT (2U)
75817 /*! LLP - Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list
75818  *    element is a link element, and its LL element pointer dwords are pointing to the next
75819  *    (non-contiguous) element. The DMA loads this field with the LLP of the linked list element. Note: The
75820  *    access attributes of this field are as follows: - Dbi: R/W
75821  */
75822 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MASK)
75823 
75824 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MASK (0x8U)
75825 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SHIFT (3U)
75826 /*! LIE - Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done
75827  *    or Abort Local interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
75828  *    the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only
75829  *    enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts. This
75830  *    field is not defined in a link LL element. Note: The access attributes of this field are as
75831  *    follows: - Dbi: R/W
75832  */
75833 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MASK)
75834 
75835 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MASK (0x10U)
75836 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SHIFT (4U)
75837 /*! RIE - Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done
75838  *    or Abort Remote interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
75839  *    the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only
75840  *    enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.
75841  *    This field is not defined in a link LL element. Note: The access attributes of this field are as
75842  *    follows: - Dbi: R/W
75843  */
75844 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MASK)
75845 
75846 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MASK  (0x60U)
75847 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SHIFT (5U)
75848 /*! CS - Channel Status (CS). The channel status bits identify the current operational state of the
75849  *    DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved
75850  *    - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition
75851  *    has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has
75852  *    transferred all data for this channel, or you have prematurely stopped this channel by writing to the
75853  *    Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell
75854  *    Register" (DMA_READ_DOORBELL_OFF).
75855  */
75856 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS(x)    (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MASK)
75857 
75858 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MASK (0x80U)
75859 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SHIFT (7U)
75860 /*! DMA_RESERVED0 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75861 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MASK)
75862 
75863 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MASK (0x100U)
75864 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SHIFT (8U)
75865 /*! CCS - Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the
75866  *    producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB
75867  *    Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked
75868  *    list operation. Note: The access attributes of this field are as follows: - Dbi: R/W
75869  */
75870 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MASK)
75871 
75872 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MASK (0x200U)
75873 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SHIFT (9U)
75874 /*! LLE - Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list
75875  *    operation Note: The access attributes of this field are as follows: - Dbi: R/W
75876  */
75877 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MASK)
75878 
75879 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MASK (0xC00U)
75880 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SHIFT (10U)
75881 /*! DMA_RESERVED1 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75882 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MASK)
75883 
75884 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MASK (0x1F000U)
75885 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SHIFT (12U)
75886 /*! DMA_FUNC_NUM - Function Number (FN). The controller uses this field when generating the
75887  *    requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you
75888  *    have set the VFE field in the "DMA Read Channel Control 2 Register"
75889  *    (DMA_CH_CONTROL2_OFF_RDCH_0). Note: The access attributes of this field are as follows: - Dbi: R/W
75890  */
75891 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MASK)
75892 
75893 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MASK (0x7E0000U)
75894 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SHIFT (17U)
75895 /*! DMA_RESERVED2 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75896 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MASK)
75897 
75898 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MASK (0x800000U)
75899 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SHIFT (23U)
75900 /*! DMA_NS_DST - Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header
75901  *    field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of
75902  *    this field are as follows: - Dbi: R/W
75903  */
75904 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MASK)
75905 
75906 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MASK (0x1000000U)
75907 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SHIFT (24U)
75908 /*! DMA_NS_SRC - Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field
75909  *    when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this
75910  *    field are as follows: - Dbi: R/W
75911  */
75912 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MASK)
75913 
75914 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MASK (0x2000000U)
75915 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SHIFT (25U)
75916 /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating
75917  *    MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
75918  */
75919 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MASK)
75920 
75921 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MASK (0x4000000U)
75922 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SHIFT (26U)
75923 /*! DMA_RESERVED5 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W */
75924 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MASK)
75925 
75926 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MASK (0x38000000U)
75927 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SHIFT (27U)
75928 /*! DMA_TC - Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating
75929  *    MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
75930  */
75931 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MASK)
75932 
75933 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MASK (0xC0000000U)
75934 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SHIFT (30U)
75935 /*! DMA_AT - Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when
75936  *    generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi:
75937  *    R/W
75938  */
75939 #define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MASK)
75940 /*! @} */
75941 
75942 /*! @name DMA_TRANSFER_SIZE_OFF_RDCH_0 - DMA Read Transfer Size Register. */
75943 /*! @{ */
75944 
75945 #define PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU)
75946 #define PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SHIFT (0U)
75947 /*! DMA_TRANSFER_SIZE - DMA Transfer Size. You program this register with the size of the DMA
75948  *    transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1).
75949  *    This field is automatically decremented by the DMA as the DMA read channel transfer progresses.
75950  *    This field indicates the number bytes remaining to be transferred. When all bytes are
75951  *    successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this
75952  *    register with the corresponding dword of the LL element. You can read this register to monitor the
75953  *    transfer progress, however in some scenarios this register is updated after a delay. For
75954  *    example, when less than 3 channels are doorbelled, this register is updated only after a descriptor
75955  *    finishes(linked list mode), or the transfer ends (non-linked list mode). Note: The access
75956  *    attributes of this field are as follows: - Dbi: R/W
75957  */
75958 #define PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MASK)
75959 /*! @} */
75960 
75961 /*! @name DMA_SAR_LOW_OFF_RDCH_0 - DMA Read SAR Low Register. */
75962 /*! @{ */
75963 
75964 #define PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
75965 #define PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SHIFT (0U)
75966 /*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). Indicates the next address to be
75967  *    read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA
75968  *    overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of
75969  *    the remote memory. - DMA Read: The SAR is the address of the local memory. Note: The access
75970  *    attributes of this field are as follows: - Dbi: R/W
75971  */
75972 #define PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MASK)
75973 /*! @} */
75974 
75975 /*! @name DMA_SAR_HIGH_OFF_RDCH_0 - DMA Read SAR High Register. */
75976 /*! @{ */
75977 
75978 #define PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
75979 #define PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SHIFT (0U)
75980 /*! SRC_ADDR_REG_HIGH - Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites
75981  *    this with the corresponding dword of the LL element. Note: The access attributes of this field
75982  *    are as follows: - Dbi: R/W
75983  */
75984 #define PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MASK)
75985 /*! @} */
75986 
75987 /*! @name DMA_DAR_LOW_OFF_RDCH_0 - DMA Read DAR Low Register. */
75988 /*! @{ */
75989 
75990 #define PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
75991 #define PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SHIFT (0U)
75992 /*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). Indicates the next address to
75993  *    be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA
75994  *    overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the
75995  *    address of the local memory. - DMA Read: The DAR is the address of the remote memory. Note: The
75996  *    access attributes of this field are as follows: - Dbi: R/W
75997  */
75998 #define PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MASK)
75999 /*! @} */
76000 
76001 /*! @name DMA_DAR_HIGH_OFF_RDCH_0 - DMA Read DAR High Register. */
76002 /*! @{ */
76003 
76004 #define PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
76005 #define PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SHIFT (0U)
76006 /*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). In LL mode, the DMA
76007  *    overwrites this with the corresponding dword of the LL element. Note: The access attributes of this
76008  *    field are as follows: - Dbi: R/W
76009  */
76010 #define PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MASK)
76011 /*! @} */
76012 
76013 /*! @name DMA_LLP_LOW_OFF_RDCH_0 - DMA Read Linked List Pointer Low Register. */
76014 /*! @{ */
76015 
76016 #define PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MASK (0xFFFFFFFFU)
76017 #define PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SHIFT (0U)
76018 /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. Used in
76019  *    linked list mode only. Updated by the DMA to point to the next element in the transfer list
76020  *    after the previous element is consumed. - When the current element is a data element; this field
76021  *    is incremented by 6. - When the current element is a link element; this field is overwritten by
76022  *    the LL Element Pointer of the element. Note: The access attributes of this field are as
76023  *    follows: - Dbi: R/W
76024  */
76025 #define PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW(x)   (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SHIFT)) & PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MASK)
76026 /*! @} */
76027 
76028 /*! @name DMA_LLP_HIGH_OFF_RDCH_0 - DMA Read Linked List Pointer High Register. */
76029 /*! @{ */
76030 
76031 #define PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MASK (0xFFFFFFFFU)
76032 #define PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SHIFT (0U)
76033 /*! LLP_HIGH - Upper 32 bits of the address of the linked list transfer list in local memory. Used
76034  *    in linked list mode only. Updated by the DMA to point to the next element in the transfer list
76035  *    as elements are consumed. Note: The access attributes of this field are as follows: - Dbi: R/W
76036  */
76037 #define PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SHIFT)) & PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MASK)
76038 /*! @} */
76039 
76040 
76041 /*!
76042  * @}
76043  */ /* end of group PCIE_Register_Masks */
76044 
76045 
76046 /* PCIE - Peripheral instance base addresses */
76047 /** Peripheral PCIE base address */
76048 #define PCIE_BASE                                (0x33800000u)
76049 /** Peripheral PCIE base pointer */
76050 #define PCIE                                     ((PCIE_Type *)PCIE_BASE)
76051 /** Array initializer of PCIE peripheral base addresses */
76052 #define PCIE_BASE_ADDRS                          { PCIE_BASE }
76053 /** Array initializer of PCIE peripheral base pointers */
76054 #define PCIE_BASE_PTRS                           { PCIE }
76055 
76056 /*!
76057  * @}
76058  */ /* end of group PCIE_Peripheral_Access_Layer */
76059 
76060 
76061 /* ----------------------------------------------------------------------------
76062    -- PCIE_PHY Peripheral Access Layer
76063    ---------------------------------------------------------------------------- */
76064 
76065 /*!
76066  * @addtogroup PCIE_PHY_Peripheral_Access_Layer PCIE_PHY Peripheral Access Layer
76067  * @{
76068  */
76069 
76070 /** PCIE_PHY - Register Layout Typedef */
76071 typedef struct {
76072   __IO uint8_t CMN_REG000;                         /**< offset: 0x0 */
76073        uint8_t RESERVED_0[3];
76074   __IO uint8_t CMN_REG001;                         /**< offset: 0x4 */
76075        uint8_t RESERVED_1[3];
76076   __IO uint8_t CMN_REG002;                         /**< offset: 0x8 */
76077        uint8_t RESERVED_2[3];
76078   __IO uint8_t CMN_REG003;                         /**< offset: 0xC */
76079        uint8_t RESERVED_3[3];
76080   __IO uint8_t CMN_REG004;                         /**< offset: 0x10 */
76081        uint8_t RESERVED_4[3];
76082   __IO uint8_t CMN_REG005;                         /**< offset: 0x14 */
76083        uint8_t RESERVED_5[3];
76084   __IO uint8_t CMN_REG006;                         /**< offset: 0x18 */
76085        uint8_t RESERVED_6[3];
76086   __IO uint8_t CMN_REG007;                         /**< offset: 0x1C */
76087        uint8_t RESERVED_7[3];
76088   __IO uint8_t CMN_REG008;                         /**< offset: 0x20 */
76089        uint8_t RESERVED_8[3];
76090   __IO uint8_t CMN_REG009;                         /**< offset: 0x24 */
76091        uint8_t RESERVED_9[3];
76092   __IO uint8_t CMN_REG00A;                         /**< offset: 0x28 */
76093        uint8_t RESERVED_10[3];
76094   __IO uint8_t CMN_REG00B;                         /**< offset: 0x2C */
76095        uint8_t RESERVED_11[3];
76096   __IO uint8_t CMN_REG00C;                         /**< offset: 0x30 */
76097        uint8_t RESERVED_12[3];
76098   __IO uint8_t CMN_REG00D;                         /**< offset: 0x34 */
76099        uint8_t RESERVED_13[3];
76100   __IO uint8_t CMN_REG00E;                         /**< offset: 0x38 */
76101        uint8_t RESERVED_14[3];
76102   __IO uint8_t CMN_REG00F;                         /**< offset: 0x3C */
76103        uint8_t RESERVED_15[3];
76104   __IO uint8_t CMN_REG010;                         /**< offset: 0x40 */
76105        uint8_t RESERVED_16[3];
76106   __IO uint8_t CMN_REG011;                         /**< offset: 0x44 */
76107        uint8_t RESERVED_17[3];
76108   __IO uint8_t CMN_REG012;                         /**< offset: 0x48 */
76109        uint8_t RESERVED_18[3];
76110   __IO uint8_t CMN_REG013;                         /**< offset: 0x4C */
76111        uint8_t RESERVED_19[3];
76112   __IO uint8_t CMN_REG014;                         /**< offset: 0x50 */
76113        uint8_t RESERVED_20[3];
76114   __IO uint8_t CMN_REG015;                         /**< offset: 0x54 */
76115        uint8_t RESERVED_21[3];
76116   __IO uint8_t CMN_REG016;                         /**< offset: 0x58 */
76117        uint8_t RESERVED_22[3];
76118   __IO uint8_t CMN_REG017;                         /**< offset: 0x5C */
76119        uint8_t RESERVED_23[3];
76120   __IO uint8_t CMN_REG018;                         /**< offset: 0x60 */
76121        uint8_t RESERVED_24[3];
76122   __IO uint8_t CMN_REG019;                         /**< offset: 0x64 */
76123        uint8_t RESERVED_25[3];
76124   __IO uint8_t CMN_REG01A;                         /**< offset: 0x68 */
76125        uint8_t RESERVED_26[3];
76126   __IO uint8_t CMN_REG01B;                         /**< offset: 0x6C */
76127        uint8_t RESERVED_27[3];
76128   __IO uint8_t CMN_REG01C;                         /**< offset: 0x70 */
76129        uint8_t RESERVED_28[3];
76130   __IO uint8_t CMN_REG01D;                         /**< offset: 0x74 */
76131        uint8_t RESERVED_29[3];
76132   __IO uint8_t CMN_REG01E;                         /**< offset: 0x78 */
76133        uint8_t RESERVED_30[3];
76134   __IO uint8_t CMN_REG01F;                         /**< offset: 0x7C */
76135        uint8_t RESERVED_31[3];
76136   __IO uint8_t CMN_REG020;                         /**< offset: 0x80 */
76137        uint8_t RESERVED_32[3];
76138   __IO uint8_t CMN_REG021;                         /**< offset: 0x84 */
76139        uint8_t RESERVED_33[3];
76140   __IO uint8_t CMN_REG022;                         /**< offset: 0x88 */
76141        uint8_t RESERVED_34[3];
76142   __IO uint8_t CMN_REG023;                         /**< offset: 0x8C */
76143        uint8_t RESERVED_35[3];
76144   __IO uint8_t CMN_REG024;                         /**< offset: 0x90 */
76145        uint8_t RESERVED_36[3];
76146   __IO uint8_t CMN_REG025;                         /**< offset: 0x94 */
76147        uint8_t RESERVED_37[3];
76148   __IO uint8_t CMN_REG026;                         /**< offset: 0x98 */
76149        uint8_t RESERVED_38[3];
76150   __IO uint8_t CMN_REG027;                         /**< offset: 0x9C */
76151        uint8_t RESERVED_39[3];
76152   __IO uint8_t CMN_REG028;                         /**< offset: 0xA0 */
76153        uint8_t RESERVED_40[3];
76154   __IO uint8_t CMN_REG029;                         /**< offset: 0xA4 */
76155        uint8_t RESERVED_41[3];
76156   __IO uint8_t CMN_REG02A;                         /**< offset: 0xA8 */
76157        uint8_t RESERVED_42[3];
76158   __IO uint8_t CMN_REG02B;                         /**< offset: 0xAC */
76159        uint8_t RESERVED_43[3];
76160   __IO uint8_t CMN_REG02C;                         /**< offset: 0xB0 */
76161        uint8_t RESERVED_44[3];
76162   __IO uint8_t CMN_REG02D;                         /**< offset: 0xB4 */
76163        uint8_t RESERVED_45[3];
76164   __IO uint8_t CMN_REG02E;                         /**< offset: 0xB8 */
76165        uint8_t RESERVED_46[3];
76166   __IO uint8_t CMN_REG02F;                         /**< offset: 0xBC */
76167        uint8_t RESERVED_47[3];
76168   __IO uint8_t CMN_REG030;                         /**< offset: 0xC0 */
76169        uint8_t RESERVED_48[3];
76170   __IO uint8_t CMN_REG031;                         /**< offset: 0xC4 */
76171        uint8_t RESERVED_49[3];
76172   __IO uint8_t CMN_REG032;                         /**< offset: 0xC8 */
76173        uint8_t RESERVED_50[3];
76174   __IO uint8_t CMN_REG033;                         /**< offset: 0xCC */
76175        uint8_t RESERVED_51[3];
76176   __IO uint8_t CMN_REG034;                         /**< offset: 0xD0 */
76177        uint8_t RESERVED_52[3];
76178   __IO uint8_t CMN_REG035;                         /**< offset: 0xD4 */
76179        uint8_t RESERVED_53[3];
76180   __IO uint8_t CMN_REG036;                         /**< offset: 0xD8 */
76181        uint8_t RESERVED_54[3];
76182   __IO uint8_t CMN_REG037;                         /**< offset: 0xDC */
76183        uint8_t RESERVED_55[3];
76184   __IO uint8_t CMN_REG038;                         /**< offset: 0xE0 */
76185        uint8_t RESERVED_56[3];
76186   __IO uint8_t CMN_REG039;                         /**< offset: 0xE4 */
76187        uint8_t RESERVED_57[3];
76188   __IO uint8_t CMN_REG03A;                         /**< offset: 0xE8 */
76189        uint8_t RESERVED_58[3];
76190   __IO uint8_t CMN_REG03B;                         /**< offset: 0xEC */
76191        uint8_t RESERVED_59[3];
76192   __IO uint8_t CMN_REG03C;                         /**< offset: 0xF0 */
76193        uint8_t RESERVED_60[3];
76194   __IO uint8_t CMN_REG03D;                         /**< offset: 0xF4 */
76195        uint8_t RESERVED_61[3];
76196   __IO uint8_t CMN_REG03E;                         /**< offset: 0xF8 */
76197        uint8_t RESERVED_62[3];
76198   __IO uint8_t CMN_REG03F;                         /**< offset: 0xFC */
76199        uint8_t RESERVED_63[3];
76200   __IO uint8_t CMN_REG040;                         /**< offset: 0x100 */
76201        uint8_t RESERVED_64[3];
76202   __IO uint8_t CMN_REG041;                         /**< offset: 0x104 */
76203        uint8_t RESERVED_65[3];
76204   __IO uint8_t CMN_REG042;                         /**< offset: 0x108 */
76205        uint8_t RESERVED_66[3];
76206   __IO uint8_t CMN_REG043;                         /**< offset: 0x10C */
76207        uint8_t RESERVED_67[3];
76208   __IO uint8_t CMN_REG044;                         /**< offset: 0x110 */
76209        uint8_t RESERVED_68[3];
76210   __IO uint8_t CMN_REG045;                         /**< offset: 0x114 */
76211        uint8_t RESERVED_69[3];
76212   __IO uint8_t CMN_REG046;                         /**< offset: 0x118 */
76213        uint8_t RESERVED_70[3];
76214   __IO uint8_t CMN_REG047;                         /**< offset: 0x11C */
76215        uint8_t RESERVED_71[3];
76216   __IO uint8_t CMN_REG048;                         /**< offset: 0x120 */
76217        uint8_t RESERVED_72[3];
76218   __IO uint8_t CMN_REG049;                         /**< offset: 0x124 */
76219        uint8_t RESERVED_73[3];
76220   __IO uint8_t CMN_REG04A;                         /**< offset: 0x128 */
76221        uint8_t RESERVED_74[3];
76222   __IO uint8_t CMN_REG04B;                         /**< offset: 0x12C */
76223        uint8_t RESERVED_75[3];
76224   __IO uint8_t CMN_REG04C;                         /**< offset: 0x130 */
76225        uint8_t RESERVED_76[3];
76226   __IO uint8_t CMN_REG04D;                         /**< offset: 0x134 */
76227        uint8_t RESERVED_77[3];
76228   __IO uint8_t CMN_REG04E;                         /**< offset: 0x138 */
76229        uint8_t RESERVED_78[3];
76230   __IO uint8_t CMN_REG04F;                         /**< offset: 0x13C */
76231        uint8_t RESERVED_79[3];
76232   __IO uint8_t CMN_REG050;                         /**< offset: 0x140 */
76233        uint8_t RESERVED_80[3];
76234   __IO uint8_t CMN_REG051;                         /**< offset: 0x144 */
76235        uint8_t RESERVED_81[3];
76236   __IO uint8_t CMN_REG052;                         /**< offset: 0x148 */
76237        uint8_t RESERVED_82[3];
76238   __IO uint8_t CMN_REG053;                         /**< offset: 0x14C */
76239        uint8_t RESERVED_83[3];
76240   __IO uint8_t CMN_REG054;                         /**< offset: 0x150 */
76241        uint8_t RESERVED_84[3];
76242   __IO uint8_t CMN_REG055;                         /**< offset: 0x154 */
76243        uint8_t RESERVED_85[3];
76244   __IO uint8_t CMN_REG056;                         /**< offset: 0x158 */
76245        uint8_t RESERVED_86[3];
76246   __IO uint8_t CMN_REG057;                         /**< offset: 0x15C */
76247        uint8_t RESERVED_87[3];
76248   __IO uint8_t CMN_REG058;                         /**< offset: 0x160 */
76249        uint8_t RESERVED_88[3];
76250   __IO uint8_t CMN_REG059;                         /**< offset: 0x164 */
76251        uint8_t RESERVED_89[3];
76252   __IO uint8_t CMN_REG05A;                         /**< offset: 0x168 */
76253        uint8_t RESERVED_90[3];
76254   __IO uint8_t CMN_REG05B;                         /**< offset: 0x16C */
76255        uint8_t RESERVED_91[3];
76256   __IO uint8_t CMN_REG05C;                         /**< offset: 0x170 */
76257        uint8_t RESERVED_92[3];
76258   __IO uint8_t CMN_REG05D;                         /**< offset: 0x174 */
76259        uint8_t RESERVED_93[3];
76260   __IO uint8_t CMN_REG05E;                         /**< offset: 0x178 */
76261        uint8_t RESERVED_94[3];
76262   __IO uint8_t CMN_REG05F;                         /**< offset: 0x17C */
76263        uint8_t RESERVED_95[3];
76264   __IO uint8_t CMN_REG060;                         /**< offset: 0x180 */
76265        uint8_t RESERVED_96[3];
76266   __IO uint8_t CMN_REG061;                         /**< offset: 0x184 */
76267        uint8_t RESERVED_97[3];
76268   __IO uint8_t CMN_REG062;                         /**< offset: 0x188 */
76269        uint8_t RESERVED_98[3];
76270   __IO uint8_t CMN_REG063;                         /**< offset: 0x18C */
76271        uint8_t RESERVED_99[3];
76272   __IO uint8_t CMN_REG064;                         /**< offset: 0x190 */
76273        uint8_t RESERVED_100[3];
76274   __IO uint8_t CMN_REG065;                         /**< offset: 0x194 */
76275        uint8_t RESERVED_101[3];
76276   __IO uint8_t CMN_REG066;                         /**< offset: 0x198 */
76277        uint8_t RESERVED_102[3];
76278   __IO uint8_t CMN_REG067;                         /**< offset: 0x19C */
76279        uint8_t RESERVED_103[3];
76280   __IO uint8_t CMN_REG068;                         /**< offset: 0x1A0 */
76281        uint8_t RESERVED_104[3];
76282   __IO uint8_t CMN_REG069;                         /**< offset: 0x1A4 */
76283        uint8_t RESERVED_105[3];
76284   __IO uint8_t CMN_REG06A;                         /**< offset: 0x1A8 */
76285        uint8_t RESERVED_106[3];
76286   __IO uint8_t CMN_REG06B;                         /**< offset: 0x1AC */
76287        uint8_t RESERVED_107[3];
76288   __IO uint8_t CMN_REG06C;                         /**< offset: 0x1B0 */
76289        uint8_t RESERVED_108[3];
76290   __IO uint8_t CMN_REG06D;                         /**< offset: 0x1B4 */
76291        uint8_t RESERVED_109[3];
76292   __IO uint8_t CMN_REG06E;                         /**< offset: 0x1B8 */
76293        uint8_t RESERVED_110[3];
76294   __IO uint8_t CMN_REG06F;                         /**< offset: 0x1BC */
76295        uint8_t RESERVED_111[3];
76296   __IO uint8_t CMN_REG070;                         /**< offset: 0x1C0 */
76297        uint8_t RESERVED_112[3];
76298   __IO uint8_t CMN_REG071;                         /**< offset: 0x1C4 */
76299        uint8_t RESERVED_113[3];
76300   __IO uint8_t CMN_REG072;                         /**< offset: 0x1C8 */
76301        uint8_t RESERVED_114[3];
76302   __IO uint8_t CMN_REG073;                         /**< offset: 0x1CC */
76303        uint8_t RESERVED_115[3];
76304   __IO uint8_t CMN_REG074;                         /**< offset: 0x1D0 */
76305        uint8_t RESERVED_116[3];
76306   __IO uint8_t CMN_REG075;                         /**< offset: 0x1D4 */
76307        uint8_t RESERVED_117[43];
76308   __IO uint8_t CMN_REG076;                         /**< offset: 0x200 */
76309        uint8_t RESERVED_118[3];
76310   __IO uint8_t CMN_REG077;                         /**< offset: 0x204 */
76311        uint8_t RESERVED_119[3];
76312   __IO uint8_t CMN_REG078;                         /**< offset: 0x208 */
76313        uint8_t RESERVED_120[3];
76314   __IO uint8_t CMN_REG079;                         /**< offset: 0x20C */
76315        uint8_t RESERVED_121[3];
76316   __IO uint8_t CMN_REG080;                         /**< offset: 0x210 */
76317        uint8_t RESERVED_122[3];
76318   __IO uint8_t CMN_REG081;                         /**< offset: 0x214 */
76319        uint8_t RESERVED_123[3];
76320   __IO uint8_t CMN_REG082;                         /**< offset: 0x218 */
76321        uint8_t RESERVED_124[487];
76322   __IO uint8_t TRSV_REG000;                        /**< offset: 0x400 */
76323        uint8_t RESERVED_125[3];
76324   __IO uint8_t TRSV_REG001;                        /**< offset: 0x404 */
76325        uint8_t RESERVED_126[3];
76326   __IO uint8_t TRSV_REG002;                        /**< offset: 0x408 */
76327        uint8_t RESERVED_127[3];
76328   __IO uint8_t TRSV_REG003;                        /**< offset: 0x40C */
76329        uint8_t RESERVED_128[3];
76330   __IO uint8_t TRSV_REG004;                        /**< offset: 0x410 */
76331        uint8_t RESERVED_129[3];
76332   __IO uint8_t TRSV_REG005;                        /**< offset: 0x414 */
76333        uint8_t RESERVED_130[3];
76334   __IO uint8_t TRSV_REG006;                        /**< offset: 0x418 */
76335        uint8_t RESERVED_131[3];
76336   __IO uint8_t TRSV_REG007;                        /**< offset: 0x41C */
76337        uint8_t RESERVED_132[3];
76338   __IO uint8_t TRSV_REG008;                        /**< offset: 0x420 */
76339        uint8_t RESERVED_133[3];
76340   __IO uint8_t TRSV_REG009;                        /**< offset: 0x424 */
76341        uint8_t RESERVED_134[3];
76342   __IO uint8_t TRSV_REG00A;                        /**< offset: 0x428 */
76343        uint8_t RESERVED_135[3];
76344   __IO uint8_t TRSV_REG00B;                        /**< offset: 0x42C */
76345        uint8_t RESERVED_136[3];
76346   __IO uint8_t TRSV_REG00C;                        /**< offset: 0x430 */
76347        uint8_t RESERVED_137[3];
76348   __IO uint8_t TRSV_REG00D;                        /**< offset: 0x434 */
76349        uint8_t RESERVED_138[3];
76350   __IO uint8_t TRSV_REG00E;                        /**< offset: 0x438 */
76351        uint8_t RESERVED_139[3];
76352   __IO uint8_t TRSV_REG00F;                        /**< offset: 0x43C */
76353        uint8_t RESERVED_140[3];
76354   __IO uint8_t TRSV_REG010;                        /**< offset: 0x440 */
76355        uint8_t RESERVED_141[3];
76356   __IO uint8_t TRSV_REG011;                        /**< offset: 0x444 */
76357        uint8_t RESERVED_142[3];
76358   __IO uint8_t TRSV_REG012;                        /**< offset: 0x448 */
76359        uint8_t RESERVED_143[3];
76360   __IO uint8_t TRSV_REG013;                        /**< offset: 0x44C */
76361        uint8_t RESERVED_144[3];
76362   __IO uint8_t TRSV_REG014;                        /**< offset: 0x450 */
76363        uint8_t RESERVED_145[3];
76364   __IO uint8_t TRSV_REG015;                        /**< offset: 0x454 */
76365        uint8_t RESERVED_146[3];
76366   __IO uint8_t TRSV_REG016;                        /**< offset: 0x458 */
76367        uint8_t RESERVED_147[3];
76368   __IO uint8_t TRSV_REG017;                        /**< offset: 0x45C */
76369        uint8_t RESERVED_148[3];
76370   __IO uint8_t TRSV_REG018;                        /**< offset: 0x460 */
76371        uint8_t RESERVED_149[3];
76372   __IO uint8_t TRSV_REG019;                        /**< offset: 0x464 */
76373        uint8_t RESERVED_150[3];
76374   __IO uint8_t TRSV_REG01A;                        /**< offset: 0x468 */
76375        uint8_t RESERVED_151[3];
76376   __IO uint8_t TRSV_REG01B;                        /**< offset: 0x46C */
76377        uint8_t RESERVED_152[3];
76378   __IO uint8_t TRSV_REG01C;                        /**< offset: 0x470 */
76379        uint8_t RESERVED_153[3];
76380   __IO uint8_t TRSV_REG01D;                        /**< offset: 0x474 */
76381        uint8_t RESERVED_154[3];
76382   __IO uint8_t TRSV_REG01E;                        /**< offset: 0x478 */
76383        uint8_t RESERVED_155[3];
76384   __IO uint8_t TRSV_REG01F;                        /**< offset: 0x47C */
76385        uint8_t RESERVED_156[3];
76386   __IO uint8_t TRSV_REG020;                        /**< offset: 0x480 */
76387        uint8_t RESERVED_157[3];
76388   __IO uint8_t TRSV_REG021;                        /**< offset: 0x484 */
76389        uint8_t RESERVED_158[3];
76390   __IO uint8_t TRSV_REG022;                        /**< offset: 0x488 */
76391        uint8_t RESERVED_159[3];
76392   __IO uint8_t TRSV_REG023;                        /**< offset: 0x48C */
76393        uint8_t RESERVED_160[3];
76394   __IO uint8_t TRSV_REG024;                        /**< offset: 0x490 */
76395        uint8_t RESERVED_161[3];
76396   __IO uint8_t TRSV_REG025;                        /**< offset: 0x494 */
76397        uint8_t RESERVED_162[3];
76398   __IO uint8_t TRSV_REG026;                        /**< offset: 0x498 */
76399        uint8_t RESERVED_163[3];
76400   __IO uint8_t TRSV_REG027;                        /**< offset: 0x49C */
76401        uint8_t RESERVED_164[3];
76402   __IO uint8_t TRSV_REG028;                        /**< offset: 0x4A0 */
76403        uint8_t RESERVED_165[3];
76404   __IO uint8_t TRSV_REG029;                        /**< offset: 0x4A4 */
76405        uint8_t RESERVED_166[3];
76406   __IO uint8_t TRSV_REG02A;                        /**< offset: 0x4A8 */
76407        uint8_t RESERVED_167[3];
76408   __IO uint8_t TRSV_REG02B;                        /**< offset: 0x4AC */
76409        uint8_t RESERVED_168[3];
76410   __IO uint8_t TRSV_REG02C;                        /**< offset: 0x4B0 */
76411        uint8_t RESERVED_169[3];
76412   __IO uint8_t TRSV_REG02D;                        /**< offset: 0x4B4 */
76413        uint8_t RESERVED_170[3];
76414   __IO uint8_t TRSV_REG02E;                        /**< offset: 0x4B8 */
76415        uint8_t RESERVED_171[3];
76416   __IO uint8_t TRSV_REG02F;                        /**< offset: 0x4BC */
76417        uint8_t RESERVED_172[3];
76418   __IO uint8_t TRSV_REG030;                        /**< offset: 0x4C0 */
76419        uint8_t RESERVED_173[3];
76420   __IO uint8_t TRSV_REG031;                        /**< offset: 0x4C4 */
76421        uint8_t RESERVED_174[3];
76422   __IO uint8_t TRSV_REG032;                        /**< offset: 0x4C8 */
76423        uint8_t RESERVED_175[3];
76424   __IO uint8_t TRSV_REG033;                        /**< offset: 0x4CC */
76425        uint8_t RESERVED_176[3];
76426   __IO uint8_t TRSV_REG034;                        /**< offset: 0x4D0 */
76427        uint8_t RESERVED_177[3];
76428   __IO uint8_t TRSV_REG035;                        /**< offset: 0x4D4 */
76429        uint8_t RESERVED_178[3];
76430   __IO uint8_t TRSV_REG036;                        /**< offset: 0x4D8 */
76431        uint8_t RESERVED_179[3];
76432   __IO uint8_t TRSV_REG037;                        /**< offset: 0x4DC */
76433        uint8_t RESERVED_180[3];
76434   __IO uint8_t TRSV_REG038;                        /**< offset: 0x4E0 */
76435        uint8_t RESERVED_181[3];
76436   __IO uint8_t TRSV_REG039;                        /**< offset: 0x4E4 */
76437        uint8_t RESERVED_182[3];
76438   __IO uint8_t TRSV_REG03A;                        /**< offset: 0x4E8 */
76439        uint8_t RESERVED_183[3];
76440   __IO uint8_t TRSV_REG03B;                        /**< offset: 0x4EC */
76441        uint8_t RESERVED_184[3];
76442   __IO uint8_t TRSV_REG03C;                        /**< offset: 0x4F0 */
76443        uint8_t RESERVED_185[3];
76444   __IO uint8_t TRSV_REG03D;                        /**< offset: 0x4F4 */
76445        uint8_t RESERVED_186[3];
76446   __IO uint8_t TRSV_REG03E;                        /**< offset: 0x4F8 */
76447        uint8_t RESERVED_187[3];
76448   __IO uint8_t TRSV_REG03F;                        /**< offset: 0x4FC */
76449        uint8_t RESERVED_188[3];
76450   __IO uint8_t TRSV_REG040;                        /**< offset: 0x500 */
76451        uint8_t RESERVED_189[3];
76452   __IO uint8_t TRSV_REG041;                        /**< offset: 0x504 */
76453        uint8_t RESERVED_190[3];
76454   __IO uint8_t TRSV_REG042;                        /**< offset: 0x508 */
76455        uint8_t RESERVED_191[3];
76456   __IO uint8_t TRSV_REG043;                        /**< offset: 0x50C */
76457        uint8_t RESERVED_192[3];
76458   __IO uint8_t TRSV_REG044;                        /**< offset: 0x510 */
76459        uint8_t RESERVED_193[3];
76460   __IO uint8_t TRSV_REG045;                        /**< offset: 0x514 */
76461        uint8_t RESERVED_194[3];
76462   __IO uint8_t TRSV_REG046;                        /**< offset: 0x518 */
76463        uint8_t RESERVED_195[3];
76464   __IO uint8_t TRSV_REG047;                        /**< offset: 0x51C */
76465        uint8_t RESERVED_196[3];
76466   __IO uint8_t TRSV_REG048;                        /**< offset: 0x520 */
76467        uint8_t RESERVED_197[3];
76468   __IO uint8_t TRSV_REG049;                        /**< offset: 0x524 */
76469        uint8_t RESERVED_198[3];
76470   __IO uint8_t TRSV_REG04A;                        /**< offset: 0x528 */
76471        uint8_t RESERVED_199[3];
76472   __IO uint8_t TRSV_REG04B;                        /**< offset: 0x52C */
76473        uint8_t RESERVED_200[3];
76474   __IO uint8_t TRSV_REG04C;                        /**< offset: 0x530 */
76475        uint8_t RESERVED_201[3];
76476   __IO uint8_t TRSV_REG04D;                        /**< offset: 0x534 */
76477        uint8_t RESERVED_202[3];
76478   __IO uint8_t TRSV_REG04E;                        /**< offset: 0x538 */
76479        uint8_t RESERVED_203[3];
76480   __IO uint8_t TRSV_REG04F;                        /**< offset: 0x53C */
76481        uint8_t RESERVED_204[3];
76482   __IO uint8_t TRSV_REG050;                        /**< offset: 0x540 */
76483        uint8_t RESERVED_205[3];
76484   __IO uint8_t TRSV_REG051;                        /**< offset: 0x544 */
76485        uint8_t RESERVED_206[3];
76486   __IO uint8_t TRSV_REG052;                        /**< offset: 0x548 */
76487        uint8_t RESERVED_207[3];
76488   __IO uint8_t TRSV_REG053;                        /**< offset: 0x54C */
76489        uint8_t RESERVED_208[3];
76490   __IO uint8_t TRSV_REG054;                        /**< offset: 0x550 */
76491        uint8_t RESERVED_209[3];
76492   __IO uint8_t TRSV_REG055;                        /**< offset: 0x554 */
76493        uint8_t RESERVED_210[3];
76494   __IO uint8_t TRSV_REG056;                        /**< offset: 0x558 */
76495        uint8_t RESERVED_211[3];
76496   __IO uint8_t TRSV_REG057;                        /**< offset: 0x55C */
76497        uint8_t RESERVED_212[3];
76498   __IO uint8_t TRSV_REG058;                        /**< offset: 0x560 */
76499        uint8_t RESERVED_213[3];
76500   __IO uint8_t TRSV_REG059;                        /**< offset: 0x564 */
76501        uint8_t RESERVED_214[3];
76502   __IO uint8_t TRSV_REG05A;                        /**< offset: 0x568 */
76503        uint8_t RESERVED_215[3];
76504   __IO uint8_t TRSV_REG05B;                        /**< offset: 0x56C */
76505        uint8_t RESERVED_216[3];
76506   __IO uint8_t TRSV_REG05C;                        /**< offset: 0x570 */
76507        uint8_t RESERVED_217[3];
76508   __IO uint8_t TRSV_REG05D;                        /**< offset: 0x574 */
76509        uint8_t RESERVED_218[3];
76510   __IO uint8_t TRSV_REG05E;                        /**< offset: 0x578 */
76511        uint8_t RESERVED_219[3];
76512   __IO uint8_t TRSV_REG05F;                        /**< offset: 0x57C */
76513        uint8_t RESERVED_220[3];
76514   __IO uint8_t TRSV_REG060;                        /**< offset: 0x580 */
76515        uint8_t RESERVED_221[3];
76516   __IO uint8_t TRSV_REG061;                        /**< offset: 0x584 */
76517        uint8_t RESERVED_222[3];
76518   __IO uint8_t TRSV_REG062;                        /**< offset: 0x588 */
76519        uint8_t RESERVED_223[3];
76520   __IO uint8_t TRSV_REG063;                        /**< offset: 0x58C */
76521        uint8_t RESERVED_224[3];
76522   __IO uint8_t TRSV_REG064;                        /**< offset: 0x590 */
76523        uint8_t RESERVED_225[3];
76524   __IO uint8_t TRSV_REG065;                        /**< offset: 0x594 */
76525        uint8_t RESERVED_226[3];
76526   __IO uint8_t TRSV_REG066;                        /**< offset: 0x598 */
76527        uint8_t RESERVED_227[3];
76528   __IO uint8_t TRSV_REG067;                        /**< offset: 0x59C */
76529        uint8_t RESERVED_228[3];
76530   __IO uint8_t TRSV_REG068;                        /**< offset: 0x5A0 */
76531        uint8_t RESERVED_229[3];
76532   __IO uint8_t TRSV_REG069;                        /**< offset: 0x5A4 */
76533        uint8_t RESERVED_230[3];
76534   __IO uint8_t TRSV_REG06A;                        /**< offset: 0x5A8 */
76535        uint8_t RESERVED_231[3];
76536   __IO uint8_t TRSV_REG06B;                        /**< offset: 0x5AC */
76537        uint8_t RESERVED_232[3];
76538   __IO uint8_t TRSV_REG06C;                        /**< offset: 0x5B0 */
76539        uint8_t RESERVED_233[3];
76540   __IO uint8_t TRSV_REG06D;                        /**< offset: 0x5B4 */
76541        uint8_t RESERVED_234[3];
76542   __IO uint8_t TRSV_REG06E;                        /**< offset: 0x5B8 */
76543        uint8_t RESERVED_235[3];
76544   __IO uint8_t TRSV_REG06F;                        /**< offset: 0x5BC */
76545        uint8_t RESERVED_236[3];
76546   __IO uint8_t TRSV_REG070;                        /**< offset: 0x5C0 */
76547        uint8_t RESERVED_237[3];
76548   __IO uint8_t TRSV_REG071;                        /**< offset: 0x5C4 */
76549        uint8_t RESERVED_238[3];
76550   __IO uint8_t TRSV_REG072;                        /**< offset: 0x5C8 */
76551        uint8_t RESERVED_239[3];
76552   __IO uint8_t TRSV_REG073;                        /**< offset: 0x5CC */
76553        uint8_t RESERVED_240[3];
76554   __IO uint8_t TRSV_REG074;                        /**< offset: 0x5D0 */
76555        uint8_t RESERVED_241[3];
76556   __IO uint8_t TRSV_REG075;                        /**< offset: 0x5D4 */
76557        uint8_t RESERVED_242[3];
76558   __IO uint8_t TRSV_REG076;                        /**< offset: 0x5D8 */
76559        uint8_t RESERVED_243[3];
76560   __IO uint8_t TRSV_REG077;                        /**< offset: 0x5DC */
76561        uint8_t RESERVED_244[3];
76562   __IO uint8_t TRSV_REG078;                        /**< offset: 0x5E0 */
76563        uint8_t RESERVED_245[3];
76564   __IO uint8_t TRSV_REG079;                        /**< offset: 0x5E4 */
76565        uint8_t RESERVED_246[3];
76566   __IO uint8_t TRSV_REG07A;                        /**< offset: 0x5E8 */
76567        uint8_t RESERVED_247[3];
76568   __IO uint8_t TRSV_REG07B;                        /**< offset: 0x5EC */
76569        uint8_t RESERVED_248[3];
76570   __IO uint8_t TRSV_REG07C;                        /**< offset: 0x5F0 */
76571        uint8_t RESERVED_249[3];
76572   __IO uint8_t TRSV_REG07D;                        /**< offset: 0x5F4 */
76573        uint8_t RESERVED_250[3];
76574   __IO uint8_t TRSV_REG07E;                        /**< offset: 0x5F8 */
76575        uint8_t RESERVED_251[3];
76576   __IO uint8_t TRSV_REG07F;                        /**< offset: 0x5FC */
76577        uint8_t RESERVED_252[3];
76578   __IO uint8_t TRSV_REG080;                        /**< offset: 0x600 */
76579        uint8_t RESERVED_253[3];
76580   __IO uint8_t TRSV_REG081;                        /**< offset: 0x604 */
76581        uint8_t RESERVED_254[3];
76582   __IO uint8_t TRSV_REG082;                        /**< offset: 0x608 */
76583        uint8_t RESERVED_255[3];
76584   __IO uint8_t TRSV_REG083;                        /**< offset: 0x60C */
76585        uint8_t RESERVED_256[3];
76586   __IO uint8_t TRSV_REG084;                        /**< offset: 0x610 */
76587        uint8_t RESERVED_257[3];
76588   __IO uint8_t TRSV_REG085;                        /**< offset: 0x614 */
76589        uint8_t RESERVED_258[3];
76590   __IO uint8_t TRSV_REG086;                        /**< offset: 0x618 */
76591        uint8_t RESERVED_259[3];
76592   __IO uint8_t TRSV_REG087;                        /**< offset: 0x61C */
76593        uint8_t RESERVED_260[3];
76594   __IO uint8_t TRSV_REG088;                        /**< offset: 0x620 */
76595        uint8_t RESERVED_261[3];
76596   __IO uint8_t TRSV_REG089;                        /**< offset: 0x624 */
76597        uint8_t RESERVED_262[3];
76598   __IO uint8_t TRSV_REG08A;                        /**< offset: 0x628 */
76599        uint8_t RESERVED_263[3];
76600   __IO uint8_t TRSV_REG08B;                        /**< offset: 0x62C */
76601        uint8_t RESERVED_264[3];
76602   __IO uint8_t TRSV_REG08C;                        /**< offset: 0x630 */
76603        uint8_t RESERVED_265[3];
76604   __IO uint8_t TRSV_REG08D;                        /**< offset: 0x634 */
76605        uint8_t RESERVED_266[3];
76606   __IO uint8_t TRSV_REG08E;                        /**< offset: 0x638 */
76607        uint8_t RESERVED_267[3];
76608   __IO uint8_t TRSV_REG08F;                        /**< offset: 0x63C */
76609        uint8_t RESERVED_268[3];
76610   __IO uint8_t TRSV_REG090;                        /**< offset: 0x640 */
76611        uint8_t RESERVED_269[3];
76612   __IO uint8_t TRSV_REG091;                        /**< offset: 0x644 */
76613        uint8_t RESERVED_270[3];
76614   __IO uint8_t TRSV_REG092;                        /**< offset: 0x648 */
76615        uint8_t RESERVED_271[3];
76616   __IO uint8_t TRSV_REG093;                        /**< offset: 0x64C */
76617        uint8_t RESERVED_272[3];
76618   __IO uint8_t TRSV_REG094;                        /**< offset: 0x650 */
76619        uint8_t RESERVED_273[3];
76620   __IO uint8_t TRSV_REG095;                        /**< offset: 0x654 */
76621        uint8_t RESERVED_274[3];
76622   __IO uint8_t TRSV_REG096;                        /**< offset: 0x658 */
76623        uint8_t RESERVED_275[3];
76624   __IO uint8_t TRSV_REG097;                        /**< offset: 0x65C */
76625        uint8_t RESERVED_276[3];
76626   __IO uint8_t TRSV_REG098;                        /**< offset: 0x660 */
76627        uint8_t RESERVED_277[3];
76628   __IO uint8_t TRSV_REG099;                        /**< offset: 0x664 */
76629        uint8_t RESERVED_278[3];
76630   __IO uint8_t TRSV_REG09A;                        /**< offset: 0x668 */
76631        uint8_t RESERVED_279[3];
76632   __IO uint8_t TRSV_REG09B;                        /**< offset: 0x66C */
76633        uint8_t RESERVED_280[3];
76634   __IO uint8_t TRSV_REG09C;                        /**< offset: 0x670 */
76635        uint8_t RESERVED_281[3];
76636   __IO uint8_t TRSV_REG09D;                        /**< offset: 0x674 */
76637        uint8_t RESERVED_282[3];
76638   __IO uint8_t TRSV_REG09E;                        /**< offset: 0x678 */
76639        uint8_t RESERVED_283[3];
76640   __IO uint8_t TRSV_REG09F;                        /**< offset: 0x67C */
76641        uint8_t RESERVED_284[3];
76642   __IO uint8_t TRSV_REG0A0;                        /**< offset: 0x680 */
76643        uint8_t RESERVED_285[3];
76644   __IO uint8_t TRSV_REG0A1;                        /**< offset: 0x684 */
76645        uint8_t RESERVED_286[3];
76646   __IO uint8_t TRSV_REG0A2;                        /**< offset: 0x688 */
76647        uint8_t RESERVED_287[3];
76648   __IO uint8_t TRSV_REG0A3;                        /**< offset: 0x68C */
76649        uint8_t RESERVED_288[3];
76650   __IO uint8_t TRSV_REG0A4;                        /**< offset: 0x690 */
76651        uint8_t RESERVED_289[3];
76652   __IO uint8_t TRSV_REG0A5;                        /**< offset: 0x694 */
76653        uint8_t RESERVED_290[3];
76654   __IO uint8_t TRSV_REG0A6;                        /**< offset: 0x698 */
76655        uint8_t RESERVED_291[3];
76656   __IO uint8_t TRSV_REG0A7;                        /**< offset: 0x69C */
76657        uint8_t RESERVED_292[3];
76658   __IO uint8_t TRSV_REG0A8;                        /**< offset: 0x6A0 */
76659        uint8_t RESERVED_293[3];
76660   __IO uint8_t TRSV_REG0A9;                        /**< offset: 0x6A4 */
76661        uint8_t RESERVED_294[3];
76662   __IO uint8_t TRSV_REG0AA;                        /**< offset: 0x6A8 */
76663        uint8_t RESERVED_295[3];
76664   __IO uint8_t TRSV_REG0AB;                        /**< offset: 0x6AC */
76665        uint8_t RESERVED_296[3];
76666   __IO uint8_t TRSV_REG0AC;                        /**< offset: 0x6B0 */
76667        uint8_t RESERVED_297[3];
76668   __IO uint8_t TRSV_REG0AD;                        /**< offset: 0x6B4 */
76669        uint8_t RESERVED_298[3];
76670   __IO uint8_t TRSV_REG0AE;                        /**< offset: 0x6B8 */
76671        uint8_t RESERVED_299[3];
76672   __IO uint8_t TRSV_REG0AF;                        /**< offset: 0x6BC */
76673        uint8_t RESERVED_300[3];
76674   __IO uint8_t TRSV_REG0B0;                        /**< offset: 0x6C0 */
76675        uint8_t RESERVED_301[3];
76676   __IO uint8_t TRSV_REG0B1;                        /**< offset: 0x6C4 */
76677        uint8_t RESERVED_302[3];
76678   __IO uint8_t TRSV_REG0B2;                        /**< offset: 0x6C8 */
76679        uint8_t RESERVED_303[3];
76680   __IO uint8_t TRSV_REG0B3;                        /**< offset: 0x6CC */
76681        uint8_t RESERVED_304[3];
76682   __IO uint8_t TRSV_REG0B4;                        /**< offset: 0x6D0 */
76683        uint8_t RESERVED_305[3];
76684   __IO uint8_t TRSV_REG0B5;                        /**< offset: 0x6D4 */
76685        uint8_t RESERVED_306[3];
76686   __IO uint8_t TRSV_REG0B6;                        /**< offset: 0x6D8 */
76687        uint8_t RESERVED_307[3];
76688   __IO uint8_t TRSV_REG0B7;                        /**< offset: 0x6DC */
76689        uint8_t RESERVED_308[3];
76690   __IO uint8_t TRSV_REG0B8;                        /**< offset: 0x6E0 */
76691        uint8_t RESERVED_309[3];
76692   __IO uint8_t TRSV_REG0B9;                        /**< offset: 0x6E4 */
76693        uint8_t RESERVED_310[3];
76694   __IO uint8_t TRSV_REG0BA;                        /**< offset: 0x6E8 */
76695        uint8_t RESERVED_311[3];
76696   __IO uint8_t TRSV_REG0BB;                        /**< offset: 0x6EC */
76697        uint8_t RESERVED_312[3];
76698   __IO uint8_t TRSV_REG0BC;                        /**< offset: 0x6F0 */
76699        uint8_t RESERVED_313[3];
76700   __IO uint8_t TRSV_REG0BD;                        /**< offset: 0x6F4 */
76701        uint8_t RESERVED_314[3];
76702   __IO uint8_t TRSV_REG0BE;                        /**< offset: 0x6F8 */
76703        uint8_t RESERVED_315[3];
76704   __IO uint8_t TRSV_REG0BF;                        /**< offset: 0x6FC */
76705        uint8_t RESERVED_316[3];
76706   __IO uint8_t TRSV_REG0C0;                        /**< offset: 0x700 */
76707        uint8_t RESERVED_317[3];
76708   __IO uint8_t TRSV_REG0C1;                        /**< offset: 0x704 */
76709        uint8_t RESERVED_318[3];
76710   __IO uint8_t TRSV_REG0C2;                        /**< offset: 0x708 */
76711        uint8_t RESERVED_319[3];
76712   __IO uint8_t TRSV_REG0C3;                        /**< offset: 0x70C */
76713        uint8_t RESERVED_320[3];
76714   __IO uint8_t TRSV_REG0C4;                        /**< offset: 0x710 */
76715        uint8_t RESERVED_321[3];
76716   __IO uint8_t TRSV_REG0C5;                        /**< offset: 0x714 */
76717        uint8_t RESERVED_322[3];
76718   __IO uint8_t TRSV_REG0C6;                        /**< offset: 0x718 */
76719        uint8_t RESERVED_323[3];
76720   __IO uint8_t TRSV_REG0C7;                        /**< offset: 0x71C */
76721        uint8_t RESERVED_324[3];
76722   __IO uint8_t TRSV_REG0C8;                        /**< offset: 0x720 */
76723        uint8_t RESERVED_325[3];
76724   __IO uint8_t TRSV_REG0C9;                        /**< offset: 0x724 */
76725        uint8_t RESERVED_326[3];
76726   __IO uint8_t TRSV_REG0CA;                        /**< offset: 0x728 */
76727        uint8_t RESERVED_327[3];
76728   __IO uint8_t TRSV_REG0CB;                        /**< offset: 0x72C */
76729        uint8_t RESERVED_328[3];
76730   __IO uint8_t TRSV_REG0CC;                        /**< offset: 0x730 */
76731        uint8_t RESERVED_329[3];
76732   __IO uint8_t TRSV_REG0CD;                        /**< offset: 0x734 */
76733        uint8_t RESERVED_330[3];
76734   __IO uint8_t TRSV_REG0CE;                        /**< offset: 0x738 */
76735        uint8_t RESERVED_331[3];
76736   __IO uint8_t TRSV_REG0CF;                        /**< offset: 0x73C */
76737        uint8_t RESERVED_332[3];
76738   __IO uint8_t TRSV_REG0D0;                        /**< offset: 0x740 */
76739        uint8_t RESERVED_333[3];
76740   __IO uint8_t TRSV_REG0D1;                        /**< offset: 0x744 */
76741        uint8_t RESERVED_334[3];
76742   __IO uint8_t TRSV_REG0D2;                        /**< offset: 0x748 */
76743        uint8_t RESERVED_335[3];
76744   __IO uint8_t TRSV_REG0D3;                        /**< offset: 0x74C */
76745        uint8_t RESERVED_336[3];
76746   __IO uint8_t TRSV_REG0D4;                        /**< offset: 0x750 */
76747        uint8_t RESERVED_337[3];
76748   __IO uint8_t TRSV_REG0D5;                        /**< offset: 0x754 */
76749        uint8_t RESERVED_338[3];
76750   __IO uint8_t TRSV_REG0D6;                        /**< offset: 0x758 */
76751        uint8_t RESERVED_339[3];
76752   __IO uint8_t TRSV_REG0D7;                        /**< offset: 0x75C */
76753        uint8_t RESERVED_340[3];
76754   __IO uint8_t TRSV_REG0D8;                        /**< offset: 0x760 */
76755        uint8_t RESERVED_341[3];
76756   __IO uint8_t TRSV_REG0D9;                        /**< offset: 0x764 */
76757        uint8_t RESERVED_342[3];
76758   __IO uint8_t TRSV_REG0DA;                        /**< offset: 0x768 */
76759        uint8_t RESERVED_343[3];
76760   __IO uint8_t TRSV_REG0DB;                        /**< offset: 0x76C */
76761        uint8_t RESERVED_344[3];
76762   __IO uint8_t TRSV_REG0DC;                        /**< offset: 0x770 */
76763        uint8_t RESERVED_345[3];
76764   __IO uint8_t TRSV_REG0DD;                        /**< offset: 0x774 */
76765        uint8_t RESERVED_346[3];
76766   __IO uint8_t TRSV_REG0DE;                        /**< offset: 0x778 */
76767        uint8_t RESERVED_347[3];
76768   __IO uint8_t TRSV_REG0DF;                        /**< offset: 0x77C */
76769        uint8_t RESERVED_348[3];
76770   __IO uint8_t TRSV_REG0E0;                        /**< offset: 0x780 */
76771        uint8_t RESERVED_349[3];
76772   __IO uint8_t TRSV_REG0E1;                        /**< offset: 0x784 */
76773        uint8_t RESERVED_350[3];
76774   __IO uint8_t TRSV_REG0E2;                        /**< offset: 0x788 */
76775        uint8_t RESERVED_351[3];
76776   __IO uint8_t TRSV_REG0E3;                        /**< offset: 0x78C */
76777        uint8_t RESERVED_352[3];
76778   __IO uint8_t TRSV_REG0E4;                        /**< offset: 0x790 */
76779        uint8_t RESERVED_353[3];
76780   __IO uint8_t TRSV_REG0E5;                        /**< offset: 0x794 */
76781        uint8_t RESERVED_354[3];
76782   __IO uint8_t TRSV_REG0E6;                        /**< offset: 0x798 */
76783        uint8_t RESERVED_355[3];
76784   __IO uint8_t TRSV_REG0E7;                        /**< offset: 0x79C */
76785        uint8_t RESERVED_356[3];
76786   __IO uint8_t TRSV_REG0E8;                        /**< offset: 0x7A0 */
76787        uint8_t RESERVED_357[3];
76788   __IO uint8_t TRSV_REG0E9;                        /**< offset: 0x7A4 */
76789        uint8_t RESERVED_358[3];
76790   __IO uint8_t TRSV_REG0EA;                        /**< offset: 0x7A8 */
76791        uint8_t RESERVED_359[3];
76792   __IO uint8_t TRSV_REG0EB;                        /**< offset: 0x7AC */
76793        uint8_t RESERVED_360[3];
76794   __IO uint8_t TRSV_REG0EC;                        /**< offset: 0x7B0 */
76795        uint8_t RESERVED_361[3];
76796   __IO uint8_t TRSV_REG0ED;                        /**< offset: 0x7B4 */
76797        uint8_t RESERVED_362[3];
76798   __IO uint8_t TRSV_REG0EE;                        /**< offset: 0x7B8 */
76799        uint8_t RESERVED_363[3];
76800   __IO uint8_t TRSV_REG0EF;                        /**< offset: 0x7BC */
76801        uint8_t RESERVED_364[3];
76802   __IO uint8_t TRSV_REG0F0;                        /**< offset: 0x7C0 */
76803        uint8_t RESERVED_365[3];
76804   __IO uint8_t TRSV_REG0F1;                        /**< offset: 0x7C4 */
76805        uint8_t RESERVED_366[3];
76806   __IO uint8_t TRSV_REG0F2;                        /**< offset: 0x7C8 */
76807        uint8_t RESERVED_367[3];
76808   __IO uint8_t TRSV_REG0F3;                        /**< offset: 0x7CC */
76809        uint8_t RESERVED_368[3];
76810   __IO uint8_t TRSV_REG0F4;                        /**< offset: 0x7D0 */
76811        uint8_t RESERVED_369[3];
76812   __IO uint8_t TRSV_REG0F5;                        /**< offset: 0x7D4 */
76813        uint8_t RESERVED_370[3];
76814   __IO uint8_t TRSV_REG0F6;                        /**< offset: 0x7D8 */
76815        uint8_t RESERVED_371[3];
76816   __IO uint8_t TRSV_REG0F7;                        /**< offset: 0x7DC */
76817        uint8_t RESERVED_372[3];
76818   __IO uint8_t TRSV_REG0F8;                        /**< offset: 0x7E0 */
76819        uint8_t RESERVED_373[3];
76820   __IO uint8_t TRSV_REG0F9;                        /**< offset: 0x7E4 */
76821        uint8_t RESERVED_374[3];
76822   __IO uint8_t TRSV_REG0FA;                        /**< offset: 0x7E8 */
76823        uint8_t RESERVED_375[3];
76824   __IO uint8_t TRSV_REG0FB;                        /**< offset: 0x7EC */
76825        uint8_t RESERVED_376[3];
76826   __IO uint8_t TRSV_REG0FC;                        /**< offset: 0x7F0 */
76827        uint8_t RESERVED_377[3];
76828   __IO uint8_t TRSV_REG0FD;                        /**< offset: 0x7F4 */
76829        uint8_t RESERVED_378[3];
76830   __IO uint8_t TRSV_REG0FE;                        /**< offset: 0x7F8 */
76831        uint8_t RESERVED_379[3];
76832   __IO uint8_t TRSV_REG0FF;                        /**< offset: 0x7FC */
76833 } PCIE_PHY_Type;
76834 
76835 /* ----------------------------------------------------------------------------
76836    -- PCIE_PHY Register Masks
76837    ---------------------------------------------------------------------------- */
76838 
76839 /*!
76840  * @addtogroup PCIE_PHY_Register_Masks PCIE_PHY Register Masks
76841  * @{
76842  */
76843 
76844 /*! @name CMN_REG000 -  */
76845 /*! @{ */
76846 
76847 #define PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_MASK  (0x1U)
76848 #define PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_SHIFT (0U)
76849 /*! BGR_LPF_BYPASS - BGR LPF bypass to reduce BGR settle time */
76850 #define PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_MASK)
76851 
76852 #define PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_MASK (0x2U)
76853 #define PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_SHIFT (1U)
76854 /*! OVRD_BGR_LPF_BYPASS - Override enable for bgr_lpf_bypass */
76855 #define PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_MASK)
76856 
76857 #define PCIE_PHY_CMN_REG000_BGR_EN_MASK          (0x4U)
76858 #define PCIE_PHY_CMN_REG000_BGR_EN_SHIFT         (2U)
76859 /*! BGR_EN - BGR enable */
76860 #define PCIE_PHY_CMN_REG000_BGR_EN(x)            (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_BGR_EN_SHIFT)) & PCIE_PHY_CMN_REG000_BGR_EN_MASK)
76861 
76862 #define PCIE_PHY_CMN_REG000_OVRD_BGR_EN_MASK     (0x8U)
76863 #define PCIE_PHY_CMN_REG000_OVRD_BGR_EN_SHIFT    (3U)
76864 /*! OVRD_BGR_EN - Override enable for bgr_en */
76865 #define PCIE_PHY_CMN_REG000_OVRD_BGR_EN(x)       (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_OVRD_BGR_EN_SHIFT)) & PCIE_PHY_CMN_REG000_OVRD_BGR_EN_MASK)
76866 /*! @} */
76867 
76868 /*! @name CMN_REG001 -  */
76869 /*! @{ */
76870 
76871 #define PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_MASK (0x1U)
76872 #define PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_SHIFT (0U)
76873 /*! ANA_BGR_LADDER_EN - BGR output voltage selection */
76874 #define PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_SHIFT)) & PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_MASK)
76875 
76876 #define PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_MASK  (0x2U)
76877 #define PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_SHIFT (1U)
76878 /*! ANA_BGR_CLK_EN - BGR chopper clock enable */
76879 #define PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_MASK)
76880 
76881 #define PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_MASK (0x7CU)
76882 #define PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_SHIFT (2U)
76883 /*! ANA_BGR_820M_SEL - BGR 820mV selection ( for current bias ) */
76884 #define PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_SHIFT)) & PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_MASK)
76885 /*! @} */
76886 
76887 /*! @name CMN_REG002 -  */
76888 /*! @{ */
76889 
76890 #define PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_MASK    (0x1U)
76891 #define PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_SHIFT   (0U)
76892 /*! BIAS_RCAL_EN - RX RCAL bias current enable */
76893 #define PCIE_PHY_CMN_REG002_BIAS_RCAL_EN(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_SHIFT)) & PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_MASK)
76894 
76895 #define PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_MASK (0x2U)
76896 #define PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_SHIFT (1U)
76897 /*! OVRD_BIAS_RCAL_EN - Override enable for bias_rcal_en */
76898 #define PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_SHIFT)) & PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_MASK)
76899 
76900 #define PCIE_PHY_CMN_REG002_BIAS_EN_MASK         (0x4U)
76901 #define PCIE_PHY_CMN_REG002_BIAS_EN_SHIFT        (2U)
76902 /*! BIAS_EN - Bias current enable */
76903 #define PCIE_PHY_CMN_REG002_BIAS_EN(x)           (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_BIAS_EN_SHIFT)) & PCIE_PHY_CMN_REG002_BIAS_EN_MASK)
76904 
76905 #define PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_MASK    (0x8U)
76906 #define PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_SHIFT   (3U)
76907 /*! OVRD_BIAS_EN - Override enable for bias_en */
76908 #define PCIE_PHY_CMN_REG002_OVRD_BIAS_EN(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_SHIFT)) & PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_MASK)
76909 
76910 #define PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_MASK (0x10U)
76911 #define PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_SHIFT (4U)
76912 /*! ANA_BGR_ATB_SEL - BGR ATB select */
76913 #define PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_SHIFT)) & PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_MASK)
76914 
76915 #define PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_MASK (0xE0U)
76916 #define PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_SHIFT (5U)
76917 /*! ANA_BGR_LADDER_SEL - Resistor ladder voltage selection */
76918 #define PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_SHIFT)) & PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_MASK)
76919 /*! @} */
76920 
76921 /*! @name CMN_REG003 -  */
76922 /*! @{ */
76923 
76924 #define PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_MASK (0x3U)
76925 #define PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_SHIFT (0U)
76926 /*! ANA_BIAS_TX_RCAL_IREXT_CTRL - REXT-refered bias current control MSB for TX RCAL */
76927 #define PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_SHIFT)) & PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_MASK)
76928 
76929 #define PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_MASK (0xCU)
76930 #define PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_SHIFT (2U)
76931 /*! ANA_BIAS_RX_RCAL_IREXT_CTRL - REXT-refered bias current controlI for RX RCAL */
76932 #define PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_SHIFT)) & PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_MASK)
76933 
76934 #define PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_MASK (0x30U)
76935 #define PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_SHIFT (4U)
76936 /*! ANA_BIAS_IREXT_CTRL - REXT-refered bias current controlI for overall IP */
76937 #define PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_SHIFT)) & PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_MASK)
76938 /*! @} */
76939 
76940 /*! @name CMN_REG004 -  */
76941 /*! @{ */
76942 
76943 #define PCIE_PHY_CMN_REG004_PLL_EN_MASK          (0x1U)
76944 #define PCIE_PHY_CMN_REG004_PLL_EN_SHIFT         (0U)
76945 /*! PLL_EN - PLL enable */
76946 #define PCIE_PHY_CMN_REG004_PLL_EN(x)            (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG004_PLL_EN_SHIFT)) & PCIE_PHY_CMN_REG004_PLL_EN_MASK)
76947 
76948 #define PCIE_PHY_CMN_REG004_OVRD_PLL_EN_MASK     (0x2U)
76949 #define PCIE_PHY_CMN_REG004_OVRD_PLL_EN_SHIFT    (1U)
76950 /*! OVRD_PLL_EN - Override enable for pll_en */
76951 #define PCIE_PHY_CMN_REG004_OVRD_PLL_EN(x)       (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG004_OVRD_PLL_EN_SHIFT)) & PCIE_PHY_CMN_REG004_OVRD_PLL_EN_MASK)
76952 /*! @} */
76953 
76954 /*! @name CMN_REG005 -  */
76955 /*! @{ */
76956 
76957 #define PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_MASK    (0x1U)
76958 #define PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_SHIFT   (0U)
76959 /*! PLL_AFC_RSTN - PLL AFC reset. When AFC reset is asserted, the previous AFC result is held. When
76960  *    AFC reset is released, AFC starts from the previous AFC code stored in internal memory.
76961  */
76962 #define PCIE_PHY_CMN_REG005_PLL_AFC_RSTN(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_MASK)
76963 
76964 #define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_MASK (0x2U)
76965 #define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_SHIFT (1U)
76966 /*! OVRD_PLL_AFC_RSTN - Override enable for pll_afc_rstn */
76967 #define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_MASK)
76968 
76969 #define PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_MASK (0x4U)
76970 #define PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_SHIFT (2U)
76971 /*! PLL_AFC_INIT_RSTN - PLL AFC initial reset. When initial reset is asserted, the previous AFC
76972  *    result is reset. When initial reset is released, AFC starts from the initial AFC code given in
76973  *    i_rx_cdr_afc_sel_logic[3:0].
76974  */
76975 #define PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_MASK)
76976 
76977 #define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_MASK (0x8U)
76978 #define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_SHIFT (3U)
76979 /*! OVRD_PLL_AFC_INIT_RSTN - Override enable for pll_afc_init_rstn */
76980 #define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_MASK)
76981 
76982 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_MASK (0x10U)
76983 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_SHIFT (4U)
76984 /*! PLL_VCO_MODE_G4 - [GEN4] */
76985 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_MASK)
76986 
76987 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_MASK (0x20U)
76988 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_SHIFT (5U)
76989 /*! PLL_VCO_MODE_G3 - [GEN3] */
76990 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_MASK)
76991 
76992 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_MASK (0x40U)
76993 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_SHIFT (6U)
76994 /*! PLL_VCO_MODE_G2 - [GEN2] */
76995 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_MASK)
76996 
76997 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_MASK (0x80U)
76998 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_SHIFT (7U)
76999 /*! PLL_VCO_MODE_G1 - [GEN1] PLL VCO selection */
77000 #define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_MASK)
77001 /*! @} */
77002 
77003 /*! @name CMN_REG006 -  */
77004 /*! @{ */
77005 
77006 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_MASK (0x3U)
77007 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_SHIFT (0U)
77008 /*! ANA_PLL_AFC_MAN_LC_CODE_SEL - Manual PLL AFC code selection (MSB) */
77009 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_MASK)
77010 
77011 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_MASK (0x4U)
77012 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_SHIFT (2U)
77013 /*! ANA_PLL_AFC_FROM_PRE_CODE - PLL AFC option in restart case */
77014 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_MASK)
77015 
77016 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_MASK  (0x8U)
77017 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_SHIFT (3U)
77018 /*! ANA_PLL_AFC_EN - PLL AFC enable; if enabled, VCO frequency is automatically calibrated. If
77019  *    disabled, VCO starts to oscillate with fixed AFC code of i_pll_man_bsel_m and _l.
77020  */
77021 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_MASK)
77022 
77023 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_MASK (0x10U)
77024 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_SHIFT (4U)
77025 /*! ANA_PLL_AFC_CODE_FORCE - PLL AFC code manual selection enable */
77026 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_MASK)
77027 
77028 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_MASK (0x20U)
77029 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_SHIFT (5U)
77030 /*! ANA_PLL_AFC_CLK_DIV2_EN - PLL AFC clock frequency selection */
77031 #define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_MASK)
77032 /*! @} */
77033 
77034 /*! @name CMN_REG007 -  */
77035 /*! @{ */
77036 
77037 #define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_MASK (0xFU)
77038 #define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_SHIFT (0U)
77039 /*! ANA_PLL_AFC_STB_NUM - Number of reference clock cycle to check VCO stabilization during PLL AFC start */
77040 #define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_SHIFT)) & PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_MASK)
77041 
77042 #define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_MASK (0xF0U)
77043 #define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_SHIFT (4U)
77044 /*! ANA_PLL_AFC_MAN_RING_CODE_SEL - Manual PLL AFC code selection (LSB) */
77045 #define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_SHIFT)) & PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_MASK)
77046 /*! @} */
77047 
77048 /*! @name CMN_REG008 -  */
77049 /*! @{ */
77050 
77051 #define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_MASK (0x1U)
77052 #define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_SHIFT (0U)
77053 /*! ANA_PLL_AFC_VCI_FORCE - PLL control voltage force for open-loop test purpose */
77054 #define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_SHIFT)) & PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_MASK)
77055 
77056 #define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_MASK (0x1EU)
77057 #define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_SHIFT (1U)
77058 /*! ANA_PLL_AFC_TOL_NUM - PLL VCO stabilization tolerance; VCO is considered as settled-down if
77059  *    |counter difference|&lt;i_pll_afc_tol during i_pll_afc_stb_num
77060  */
77061 #define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_SHIFT)) & PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_MASK)
77062 /*! @} */
77063 
77064 /*! @name CMN_REG009 -  */
77065 /*! @{ */
77066 
77067 #define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_MASK (0x7U)
77068 #define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_SHIFT (0U)
77069 /*! ANA_PLL_AFC_VCO_CNT_WAIT_NUM - Number of reference clock cycle to count VCO clock during AFC */
77070 #define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_SHIFT)) & PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_MASK)
77071 
77072 #define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_MASK (0xF8U)
77073 #define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_SHIFT (3U)
77074 /*! ANA_PLL_AFC_VCO_CNT_RUN_NUM - Number of reference clock cycle to wait VCO clock during AFC */
77075 #define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_SHIFT)) & PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_MASK)
77076 /*! @} */
77077 
77078 /*! @name CMN_REG00A -  */
77079 /*! @{ */
77080 
77081 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_MASK (0x1U)
77082 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_SHIFT (0U)
77083 /*! ANA_PLL_AGMC_MAN_GM_SEL_EN - PLL LC VCO GM code selection */
77084 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_MASK)
77085 
77086 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_MASK (0x6U)
77087 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_SHIFT (1U)
77088 /*! ANA_PLL_AGMC_GM_ADD - Offset code to be added to final gm code */
77089 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_MASK)
77090 
77091 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_MASK (0x8U)
77092 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_SHIFT (3U)
77093 /*! ANA_PLL_AGMC_FROM_MAX_GM - PLL LC VCO automatic gm search initial condition */
77094 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_MASK)
77095 
77096 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_MASK (0x10U)
77097 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_SHIFT (4U)
77098 /*! ANA_PLL_AGMC_COMP_EN - Comparator enable for PLL LC VCO automatic gm search */
77099 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_MASK)
77100 
77101 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_MASK (0xE0U)
77102 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_SHIFT (5U)
77103 /*! ANA_PLL_AFC_VCO_START_CRITERION - Minimum PLL VCO counter value to start AFC (Criterion to suppose PLL VCO successfully start to oscillate) */
77104 #define PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_MASK)
77105 /*! @} */
77106 
77107 /*! @name CMN_REG00B -  */
77108 /*! @{ */
77109 
77110 #define PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_MASK (0xFU)
77111 #define PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_SHIFT (0U)
77112 /*! ANA_PLL_AGMC_MAN_GM_SEL - Manual GM code selection for LC VCO */
77113 #define PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_SHIFT)) & PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_MASK)
77114 /*! @} */
77115 
77116 /*! @name CMN_REG00C -  */
77117 /*! @{ */
77118 
77119 #define PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_MASK (0xFFU)
77120 #define PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_SHIFT (0U)
77121 /*! PLL_AGMC_TG_CODE_G1 - [GEN1] Target counter value for automatic GM search of LC VCO */
77122 #define PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_SHIFT)) & PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_MASK)
77123 /*! @} */
77124 
77125 /*! @name CMN_REG00D -  */
77126 /*! @{ */
77127 
77128 #define PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_MASK (0xFFU)
77129 #define PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_SHIFT (0U)
77130 /*! PLL_AGMC_TG_CODE_G2 - [GEN2] */
77131 #define PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_SHIFT)) & PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_MASK)
77132 /*! @} */
77133 
77134 /*! @name CMN_REG00E -  */
77135 /*! @{ */
77136 
77137 #define PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_MASK (0xFFU)
77138 #define PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_SHIFT (0U)
77139 /*! PLL_AGMC_TG_CODE_G3 - [GEN3] */
77140 #define PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_SHIFT)) & PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_MASK)
77141 /*! @} */
77142 
77143 /*! @name CMN_REG00F -  */
77144 /*! @{ */
77145 
77146 #define PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_MASK (0xFFU)
77147 #define PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_SHIFT (0U)
77148 /*! PLL_AGMC_TG_CODE_G4 - [GEN4] */
77149 #define PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_SHIFT)) & PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_MASK)
77150 /*! @} */
77151 
77152 /*! @name CMN_REG010 -  */
77153 /*! @{ */
77154 
77155 #define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_MASK (0x7U)
77156 #define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_SHIFT (0U)
77157 /*! PLL_ANA_CPI_CTRL_COARSE_G2 - [GEN1] PLL integral path charge-pump current contorl */
77158 #define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_MASK)
77159 
77160 #define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_MASK (0x38U)
77161 #define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_SHIFT (3U)
77162 /*! PLL_ANA_CPI_CTRL_COARSE_G1 - [GEN1] PLL integral path charge-pump current contorl */
77163 #define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_MASK)
77164 /*! @} */
77165 
77166 /*! @name CMN_REG011 -  */
77167 /*! @{ */
77168 
77169 #define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_MASK (0x7U)
77170 #define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_SHIFT (0U)
77171 /*! PLL_ANA_CPI_CTRL_COARSE_G4 - [GEN1] PLL integral path charge-pump current contorl */
77172 #define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_MASK)
77173 
77174 #define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_MASK (0x38U)
77175 #define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_SHIFT (3U)
77176 /*! PLL_ANA_CPI_CTRL_COARSE_G3 - [GEN1] PLL integral path charge-pump current contorl */
77177 #define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_MASK)
77178 /*! @} */
77179 
77180 /*! @name CMN_REG012 -  */
77181 /*! @{ */
77182 
77183 #define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_MASK (0x7U)
77184 #define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_SHIFT (0U)
77185 /*! PLL_ANA_CPI_CTRL_FINE_G2 - [GEN1] PLL integral path charge-pump current contorl */
77186 #define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_MASK)
77187 
77188 #define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_MASK (0x38U)
77189 #define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_SHIFT (3U)
77190 /*! PLL_ANA_CPI_CTRL_FINE_G1 - [GEN1] PLL integral path charge-pump current contorl */
77191 #define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_MASK)
77192 /*! @} */
77193 
77194 /*! @name CMN_REG013 -  */
77195 /*! @{ */
77196 
77197 #define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_MASK (0x7U)
77198 #define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_SHIFT (0U)
77199 /*! PLL_ANA_CPI_CTRL_FINE_G4 - [GEN1] PLL integral path charge-pump current contorl */
77200 #define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_MASK)
77201 
77202 #define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_MASK (0x38U)
77203 #define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_SHIFT (3U)
77204 /*! PLL_ANA_CPI_CTRL_FINE_G3 - [GEN1] PLL integral path charge-pump current contorl */
77205 #define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_MASK)
77206 /*! @} */
77207 
77208 /*! @name CMN_REG014 -  */
77209 /*! @{ */
77210 
77211 #define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_MASK (0xFU)
77212 #define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_SHIFT (0U)
77213 /*! PLL_ANA_CPP_CTRL_COARSE_G2 - [GEN1] PLL integral path charge-pump current contorl */
77214 #define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_MASK)
77215 
77216 #define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_MASK (0xF0U)
77217 #define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_SHIFT (4U)
77218 /*! PLL_ANA_CPP_CTRL_COARSE_G1 - [GEN1] PLL integral path charge-pump current contorl */
77219 #define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_MASK)
77220 /*! @} */
77221 
77222 /*! @name CMN_REG015 -  */
77223 /*! @{ */
77224 
77225 #define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_MASK (0xFU)
77226 #define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_SHIFT (0U)
77227 /*! PLL_ANA_CPP_CTRL_COARSE_G4 - [GEN1] PLL integral path charge-pump current contorl */
77228 #define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_MASK)
77229 
77230 #define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_MASK (0xF0U)
77231 #define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_SHIFT (4U)
77232 /*! PLL_ANA_CPP_CTRL_COARSE_G3 - [GEN1] PLL integral path charge-pump current contorl */
77233 #define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_MASK)
77234 /*! @} */
77235 
77236 /*! @name CMN_REG016 -  */
77237 /*! @{ */
77238 
77239 #define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_MASK (0xFU)
77240 #define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_SHIFT (0U)
77241 /*! PLL_ANA_CPP_CTRL_FINE_G2 - [GEN1] PLL integral path charge-pump current contorl */
77242 #define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_MASK)
77243 
77244 #define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_MASK (0xF0U)
77245 #define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_SHIFT (4U)
77246 /*! PLL_ANA_CPP_CTRL_FINE_G1 - [GEN1] PLL integral path charge-pump current contorl */
77247 #define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_MASK)
77248 /*! @} */
77249 
77250 /*! @name CMN_REG017 -  */
77251 /*! @{ */
77252 
77253 #define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_MASK (0xFU)
77254 #define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_SHIFT (0U)
77255 /*! PLL_ANA_CPP_CTRL_FINE_G4 - [GEN1] PLL integral path charge-pump current contorl */
77256 #define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_MASK)
77257 
77258 #define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_MASK (0xF0U)
77259 #define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_SHIFT (4U)
77260 /*! PLL_ANA_CPP_CTRL_FINE_G3 - [GEN1] PLL integral path charge-pump current contorl */
77261 #define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_MASK)
77262 /*! @} */
77263 
77264 /*! @name CMN_REG018 -  */
77265 /*! @{ */
77266 
77267 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_MASK (0x7U)
77268 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_SHIFT (0U)
77269 /*! ANA_PLL_ANA_LC_GM_COMP_VREF_SEL - PLL GM comparator reference voltage selection */
77270 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_SHIFT)) & PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_MASK)
77271 
77272 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_MASK (0x8U)
77273 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_SHIFT (3U)
77274 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_SHIFT)) & PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_MASK)
77275 
77276 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_MASK (0x70U)
77277 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_SHIFT (4U)
77278 /*! ANA_PLL_ANA_LC_CAP_OFFSET_SEL - LC VCO varactor bias voltage selection */
77279 #define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_SHIFT)) & PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_MASK)
77280 /*! @} */
77281 
77282 /*! @name CMN_REG019 -  */
77283 /*! @{ */
77284 
77285 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_MASK (0x7U)
77286 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_SHIFT (0U)
77287 /*! ANA_PLL_ANA_LC_VREG_R_SEL - LC VCO voltage regulator output control */
77288 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_SHIFT)) & PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_MASK)
77289 
77290 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_MASK (0x8U)
77291 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_SHIFT (3U)
77292 /*! ANA_PLL_ANA_LC_VREF_BYPASS - LPF on reference voltage for PLL LC VCO bypass */
77293 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_MASK)
77294 
77295 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_MASK (0x30U)
77296 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_SHIFT (4U)
77297 /*! ANA_PLL_ANA_LC_VREG_I_CTRL - LC VCO Vreg current branch enable (1+1/20 or 1+ 1/33) */
77298 #define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_SHIFT)) & PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_MASK)
77299 /*! @} */
77300 
77301 /*! @name CMN_REG01A -  */
77302 /*! @{ */
77303 
77304 #define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_MASK (0x7U)
77305 #define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_SHIFT (0U)
77306 /*! PLL_ANA_LPF_C_SEL_COARSE_G2 - [GEN2] [Coarse Mode] */
77307 #define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_MASK)
77308 
77309 #define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_MASK (0x38U)
77310 #define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_SHIFT (3U)
77311 /*! PLL_ANA_LPF_C_SEL_COARSE_G1 - [GEN1] [Coarse Mode] PLL loop filter capacitor control */
77312 #define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_MASK)
77313 /*! @} */
77314 
77315 /*! @name CMN_REG01B -  */
77316 /*! @{ */
77317 
77318 #define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_MASK (0x7U)
77319 #define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_SHIFT (0U)
77320 /*! PLL_ANA_LPF_C_SEL_COARSE_G4 - [GEN4] [Coarse Mode] */
77321 #define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_MASK)
77322 
77323 #define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_MASK (0x38U)
77324 #define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_SHIFT (3U)
77325 /*! PLL_ANA_LPF_C_SEL_COARSE_G3 - [GEN3] [Coarse Mode] */
77326 #define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_MASK)
77327 /*! @} */
77328 
77329 /*! @name CMN_REG01C -  */
77330 /*! @{ */
77331 
77332 #define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_MASK (0x7U)
77333 #define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_SHIFT (0U)
77334 /*! PLL_ANA_LPF_C_SEL_FINE_G2 - [GEN2] [Fine Mode] */
77335 #define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_MASK)
77336 
77337 #define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_MASK (0x38U)
77338 #define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_SHIFT (3U)
77339 /*! PLL_ANA_LPF_C_SEL_FINE_G1 - [GEN1] [Fine Mode] PLL loop filter capacitor control */
77340 #define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_MASK)
77341 /*! @} */
77342 
77343 /*! @name CMN_REG01D -  */
77344 /*! @{ */
77345 
77346 #define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_MASK (0x7U)
77347 #define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_SHIFT (0U)
77348 /*! PLL_ANA_LPF_C_SEL_FINE_G4 - [GEN4] [Fine Mode] */
77349 #define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_MASK)
77350 
77351 #define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_MASK (0x38U)
77352 #define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_SHIFT (3U)
77353 /*! PLL_ANA_LPF_C_SEL_FINE_G3 - [GEN3] [Fine Mode] */
77354 #define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_MASK)
77355 /*! @} */
77356 
77357 /*! @name CMN_REG01E -  */
77358 /*! @{ */
77359 
77360 #define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_MASK (0xFU)
77361 #define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_SHIFT (0U)
77362 /*! PLL_ANA_LPF_R_SEL_COARSE_G2 - [GEN2] [Coarse Mode] */
77363 #define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_MASK)
77364 
77365 #define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_MASK (0xF0U)
77366 #define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_SHIFT (4U)
77367 /*! PLL_ANA_LPF_R_SEL_COARSE_G1 - [GEN1] [Coarse Mode] PLL loop filter resistor control */
77368 #define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_MASK)
77369 /*! @} */
77370 
77371 /*! @name CMN_REG01F -  */
77372 /*! @{ */
77373 
77374 #define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_MASK (0xFU)
77375 #define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_SHIFT (0U)
77376 /*! PLL_ANA_LPF_R_SEL_COARSE_G4 - [GEN4] [Coarse Mode] */
77377 #define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_MASK)
77378 
77379 #define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_MASK (0xF0U)
77380 #define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_SHIFT (4U)
77381 /*! PLL_ANA_LPF_R_SEL_COARSE_G3 - [GEN3] [Coarse Mode] */
77382 #define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_MASK)
77383 /*! @} */
77384 
77385 /*! @name CMN_REG020 -  */
77386 /*! @{ */
77387 
77388 #define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_MASK (0xFU)
77389 #define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_SHIFT (0U)
77390 /*! PLL_ANA_LPF_R_SEL_FINE_G2 - [GEN2] [Fine Mode] */
77391 #define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_MASK)
77392 
77393 #define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_MASK (0xF0U)
77394 #define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_SHIFT (4U)
77395 /*! PLL_ANA_LPF_R_SEL_FINE_G1 - [GEN1] [Fine Mode] PLL loop filter resistor control */
77396 #define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_MASK)
77397 /*! @} */
77398 
77399 /*! @name CMN_REG021 -  */
77400 /*! @{ */
77401 
77402 #define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_MASK (0xFU)
77403 #define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_SHIFT (0U)
77404 /*! PLL_ANA_LPF_R_SEL_FINE_G4 - [GEN4] [Fine Mode] */
77405 #define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_MASK)
77406 
77407 #define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_MASK (0xF0U)
77408 #define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_SHIFT (4U)
77409 /*! PLL_ANA_LPF_R_SEL_FINE_G3 - [GEN3] [Fine Mode] */
77410 #define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_MASK)
77411 /*! @} */
77412 
77413 /*! @name CMN_REG022 -  */
77414 /*! @{ */
77415 
77416 #define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_MASK (0x1U)
77417 #define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_SHIFT (0U)
77418 /*! ANA_PLL_ANA_RING_IQ_DIV_EN - I/Q divider enable for PLL ring VCO clock */
77419 #define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_SHIFT)) & PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_MASK)
77420 
77421 #define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_MASK (0x1EU)
77422 #define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_SHIFT (1U)
77423 /*! ANA_PLL_ANA_RING_DCC_EN - PLL ring VCO DCC enable for each phase */
77424 #define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_SHIFT)) & PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_MASK)
77425 /*! @} */
77426 
77427 /*! @name CMN_REG023 -  */
77428 /*! @{ */
77429 
77430 #define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_MASK (0x1U)
77431 #define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_SHIFT (0U)
77432 /*! ANA_PLL_ANA_VCI_TEST_EN - PLL VCO test mode enable */
77433 #define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_SHIFT)) & PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_MASK)
77434 
77435 #define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_MASK (0xEU)
77436 #define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_SHIFT (1U)
77437 /*! ANA_PLL_ANA_VCI_SEL - PLL control voltage selection in AFC or open-loop test */
77438 #define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_SHIFT)) & PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_MASK)
77439 
77440 #define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_MASK (0x30U)
77441 #define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_SHIFT (4U)
77442 /*! PLL_ANA_RING_PI_RATIO_CTRL_FINE - Ratio between proportional and integral path gain */
77443 #define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_SHIFT)) & PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_MASK)
77444 
77445 #define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_MASK (0xC0U)
77446 #define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_SHIFT (6U)
77447 /*! PLL_ANA_RING_PI_RATIO_CTRL_COARSE - Ratio between proportional and integral path gain */
77448 #define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_SHIFT)) & PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_MASK)
77449 /*! @} */
77450 
77451 /*! @name CMN_REG024 -  */
77452 /*! @{ */
77453 
77454 #define PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_MASK (0x1U)
77455 #define PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_SHIFT (0U)
77456 /*! ANA_PLL_EOM_PH_FINE_STEP - EOM phase resolution enhancement */
77457 #define PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_SHIFT)) & PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_MASK)
77458 
77459 #define PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_MASK (0xFEU)
77460 #define PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_SHIFT (1U)
77461 /*! ANA_PLL_ATB_SEL - Select PLL ATB */
77462 #define PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_SHIFT)) & PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_MASK)
77463 /*! @} */
77464 
77465 /*! @name CMN_REG025 -  */
77466 /*! @{ */
77467 
77468 #define PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_MASK (0x1U)
77469 #define PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_SHIFT (0U)
77470 /*! ANA_PLL_FLD_FAST_BYPASS - PLL fast frequency lock detection bypass */
77471 #define PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_MASK)
77472 
77473 #define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_MASK (0x1EU)
77474 #define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_SHIFT (1U)
77475 /*! ANA_PLL_EOM_PH_SEL - EOM phase selection */
77476 #define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_SHIFT)) & PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_MASK)
77477 
77478 #define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_MASK (0x20U)
77479 #define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_SHIFT (5U)
77480 /*! ANA_PLL_EOM_PH_FIX - Phase shift enable for EOM */
77481 #define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_SHIFT)) & PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_MASK)
77482 /*! @} */
77483 
77484 /*! @name CMN_REG026 -  */
77485 /*! @{ */
77486 
77487 #define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_MASK (0x1FU)
77488 #define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_SHIFT (0U)
77489 /*! ANA_PLL_FLD_LOCK_TOL_NUM - FLD lock tolerance setting */
77490 #define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_SHIFT)) & PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_MASK)
77491 
77492 #define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_MASK (0xE0U)
77493 #define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_SHIFT (5U)
77494 /*! ANA_PLL_FLD_FAST_SETTLE_NUM - Number of reference clock cycle to check VCO stabilization in fast FLD */
77495 #define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_SHIFT)) & PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_MASK)
77496 /*! @} */
77497 
77498 /*! @name CMN_REG027 -  */
77499 /*! @{ */
77500 
77501 #define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_MASK (0x1U)
77502 #define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_SHIFT (0U)
77503 /*! ANA_PLL_FLD_SLOW_BYPASS - PLL slow frequency lock detection bypass */
77504 #define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_MASK)
77505 
77506 #define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_MASK (0x2U)
77507 #define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_SHIFT (1U)
77508 /*! ANA_PLL_FLD_NON_CONTINUOUS_MODE - Check frequency lock detection of PLL */
77509 #define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_SHIFT)) & PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_MASK)
77510 /*! @} */
77511 
77512 /*! @name CMN_REG028 -  */
77513 /*! @{ */
77514 
77515 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_MASK    (0x1U)
77516 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_SHIFT   (0U)
77517 /*! PLL_PI_EN_G4 - [GEN4] */
77518 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G4(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_MASK)
77519 
77520 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_MASK    (0x2U)
77521 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_SHIFT   (1U)
77522 /*! PLL_PI_EN_G3 - [GEN3] */
77523 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G3(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_MASK)
77524 
77525 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_MASK    (0x4U)
77526 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_SHIFT   (2U)
77527 /*! PLL_PI_EN_G2 - [GEN2] */
77528 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G2(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_MASK)
77529 
77530 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_MASK    (0x8U)
77531 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_SHIFT   (3U)
77532 /*! PLL_PI_EN_G1 - [GEN1] PLL phase interpolator enable */
77533 #define PCIE_PHY_CMN_REG028_PLL_PI_EN_G1(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_MASK)
77534 /*! @} */
77535 
77536 /*! @name CMN_REG029 -  */
77537 /*! @{ */
77538 
77539 #define PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_MASK   (0xFU)
77540 #define PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_SHIFT  (0U)
77541 /*! PLL_PI_STR_G2 - [GEN2] */
77542 #define PCIE_PHY_CMN_REG029_PLL_PI_STR_G2(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_SHIFT)) & PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_MASK)
77543 
77544 #define PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_MASK   (0xF0U)
77545 #define PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_SHIFT  (4U)
77546 /*! PLL_PI_STR_G1 - [GEN1] PLL phase interpolator input buffer strength control for Gen3 and Gen4 ( for 8GHz VCO ) */
77547 #define PCIE_PHY_CMN_REG029_PLL_PI_STR_G1(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_SHIFT)) & PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_MASK)
77548 /*! @} */
77549 
77550 /*! @name CMN_REG02A -  */
77551 /*! @{ */
77552 
77553 #define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_MASK   (0xFU)
77554 #define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_SHIFT  (0U)
77555 /*! PLL_PI_STR_G4 - [GEN4] */
77556 #define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_SHIFT)) & PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_MASK)
77557 
77558 #define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_MASK   (0xF0U)
77559 #define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_SHIFT  (4U)
77560 /*! PLL_PI_STR_G3 - [GEN3] */
77561 #define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_SHIFT)) & PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_MASK)
77562 /*! @} */
77563 
77564 /*! @name CMN_REG02B -  */
77565 /*! @{ */
77566 
77567 #define PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_MASK (0x1U)
77568 #define PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_SHIFT (0U)
77569 /*! PLL_PMS_PDIV_RSTN - PLL pre-divider reset */
77570 #define PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_MASK)
77571 
77572 #define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_MASK (0x2U)
77573 #define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_SHIFT (1U)
77574 /*! OVRD_PLL_PMS_PDIV_RSTN - Override enable for pll_pms_pdiv_rstn */
77575 #define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_MASK)
77576 
77577 #define PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_MASK (0x4U)
77578 #define PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_SHIFT (2U)
77579 /*! PLL_PMS_MDIV_RSTN - PLL main divider reset */
77580 #define PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_MASK)
77581 
77582 #define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_MASK (0x8U)
77583 #define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_SHIFT (3U)
77584 /*! OVRD_PLL_PMS_MDIV_RSTN - Override enable for pll_pms_mdiv_rstn */
77585 #define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_MASK)
77586 /*! @} */
77587 
77588 /*! @name CMN_REG02C -  */
77589 /*! @{ */
77590 
77591 #define PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_MASK (0xFFU)
77592 #define PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_SHIFT (0U)
77593 /*! PLL_PMS_MDIV_AFC_G1 - [GEN1] PLL AFC target value (fVCO/fREF) setting */
77594 #define PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_SHIFT)) & PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_MASK)
77595 /*! @} */
77596 
77597 /*! @name CMN_REG02D -  */
77598 /*! @{ */
77599 
77600 #define PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_MASK (0xFFU)
77601 #define PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_SHIFT (0U)
77602 /*! PLL_PMS_MDIV_AFC_G2 - [GEN2] */
77603 #define PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_SHIFT)) & PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_MASK)
77604 /*! @} */
77605 
77606 /*! @name CMN_REG02E -  */
77607 /*! @{ */
77608 
77609 #define PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_MASK (0xFFU)
77610 #define PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_SHIFT (0U)
77611 /*! PLL_PMS_MDIV_AFC_G3 - [GEN3] */
77612 #define PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_SHIFT)) & PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_MASK)
77613 /*! @} */
77614 
77615 /*! @name CMN_REG02F -  */
77616 /*! @{ */
77617 
77618 #define PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_MASK (0xFFU)
77619 #define PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_SHIFT (0U)
77620 /*! PLL_PMS_MDIV_AFC_G4 - [GEN4] */
77621 #define PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_SHIFT)) & PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_MASK)
77622 /*! @} */
77623 
77624 /*! @name CMN_REG030 -  */
77625 /*! @{ */
77626 
77627 #define PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_MASK (0xFFU)
77628 #define PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_SHIFT (0U)
77629 /*! PLL_PMS_MDIV_G1 - [GEN1] PLL main divider setting */
77630 #define PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_SHIFT)) & PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_MASK)
77631 /*! @} */
77632 
77633 /*! @name CMN_REG031 -  */
77634 /*! @{ */
77635 
77636 #define PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_MASK (0xFFU)
77637 #define PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_SHIFT (0U)
77638 /*! PLL_PMS_MDIV_G2 - [GEN2] */
77639 #define PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_SHIFT)) & PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_MASK)
77640 /*! @} */
77641 
77642 /*! @name CMN_REG032 -  */
77643 /*! @{ */
77644 
77645 #define PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_MASK (0xFFU)
77646 #define PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_SHIFT (0U)
77647 /*! PLL_PMS_MDIV_G3 - [GEN3] */
77648 #define PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_SHIFT)) & PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_MASK)
77649 /*! @} */
77650 
77651 /*! @name CMN_REG033 -  */
77652 /*! @{ */
77653 
77654 #define PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_MASK (0xFFU)
77655 #define PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_SHIFT (0U)
77656 /*! PLL_PMS_MDIV_G4 - [GEN4] */
77657 #define PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_SHIFT)) & PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_MASK)
77658 /*! @} */
77659 
77660 /*! @name CMN_REG034 -  */
77661 /*! @{ */
77662 
77663 #define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_MASK (0xFU)
77664 #define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_SHIFT (0U)
77665 /*! ANA_PLL_PMS_PDIV - PLL pre-divider setting */
77666 #define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_SHIFT)) & PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_MASK)
77667 
77668 #define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_MASK (0x10U)
77669 #define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_SHIFT (4U)
77670 /*! ANA_PLL_PMS_MDIV_X2_EN - PLL main divider extra X2 enable */
77671 #define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_SHIFT)) & PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_MASK)
77672 /*! @} */
77673 
77674 /*! @name CMN_REG035 -  */
77675 /*! @{ */
77676 
77677 #define PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_MASK (0xFU)
77678 #define PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_SHIFT (0U)
77679 /*! ANA_PLL_PMS_REFDIV - PLL reference clock divider setting */
77680 #define PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_SHIFT)) & PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_MASK)
77681 /*! @} */
77682 
77683 /*! @name CMN_REG036 -  */
77684 /*! @{ */
77685 
77686 #define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_MASK (0xFU)
77687 #define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_SHIFT (0U)
77688 /*! PLL_PMS_SDIV_G2 - [GEN2] */
77689 #define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_SHIFT)) & PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_MASK)
77690 
77691 #define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_MASK (0xF0U)
77692 #define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_SHIFT (4U)
77693 /*! PLL_PMS_SDIV_G1 - [GEN1] PLL post divider setting */
77694 #define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_SHIFT)) & PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_MASK)
77695 /*! @} */
77696 
77697 /*! @name CMN_REG037 -  */
77698 /*! @{ */
77699 
77700 #define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_MASK (0xFU)
77701 #define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_SHIFT (0U)
77702 /*! PLL_PMS_SDIV_G4 - [GEN4] */
77703 #define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_SHIFT)) & PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_MASK)
77704 
77705 #define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_MASK (0xF0U)
77706 #define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_SHIFT (4U)
77707 /*! PLL_PMS_SDIV_G3 - [GEN3] */
77708 #define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_SHIFT)) & PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_MASK)
77709 /*! @} */
77710 
77711 /*! @name CMN_REG038 -  */
77712 /*! @{ */
77713 
77714 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_MASK (0x1U)
77715 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_SHIFT (0U)
77716 /*! ANA_PLL_REF_CHOPPER_CLK_EN - Chopper clk enable */
77717 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_MASK)
77718 
77719 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_MASK (0x6U)
77720 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_SHIFT (1U)
77721 /*! ANA_PLL_REF_CHOPPER_CLK_DIV_SEL - Chopper clk divider value */
77722 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_SHIFT)) & PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_MASK)
77723 
77724 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_MASK (0x18U)
77725 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_SHIFT (3U)
77726 /*! ANA_PLL_REF_BYPASS_CLK_SEL - PLL Bypass clock selection */
77727 #define PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_MASK)
77728 
77729 #define PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK (0x20U)
77730 #define PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT (5U)
77731 /*! PLL_REF_CHOPPER_CLK_DIV_RSTN - Chopper clk divider reset */
77732 #define PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK)
77733 
77734 #define PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK (0x40U)
77735 #define PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT (6U)
77736 /*! OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN - Override enable for pll_ref_chopper_clk_div_rstn */
77737 #define PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK)
77738 /*! @} */
77739 
77740 /*! @name CMN_REG039 -  */
77741 /*! @{ */
77742 
77743 #define PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_MASK (0x1U)
77744 #define PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_SHIFT (0U)
77745 #define PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_MASK)
77746 
77747 #define PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_MASK (0x6U)
77748 #define PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_SHIFT (1U)
77749 /*! PLL_REF_CLK_SEL - PLL reference clock selection */
77750 #define PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_MASK)
77751 
77752 #define PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_MASK (0x8U)
77753 #define PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_SHIFT (3U)
77754 /*! OVRD_PLL_REF_CLK_SEL - Override enable for pll_ref_clk_sel */
77755 #define PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_MASK)
77756 /*! @} */
77757 
77758 /*! @name CMN_REG03A -  */
77759 /*! @{ */
77760 
77761 #define PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_MASK    (0x1U)
77762 #define PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_SHIFT   (0U)
77763 /*! PLL_SDM_RSTN - PLL SDM reset */
77764 #define PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_MASK)
77765 
77766 #define PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_MASK (0x2U)
77767 #define PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_SHIFT (1U)
77768 /*! OVRD_PLL_SDM_RSTN - Override enable for pll_sdm_rstn */
77769 #define PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_MASK)
77770 
77771 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_MASK   (0x4U)
77772 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_SHIFT  (2U)
77773 /*! PLL_SDM_EN_G4 - [GEN4] */
77774 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_MASK)
77775 
77776 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_MASK   (0x8U)
77777 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_SHIFT  (3U)
77778 /*! PLL_SDM_EN_G3 - [GEN3] */
77779 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_MASK)
77780 
77781 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_MASK   (0x10U)
77782 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_SHIFT  (4U)
77783 /*! PLL_SDM_EN_G2 - [GEN2] */
77784 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_MASK)
77785 
77786 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_MASK   (0x20U)
77787 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_SHIFT  (5U)
77788 /*! PLL_SDM_EN_G1 - [GEN1] PLL SDM enable */
77789 #define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_MASK)
77790 /*! @} */
77791 
77792 /*! @name CMN_REG03B -  */
77793 /*! @{ */
77794 
77795 #define PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_MASK    (0x1U)
77796 #define PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_SHIFT   (0U)
77797 /*! PLL_SDC_RSTN - PLL SDM clock generation (SDC) reset */
77798 #define PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_MASK)
77799 
77800 #define PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_MASK (0x2U)
77801 #define PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_SHIFT (1U)
77802 /*! OVRD_PLL_SDC_RSTN - Override enable for pll_sdc_rstn */
77803 #define PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_MASK)
77804 
77805 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_MASK (0x4U)
77806 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_SHIFT (2U)
77807 /*! PLL_SDC_FRACTIONAL_EN_G4 - [GEN4] */
77808 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_MASK)
77809 
77810 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_MASK (0x8U)
77811 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_SHIFT (3U)
77812 /*! PLL_SDC_FRACTIONAL_EN_G3 - [GEN3] */
77813 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_MASK)
77814 
77815 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_MASK (0x10U)
77816 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_SHIFT (4U)
77817 /*! PLL_SDC_FRACTIONAL_EN_G2 - [GEN2] */
77818 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_MASK)
77819 
77820 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_MASK (0x20U)
77821 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_SHIFT (5U)
77822 /*! PLL_SDC_FRACTIONAL_EN_G1 - [GEN1] Fractional clock divide in SDM clock generation */
77823 #define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_MASK)
77824 /*! @} */
77825 
77826 /*! @name CMN_REG03C -  */
77827 /*! @{ */
77828 
77829 #define PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_MASK (0xFFU)
77830 #define PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_SHIFT (0U)
77831 /*! PLL_SDM_DENOMINATOR_G1 - [GEN1] Denominator of SDM (Max. 255) */
77832 #define PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_MASK)
77833 /*! @} */
77834 
77835 /*! @name CMN_REG03D -  */
77836 /*! @{ */
77837 
77838 #define PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_MASK (0xFFU)
77839 #define PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_SHIFT (0U)
77840 /*! PLL_SDM_DENOMINATOR_G2 - [GEN2] */
77841 #define PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_MASK)
77842 /*! @} */
77843 
77844 /*! @name CMN_REG03E -  */
77845 /*! @{ */
77846 
77847 #define PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_MASK (0xFFU)
77848 #define PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_SHIFT (0U)
77849 /*! PLL_SDM_DENOMINATOR_G3 - [GEN3] */
77850 #define PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_MASK)
77851 /*! @} */
77852 
77853 /*! @name CMN_REG03F -  */
77854 /*! @{ */
77855 
77856 #define PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_MASK (0xFFU)
77857 #define PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_SHIFT (0U)
77858 /*! PLL_SDM_DENOMINATOR_G4 - [GEN4] */
77859 #define PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_MASK)
77860 /*! @} */
77861 
77862 /*! @name CMN_REG040 -  */
77863 /*! @{ */
77864 
77865 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_MASK (0x1U)
77866 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_SHIFT (0U)
77867 /*! PLL_SDM_NUMERATOR_SIGN_G4 - [GEN4] */
77868 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_MASK)
77869 
77870 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_MASK (0x2U)
77871 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_SHIFT (1U)
77872 /*! PLL_SDM_NUMERATOR_SIGN_G3 - [GEN3] */
77873 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_MASK)
77874 
77875 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_MASK (0x4U)
77876 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_SHIFT (2U)
77877 /*! PLL_SDM_NUMERATOR_SIGN_G2 - [GEN2] */
77878 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_MASK)
77879 
77880 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_MASK (0x8U)
77881 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_SHIFT (3U)
77882 /*! PLL_SDM_NUMERATOR_SIGN_G1 - [GEN1] Sign of SDM numerator */
77883 #define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_MASK)
77884 /*! @} */
77885 
77886 /*! @name CMN_REG041 -  */
77887 /*! @{ */
77888 
77889 #define PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_MASK (0xFFU)
77890 #define PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_SHIFT (0U)
77891 /*! PLL_SDM_NUMERATOR_G1 - [GEN1] Numerator of SDM with i_pll_sdm_k_sign (-255~255) */
77892 #define PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_MASK)
77893 /*! @} */
77894 
77895 /*! @name CMN_REG042 -  */
77896 /*! @{ */
77897 
77898 #define PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_MASK (0xFFU)
77899 #define PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_SHIFT (0U)
77900 /*! PLL_SDM_NUMERATOR_G2 - [GEN2] */
77901 #define PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_MASK)
77902 /*! @} */
77903 
77904 /*! @name CMN_REG043 -  */
77905 /*! @{ */
77906 
77907 #define PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_MASK (0xFFU)
77908 #define PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_SHIFT (0U)
77909 /*! PLL_SDM_NUMERATOR_G3 - [GEN3] */
77910 #define PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_MASK)
77911 /*! @} */
77912 
77913 /*! @name CMN_REG044 -  */
77914 /*! @{ */
77915 
77916 #define PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_MASK (0xFFU)
77917 #define PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_SHIFT (0U)
77918 /*! PLL_SDM_NUMERATOR_G4 - [GEN4] */
77919 #define PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_MASK)
77920 /*! @} */
77921 
77922 /*! @name CMN_REG045 -  */
77923 /*! @{ */
77924 
77925 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_MASK (0x1U)
77926 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_SHIFT (0U)
77927 /*! PLL_SDM_PH_NUM_SEL_G4 - [GEN4] */
77928 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_MASK)
77929 
77930 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_MASK (0x2U)
77931 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_SHIFT (1U)
77932 /*! PLL_SDM_PH_NUM_SEL_G3 - [GEN3] */
77933 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_MASK)
77934 
77935 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_MASK (0x4U)
77936 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_SHIFT (2U)
77937 /*! PLL_SDM_PH_NUM_SEL_G2 - [GEN2] */
77938 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_MASK)
77939 
77940 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_MASK (0x8U)
77941 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_SHIFT (3U)
77942 /*! PLL_SDM_PH_NUM_SEL_G1 - [GEN1] PLL PI input clock phase number */
77943 #define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_MASK)
77944 /*! @} */
77945 
77946 /*! @name CMN_REG046 -  */
77947 /*! @{ */
77948 
77949 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_MASK (0x3U)
77950 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_SHIFT (0U)
77951 /*! PLL_SDM_PI_STEP_G4 - [GEN4] */
77952 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_MASK)
77953 
77954 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_MASK (0xCU)
77955 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_SHIFT (2U)
77956 /*! PLL_SDM_PI_STEP_G3 - [GEN3] */
77957 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_MASK)
77958 
77959 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_MASK (0x30U)
77960 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_SHIFT (4U)
77961 /*! PLL_SDM_PI_STEP_G2 - [GEN2] */
77962 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_MASK)
77963 
77964 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_MASK (0xC0U)
77965 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_SHIFT (6U)
77966 /*! PLL_SDM_PI_STEP_G1 - [GEN1] PLL phase interpolstor step */
77967 #define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_MASK)
77968 /*! @} */
77969 
77970 /*! @name CMN_REG047 -  */
77971 /*! @{ */
77972 
77973 #define PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_MASK    (0x7U)
77974 #define PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_SHIFT   (0U)
77975 /*! PLL_SDC_N_G2 - [GEN2] */
77976 #define PCIE_PHY_CMN_REG047_PLL_SDC_N_G2(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_SHIFT)) & PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_MASK)
77977 
77978 #define PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_MASK    (0x38U)
77979 #define PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_SHIFT   (3U)
77980 /*! PLL_SDC_N_G1 - [GEN1] PLL SDC divide-ratio selection */
77981 #define PCIE_PHY_CMN_REG047_PLL_SDC_N_G1(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_SHIFT)) & PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_MASK)
77982 /*! @} */
77983 
77984 /*! @name CMN_REG048 -  */
77985 /*! @{ */
77986 
77987 #define PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_MASK    (0x7U)
77988 #define PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_SHIFT   (0U)
77989 /*! PLL_SDC_N_G4 - [GEN4] */
77990 #define PCIE_PHY_CMN_REG048_PLL_SDC_N_G4(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_SHIFT)) & PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_MASK)
77991 
77992 #define PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_MASK    (0x38U)
77993 #define PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_SHIFT   (3U)
77994 /*! PLL_SDC_N_G3 - [GEN3] */
77995 #define PCIE_PHY_CMN_REG048_PLL_SDC_N_G3(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_SHIFT)) & PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_MASK)
77996 /*! @} */
77997 
77998 /*! @name CMN_REG049 -  */
77999 /*! @{ */
78000 
78001 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_MASK   (0x1U)
78002 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_SHIFT  (0U)
78003 /*! PLL_SDC_N2_G4 - [GEN4] */
78004 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_MASK)
78005 
78006 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_MASK   (0x2U)
78007 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_SHIFT  (1U)
78008 /*! PLL_SDC_N2_G3 - [GEN3] */
78009 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_MASK)
78010 
78011 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_MASK   (0x4U)
78012 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_SHIFT  (2U)
78013 /*! PLL_SDC_N2_G2 - [GEN2] */
78014 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_MASK)
78015 
78016 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_MASK   (0x8U)
78017 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_SHIFT  (3U)
78018 /*! PLL_SDC_N2_G1 - [GEN1] PLL SDC divide-ratio selection */
78019 #define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_MASK)
78020 /*! @} */
78021 
78022 /*! @name CMN_REG04A -  */
78023 /*! @{ */
78024 
78025 #define PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_MASK (0x3FU)
78026 #define PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_SHIFT (0U)
78027 /*! PLL_SDC_NUMERATOR_G1 - [GEN1] Numerator of SDC (Max 65) */
78028 #define PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_MASK)
78029 /*! @} */
78030 
78031 /*! @name CMN_REG04B -  */
78032 /*! @{ */
78033 
78034 #define PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_MASK (0x3FU)
78035 #define PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_SHIFT (0U)
78036 /*! PLL_SDC_NUMERATOR_G2 - [GEN2] */
78037 #define PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_MASK)
78038 /*! @} */
78039 
78040 /*! @name CMN_REG04C -  */
78041 /*! @{ */
78042 
78043 #define PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_MASK (0x3FU)
78044 #define PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_SHIFT (0U)
78045 /*! PLL_SDC_NUMERATOR_G3 - [GEN3] */
78046 #define PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_MASK)
78047 /*! @} */
78048 
78049 /*! @name CMN_REG04D -  */
78050 /*! @{ */
78051 
78052 #define PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_MASK (0x3FU)
78053 #define PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_SHIFT (0U)
78054 /*! PLL_SDC_NUMERATOR_G4 - [GEN4] */
78055 #define PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_MASK)
78056 /*! @} */
78057 
78058 /*! @name CMN_REG04E -  */
78059 /*! @{ */
78060 
78061 #define PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_MASK (0x3FU)
78062 #define PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_SHIFT (0U)
78063 /*! PLL_SDC_DENOMINATOR_G1 - [GEN1] Denominator of SDC (Max 65) */
78064 #define PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_MASK)
78065 /*! @} */
78066 
78067 /*! @name CMN_REG04F -  */
78068 /*! @{ */
78069 
78070 #define PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_MASK (0x3FU)
78071 #define PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_SHIFT (0U)
78072 /*! PLL_SDC_DENOMINATOR_G2 - [GEN2] */
78073 #define PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_MASK)
78074 /*! @} */
78075 
78076 /*! @name CMN_REG050 -  */
78077 /*! @{ */
78078 
78079 #define PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_MASK (0x3FU)
78080 #define PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_SHIFT (0U)
78081 /*! PLL_SDC_DENOMINATOR_G3 - [GEN3] */
78082 #define PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_MASK)
78083 /*! @} */
78084 
78085 /*! @name CMN_REG051 -  */
78086 /*! @{ */
78087 
78088 #define PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_MASK (0x1U)
78089 #define PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_SHIFT (0U)
78090 /*! ANA_PLL_SDC_MC_VALUE_SEL - PLL SDC value force */
78091 #define PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_SHIFT)) & PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_MASK)
78092 
78093 #define PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_MASK (0x7EU)
78094 #define PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_SHIFT (1U)
78095 /*! PLL_SDC_DENOMINATOR_G4 - [GEN4] */
78096 #define PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_MASK)
78097 /*! @} */
78098 
78099 /*! @name CMN_REG052 -  */
78100 /*! @{ */
78101 
78102 #define PCIE_PHY_CMN_REG052_PLL_SSC_EN_MASK      (0x1U)
78103 #define PCIE_PHY_CMN_REG052_PLL_SSC_EN_SHIFT     (0U)
78104 /*! PLL_SSC_EN - PLL SSC enable */
78105 #define PCIE_PHY_CMN_REG052_PLL_SSC_EN(x)        (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG052_PLL_SSC_EN_SHIFT)) & PCIE_PHY_CMN_REG052_PLL_SSC_EN_MASK)
78106 
78107 #define PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_MASK (0x2U)
78108 #define PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_SHIFT (1U)
78109 /*! OVRD_PLL_SSC_EN - Override enable for pll_ssc_en */
78110 #define PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_SHIFT)) & PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_MASK)
78111 /*! @} */
78112 
78113 /*! @name CMN_REG053 -  */
78114 /*! @{ */
78115 
78116 #define PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_MASK (0x3FU)
78117 #define PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_SHIFT (0U)
78118 /*! PLL_SSC_FM_DEVIATION_G1 - [GEN1] PLL SSC modulation deviation */
78119 #define PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_SHIFT)) & PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_MASK)
78120 /*! @} */
78121 
78122 /*! @name CMN_REG054 -  */
78123 /*! @{ */
78124 
78125 #define PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_MASK (0x3FU)
78126 #define PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_SHIFT (0U)
78127 /*! PLL_SSC_FM_DEVIATION_G2 - [GEN2] */
78128 #define PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_SHIFT)) & PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_MASK)
78129 /*! @} */
78130 
78131 /*! @name CMN_REG055 -  */
78132 /*! @{ */
78133 
78134 #define PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_MASK (0x3FU)
78135 #define PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_SHIFT (0U)
78136 /*! PLL_SSC_FM_DEVIATION_G3 - [GEN3] */
78137 #define PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_SHIFT)) & PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_MASK)
78138 /*! @} */
78139 
78140 /*! @name CMN_REG056 -  */
78141 /*! @{ */
78142 
78143 #define PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_MASK (0x3FU)
78144 #define PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_SHIFT (0U)
78145 /*! PLL_SSC_FM_DEVIATION_G4 - [GEN4] */
78146 #define PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_SHIFT)) & PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_MASK)
78147 /*! @} */
78148 
78149 /*! @name CMN_REG057 -  */
78150 /*! @{ */
78151 
78152 #define PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_MASK (0x1FU)
78153 #define PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_SHIFT (0U)
78154 /*! PLL_SSC_FM_FREQ_G1 - [GEN1] PLL SSC modulation frequency */
78155 #define PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_SHIFT)) & PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_MASK)
78156 /*! @} */
78157 
78158 /*! @name CMN_REG058 -  */
78159 /*! @{ */
78160 
78161 #define PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_MASK (0x1FU)
78162 #define PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_SHIFT (0U)
78163 /*! PLL_SSC_FM_FREQ_G2 - [GEN2] */
78164 #define PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_SHIFT)) & PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_MASK)
78165 /*! @} */
78166 
78167 /*! @name CMN_REG059 -  */
78168 /*! @{ */
78169 
78170 #define PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_MASK (0x1FU)
78171 #define PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_SHIFT (0U)
78172 /*! PLL_SSC_FM_FREQ_G3 - [GEN3] */
78173 #define PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_SHIFT)) & PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_MASK)
78174 /*! @} */
78175 
78176 /*! @name CMN_REG05A -  */
78177 /*! @{ */
78178 
78179 #define PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_MASK (0x1FU)
78180 #define PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_SHIFT (0U)
78181 /*! PLL_SSC_FM_FREQ_G4 - [GEN4] */
78182 #define PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_SHIFT)) & PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_MASK)
78183 /*! @} */
78184 
78185 /*! @name CMN_REG05B -  */
78186 /*! @{ */
78187 
78188 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_MASK (0x3U)
78189 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_SHIFT (0U)
78190 /*! PLL_SSC_PROFILE_OPT_G4 - [GEN4] */
78191 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_MASK)
78192 
78193 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_MASK (0xCU)
78194 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_SHIFT (2U)
78195 /*! PLL_SSC_PROFILE_OPT_G3 - [GEN3] */
78196 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_MASK)
78197 
78198 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_MASK (0x30U)
78199 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_SHIFT (4U)
78200 /*! PLL_SSC_PROFILE_OPT_G2 - [GEN2] */
78201 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_MASK)
78202 
78203 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_MASK (0xC0U)
78204 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_SHIFT (6U)
78205 /*! PLL_SSC_PROFILE_OPT_G1 - [GEN1] PLL SSC modulation profile shape control */
78206 #define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_MASK)
78207 /*! @} */
78208 
78209 /*! @name CMN_REG05C -  */
78210 /*! @{ */
78211 
78212 #define PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_MASK (0x1U)
78213 #define PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_SHIFT (0U)
78214 /*! PLL_CD_TX_SER_RSTN - TX_SER resetn */
78215 #define PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_SHIFT)) & PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_MASK)
78216 
78217 #define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_MASK (0x2U)
78218 #define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_SHIFT (1U)
78219 /*! OVRD_PLL_CD_TX_SER_RSTN - Override enable for pll_cd_tx_ser_rstn */
78220 #define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_SHIFT)) & PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_MASK)
78221 
78222 #define PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_MASK   (0x4U)
78223 #define PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_SHIFT  (2U)
78224 /*! PLL_CD_CLK_EN - CD enable */
78225 #define PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_MASK)
78226 
78227 #define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_MASK (0x8U)
78228 #define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_SHIFT (3U)
78229 /*! OVRD_PLL_CD_CLK_EN - Override enable for pll_cd_clk_en */
78230 #define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_MASK)
78231 
78232 #define PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_MASK (0xF0U)
78233 #define PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_SHIFT (4U)
78234 /*! ANA_PLL_SSC_CLK_DIV_SEL - PLL SSC clock divide ratio */
78235 #define PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_SHIFT)) & PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_MASK)
78236 /*! @} */
78237 
78238 /*! @name CMN_REG05D -  */
78239 /*! @{ */
78240 
78241 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_MASK (0x1U)
78242 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_SHIFT (0U)
78243 /*! ANA_PLL_CD_HSCLK_EAST_EN - CD driver pmos strength control */
78244 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_SHIFT)) & PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_MASK)
78245 
78246 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_MASK (0x2U)
78247 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_SHIFT (1U)
78248 /*! ANA_PLL_CD_HSCLK_WEST_EN - CD driver nmos strength control */
78249 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_SHIFT)) & PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_MASK)
78250 
78251 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_MASK (0x4U)
78252 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_SHIFT (2U)
78253 /*! ANA_PLL_CD_HSCLK_INV - CD output clock polarity inversion */
78254 #define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_SHIFT)) & PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_MASK)
78255 
78256 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_MASK (0x8U)
78257 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_SHIFT (3U)
78258 /*! PLL_CD_TX_SER_RATE_SEL_G4 - [GEN4] */
78259 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_MASK)
78260 
78261 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_MASK (0x10U)
78262 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_SHIFT (4U)
78263 /*! PLL_CD_TX_SER_RATE_SEL_G3 - [GEN3] */
78264 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_MASK)
78265 
78266 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_MASK (0x20U)
78267 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_SHIFT (5U)
78268 /*! PLL_CD_TX_SER_RATE_SEL_G2 - [GEN2] */
78269 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_MASK)
78270 
78271 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_MASK (0x40U)
78272 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_SHIFT (6U)
78273 /*! PLL_CD_TX_SER_RATE_SEL_G1 - [GEN1] TX serializer data rate selection for Gen4 (Need to be controlled with i_tx_en_40bit) */
78274 #define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_MASK)
78275 /*! @} */
78276 
78277 /*! @name CMN_REG05E -  */
78278 /*! @{ */
78279 
78280 #define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_MASK (0x3U)
78281 #define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_SHIFT (0U)
78282 /*! ANA_PLL_MISC_CLK_SEL - PLL low-frequency clock output source selection */
78283 #define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_MASK)
78284 
78285 #define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_MASK (0x4U)
78286 #define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_SHIFT (2U)
78287 /*! ANA_PLL_MISC_CLK_SYNC_EN - PLL miscellaneous clock synchronization enable */
78288 #define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_SHIFT)) & PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_MASK)
78289 
78290 #define PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_MASK (0x8U)
78291 #define PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_SHIFT (3U)
78292 /*! PLL_BEACON_LFPS_OUT_EN - TX beacon clock enable */
78293 #define PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_MASK)
78294 
78295 #define PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_MASK (0x10U)
78296 #define PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_SHIFT (4U)
78297 /*! OVRD_PLL_BEACON_LFPS_OUT_EN - Override enable for pll_beacon_lfps_out_en */
78298 #define PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_MASK)
78299 /*! @} */
78300 
78301 /*! @name CMN_REG05F -  */
78302 /*! @{ */
78303 
78304 #define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_MASK (0xFU)
78305 #define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_SHIFT (0U)
78306 /*! PLL_MISC_CLK_DIV_G2 - [GEN2] */
78307 #define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_SHIFT)) & PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_MASK)
78308 
78309 #define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_MASK (0xF0U)
78310 #define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_SHIFT (4U)
78311 /*! PLL_MISC_CLK_DIV_G1 - [GEN1] PLL miscellaneous clock divider ratio */
78312 #define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_SHIFT)) & PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_MASK)
78313 /*! @} */
78314 
78315 /*! @name CMN_REG060 -  */
78316 /*! @{ */
78317 
78318 #define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_MASK (0xFU)
78319 #define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_SHIFT (0U)
78320 /*! PLL_MISC_CLK_DIV_G4 - [GEN4] */
78321 #define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_SHIFT)) & PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_MASK)
78322 
78323 #define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_MASK (0xF0U)
78324 #define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_SHIFT (4U)
78325 /*! PLL_MISC_CLK_DIV_G3 - [GEN3] */
78326 #define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_SHIFT)) & PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_MASK)
78327 /*! @} */
78328 
78329 /*! @name CMN_REG061 -  */
78330 /*! @{ */
78331 
78332 #define PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_MASK (0x1U)
78333 #define PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_SHIFT (0U)
78334 /*! ANA_PLL_CLK_OUT_TO_EXT_IO_EN - PLL low-frequency clock output to external I/O enable */
78335 #define PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_SHIFT)) & PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_MASK)
78336 
78337 #define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_MASK (0x2U)
78338 #define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_SHIFT (1U)
78339 /*! PLL_MISC_OSC_RSTN - PLL miscellaneous clock oscillator reset */
78340 #define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_MASK)
78341 
78342 #define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_MASK (0x4U)
78343 #define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_SHIFT (2U)
78344 /*! OVRD_PLL_MISC_OSC_RSTN - Override enable for pll_misc_osc_rstn */
78345 #define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_MASK)
78346 
78347 #define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_MASK (0x78U)
78348 #define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_SHIFT (3U)
78349 /*! PLL_MISC_OSC_FREQ_SEL - PLL miscellaneous clock frequency selection */
78350 #define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_SHIFT)) & PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_MASK)
78351 
78352 #define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_MASK (0x80U)
78353 #define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_SHIFT (7U)
78354 /*! OVRD_PLL_MISC_OSC_FREQ_SEL - Override enable for pll_misc_osc_freq_sel */
78355 #define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_SHIFT)) & PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_MASK)
78356 /*! @} */
78357 
78358 /*! @name CMN_REG062 -  */
78359 /*! @{ */
78360 
78361 #define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_MASK (0x3U)
78362 #define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_SHIFT (0U)
78363 /*! ANA_PLL_REF_CLK_MON_SEL - PLL reference clock selection for monitor */
78364 #define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_SHIFT)) & PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_MASK)
78365 
78366 #define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_MASK (0x4U)
78367 #define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_SHIFT (2U)
78368 /*! ANA_PLL_REF_CLK_MON_EN - PLL reference clock monitor enable */
78369 #define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_SHIFT)) & PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_MASK)
78370 
78371 #define PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_MASK (0x8U)
78372 #define PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_SHIFT (3U)
78373 /*! ANA_PLL_CLK_OUT_TO_EXT_IO_SEL - PLL low-frequency clock output to external I/O source selection */
78374 #define PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_SHIFT)) & PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_MASK)
78375 /*! @} */
78376 
78377 /*! @name CMN_REG063 -  */
78378 /*! @{ */
78379 
78380 #define PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_MASK (0x3FU)
78381 #define PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_SHIFT (0U)
78382 /*! ANA_PLL_RESERVED - PLL Reserved pins */
78383 #define PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_SHIFT)) & PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_MASK)
78384 
78385 #define PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_MASK (0xC0U)
78386 #define PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_SHIFT (6U)
78387 /*! AUX_PLL_REFCLK_SEL - 0X: AUX_IN (PLL clock) */
78388 #define PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_MASK)
78389 /*! @} */
78390 
78391 /*! @name CMN_REG064 -  */
78392 /*! @{ */
78393 
78394 #define PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_MASK (0x7U)
78395 #define PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_SHIFT (0U)
78396 /*! ANA_AUX_TX_TERM - TX termination resistor control. Default code : 010, 50.7Ω */
78397 #define PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_MASK)
78398 
78399 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_MASK (0x8U)
78400 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_SHIFT (3U)
78401 /*! ANA_AUX_RX_TERM_GND_EN - External reference clock I/O termination to ground */
78402 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_MASK)
78403 
78404 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_MASK (0x10U)
78405 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_SHIFT (4U)
78406 /*! ANA_AUX_RX_CAP_BYPASS - External reference clock I/O AC-coupling capacitor bypass enable */
78407 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_MASK)
78408 
78409 #define PCIE_PHY_CMN_REG064_AUX_EN_MASK          (0x20U)
78410 #define PCIE_PHY_CMN_REG064_AUX_EN_SHIFT         (5U)
78411 /*! AUX_EN - AUX Enable */
78412 #define PCIE_PHY_CMN_REG064_AUX_EN(x)            (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_AUX_EN_SHIFT)) & PCIE_PHY_CMN_REG064_AUX_EN_MASK)
78413 
78414 #define PCIE_PHY_CMN_REG064_OVRD_AUX_EN_MASK     (0x40U)
78415 #define PCIE_PHY_CMN_REG064_OVRD_AUX_EN_SHIFT    (6U)
78416 /*! OVRD_AUX_EN - Override enable for aux_en */
78417 #define PCIE_PHY_CMN_REG064_OVRD_AUX_EN(x)       (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_OVRD_AUX_EN_SHIFT)) & PCIE_PHY_CMN_REG064_OVRD_AUX_EN_MASK)
78418 
78419 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_MASK (0x80U)
78420 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_SHIFT (7U)
78421 /*! ANA_AUX_RX_TX_SEL - Select mode (TX or RX) */
78422 #define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_MASK)
78423 /*! @} */
78424 
78425 /*! @name CMN_REG065 -  */
78426 /*! @{ */
78427 
78428 #define PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_MASK (0xFU)
78429 #define PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_SHIFT (0U)
78430 /*! ANA_AUX_TX_LVL_CTRL - TX Amplitude resistor control. Default code : 101, 375mVpp */
78431 #define PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_SHIFT)) & PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_MASK)
78432 
78433 #define PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_MASK (0xF0U)
78434 #define PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_SHIFT (4U)
78435 /*! ANA_AUX_RX_TERM - RX termination resistor control. Default code : 1001, 99.6Ω */
78436 #define PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_SHIFT)) & PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_MASK)
78437 /*! @} */
78438 
78439 /*! @name CMN_REG066 -  */
78440 /*! @{ */
78441 
78442 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_MASK (0x7U)
78443 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_SHIFT (0U)
78444 /*! ANA_AUX_RX_HYS_CTRL - Hysteresis for RX noise blocking control. */
78445 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_MASK)
78446 
78447 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_MASK (0x18U)
78448 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_SHIFT (3U)
78449 /*! ANA_AUX_RX_VCM_FINE_CTRL - VCM of RX control. 171mV ~ 680mV at typical condition. */
78450 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_MASK)
78451 
78452 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_MASK (0x60U)
78453 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_SHIFT (5U)
78454 /*! ANA_AUX_RX_VCM_COARSE_CTRL - VCM of RX control. 171mV ~ 680mV at typical condition. */
78455 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_MASK)
78456 
78457 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_MASK (0x80U)
78458 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_SHIFT (7U)
78459 /*! ANA_AUX_RX_VCM_SEL - Input common mode voltage control. */
78460 #define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_MASK)
78461 /*! @} */
78462 
78463 /*! @name CMN_REG067 -  */
78464 /*! @{ */
78465 
78466 #define PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_MASK (0xFFU)
78467 #define PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_SHIFT (0U)
78468 /*! ANA_AUX_RESERVED - Reserved port */
78469 #define PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_SHIFT)) & PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_MASK)
78470 /*! @} */
78471 
78472 /*! @name CMN_REG068 -  */
78473 /*! @{ */
78474 
78475 #define PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_MASK   (0x1U)
78476 #define PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_SHIFT  (0U)
78477 /*! PLL_LOCK_DONE - PLL lock done overide value */
78478 #define PCIE_PHY_CMN_REG068_PLL_LOCK_DONE(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_MASK)
78479 
78480 #define PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_MASK (0x2U)
78481 #define PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_SHIFT (1U)
78482 /*! OVRD_PLL_LOCK_DONE - Override enable for pll_lock_done */
78483 #define PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_MASK)
78484 
78485 #define PCIE_PHY_CMN_REG068_PLL_AFC_DONE_MASK    (0x4U)
78486 #define PCIE_PHY_CMN_REG068_PLL_AFC_DONE_SHIFT   (2U)
78487 /*! PLL_AFC_DONE - PLL AFC done overide value */
78488 #define PCIE_PHY_CMN_REG068_PLL_AFC_DONE(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_PLL_AFC_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_PLL_AFC_DONE_MASK)
78489 
78490 #define PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_MASK (0x8U)
78491 #define PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_SHIFT (3U)
78492 /*! OVRD_PLL_AFC_DONE - Override enable for pll_afc_done */
78493 #define PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_MASK)
78494 
78495 #define PCIE_PHY_CMN_REG068_BGR_SET_DONE_MASK    (0x10U)
78496 #define PCIE_PHY_CMN_REG068_BGR_SET_DONE_SHIFT   (4U)
78497 /*! BGR_SET_DONE - BGR set done */
78498 #define PCIE_PHY_CMN_REG068_BGR_SET_DONE(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_BGR_SET_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_BGR_SET_DONE_MASK)
78499 
78500 #define PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_MASK (0x20U)
78501 #define PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_SHIFT (5U)
78502 /*! OVRD_BGR_SET_DONE - Override enable for bgr_set_done */
78503 #define PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_MASK)
78504 /*! @} */
78505 
78506 /*! @name CMN_REG069 -  */
78507 /*! @{ */
78508 
78509 #define PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_MASK (0x1U)
78510 #define PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_SHIFT (0U)
78511 #define PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_SHIFT)) & PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_MASK)
78512 
78513 #define PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_MASK (0x2U)
78514 #define PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_SHIFT (1U)
78515 /*! OVRD_PLL_FINE_TUNE_START - Override enable for pll_fine_tune_start */
78516 #define PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_SHIFT)) & PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_MASK)
78517 
78518 #define PCIE_PHY_CMN_REG069_HIGH_SPEED_MASK      (0x4U)
78519 #define PCIE_PHY_CMN_REG069_HIGH_SPEED_SHIFT     (2U)
78520 /*! HIGH_SPEED - HIGH SPEED indicator by operating LC VCO */
78521 #define PCIE_PHY_CMN_REG069_HIGH_SPEED(x)        (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_HIGH_SPEED_SHIFT)) & PCIE_PHY_CMN_REG069_HIGH_SPEED_MASK)
78522 
78523 #define PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_MASK (0x8U)
78524 #define PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_SHIFT (3U)
78525 /*! OVRD_HIGH_SPEED - Override enable for high_speed */
78526 #define PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_SHIFT)) & PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_MASK)
78527 
78528 #define PCIE_PHY_CMN_REG069_PHY_MODE_MASK        (0x30U)
78529 #define PCIE_PHY_CMN_REG069_PHY_MODE_SHIFT       (4U)
78530 #define PCIE_PHY_CMN_REG069_PHY_MODE(x)          (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_PHY_MODE_SHIFT)) & PCIE_PHY_CMN_REG069_PHY_MODE_MASK)
78531 
78532 #define PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_MASK   (0x40U)
78533 #define PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_SHIFT  (6U)
78534 /*! OVRD_PHY_MODE - Override enable for phy_mode */
78535 #define PCIE_PHY_CMN_REG069_OVRD_PHY_MODE(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_SHIFT)) & PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_MASK)
78536 /*! @} */
78537 
78538 /*! @name CMN_REG06A -  */
78539 /*! @{ */
78540 
78541 #define PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_MASK (0xFU)
78542 #define PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_SHIFT (0U)
78543 /*! TG_BGR_FAST_PULSE_TIME - BGR LPF bypass duration after BGR_EN = 1 */
78544 #define PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_SHIFT)) & PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_MASK)
78545 
78546 #define PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_MASK   (0x10U)
78547 #define PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_SHIFT  (4U)
78548 #define PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_SHIFT)) & PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_MASK)
78549 
78550 #define PCIE_PHY_CMN_REG06A_CMN_RATE_MASK        (0x60U)
78551 #define PCIE_PHY_CMN_REG06A_CMN_RATE_SHIFT       (5U)
78552 /*! CMN_RATE - TX Data Rate manual setting */
78553 #define PCIE_PHY_CMN_REG06A_CMN_RATE(x)          (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_CMN_RATE_SHIFT)) & PCIE_PHY_CMN_REG06A_CMN_RATE_MASK)
78554 
78555 #define PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_MASK   (0x80U)
78556 #define PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_SHIFT  (7U)
78557 /*! OVRD_CMN_RATE - Override enable for cmn_rate */
78558 #define PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_SHIFT)) & PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_MASK)
78559 /*! @} */
78560 
78561 /*! @name CMN_REG06B -  */
78562 /*! @{ */
78563 
78564 #define PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_MASK (0x7U)
78565 #define PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_SHIFT (0U)
78566 /*! TG_PLL_SDM_RSTN_DELAY_TIME - PLL SDM start delay after PLL integer-mode lock(PLL lock) */
78567 #define PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_MASK)
78568 
78569 #define PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_MASK (0x38U)
78570 #define PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_SHIFT (3U)
78571 #define PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_MASK)
78572 /*! @} */
78573 
78574 /*! @name CMN_REG06C -  */
78575 /*! @{ */
78576 
78577 #define PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_MASK (0x7U)
78578 #define PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_SHIFT (0U)
78579 /*! TG_PLL_FINE_LOCK_DELAY_TIME - PLL Fine LOCK DLY CODE */
78580 #define PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_MASK)
78581 
78582 #define PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_MASK (0x38U)
78583 #define PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_SHIFT (3U)
78584 /*! TG_PLL_AFC_RSTN_DELAY_TIME - PLL AFC reset delay time after bypassing BGR LPF */
78585 #define PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_MASK)
78586 /*! @} */
78587 
78588 /*! @name CMN_REG06D -  */
78589 /*! @{ */
78590 
78591 #define PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_MASK (0x7U)
78592 #define PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_SHIFT (0U)
78593 /*! TG_PLL_SDC_RSTN_DELAY_TIME - PLL SDM RESET STABLE DLY CODE */
78594 #define PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_MASK)
78595 
78596 #define PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_MASK (0x38U)
78597 #define PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_SHIFT (3U)
78598 /*! TG_PLL_SSC_EN_DELAY_TIME - PLL SSC start delay time after */
78599 #define PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_MASK)
78600 /*! @} */
78601 
78602 /*! @name CMN_REG06E -  */
78603 /*! @{ */
78604 
78605 #define PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_MASK (0x7U)
78606 #define PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_SHIFT (0U)
78607 #define PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_MASK)
78608 /*! @} */
78609 
78610 /*! @name CMN_REG06F -  */
78611 /*! @{ */
78612 
78613 #define PCIE_PHY_CMN_REG06F_DTB_SEL_MASK         (0xFFU)
78614 #define PCIE_PHY_CMN_REG06F_DTB_SEL_SHIFT        (0U)
78615 /*! DTB_SEL - Digital Test Bus (DTB) selection */
78616 #define PCIE_PHY_CMN_REG06F_DTB_SEL(x)           (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06F_DTB_SEL_SHIFT)) & PCIE_PHY_CMN_REG06F_DTB_SEL_MASK)
78617 /*! @} */
78618 
78619 /*! @name CMN_REG070 -  */
78620 /*! @{ */
78621 
78622 #define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_MASK (0xFU)
78623 #define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_SHIFT (0U)
78624 /*! ANA_PLL_AFC_RING_CODE_MON - LC AFC code MSB monitor */
78625 #define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_SHIFT)) & PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_MASK)
78626 
78627 #define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_MASK (0x30U)
78628 #define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_SHIFT (4U)
78629 /*! ANA_PLL_AFC_LC_CODE_MON - LC AFC code MSB monitor */
78630 #define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_SHIFT)) & PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_MASK)
78631 /*! @} */
78632 
78633 /*! @name CMN_REG071 -  */
78634 /*! @{ */
78635 
78636 #define PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_MASK (0xFU)
78637 #define PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_SHIFT (0U)
78638 /*! ANA_PLL_AGMC_CODE_MON - LC VCO GM code monitor */
78639 #define PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_SHIFT)) & PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_MASK)
78640 /*! @} */
78641 
78642 /*! @name CMN_REG072 -  */
78643 /*! @{ */
78644 
78645 #define PCIE_PHY_CMN_REG072_MON_CMN_STATE_MASK   (0x1FU)
78646 #define PCIE_PHY_CMN_REG072_MON_CMN_STATE_SHIFT  (0U)
78647 /*! MON_CMN_STATE - CMN state monitor */
78648 #define PCIE_PHY_CMN_REG072_MON_CMN_STATE(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG072_MON_CMN_STATE_SHIFT)) & PCIE_PHY_CMN_REG072_MON_CMN_STATE_MASK)
78649 /*! @} */
78650 
78651 /*! @name CMN_REG073 -  */
78652 /*! @{ */
78653 
78654 #define PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_MASK (0x7FU)
78655 #define PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_SHIFT (0U)
78656 /*! MON_CMN_TIME__14_8 - CMN timer monitor */
78657 #define PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_SHIFT)) & PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_MASK)
78658 /*! @} */
78659 
78660 /*! @name CMN_REG074 -  */
78661 /*! @{ */
78662 
78663 #define PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_MASK (0xFFU)
78664 #define PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_SHIFT (0U)
78665 /*! MON_CMN_TIME__7_0 - CMN timer monitor */
78666 #define PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_SHIFT)) & PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_MASK)
78667 /*! @} */
78668 
78669 /*! @name CMN_REG075 -  */
78670 /*! @{ */
78671 
78672 #define PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_MASK (0x1U)
78673 #define PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_SHIFT (0U)
78674 /*! ANA_PLL_AFC_DONE - PLL AFC Done */
78675 #define PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_SHIFT)) & PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_MASK)
78676 
78677 #define PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_MASK (0x2U)
78678 #define PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_SHIFT (1U)
78679 /*! ANA_PLL_LOCK_DONE - PLL Lock Done */
78680 #define PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_SHIFT)) & PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_MASK)
78681 /*! @} */
78682 
78683 /*! @name CMN_REG076 -  */
78684 /*! @{ */
78685 
78686 #define PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_MASK (0x3U)
78687 #define PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_SHIFT (0U)
78688 /*! LANE0_RESET_MUX_SEL - 0x0 : Lane0 reset signal from Port 0 */
78689 #define PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_MASK)
78690 
78691 #define PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_MASK (0xCU)
78692 #define PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_SHIFT (2U)
78693 /*! LANE1_RESET_MUX_SEL - 0x0 : Lane1 reset signal from Port 0 */
78694 #define PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_MASK)
78695 
78696 #define PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_MASK (0x30U)
78697 #define PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_SHIFT (4U)
78698 /*! LANE2_RESET_MUX_SEL - 0x0 : Lane2 reset signal from Port 0 */
78699 #define PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_MASK)
78700 
78701 #define PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_MASK (0xC0U)
78702 #define PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_SHIFT (6U)
78703 /*! LANE3_RESET_MUX_SEL - 0x0 : Lane3 reset signal from Port 0 */
78704 #define PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_MASK)
78705 /*! @} */
78706 
78707 /*! @name CMN_REG077 -  */
78708 /*! @{ */
78709 
78710 #define PCIE_PHY_CMN_REG077_LANE0_SW_RESET_MASK  (0x1U)
78711 #define PCIE_PHY_CMN_REG077_LANE0_SW_RESET_SHIFT (0U)
78712 /*! LANE0_SW_RESET - 0x0 : Lane0 reset */
78713 #define PCIE_PHY_CMN_REG077_LANE0_SW_RESET(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE0_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE0_SW_RESET_MASK)
78714 
78715 #define PCIE_PHY_CMN_REG077_LANE1_SW_RESET_MASK  (0x2U)
78716 #define PCIE_PHY_CMN_REG077_LANE1_SW_RESET_SHIFT (1U)
78717 /*! LANE1_SW_RESET - 0x0 : Lane1 reset */
78718 #define PCIE_PHY_CMN_REG077_LANE1_SW_RESET(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE1_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE1_SW_RESET_MASK)
78719 
78720 #define PCIE_PHY_CMN_REG077_LANE2_SW_RESET_MASK  (0x4U)
78721 #define PCIE_PHY_CMN_REG077_LANE2_SW_RESET_SHIFT (2U)
78722 /*! LANE2_SW_RESET - 0x0 : Lane2 reset */
78723 #define PCIE_PHY_CMN_REG077_LANE2_SW_RESET(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE2_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE2_SW_RESET_MASK)
78724 
78725 #define PCIE_PHY_CMN_REG077_LANE3_SW_RESET_MASK  (0x8U)
78726 #define PCIE_PHY_CMN_REG077_LANE3_SW_RESET_SHIFT (3U)
78727 /*! LANE3_SW_RESET - 0x0 : Lane3 reset */
78728 #define PCIE_PHY_CMN_REG077_LANE3_SW_RESET(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE3_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE3_SW_RESET_MASK)
78729 
78730 #define PCIE_PHY_CMN_REG077_CMN_SW_RESET_MASK    (0x10U)
78731 #define PCIE_PHY_CMN_REG077_CMN_SW_RESET_SHIFT   (4U)
78732 /*! CMN_SW_RESET - 0x0 : cmn reset */
78733 #define PCIE_PHY_CMN_REG077_CMN_SW_RESET(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_CMN_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_CMN_SW_RESET_MASK)
78734 /*! @} */
78735 
78736 /*! @name CMN_REG078 -  */
78737 /*! @{ */
78738 
78739 #define PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_MASK (0x3U)
78740 #define PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_SHIFT (0U)
78741 #define PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_MASK)
78742 
78743 #define PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_MASK (0xCU)
78744 #define PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_SHIFT (2U)
78745 #define PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_MASK)
78746 
78747 #define PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_MASK (0x30U)
78748 #define PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_SHIFT (4U)
78749 #define PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_MASK)
78750 
78751 #define PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_MASK (0xC0U)
78752 #define PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_SHIFT (6U)
78753 /*! LANE3_TX_DATA_CLK_MUX_SEL - 0x0 : tx data clock from lane0 */
78754 #define PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_MASK)
78755 /*! @} */
78756 
78757 /*! @name CMN_REG079 -  */
78758 /*! @{ */
78759 
78760 #define PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_MASK (0x1U)
78761 #define PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_SHIFT (0U)
78762 #define PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_SHIFT)) & PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_MASK)
78763 /*! @} */
78764 
78765 /*! @name CMN_REG080 -  */
78766 /*! @{ */
78767 
78768 #define PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_MASK (0xFFU)
78769 #define PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_SHIFT (0U)
78770 #define PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_SHIFT)) & PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_MASK)
78771 /*! @} */
78772 
78773 /*! @name CMN_REG081 -  */
78774 /*! @{ */
78775 
78776 #define PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_MASK (0xFFU)
78777 #define PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_SHIFT (0U)
78778 #define PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_SHIFT)) & PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_MASK)
78779 /*! @} */
78780 
78781 /*! @name CMN_REG082 -  */
78782 /*! @{ */
78783 
78784 #define PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_MASK (0x3U)
78785 #define PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_SHIFT (0U)
78786 #define PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_SHIFT)) & PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_MASK)
78787 /*! @} */
78788 
78789 /*! @name TRSV_REG000 -  */
78790 /*! @{ */
78791 
78792 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_MASK (0x1U)
78793 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_SHIFT (0U)
78794 /*! LN0_TX_DRV_EI_EN - TX driver electrical-idle state enable */
78795 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_MASK)
78796 
78797 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_MASK (0x2U)
78798 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_SHIFT (1U)
78799 /*! LN0_OVRD_TX_DRV_EI_EN - Override enable for tx_drv_ei_en */
78800 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_MASK)
78801 
78802 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_MASK (0x4U)
78803 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_SHIFT (2U)
78804 /*! LN0_TX_DRV_CM_KEEPER_EN - TX driver common-mode keep enable */
78805 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_MASK)
78806 
78807 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_MASK (0x8U)
78808 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_SHIFT (3U)
78809 /*! LN0_OVRD_TX_DRV_CM_KEEPER_EN - Override enable for tx_drv_cm_keeper_en */
78810 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_MASK)
78811 
78812 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_MASK (0x10U)
78813 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT (4U)
78814 /*! LN0_TX_DRV_BEACON_LFPS_OUT_EN - TX beacon or LFPS enable */
78815 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_MASK)
78816 
78817 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_MASK (0x20U)
78818 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT (5U)
78819 /*! LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN - Override enable for tx_drv_beacon_lfps_out_en */
78820 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_MASK)
78821 
78822 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_MASK  (0x40U)
78823 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_SHIFT (6U)
78824 /*! LN0_TX_DRV_EN - TX driver enable */
78825 #define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_MASK)
78826 
78827 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_MASK (0x80U)
78828 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_SHIFT (7U)
78829 /*! LN0_OVRD_TX_DRV_EN - Override enable for tx_drv_en */
78830 #define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_MASK)
78831 /*! @} */
78832 
78833 /*! @name TRSV_REG001 -  */
78834 /*! @{ */
78835 
78836 #define PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_MASK (0x1FU)
78837 #define PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_SHIFT (0U)
78838 /*! LN0_TX_DRV_LVL_CTRL_G1 - [GEN1] TX driver main-tap level */
78839 #define PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_MASK)
78840 
78841 #define PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_MASK (0x20U)
78842 #define PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_SHIFT (5U)
78843 /*! LN0_OVRD_TX_DRV_LVL_CTRL - Override enable for tx_drv_lvl_ctrl_g1 */
78844 #define PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_MASK)
78845 /*! @} */
78846 
78847 /*! @name TRSV_REG002 -  */
78848 /*! @{ */
78849 
78850 #define PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_MASK (0x1FU)
78851 #define PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_SHIFT (0U)
78852 /*! LN0_TX_DRV_LVL_CTRL_G2 - [GEN2] */
78853 #define PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_MASK)
78854 /*! @} */
78855 
78856 /*! @name TRSV_REG003 -  */
78857 /*! @{ */
78858 
78859 #define PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_MASK (0x1FU)
78860 #define PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_SHIFT (0U)
78861 /*! LN0_TX_DRV_LVL_CTRL_G3 - [GEN3] */
78862 #define PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_MASK)
78863 /*! @} */
78864 
78865 /*! @name TRSV_REG004 -  */
78866 /*! @{ */
78867 
78868 #define PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_MASK (0x1FU)
78869 #define PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_SHIFT (0U)
78870 /*! LN0_TX_DRV_LVL_CTRL_G4 - [GEN4] */
78871 #define PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_MASK)
78872 /*! @} */
78873 
78874 /*! @name TRSV_REG005 -  */
78875 /*! @{ */
78876 
78877 #define PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_MASK (0x1FU)
78878 #define PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_SHIFT (0U)
78879 /*! LN0_TX_DRV_POST_LVL_CTRL_G1 - [GEN1] TX driver de-emphasis level */
78880 #define PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_MASK)
78881 
78882 #define PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_MASK (0x20U)
78883 #define PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_SHIFT (5U)
78884 /*! LN0_OVRD_TX_DRV_POST_LVL_CTRL - Override enable for tx_drv_post_lvl_ctrl_g1 */
78885 #define PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_MASK)
78886 /*! @} */
78887 
78888 /*! @name TRSV_REG006 -  */
78889 /*! @{ */
78890 
78891 #define PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_MASK (0x1FU)
78892 #define PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_SHIFT (0U)
78893 /*! LN0_TX_DRV_POST_LVL_CTRL_G2 - [GEN2] */
78894 #define PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_MASK)
78895 /*! @} */
78896 
78897 /*! @name TRSV_REG007 -  */
78898 /*! @{ */
78899 
78900 #define PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_MASK (0x1FU)
78901 #define PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_SHIFT (0U)
78902 /*! LN0_TX_DRV_POST_LVL_CTRL_G3 - [GEN3] */
78903 #define PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_MASK)
78904 /*! @} */
78905 
78906 /*! @name TRSV_REG008 -  */
78907 /*! @{ */
78908 
78909 #define PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_MASK (0x1FU)
78910 #define PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_SHIFT (0U)
78911 /*! LN0_TX_DRV_POST_LVL_CTRL_G4 - [GEN4] */
78912 #define PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_MASK)
78913 /*! @} */
78914 
78915 /*! @name TRSV_REG009 -  */
78916 /*! @{ */
78917 
78918 #define PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_MASK (0xFU)
78919 #define PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_SHIFT (0U)
78920 /*! LN0_TX_DRV_PRE_LVL_CTRL_G1 - [GEN1] TX driver pre-shoot level */
78921 #define PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_MASK)
78922 
78923 #define PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_MASK (0x10U)
78924 #define PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_SHIFT (4U)
78925 /*! LN0_OVRD_TX_DRV_PRE_LVL_CTRL - Override enable for tx_drv_pre_lvl_ctrl_g1 */
78926 #define PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_MASK)
78927 /*! @} */
78928 
78929 /*! @name TRSV_REG00A -  */
78930 /*! @{ */
78931 
78932 #define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_MASK (0xFU)
78933 #define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_SHIFT (0U)
78934 /*! LN0_TX_DRV_PRE_LVL_CTRL_G3 - [GEN3] */
78935 #define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_MASK)
78936 
78937 #define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_MASK (0xF0U)
78938 #define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_SHIFT (4U)
78939 /*! LN0_TX_DRV_PRE_LVL_CTRL_G2 - [GEN2] */
78940 #define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_MASK)
78941 /*! @} */
78942 
78943 /*! @name TRSV_REG00B -  */
78944 /*! @{ */
78945 
78946 #define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_MASK (0x1U)
78947 #define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_SHIFT (0U)
78948 /*! LN0_TX_DRV_IDRV_EN - TX current-driver enable */
78949 #define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_MASK)
78950 
78951 #define PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_MASK (0x2U)
78952 #define PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_SHIFT (1U)
78953 /*! LN0_OVRD_TX_DRV_IDRV_EN - Override enable for tx_drv_idrv_en */
78954 #define PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_MASK)
78955 
78956 #define PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MASK (0x4U)
78957 #define PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SHIFT (2U)
78958 /*! LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN - TX LFPS/BEACON synchronization enable */
78959 #define PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MASK)
78960 
78961 #define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_MASK (0x78U)
78962 #define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_SHIFT (3U)
78963 /*! LN0_TX_DRV_PRE_LVL_CTRL_G4 - [GEN4] */
78964 #define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_MASK)
78965 /*! @} */
78966 
78967 /*! @name TRSV_REG00C -  */
78968 /*! @{ */
78969 
78970 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_MASK (0x1U)
78971 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_SHIFT (0U)
78972 /*! LN0_ANA_TX_DRV_ACCDRV_EN - Enable of Cap. Peaking block. */
78973 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_MASK)
78974 
78975 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_MASK (0x2U)
78976 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_SHIFT (1U)
78977 /*! LN0_ANA_TX_DRV_IDRV_VREF_SEL - TX current driver reference selection */
78978 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_MASK)
78979 
78980 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_MASK (0x1CU)
78981 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_SHIFT (2U)
78982 /*! LN0_ANA_TX_DRV_IDRV_IUP_CTRL - TX current driver pmos current control */
78983 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_MASK)
78984 
78985 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_MASK (0xE0U)
78986 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_SHIFT (5U)
78987 /*! LN0_ANA_TX_DRV_IDRV_IDN_CTRL - TX current driver pmos current control */
78988 #define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_MASK)
78989 /*! @} */
78990 
78991 /*! @name TRSV_REG00D -  */
78992 /*! @{ */
78993 
78994 #define PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_MASK (0x1FU)
78995 #define PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_SHIFT (0U)
78996 #define PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_SHIFT)) & PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_MASK)
78997 /*! @} */
78998 
78999 /*! @name TRSV_REG00E -  */
79000 /*! @{ */
79001 
79002 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_MASK (0x3U)
79003 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_SHIFT (0U)
79004 /*! LN0_TX_DRV_EI_EN_DELAY_SEL_G4 - [GEN4] */
79005 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_MASK)
79006 
79007 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_MASK (0xCU)
79008 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_SHIFT (2U)
79009 /*! LN0_TX_DRV_EI_EN_DELAY_SEL_G3 - [GEN3] */
79010 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_MASK)
79011 
79012 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_MASK (0x30U)
79013 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_SHIFT (4U)
79014 /*! LN0_TX_DRV_EI_EN_DELAY_SEL_G2 - [GEN2] */
79015 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_MASK)
79016 
79017 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_MASK (0xC0U)
79018 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_SHIFT (6U)
79019 /*! LN0_TX_DRV_EI_EN_DELAY_SEL_G1 - [GEN1] TX EI enable latency control */
79020 #define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_MASK)
79021 /*! @} */
79022 
79023 /*! @name TRSV_REG00F -  */
79024 /*! @{ */
79025 
79026 #define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_MASK (0x1U)
79027 #define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_SHIFT (0U)
79028 /*! LN0_ANA_TX_DRV_PLL_REF_MON_EN - Enable of PLL reference clock monitor through Tx driver */
79029 #define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_MASK)
79030 
79031 #define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_MASK (0x2U)
79032 #define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_SHIFT (1U)
79033 /*! LN0_ANA_TX_DRV_HSCLK_MON_EN - Enable of high-speed clock monitor through Tx driver */
79034 #define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_MASK)
79035 /*! @} */
79036 
79037 /*! @name TRSV_REG010 -  */
79038 /*! @{ */
79039 
79040 #define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_MASK (0xFU)
79041 #define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_SHIFT (0U)
79042 /*! LN0_TX_JEQ_CAP_CTRL_G2 - [GEN2] */
79043 #define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_MASK)
79044 
79045 #define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_MASK (0xF0U)
79046 #define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_SHIFT (4U)
79047 /*! LN0_TX_JEQ_CAP_CTRL_G1 - [GEN1] TX jitter EQ loding capacitance control in thermomether */
79048 #define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_MASK)
79049 /*! @} */
79050 
79051 /*! @name TRSV_REG011 -  */
79052 /*! @{ */
79053 
79054 #define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_MASK (0xFU)
79055 #define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_SHIFT (0U)
79056 /*! LN0_TX_JEQ_CAP_CTRL_G4 - [GEN4] */
79057 #define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_MASK)
79058 
79059 #define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_MASK (0xF0U)
79060 #define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_SHIFT (4U)
79061 /*! LN0_TX_JEQ_CAP_CTRL_G3 - [GEN3] */
79062 #define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_MASK)
79063 /*! @} */
79064 
79065 /*! @name TRSV_REG012 -  */
79066 /*! @{ */
79067 
79068 #define PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_MASK (0x1U)
79069 #define PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_SHIFT (0U)
79070 /*! LN0_ANA_TX_JEQ_EN - TX jitter EQ enable */
79071 #define PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_SHIFT)) & PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_MASK)
79072 /*! @} */
79073 
79074 /*! @name TRSV_REG013 -  */
79075 /*! @{ */
79076 
79077 #define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_MASK (0xFU)
79078 #define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_SHIFT (0U)
79079 /*! LN0_TX_JEQ_EVEN_CTRL_G2 - [GEN2] */
79080 #define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_MASK)
79081 
79082 #define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_MASK (0xF0U)
79083 #define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_SHIFT (4U)
79084 /*! LN0_TX_JEQ_EVEN_CTRL_G1 - [GEN1] TX jitter EQ driver (even) strength control */
79085 #define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_MASK)
79086 /*! @} */
79087 
79088 /*! @name TRSV_REG014 -  */
79089 /*! @{ */
79090 
79091 #define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_MASK (0xFU)
79092 #define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_SHIFT (0U)
79093 /*! LN0_TX_JEQ_EVEN_CTRL_G4 - [GEN4] */
79094 #define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_MASK)
79095 
79096 #define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_MASK (0xF0U)
79097 #define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_SHIFT (4U)
79098 /*! LN0_TX_JEQ_EVEN_CTRL_G3 - [GEN3] */
79099 #define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_MASK)
79100 /*! @} */
79101 
79102 /*! @name TRSV_REG015 -  */
79103 /*! @{ */
79104 
79105 #define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_MASK (0xFU)
79106 #define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_SHIFT (0U)
79107 /*! LN0_TX_JEQ_ODD_CTRL_G2 - [GEN2] */
79108 #define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_MASK)
79109 
79110 #define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_MASK (0xF0U)
79111 #define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_SHIFT (4U)
79112 /*! LN0_TX_JEQ_ODD_CTRL_G1 - [GEN1] TX jitter EQ driver (odd) strength control */
79113 #define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_MASK)
79114 /*! @} */
79115 
79116 /*! @name TRSV_REG016 -  */
79117 /*! @{ */
79118 
79119 #define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_MASK (0xFU)
79120 #define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_SHIFT (0U)
79121 /*! LN0_TX_JEQ_ODD_CTRL_G4 - [GEN4] */
79122 #define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_MASK)
79123 
79124 #define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_MASK (0xF0U)
79125 #define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_SHIFT (4U)
79126 /*! LN0_TX_JEQ_ODD_CTRL_G3 - [GEN3] */
79127 #define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_MASK)
79128 /*! @} */
79129 
79130 /*! @name TRSV_REG017 -  */
79131 /*! @{ */
79132 
79133 #define PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_MASK (0x3U)
79134 #define PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_SHIFT (0U)
79135 /*! LN0_ANA_TX_RCAL_IRMRES_CTRL - TX RCAL rmres bias current control */
79136 #define PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_MASK)
79137 
79138 #define PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_MASK (0x4U)
79139 #define PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_SHIFT (2U)
79140 /*! LN0_TX_RCAL_EN - TX RCAL enable */
79141 #define PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_MASK)
79142 
79143 #define PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_MASK (0x8U)
79144 #define PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_SHIFT (3U)
79145 /*! LN0_OVRD_TX_RCAL_EN - Override enable for tx_rcal_en */
79146 #define PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_MASK)
79147 /*! @} */
79148 
79149 /*! @name TRSV_REG018 -  */
79150 /*! @{ */
79151 
79152 #define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_MASK  (0x1U)
79153 #define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_SHIFT (0U)
79154 /*! LN0_TX_RXD_EN - TX receiver detector enable. Drives a transition on the serial data and measures
79155  *    the charge time of the line in order to determine whether a receiver is connected.
79156  */
79157 #define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_MASK)
79158 
79159 #define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_MASK (0x2U)
79160 #define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_SHIFT (1U)
79161 /*! LN0_OVRD_TX_RXD_EN - Override enable for tx_rxd_en */
79162 #define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_MASK)
79163 
79164 #define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_MASK (0x4U)
79165 #define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_SHIFT (2U)
79166 /*! LN0_TX_RXD_COMP_EN - TX receiver detector comparator enable */
79167 #define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_MASK)
79168 
79169 #define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_MASK (0x8U)
79170 #define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_SHIFT (3U)
79171 /*! LN0_OVRD_TX_RXD_COMP_EN - Override enable for tx_rxd_comp_en */
79172 #define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_MASK)
79173 
79174 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_MASK (0x10U)
79175 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_SHIFT (4U)
79176 /*! LN0_TX_RTERM_42P5_EN_G4 - [GEN4] */
79177 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_MASK)
79178 
79179 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_MASK (0x20U)
79180 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_SHIFT (5U)
79181 /*! LN0_TX_RTERM_42P5_EN_G3 - [GEN3] */
79182 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_MASK)
79183 
79184 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_MASK (0x40U)
79185 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_SHIFT (6U)
79186 /*! LN0_TX_RTERM_42P5_EN_G2 - [GEN2] */
79187 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_MASK)
79188 
79189 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_MASK (0x80U)
79190 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_SHIFT (7U)
79191 /*! LN0_TX_RTERM_42P5_EN_G1 - [GEN1] */
79192 #define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_MASK)
79193 /*! @} */
79194 
79195 /*! @name TRSV_REG019 -  */
79196 /*! @{ */
79197 
79198 #define PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_MASK (0x1U)
79199 #define PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_SHIFT (0U)
79200 /*! LN0_ANA_TX_RXD_COMP_I_CTRL - TX receiver detector comparator bias control */
79201 #define PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_MASK)
79202 /*! @} */
79203 
79204 /*! @name TRSV_REG01A -  */
79205 /*! @{ */
79206 
79207 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_MASK (0x1U)
79208 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_SHIFT (0U)
79209 /*! LN0_TX_SER_DATA_RSTN - TX serializer data-path resetn */
79210 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_MASK)
79211 
79212 #define PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_MASK (0x2U)
79213 #define PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_SHIFT (1U)
79214 /*! LN0_OVRD_TX_SER_DATA_RSTN - Override enable for tx_ser_data_rstn */
79215 #define PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_MASK)
79216 
79217 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_MASK (0x4U)
79218 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_SHIFT (2U)
79219 /*! LN0_TX_SER_40BIT_EN_G4 - [GEN4] */
79220 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_MASK)
79221 
79222 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_MASK (0x8U)
79223 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_SHIFT (3U)
79224 /*! LN0_TX_SER_40BIT_EN_G3 - [GEN3] */
79225 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_MASK)
79226 
79227 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_MASK (0x10U)
79228 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_SHIFT (4U)
79229 /*! LN0_TX_SER_40BIT_EN_G2 - [GEN2] */
79230 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_MASK)
79231 
79232 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_MASK (0x20U)
79233 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_SHIFT (5U)
79234 /*! LN0_TX_SER_40BIT_EN_G1 - [GEN1] TX serializer data width selection */
79235 #define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_MASK)
79236 /*! @} */
79237 
79238 /*! @name TRSV_REG01B -  */
79239 /*! @{ */
79240 
79241 #define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_MASK (0x1U)
79242 #define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_SHIFT (0U)
79243 /*! LN0_ANA_TX_SER_TXCLK_INV - TX byte clock polarity inversion */
79244 #define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_MASK)
79245 
79246 #define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_MASK (0x2U)
79247 #define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_SHIFT (1U)
79248 /*! LN0_ANA_TX_CDR_CLK_MON_EN - TX serializer clock selection */
79249 #define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_MASK)
79250 
79251 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_MASK (0x4U)
79252 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_SHIFT (2U)
79253 /*! LN0_TX_SER_CLK_RSTN - TX serializer clock-path resetn */
79254 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_MASK)
79255 
79256 #define PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_MASK (0x8U)
79257 #define PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_SHIFT (3U)
79258 /*! LN0_OVRD_TX_SER_CLK_RSTN - Override enable for tx_ser_clk_rstn */
79259 #define PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_MASK)
79260 
79261 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_MASK (0x10U)
79262 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_SHIFT (4U)
79263 /*! LN0_TX_SER_RATE_SEL_G4 - [GEN4] */
79264 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_MASK)
79265 
79266 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_MASK (0x20U)
79267 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_SHIFT (5U)
79268 /*! LN0_TX_SER_RATE_SEL_G3 - [GEN3] */
79269 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_MASK)
79270 
79271 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_MASK (0x40U)
79272 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_SHIFT (6U)
79273 /*! LN0_TX_SER_RATE_SEL_G2 - [GEN2] */
79274 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_MASK)
79275 
79276 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_MASK (0x80U)
79277 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_SHIFT (7U)
79278 /*! LN0_TX_SER_RATE_SEL_G1 - [GEN1] TX serializer data rate selection for Gen4 (Need to be controlled with i_tx_en_40bit) */
79279 #define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_MASK)
79280 /*! @} */
79281 
79282 /*! @name TRSV_REG01C -  */
79283 /*! @{ */
79284 
79285 #define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_MASK (0x1U)
79286 #define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_SHIFT (0U)
79287 /*! LN0_ANA_TX_ATB_EN - TX ATB enable */
79288 #define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_MASK)
79289 
79290 #define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_MASK (0x3EU)
79291 #define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_SHIFT (1U)
79292 /*! LN0_ANA_TX_ATB_SEL - 0000: Serailizer VDD, 0001: Pre Driver VDD, 0010: Driver VDD, 0011: Driver VDDH, */
79293 #define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_SHIFT)) & PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_MASK)
79294 /*! @} */
79295 
79296 /*! @name TRSV_REG01D -  */
79297 /*! @{ */
79298 
79299 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_MASK (0x1U)
79300 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_SHIFT (0U)
79301 /*! LN0_ANA_TX_SRLB_EN - Serial retimed loopback enable */
79302 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_MASK)
79303 
79304 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_MASK (0x2U)
79305 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_SHIFT (1U)
79306 /*! LN0_ANA_TX_LLB_EN - Line loopback enalble */
79307 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_MASK)
79308 
79309 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_MASK (0x4U)
79310 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_SHIFT (2U)
79311 /*! LN0_ANA_TX_SLB_EN - Serial loopback enable */
79312 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_MASK)
79313 
79314 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_MASK (0x38U)
79315 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_SHIFT (3U)
79316 /*! LN0_ANA_TX_BIAS_RMRES_CTRL - RX RMRES bias current control */
79317 #define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_MASK)
79318 /*! @} */
79319 
79320 /*! @name TRSV_REG01E -  */
79321 /*! @{ */
79322 
79323 #define PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_MASK (0xFU)
79324 #define PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_SHIFT (0U)
79325 /*! LN0_ANA_TX_RESERVED - Reserved port */
79326 #define PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_MASK)
79327 
79328 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_MASK (0x10U)
79329 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_SHIFT (4U)
79330 /*! LN0_TX_EQ_2UI_DELAY_EN_G4 - [GEN4] */
79331 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_MASK)
79332 
79333 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_MASK (0x20U)
79334 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_SHIFT (5U)
79335 /*! LN0_TX_EQ_2UI_DELAY_EN_G3 - [GEN3] */
79336 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_MASK)
79337 
79338 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_MASK (0x40U)
79339 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_SHIFT (6U)
79340 /*! LN0_TX_EQ_2UI_DELAY_EN_G2 - [GEN2] */
79341 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_MASK)
79342 
79343 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_MASK (0x80U)
79344 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_SHIFT (7U)
79345 /*! LN0_TX_EQ_2UI_DELAY_EN_G1 - [GEN1] TX FIR filter delay control when bit-duplication */
79346 #define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_MASK)
79347 /*! @} */
79348 
79349 /*! @name TRSV_REG01F -  */
79350 /*! @{ */
79351 
79352 #define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_MASK (0x3U)
79353 #define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_SHIFT (0U)
79354 /*! LN0_RX_CDR_MODE_CTRL - RX CDR mode select */
79355 #define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_MASK)
79356 
79357 #define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_MASK (0x4U)
79358 #define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_SHIFT (2U)
79359 /*! LN0_OVRD_RX_CDR_MODE_CTRL - Override enable for rx_cdr_mode_ctrl */
79360 #define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_MASK)
79361 
79362 #define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_MASK  (0x8U)
79363 #define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_SHIFT (3U)
79364 /*! LN0_RX_CDR_EN - RX CDR enable */
79365 #define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_MASK)
79366 
79367 #define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_MASK (0x10U)
79368 #define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_SHIFT (4U)
79369 /*! LN0_OVRD_RX_CDR_EN - Override enable for rx_cdr_en */
79370 #define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_MASK)
79371 /*! @} */
79372 
79373 /*! @name TRSV_REG020 -  */
79374 /*! @{ */
79375 
79376 #define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_MASK (0xFU)
79377 #define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_SHIFT (0U)
79378 /*! LN0_RX_CDR_REFDIV_SEL_PLL_G2 - [GEN2] [PLL mode] */
79379 #define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_SHIFT)) & PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_MASK)
79380 
79381 #define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_MASK (0xF0U)
79382 #define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_SHIFT (4U)
79383 /*! LN0_RX_CDR_REFDIV_SEL_PLL_G1 - [GEN1] [PLL mode] Decision of CDR ref. clock dividing-rate */
79384 #define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_SHIFT)) & PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_MASK)
79385 /*! @} */
79386 
79387 /*! @name TRSV_REG021 -  */
79388 /*! @{ */
79389 
79390 #define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_MASK (0xFU)
79391 #define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_SHIFT (0U)
79392 /*! LN0_RX_CDR_REFDIV_SEL_PLL_G4 - [GEN4] [PLL mode] */
79393 #define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_SHIFT)) & PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_MASK)
79394 
79395 #define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_MASK (0xF0U)
79396 #define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_SHIFT (4U)
79397 /*! LN0_RX_CDR_REFDIV_SEL_PLL_G3 - [GEN3] [PLL mode] */
79398 #define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_SHIFT)) & PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_MASK)
79399 /*! @} */
79400 
79401 /*! @name TRSV_REG022 -  */
79402 /*! @{ */
79403 
79404 #define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_MASK (0xFU)
79405 #define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_SHIFT (0U)
79406 /*! LN0_RX_CDR_REFDIV_SEL_DATA_G2 - [GEN2] [Data mode] */
79407 #define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_SHIFT)) & PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_MASK)
79408 
79409 #define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_MASK (0xF0U)
79410 #define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_SHIFT (4U)
79411 /*! LN0_RX_CDR_REFDIV_SEL_DATA_G1 - [GEN1] [Data mode] Decision of CDR ref. divider ratio */
79412 #define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_SHIFT)) & PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_MASK)
79413 /*! @} */
79414 
79415 /*! @name TRSV_REG023 -  */
79416 /*! @{ */
79417 
79418 #define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_MASK (0xFU)
79419 #define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_SHIFT (0U)
79420 /*! LN0_RX_CDR_REFDIV_SEL_DATA_G4 - [GEN4] [Data mode] */
79421 #define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_SHIFT)) & PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_MASK)
79422 
79423 #define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_MASK (0xF0U)
79424 #define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_SHIFT (4U)
79425 /*! LN0_RX_CDR_REFDIV_SEL_DATA_G3 - [GEN3] [Data mode] */
79426 #define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_SHIFT)) & PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_MASK)
79427 /*! @} */
79428 
79429 /*! @name TRSV_REG024 -  */
79430 /*! @{ */
79431 
79432 #define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_MASK (0xFU)
79433 #define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_SHIFT (0U)
79434 /*! LN0_RX_CDR_MDIV_SEL_PLL_G2 - [GEN2] [PLL mode] */
79435 #define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_SHIFT)) & PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_MASK)
79436 
79437 #define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_MASK (0xF0U)
79438 #define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_SHIFT (4U)
79439 /*! LN0_RX_CDR_MDIV_SEL_PLL_G1 - [GEN1] [PLL mode] Decision of CDR main-divider ratio */
79440 #define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_SHIFT)) & PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_MASK)
79441 /*! @} */
79442 
79443 /*! @name TRSV_REG025 -  */
79444 /*! @{ */
79445 
79446 #define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_MASK (0xFU)
79447 #define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_SHIFT (0U)
79448 /*! LN0_RX_CDR_MDIV_SEL_PLL_G4 - [GEN4] [PLL mode] */
79449 #define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_SHIFT)) & PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_MASK)
79450 
79451 #define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_MASK (0xF0U)
79452 #define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_SHIFT (4U)
79453 /*! LN0_RX_CDR_MDIV_SEL_PLL_G3 - [GEN3] [PLL mode] */
79454 #define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_SHIFT)) & PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_MASK)
79455 /*! @} */
79456 
79457 /*! @name TRSV_REG026 -  */
79458 /*! @{ */
79459 
79460 #define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_MASK (0xFU)
79461 #define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_SHIFT (0U)
79462 /*! LN0_RX_CDR_MDIV_SEL_DATA_G2 - [GEN2] [Data mode] */
79463 #define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_SHIFT)) & PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_MASK)
79464 
79465 #define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_MASK (0xF0U)
79466 #define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_SHIFT (4U)
79467 /*! LN0_RX_CDR_MDIV_SEL_DATA_G1 - [GEN1] [Data mode] Decision of CDR main-divider ratio */
79468 #define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_SHIFT)) & PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_MASK)
79469 /*! @} */
79470 
79471 /*! @name TRSV_REG027 -  */
79472 /*! @{ */
79473 
79474 #define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_MASK (0xFU)
79475 #define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_SHIFT (0U)
79476 /*! LN0_RX_CDR_MDIV_SEL_DATA_G4 - [GEN4] [Data mode] */
79477 #define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_SHIFT)) & PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_MASK)
79478 
79479 #define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_MASK (0xF0U)
79480 #define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_SHIFT (4U)
79481 /*! LN0_RX_CDR_MDIV_SEL_DATA_G3 - [GEN3] [Data mode] */
79482 #define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_SHIFT)) & PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_MASK)
79483 /*! @} */
79484 
79485 /*! @name TRSV_REG028 -  */
79486 /*! @{ */
79487 
79488 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_MASK (0x1U)
79489 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_SHIFT (0U)
79490 /*! LN0_ANA_RX_CDR_AFC_VCI_FORCE - RX CDR control voltage force */
79491 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_MASK)
79492 
79493 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_MASK (0x2U)
79494 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_SHIFT (1U)
79495 /*! LN0_ANA_RX_CDR_AFC_TEST_EN - RX CDR test mode enable */
79496 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_MASK)
79497 
79498 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_MASK (0x4U)
79499 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_SHIFT (2U)
79500 /*! LN0_ANA_RX_CDR_AFC_EN - RX CDR AFC enable */
79501 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_MASK)
79502 
79503 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_MASK (0x8U)
79504 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_SHIFT (3U)
79505 /*! LN0_ANA_RX_CDR_DES_RXCLK_INV - RX byte clock polarity inversion */
79506 #define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_MASK)
79507 
79508 #define PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_MASK (0x10U)
79509 #define PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_SHIFT (4U)
79510 /*! LN0_RX_CDR_BW_CTRL - RX CDR bandwidth control */
79511 #define PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_MASK)
79512 
79513 #define PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_MASK (0x20U)
79514 #define PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_SHIFT (5U)
79515 /*! LN0_OVRD_RX_CDR_BW_CTRL - Override enable for rx_cdr_bw_ctrl */
79516 #define PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_MASK)
79517 /*! @} */
79518 
79519 /*! @name TRSV_REG029 -  */
79520 /*! @{ */
79521 
79522 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_MASK (0x1U)
79523 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_SHIFT (0U)
79524 /*! LN0_ANA_RX_CDR_CP_E_EN - RX CDR even charge-pump enable */
79525 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_SHIFT)) & PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_MASK)
79526 
79527 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_MASK (0xEU)
79528 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_SHIFT (1U)
79529 /*! LN0_ANA_RX_CDR_CP_CTRL - RX CDR charge pump current control (Ieven + Iodd) */
79530 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_MASK)
79531 
79532 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_MASK (0x10U)
79533 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_SHIFT (4U)
79534 /*! LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL - RX CDR VCI reference voltage selection */
79535 #define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_SHIFT)) & PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_MASK)
79536 /*! @} */
79537 
79538 /*! @name TRSV_REG02A -  */
79539 /*! @{ */
79540 
79541 #define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_MASK (0x1U)
79542 #define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_SHIFT (0U)
79543 /*! LN0_RX_CDR_VCO_STARTUP - RX CDR VCO startup signal, low to high transition */
79544 #define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_MASK)
79545 
79546 #define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_MASK (0x2U)
79547 #define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_SHIFT (1U)
79548 /*! LN0_OVRD_RX_CDR_VCO_STARTUP - Override enable for rx_cdr_vco_startup */
79549 #define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_MASK)
79550 
79551 #define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_MASK (0x4U)
79552 #define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_SHIFT (2U)
79553 /*! LN0_RX_CDR_FBB_CAL_EN - RX CDR FBB calibration enable */
79554 #define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_MASK)
79555 
79556 #define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_MASK (0x8U)
79557 #define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_SHIFT (3U)
79558 /*! LN0_OVRD_RX_CDR_FBB_CAL_EN - Override enable for rx_cdr_fbb_cal_en */
79559 #define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_MASK)
79560 
79561 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_MASK (0x10U)
79562 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_SHIFT (4U)
79563 /*! LN0_ANA_RX_CDR_CP_VREG_LPF_EN - LPF enable for RX CDR charge pump regualtor */
79564 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_MASK)
79565 
79566 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_MASK (0x20U)
79567 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_SHIFT (5U)
79568 /*! LN0_ANA_RX_CDR_CP_VREG_IN_SEL - RX CDR charge pump regulator reference voltage selection */
79569 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_MASK)
79570 
79571 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_MASK (0x40U)
79572 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_SHIFT (6U)
79573 /*! LN0_ANA_RX_CDR_CP_O_EN - RX CDR odd charge-pump enable */
79574 #define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_MASK)
79575 /*! @} */
79576 
79577 /*! @name TRSV_REG02B -  */
79578 /*! @{ */
79579 
79580 #define PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_MASK (0xFU)
79581 #define PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_SHIFT (0U)
79582 /*! LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL - RX CDR BBVCO dummy cap control to decrease frequency */
79583 #define PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_MASK)
79584 /*! @} */
79585 
79586 /*! @name TRSV_REG02C -  */
79587 /*! @{ */
79588 
79589 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_MASK (0x1U)
79590 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_SHIFT (0U)
79591 /*! LN0_RX_CDR_VCO_FREQ_BOOST_G4 - [GEN4] */
79592 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_MASK)
79593 
79594 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_MASK (0x2U)
79595 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_SHIFT (1U)
79596 /*! LN0_RX_CDR_VCO_FREQ_BOOST_G3 - [GEN3] */
79597 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_MASK)
79598 
79599 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_MASK (0x4U)
79600 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_SHIFT (2U)
79601 /*! LN0_RX_CDR_VCO_FREQ_BOOST_G2 - [GEN2] */
79602 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_MASK)
79603 
79604 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_MASK (0x8U)
79605 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_SHIFT (3U)
79606 /*! LN0_RX_CDR_VCO_FREQ_BOOST_G1 - [GEN1] RX CDR VCO frequency boost enable */
79607 #define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_MASK)
79608 /*! @} */
79609 
79610 /*! @name TRSV_REG02D -  */
79611 /*! @{ */
79612 
79613 #define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_MASK (0x7U)
79614 #define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_SHIFT (0U)
79615 /*! LN0_RX_CDR_VCO_VREG_SEL_G2 - [GEN2] */
79616 #define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_MASK)
79617 
79618 #define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_MASK (0x38U)
79619 #define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_SHIFT (3U)
79620 /*! LN0_RX_CDR_VCO_VREG_SEL_G1 - [GEN1] RX CDR voltage regualtor selection */
79621 #define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_MASK)
79622 /*! @} */
79623 
79624 /*! @name TRSV_REG02E -  */
79625 /*! @{ */
79626 
79627 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_MASK (0x1U)
79628 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_SHIFT (0U)
79629 /*! LN0_RX_CTLE_EN - RX CTLE enable */
79630 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_MASK)
79631 
79632 #define PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_MASK (0x2U)
79633 #define PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_SHIFT (1U)
79634 /*! LN0_OVRD_RX_CTLE_EN - Override enable for rx_ctle_en */
79635 #define PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_MASK)
79636 
79637 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_MASK (0x1CU)
79638 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_SHIFT (2U)
79639 /*! LN0_RX_CDR_VCO_VREG_SEL_G4 - [GEN4] */
79640 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_MASK)
79641 
79642 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_MASK (0xE0U)
79643 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_SHIFT (5U)
79644 /*! LN0_RX_CDR_VCO_VREG_SEL_G3 - [GEN3] */
79645 #define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_MASK)
79646 /*! @} */
79647 
79648 /*! @name TRSV_REG02F -  */
79649 /*! @{ */
79650 
79651 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_MASK (0x1U)
79652 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_SHIFT (0U)
79653 /*! LN0_RX_CTLE_HIGH_BW_EN_G4 - [GEN4] */
79654 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_MASK)
79655 
79656 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_MASK (0x2U)
79657 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_SHIFT (1U)
79658 /*! LN0_RX_CTLE_HIGH_BW_EN_G3 - [GEN3] */
79659 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_MASK)
79660 
79661 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_MASK (0x4U)
79662 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_SHIFT (2U)
79663 /*! LN0_RX_CTLE_HIGH_BW_EN_G2 - [GEN2] */
79664 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_MASK)
79665 
79666 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_MASK (0x8U)
79667 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_SHIFT (3U)
79668 /*! LN0_RX_CTLE_HIGH_BW_EN_G1 - [GEN1] RX CTLE bandwidth enhancement by boosting up current */
79669 #define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_MASK)
79670 /*! @} */
79671 
79672 /*! @name TRSV_REG030 -  */
79673 /*! @{ */
79674 
79675 #define PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_MASK (0x7FU)
79676 #define PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_SHIFT (0U)
79677 /*! LN0_RX_CTLE_ITAIL_CTRL_G1 - [GEN1] RX CTLE main tail current */
79678 #define PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_MASK)
79679 /*! @} */
79680 
79681 /*! @name TRSV_REG031 -  */
79682 /*! @{ */
79683 
79684 #define PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_MASK (0x7FU)
79685 #define PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_SHIFT (0U)
79686 /*! LN0_RX_CTLE_ITAIL_CTRL_G2 - [GEN2] */
79687 #define PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_MASK)
79688 /*! @} */
79689 
79690 /*! @name TRSV_REG032 -  */
79691 /*! @{ */
79692 
79693 #define PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_MASK (0x7FU)
79694 #define PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_SHIFT (0U)
79695 /*! LN0_RX_CTLE_ITAIL_CTRL_G3 - [GEN3] */
79696 #define PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_MASK)
79697 /*! @} */
79698 
79699 /*! @name TRSV_REG033 -  */
79700 /*! @{ */
79701 
79702 #define PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_MASK (0x7FU)
79703 #define PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_SHIFT (0U)
79704 /*! LN0_RX_CTLE_ITAIL_CTRL_G4 - [GEN4] */
79705 #define PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_MASK)
79706 /*! @} */
79707 
79708 /*! @name TRSV_REG034 -  */
79709 /*! @{ */
79710 
79711 #define PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_MASK (0x7FU)
79712 #define PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_SHIFT (0U)
79713 /*! LN0_RX_CTLE_OC_CODE - RX CTLE manual offset code */
79714 #define PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_MASK)
79715 
79716 #define PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_MASK (0x80U)
79717 #define PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_SHIFT (7U)
79718 /*! LN0_OVRD_RX_CTLE_OC_CODE - Override enable for rx_ctle_oc_code */
79719 #define PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_MASK)
79720 /*! @} */
79721 
79722 /*! @name TRSV_REG035 -  */
79723 /*! @{ */
79724 
79725 #define PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_MASK (0x1U)
79726 #define PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_SHIFT (0U)
79727 /*! LN0_RX_CTLE_OC_EN - RX CTLE offset calibration enable */
79728 #define PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_MASK)
79729 
79730 #define PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_MASK (0x2U)
79731 #define PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_SHIFT (1U)
79732 /*! LN0_OVRD_RX_CTLE_OC_EN - Override enable for rx_ctle_oc_en */
79733 #define PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_MASK)
79734 /*! @} */
79735 
79736 /*! @name TRSV_REG036 -  */
79737 /*! @{ */
79738 
79739 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_MASK (0x1U)
79740 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_SHIFT (0U)
79741 /*! LN0_RX_CTLE_OC_VCM_SEL_G4 - [GEN4] */
79742 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_MASK)
79743 
79744 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_MASK (0x2U)
79745 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_SHIFT (1U)
79746 /*! LN0_RX_CTLE_OC_VCM_SEL_G3 - [GEN3] */
79747 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_MASK)
79748 
79749 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_MASK (0x4U)
79750 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_SHIFT (2U)
79751 /*! LN0_RX_CTLE_OC_VCM_SEL_G2 - [GEN2] */
79752 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_MASK)
79753 
79754 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_MASK (0x8U)
79755 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_SHIFT (3U)
79756 /*! LN0_RX_CTLE_OC_VCM_SEL_G1 - [GEN1] RX CTLE input common-mode selection in offset calibration */
79757 #define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_MASK)
79758 /*! @} */
79759 
79760 /*! @name TRSV_REG037 -  */
79761 /*! @{ */
79762 
79763 #define PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_MASK (0x1FU)
79764 #define PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_SHIFT (0U)
79765 /*! LN0_RX_CTLE_RL_CTRL_G1 - [GEN1] RX CTLE load resistance control for Gen1 */
79766 #define PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_MASK)
79767 /*! @} */
79768 
79769 /*! @name TRSV_REG038 -  */
79770 /*! @{ */
79771 
79772 #define PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_MASK (0x1FU)
79773 #define PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_SHIFT (0U)
79774 /*! LN0_RX_CTLE_RL_CTRL_G2 - [GEN2] */
79775 #define PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_MASK)
79776 /*! @} */
79777 
79778 /*! @name TRSV_REG039 -  */
79779 /*! @{ */
79780 
79781 #define PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_MASK (0x1FU)
79782 #define PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_SHIFT (0U)
79783 /*! LN0_RX_CTLE_RL_CTRL_G3 - [GEN3] */
79784 #define PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_MASK)
79785 /*! @} */
79786 
79787 /*! @name TRSV_REG03A -  */
79788 /*! @{ */
79789 
79790 #define PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_MASK (0x1FU)
79791 #define PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_SHIFT (0U)
79792 /*! LN0_RX_CTLE_RL_CTRL_G4 - [GEN4] */
79793 #define PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_MASK)
79794 /*! @} */
79795 
79796 /*! @name TRSV_REG03B -  */
79797 /*! @{ */
79798 
79799 #define PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_MASK (0xFU)
79800 #define PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_SHIFT (0U)
79801 /*! LN0_RX_CTLE_RS1_CTRL_G1 - [GEN1] RX CTLE 1st stage source series resistance control */
79802 #define PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_MASK)
79803 
79804 #define PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_MASK (0x10U)
79805 #define PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_SHIFT (4U)
79806 /*! LN0_OVRD_RX_CTLE_RS1_CTRL - Override enable for rx_ctle_rs1_ctrl_g1 */
79807 #define PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_MASK)
79808 /*! @} */
79809 
79810 /*! @name TRSV_REG03C -  */
79811 /*! @{ */
79812 
79813 #define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_MASK (0xFU)
79814 #define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_SHIFT (0U)
79815 /*! LN0_RX_CTLE_RS1_CTRL_G3 - [GEN3] */
79816 #define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_MASK)
79817 
79818 #define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_MASK (0xF0U)
79819 #define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_SHIFT (4U)
79820 /*! LN0_RX_CTLE_RS1_CTRL_G2 - [GEN2] */
79821 #define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_MASK)
79822 /*! @} */
79823 
79824 /*! @name TRSV_REG03D -  */
79825 /*! @{ */
79826 
79827 #define PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_MASK (0xFU)
79828 #define PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_SHIFT (0U)
79829 /*! LN0_RX_CTLE_RS1_CTRL_G4 - [GEN4] */
79830 #define PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_MASK)
79831 /*! @} */
79832 
79833 /*! @name TRSV_REG03E -  */
79834 /*! @{ */
79835 
79836 #define PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_MASK (0xFU)
79837 #define PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_SHIFT (0U)
79838 /*! LN0_RX_CTLE_RS2_CTRL_G1 - [GEN1] RX CTLE 2nd stage source series resistance control */
79839 #define PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_MASK)
79840 
79841 #define PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_MASK (0x10U)
79842 #define PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_SHIFT (4U)
79843 /*! LN0_OVRD_RX_CTLE_RS2_CTRL - Override enable for rx_ctle_rs2_ctrl_g1 */
79844 #define PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_MASK)
79845 /*! @} */
79846 
79847 /*! @name TRSV_REG03F -  */
79848 /*! @{ */
79849 
79850 #define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_MASK (0xFU)
79851 #define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_SHIFT (0U)
79852 /*! LN0_RX_CTLE_RS2_CTRL_G3 - [GEN3] */
79853 #define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_MASK)
79854 
79855 #define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_MASK (0xF0U)
79856 #define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_SHIFT (4U)
79857 /*! LN0_RX_CTLE_RS2_CTRL_G2 - [GEN2] */
79858 #define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_MASK)
79859 /*! @} */
79860 
79861 /*! @name TRSV_REG040 -  */
79862 /*! @{ */
79863 
79864 #define PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_MASK (0xFU)
79865 #define PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_SHIFT (0U)
79866 /*! LN0_RX_CTLE_RS2_CTRL_G4 - [GEN4] */
79867 #define PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_MASK)
79868 /*! @} */
79869 
79870 /*! @name TRSV_REG041 -  */
79871 /*! @{ */
79872 
79873 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_MASK (0x1U)
79874 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_SHIFT (0U)
79875 /*! LN0_RX_CTLE_CHFB_EN_G4 - [GEN4] */
79876 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_MASK)
79877 
79878 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_MASK (0x2U)
79879 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_SHIFT (1U)
79880 /*! LN0_RX_CTLE_CHFB_EN_G3 - [GEN3] */
79881 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_MASK)
79882 
79883 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_MASK (0x4U)
79884 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_SHIFT (2U)
79885 /*! LN0_RX_CTLE_CHFB_EN_G2 - [GEN2] */
79886 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_MASK)
79887 
79888 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_MASK (0x8U)
79889 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_SHIFT (3U)
79890 /*! LN0_RX_CTLE_CHFB_EN_G1 - [GEN1] RX CTLE Cherry-Hooper feedback amplifier enable */
79891 #define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_MASK)
79892 /*! @} */
79893 
79894 /*! @name TRSV_REG042 -  */
79895 /*! @{ */
79896 
79897 #define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_MASK (0xFU)
79898 #define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_SHIFT (0U)
79899 /*! LN0_RX_CTLE_CS_CTRL_G2 - [GEN2] */
79900 #define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_MASK)
79901 
79902 #define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_MASK (0xF0U)
79903 #define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_SHIFT (4U)
79904 /*! LN0_RX_CTLE_CS_CTRL_G1 - [GEN1] CTLE capacitance control. 4'h0=Gen4,3 4'h3=Gen2 4'h7=Gen1 */
79905 #define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_MASK)
79906 /*! @} */
79907 
79908 /*! @name TRSV_REG043 -  */
79909 /*! @{ */
79910 
79911 #define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_MASK (0xFU)
79912 #define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_SHIFT (0U)
79913 /*! LN0_RX_CTLE_CS_CTRL_G4 - [GEN4] */
79914 #define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_MASK)
79915 
79916 #define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_MASK (0xF0U)
79917 #define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_SHIFT (4U)
79918 /*! LN0_RX_CTLE_CS_CTRL_G3 - [GEN3] */
79919 #define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_MASK)
79920 /*! @} */
79921 
79922 /*! @name TRSV_REG044 -  */
79923 /*! @{ */
79924 
79925 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_MASK (0x3U)
79926 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_SHIFT (0U)
79927 /*! LN0_RX_CTLE_PEAKING_EN_G4 - [GEN4] */
79928 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_MASK)
79929 
79930 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_MASK (0xCU)
79931 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_SHIFT (2U)
79932 /*! LN0_RX_CTLE_PEAKING_EN_G3 - [GEN3] */
79933 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_MASK)
79934 
79935 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_MASK (0x30U)
79936 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_SHIFT (4U)
79937 /*! LN0_RX_CTLE_PEAKING_EN_G2 - [GEN2] */
79938 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_MASK)
79939 
79940 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_MASK (0xC0U)
79941 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_SHIFT (6U)
79942 /*! LN0_RX_CTLE_PEAKING_EN_G1 - [GEN1] RX CTLE stage enable for Gen1 */
79943 #define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_MASK)
79944 /*! @} */
79945 
79946 /*! @name TRSV_REG045 -  */
79947 /*! @{ */
79948 
79949 #define PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_MASK (0x7U)
79950 #define PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_SHIFT (0U)
79951 /*! LN0_ANA_RX_CTLE_IBLEED_CTRL - RX CTLE bleeder current control */
79952 #define PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_MASK)
79953 /*! @} */
79954 
79955 /*! @name TRSV_REG046 -  */
79956 /*! @{ */
79957 
79958 #define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_MASK (0xFU)
79959 #define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_SHIFT (0U)
79960 /*! LN0_RX_CTLE_NEGC_EN_G2 - [GEN2] */
79961 #define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_MASK)
79962 
79963 #define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_MASK (0xF0U)
79964 #define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_SHIFT (4U)
79965 /*! LN0_RX_CTLE_NEGC_EN_G1 - [GEN1] RX CTLE negative-C enable */
79966 #define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_MASK)
79967 /*! @} */
79968 
79969 /*! @name TRSV_REG047 -  */
79970 /*! @{ */
79971 
79972 #define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_MASK (0xFU)
79973 #define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_SHIFT (0U)
79974 /*! LN0_RX_CTLE_NEGC_EN_G4 - [GEN4] */
79975 #define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_MASK)
79976 
79977 #define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_MASK (0xF0U)
79978 #define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_SHIFT (4U)
79979 /*! LN0_RX_CTLE_NEGC_EN_G3 - [GEN3] */
79980 #define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_MASK)
79981 /*! @} */
79982 
79983 /*! @name TRSV_REG048 -  */
79984 /*! @{ */
79985 
79986 #define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_MASK (0xFU)
79987 #define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_SHIFT (0U)
79988 /*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2 - [GEN2] */
79989 #define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_MASK)
79990 
79991 #define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_MASK (0xF0U)
79992 #define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_SHIFT (4U)
79993 /*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1 - [GEN1] RX CTLE negative-C tail current control */
79994 #define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_MASK)
79995 /*! @} */
79996 
79997 /*! @name TRSV_REG049 -  */
79998 /*! @{ */
79999 
80000 #define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_MASK (0xFU)
80001 #define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_SHIFT (0U)
80002 /*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4 - [GEN4] */
80003 #define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_MASK)
80004 
80005 #define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_MASK (0xF0U)
80006 #define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_SHIFT (4U)
80007 /*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3 - [GEN3] */
80008 #define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_MASK)
80009 /*! @} */
80010 
80011 /*! @name TRSV_REG04A -  */
80012 /*! @{ */
80013 
80014 #define PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_MASK (0x3U)
80015 #define PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_SHIFT (0U)
80016 /*! LN0_ANA_RX_CTLE_VCM_SEL - RX AFE (CTLE output) common-mode voltage selection */
80017 #define PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_SHIFT)) & PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_MASK)
80018 /*! @} */
80019 
80020 /*! @name TRSV_REG04B -  */
80021 /*! @{ */
80022 
80023 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_MASK (0x3U)
80024 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_SHIFT (0U)
80025 /*! LN0_RX_CTLE_CHFB_BW_CTRL_G4 - [GEN4] */
80026 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_MASK)
80027 
80028 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_MASK (0xCU)
80029 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_SHIFT (2U)
80030 /*! LN0_RX_CTLE_CHFB_BW_CTRL_G3 - [GEN3] */
80031 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_MASK)
80032 
80033 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_MASK (0x30U)
80034 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_SHIFT (4U)
80035 /*! LN0_RX_CTLE_CHFB_BW_CTRL_G2 - [GEN2] */
80036 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_MASK)
80037 
80038 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_MASK (0xC0U)
80039 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_SHIFT (6U)
80040 /*! LN0_RX_CTLE_CHFB_BW_CTRL_G1 - [GEN1] RX CTLE Cherry-Hooper feedback amplifier bandwidth control */
80041 #define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_MASK)
80042 /*! @} */
80043 
80044 /*! @name TRSV_REG04C -  */
80045 /*! @{ */
80046 
80047 #define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_MASK (0x7U)
80048 #define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_SHIFT (0U)
80049 /*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G2 - [GEN2] */
80050 #define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_MASK)
80051 
80052 #define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_MASK (0x38U)
80053 #define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_SHIFT (3U)
80054 /*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G1 - [GEN1] RX CTLE Cherry-Hooper feedback amplifier gain control */
80055 #define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_MASK)
80056 /*! @} */
80057 
80058 /*! @name TRSV_REG04D -  */
80059 /*! @{ */
80060 
80061 #define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_MASK (0x7U)
80062 #define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_SHIFT (0U)
80063 /*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G4 - [GEN4] */
80064 #define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_MASK)
80065 
80066 #define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_MASK (0x38U)
80067 #define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_SHIFT (3U)
80068 /*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G3 - [GEN3] */
80069 #define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_MASK)
80070 /*! @} */
80071 
80072 /*! @name TRSV_REG04E -  */
80073 /*! @{ */
80074 
80075 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_MASK (0x3U)
80076 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_SHIFT (0U)
80077 /*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4 - [GEN4] */
80078 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_MASK)
80079 
80080 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_MASK (0xCU)
80081 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_SHIFT (2U)
80082 /*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3 - [GEN3] */
80083 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_MASK)
80084 
80085 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_MASK (0x30U)
80086 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_SHIFT (4U)
80087 /*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2 - [GEN2] */
80088 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_MASK)
80089 
80090 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_MASK (0xC0U)
80091 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_SHIFT (6U)
80092 /*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1 - [GEN1] RX CTLE active load control */
80093 #define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_MASK)
80094 /*! @} */
80095 
80096 /*! @name TRSV_REG04F -  */
80097 /*! @{ */
80098 
80099 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_MASK (0x1U)
80100 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_SHIFT (0U)
80101 /*! LN0_ANA_RX_CTLE_PTAT_EN - RX CTLE PTAT current enable */
80102 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_SHIFT)) & PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_MASK)
80103 
80104 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_MASK (0x1EU)
80105 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_SHIFT (1U)
80106 /*! LN0_ANA_RX_CTLE_VREG_SEL - RX CTLE voltage regulator output voltage */
80107 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_SHIFT)) & PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_MASK)
80108 
80109 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_MASK (0xE0U)
80110 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_SHIFT (5U)
80111 /*! LN0_ANA_RX_CTLE_VGA_CTRL - RX CTLE stage3 gain control */
80112 #define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_MASK)
80113 /*! @} */
80114 
80115 /*! @name TRSV_REG050 -  */
80116 /*! @{ */
80117 
80118 #define PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_MASK (0x1U)
80119 #define PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_SHIFT (0U)
80120 /*! LN0_RX_DES_DATA_CLEAR - RX deserializer data clear to prevent garbage data */
80121 #define PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_SHIFT)) & PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_MASK)
80122 
80123 #define PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_MASK (0x2U)
80124 #define PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_SHIFT (1U)
80125 /*! LN0_OVRD_RX_DES_DATA_CLEAR - Override enable for rx_des_data_clear */
80126 #define PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_SHIFT)) & PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_MASK)
80127 
80128 #define PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_MASK (0x1CU)
80129 #define PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_SHIFT (2U)
80130 /*! LN0_ANA_RX_CTLE_RESERVED - Reserved port */
80131 #define PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_SHIFT)) & PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_MASK)
80132 /*! @} */
80133 
80134 /*! @name TRSV_REG051 -  */
80135 /*! @{ */
80136 
80137 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_MASK (0x3U)
80138 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_SHIFT (0U)
80139 /*! LN0_RX_DES_DATA_WIDTH_SEL_G4 - [GEN4] */
80140 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_MASK)
80141 
80142 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_MASK (0xCU)
80143 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_SHIFT (2U)
80144 /*! LN0_RX_DES_DATA_WIDTH_SEL_G3 - [GEN3] */
80145 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_MASK)
80146 
80147 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_MASK (0x30U)
80148 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_SHIFT (4U)
80149 /*! LN0_RX_DES_DATA_WIDTH_SEL_G2 - [GEN2] */
80150 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_MASK)
80151 
80152 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_MASK (0xC0U)
80153 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_SHIFT (6U)
80154 /*! LN0_RX_DES_DATA_WIDTH_SEL_G1 - [GEN1] RX deserializer data width selection */
80155 #define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_MASK)
80156 /*! @} */
80157 
80158 /*! @name TRSV_REG052 -  */
80159 /*! @{ */
80160 
80161 #define PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_MASK (0x3U)
80162 #define PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_SHIFT (0U)
80163 #define PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_MASK)
80164 
80165 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_MASK (0x4U)
80166 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_SHIFT (2U)
80167 /*! LN0_RX_DES_RSTN - RX deserializer reset */
80168 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_MASK)
80169 
80170 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_MASK (0x8U)
80171 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_SHIFT (3U)
80172 /*! LN0_OVRD_RX_DES_RSTN - Override enable for rx_des_rstn */
80173 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_MASK)
80174 
80175 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_MASK (0x10U)
80176 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_SHIFT (4U)
80177 /*! LN0_RX_DES_NON_DATA_SEL - RX deserializer non-data selection for edge/error sampler calibration */
80178 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_MASK)
80179 
80180 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_MASK (0x20U)
80181 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_SHIFT (5U)
80182 /*! LN0_OVRD_RX_DES_NON_DATA_SEL - Override enable for rx_des_non_data_sel */
80183 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_MASK)
80184 
80185 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_MASK  (0x40U)
80186 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_SHIFT (6U)
80187 /*! LN0_RX_DES_EN - RX deserializer enable */
80188 #define PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_MASK)
80189 
80190 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_MASK (0x80U)
80191 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_SHIFT (7U)
80192 /*! LN0_OVRD_RX_DES_EN - Override enable for rx_des_en */
80193 #define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_MASK)
80194 /*! @} */
80195 
80196 /*! @name TRSV_REG053 -  */
80197 /*! @{ */
80198 
80199 #define PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_MASK (0x7U)
80200 #define PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_SHIFT (0U)
80201 /*! LN0_ANA_RX_DFE_EOM_PI_DIV_SEL - Clock divider control before RX EOM phase interpolator */
80202 #define PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_MASK)
80203 
80204 #define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_MASK (0x8U)
80205 #define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_SHIFT (3U)
80206 /*! LN0_RX_DFE_EOM_EN - RX EOM enable */
80207 #define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_MASK)
80208 
80209 #define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_MASK (0x10U)
80210 #define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_SHIFT (4U)
80211 /*! LN0_OVRD_RX_DFE_EOM_EN - Override enable for rx_dfe_eom_en */
80212 #define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_MASK)
80213 
80214 #define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_MASK (0x20U)
80215 #define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_SHIFT (5U)
80216 /*! LN0_RX_DFE_ADAP_EN - RX DFE adaptation path enable. Only one of i_rx_dfe_adap_en and i_rx_eom_en should be "1". */
80217 #define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_MASK)
80218 
80219 #define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_MASK (0x40U)
80220 #define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_SHIFT (6U)
80221 /*! LN0_OVRD_RX_DFE_ADAP_EN - Override enable for rx_dfe_adap_en */
80222 #define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_MASK)
80223 /*! @} */
80224 
80225 /*! @name TRSV_REG054 -  */
80226 /*! @{ */
80227 
80228 #define PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_MASK (0xFU)
80229 #define PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_SHIFT (0U)
80230 /*! LN0_ANA_RX_DFE_EOM_PI_STR_CTRL - RX EOM PI drive strengh in pre-buffer stage */
80231 #define PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_MASK)
80232 /*! @} */
80233 
80234 /*! @name TRSV_REG055 -  */
80235 /*! @{ */
80236 
80237 #define PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_MASK (0x7FU)
80238 #define PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT (0U)
80239 /*! LN0_RX_DFE_OC_ADDER_EVEN_CODE - RX DFE even data path offset calibration code */
80240 #define PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_MASK)
80241 
80242 #define PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_MASK (0x80U)
80243 #define PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT (7U)
80244 /*! LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE - Override enable for rx_dfe_oc_adder_even_code */
80245 #define PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_MASK)
80246 /*! @} */
80247 
80248 /*! @name TRSV_REG056 -  */
80249 /*! @{ */
80250 
80251 #define PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_MASK (0x7FU)
80252 #define PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_SHIFT (0U)
80253 /*! LN0_RX_DFE_OC_ADDER_ODD_CODE - RX DFE odd data path offset calibration code */
80254 #define PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_MASK)
80255 
80256 #define PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_MASK (0x80U)
80257 #define PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_SHIFT (7U)
80258 /*! LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE - Override enable for rx_dfe_oc_adder_odd_code */
80259 #define PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_MASK)
80260 /*! @} */
80261 
80262 /*! @name TRSV_REG057 -  */
80263 /*! @{ */
80264 
80265 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK (0x7U)
80266 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT (0U)
80267 /*! LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE - Fine control of zero-crossing in RX DFE DAC for even edge path offset calibration */
80268 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK)
80269 
80270 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK (0x8U)
80271 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT (3U)
80272 /*! LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE - Override enable for rx_dfe_oc_dac_edge_even_code */
80273 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK)
80274 
80275 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK (0x10U)
80276 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT (4U)
80277 /*! LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE - Fine control of zero-crossing in RX DFE DAC for odd adder offset calibration */
80278 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK)
80279 
80280 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK (0x20U)
80281 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT (5U)
80282 /*! LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE - Override enable for rx_dfe_oc_dac_adder_odd_code */
80283 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK)
80284 
80285 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK (0x40U)
80286 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT (6U)
80287 /*! LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE - Fine control of zero-crossing in RX DFE DAC for even adder offset calibration */
80288 #define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK)
80289 
80290 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK (0x80U)
80291 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT (7U)
80292 /*! LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE - Override enable for rx_dfe_oc_dac_adder_even_code */
80293 #define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK)
80294 /*! @} */
80295 
80296 /*! @name TRSV_REG058 -  */
80297 /*! @{ */
80298 
80299 #define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK (0x7U)
80300 #define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT (0U)
80301 /*! LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE - Fine control of zero-crossing in RX DFE DAC for even error path offset calibration */
80302 #define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK)
80303 
80304 #define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK (0x8U)
80305 #define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT (3U)
80306 /*! LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE - Override enable for rx_dfe_oc_dac_err_even_code */
80307 #define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK)
80308 
80309 #define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK (0x70U)
80310 #define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT (4U)
80311 /*! LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE - Fine control of zero-crossing in RX DFE DAC for odd edge path offset calibration */
80312 #define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK)
80313 
80314 #define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK (0x80U)
80315 #define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT (7U)
80316 /*! LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE - Override enable for rx_dfe_oc_dac_edge_odd_code */
80317 #define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK)
80318 /*! @} */
80319 
80320 /*! @name TRSV_REG059 -  */
80321 /*! @{ */
80322 
80323 #define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_MASK (0x1U)
80324 #define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_SHIFT (0U)
80325 /*! LN0_RX_DFE_OC_EN - RX DFE offset calibration progress enable */
80326 #define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_MASK)
80327 
80328 #define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_MASK (0x2U)
80329 #define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_SHIFT (1U)
80330 /*! LN0_OVRD_RX_DFE_OC_EN - Override enable for rx_dfe_oc_en */
80331 #define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_MASK)
80332 
80333 #define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK (0x1CU)
80334 #define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT (2U)
80335 /*! LN0_RX_DFE_OC_DAC_ERR_ODD_CODE - Fine control of zero-crossing in RX DFE DAC for odd error path offset calibration */
80336 #define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK)
80337 
80338 #define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK (0x20U)
80339 #define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT (5U)
80340 /*! LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE - Override enable for rx_dfe_oc_dac_err_odd_code */
80341 #define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK)
80342 /*! @} */
80343 
80344 /*! @name TRSV_REG05A -  */
80345 /*! @{ */
80346 
80347 #define PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_MASK (0x1U)
80348 #define PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_SHIFT (0U)
80349 /*! LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8 - RX DFE even edge path offset calibration code */
80350 #define PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_MASK)
80351 
80352 #define PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_MASK (0x2U)
80353 #define PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_SHIFT (1U)
80354 /*! LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE - Override enable for rx_dfe_oc_sa_edge_even_code */
80355 #define PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_MASK)
80356 /*! @} */
80357 
80358 /*! @name TRSV_REG05B -  */
80359 /*! @{ */
80360 
80361 #define PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_MASK (0xFFU)
80362 #define PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_SHIFT (0U)
80363 /*! LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0 - RX DFE even edge path offset calibration code */
80364 #define PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_MASK)
80365 /*! @} */
80366 
80367 /*! @name TRSV_REG05C -  */
80368 /*! @{ */
80369 
80370 #define PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_MASK (0x1U)
80371 #define PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_SHIFT (0U)
80372 /*! LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8 - RX DFE odd edge path offset calibration code */
80373 #define PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_MASK)
80374 
80375 #define PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_MASK (0x2U)
80376 #define PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_SHIFT (1U)
80377 /*! LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE - Override enable for rx_dfe_oc_sa_edge_odd_code */
80378 #define PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_MASK)
80379 /*! @} */
80380 
80381 /*! @name TRSV_REG05D -  */
80382 /*! @{ */
80383 
80384 #define PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_MASK (0xFFU)
80385 #define PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_SHIFT (0U)
80386 /*! LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0 - RX DFE odd edge path offset calibration code */
80387 #define PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_MASK)
80388 /*! @} */
80389 
80390 /*! @name TRSV_REG05E -  */
80391 /*! @{ */
80392 
80393 #define PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_MASK (0x1U)
80394 #define PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_SHIFT (0U)
80395 /*! LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8 - RX DFE even error path offset calibration code */
80396 #define PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_MASK)
80397 
80398 #define PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_MASK (0x2U)
80399 #define PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_SHIFT (1U)
80400 /*! LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE - Override enable for rx_dfe_oc_sa_err_even_code */
80401 #define PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_MASK)
80402 /*! @} */
80403 
80404 /*! @name TRSV_REG05F -  */
80405 /*! @{ */
80406 
80407 #define PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_MASK (0xFFU)
80408 #define PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_SHIFT (0U)
80409 /*! LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0 - RX DFE even error path offset calibration code */
80410 #define PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_MASK)
80411 /*! @} */
80412 
80413 /*! @name TRSV_REG060 -  */
80414 /*! @{ */
80415 
80416 #define PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_MASK (0x1U)
80417 #define PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_SHIFT (0U)
80418 /*! LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8 - RX DFE odd error path offset calibration code */
80419 #define PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_MASK)
80420 
80421 #define PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_MASK (0x2U)
80422 #define PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_SHIFT (1U)
80423 /*! LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE - Override enable for rx_dfe_oc_sa_err_odd_code */
80424 #define PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_MASK)
80425 /*! @} */
80426 
80427 /*! @name TRSV_REG061 -  */
80428 /*! @{ */
80429 
80430 #define PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_MASK (0xFFU)
80431 #define PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_SHIFT (0U)
80432 /*! LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0 - RX DFE odd error path offset calibration code */
80433 #define PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_MASK)
80434 /*! @} */
80435 
80436 /*! @name TRSV_REG062 -  */
80437 /*! @{ */
80438 
80439 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_MASK (0x1U)
80440 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_SHIFT (0U)
80441 /*! LN0_RX_DFE_SA_ERR_OC_EN - RX DFE error path enable in offset calibration (If all of
80442  *    rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
80443  */
80444 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_MASK)
80445 
80446 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_MASK (0x2U)
80447 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_SHIFT (1U)
80448 /*! LN0_OVRD_RX_DFE_SA_ERR_OC_EN - Override enable for rx_dfe_sa_err_oc_en */
80449 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_MASK)
80450 
80451 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_MASK (0x4U)
80452 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_SHIFT (2U)
80453 /*! LN0_RX_DFE_SA_EDGE_OC_EN - RX DFE edge path enable in offset calibration (If all of
80454  *    rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
80455  */
80456 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_MASK)
80457 
80458 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_MASK (0x8U)
80459 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_SHIFT (3U)
80460 /*! LN0_OVRD_RX_DFE_SA_EDGE_OC_EN - Override enable for rx_dfe_sa_edge_oc_en */
80461 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_MASK)
80462 
80463 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_MASK (0x10U)
80464 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT (4U)
80465 /*! LN0_RX_DFE_SA_DATA_ODD_OC_EN - RX DFE data even path enable in offset calibration (If all of
80466  *    rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
80467  */
80468 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_MASK)
80469 
80470 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_MASK (0x20U)
80471 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT (5U)
80472 /*! LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN - Override enable for rx_dfe_sa_data_odd_oc_en */
80473 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_MASK)
80474 
80475 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_MASK (0x40U)
80476 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT (6U)
80477 /*! LN0_RX_DFE_SA_DATA_EVEN_OC_EN - RX DFE data odd path enable in offset calibration (If all of
80478  *    rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
80479  */
80480 #define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_MASK)
80481 
80482 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_MASK (0x80U)
80483 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT (7U)
80484 /*! LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN - Override enable for rx_dfe_sa_data_even_oc_en */
80485 #define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_MASK)
80486 /*! @} */
80487 
80488 /*! @name TRSV_REG063 -  */
80489 /*! @{ */
80490 
80491 #define PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_MASK (0x1U)
80492 #define PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_SHIFT (0U)
80493 /*! LN0_RX_DFE_VREF_CTRL__8 - RX DFE Vref control */
80494 #define PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_SHIFT)) & PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_MASK)
80495 
80496 #define PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_MASK (0x2U)
80497 #define PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_SHIFT (1U)
80498 /*! LN0_OVRD_RX_DFE_VREF_CTRL - Override enable for rx_dfe_vref_ctrl */
80499 #define PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_MASK)
80500 /*! @} */
80501 
80502 /*! @name TRSV_REG064 -  */
80503 /*! @{ */
80504 
80505 #define PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_MASK (0xFFU)
80506 #define PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_SHIFT (0U)
80507 /*! LN0_RX_DFE_VREF_CTRL__7_0 - RX DFE Vref control */
80508 #define PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_SHIFT)) & PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_MASK)
80509 /*! @} */
80510 
80511 /*! @name TRSV_REG065 -  */
80512 /*! @{ */
80513 
80514 #define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_MASK (0xFU)
80515 #define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_SHIFT (0U)
80516 /*! LN0_ANA_RX_DFE_VREG_SEL - N/A, DFE bias current control [3:2]: DFE adder bias current, [1:0]: OC DAC bias current. */
80517 #define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_SHIFT)) & PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_MASK)
80518 
80519 #define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_MASK (0xF0U)
80520 #define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_SHIFT (4U)
80521 #define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_MASK)
80522 /*! @} */
80523 
80524 /*! @name TRSV_REG066 -  */
80525 /*! @{ */
80526 
80527 #define PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_MASK (0x1U)
80528 #define PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_SHIFT (0U)
80529 /*! LN0_RX_RCAL_EN - RX RCAL enable */
80530 #define PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_MASK)
80531 
80532 #define PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_MASK (0x2U)
80533 #define PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_SHIFT (1U)
80534 /*! LN0_OVRD_RX_RCAL_EN - Override enable for rx_rcal_en */
80535 #define PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_MASK)
80536 
80537 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_MASK (0x4U)
80538 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_SHIFT (2U)
80539 /*! LN0_ANA_RX_DFE_EOM_CLK_SEL - RX EOM clock selection */
80540 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_MASK)
80541 
80542 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_MASK (0x38U)
80543 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_SHIFT (3U)
80544 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_MASK)
80545 
80546 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_MASK (0x40U)
80547 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_SHIFT (6U)
80548 /*! LN0_ANA_RX_DFE_DAC_OUT_PULLUP - Pull-up all DAC output in RX DFE to disable all offset code effect */
80549 #define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_MASK)
80550 /*! @} */
80551 
80552 /*! @name TRSV_REG067 -  */
80553 /*! @{ */
80554 
80555 #define PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_MASK (0x1U)
80556 #define PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_SHIFT (0U)
80557 /*! LN0_RX_RTERM_EN - RX RTERM enable */
80558 #define PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_MASK)
80559 
80560 #define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_MASK (0x2U)
80561 #define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_SHIFT (1U)
80562 /*! LN0_OVRD_RX_RTERM_EN - Override enable for rx_rterm_en */
80563 #define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_MASK)
80564 
80565 #define PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_MASK (0xCU)
80566 #define PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_SHIFT (2U)
80567 #define PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_MASK)
80568 
80569 #define PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_MASK (0x10U)
80570 #define PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_SHIFT (4U)
80571 /*! LN0_RX_RCAL_BIAS_EN - RX RCAL bias current enable */
80572 #define PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_MASK)
80573 
80574 #define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_MASK (0x20U)
80575 #define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_SHIFT (5U)
80576 /*! LN0_OVRD_RX_RCAL_BIAS_EN - Override enable for rx_rcal_bias_en */
80577 #define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_MASK)
80578 /*! @} */
80579 
80580 /*! @name TRSV_REG068 -  */
80581 /*! @{ */
80582 
80583 #define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_MASK (0x3U)
80584 #define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_SHIFT (0U)
80585 /*! LN0_ANA_RX_RTERM_INCM_SW_CTRL - RX RTERM single-ended impedance control by switch control */
80586 #define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_MASK)
80587 
80588 #define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_MASK (0xCU)
80589 #define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_SHIFT (2U)
80590 /*! LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL - RX RTERM single-ended impedance control by current control */
80591 #define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_MASK)
80592 
80593 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_MASK (0x10U)
80594 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_SHIFT (4U)
80595 /*! LN0_RX_RTERM_42P5_EN_G4 - [GEN4] */
80596 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_MASK)
80597 
80598 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_MASK (0x20U)
80599 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_SHIFT (5U)
80600 /*! LN0_RX_RTERM_42P5_EN_G3 - [GEN3] */
80601 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_MASK)
80602 
80603 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_MASK (0x40U)
80604 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_SHIFT (6U)
80605 /*! LN0_RX_RTERM_42P5_EN_G2 - [GEN2] */
80606 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_MASK)
80607 
80608 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_MASK (0x80U)
80609 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_SHIFT (7U)
80610 /*! LN0_RX_RTERM_42P5_EN_G1 - [GEN1] RX RTERM resistance shift */
80611 #define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_MASK)
80612 /*! @} */
80613 
80614 /*! @name TRSV_REG069 -  */
80615 /*! @{ */
80616 
80617 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_MASK (0x1U)
80618 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_SHIFT (0U)
80619 /*! LN0_ANA_RX_RTERM_OFSP_CTRL - Offset code for RX RTERM P node */
80620 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_MASK)
80621 
80622 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_MASK (0x2U)
80623 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_SHIFT (1U)
80624 /*! LN0_ANA_RX_RTERM_OFSN_CTRL - Offset code for RX RTERM N node */
80625 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_MASK)
80626 
80627 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_MASK (0xCU)
80628 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_SHIFT (2U)
80629 /*! LN0_ANA_RX_RTERM_INCM_VCM_CTRL - RX RTERM output common-mode voltage control */
80630 #define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_MASK)
80631 /*! @} */
80632 
80633 /*! @name TRSV_REG06A -  */
80634 /*! @{ */
80635 
80636 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_MASK (0x1U)
80637 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_SHIFT (0U)
80638 /*! LN0_RX_RTERM_CM_PULLDN_G4 - [GEN4] */
80639 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_MASK)
80640 
80641 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_MASK (0x2U)
80642 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_SHIFT (1U)
80643 /*! LN0_RX_RTERM_CM_PULLDN_G3 - [GEN3] */
80644 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_MASK)
80645 
80646 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_MASK (0x4U)
80647 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_SHIFT (2U)
80648 /*! LN0_RX_RTERM_CM_PULLDN_G2 - [GEN2] */
80649 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_MASK)
80650 
80651 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_MASK (0x8U)
80652 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_SHIFT (3U)
80653 /*! LN0_RX_RTERM_CM_PULLDN_G1 - [GEN1] RX RTERM termination voltage pull-down */
80654 #define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_MASK)
80655 
80656 #define PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_MASK (0x10U)
80657 #define PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_SHIFT (4U)
80658 /*! LN0_OVRD_RX_RTERM_CM_PULLDN - Override enable for rx_rterm_cm_pulldn_g1 */
80659 #define PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_MASK)
80660 /*! @} */
80661 
80662 /*! @name TRSV_REG06B -  */
80663 /*! @{ */
80664 
80665 #define PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_MASK (0x1U)
80666 #define PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_SHIFT (0U)
80667 #define PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_MASK)
80668 
80669 #define PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_MASK (0x2U)
80670 #define PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_SHIFT (1U)
80671 #define PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_MASK)
80672 
80673 #define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_MASK (0x4U)
80674 #define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_SHIFT (2U)
80675 /*! LN0_OVRD_RX_SQ_BMR_EN - Override enable for rx_sq_bmr_en */
80676 #define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_MASK)
80677 
80678 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_MASK (0x8U)
80679 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_SHIFT (3U)
80680 /*! LN0_RX_RTERM_VCM_EN_G4 - [GEN4] */
80681 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_MASK)
80682 
80683 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_MASK (0x10U)
80684 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_SHIFT (4U)
80685 /*! LN0_RX_RTERM_VCM_EN_G3 - [GEN3] */
80686 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_MASK)
80687 
80688 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_MASK (0x20U)
80689 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_SHIFT (5U)
80690 /*! LN0_RX_RTERM_VCM_EN_G2 - [GEN2] */
80691 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_MASK)
80692 
80693 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_MASK (0x40U)
80694 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_SHIFT (6U)
80695 /*! LN0_RX_RTERM_VCM_EN_G1 - [GEN1] */
80696 #define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_MASK)
80697 
80698 #define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_MASK (0x80U)
80699 #define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_SHIFT (7U)
80700 /*! LN0_OVRD_RX_RTERM_VCM_EN - Override enable for rx_rterm_vcm_en_g1 */
80701 #define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_MASK)
80702 /*! @} */
80703 
80704 /*! @name TRSV_REG06C -  */
80705 /*! @{ */
80706 
80707 #define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_MASK (0x1U)
80708 #define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_SHIFT (0U)
80709 /*! LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN - RX high-squelch diff-N offset sign */
80710 #define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_MASK)
80711 
80712 #define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_MASK (0x2U)
80713 #define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_SHIFT (1U)
80714 /*! LN0_RX_SQHS_DIFN_OC_EN - RX high-squelch diff-N offset calibration enable */
80715 #define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_MASK)
80716 
80717 #define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_MASK (0x4U)
80718 #define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_SHIFT (2U)
80719 /*! LN0_OVRD_RX_SQHS_DIFN_OC_EN - Override enable for rx_sqhs_difn_oc_en */
80720 #define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_MASK)
80721 
80722 #define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_MASK (0x8U)
80723 #define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_SHIFT (3U)
80724 /*! LN0_RX_SQHS_EN - RX high-speed squelch enable */
80725 #define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_MASK)
80726 
80727 #define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_MASK (0x10U)
80728 #define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_SHIFT (4U)
80729 /*! LN0_OVRD_RX_SQHS_EN - Override enable for rx_sqhs_en */
80730 #define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_MASK)
80731 
80732 #define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_MASK (0x60U)
80733 #define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_SHIFT (5U)
80734 #define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_MASK)
80735 /*! @} */
80736 
80737 /*! @name TRSV_REG06D -  */
80738 /*! @{ */
80739 
80740 #define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_MASK (0x1U)
80741 #define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_SHIFT (0U)
80742 /*! LN0_RX_SQHS_DIFP_OC_EN - RX high-squelch diff-P offset calibration enable */
80743 #define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_MASK)
80744 
80745 #define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_MASK (0x2U)
80746 #define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_SHIFT (1U)
80747 /*! LN0_OVRD_RX_SQHS_DIFP_OC_EN - Override enable for rx_sqhs_difp_oc_en */
80748 #define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_MASK)
80749 
80750 #define PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_MASK (0x4U)
80751 #define PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_SHIFT (2U)
80752 #define PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_MASK)
80753 
80754 #define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_MASK (0x78U)
80755 #define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_SHIFT (3U)
80756 /*! LN0_RX_SQHS_DIFN_OC_CODE - RX high-squelch diff-N manual offset code */
80757 #define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_MASK)
80758 
80759 #define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_MASK (0x80U)
80760 #define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_SHIFT (7U)
80761 /*! LN0_OVRD_RX_SQHS_DIFN_OC_CODE - Override enable for rx_sqhs_difn_oc_code */
80762 #define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_MASK)
80763 /*! @} */
80764 
80765 /*! @name TRSV_REG06E -  */
80766 /*! @{ */
80767 
80768 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_MASK (0x1U)
80769 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_SHIFT (0U)
80770 /*! LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN - Fixed skew for PCIe/SATA Squelch */
80771 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_MASK)
80772 
80773 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_MASK (0x2U)
80774 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_SHIFT (1U)
80775 /*! LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN - Enable the high speed Squelch DIFP SKEW BUFFER */
80776 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_MASK)
80777 
80778 #define PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_MASK (0x3CU)
80779 #define PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_SHIFT (2U)
80780 /*! LN0_RX_SQHS_DIFP_OC_CODE - RX squelch diff-P manual offset code */
80781 #define PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_MASK)
80782 
80783 #define PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_MASK (0x40U)
80784 #define PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_SHIFT (6U)
80785 /*! LN0_OVRD_RX_SQHS_DIFP_OC_CODE - Override enable for rx_sqhs_difp_oc_code */
80786 #define PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_MASK)
80787 
80788 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_MASK (0x80U)
80789 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_SHIFT (7U)
80790 /*! LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN - RX high-squelch diff-P offset sign */
80791 #define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_MASK)
80792 /*! @} */
80793 
80794 /*! @name TRSV_REG06F -  */
80795 /*! @{ */
80796 
80797 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_MASK (0x1U)
80798 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_SHIFT (0U)
80799 /*! LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL - Selection of supply voltage of reference voltage for threshold calibration of HS SQ */
80800 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_MASK)
80801 
80802 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_MASK (0x6U)
80803 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_SHIFT (1U)
80804 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_MASK)
80805 
80806 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_MASK (0x8U)
80807 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_SHIFT (3U)
80808 /*! LN0_ANA_RX_SQHS_FILTER_EN - SQHS loss detector enable */
80809 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_MASK)
80810 
80811 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_MASK (0xF0U)
80812 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_SHIFT (4U)
80813 /*! LN0_ANA_RX_SQHS_TH_CTRL - RX squelch threshold voltage selection */
80814 #define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_MASK)
80815 /*! @} */
80816 
80817 /*! @name TRSV_REG070 -  */
80818 /*! @{ */
80819 
80820 #define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_MASK (0x7U)
80821 #define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_SHIFT (0U)
80822 /*! LN0_ANA_RX_SQLS_DIFN_TH_CTRL - DIFN in MPHY, LFPS in USB: */
80823 #define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_MASK)
80824 
80825 #define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_MASK (0x8U)
80826 #define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_SHIFT (3U)
80827 /*! LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL - RX DIFP detect signal selection for PRE_DATA_VALID and DATA_VALID signal */
80828 #define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_MASK)
80829 
80830 #define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_MASK (0x10U)
80831 #define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_SHIFT (4U)
80832 /*! LN0_RX_SQLS_DIFP_DET_EN - RX low-speed DIFP squelch enable */
80833 #define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_MASK)
80834 
80835 #define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_MASK (0x20U)
80836 #define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_SHIFT (5U)
80837 /*! LN0_OVRD_RX_SQLS_DIFP_DET_EN - Override enable for rx_sqls_difp_det_en */
80838 #define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_MASK)
80839 
80840 #define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_MASK (0x40U)
80841 #define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_SHIFT (6U)
80842 /*! LN0_RX_SQLS_DIFN_DET_EN - RX low-speed DIFN squelch enable */
80843 #define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_MASK)
80844 
80845 #define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_MASK (0x80U)
80846 #define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_SHIFT (7U)
80847 /*! LN0_OVRD_RX_SQLS_DIFN_DET_EN - Override enable for rx_sqls_difn_det_en */
80848 #define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_MASK)
80849 /*! @} */
80850 
80851 /*! @name TRSV_REG071 -  */
80852 /*! @{ */
80853 
80854 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_MASK (0x3U)
80855 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_SHIFT (0U)
80856 /*! LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL - Current controls for low-speed Squelch comparator current source */
80857 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_MASK)
80858 
80859 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_MASK (0x1CU)
80860 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_SHIFT (2U)
80861 /*! LN0_ANA_RX_SQLS_IN_LPF_CTRL - Low pass filter resistor control for Squelch input : 00:30MHz,01:60MHz,, 10:100MHz, 11: 150MHz */
80862 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_MASK)
80863 
80864 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_MASK (0xE0U)
80865 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_SHIFT (5U)
80866 /*! LN0_ANA_RX_SQLS_DIFP_TH_CTRL - DIFP in MPHY */
80867 #define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_MASK)
80868 /*! @} */
80869 
80870 /*! @name TRSV_REG072 -  */
80871 /*! @{ */
80872 
80873 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_MASK (0x1U)
80874 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_SHIFT (0U)
80875 /*! LN0_RX_PWM_AFC_RSTN - RX MPHY PWM AFC reset */
80876 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_MASK)
80877 
80878 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_MASK (0x2U)
80879 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_SHIFT (1U)
80880 /*! LN0_OVRD_RX_PWM_AFC_RSTN - Override enable for rx_pwm_afc_rstn */
80881 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_MASK)
80882 
80883 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_MASK (0x4U)
80884 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_SHIFT (2U)
80885 /*! LN0_RX_PWM_RSTN - RX MPHY PWM reset */
80886 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN(x)  (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_MASK)
80887 
80888 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_MASK (0x8U)
80889 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_SHIFT (3U)
80890 /*! LN0_OVRD_RX_PWM_RSTN - Override enable for rx_pwm_rstn */
80891 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_MASK)
80892 
80893 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_MASK (0x10U)
80894 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_SHIFT (4U)
80895 /*! LN0_RX_PWM_CNT_EN - Enalbe counter clock for PWM over sampling */
80896 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_MASK)
80897 
80898 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_MASK (0x20U)
80899 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_SHIFT (5U)
80900 /*! LN0_OVRD_RX_PWM_CNT_EN - Override enable for rx_pwm_cnt_en */
80901 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_MASK)
80902 
80903 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_MASK (0x40U)
80904 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_SHIFT (6U)
80905 /*! LN0_RX_PWM_OSC_EN - RX MPHY PWM oscillator enable which is used in analog RX block in order to oversample */
80906 #define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_MASK)
80907 
80908 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_MASK (0x80U)
80909 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_SHIFT (7U)
80910 /*! LN0_OVRD_RX_PWM_OSC_EN - Override enable for rx_pwm_osc_en */
80911 #define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_MASK)
80912 /*! @} */
80913 
80914 /*! @name TRSV_REG073 -  */
80915 /*! @{ */
80916 
80917 #define PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_MASK (0x7U)
80918 #define PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_SHIFT (0U)
80919 /*! LN0_ANA_RX_PWM_DIV_RATIO - RX MPHY PWM oversampling clock divide ratio from PWM oscillator */
80920 #define PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_SHIFT)) & PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_MASK)
80921 
80922 #define PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_MASK (0x8U)
80923 #define PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_SHIFT (3U)
80924 /*! LN0_RX_PWM_AFC_DONE - RX MPHY PWM AFC done signal */
80925 #define PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_MASK)
80926 
80927 #define PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_MASK (0x10U)
80928 #define PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_SHIFT (4U)
80929 /*! LN0_OVRD_RX_PWM_AFC_DONE - Override enable for rx_pwm_afc_done */
80930 #define PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_MASK)
80931 /*! @} */
80932 
80933 /*! @name TRSV_REG074 -  */
80934 /*! @{ */
80935 
80936 #define PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_MASK (0x1U)
80937 #define PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_SHIFT (0U)
80938 #define PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_MASK)
80939 
80940 #define PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_MASK (0x1EU)
80941 #define PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_SHIFT (1U)
80942 /*! LN0_RX_PWM_OSC_CODE - RX MPHY PWM AFC code for oscillator */
80943 #define PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_MASK)
80944 
80945 #define PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_MASK (0x20U)
80946 #define PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_SHIFT (5U)
80947 /*! LN0_OVRD_RX_PWM_OSC_CODE - Override enable for rx_pwm_osc_code */
80948 #define PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_MASK)
80949 /*! @} */
80950 
80951 /*! @name TRSV_REG075 -  */
80952 /*! @{ */
80953 
80954 #define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_MASK (0x1U)
80955 #define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_SHIFT (0U)
80956 /*! LN0_ANA_RX_LFPS_LOSS_DET_EN - LFPS loss detector enable */
80957 #define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_MASK)
80958 
80959 #define PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_MASK (0x2U)
80960 #define PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_SHIFT (1U)
80961 /*! LN0_RX_LFPS_DET_EN - LFPS detector enable */
80962 #define PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_MASK)
80963 
80964 #define PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_MASK (0x4U)
80965 #define PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_SHIFT (2U)
80966 /*! LN0_OVRD_RX_LFPS_DET_EN - Override enable for rx_lfps_det_en */
80967 #define PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_MASK)
80968 
80969 #define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_MASK (0x78U)
80970 #define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_SHIFT (3U)
80971 /*! LN0_ANA_RX_PWM_OC_CODE - min(-7 or 0_111){maximum negative offset} - max(+7 or 1_111) {maximum positive offset} */
80972 #define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_MASK)
80973 /*! @} */
80974 
80975 /*! @name TRSV_REG076 -  */
80976 /*! @{ */
80977 
80978 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_MASK (0x1U)
80979 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_SHIFT (0U)
80980 /*! LN0_ANA_RX_SRLB_EN - Serial retimed loopback enable */
80981 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_MASK)
80982 
80983 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_MASK (0x2U)
80984 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_SHIFT (1U)
80985 /*! LN0_ANA_RX_LLB_EN - Line loopback enalble */
80986 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_MASK)
80987 
80988 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_MASK (0x4U)
80989 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_SHIFT (2U)
80990 /*! LN0_ANA_RX_SLB_EN - Serial loopback enable */
80991 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_MASK)
80992 
80993 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_MASK (0x38U)
80994 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_SHIFT (3U)
80995 /*! LN0_ANA_RX_BIAS_RMRES_CTRL - RX RMRES bias current control */
80996 #define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_MASK)
80997 
80998 #define PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_MASK (0x40U)
80999 #define PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_SHIFT (6U)
81000 /*! LN0_RX_BIAS_EN - RX bias current enable */
81001 #define PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_MASK)
81002 
81003 #define PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_MASK (0x80U)
81004 #define PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_SHIFT (7U)
81005 /*! LN0_OVRD_RX_BIAS_EN - Override enable for rx_bias_en */
81006 #define PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_MASK)
81007 /*! @} */
81008 
81009 /*! @name TRSV_REG077 -  */
81010 /*! @{ */
81011 
81012 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_MASK (0x3U)
81013 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_SHIFT (0U)
81014 /*! LN0_ANA_RX_LLB_ITAIL_CTRL - Line loopback tail-current control */
81015 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_MASK)
81016 
81017 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_MASK (0x1CU)
81018 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_SHIFT (2U)
81019 /*! LN0_ANA_RX_LLB_DUTY_CTRL - Line loopback duty-ratio control */
81020 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_MASK)
81021 
81022 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_MASK (0x20U)
81023 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_SHIFT (5U)
81024 /*! LN0_ANA_RX_LLB_ACCAP_EN - Line loopback path selection */
81025 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_MASK)
81026 
81027 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_MASK (0x40U)
81028 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_SHIFT (6U)
81029 /*! LN0_ANA_RX_SRLB_DATA_EDGE_SEL - Serial retimed loopback path selection */
81030 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_MASK)
81031 
81032 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_MASK (0x80U)
81033 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_SHIFT (7U)
81034 /*! LN0_ANA_RX_SRLB_EVEN_ODD_SEL - Serial retimed loopback path selection */
81035 #define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_MASK)
81036 /*! @} */
81037 
81038 /*! @name TRSV_REG078 -  */
81039 /*! @{ */
81040 
81041 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_MASK (0x1U)
81042 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_SHIFT (0U)
81043 /*! LN0_ANA_RX_ATB_EN - RX ATB enable */
81044 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_SHIFT)) & PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_MASK)
81045 
81046 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_MASK (0x2U)
81047 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_SHIFT (1U)
81048 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_MASK)
81049 
81050 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_MASK (0x4U)
81051 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_SHIFT (2U)
81052 /*! LN0_ANA_RX_LLB_RLOAD_CTRL - Line loopback load resistance control */
81053 #define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_MASK)
81054 /*! @} */
81055 
81056 /*! @name TRSV_REG079 -  */
81057 /*! @{ */
81058 
81059 #define PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_MASK (0x3FU)
81060 #define PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_SHIFT (0U)
81061 /*! LN0_ANA_RX_ATB_SEL - When i_sfr_rx_atb_en=1 and i_sfr_rx_atb_sel&lt;5&gt;=0, RX AFE nodes are under monitoring. */
81062 #define PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_SHIFT)) & PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_MASK)
81063 /*! @} */
81064 
81065 /*! @name TRSV_REG07A -  */
81066 /*! @{ */
81067 
81068 #define PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_MASK (0xFFU)
81069 #define PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_SHIFT (0U)
81070 /*! LN0_ANA_RX_RESERVED - Reserved port */
81071 #define PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_SHIFT)) & PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_MASK)
81072 /*! @} */
81073 
81074 /*! @name TRSV_REG07B -  */
81075 /*! @{ */
81076 
81077 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_MASK   (0x1U)
81078 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_SHIFT  (0U)
81079 /*! LN0_RX_OC_EN - RX offset calibration tolerance for average value */
81080 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN(x)     (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_MASK)
81081 
81082 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_MASK  (0x6U)
81083 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_SHIFT (1U)
81084 /*! LN0_RX_OC_TOL - RX offset calibration enable */
81085 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_MASK)
81086 
81087 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_MASK (0x18U)
81088 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_SHIFT (3U)
81089 /*! LN0_RX_OC_CNT_SEL - RX SQ offset calibraiton counter selection for waiting time */
81090 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_MASK)
81091 
81092 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_MASK (0xE0U)
81093 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_SHIFT (5U)
81094 /*! LN0_RX_OC_TRIAL_CNT - RX offset calibration trial number selection */
81095 #define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_MASK)
81096 /*! @} */
81097 
81098 /*! @name TRSV_REG07C -  */
81099 /*! @{ */
81100 
81101 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_MASK (0x1U)
81102 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_SHIFT (0U)
81103 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_MASK)
81104 
81105 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_MASK (0x2U)
81106 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_SHIFT (1U)
81107 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_MASK)
81108 
81109 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_MASK (0x4U)
81110 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_SHIFT (2U)
81111 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_MASK)
81112 
81113 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_MASK (0x8U)
81114 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_SHIFT (3U)
81115 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_MASK)
81116 
81117 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_MASK (0x10U)
81118 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_SHIFT (4U)
81119 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_MASK)
81120 
81121 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_MASK (0x20U)
81122 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_SHIFT (5U)
81123 /*! LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD - Bypass */
81124 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_MASK)
81125 
81126 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_MASK (0xC0U)
81127 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_SHIFT (6U)
81128 /*! LN0_RX_OC_UPD_CNT_SEL - RX offset calibration code wating time selection for SA & CTLE only */
81129 #define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_MASK)
81130 /*! @} */
81131 
81132 /*! @name TRSV_REG07D -  */
81133 /*! @{ */
81134 
81135 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_MASK (0x1U)
81136 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_SHIFT (0U)
81137 /*! LN0_RX_OC_DONE - RX offset calibration overide value */
81138 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_MASK)
81139 
81140 #define PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_MASK (0x2U)
81141 #define PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_SHIFT (1U)
81142 /*! LN0_OVRD_RX_OC_DONE - Override enable for rx_oc_done */
81143 #define PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_MASK)
81144 
81145 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_MASK (0x4U)
81146 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_SHIFT (2U)
81147 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_MASK)
81148 
81149 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_MASK (0x8U)
81150 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_SHIFT (3U)
81151 /*! LN0_RX_OC_BYPASS_CTLE - Bypass offset calibration for CTLE */
81152 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_MASK)
81153 
81154 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_MASK (0x10U)
81155 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_SHIFT (4U)
81156 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_MASK)
81157 
81158 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_MASK (0x20U)
81159 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_SHIFT (5U)
81160 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_MASK)
81161 
81162 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_MASK (0x40U)
81163 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_SHIFT (6U)
81164 #define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_MASK)
81165 /*! @} */
81166 
81167 /*! @name TRSV_REG07E -  */
81168 /*! @{ */
81169 
81170 #define PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_MASK (0xFFU)
81171 #define PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_SHIFT (0U)
81172 #define PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_MASK)
81173 /*! @} */
81174 
81175 /*! @name TRSV_REG07F -  */
81176 /*! @{ */
81177 
81178 #define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_MASK (0x1U)
81179 #define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_SHIFT (0U)
81180 #define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_MASK)
81181 
81182 #define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_MASK (0x7EU)
81183 #define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_SHIFT (1U)
81184 #define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_MASK)
81185 /*! @} */
81186 
81187 /*! @name TRSV_REG080 -  */
81188 /*! @{ */
81189 
81190 #define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_MASK (0x1U)
81191 #define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_SHIFT (0U)
81192 #define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_MASK)
81193 
81194 #define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_MASK (0x3EU)
81195 #define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_SHIFT (1U)
81196 #define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_SHIFT)) & PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_MASK)
81197 /*! @} */
81198 
81199 /*! @name TRSV_REG081 -  */
81200 /*! @{ */
81201 
81202 #define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_MASK (0x1U)
81203 #define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_SHIFT (0U)
81204 #define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_MASK)
81205 
81206 #define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_MASK (0x3EU)
81207 #define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_SHIFT (1U)
81208 #define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_SHIFT)) & PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_MASK)
81209 /*! @} */
81210 
81211 /*! @name TRSV_REG082 -  */
81212 /*! @{ */
81213 
81214 #define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_MASK (0x1U)
81215 #define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_SHIFT (0U)
81216 #define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_MASK)
81217 
81218 #define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_MASK (0x1EU)
81219 #define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_SHIFT (1U)
81220 #define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_SHIFT)) & PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_MASK)
81221 /*! @} */
81222 
81223 /*! @name TRSV_REG083 -  */
81224 /*! @{ */
81225 
81226 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_MASK (0x3U)
81227 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_SHIFT (0U)
81228 /*! LN0_RX_SSLMS_C1_ADAP_SPEED - RX DFE SSLMS c1 adaptation speed selection */
81229 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_SHIFT)) & PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_MASK)
81230 
81231 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_MASK (0xCU)
81232 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_SHIFT (2U)
81233 /*! LN0_RX_SSLMS_C0_ADAP_SPEED - RX DFE SSLMS c0 adaptation speed selection */
81234 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_SHIFT)) & PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_MASK)
81235 
81236 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_MASK (0xF0U)
81237 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_SHIFT (4U)
81238 #define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_SHIFT)) & PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_MASK)
81239 /*! @} */
81240 
81241 /*! @name TRSV_REG084 -  */
81242 /*! @{ */
81243 
81244 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_MASK (0x3U)
81245 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_SHIFT (0U)
81246 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_MASK)
81247 
81248 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_MASK (0xCU)
81249 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_SHIFT (2U)
81250 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_MASK)
81251 
81252 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_MASK (0x30U)
81253 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_SHIFT (4U)
81254 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_MASK)
81255 
81256 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_MASK (0xC0U)
81257 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_SHIFT (6U)
81258 /*! LN0_RX_SSLMS_C2_ADAP_SPEED - RX DFE SSLMS c2 adaptation speed selection */
81259 #define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_MASK)
81260 /*! @} */
81261 
81262 /*! @name TRSV_REG085 -  */
81263 /*! @{ */
81264 
81265 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_MASK (0x3U)
81266 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_SHIFT (0U)
81267 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_SHIFT)) & PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_MASK)
81268 
81269 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_MASK (0xCU)
81270 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_SHIFT (2U)
81271 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_SHIFT)) & PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_MASK)
81272 
81273 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_MASK (0x10U)
81274 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_SHIFT (4U)
81275 #define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_SHIFT)) & PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_MASK)
81276 /*! @} */
81277 
81278 /*! @name TRSV_REG086 -  */
81279 /*! @{ */
81280 
81281 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_MASK (0x1U)
81282 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_SHIFT (0U)
81283 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_SHIFT)) & PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_MASK)
81284 
81285 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_MASK (0x2U)
81286 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_SHIFT (1U)
81287 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_SHIFT)) & PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_MASK)
81288 
81289 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_MASK (0xFCU)
81290 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_SHIFT (2U)
81291 #define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_SHIFT)) & PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_MASK)
81292 /*! @} */
81293 
81294 /*! @name TRSV_REG087 -  */
81295 /*! @{ */
81296 
81297 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_MASK (0x1U)
81298 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_SHIFT (0U)
81299 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_MASK)
81300 
81301 #define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_MASK (0x2U)
81302 #define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SHIFT (1U)
81303 /*! LN0_OVRD_RX_SSLMS_ADAP_HOLD - Override enable for rx_sslms_adap_hold */
81304 #define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_MASK)
81305 
81306 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_MASK (0x4U)
81307 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_SHIFT (2U)
81308 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_MASK)
81309 
81310 #define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_MASK (0x8U)
81311 #define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_SHIFT (3U)
81312 /*! LN0_OVRD_RX_SSLMS_ADAP_EN - Override enable for rx_sslms_adap_en */
81313 #define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_MASK)
81314 
81315 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_MASK (0x10U)
81316 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_SHIFT (4U)
81317 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_MASK)
81318 
81319 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_MASK (0x20U)
81320 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_SHIFT (5U)
81321 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_MASK)
81322 
81323 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_MASK (0xC0U)
81324 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_SHIFT (6U)
81325 #define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_MASK)
81326 /*! @} */
81327 
81328 /*! @name TRSV_REG088 -  */
81329 /*! @{ */
81330 
81331 #define PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_MASK (0x1U)
81332 #define PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_SHIFT (0U)
81333 #define PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_SHIFT)) & PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_MASK)
81334 /*! @} */
81335 
81336 /*! @name TRSV_REG089 -  */
81337 /*! @{ */
81338 
81339 #define PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_MASK (0xFFU)
81340 #define PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_SHIFT (0U)
81341 #define PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_SHIFT)) & PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_MASK)
81342 /*! @} */
81343 
81344 /*! @name TRSV_REG08A -  */
81345 /*! @{ */
81346 
81347 #define PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_MASK (0x1U)
81348 #define PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_SHIFT (0U)
81349 #define PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_SHIFT)) & PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_MASK)
81350 /*! @} */
81351 
81352 /*! @name TRSV_REG08B -  */
81353 /*! @{ */
81354 
81355 #define PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_MASK (0xFFU)
81356 #define PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_SHIFT (0U)
81357 #define PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_SHIFT)) & PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_MASK)
81358 /*! @} */
81359 
81360 /*! @name TRSV_REG08C -  */
81361 /*! @{ */
81362 
81363 #define PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_MASK (0x1U)
81364 #define PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_SHIFT (0U)
81365 #define PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_SHIFT)) & PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_MASK)
81366 /*! @} */
81367 
81368 /*! @name TRSV_REG08D -  */
81369 /*! @{ */
81370 
81371 #define PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_MASK (0xFFU)
81372 #define PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_SHIFT (0U)
81373 #define PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_SHIFT)) & PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_MASK)
81374 /*! @} */
81375 
81376 /*! @name TRSV_REG08E -  */
81377 /*! @{ */
81378 
81379 #define PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_MASK (0x1U)
81380 #define PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_SHIFT (0U)
81381 #define PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_SHIFT)) & PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_MASK)
81382 /*! @} */
81383 
81384 /*! @name TRSV_REG08F -  */
81385 /*! @{ */
81386 
81387 #define PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_MASK (0xFFU)
81388 #define PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_SHIFT (0U)
81389 #define PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_SHIFT)) & PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_MASK)
81390 /*! @} */
81391 
81392 /*! @name TRSV_REG090 -  */
81393 /*! @{ */
81394 
81395 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_MASK (0xFU)
81396 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_SHIFT (0U)
81397 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_MASK)
81398 
81399 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_MASK (0x10U)
81400 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_SHIFT (4U)
81401 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_MASK)
81402 
81403 #define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_MASK (0x20U)
81404 #define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_SHIFT (5U)
81405 /*! LN0_OVRD_RX_CDR_AFC_INIT_RSTN - Override enable for rx_cdr_afc_init_rstn */
81406 #define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_MASK)
81407 
81408 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_MASK (0x40U)
81409 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_SHIFT (6U)
81410 #define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_MASK)
81411 
81412 #define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_MASK (0x80U)
81413 #define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_SHIFT (7U)
81414 /*! LN0_OVRD_RX_CDR_AFC_RSTN - Override enable for rx_cdr_afc_rstn */
81415 #define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_MASK)
81416 /*! @} */
81417 
81418 /*! @name TRSV_REG091 -  */
81419 /*! @{ */
81420 
81421 #define PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_MASK (0xFU)
81422 #define PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_SHIFT (0U)
81423 #define PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_SHIFT)) & PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_MASK)
81424 /*! @} */
81425 
81426 /*! @name TRSV_REG092 -  */
81427 /*! @{ */
81428 
81429 #define PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_MASK (0x1FU)
81430 #define PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_SHIFT (0U)
81431 #define PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_MASK)
81432 /*! @} */
81433 
81434 /*! @name TRSV_REG093 -  */
81435 /*! @{ */
81436 
81437 #define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_MASK (0x1U)
81438 #define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_SHIFT (0U)
81439 #define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_SHIFT)) & PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_MASK)
81440 
81441 #define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_MASK (0x1EU)
81442 #define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_SHIFT (1U)
81443 #define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_SHIFT)) & PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_MASK)
81444 /*! @} */
81445 
81446 /*! @name TRSV_REG094 -  */
81447 /*! @{ */
81448 
81449 #define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_MASK (0x1U)
81450 #define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_SHIFT (0U)
81451 #define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_SHIFT)) & PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_MASK)
81452 
81453 #define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_MASK (0x1EU)
81454 #define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_SHIFT (1U)
81455 #define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_SHIFT)) & PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_MASK)
81456 /*! @} */
81457 
81458 /*! @name TRSV_REG095 -  */
81459 /*! @{ */
81460 
81461 #define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_MASK (0x1U)
81462 #define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_SHIFT (0U)
81463 #define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_SHIFT)) & PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_MASK)
81464 
81465 #define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_MASK (0x1EU)
81466 #define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_SHIFT (1U)
81467 #define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_SHIFT)) & PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_MASK)
81468 /*! @} */
81469 
81470 /*! @name TRSV_REG096 -  */
81471 /*! @{ */
81472 
81473 #define PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_MASK (0x3FU)
81474 #define PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SHIFT (0U)
81475 #define PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_MASK)
81476 /*! @} */
81477 
81478 /*! @name TRSV_REG097 -  */
81479 /*! @{ */
81480 
81481 #define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_MASK (0x1U)
81482 #define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_SHIFT (0U)
81483 #define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_SHIFT)) & PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_MASK)
81484 
81485 #define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_MASK (0x1EU)
81486 #define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SHIFT (1U)
81487 #define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SHIFT)) & PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_MASK)
81488 /*! @} */
81489 
81490 /*! @name TRSV_REG098 -  */
81491 /*! @{ */
81492 
81493 #define PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_MASK (0xFU)
81494 #define PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SHIFT (0U)
81495 #define PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SHIFT)) & PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_MASK)
81496 /*! @} */
81497 
81498 /*! @name TRSV_REG099 -  */
81499 /*! @{ */
81500 
81501 #define PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_MASK (0x3FU)
81502 #define PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_SHIFT (0U)
81503 /*! LN0_RX_CDR_FBB_DELTA_CNT - Target delta number in VCO counter in CDR FBB cal mode */
81504 #define PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_SHIFT)) & PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_MASK)
81505 /*! @} */
81506 
81507 /*! @name TRSV_REG09A -  */
81508 /*! @{ */
81509 
81510 #define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_MASK (0xFU)
81511 #define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_SHIFT (0U)
81512 /*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2 - [GEN2] */
81513 #define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_MASK)
81514 
81515 #define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_MASK (0xF0U)
81516 #define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_SHIFT (4U)
81517 /*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1 - [GEN1] RX CDR BBVCO FBB gain control in PLL mode */
81518 #define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_MASK)
81519 /*! @} */
81520 
81521 /*! @name TRSV_REG09B -  */
81522 /*! @{ */
81523 
81524 #define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_MASK (0xFU)
81525 #define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_SHIFT (0U)
81526 /*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4 - [GEN4] */
81527 #define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_MASK)
81528 
81529 #define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_MASK (0xF0U)
81530 #define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_SHIFT (4U)
81531 /*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3 - [GEN3] */
81532 #define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_MASK)
81533 /*! @} */
81534 
81535 /*! @name TRSV_REG09C -  */
81536 /*! @{ */
81537 
81538 #define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_MASK (0xFU)
81539 #define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_SHIFT (0U)
81540 /*! LN0_RX_CDR_FBB_COARSE_CTRL_G2 - [GEN2] */
81541 #define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_MASK)
81542 
81543 #define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_MASK (0xF0U)
81544 #define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_SHIFT (4U)
81545 /*! LN0_RX_CDR_FBB_COARSE_CTRL_G1 - [GEN1] RX CDR BBVCO FBB gain control in coarse mode (high bandwidth) */
81546 #define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_MASK)
81547 /*! @} */
81548 
81549 /*! @name TRSV_REG09D -  */
81550 /*! @{ */
81551 
81552 #define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_MASK (0xFU)
81553 #define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_SHIFT (0U)
81554 /*! LN0_RX_CDR_FBB_COARSE_CTRL_G4 - [GEN4] */
81555 #define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_MASK)
81556 
81557 #define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_MASK (0xF0U)
81558 #define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_SHIFT (4U)
81559 /*! LN0_RX_CDR_FBB_COARSE_CTRL_G3 - [GEN3] */
81560 #define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_MASK)
81561 /*! @} */
81562 
81563 /*! @name TRSV_REG09E -  */
81564 /*! @{ */
81565 
81566 #define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_MASK (0xFU)
81567 #define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_SHIFT (0U)
81568 /*! LN0_RX_CDR_FBB_FINE_CTRL_G2 - [GEN2] */
81569 #define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_MASK)
81570 
81571 #define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_MASK (0xF0U)
81572 #define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_SHIFT (4U)
81573 /*! LN0_RX_CDR_FBB_FINE_CTRL_G1 - [GEN1] RX CDR BBVCO FBB gain control in fine mode (low bandwidth) */
81574 #define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_MASK)
81575 /*! @} */
81576 
81577 /*! @name TRSV_REG09F -  */
81578 /*! @{ */
81579 
81580 #define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_MASK (0xFU)
81581 #define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_SHIFT (0U)
81582 /*! LN0_RX_CDR_FBB_FINE_CTRL_G4 - [GEN4] */
81583 #define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_MASK)
81584 
81585 #define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_MASK (0xF0U)
81586 #define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_SHIFT (4U)
81587 /*! LN0_RX_CDR_FBB_FINE_CTRL_G3 - [GEN3] */
81588 #define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_MASK)
81589 /*! @} */
81590 
81591 /*! @name TRSV_REG0A0 -  */
81592 /*! @{ */
81593 
81594 #define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_MASK (0xFU)
81595 #define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_SHIFT (0U)
81596 /*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G2 - [GEN4] */
81597 #define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_SHIFT)) & PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_MASK)
81598 
81599 #define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_MASK (0xF0U)
81600 #define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_SHIFT (4U)
81601 /*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G1 - [GEN4] */
81602 #define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_SHIFT)) & PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_MASK)
81603 /*! @} */
81604 
81605 /*! @name TRSV_REG0A1 -  */
81606 /*! @{ */
81607 
81608 #define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_MASK (0xFU)
81609 #define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_SHIFT (0U)
81610 /*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G4 - [GEN4] */
81611 #define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_SHIFT)) & PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_MASK)
81612 
81613 #define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_MASK (0xF0U)
81614 #define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_SHIFT (4U)
81615 /*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G3 - [GEN4] */
81616 #define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_SHIFT)) & PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_MASK)
81617 /*! @} */
81618 
81619 /*! @name TRSV_REG0A2 -  */
81620 /*! @{ */
81621 
81622 #define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_MASK (0xFU)
81623 #define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_SHIFT (0U)
81624 /*! LN0_RX_CDR_FBB_HI_BW_DIFF_G2 - [GEN4] */
81625 #define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_SHIFT)) & PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_MASK)
81626 
81627 #define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_MASK (0xF0U)
81628 #define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_SHIFT (4U)
81629 /*! LN0_RX_CDR_FBB_HI_BW_DIFF_G1 - [GEN4] */
81630 #define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_SHIFT)) & PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_MASK)
81631 /*! @} */
81632 
81633 /*! @name TRSV_REG0A3 -  */
81634 /*! @{ */
81635 
81636 #define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_MASK (0xFU)
81637 #define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_SHIFT (0U)
81638 /*! LN0_RX_CDR_FBB_HI_BW_DIFF_G4 - [GEN4] */
81639 #define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_SHIFT)) & PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_MASK)
81640 
81641 #define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_MASK (0xF0U)
81642 #define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_SHIFT (4U)
81643 /*! LN0_RX_CDR_FBB_HI_BW_DIFF_G3 - [GEN4] */
81644 #define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_SHIFT)) & PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_MASK)
81645 /*! @} */
81646 
81647 /*! @name TRSV_REG0A4 -  */
81648 /*! @{ */
81649 
81650 #define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_MASK (0xFU)
81651 #define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_SHIFT (0U)
81652 /*! LN0_RX_CDR_FBB_LO_BW_DIFF_G2 - [GEN4] */
81653 #define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_SHIFT)) & PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_MASK)
81654 
81655 #define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_MASK (0xF0U)
81656 #define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_SHIFT (4U)
81657 /*! LN0_RX_CDR_FBB_LO_BW_DIFF_G1 - [GEN4] */
81658 #define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_SHIFT)) & PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_MASK)
81659 /*! @} */
81660 
81661 /*! @name TRSV_REG0A5 -  */
81662 /*! @{ */
81663 
81664 #define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_MASK (0xFU)
81665 #define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_SHIFT (0U)
81666 /*! LN0_RX_CDR_FBB_LO_BW_DIFF_G4 - [GEN4] */
81667 #define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_SHIFT)) & PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_MASK)
81668 
81669 #define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_MASK (0xF0U)
81670 #define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_SHIFT (4U)
81671 /*! LN0_RX_CDR_FBB_LO_BW_DIFF_G3 - [GEN4] */
81672 #define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_SHIFT)) & PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_MASK)
81673 /*! @} */
81674 
81675 /*! @name TRSV_REG0A6 -  */
81676 /*! @{ */
81677 
81678 #define PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_MASK (0x1FU)
81679 #define PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_SHIFT (0U)
81680 #define PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_MASK)
81681 /*! @} */
81682 
81683 /*! @name TRSV_REG0A7 -  */
81684 /*! @{ */
81685 
81686 #define PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_MASK (0xFU)
81687 #define PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_SHIFT (0U)
81688 #define PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_SHIFT)) & PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_MASK)
81689 /*! @} */
81690 
81691 /*! @name TRSV_REG0A8 -  */
81692 /*! @{ */
81693 
81694 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_MASK (0x1U)
81695 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_SHIFT (0U)
81696 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_SHIFT)) & PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_MASK)
81697 
81698 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_MASK (0x2U)
81699 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_SHIFT (1U)
81700 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_MASK)
81701 
81702 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_MASK (0x7CU)
81703 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_SHIFT (2U)
81704 #define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_SHIFT)) & PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_MASK)
81705 /*! @} */
81706 
81707 /*! @name TRSV_REG0A9 -  */
81708 /*! @{ */
81709 
81710 #define PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_MASK (0x1FU)
81711 #define PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_SHIFT (0U)
81712 #define PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_MASK)
81713 /*! @} */
81714 
81715 /*! @name TRSV_REG0AA -  */
81716 /*! @{ */
81717 
81718 #define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_MASK (0x7U)
81719 #define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_SHIFT (0U)
81720 #define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_SHIFT)) & PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_MASK)
81721 
81722 #define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_MASK (0x78U)
81723 #define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_SHIFT (3U)
81724 #define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_SHIFT)) & PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_MASK)
81725 /*! @} */
81726 
81727 /*! @name TRSV_REG0AB -  */
81728 /*! @{ */
81729 
81730 #define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_MASK (0x1U)
81731 #define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_SHIFT (0U)
81732 #define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_MASK)
81733 
81734 #define PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_MASK (0x2U)
81735 #define PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_SHIFT (1U)
81736 /*! LN0_OVRD_RX_CDR_CAL_DONE - Override enable for rx_cdr_cal_done */
81737 #define PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_MASK)
81738 
81739 #define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_MASK (0x7CU)
81740 #define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_SHIFT (2U)
81741 #define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_SHIFT)) & PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_MASK)
81742 /*! @} */
81743 
81744 /*! @name TRSV_REG0AC -  */
81745 /*! @{ */
81746 
81747 #define PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_MASK (0xFFU)
81748 #define PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_SHIFT (0U)
81749 #define PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_SHIFT)) & PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_MASK)
81750 /*! @} */
81751 
81752 /*! @name TRSV_REG0AD -  */
81753 /*! @{ */
81754 
81755 #define PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_MASK (0xFFU)
81756 #define PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_SHIFT (0U)
81757 #define PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_SHIFT)) & PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_MASK)
81758 /*! @} */
81759 
81760 /*! @name TRSV_REG0AE -  */
81761 /*! @{ */
81762 
81763 #define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_MASK (0xFU)
81764 #define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_SHIFT (0U)
81765 #define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_MASK)
81766 
81767 #define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_MASK (0xF0U)
81768 #define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_SHIFT (4U)
81769 #define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_SHIFT)) & PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_MASK)
81770 /*! @} */
81771 
81772 /*! @name TRSV_REG0AF -  */
81773 /*! @{ */
81774 
81775 #define PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_MASK (0x1U)
81776 #define PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_SHIFT (0U)
81777 #define PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_SHIFT)) & PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_MASK)
81778 /*! @} */
81779 
81780 /*! @name TRSV_REG0B0 -  */
81781 /*! @{ */
81782 
81783 #define PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_MASK (0x1U)
81784 #define PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_SHIFT (0U)
81785 /*! LN0_OVRD_RX_EFOM_FEEDBACK - Override enable for */
81786 #define PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_SHIFT)) & PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_MASK)
81787 /*! @} */
81788 
81789 /*! @name TRSV_REG0B1 -  */
81790 /*! @{ */
81791 
81792 #define PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_MASK (0xFFU)
81793 #define PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_SHIFT (0U)
81794 #define PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_SHIFT)) & PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_MASK)
81795 /*! @} */
81796 
81797 /*! @name TRSV_REG0B2 -  */
81798 /*! @{ */
81799 
81800 #define PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_MASK (0xFFU)
81801 #define PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_SHIFT (0U)
81802 #define PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_MASK)
81803 /*! @} */
81804 
81805 /*! @name TRSV_REG0B3 -  */
81806 /*! @{ */
81807 
81808 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_MASK (0x1U)
81809 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_SHIFT (0U)
81810 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_MASK)
81811 
81812 #define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_MASK (0x2U)
81813 #define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_SHIFT (1U)
81814 /*! LN0_OVRD_RX_EFOM_START - Override enable for rx_efom_start */
81815 #define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_MASK)
81816 
81817 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_MASK (0x1CU)
81818 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_SHIFT (2U)
81819 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_MASK)
81820 
81821 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_MASK (0x20U)
81822 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_SHIFT (5U)
81823 #define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_MASK)
81824 
81825 #define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_MASK (0x40U)
81826 #define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_SHIFT (6U)
81827 /*! LN0_OVRD_RX_EFOM_DONE - Override enable for rx_efom_done */
81828 #define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_MASK)
81829 /*! @} */
81830 
81831 /*! @name TRSV_REG0B4 -  */
81832 /*! @{ */
81833 
81834 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_MASK (0x3U)
81835 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_SHIFT (0U)
81836 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_MASK)
81837 
81838 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_MASK (0xCU)
81839 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_SHIFT (2U)
81840 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_MASK)
81841 
81842 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_MASK (0x10U)
81843 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_SHIFT (4U)
81844 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_MASK)
81845 
81846 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_MASK (0xE0U)
81847 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_SHIFT (5U)
81848 #define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_MASK)
81849 /*! @} */
81850 
81851 /*! @name TRSV_REG0B5 -  */
81852 /*! @{ */
81853 
81854 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_MASK (0x1U)
81855 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_SHIFT (0U)
81856 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_MASK)
81857 
81858 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_MASK (0x2U)
81859 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_SHIFT (1U)
81860 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_MASK)
81861 
81862 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_MASK (0xCU)
81863 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_SHIFT (2U)
81864 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_MASK)
81865 
81866 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_MASK (0xF0U)
81867 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_SHIFT (4U)
81868 #define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_MASK)
81869 /*! @} */
81870 
81871 /*! @name TRSV_REG0B6 -  */
81872 /*! @{ */
81873 
81874 #define PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_MASK (0x3FU)
81875 #define PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_SHIFT (0U)
81876 #define PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_SHIFT)) & PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_MASK)
81877 /*! @} */
81878 
81879 /*! @name TRSV_REG0B7 -  */
81880 /*! @{ */
81881 
81882 #define PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_MASK (0xFFU)
81883 #define PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_SHIFT (0U)
81884 #define PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_MASK)
81885 /*! @} */
81886 
81887 /*! @name TRSV_REG0B8 -  */
81888 /*! @{ */
81889 
81890 #define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_MASK (0x1U)
81891 #define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_SHIFT (0U)
81892 #define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_MASK)
81893 
81894 #define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_MASK (0xEU)
81895 #define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_SHIFT (1U)
81896 #define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_MASK)
81897 /*! @} */
81898 
81899 /*! @name TRSV_REG0B9 -  */
81900 /*! @{ */
81901 
81902 #define PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_MASK (0xFFU)
81903 #define PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_SHIFT (0U)
81904 #define PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_MASK)
81905 /*! @} */
81906 
81907 /*! @name TRSV_REG0BA -  */
81908 /*! @{ */
81909 
81910 #define PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_MASK (0x7FU)
81911 #define PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_SHIFT (0U)
81912 #define PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_MASK)
81913 /*! @} */
81914 
81915 /*! @name TRSV_REG0BB -  */
81916 /*! @{ */
81917 
81918 #define PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_MASK (0x1U)
81919 #define PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_SHIFT (0U)
81920 #define PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_MASK)
81921 
81922 #define PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_MASK  (0x2U)
81923 #define PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_SHIFT (1U)
81924 #define PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_MASK)
81925 
81926 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_MASK (0x4U)
81927 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_SHIFT (2U)
81928 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_MASK)
81929 
81930 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_MASK (0x8U)
81931 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_SHIFT (3U)
81932 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_MASK)
81933 
81934 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_MASK (0x10U)
81935 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_SHIFT (4U)
81936 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_MASK)
81937 
81938 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_MASK (0x20U)
81939 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_SHIFT (5U)
81940 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_MASK)
81941 
81942 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_MASK (0x40U)
81943 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_SHIFT (6U)
81944 #define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_MASK)
81945 
81946 #define PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_MASK (0x80U)
81947 #define PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_SHIFT (7U)
81948 /*! LN0_OVRD_TXD_DESKEW_RSTN - Override enable for txd_deskew_rstn */
81949 #define PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_MASK)
81950 /*! @} */
81951 
81952 /*! @name TRSV_REG0BC -  */
81953 /*! @{ */
81954 
81955 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_MASK (0x1U)
81956 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_SHIFT (0U)
81957 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_MASK)
81958 
81959 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_MASK (0x1EU)
81960 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_SHIFT (1U)
81961 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_MASK)
81962 
81963 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_MASK (0x20U)
81964 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_SHIFT (5U)
81965 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_MASK)
81966 
81967 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_MASK (0x40U)
81968 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_SHIFT (6U)
81969 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_MASK)
81970 
81971 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_MASK (0x80U)
81972 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_SHIFT (7U)
81973 #define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_MASK)
81974 /*! @} */
81975 
81976 /*! @name TRSV_REG0BD -  */
81977 /*! @{ */
81978 
81979 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_MASK (0x3U)
81980 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_SHIFT (0U)
81981 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_MASK)
81982 
81983 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_MASK (0xCU)
81984 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_SHIFT (2U)
81985 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_MASK)
81986 
81987 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_MASK (0x10U)
81988 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_SHIFT (4U)
81989 #define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_MASK)
81990 
81991 #define PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_MASK (0x20U)
81992 #define PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_SHIFT (5U)
81993 /*! LN0_OVRD_TX_RCAL_RSTN - Override enable for tx_rcal_rstn */
81994 #define PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_MASK)
81995 
81996 #define PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_MASK (0x40U)
81997 #define PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_SHIFT (6U)
81998 #define PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_MASK)
81999 
82000 #define PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_MASK (0x80U)
82001 #define PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_SHIFT (7U)
82002 #define PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_MASK)
82003 /*! @} */
82004 
82005 /*! @name TRSV_REG0BE -  */
82006 /*! @{ */
82007 
82008 #define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_MASK (0xFU)
82009 #define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_SHIFT (0U)
82010 /*! LN0_TX_RCAL_DN_CODE - Termination down control bits. &lt;3&gt;bit is reserved bit., Default code= 011,Min code =000 and Max code is 111 */
82011 #define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_MASK)
82012 
82013 #define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_MASK (0xF0U)
82014 #define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_SHIFT (4U)
82015 /*! LN0_TX_RCAL_UP_CODE - Termination up control bits. &lt;3&gt; bit is reserved bit., Default code = 011,Min code =000 and Max code is 111 */
82016 #define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_MASK)
82017 /*! @} */
82018 
82019 /*! @name TRSV_REG0BF -  */
82020 /*! @{ */
82021 
82022 #define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_MASK (0x3U)
82023 #define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_SHIFT (0U)
82024 #define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_MASK)
82025 
82026 #define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_MASK (0x4U)
82027 #define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_SHIFT (2U)
82028 #define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_MASK)
82029 
82030 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_MASK (0x8U)
82031 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_SHIFT (3U)
82032 /*! LN0_OVRD_RX_RCAL_RSTN - Override enable for rx_rcal_rstn */
82033 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_MASK)
82034 
82035 #define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_MASK (0x10U)
82036 #define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_SHIFT (4U)
82037 /*! LN0_TX_RCAL_DONE - Monitoring for TX RCAL done */
82038 #define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_MASK)
82039 
82040 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_MASK (0x20U)
82041 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_SHIFT (5U)
82042 /*! LN0_OVRD_TX_RCAL_DONE - Override enable for tx_rcal_done */
82043 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_MASK)
82044 
82045 #define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_MASK (0x40U)
82046 #define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_SHIFT (6U)
82047 #define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_MASK)
82048 
82049 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_MASK (0x80U)
82050 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_SHIFT (7U)
82051 /*! LN0_OVRD_TX_RCAL_COMP_OUT - Override enable for tx_rcal_comp_out */
82052 #define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_MASK)
82053 /*! @} */
82054 
82055 /*! @name TRSV_REG0C0 -  */
82056 /*! @{ */
82057 
82058 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_MASK (0x1U)
82059 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_SHIFT (0U)
82060 /*! LN0_RX_RCAL_DONE - RX RCAL done */
82061 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_MASK)
82062 
82063 #define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_MASK (0x2U)
82064 #define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_SHIFT (1U)
82065 /*! LN0_OVRD_RX_RCAL_DONE - Override enable for rx_rcal_done */
82066 #define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_MASK)
82067 
82068 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_MASK (0x4U)
82069 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_SHIFT (2U)
82070 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_MASK)
82071 
82072 #define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_MASK (0x8U)
82073 #define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_SHIFT (3U)
82074 /*! LN0_OVRD_RX_RCAL_COMP_OUT - Override enable for rx_rcal_comp_out */
82075 #define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_MASK)
82076 
82077 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_MASK (0xF0U)
82078 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_SHIFT (4U)
82079 /*! LN0_RX_RTERM_CTRL - Termination Calibration will send control signals to make 42.5 ohms. MSB&lt;4&gt;=&gt;1'b0=50,1'b1=42.5(default). */
82080 #define PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_MASK)
82081 /*! @} */
82082 
82083 /*! @name TRSV_REG0C1 -  */
82084 /*! @{ */
82085 
82086 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_MASK (0x3U)
82087 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_SHIFT (0U)
82088 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_MASK)
82089 
82090 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_MASK (0x1CU)
82091 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_SHIFT (2U)
82092 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_MASK)
82093 
82094 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_MASK (0x60U)
82095 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_SHIFT (5U)
82096 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_MASK)
82097 
82098 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_MASK (0x80U)
82099 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_SHIFT (7U)
82100 #define PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_MASK)
82101 /*! @} */
82102 
82103 /*! @name TRSV_REG0C2 -  */
82104 /*! @{ */
82105 
82106 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_MASK (0x1U)
82107 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_SHIFT (0U)
82108 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_MASK)
82109 
82110 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_MASK (0x2U)
82111 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_SHIFT (1U)
82112 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_MASK)
82113 
82114 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_MASK (0x4U)
82115 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_SHIFT (2U)
82116 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_MASK)
82117 
82118 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_MASK (0x8U)
82119 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_SHIFT (3U)
82120 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_MASK)
82121 
82122 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_MASK (0x10U)
82123 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_SHIFT (4U)
82124 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_MASK)
82125 
82126 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_MASK (0x20U)
82127 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_SHIFT (5U)
82128 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN(x)   (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_MASK)
82129 
82130 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_MASK (0x40U)
82131 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_SHIFT (6U)
82132 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_MASK)
82133 
82134 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_MASK    (0x80U)
82135 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_SHIFT   (7U)
82136 #define PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN(x)      (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_MASK)
82137 /*! @} */
82138 
82139 /*! @name TRSV_REG0C3 -  */
82140 /*! @{ */
82141 
82142 #define PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_MASK (0x1U)
82143 #define PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_SHIFT (0U)
82144 #define PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_MASK)
82145 /*! @} */
82146 
82147 /*! @name TRSV_REG0C4 -  */
82148 /*! @{ */
82149 
82150 #define PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_MASK (0xFFU)
82151 #define PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_SHIFT (0U)
82152 #define PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_SHIFT)) & PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_MASK)
82153 /*! @} */
82154 
82155 /*! @name TRSV_REG0C5 -  */
82156 /*! @{ */
82157 
82158 #define PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_MASK (0xFFU)
82159 #define PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_SHIFT (0U)
82160 #define PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_SHIFT)) & PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_MASK)
82161 /*! @} */
82162 
82163 /*! @name TRSV_REG0C6 -  */
82164 /*! @{ */
82165 
82166 #define PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_MASK (0xFFU)
82167 #define PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_SHIFT (0U)
82168 #define PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_SHIFT)) & PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_MASK)
82169 /*! @} */
82170 
82171 /*! @name TRSV_REG0C7 -  */
82172 /*! @{ */
82173 
82174 #define PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_MASK (0xFFU)
82175 #define PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_SHIFT (0U)
82176 #define PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_SHIFT)) & PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_MASK)
82177 /*! @} */
82178 
82179 /*! @name TRSV_REG0C8 -  */
82180 /*! @{ */
82181 
82182 #define PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_MASK (0xFFU)
82183 #define PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_SHIFT (0U)
82184 #define PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_SHIFT)) & PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_MASK)
82185 /*! @} */
82186 
82187 /*! @name TRSV_REG0C9 -  */
82188 /*! @{ */
82189 
82190 #define PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_MASK (0xFFU)
82191 #define PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_SHIFT (0U)
82192 #define PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_SHIFT)) & PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_MASK)
82193 /*! @} */
82194 
82195 /*! @name TRSV_REG0CA -  */
82196 /*! @{ */
82197 
82198 #define PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_MASK (0xFFU)
82199 #define PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_SHIFT (0U)
82200 #define PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_SHIFT)) & PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_MASK)
82201 /*! @} */
82202 
82203 /*! @name TRSV_REG0CB -  */
82204 /*! @{ */
82205 
82206 #define PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_MASK (0xFFU)
82207 #define PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_SHIFT (0U)
82208 #define PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_SHIFT)) & PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_MASK)
82209 /*! @} */
82210 
82211 /*! @name TRSV_REG0CC -  */
82212 /*! @{ */
82213 
82214 #define PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_MASK (0xFFU)
82215 #define PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_SHIFT (0U)
82216 #define PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_SHIFT)) & PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_MASK)
82217 /*! @} */
82218 
82219 /*! @name TRSV_REG0CD -  */
82220 /*! @{ */
82221 
82222 #define PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_MASK (0xFFU)
82223 #define PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_SHIFT (0U)
82224 #define PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_MASK)
82225 /*! @} */
82226 
82227 /*! @name TRSV_REG0CE -  */
82228 /*! @{ */
82229 
82230 #define PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_MASK  (0x1U)
82231 #define PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_SHIFT (0U)
82232 /*! LN0_LANE_MODE - Lane operation mode */
82233 #define PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_SHIFT)) & PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_MASK)
82234 
82235 #define PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_MASK (0xEU)
82236 #define PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_SHIFT (1U)
82237 #define PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_MASK)
82238 
82239 #define PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_MASK (0x30U)
82240 #define PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_SHIFT (4U)
82241 #define PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_SHIFT)) & PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_MASK)
82242 /*! @} */
82243 
82244 /*! @name TRSV_REG0CF -  */
82245 /*! @{ */
82246 
82247 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_MASK (0x1U)
82248 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_SHIFT (0U)
82249 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_MASK)
82250 
82251 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_MASK (0x2U)
82252 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_SHIFT (1U)
82253 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_MASK)
82254 
82255 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_MASK (0x4U)
82256 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_SHIFT (2U)
82257 #define PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_MASK)
82258 
82259 #define PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_MASK (0x8U)
82260 #define PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_SHIFT (3U)
82261 #define PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_MASK)
82262 
82263 #define PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_MASK  (0x30U)
82264 #define PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_SHIFT (4U)
82265 #define PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE(x)    (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_MASK)
82266 
82267 #define PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_MASK (0x40U)
82268 #define PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_SHIFT (6U)
82269 /*! LN0_OVRD_LANE_RATE - Override enable for lane_rate */
82270 #define PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_MASK)
82271 /*! @} */
82272 
82273 /*! @name TRSV_REG0D0 -  */
82274 /*! @{ */
82275 
82276 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_MASK (0x1U)
82277 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_SHIFT (0U)
82278 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_MASK)
82279 
82280 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_MASK (0x2U)
82281 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_SHIFT (1U)
82282 /*! LN0_OVRD_MISC_TX_RXD_DETECTED - Override enable for misc_tx_rxd_detected */
82283 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_MASK)
82284 
82285 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_MASK (0x4U)
82286 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_SHIFT (2U)
82287 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_MASK)
82288 
82289 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_MASK (0x8U)
82290 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_SHIFT (3U)
82291 /*! LN0_OVRD_MISC_RX_LFPS_DET - Override enable for misc_rx_lfps_det */
82292 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_MASK)
82293 
82294 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_MASK (0x10U)
82295 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_SHIFT (4U)
82296 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_MASK)
82297 
82298 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_MASK (0x20U)
82299 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_SHIFT (5U)
82300 #define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_MASK)
82301 
82302 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_MASK (0x40U)
82303 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_SHIFT (6U)
82304 /*! LN0_OVRD_MISC_RX_SQHS_SIGVAL - Override enable for misc_rx_sqhs_sigval */
82305 #define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_MASK)
82306 /*! @} */
82307 
82308 /*! @name TRSV_REG0D1 -  */
82309 /*! @{ */
82310 
82311 #define PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_MASK (0x7U)
82312 #define PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_SHIFT (0U)
82313 /*! LN0_TG_RCAL_RSTN_DELAY_TIME - Rx Rcal reset delay time after PLL AFC done */
82314 #define PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_MASK)
82315 
82316 #define PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_MASK (0x38U)
82317 #define PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_SHIFT (3U)
82318 /*! LN0_TG_CDR_BW_CTRL_DELAY_TIME - RX CDR bandwidth change time control */
82319 #define PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_MASK)
82320 
82321 #define PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_MASK (0x40U)
82322 #define PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_SHIFT (6U)
82323 #define PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_MASK)
82324 
82325 #define PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_MASK (0x80U)
82326 #define PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_SHIFT (7U)
82327 /*! LN0_OVRD_MISC_RX_VALID_RSTN - Override enable for misc_rx_valid_rstn */
82328 #define PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_MASK)
82329 /*! @} */
82330 
82331 /*! @name TRSV_REG0D2 -  */
82332 /*! @{ */
82333 
82334 #define PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_MASK (0x3U)
82335 #define PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_SHIFT (0U)
82336 #define PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_MASK)
82337 /*! @} */
82338 
82339 /*! @name TRSV_REG0D3 -  */
82340 /*! @{ */
82341 
82342 #define PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_MASK (0xFU)
82343 #define PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_SHIFT (0U)
82344 #define PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_SHIFT)) & PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_MASK)
82345 
82346 #define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_MASK (0x10U)
82347 #define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_SHIFT (4U)
82348 /*! LN0_ANA_RX_SQLS_DIFP_DET - DIFP Detection signal */
82349 #define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_MASK)
82350 
82351 #define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_MASK (0x20U)
82352 #define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_SHIFT (5U)
82353 /*! LN0_ANA_RX_SQLS_DIFN_DET - DIFN Detection signal */
82354 #define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_MASK)
82355 /*! @} */
82356 
82357 /*! @name TRSV_REG0D4 -  */
82358 /*! @{ */
82359 
82360 #define PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_MASK (0xFU)
82361 #define PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_SHIFT (0U)
82362 #define PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_SHIFT)) & PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_MASK)
82363 /*! @} */
82364 
82365 /*! @name TRSV_REG0D5 -  */
82366 /*! @{ */
82367 
82368 #define PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_MASK (0x7FU)
82369 #define PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_SHIFT (0U)
82370 #define PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_SHIFT)) & PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_MASK)
82371 /*! @} */
82372 
82373 /*! @name TRSV_REG0D6 -  */
82374 /*! @{ */
82375 
82376 #define PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_MASK (0xFFU)
82377 #define PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_SHIFT (0U)
82378 #define PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_MASK)
82379 /*! @} */
82380 
82381 /*! @name TRSV_REG0D7 -  */
82382 /*! @{ */
82383 
82384 #define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_MASK (0xFU)
82385 #define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_SHIFT (0U)
82386 #define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_MASK)
82387 
82388 #define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_MASK (0xF0U)
82389 #define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_SHIFT (4U)
82390 #define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_SHIFT)) & PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_MASK)
82391 /*! @} */
82392 
82393 /*! @name TRSV_REG0D8 -  */
82394 /*! @{ */
82395 
82396 #define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_MASK (0xFU)
82397 #define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_SHIFT (0U)
82398 #define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_MASK)
82399 
82400 #define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_MASK (0xF0U)
82401 #define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_SHIFT (4U)
82402 #define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_MASK)
82403 /*! @} */
82404 
82405 /*! @name TRSV_REG0D9 -  */
82406 /*! @{ */
82407 
82408 #define PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_MASK (0x3U)
82409 #define PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_SHIFT (0U)
82410 #define PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_MASK)
82411 /*! @} */
82412 
82413 /*! @name TRSV_REG0DA -  */
82414 /*! @{ */
82415 
82416 #define PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_MASK (0x7FU)
82417 #define PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_SHIFT (0U)
82418 #define PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_MASK)
82419 /*! @} */
82420 
82421 /*! @name TRSV_REG0DB -  */
82422 /*! @{ */
82423 
82424 #define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_MASK (0x1U)
82425 #define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_SHIFT (0U)
82426 #define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_MASK)
82427 
82428 #define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_MASK (0xFEU)
82429 #define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_SHIFT (1U)
82430 #define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_MASK)
82431 /*! @} */
82432 
82433 /*! @name TRSV_REG0DC -  */
82434 /*! @{ */
82435 
82436 #define PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_MASK (0x1U)
82437 #define PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_SHIFT (0U)
82438 #define PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_MASK)
82439 /*! @} */
82440 
82441 /*! @name TRSV_REG0DD -  */
82442 /*! @{ */
82443 
82444 #define PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_MASK (0x1U)
82445 #define PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_SHIFT (0U)
82446 #define PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_SHIFT)) & PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_MASK)
82447 /*! @} */
82448 
82449 /*! @name TRSV_REG0DE -  */
82450 /*! @{ */
82451 
82452 #define PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_MASK (0xFFU)
82453 #define PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_SHIFT (0U)
82454 #define PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_MASK)
82455 /*! @} */
82456 
82457 /*! @name TRSV_REG0DF -  */
82458 /*! @{ */
82459 
82460 #define PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_MASK (0x1U)
82461 #define PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_SHIFT (0U)
82462 #define PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_SHIFT)) & PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_MASK)
82463 /*! @} */
82464 
82465 /*! @name TRSV_REG0E0 -  */
82466 /*! @{ */
82467 
82468 #define PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_MASK (0xFFU)
82469 #define PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_SHIFT (0U)
82470 #define PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_MASK)
82471 /*! @} */
82472 
82473 /*! @name TRSV_REG0E1 -  */
82474 /*! @{ */
82475 
82476 #define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_MASK (0x7U)
82477 #define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_SHIFT (0U)
82478 #define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_MASK)
82479 
82480 #define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_MASK (0x38U)
82481 #define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_SHIFT (3U)
82482 #define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_MASK)
82483 /*! @} */
82484 
82485 /*! @name TRSV_REG0E2 -  */
82486 /*! @{ */
82487 
82488 #define PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_MASK (0x1U)
82489 #define PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_SHIFT (0U)
82490 #define PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_SHIFT)) & PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_MASK)
82491 /*! @} */
82492 
82493 /*! @name TRSV_REG0E3 -  */
82494 /*! @{ */
82495 
82496 #define PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_MASK (0xFFU)
82497 #define PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_SHIFT (0U)
82498 #define PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_MASK)
82499 /*! @} */
82500 
82501 /*! @name TRSV_REG0E4 -  */
82502 /*! @{ */
82503 
82504 #define PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_MASK (0x1U)
82505 #define PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_SHIFT (0U)
82506 #define PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_SHIFT)) & PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_MASK)
82507 /*! @} */
82508 
82509 /*! @name TRSV_REG0E5 -  */
82510 /*! @{ */
82511 
82512 #define PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_MASK (0xFFU)
82513 #define PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_SHIFT (0U)
82514 #define PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_MASK)
82515 /*! @} */
82516 
82517 /*! @name TRSV_REG0E6 -  */
82518 /*! @{ */
82519 
82520 #define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_MASK (0x7U)
82521 #define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_SHIFT (0U)
82522 #define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_MASK)
82523 
82524 #define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_MASK (0x38U)
82525 #define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_SHIFT (3U)
82526 #define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_MASK)
82527 /*! @} */
82528 
82529 /*! @name TRSV_REG0E7 -  */
82530 /*! @{ */
82531 
82532 #define PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_MASK (0x7FU)
82533 #define PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_SHIFT (0U)
82534 #define PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_SHIFT)) & PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_MASK)
82535 /*! @} */
82536 
82537 /*! @name TRSV_REG0E8 -  */
82538 /*! @{ */
82539 
82540 #define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_MASK (0xFU)
82541 #define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_SHIFT (0U)
82542 #define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_SHIFT)) & PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_MASK)
82543 
82544 #define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_MASK (0xF0U)
82545 #define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_SHIFT (4U)
82546 #define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_SHIFT)) & PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_MASK)
82547 /*! @} */
82548 
82549 /*! @name TRSV_REG0E9 -  */
82550 /*! @{ */
82551 
82552 #define PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_MASK (0x1U)
82553 #define PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_SHIFT (0U)
82554 #define PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_MASK)
82555 /*! @} */
82556 
82557 /*! @name TRSV_REG0EA -  */
82558 /*! @{ */
82559 
82560 #define PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_MASK (0x3U)
82561 #define PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_SHIFT (0U)
82562 #define PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_SHIFT)) & PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_MASK)
82563 /*! @} */
82564 
82565 /*! @name TRSV_REG0EB -  */
82566 /*! @{ */
82567 
82568 #define PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_MASK (0xFFU)
82569 #define PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_SHIFT (0U)
82570 #define PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_MASK)
82571 /*! @} */
82572 
82573 /*! @name TRSV_REG0EC -  */
82574 /*! @{ */
82575 
82576 #define PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_MASK (0x1U)
82577 #define PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_SHIFT (0U)
82578 #define PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_SHIFT)) & PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_MASK)
82579 /*! @} */
82580 
82581 /*! @name TRSV_REG0ED -  */
82582 /*! @{ */
82583 
82584 #define PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_MASK (0xFFU)
82585 #define PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_SHIFT (0U)
82586 #define PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_MASK)
82587 /*! @} */
82588 
82589 /*! @name TRSV_REG0EE -  */
82590 /*! @{ */
82591 
82592 #define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_MASK (0x1U)
82593 #define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_SHIFT (0U)
82594 #define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_MASK)
82595 
82596 #define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_MASK (0xFEU)
82597 #define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_SHIFT (1U)
82598 #define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_SHIFT)) & PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_MASK)
82599 /*! @} */
82600 
82601 /*! @name TRSV_REG0EF -  */
82602 /*! @{ */
82603 
82604 #define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_MASK (0x1U)
82605 #define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_SHIFT (0U)
82606 #define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_MASK)
82607 
82608 #define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_MASK (0x3EU)
82609 #define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_SHIFT (1U)
82610 #define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_SHIFT)) & PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_MASK)
82611 /*! @} */
82612 
82613 /*! @name TRSV_REG0F0 -  */
82614 /*! @{ */
82615 
82616 #define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_MASK (0x1U)
82617 #define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_SHIFT (0U)
82618 #define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_MASK)
82619 
82620 #define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_MASK (0x3EU)
82621 #define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_SHIFT (1U)
82622 #define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_SHIFT)) & PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_MASK)
82623 /*! @} */
82624 
82625 /*! @name TRSV_REG0F1 -  */
82626 /*! @{ */
82627 
82628 #define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_MASK (0x1U)
82629 #define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_SHIFT (0U)
82630 #define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_MASK)
82631 
82632 #define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_MASK (0x1EU)
82633 #define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_SHIFT (1U)
82634 #define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_SHIFT)) & PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_MASK)
82635 /*! @} */
82636 
82637 /*! @name TRSV_REG0F2 -  */
82638 /*! @{ */
82639 
82640 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_MASK (0x1U)
82641 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_SHIFT (0U)
82642 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_MASK)
82643 
82644 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_MASK (0x2U)
82645 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_SHIFT (1U)
82646 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_MASK)
82647 
82648 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_MASK (0x3CU)
82649 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_SHIFT (2U)
82650 #define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_SHIFT)) & PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_MASK)
82651 /*! @} */
82652 
82653 /*! @name TRSV_REG0F3 -  */
82654 /*! @{ */
82655 
82656 #define PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_MASK (0x3FU)
82657 #define PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_SHIFT (0U)
82658 #define PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_SHIFT)) & PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_MASK)
82659 /*! @} */
82660 
82661 /*! @name TRSV_REG0F4 -  */
82662 /*! @{ */
82663 
82664 #define PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_MASK (0xFFU)
82665 #define PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_SHIFT (0U)
82666 #define PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_MASK)
82667 /*! @} */
82668 
82669 /*! @name TRSV_REG0F5 -  */
82670 /*! @{ */
82671 
82672 #define PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_MASK (0xFFU)
82673 #define PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_SHIFT (0U)
82674 #define PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_SHIFT)) & PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_MASK)
82675 /*! @} */
82676 
82677 /*! @name TRSV_REG0F6 -  */
82678 /*! @{ */
82679 
82680 #define PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_MASK (0xFFU)
82681 #define PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_SHIFT (0U)
82682 #define PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_MASK)
82683 /*! @} */
82684 
82685 /*! @name TRSV_REG0F7 -  */
82686 /*! @{ */
82687 
82688 #define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_MASK (0x1U)
82689 #define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_SHIFT (0U)
82690 #define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_MASK)
82691 
82692 #define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_MASK (0x1EU)
82693 #define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_SHIFT (1U)
82694 #define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_MASK)
82695 /*! @} */
82696 
82697 /*! @name TRSV_REG0F8 -  */
82698 /*! @{ */
82699 
82700 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_MASK (0x1U)
82701 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_SHIFT (0U)
82702 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_MASK)
82703 
82704 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_MASK (0x2U)
82705 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_SHIFT (1U)
82706 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_MASK)
82707 
82708 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_MASK (0x4U)
82709 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_SHIFT (2U)
82710 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_MASK)
82711 
82712 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_MASK (0x8U)
82713 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_SHIFT (3U)
82714 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_MASK)
82715 
82716 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_MASK (0xF0U)
82717 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_SHIFT (4U)
82718 #define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_MASK)
82719 /*! @} */
82720 
82721 /*! @name TRSV_REG0F9 -  */
82722 /*! @{ */
82723 
82724 #define PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_MASK (0xFU)
82725 #define PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_SHIFT (0U)
82726 #define PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_MASK)
82727 /*! @} */
82728 
82729 /*! @name TRSV_REG0FA -  */
82730 /*! @{ */
82731 
82732 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_MASK (0x1U)
82733 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_SHIFT (0U)
82734 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_MASK)
82735 
82736 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_MASK (0x2U)
82737 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_SHIFT (1U)
82738 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_MASK)
82739 
82740 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_MASK (0x4U)
82741 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_SHIFT (2U)
82742 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_MASK)
82743 
82744 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_MASK (0x8U)
82745 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_SHIFT (3U)
82746 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_MASK)
82747 
82748 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_MASK (0x10U)
82749 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_SHIFT (4U)
82750 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_MASK)
82751 
82752 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_MASK (0x20U)
82753 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_SHIFT (5U)
82754 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_MASK)
82755 
82756 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_MASK (0x40U)
82757 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_SHIFT (6U)
82758 #define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_MASK)
82759 /*! @} */
82760 
82761 /*! @name TRSV_REG0FB -  */
82762 /*! @{ */
82763 
82764 #define PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_MASK (0xFFU)
82765 #define PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_SHIFT (0U)
82766 #define PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_SHIFT)) & PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_MASK)
82767 /*! @} */
82768 
82769 /*! @name TRSV_REG0FC -  */
82770 /*! @{ */
82771 
82772 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_MASK (0x7U)
82773 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_SHIFT (0U)
82774 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_MASK)
82775 
82776 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_MASK (0x8U)
82777 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_SHIFT (3U)
82778 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_MASK)
82779 
82780 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_MASK (0x70U)
82781 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_SHIFT (4U)
82782 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_MASK)
82783 
82784 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_MASK (0x80U)
82785 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_SHIFT (7U)
82786 #define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_MASK)
82787 /*! @} */
82788 
82789 /*! @name TRSV_REG0FD -  */
82790 /*! @{ */
82791 
82792 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_MASK (0x7U)
82793 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_SHIFT (0U)
82794 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_MASK)
82795 
82796 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_MASK (0x8U)
82797 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_SHIFT (3U)
82798 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_MASK)
82799 
82800 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_MASK (0x70U)
82801 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_SHIFT (4U)
82802 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_MASK)
82803 
82804 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_MASK (0x80U)
82805 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_SHIFT (7U)
82806 #define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_MASK)
82807 /*! @} */
82808 
82809 /*! @name TRSV_REG0FE -  */
82810 /*! @{ */
82811 
82812 #define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_MASK (0x7U)
82813 #define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_SHIFT (0U)
82814 #define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_MASK)
82815 
82816 #define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_MASK (0x70U)
82817 #define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_SHIFT (4U)
82818 #define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_MASK)
82819 /*! @} */
82820 
82821 /*! @name TRSV_REG0FF -  */
82822 /*! @{ */
82823 
82824 #define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_MASK (0x7U)
82825 #define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_SHIFT (0U)
82826 #define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_MASK)
82827 
82828 #define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_MASK (0x70U)
82829 #define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_SHIFT (4U)
82830 #define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_MASK)
82831 /*! @} */
82832 
82833 
82834 /*!
82835  * @}
82836  */ /* end of group PCIE_PHY_Register_Masks */
82837 
82838 
82839 /* PCIE_PHY - Peripheral instance base addresses */
82840 /** Peripheral PCIE_PHY base address */
82841 #define PCIE_PHY_BASE                            (0x32F00000u)
82842 /** Peripheral PCIE_PHY base pointer */
82843 #define PCIE_PHY                                 ((PCIE_PHY_Type *)PCIE_PHY_BASE)
82844 /** Array initializer of PCIE_PHY peripheral base addresses */
82845 #define PCIE_PHY_BASE_ADDRS                      { PCIE_PHY_BASE }
82846 /** Array initializer of PCIE_PHY peripheral base pointers */
82847 #define PCIE_PHY_BASE_PTRS                       { PCIE_PHY }
82848 
82849 /*!
82850  * @}
82851  */ /* end of group PCIE_PHY_Peripheral_Access_Layer */
82852 
82853 
82854 /* ----------------------------------------------------------------------------
82855    -- PDM Peripheral Access Layer
82856    ---------------------------------------------------------------------------- */
82857 
82858 /*!
82859  * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
82860  * @{
82861  */
82862 
82863 /** PDM - Register Layout Typedef */
82864 typedef struct {
82865   __IO uint32_t CTRL_1;                            /**< MICFIL Control register 1, offset: 0x0 */
82866   __IO uint32_t CTRL_2;                            /**< MICFIL Control register 2, offset: 0x4 */
82867   __IO uint32_t STAT;                              /**< MICFIL Status register, offset: 0x8 */
82868        uint8_t RESERVED_0[4];
82869   __IO uint32_t FIFO_CTRL;                         /**< MICFIL FIFO Control register, offset: 0x10 */
82870   __IO uint32_t FIFO_STAT;                         /**< MICFIL FIFO Status register, offset: 0x14 */
82871        uint8_t RESERVED_1[12];
82872   __I  uint32_t DATACH[8];                         /**< MICFIL Output Result Register, array offset: 0x24, array step: 0x4 */
82873        uint8_t RESERVED_2[32];
82874   __IO uint32_t DC_CTRL;                           /**< MICFIL DC Remover Control register, offset: 0x64 */
82875        uint8_t RESERVED_3[12];
82876   __IO uint32_t RANGE_CTRL;                        /**< MICFIL Range Control register, offset: 0x74 */
82877        uint8_t RESERVED_4[4];
82878   __IO uint32_t RANGE_STAT;                        /**< MICFIL Range Status register, offset: 0x7C */
82879        uint8_t RESERVED_5[16];
82880   __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector Control register, offset: 0x90 */
82881   __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector Control register, offset: 0x94 */
82882   __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector Status register, offset: 0x98 */
82883   __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector Signal Configuration, offset: 0x9C */
82884   __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector Noise Configuration, offset: 0xA0 */
82885   __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector Noise Data, offset: 0xA4 */
82886   __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector Zero-Crossing Detector, offset: 0xA8 */
82887 } PDM_Type;
82888 
82889 /* ----------------------------------------------------------------------------
82890    -- PDM Register Masks
82891    ---------------------------------------------------------------------------- */
82892 
82893 /*!
82894  * @addtogroup PDM_Register_Masks PDM Register Masks
82895  * @{
82896  */
82897 
82898 /*! @name CTRL_1 - MICFIL Control register 1 */
82899 /*! @{ */
82900 
82901 #define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
82902 #define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
82903 /*! CH0EN - Channel 0 Enable */
82904 #define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
82905 
82906 #define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
82907 #define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
82908 /*! CH1EN - Channel 1 Enable */
82909 #define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
82910 
82911 #define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
82912 #define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
82913 /*! CH2EN - Channel 2 Enable */
82914 #define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
82915 
82916 #define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
82917 #define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
82918 /*! CH3EN - Channel 3 Enable */
82919 #define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
82920 
82921 #define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
82922 #define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
82923 /*! CH4EN - Channel 4 Enable */
82924 #define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
82925 
82926 #define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
82927 #define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
82928 /*! CH5EN - Channel 5 Enable */
82929 #define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
82930 
82931 #define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
82932 #define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
82933 /*! CH6EN - Channel 6 Enable */
82934 #define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
82935 
82936 #define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
82937 #define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
82938 /*! CH7EN - Channel 7 Enable */
82939 #define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
82940 
82941 #define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
82942 #define PDM_CTRL_1_ERREN_SHIFT                   (23U)
82943 /*! ERREN - Error Interruption Enable
82944  *  0b0..Error Interrupts disabled
82945  *  0b1..Error Interrupts enabled
82946  */
82947 #define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
82948 
82949 #define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
82950 #define PDM_CTRL_1_DISEL_SHIFT                   (24U)
82951 /*! DISEL - DMA Interrupt Selection
82952  *  0b00..DMA and interrupt requests disabled
82953  *  0b01..DMA requests enabled
82954  *  0b10..Interrupt requests enabled
82955  *  0b11..Reserved
82956  */
82957 #define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
82958 
82959 #define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
82960 #define PDM_CTRL_1_DBGE_SHIFT                    (26U)
82961 /*! DBGE - Module Enable in Debug
82962  *  0b0..PDM Interface is disabled in debug mode, after completing the current frame.
82963  *  0b1..PDM Interface is enabled in debug mode.
82964  */
82965 #define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
82966 
82967 #define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
82968 #define PDM_CTRL_1_SRES_SHIFT                    (27U)
82969 /*! SRES - Software-reset bit
82970  *  0b0..No action
82971  *  0b1..Software reset
82972  */
82973 #define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
82974 
82975 #define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
82976 #define PDM_CTRL_1_DBG_SHIFT                     (28U)
82977 /*! DBG - Debug Mode
82978  *  0b0..PDM Interface is in Normal Mode.
82979  *  0b1..PDM Interface is in Debug Mode.
82980  */
82981 #define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
82982 
82983 #define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
82984 #define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
82985 /*! PDMIEN - PDM Inteface Enable
82986  *  0b0..PDM Interface disabled
82987  *  0b1..PDM Interface enabled.
82988  */
82989 #define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
82990 
82991 #define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
82992 #define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
82993 /*! DOZEN - DOZE enable
82994  *  0b0..DOZE enable bit is not asserted
82995  *  0b1..DOZE enable bit is asserted
82996  */
82997 #define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
82998 
82999 #define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
83000 #define PDM_CTRL_1_MDIS_SHIFT                    (31U)
83001 /*! MDIS - Module Disable
83002  *  0b0..Normal Mode
83003  *  0b1..Disable/Low Leakage Mode
83004  */
83005 #define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
83006 /*! @} */
83007 
83008 /*! @name CTRL_2 - MICFIL Control register 2 */
83009 /*! @{ */
83010 
83011 #define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
83012 #define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
83013 /*! CLKDIV - Clock Divider */
83014 #define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
83015 
83016 #define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
83017 #define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
83018 /*! CICOSR - CIC Oversampling Rate */
83019 #define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
83020 
83021 #define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
83022 #define PDM_CTRL_2_QSEL_SHIFT                    (25U)
83023 /*! QSEL - Quality Select
83024  *  0b001..High quality mode.
83025  *  0b000..Medium quality mode.
83026  *  0b111..Low quality mode.
83027  *  0b110..Very low quality 0 mode.
83028  *  0b101..Very low quality 1 mode.
83029  *  0b100..Very low quality 2 mode.
83030  */
83031 #define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
83032 /*! @} */
83033 
83034 /*! @name STAT - MICFIL Status register */
83035 /*! @{ */
83036 
83037 #define PDM_STAT_CH0F_MASK                       (0x1U)
83038 #define PDM_STAT_CH0F_SHIFT                      (0U)
83039 /*! CH0F - Channel 0 Output Data Flag
83040  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83041  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83042  */
83043 #define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
83044 
83045 #define PDM_STAT_CH1F_MASK                       (0x2U)
83046 #define PDM_STAT_CH1F_SHIFT                      (1U)
83047 /*! CH1F - Channel 1 Output Data Flag
83048  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83049  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83050  */
83051 #define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
83052 
83053 #define PDM_STAT_CH2F_MASK                       (0x4U)
83054 #define PDM_STAT_CH2F_SHIFT                      (2U)
83055 /*! CH2F - Channel 2 Output Data Flag
83056  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83057  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83058  */
83059 #define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
83060 
83061 #define PDM_STAT_CH3F_MASK                       (0x8U)
83062 #define PDM_STAT_CH3F_SHIFT                      (3U)
83063 /*! CH3F - Channel 3 Output Data Flag
83064  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83065  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83066  */
83067 #define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
83068 
83069 #define PDM_STAT_CH4F_MASK                       (0x10U)
83070 #define PDM_STAT_CH4F_SHIFT                      (4U)
83071 /*! CH4F - Channel 4 Output Data Flag
83072  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83073  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83074  */
83075 #define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
83076 
83077 #define PDM_STAT_CH5F_MASK                       (0x20U)
83078 #define PDM_STAT_CH5F_SHIFT                      (5U)
83079 /*! CH5F - Channel 5 Output Data Flag
83080  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83081  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83082  */
83083 #define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
83084 
83085 #define PDM_STAT_CH6F_MASK                       (0x40U)
83086 #define PDM_STAT_CH6F_SHIFT                      (6U)
83087 /*! CH6F - Channel 6 Output Data Flag
83088  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83089  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83090  */
83091 #define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
83092 
83093 #define PDM_STAT_CH7F_MASK                       (0x80U)
83094 #define PDM_STAT_CH7F_SHIFT                      (7U)
83095 /*! CH7F - Channel 7 Output Data Flag
83096  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
83097  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
83098  */
83099 #define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
83100 
83101 #define PDM_STAT_LOWFREQF_MASK                   (0x20000000U)
83102 #define PDM_STAT_LOWFREQF_SHIFT                  (29U)
83103 /*! LOWFREQF - Low Frequency Flag
83104  *  0b0..CLKDIV value is OK.
83105  *  0b1..CLKDIV value is too low.
83106  */
83107 #define PDM_STAT_LOWFREQF(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
83108 
83109 #define PDM_STAT_FIR_RDY_MASK                    (0x40000000U)
83110 #define PDM_STAT_FIR_RDY_SHIFT                   (30U)
83111 /*! FIR_RDY - FIR Filter Data Ready
83112  *  0b0..FIR Filter data not reliable.
83113  *  0b1..FIR Filter data reliable.
83114  */
83115 #define PDM_STAT_FIR_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
83116 
83117 #define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
83118 #define PDM_STAT_BSY_FIL_SHIFT                   (31U)
83119 /*! BSY_FIL - Decimation Filter Busy Flag
83120  *  0b1..At least one Decimation Filter channel is running.
83121  *  0b0..All Decimation Filters are stopped.
83122  */
83123 #define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
83124 /*! @} */
83125 
83126 /*! @name FIFO_CTRL - MICFIL FIFO Control register */
83127 /*! @{ */
83128 
83129 #define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x1FU)
83130 #define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
83131 /*! FIFOWMK - FIFO Watermark Control */
83132 #define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
83133 /*! @} */
83134 
83135 /*! @name FIFO_STAT - MICFIL FIFO Status register */
83136 /*! @{ */
83137 
83138 #define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
83139 #define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
83140 /*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
83141  *  0b0..No exception by FIFO overflow
83142  *  0b1..Exception by FIFO overflow
83143  */
83144 #define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
83145 
83146 #define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
83147 #define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
83148 /*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
83149  *  0b0..No exception by FIFO overflow
83150  *  0b1..Exception by FIFO overflow
83151  */
83152 #define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
83153 
83154 #define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
83155 #define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
83156 /*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
83157  *  0b0..No exception by FIFO overflow
83158  *  0b1..Exception by FIFO overflow
83159  */
83160 #define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
83161 
83162 #define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
83163 #define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
83164 /*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
83165  *  0b0..No exception by FIFO overflow
83166  *  0b1..Exception by FIFO overflow
83167  */
83168 #define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
83169 
83170 #define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
83171 #define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
83172 /*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
83173  *  0b0..No exception by FIFO overflow
83174  *  0b1..Exception by FIFO overflow
83175  */
83176 #define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
83177 
83178 #define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
83179 #define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
83180 /*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
83181  *  0b0..No exception by FIFO overflow
83182  *  0b1..Exception by FIFO overflow
83183  */
83184 #define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
83185 
83186 #define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
83187 #define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
83188 /*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
83189  *  0b0..No exception by FIFO overflow
83190  *  0b1..Exception by FIFO overflow
83191  */
83192 #define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
83193 
83194 #define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
83195 #define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
83196 /*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
83197  *  0b0..No exception by FIFO overflow
83198  *  0b1..Exception by FIFO overflow
83199  */
83200 #define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
83201 
83202 #define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
83203 #define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
83204 /*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
83205  *  0b0..No exception by FIFO Underflow
83206  *  0b1..Exception by FIFO underflow
83207  */
83208 #define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
83209 
83210 #define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
83211 #define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
83212 /*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
83213  *  0b0..No exception by FIFO Underflow
83214  *  0b1..Exception by FIFO underflow
83215  */
83216 #define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
83217 
83218 #define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
83219 #define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
83220 /*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
83221  *  0b0..No exception by FIFO Underflow
83222  *  0b1..Exception by FIFO underflow
83223  */
83224 #define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
83225 
83226 #define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
83227 #define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
83228 /*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
83229  *  0b0..No exception by FIFO Underflow
83230  *  0b1..Exception by FIFO underflow
83231  */
83232 #define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
83233 
83234 #define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
83235 #define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
83236 /*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
83237  *  0b0..No exception by FIFO Underflow
83238  *  0b1..Exception by FIFO underflow
83239  */
83240 #define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
83241 
83242 #define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
83243 #define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
83244 /*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
83245  *  0b0..No exception by FIFO Underflow
83246  *  0b1..Exception by FIFO underflow
83247  */
83248 #define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
83249 
83250 #define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
83251 #define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
83252 /*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
83253  *  0b0..No exception by FIFO Underflow
83254  *  0b1..Exception by FIFO underflow
83255  */
83256 #define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
83257 
83258 #define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
83259 #define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
83260 /*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
83261  *  0b0..No exception by FIFO Underflow
83262  *  0b1..Exception by FIFO underflow
83263  */
83264 #define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
83265 /*! @} */
83266 
83267 /*! @name DATACH - MICFIL Output Result Register */
83268 /*! @{ */
83269 
83270 #define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
83271 #define PDM_DATACH_DATA_SHIFT                    (0U)
83272 /*! DATA - Channel n Data */
83273 #define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
83274 /*! @} */
83275 
83276 /* The count of PDM_DATACH */
83277 #define PDM_DATACH_COUNT                         (8U)
83278 
83279 /*! @name DC_CTRL - MICFIL DC Remover Control register */
83280 /*! @{ */
83281 
83282 #define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
83283 #define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
83284 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
83285  *  0b11..DC Remover is bypassed.
83286  *  0b00..DC Remover cut-off at 21Hz.
83287  *  0b01..DC Remover cut-off at 83Hz.
83288  *  0b10..DC Remover cut-off at 152Hz.
83289  */
83290 #define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
83291 
83292 #define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
83293 #define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
83294 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
83295  *  0b11..DC Remover is bypassed.
83296  *  0b00..DC Remover cut-off at 21Hz.
83297  *  0b01..DC Remover cut-off at 83Hz.
83298  *  0b10..DC Remover cut-off at 152Hz.
83299  */
83300 #define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
83301 
83302 #define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
83303 #define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
83304 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
83305  *  0b11..DC Remover is bypassed.
83306  *  0b00..DC Remover cut-off at 21Hz.
83307  *  0b01..DC Remover cut-off at 83Hz.
83308  *  0b10..DC Remover cut-off at 152Hz.
83309  */
83310 #define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
83311 
83312 #define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
83313 #define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
83314 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
83315  *  0b11..DC Remover is bypassed.
83316  *  0b00..DC Remover cut-off at 21Hz.
83317  *  0b01..DC Remover cut-off at 83Hz.
83318  *  0b10..DC Remover cut-off at 152Hz.
83319  */
83320 #define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
83321 
83322 #define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
83323 #define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
83324 /*! DCCONFIG4 - Channel 4 DC Remover Configuration
83325  *  0b11..DC Remover is bypassed.
83326  *  0b00..DC Remover cut-off at 21Hz.
83327  *  0b01..DC Remover cut-off at 83Hz.
83328  *  0b10..DC Remover cut-off at 152Hz.
83329  */
83330 #define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
83331 
83332 #define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
83333 #define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
83334 /*! DCCONFIG5 - Channel 5 DC Remover Configuration
83335  *  0b11..DC Remover is bypassed.
83336  *  0b00..DC Remover cut-off at 21Hz.
83337  *  0b01..DC Remover cut-off at 83Hz.
83338  *  0b10..DC Remover cut-off at 152Hz.
83339  */
83340 #define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
83341 
83342 #define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
83343 #define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
83344 /*! DCCONFIG6 - Channel 6 DC Remover Configuration
83345  *  0b11..DC Remover is bypassed.
83346  *  0b00..DC Remover cut-off at 21Hz.
83347  *  0b01..DC Remover cut-off at 83Hz.
83348  *  0b10..DC Remover cut-off at 152Hz.
83349  */
83350 #define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
83351 
83352 #define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
83353 #define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
83354 /*! DCCONFIG7 - Channel 7 DC Remover Configuration
83355  *  0b11..DC Remover is bypassed.
83356  *  0b00..DC Remover cut-off at 21Hz.
83357  *  0b01..DC Remover cut-off at 83Hz.
83358  *  0b10..DC Remover cut-off at 152Hz.
83359  */
83360 #define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
83361 /*! @} */
83362 
83363 /*! @name RANGE_CTRL - MICFIL Range Control register */
83364 /*! @{ */
83365 
83366 #define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
83367 #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
83368 /*! RANGEADJ0 - Channel 0 Range Adjustment */
83369 #define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
83370 
83371 #define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
83372 #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
83373 /*! RANGEADJ1 - Channel 1 Range Adjustment */
83374 #define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
83375 
83376 #define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
83377 #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
83378 /*! RANGEADJ2 - Channel 2 Range Adjustment */
83379 #define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
83380 
83381 #define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
83382 #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
83383 /*! RANGEADJ3 - Channel 3 Range Adjustment */
83384 #define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
83385 
83386 #define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
83387 #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
83388 /*! RANGEADJ4 - Channel 4 Range Adjustment */
83389 #define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
83390 
83391 #define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
83392 #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
83393 /*! RANGEADJ5 - Channel 5 Range Adjustment */
83394 #define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
83395 
83396 #define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
83397 #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
83398 /*! RANGEADJ6 - Channel 6 Range Adjustment */
83399 #define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
83400 
83401 #define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
83402 #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
83403 /*! RANGEADJ7 - Channel 7 Range Adjustment */
83404 #define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
83405 /*! @} */
83406 
83407 /*! @name RANGE_STAT - MICFIL Range Status register */
83408 /*! @{ */
83409 
83410 #define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
83411 #define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
83412 /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
83413  *  0b0..No exception by range overflow.
83414  *  0b1..Exception by range overflow.
83415  */
83416 #define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
83417 
83418 #define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
83419 #define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
83420 /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
83421  *  0b0..No exception by range overflow.
83422  *  0b1..Exception by range overflow.
83423  */
83424 #define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
83425 
83426 #define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
83427 #define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
83428 /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
83429  *  0b0..No exception by range overflow.
83430  *  0b1..Exception by range overflow.
83431  */
83432 #define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
83433 
83434 #define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
83435 #define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
83436 /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
83437  *  0b0..No exception by range overflow.
83438  *  0b1..Exception by range overflow.
83439  */
83440 #define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
83441 
83442 #define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
83443 #define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
83444 /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
83445  *  0b0..No exception by range overflow.
83446  *  0b1..Exception by range overflow.
83447  */
83448 #define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
83449 
83450 #define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
83451 #define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
83452 /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
83453  *  0b0..No exception by range overflow.
83454  *  0b1..Exception by range overflow.
83455  */
83456 #define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
83457 
83458 #define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
83459 #define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
83460 /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
83461  *  0b0..No exception by range overflow.
83462  *  0b1..Exception by range overflow.
83463  */
83464 #define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
83465 
83466 #define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
83467 #define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
83468 /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
83469  *  0b0..No exception by range overflow.
83470  *  0b1..Exception by range overflow.
83471  */
83472 #define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
83473 
83474 #define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
83475 #define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
83476 /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
83477  *  0b0..No exception by range underflow.
83478  *  0b1..Exception by range underflow.
83479  */
83480 #define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
83481 
83482 #define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
83483 #define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
83484 /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
83485  *  0b0..No exception by range underflow.
83486  *  0b1..Exception by range underflow.
83487  */
83488 #define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
83489 
83490 #define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
83491 #define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
83492 /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
83493  *  0b0..No exception by range underflow.
83494  *  0b1..Exception by range underflow.
83495  */
83496 #define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
83497 
83498 #define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
83499 #define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
83500 /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
83501  *  0b0..No exception by range underflow.
83502  *  0b1..Exception by range underflow.
83503  */
83504 #define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
83505 
83506 #define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
83507 #define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
83508 /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
83509  *  0b0..No exception by range underflow.
83510  *  0b1..Exception by range underflow.
83511  */
83512 #define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
83513 
83514 #define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
83515 #define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
83516 /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
83517  *  0b0..No exception by range underflow.
83518  *  0b1..Exception by range underflow.
83519  */
83520 #define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
83521 
83522 #define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
83523 #define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
83524 /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
83525  *  0b0..No exception by range underflow.
83526  *  0b1..Exception by range underflow.
83527  */
83528 #define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
83529 
83530 #define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
83531 #define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
83532 /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
83533  *  0b0..No exception by range underflow.
83534  *  0b1..Exception by range underflow.
83535  */
83536 #define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
83537 /*! @} */
83538 
83539 /*! @name VAD0_CTRL_1 - Voice Activity Detector Control register */
83540 /*! @{ */
83541 
83542 #define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
83543 #define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
83544 /*! VADEN - Voice Activity Detector Enable
83545  *  0b0..The HWVAD is disabled.
83546  *  0b1..The HWVAD is enabled.
83547  */
83548 #define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
83549 
83550 #define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
83551 #define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
83552 /*! VADRST - Voice Activity Detector Reset */
83553 #define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
83554 
83555 #define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
83556 #define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
83557 /*! VADIE - Voice Activity Detector Interruption Enable
83558  *  0b0..HWVAD Interrupts disabled
83559  *  0b1..HWVAD Interrupts enabled
83560  */
83561 #define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
83562 
83563 #define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
83564 #define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
83565 /*! VADERIE - Voice Activity Detector Error Interruption Enable
83566  *  0b0..HWVAD Error Interrupts disabled
83567  *  0b1..HWVAD Error Interrupts enabled
83568  */
83569 #define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
83570 
83571 #define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
83572 #define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
83573 /*! VADST10 - Voice Activity Detector Internal Filters Initialization
83574  *  0b0..Normal operation.
83575  *  0b1..Filters are initialized.
83576  */
83577 #define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
83578 
83579 #define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
83580 #define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
83581 /*! VADINITT - Voice Activity Detector Initialization Time */
83582 #define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
83583 
83584 #define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
83585 #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
83586 /*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate */
83587 #define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
83588 
83589 #define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
83590 #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
83591 /*! VADCHSEL - Voice Activity Detector Channel Selector */
83592 #define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
83593 /*! @} */
83594 
83595 /*! @name VAD0_CTRL_2 - Voice Activity Detector Control register */
83596 /*! @{ */
83597 
83598 #define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
83599 #define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
83600 /*! VADHPF - Voice Activity Detector High-Pass Filter
83601  *  0b00..Filter bypassed.
83602  *  0b01..Cut-off frequency at 1750Hz.
83603  *  0b10..Cut-off frequency at 215Hz.
83604  *  0b11..Cut-off frequency at 102Hz.
83605  */
83606 #define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
83607 
83608 #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
83609 #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
83610 /*! VADINPGAIN - Voice Activity Detector Input Gain */
83611 #define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
83612 
83613 #define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
83614 #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
83615 /*! VADFRAMET - Voice Activity Detector Frame Time */
83616 #define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
83617 
83618 #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
83619 #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
83620 /*! VADFOUTDIS - Voice Activity Detector Force Output Disable
83621  *  0b0..Output is enabled.
83622  *  0b1..Output is disabled.
83623  */
83624 #define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
83625 
83626 #define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
83627 #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
83628 /*! VADPREFEN - Voice Activity Detector Pre Filter Enable
83629  *  0b0..Pre-filter is bypassed.
83630  *  0b1..Pre-filter is enabled.
83631  */
83632 #define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
83633 
83634 #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
83635 #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
83636 /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
83637  *  0b1..Frame energy calculus disabled.
83638  *  0b0..Frame energy calculus enabled.
83639  */
83640 #define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
83641 /*! @} */
83642 
83643 /*! @name VAD0_STAT - Voice Activity Detector Status register */
83644 /*! @{ */
83645 
83646 #define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
83647 #define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
83648 /*! VADIF - Voice Activity Detector Interrupt Flag
83649  *  0b0..Voice activity has not been detected by the HWVAD.
83650  *  0b1..Voice activity has been detected by the HWVAD.
83651  */
83652 #define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
83653 
83654 #define PDM_VAD0_STAT_VADEF_MASK                 (0x8000U)
83655 #define PDM_VAD0_STAT_VADEF_SHIFT                (15U)
83656 /*! VADEF - Voice Activity Detector Event Flag
83657  *  0b0..Voice activity has not been detected by the HWVAD.
83658  *  0b1..Voice activity has been detected by the HWVAD.
83659  */
83660 #define PDM_VAD0_STAT_VADEF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
83661 
83662 #define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
83663 #define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
83664 /*! VADINSATF - Voice Activity Detector Input Saturation Flag
83665  *  0b0..No exception by HWVAD input saturation.
83666  *  0b1..Exception by HWVAD input saturation.
83667  */
83668 #define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
83669 
83670 #define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
83671 #define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
83672 /*! VADINITF - Voice Activity Detector Initialization Flag
83673  *  0b0..HWVAD is not being initialized.
83674  *  0b1..HWVAD is being initialized.
83675  */
83676 #define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
83677 /*! @} */
83678 
83679 /*! @name VAD0_SCONFIG - Voice Activity Detector Signal Configuration */
83680 /*! @{ */
83681 
83682 #define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
83683 #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
83684 /*! VADSGAIN - Voice Activity Detector Signal Gain */
83685 #define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
83686 
83687 #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
83688 #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
83689 /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
83690  *  0b0..Maximum block is bypassed.
83691  *  0b1..Maximum block is enabled.
83692  */
83693 #define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
83694 
83695 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
83696 #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
83697 /*! VADSFILEN - Voice Activity Detector Signal Filter Enable
83698  *  0b0..Signal filter is disabled.
83699  *  0b1..Signal filter is enabled.
83700  */
83701 #define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
83702 /*! @} */
83703 
83704 /*! @name VAD0_NCONFIG - Voice Activity Detector Noise Configuration */
83705 /*! @{ */
83706 
83707 #define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
83708 #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
83709 /*! VADNGAIN - Voice Activity Detector Noise Gain */
83710 #define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
83711 
83712 #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
83713 #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
83714 /*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment */
83715 #define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
83716 
83717 #define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
83718 #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
83719 /*! VADNOREN - Voice Activity Detector Noise OR Enable
83720  *  0b0..Noise input is not decimated.
83721  *  0b1..Noise input is decimated.
83722  */
83723 #define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
83724 
83725 #define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
83726 #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
83727 /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
83728  *  0b0..Noise input is not decimated.
83729  *  0b1..Noise input is decimated.
83730  */
83731 #define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
83732 
83733 #define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
83734 #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
83735 /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
83736  *  0b0..Minimum block is bypassed.
83737  *  0b1..Minimum block is enabled.
83738  */
83739 #define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
83740 
83741 #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
83742 #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
83743 /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
83744  *  0b0..Noise filter is always enabled.
83745  *  0b1..Noise filter is enabled/disabled based on voice activity information.
83746  */
83747 #define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
83748 /*! @} */
83749 
83750 /*! @name VAD0_NDATA - Voice Activity Detector Noise Data */
83751 /*! @{ */
83752 
83753 #define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
83754 #define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
83755 /*! VADNDATA - Voice Activity Detector Noise Data */
83756 #define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
83757 /*! @} */
83758 
83759 /*! @name VAD0_ZCD - Voice Activity Detector Zero-Crossing Detector */
83760 /*! @{ */
83761 
83762 #define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
83763 #define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
83764 /*! VADZCDEN - Zero-Crossing Detector Enable
83765  *  0b0..The ZCD is disabled.
83766  *  0b1..The ZCD is enabled.
83767  */
83768 #define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
83769 
83770 #define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
83771 #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
83772 /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
83773  *  0b0..The ZCD threshold is not estimated automatically,
83774  *  0b1..The ZCD threshold is estimated automatically.
83775  */
83776 #define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
83777 
83778 #define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
83779 #define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
83780 /*! VADZCDAND - Zero-Crossing Detector AND Behavior
83781  *  0b0..The ZCD result is OR'ed with the energy-based detection.
83782  *  0b1..The ZCD result is AND'ed with the energy-based detection.
83783  */
83784 #define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
83785 
83786 #define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
83787 #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
83788 /*! VADZCDADJ - Zero-Crossing Detector Adjustment */
83789 #define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
83790 
83791 #define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
83792 #define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
83793 /*! VADZCDTH - Zero-Crossing Detector Threshold */
83794 #define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
83795 /*! @} */
83796 
83797 
83798 /*!
83799  * @}
83800  */ /* end of group PDM_Register_Masks */
83801 
83802 
83803 /* PDM - Peripheral instance base addresses */
83804 /** Peripheral PDM base address */
83805 #define PDM_BASE                                 (0x30CA0000u)
83806 /** Peripheral PDM base pointer */
83807 #define PDM                                      ((PDM_Type *)PDM_BASE)
83808 /** Array initializer of PDM peripheral base addresses */
83809 #define PDM_BASE_ADDRS                           { PDM_BASE }
83810 /** Array initializer of PDM peripheral base pointers */
83811 #define PDM_BASE_PTRS                            { PDM }
83812 
83813 /*!
83814  * @}
83815  */ /* end of group PDM_Peripheral_Access_Layer */
83816 
83817 
83818 /* ----------------------------------------------------------------------------
83819    -- PHYCONFIGURATION Peripheral Access Layer
83820    ---------------------------------------------------------------------------- */
83821 
83822 /*!
83823  * @addtogroup PHYCONFIGURATION_Peripheral_Access_Layer PHYCONFIGURATION Peripheral Access Layer
83824  * @{
83825  */
83826 
83827 /** PHYCONFIGURATION - Register Layout Typedef */
83828 typedef struct {
83829   __IO uint8_t PHY_CONF0;                          /**< PHY Configuration Register This register holds the power down, data enable polarity, and interface control of the HDMI Source PHY control., offset: 0x0 */
83830   __IO uint8_t PHY_TST0;                           /**< PHY Test Interface Register 0 PHY TX mapped test interface (control)., offset: 0x1 */
83831   __IO uint8_t PHY_TST1;                           /**< PHY Test Interface Register 1 PHY TX mapped text interface (data in)., offset: 0x2 */
83832   __I  uint8_t PHY_TST2;                           /**< PHY Test Interface Register 2 PHY TX mapped text interface (data out)., offset: 0x3 */
83833   __I  uint8_t PHY_STAT0;                          /**< PHY RXSENSE, PLL Lock, and HPD Status Register This register contains the following active high packet sent status indications., offset: 0x4 */
83834   __I  uint8_t PHY_INT0;                           /**< PHY RXSENSE, PLL Lock, and HPD Interrupt Register This register contains the interrupt indication of the PHY_STAT0 status interrupts., offset: 0x5 */
83835   __IO uint8_t PHY_MASK0;                          /**< PHY RXSENSE, PLL Lock, and HPD Mask Register Mask register for generation of PHY_INT0 interrupts., offset: 0x6 */
83836   __IO uint8_t PHY_POL0;                           /**< PHY RXSENSE, PLL Lock, and HPD Polarity Register Polarity register for generation of PHY_INT0 interrupts., offset: 0x7 */
83837        uint8_t RESERVED_0[24];
83838   __IO uint8_t PHY_I2CM_SLAVE;                     /**< PHY I2C Slave Address Configuration Register, offset: 0x20 */
83839   __IO uint8_t PHY_I2CM_ADDRESS;                   /**< PHY I2C Address Configuration Register This register writes the address for read and write operations., offset: 0x21 */
83840   __IO uint8_t PHY_I2CM_DATAO_1;                   /**< PHY I2C Data Write Register 1, offset: 0x22 */
83841   __IO uint8_t PHY_I2CM_DATAO_0;                   /**< PHY I2C Data Write Register 0, offset: 0x23 */
83842   __I  uint8_t PHY_I2CM_DATAI_1;                   /**< PHY I2C Data Read Register 1, offset: 0x24 */
83843   __I  uint8_t PHY_I2CM_DATAI_0;                   /**< PHY I2C Data Read Register 0, offset: 0x25 */
83844   __O  uint8_t PHY_I2CM_OPERATION;                 /**< PHY I2C RD/RD_EXT/WR Operation Register This register requests read and write operations from the I2C Master PHY., offset: 0x26 */
83845   __IO uint8_t PHY_I2CM_INT;                       /**< PHY I2C Done Interrupt Register This register contains and configures I2C master PHY done interrupt., offset: 0x27 */
83846   __IO uint8_t PHY_I2CM_CTLINT;                    /**< PHY I2C error Interrupt Register This register contains and configures the I2C master PHY error interrupts., offset: 0x28 */
83847   __IO uint8_t PHY_I2CM_DIV;                       /**< PHY I2C Speed control Register This register wets the I2C Master PHY to work in either Fast or Standard mode., offset: 0x29 */
83848   __IO uint8_t PHY_I2CM_SOFTRSTZ;                  /**< PHY I2C SW reset control register This register sets the I2C Master PHY software reset., offset: 0x2A */
83849   __IO uint8_t PHY_I2CM_SS_SCL_HCNT_1_ADDR;        /**< PHY I2C Slow Speed SCL High Level Control Register 1, offset: 0x2B */
83850   __IO uint8_t PHY_I2CM_SS_SCL_HCNT_0_ADDR;        /**< PHY I2C Slow Speed SCL High Level Control Register 0, offset: 0x2C */
83851   __IO uint8_t PHY_I2CM_SS_SCL_LCNT_1_ADDR;        /**< PHY I2C Slow Speed SCL Low Level Control Register 1, offset: 0x2D */
83852   __IO uint8_t PHY_I2CM_SS_SCL_LCNT_0_ADDR;        /**< PHY I2C Slow Speed SCL Low Level Control Register 0, offset: 0x2E */
83853   __IO uint8_t PHY_I2CM_FS_SCL_HCNT_1_ADDR;        /**< PHY I2C Fast Speed SCL High Level Control Register 1, offset: 0x2F */
83854   __IO uint8_t PHY_I2CM_FS_SCL_HCNT_0_ADDR;        /**< PHY I2C Fast Speed SCL High Level Control Register 0, offset: 0x30 */
83855   __IO uint8_t PHY_I2CM_FS_SCL_LCNT_1_ADDR;        /**< PHY I2C Fast Speed SCL Low Level Control Register 1, offset: 0x31 */
83856   __IO uint8_t PHY_I2CM_FS_SCL_LCNT_0_ADDR;        /**< PHY I2C Fast Speed SCL Low Level Control Register 0, offset: 0x32 */
83857   __IO uint8_t PHY_I2CM_SDA_HOLD;                  /**< PHY I2C SDA HOLD Control Register, offset: 0x33 */
83858   __IO uint8_t JTAG_PHY_CONFIG;                    /**< PHY I2C/JTAG I/O Configuration Control Register, offset: 0x34 */
83859   __IO uint8_t JTAG_PHY_TAP_TCK;                   /**< PHY JTAG Clock Control Register, offset: 0x35 */
83860   __IO uint8_t JTAG_PHY_TAP_IN;                    /**< PHY JTAG TAP In Control Register, offset: 0x36 */
83861   __I  uint8_t JTAG_PHY_TAP_OUT;                   /**< PHY JTAG TAP Out Control Register, offset: 0x37 */
83862   __IO uint8_t JTAG_PHY_ADDR;                      /**< PHY JTAG Address Control Register, offset: 0x38 */
83863 } PHYCONFIGURATION_Type;
83864 
83865 /* ----------------------------------------------------------------------------
83866    -- PHYCONFIGURATION Register Masks
83867    ---------------------------------------------------------------------------- */
83868 
83869 /*!
83870  * @addtogroup PHYCONFIGURATION_Register_Masks PHYCONFIGURATION Register Masks
83871  * @{
83872  */
83873 
83874 /*! @name PHY_CONF0 - PHY Configuration Register This register holds the power down, data enable polarity, and interface control of the HDMI Source PHY control. */
83875 /*! @{ */
83876 
83877 #define PHYCONFIGURATION_PHY_CONF0_SELDIPIF_MASK (0x1U)
83878 #define PHYCONFIGURATION_PHY_CONF0_SELDIPIF_SHIFT (0U)
83879 /*! seldipif - Select interface control. */
83880 #define PHYCONFIGURATION_PHY_CONF0_SELDIPIF(x)   (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SELDIPIF_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SELDIPIF_MASK)
83881 
83882 #define PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_MASK (0x2U)
83883 #define PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_SHIFT (1U)
83884 /*! seldataenpol - Select data enable polarity. */
83885 #define PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_MASK)
83886 
83887 #define PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_MASK (0x4U)
83888 #define PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_SHIFT (2U)
83889 /*! enhpdrxsense - PHY ENHPDRXSENSE signal. */
83890 #define PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_MASK)
83891 
83892 #define PHYCONFIGURATION_PHY_CONF0_TXPWRON_MASK  (0x8U)
83893 #define PHYCONFIGURATION_PHY_CONF0_TXPWRON_SHIFT (3U)
83894 /*! txpwron - PHY TXPWRON signal. */
83895 #define PHYCONFIGURATION_PHY_CONF0_TXPWRON(x)    (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_TXPWRON_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_TXPWRON_MASK)
83896 
83897 #define PHYCONFIGURATION_PHY_CONF0_PDDQ_MASK     (0x10U)
83898 #define PHYCONFIGURATION_PHY_CONF0_PDDQ_SHIFT    (4U)
83899 /*! pddq - PHY PDDQ signal. */
83900 #define PHYCONFIGURATION_PHY_CONF0_PDDQ(x)       (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_PDDQ_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_PDDQ_MASK)
83901 
83902 #define PHYCONFIGURATION_PHY_CONF0_SPARECTRL_MASK (0x20U)
83903 #define PHYCONFIGURATION_PHY_CONF0_SPARECTRL_SHIFT (5U)
83904 /*! sparectrl - Reserved as "spare" register with no associated functionality. */
83905 #define PHYCONFIGURATION_PHY_CONF0_SPARECTRL(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SPARECTRL_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SPARECTRL_MASK)
83906 
83907 #define PHYCONFIGURATION_PHY_CONF0_SPARES_1_MASK (0x40U)
83908 #define PHYCONFIGURATION_PHY_CONF0_SPARES_1_SHIFT (6U)
83909 /*! spares_1 - Reserved as "spare" register with no associated functionality. */
83910 #define PHYCONFIGURATION_PHY_CONF0_SPARES_1(x)   (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SPARES_1_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SPARES_1_MASK)
83911 
83912 #define PHYCONFIGURATION_PHY_CONF0_SPARES_2_MASK (0x80U)
83913 #define PHYCONFIGURATION_PHY_CONF0_SPARES_2_SHIFT (7U)
83914 /*! spares_2 - Reserved as "spare" register with no associated functionality. */
83915 #define PHYCONFIGURATION_PHY_CONF0_SPARES_2(x)   (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SPARES_2_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SPARES_2_MASK)
83916 /*! @} */
83917 
83918 /*! @name PHY_TST0 - PHY Test Interface Register 0 PHY TX mapped test interface (control). */
83919 /*! @{ */
83920 
83921 #define PHYCONFIGURATION_PHY_TST0_SPARE_0_MASK   (0x1U)
83922 #define PHYCONFIGURATION_PHY_TST0_SPARE_0_SHIFT  (0U)
83923 /*! spare_0 - Reserved as "spare" register with no associated functionality. */
83924 #define PHYCONFIGURATION_PHY_TST0_SPARE_0(x)     (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_0_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_0_MASK)
83925 
83926 #define PHYCONFIGURATION_PHY_TST0_SPARE_1_MASK   (0xEU)
83927 #define PHYCONFIGURATION_PHY_TST0_SPARE_1_SHIFT  (1U)
83928 /*! spare_1 - Reserved as "spare" bit with no associated functionality. */
83929 #define PHYCONFIGURATION_PHY_TST0_SPARE_1(x)     (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_1_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_1_MASK)
83930 
83931 #define PHYCONFIGURATION_PHY_TST0_SPARE_3_MASK   (0x10U)
83932 #define PHYCONFIGURATION_PHY_TST0_SPARE_3_SHIFT  (4U)
83933 /*! spare_3 - Reserved as "spare" register with no associated functionality. */
83934 #define PHYCONFIGURATION_PHY_TST0_SPARE_3(x)     (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_3_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_3_MASK)
83935 
83936 #define PHYCONFIGURATION_PHY_TST0_SPARE_4_MASK   (0x20U)
83937 #define PHYCONFIGURATION_PHY_TST0_SPARE_4_SHIFT  (5U)
83938 /*! spare_4 - Reserved as "spare" register with no associated functionality. */
83939 #define PHYCONFIGURATION_PHY_TST0_SPARE_4(x)     (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_4_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_4_MASK)
83940 
83941 #define PHYCONFIGURATION_PHY_TST0_SPARE_2_MASK   (0xC0U)
83942 #define PHYCONFIGURATION_PHY_TST0_SPARE_2_SHIFT  (6U)
83943 /*! spare_2 - Reserved as "spare" bit with no associated functionality. */
83944 #define PHYCONFIGURATION_PHY_TST0_SPARE_2(x)     (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_2_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_2_MASK)
83945 /*! @} */
83946 
83947 /*! @name PHY_TST1 - PHY Test Interface Register 1 PHY TX mapped text interface (data in). */
83948 /*! @{ */
83949 
83950 #define PHYCONFIGURATION_PHY_TST1_SPARE_MASK     (0xFFU)
83951 #define PHYCONFIGURATION_PHY_TST1_SPARE_SHIFT    (0U)
83952 /*! spare - Reserved as "spare" register with no associated functionality. */
83953 #define PHYCONFIGURATION_PHY_TST1_SPARE(x)       (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST1_SPARE_SHIFT)) & PHYCONFIGURATION_PHY_TST1_SPARE_MASK)
83954 /*! @} */
83955 
83956 /*! @name PHY_TST2 - PHY Test Interface Register 2 PHY TX mapped text interface (data out). */
83957 /*! @{ */
83958 
83959 #define PHYCONFIGURATION_PHY_TST2_SPARE_MASK     (0xFFU)
83960 #define PHYCONFIGURATION_PHY_TST2_SPARE_SHIFT    (0U)
83961 /*! spare - Reserved as "spare" register with no associated functionality. */
83962 #define PHYCONFIGURATION_PHY_TST2_SPARE(x)       (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST2_SPARE_SHIFT)) & PHYCONFIGURATION_PHY_TST2_SPARE_MASK)
83963 /*! @} */
83964 
83965 /*! @name PHY_STAT0 - PHY RXSENSE, PLL Lock, and HPD Status Register This register contains the following active high packet sent status indications. */
83966 /*! @{ */
83967 
83968 #define PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_MASK (0x1U)
83969 #define PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_SHIFT (0U)
83970 /*! TX_PHY_LOCK - Status bit. */
83971 #define PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_MASK)
83972 
83973 #define PHYCONFIGURATION_PHY_STAT0_HPD_MASK      (0x2U)
83974 #define PHYCONFIGURATION_PHY_STAT0_HPD_SHIFT     (1U)
83975 /*! HPD - Status bit. */
83976 #define PHYCONFIGURATION_PHY_STAT0_HPD(x)        (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_HPD_MASK)
83977 
83978 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_MASK (0x10U)
83979 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_SHIFT (4U)
83980 /*! RX_SENSE_0 - Status bit. */
83981 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_MASK)
83982 
83983 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_MASK (0x20U)
83984 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_SHIFT (5U)
83985 /*! RX_SENSE_1 - Status bit. */
83986 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_MASK)
83987 
83988 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_MASK (0x40U)
83989 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_SHIFT (6U)
83990 /*! RX_SENSE_2 - Status bit. */
83991 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_MASK)
83992 
83993 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_MASK (0x80U)
83994 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_SHIFT (7U)
83995 /*! RX_SENSE_3 - Status bit. */
83996 #define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_MASK)
83997 /*! @} */
83998 
83999 /*! @name PHY_INT0 - PHY RXSENSE, PLL Lock, and HPD Interrupt Register This register contains the interrupt indication of the PHY_STAT0 status interrupts. */
84000 /*! @{ */
84001 
84002 #define PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_MASK (0x1U)
84003 #define PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_SHIFT (0U)
84004 /*! TX_PHY_LOCK - Interrupt indication bit. */
84005 #define PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_MASK)
84006 
84007 #define PHYCONFIGURATION_PHY_INT0_HPD_MASK       (0x2U)
84008 #define PHYCONFIGURATION_PHY_INT0_HPD_SHIFT      (1U)
84009 /*! HPD - Interrupt indication bit. */
84010 #define PHYCONFIGURATION_PHY_INT0_HPD(x)         (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_INT0_HPD_MASK)
84011 
84012 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_MASK (0x10U)
84013 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_SHIFT (4U)
84014 /*! RX_SENSE_0 - Interrupt indication bit. */
84015 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_0(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_MASK)
84016 
84017 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_MASK (0x20U)
84018 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_SHIFT (5U)
84019 /*! RX_SENSE_1 - Interrupt indication bit. */
84020 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_1(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_MASK)
84021 
84022 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_MASK (0x40U)
84023 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_SHIFT (6U)
84024 /*! RX_SENSE_2 - Interrupt indication bit. */
84025 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_2(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_MASK)
84026 
84027 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_MASK (0x80U)
84028 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_SHIFT (7U)
84029 /*! RX_SENSE_3 - Interrupt indication bit. */
84030 #define PHYCONFIGURATION_PHY_INT0_RX_SENSE_3(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_MASK)
84031 /*! @} */
84032 
84033 /*! @name PHY_MASK0 - PHY RXSENSE, PLL Lock, and HPD Mask Register Mask register for generation of PHY_INT0 interrupts. */
84034 /*! @{ */
84035 
84036 #define PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_MASK (0x1U)
84037 #define PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_SHIFT (0U)
84038 /*! TX_PHY_LOCK - Mask bit for PHY_INT0. */
84039 #define PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_MASK)
84040 
84041 #define PHYCONFIGURATION_PHY_MASK0_HPD_MASK      (0x2U)
84042 #define PHYCONFIGURATION_PHY_MASK0_HPD_SHIFT     (1U)
84043 /*! HPD - Mask bit for PHY_INT0. */
84044 #define PHYCONFIGURATION_PHY_MASK0_HPD(x)        (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_HPD_MASK)
84045 
84046 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_MASK (0x10U)
84047 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_SHIFT (4U)
84048 /*! RX_SENSE_0 - Mask bit for PHY_INT0. */
84049 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_MASK)
84050 
84051 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_MASK (0x20U)
84052 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_SHIFT (5U)
84053 /*! RX_SENSE_1 - Mask bit for PHY_INT0. */
84054 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_MASK)
84055 
84056 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_MASK (0x40U)
84057 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_SHIFT (6U)
84058 /*! RX_SENSE_2 - Mask bit for PHY_INT0. */
84059 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_MASK)
84060 
84061 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_MASK (0x80U)
84062 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_SHIFT (7U)
84063 /*! RX_SENSE_3 - Mask bit for PHY_INT0. */
84064 #define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_MASK)
84065 /*! @} */
84066 
84067 /*! @name PHY_POL0 - PHY RXSENSE, PLL Lock, and HPD Polarity Register Polarity register for generation of PHY_INT0 interrupts. */
84068 /*! @{ */
84069 
84070 #define PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_MASK (0x1U)
84071 #define PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_SHIFT (0U)
84072 /*! TX_PHY_LOCK - Polarity bit for PHY_INT0. */
84073 #define PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_MASK)
84074 
84075 #define PHYCONFIGURATION_PHY_POL0_HPD_MASK       (0x2U)
84076 #define PHYCONFIGURATION_PHY_POL0_HPD_SHIFT      (1U)
84077 /*! HPD - Polarity bit for PHY_INT0. */
84078 #define PHYCONFIGURATION_PHY_POL0_HPD(x)         (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_POL0_HPD_MASK)
84079 
84080 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_MASK (0x10U)
84081 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_SHIFT (4U)
84082 /*! RX_SENSE_0 - Polarity bit for PHY_INT0. */
84083 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_0(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_MASK)
84084 
84085 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_MASK (0x20U)
84086 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_SHIFT (5U)
84087 /*! RX_SENSE_1 - Polarity bit for PHY_INT0. */
84088 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_1(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_MASK)
84089 
84090 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_MASK (0x40U)
84091 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_SHIFT (6U)
84092 /*! RX_SENSE_2 - Polarity bit for PHY_INT0. */
84093 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_2(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_MASK)
84094 
84095 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_MASK (0x80U)
84096 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_SHIFT (7U)
84097 /*! RX_SENSE_3 - Polarity bit for PHY_INT0. */
84098 #define PHYCONFIGURATION_PHY_POL0_RX_SENSE_3(x)  (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_MASK)
84099 /*! @} */
84100 
84101 /*! @name PHY_I2CM_SLAVE - PHY I2C Slave Address Configuration Register */
84102 /*! @{ */
84103 
84104 #define PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_MASK (0x7FU)
84105 #define PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_SHIFT (0U)
84106 /*! slaveaddr - Slave address to be sent during read and write operations. */
84107 #define PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_MASK)
84108 /*! @} */
84109 
84110 /*! @name PHY_I2CM_ADDRESS - PHY I2C Address Configuration Register This register writes the address for read and write operations. */
84111 /*! @{ */
84112 
84113 #define PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_MASK (0xFFU)
84114 #define PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_SHIFT (0U)
84115 /*! address - Register address for read and write operations */
84116 #define PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_MASK)
84117 /*! @} */
84118 
84119 /*! @name PHY_I2CM_DATAO_1 - PHY I2C Data Write Register 1 */
84120 /*! @{ */
84121 
84122 #define PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_MASK (0xFFU)
84123 #define PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_SHIFT (0U)
84124 /*! datao - Data MSB (datao[15:8]) to be written on register pointed by phy_i2cm_address [7:0]. */
84125 #define PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_MASK)
84126 /*! @} */
84127 
84128 /*! @name PHY_I2CM_DATAO_0 - PHY I2C Data Write Register 0 */
84129 /*! @{ */
84130 
84131 #define PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_MASK (0xFFU)
84132 #define PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_SHIFT (0U)
84133 /*! datao - Data LSB (datao[7:0]) to be written on register pointed by phy_i2cm_address [7:0]. */
84134 #define PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_MASK)
84135 /*! @} */
84136 
84137 /*! @name PHY_I2CM_DATAI_1 - PHY I2C Data Read Register 1 */
84138 /*! @{ */
84139 
84140 #define PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_MASK (0xFFU)
84141 #define PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_SHIFT (0U)
84142 /*! datai - Data MSB (datai[15:8]) read from register pointed by phy_i2cm_address[7:0]. */
84143 #define PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_MASK)
84144 /*! @} */
84145 
84146 /*! @name PHY_I2CM_DATAI_0 - PHY I2C Data Read Register 0 */
84147 /*! @{ */
84148 
84149 #define PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_MASK (0xFFU)
84150 #define PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_SHIFT (0U)
84151 /*! datai - Data LSB (datai[7:0]) read from register pointed by phy_i2cm_address[7:0]. */
84152 #define PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_MASK)
84153 /*! @} */
84154 
84155 /*! @name PHY_I2CM_OPERATION - PHY I2C RD/RD_EXT/WR Operation Register This register requests read and write operations from the I2C Master PHY. */
84156 /*! @{ */
84157 
84158 #define PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_MASK (0x1U)
84159 #define PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_SHIFT (0U)
84160 /*! rd - Read operation request */
84161 #define PHYCONFIGURATION_PHY_I2CM_OPERATION_RD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_MASK)
84162 
84163 #define PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_MASK (0x10U)
84164 #define PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_SHIFT (4U)
84165 /*! wr - Write operation request */
84166 #define PHYCONFIGURATION_PHY_I2CM_OPERATION_WR(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_MASK)
84167 /*! @} */
84168 
84169 /*! @name PHY_I2CM_INT - PHY I2C Done Interrupt Register This register contains and configures I2C master PHY done interrupt. */
84170 /*! @{ */
84171 
84172 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_MASK (0x1U)
84173 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_SHIFT (0U)
84174 /*! done_status - Operation done status bit. */
84175 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_MASK)
84176 
84177 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_MASK (0x2U)
84178 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_SHIFT (1U)
84179 /*! done_interrupt - Operation done interrupt bit. */
84180 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_MASK)
84181 
84182 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_MASK (0x4U)
84183 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_SHIFT (2U)
84184 /*! done_mask - Done interrupt mask signal */
84185 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_MASK)
84186 
84187 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_MASK (0x8U)
84188 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_SHIFT (3U)
84189 /*! done_pol - Done interrupt polarity configuration */
84190 #define PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_MASK)
84191 /*! @} */
84192 
84193 /*! @name PHY_I2CM_CTLINT - PHY I2C error Interrupt Register This register contains and configures the I2C master PHY error interrupts. */
84194 /*! @{ */
84195 
84196 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_MASK (0x1U)
84197 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_SHIFT (0U)
84198 /*! arbitration_status - Arbitration error status bit. */
84199 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_MASK)
84200 
84201 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_MASK (0x2U)
84202 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_SHIFT (1U)
84203 /*! arbitration_interrupt - Arbitration error interrupt bit {arbitration_interrupt =
84204  *    (arbitration_mask==0b) && (arbitration_status==arbitration_pol)} Note: This bit field is read by the sticky
84205  *    bits present on the ih_i2cmphy_stat0 register.
84206  */
84207 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_MASK)
84208 
84209 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_MASK (0x4U)
84210 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_SHIFT (2U)
84211 /*! arbitration_mask - Arbitration error interrupt mask signal. */
84212 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_MASK)
84213 
84214 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_MASK (0x8U)
84215 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_SHIFT (3U)
84216 /*! arbitration_pol - Arbitration error interrupt polarity configuration. */
84217 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_MASK)
84218 
84219 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_MASK (0x10U)
84220 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_SHIFT (4U)
84221 /*! nack_status - Not acknowledge error status bit. */
84222 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_MASK)
84223 
84224 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_MASK (0x20U)
84225 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_SHIFT (5U)
84226 /*! nack_interrupt - Not acknowledge error interrupt bit. */
84227 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_MASK)
84228 
84229 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_MASK (0x40U)
84230 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_SHIFT (6U)
84231 /*! nack_mask - Not acknowledge error interrupt mask signal */
84232 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_MASK)
84233 
84234 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_MASK (0x80U)
84235 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_SHIFT (7U)
84236 /*! nack_pol - Not acknowledge error interrupt polarity configuration */
84237 #define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_MASK)
84238 /*! @} */
84239 
84240 /*! @name PHY_I2CM_DIV - PHY I2C Speed control Register This register wets the I2C Master PHY to work in either Fast or Standard mode. */
84241 /*! @{ */
84242 
84243 #define PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_MASK (0x7U)
84244 #define PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_SHIFT (0U)
84245 /*! spare - Reserved as "spare" register with no associated functionality. */
84246 #define PHYCONFIGURATION_PHY_I2CM_DIV_SPARE(x)   (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_MASK)
84247 
84248 #define PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_MASK (0x8U)
84249 #define PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_SHIFT (3U)
84250 /*! fast_std_mode - Sets the I2C Master to work in Fast Mode or Standard Mode: 1: Fast Mode 0: Standard Mode */
84251 #define PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_MASK)
84252 /*! @} */
84253 
84254 /*! @name PHY_I2CM_SOFTRSTZ - PHY I2C SW reset control register This register sets the I2C Master PHY software reset. */
84255 /*! @{ */
84256 
84257 #define PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK (0x1U)
84258 #define PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT (0U)
84259 /*! i2c_softrstz - I2C Master Software Reset. */
84260 #define PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK)
84261 /*! @} */
84262 
84263 /*! @name PHY_I2CM_SS_SCL_HCNT_1_ADDR - PHY I2C Slow Speed SCL High Level Control Register 1 */
84264 /*! @{ */
84265 
84266 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK (0xFFU)
84267 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT (0U)
84268 /*! i2cmp_ss_scl_hcnt1 - PHY I2C Slow Speed SCL High Level Control Register 1 */
84269 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK)
84270 /*! @} */
84271 
84272 /*! @name PHY_I2CM_SS_SCL_HCNT_0_ADDR - PHY I2C Slow Speed SCL High Level Control Register 0 */
84273 /*! @{ */
84274 
84275 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK (0xFFU)
84276 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT (0U)
84277 /*! i2cmp_ss_scl_hcnt0 - PHY I2C Slow Speed SCL High Level Control Register 0 */
84278 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK)
84279 /*! @} */
84280 
84281 /*! @name PHY_I2CM_SS_SCL_LCNT_1_ADDR - PHY I2C Slow Speed SCL Low Level Control Register 1 */
84282 /*! @{ */
84283 
84284 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK (0xFFU)
84285 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT (0U)
84286 /*! i2cmp_ss_scl_lcnt1 - PHY I2C Slow Speed SCL Low Level Control Register 1 */
84287 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK)
84288 /*! @} */
84289 
84290 /*! @name PHY_I2CM_SS_SCL_LCNT_0_ADDR - PHY I2C Slow Speed SCL Low Level Control Register 0 */
84291 /*! @{ */
84292 
84293 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK (0xFFU)
84294 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT (0U)
84295 /*! i2cmp_ss_scl_lcnt0 - PHY I2C Slow Speed SCL Low Level Control Register 0 */
84296 #define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK)
84297 /*! @} */
84298 
84299 /*! @name PHY_I2CM_FS_SCL_HCNT_1_ADDR - PHY I2C Fast Speed SCL High Level Control Register 1 */
84300 /*! @{ */
84301 
84302 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK (0xFFU)
84303 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT (0U)
84304 /*! i2cmp_fs_scl_hcnt1 - PHY I2C Fast Speed SCL High Level Control Register 1 */
84305 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK)
84306 /*! @} */
84307 
84308 /*! @name PHY_I2CM_FS_SCL_HCNT_0_ADDR - PHY I2C Fast Speed SCL High Level Control Register 0 */
84309 /*! @{ */
84310 
84311 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK (0xFFU)
84312 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT (0U)
84313 /*! i2cmp_fs_scl_hcnt0 - PHY I2C Fast Speed SCL High Level Control Register 0 */
84314 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK)
84315 /*! @} */
84316 
84317 /*! @name PHY_I2CM_FS_SCL_LCNT_1_ADDR - PHY I2C Fast Speed SCL Low Level Control Register 1 */
84318 /*! @{ */
84319 
84320 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK (0xFFU)
84321 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT (0U)
84322 /*! i2cmp_fs_scl_lcnt1 - PHY I2C Fast Speed SCL Low Level Control Register 1 */
84323 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK)
84324 /*! @} */
84325 
84326 /*! @name PHY_I2CM_FS_SCL_LCNT_0_ADDR - PHY I2C Fast Speed SCL Low Level Control Register 0 */
84327 /*! @{ */
84328 
84329 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK (0xFFU)
84330 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT (0U)
84331 /*! i2cmp_fs_scl_lcnt0 - PHY I2C Fast Speed SCL Low Level Control Register 0 */
84332 #define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK)
84333 /*! @} */
84334 
84335 /*! @name PHY_I2CM_SDA_HOLD - PHY I2C SDA HOLD Control Register */
84336 /*! @{ */
84337 
84338 #define PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_MASK (0xFFU)
84339 #define PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT (0U)
84340 /*! osda_hold - Defines the number of SFR clock cycles to meet tHD:DAT (300 ns) osda_hold =
84341  *    round_to_high_integer (300 ns / (1/isfrclk_frequency))
84342  */
84343 #define PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_MASK)
84344 /*! @} */
84345 
84346 /*! @name JTAG_PHY_CONFIG - PHY I2C/JTAG I/O Configuration Control Register */
84347 /*! @{ */
84348 
84349 #define PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_MASK (0x1U)
84350 #define PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_SHIFT (0U)
84351 /*! jtag_trst_n - Configures the JTAG PHY interface output pin JTAG_TRST_N when in internal control
84352  *    mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_trst_n when PHY_EXTERNAL=1.
84353  */
84354 #define PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_MASK)
84355 
84356 #define PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_MASK (0x10U)
84357 #define PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_SHIFT (4U)
84358 /*! i2c_jtagz - Configures the JTAG PHY interface output pin I2C_JTAGZ to select the PHY
84359  *    configuration interface when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_i2c_jtagz when
84360  *    PHY_EXTERNAL=1.
84361  */
84362 #define PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_MASK)
84363 /*! @} */
84364 
84365 /*! @name JTAG_PHY_TAP_TCK - PHY JTAG Clock Control Register */
84366 /*! @{ */
84367 
84368 #define PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_MASK (0x1U)
84369 #define PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_SHIFT (0U)
84370 /*! jtag_tck - Configures the JTAG PHY interface pin JTAG_TCK when in internal control mode
84371  *    (iphy_ext_ctrl=1'b0) or ophyext_jtag_tck when PHY_EXTERNAL=1.
84372  */
84373 #define PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_MASK)
84374 /*! @} */
84375 
84376 /*! @name JTAG_PHY_TAP_IN - PHY JTAG TAP In Control Register */
84377 /*! @{ */
84378 
84379 #define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_MASK (0x1U)
84380 #define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_SHIFT (0U)
84381 /*! jtag_tdi - Configures the JTAG PHY interface pin JTAG_TDI when in internal control mode
84382  *    (iphy_ext_ctrl=1'b0) or ophyext_jtag_tdi when PHY_EXTERNAL=1.
84383  */
84384 #define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_MASK)
84385 
84386 #define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_MASK (0x10U)
84387 #define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_SHIFT (4U)
84388 /*! jtag_tms - Configures the JTAG PHY interface pin JTAG_TMS when in internal control mode
84389  *    (iphy_ext_ctrl=1'b0) or ophyext_jtag_tms when PHY_EXTERNAL=1.
84390  */
84391 #define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_MASK)
84392 /*! @} */
84393 
84394 /*! @name JTAG_PHY_TAP_OUT - PHY JTAG TAP Out Control Register */
84395 /*! @{ */
84396 
84397 #define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_MASK (0x1U)
84398 #define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_SHIFT (0U)
84399 /*! jtag_tdo - Read JTAG PHY interface input pin JTAG_TDO when in internal control mode
84400  *    (iphy_ext_ctrl=1'b0) or iphyext_jtag_tdo when PHY_EXTERNAL=1
84401  */
84402 #define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_MASK)
84403 
84404 #define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_MASK (0x10U)
84405 #define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_SHIFT (4U)
84406 /*! jtag_tdo_en - Read JTAG PHY interface input pin JTAG_TDO_EN when in internal control mode
84407  *    (iphy_ext_ctrl=1'b0) or iphyext_jtag_tdo_en when PHY_EXTERNAL=1
84408  */
84409 #define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_MASK)
84410 /*! @} */
84411 
84412 /*! @name JTAG_PHY_ADDR - PHY JTAG Address Control Register */
84413 /*! @{ */
84414 
84415 #define PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_MASK (0xFFU)
84416 #define PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_SHIFT (0U)
84417 /*! jtag_addr - Configures the JTAG PHY interface pin JTAG_ADDR[7:0] when in internal control mode
84418  *    (iphy_ext_ctrl=1'b0) or iphyext_jtag_addr[7:0] when PHY_EXTERNAL=1
84419  */
84420 #define PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_MASK)
84421 /*! @} */
84422 
84423 
84424 /*!
84425  * @}
84426  */ /* end of group PHYCONFIGURATION_Register_Masks */
84427 
84428 
84429 /* PHYCONFIGURATION - Peripheral instance base addresses */
84430 /** Peripheral PHYCONFIGURATION base address */
84431 #define PHYCONFIGURATION_BASE                    (0x32FDB000u)
84432 /** Peripheral PHYCONFIGURATION base pointer */
84433 #define PHYCONFIGURATION                         ((PHYCONFIGURATION_Type *)PHYCONFIGURATION_BASE)
84434 /** Array initializer of PHYCONFIGURATION peripheral base addresses */
84435 #define PHYCONFIGURATION_BASE_ADDRS              { PHYCONFIGURATION_BASE }
84436 /** Array initializer of PHYCONFIGURATION peripheral base pointers */
84437 #define PHYCONFIGURATION_BASE_PTRS               { PHYCONFIGURATION }
84438 
84439 /*!
84440  * @}
84441  */ /* end of group PHYCONFIGURATION_Peripheral_Access_Layer */
84442 
84443 
84444 /* ----------------------------------------------------------------------------
84445    -- PWM Peripheral Access Layer
84446    ---------------------------------------------------------------------------- */
84447 
84448 /*!
84449  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
84450  * @{
84451  */
84452 
84453 /** PWM - Register Layout Typedef */
84454 typedef struct {
84455   __IO uint32_t PWMCR;                             /**< PWM Control Register, offset: 0x0 */
84456   __IO uint32_t PWMSR;                             /**< PWM Status Register, offset: 0x4 */
84457   __IO uint32_t PWMIR;                             /**< PWM Interrupt Register, offset: 0x8 */
84458   __IO uint32_t PWMSAR;                            /**< PWM Sample Register, offset: 0xC */
84459   __IO uint32_t PWMPR;                             /**< PWM Period Register, offset: 0x10 */
84460   __I  uint32_t PWMCNR;                            /**< PWM Counter Register, offset: 0x14 */
84461 } PWM_Type;
84462 
84463 /* ----------------------------------------------------------------------------
84464    -- PWM Register Masks
84465    ---------------------------------------------------------------------------- */
84466 
84467 /*!
84468  * @addtogroup PWM_Register_Masks PWM Register Masks
84469  * @{
84470  */
84471 
84472 /*! @name PWMCR - PWM Control Register */
84473 /*! @{ */
84474 
84475 #define PWM_PWMCR_EN_MASK                        (0x1U)
84476 #define PWM_PWMCR_EN_SHIFT                       (0U)
84477 /*! EN
84478  *  0b0..PWM disabled
84479  *  0b1..PWM enabled
84480  */
84481 #define PWM_PWMCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK)
84482 
84483 #define PWM_PWMCR_REPEAT_MASK                    (0x6U)
84484 #define PWM_PWMCR_REPEAT_SHIFT                   (1U)
84485 /*! REPEAT
84486  *  0b00..Use each sample once
84487  *  0b01..Use each sample twice
84488  *  0b10..Use each sample four times
84489  *  0b11..Use each sample eight times
84490  */
84491 #define PWM_PWMCR_REPEAT(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK)
84492 
84493 #define PWM_PWMCR_SWR_MASK                       (0x8U)
84494 #define PWM_PWMCR_SWR_SHIFT                      (3U)
84495 /*! SWR
84496  *  0b0..PWM is out of reset
84497  *  0b1..PWM is undergoing reset
84498  */
84499 #define PWM_PWMCR_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK)
84500 
84501 #define PWM_PWMCR_PRESCALER_MASK                 (0xFFF0U)
84502 #define PWM_PWMCR_PRESCALER_SHIFT                (4U)
84503 /*! PRESCALER
84504  *  0b000000000000..Divide by 1
84505  *  0b000000000001..Divide by 2
84506  *  0b111111111111..Divide by 4096
84507  */
84508 #define PWM_PWMCR_PRESCALER(x)                   (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK)
84509 
84510 #define PWM_PWMCR_CLKSRC_MASK                    (0x30000U)
84511 #define PWM_PWMCR_CLKSRC_SHIFT                   (16U)
84512 /*! CLKSRC
84513  *  0b00..Clock is off
84514  *  0b01..ipg_clk
84515  *  0b10..ipg_clk_highfreq
84516  *  0b11..ipg_clk_32k
84517  */
84518 #define PWM_PWMCR_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK)
84519 
84520 #define PWM_PWMCR_POUTC_MASK                     (0xC0000U)
84521 #define PWM_PWMCR_POUTC_SHIFT                    (18U)
84522 /*! POUTC
84523  *  0b00..Output pin is set at rollover and cleared at comparison
84524  *  0b01..Output pin is cleared at rollover and set at comparison
84525  *  0b10..PWM output is disconnected
84526  *  0b11..PWM output is disconnected
84527  */
84528 #define PWM_PWMCR_POUTC(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK)
84529 
84530 #define PWM_PWMCR_HCTR_MASK                      (0x100000U)
84531 #define PWM_PWMCR_HCTR_SHIFT                     (20U)
84532 /*! HCTR
84533  *  0b0..Half word swapping does not take place
84534  *  0b1..Half words from write data bus are swapped
84535  */
84536 #define PWM_PWMCR_HCTR(x)                        (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK)
84537 
84538 #define PWM_PWMCR_BCTR_MASK                      (0x200000U)
84539 #define PWM_PWMCR_BCTR_SHIFT                     (21U)
84540 /*! BCTR
84541  *  0b0..byte ordering remains the same
84542  *  0b1..byte ordering is reversed
84543  */
84544 #define PWM_PWMCR_BCTR(x)                        (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK)
84545 
84546 #define PWM_PWMCR_DBGEN_MASK                     (0x400000U)
84547 #define PWM_PWMCR_DBGEN_SHIFT                    (22U)
84548 /*! DBGEN
84549  *  0b0..Inactive in debug mode
84550  *  0b1..Active in debug mode
84551  */
84552 #define PWM_PWMCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK)
84553 
84554 #define PWM_PWMCR_WAITEN_MASK                    (0x800000U)
84555 #define PWM_PWMCR_WAITEN_SHIFT                   (23U)
84556 /*! WAITEN
84557  *  0b0..Inactive in wait mode
84558  *  0b1..Active in wait mode
84559  */
84560 #define PWM_PWMCR_WAITEN(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK)
84561 
84562 #define PWM_PWMCR_DOZEN_MASK                     (0x1000000U)
84563 #define PWM_PWMCR_DOZEN_SHIFT                    (24U)
84564 /*! DOZEN
84565  *  0b0..Inactive in doze mode
84566  *  0b1..Active in doze mode
84567  */
84568 #define PWM_PWMCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK)
84569 
84570 #define PWM_PWMCR_STOPEN_MASK                    (0x2000000U)
84571 #define PWM_PWMCR_STOPEN_SHIFT                   (25U)
84572 /*! STOPEN
84573  *  0b0..Inactive in stop mode
84574  *  0b1..Active in stop mode
84575  */
84576 #define PWM_PWMCR_STOPEN(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK)
84577 
84578 #define PWM_PWMCR_FWM_MASK                       (0xC000000U)
84579 #define PWM_PWMCR_FWM_SHIFT                      (26U)
84580 /*! FWM
84581  *  0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
84582  *  0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
84583  *  0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
84584  *  0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
84585  */
84586 #define PWM_PWMCR_FWM(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK)
84587 /*! @} */
84588 
84589 /*! @name PWMSR - PWM Status Register */
84590 /*! @{ */
84591 
84592 #define PWM_PWMSR_FIFOAV_MASK                    (0x7U)
84593 #define PWM_PWMSR_FIFOAV_SHIFT                   (0U)
84594 /*! FIFOAV
84595  *  0b000..No data available
84596  *  0b001..1 word of data in FIFO
84597  *  0b010..2 words of data in FIFO
84598  *  0b011..3 words of data in FIFO
84599  *  0b100..4 words of data in FIFO
84600  *  0b101..unused
84601  *  0b110..unused
84602  *  0b111..unused
84603  */
84604 #define PWM_PWMSR_FIFOAV(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK)
84605 
84606 #define PWM_PWMSR_FE_MASK                        (0x8U)
84607 #define PWM_PWMSR_FE_SHIFT                       (3U)
84608 /*! FE
84609  *  0b0..Data level is above water mark
84610  *  0b1..When the data level falls below the mark set by FWM field
84611  */
84612 #define PWM_PWMSR_FE(x)                          (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK)
84613 
84614 #define PWM_PWMSR_ROV_MASK                       (0x10U)
84615 #define PWM_PWMSR_ROV_SHIFT                      (4U)
84616 /*! ROV
84617  *  0b0..Roll-over event not occurred
84618  *  0b1..Roll-over event occurred
84619  */
84620 #define PWM_PWMSR_ROV(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK)
84621 
84622 #define PWM_PWMSR_CMP_MASK                       (0x20U)
84623 #define PWM_PWMSR_CMP_SHIFT                      (5U)
84624 /*! CMP
84625  *  0b0..Compare event not occurred
84626  *  0b1..Compare event occurred
84627  */
84628 #define PWM_PWMSR_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK)
84629 
84630 #define PWM_PWMSR_FWE_MASK                       (0x40U)
84631 #define PWM_PWMSR_FWE_SHIFT                      (6U)
84632 /*! FWE
84633  *  0b0..FIFO write error not occurred
84634  *  0b1..FIFO write error occurred
84635  */
84636 #define PWM_PWMSR_FWE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK)
84637 /*! @} */
84638 
84639 /*! @name PWMIR - PWM Interrupt Register */
84640 /*! @{ */
84641 
84642 #define PWM_PWMIR_FIE_MASK                       (0x1U)
84643 #define PWM_PWMIR_FIE_SHIFT                      (0U)
84644 /*! FIE
84645  *  0b0..FIFO Empty interrupt disabled
84646  *  0b1..FIFO Empty interrupt enabled
84647  */
84648 #define PWM_PWMIR_FIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK)
84649 
84650 #define PWM_PWMIR_RIE_MASK                       (0x2U)
84651 #define PWM_PWMIR_RIE_SHIFT                      (1U)
84652 /*! RIE
84653  *  0b0..Roll-over interrupt not enabled
84654  *  0b1..Roll-over Interrupt enabled
84655  */
84656 #define PWM_PWMIR_RIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK)
84657 
84658 #define PWM_PWMIR_CIE_MASK                       (0x4U)
84659 #define PWM_PWMIR_CIE_SHIFT                      (2U)
84660 /*! CIE
84661  *  0b0..Compare Interrupt not enabled
84662  *  0b1..Compare Interrupt enabled
84663  */
84664 #define PWM_PWMIR_CIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK)
84665 /*! @} */
84666 
84667 /*! @name PWMSAR - PWM Sample Register */
84668 /*! @{ */
84669 
84670 #define PWM_PWMSAR_SAMPLE_MASK                   (0xFFFFU)
84671 #define PWM_PWMSAR_SAMPLE_SHIFT                  (0U)
84672 #define PWM_PWMSAR_SAMPLE(x)                     (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK)
84673 /*! @} */
84674 
84675 /*! @name PWMPR - PWM Period Register */
84676 /*! @{ */
84677 
84678 #define PWM_PWMPR_PERIOD_MASK                    (0xFFFFU)
84679 #define PWM_PWMPR_PERIOD_SHIFT                   (0U)
84680 #define PWM_PWMPR_PERIOD(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK)
84681 /*! @} */
84682 
84683 /*! @name PWMCNR - PWM Counter Register */
84684 /*! @{ */
84685 
84686 #define PWM_PWMCNR_COUNT_MASK                    (0xFFFFU)
84687 #define PWM_PWMCNR_COUNT_SHIFT                   (0U)
84688 #define PWM_PWMCNR_COUNT(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK)
84689 /*! @} */
84690 
84691 
84692 /*!
84693  * @}
84694  */ /* end of group PWM_Register_Masks */
84695 
84696 
84697 /* PWM - Peripheral instance base addresses */
84698 /** Peripheral PWM1 base address */
84699 #define PWM1_BASE                                (0x30660000u)
84700 /** Peripheral PWM1 base pointer */
84701 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
84702 /** Peripheral PWM2 base address */
84703 #define PWM2_BASE                                (0x30670000u)
84704 /** Peripheral PWM2 base pointer */
84705 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
84706 /** Peripheral PWM3 base address */
84707 #define PWM3_BASE                                (0x30680000u)
84708 /** Peripheral PWM3 base pointer */
84709 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
84710 /** Peripheral PWM4 base address */
84711 #define PWM4_BASE                                (0x30690000u)
84712 /** Peripheral PWM4 base pointer */
84713 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
84714 /** Array initializer of PWM peripheral base addresses */
84715 #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
84716 /** Array initializer of PWM peripheral base pointers */
84717 #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
84718 /** Interrupt vectors for the PWM peripheral type */
84719 #define PWM_IRQS                                 { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn }
84720 
84721 /*!
84722  * @}
84723  */ /* end of group PWM_Peripheral_Access_Layer */
84724 
84725 
84726 /* ----------------------------------------------------------------------------
84727    -- RDC Peripheral Access Layer
84728    ---------------------------------------------------------------------------- */
84729 
84730 /*!
84731  * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
84732  * @{
84733  */
84734 
84735 /** RDC - Register Layout Typedef */
84736 typedef struct {
84737   __I  uint32_t VIR;                               /**< Version Information, offset: 0x0 */
84738        uint8_t RESERVED_0[32];
84739   __IO uint32_t STAT;                              /**< Status, offset: 0x24 */
84740   __IO uint32_t INTCTRL;                           /**< Interrupt and Control, offset: 0x28 */
84741   __IO uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x2C */
84742        uint8_t RESERVED_1[464];
84743   __IO uint32_t MDA[40];                           /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
84744        uint8_t RESERVED_2[352];
84745   __IO uint32_t PDAP[112];                         /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
84746        uint8_t RESERVED_3[576];
84747   struct {                                         /* offset: 0x800, array step: 0x10 */
84748     __IO uint32_t MRSA;                              /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
84749     __IO uint32_t MREA;                              /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
84750     __IO uint32_t MRC;                               /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
84751     __IO uint32_t MRVS;                              /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
84752   } MR[77];
84753 } RDC_Type;
84754 
84755 /* ----------------------------------------------------------------------------
84756    -- RDC Register Masks
84757    ---------------------------------------------------------------------------- */
84758 
84759 /*!
84760  * @addtogroup RDC_Register_Masks RDC Register Masks
84761  * @{
84762  */
84763 
84764 /*! @name VIR - Version Information */
84765 /*! @{ */
84766 
84767 #define RDC_VIR_NDID_MASK                        (0xFU)
84768 #define RDC_VIR_NDID_SHIFT                       (0U)
84769 /*! NDID - Number of Domains */
84770 #define RDC_VIR_NDID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
84771 
84772 #define RDC_VIR_NMSTR_MASK                       (0xFF0U)
84773 #define RDC_VIR_NMSTR_SHIFT                      (4U)
84774 /*! NMSTR - Number of Masters */
84775 #define RDC_VIR_NMSTR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
84776 
84777 #define RDC_VIR_NPER_MASK                        (0xFF000U)
84778 #define RDC_VIR_NPER_SHIFT                       (12U)
84779 /*! NPER - Number of Peripherals */
84780 #define RDC_VIR_NPER(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
84781 
84782 #define RDC_VIR_NRGN_MASK                        (0xFF00000U)
84783 #define RDC_VIR_NRGN_SHIFT                       (20U)
84784 /*! NRGN - Number of Memory Regions */
84785 #define RDC_VIR_NRGN(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
84786 /*! @} */
84787 
84788 /*! @name STAT - Status */
84789 /*! @{ */
84790 
84791 #define RDC_STAT_DID_MASK                        (0xFU)
84792 #define RDC_STAT_DID_SHIFT                       (0U)
84793 /*! DID - Domain ID */
84794 #define RDC_STAT_DID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
84795 
84796 #define RDC_STAT_PDS_MASK                        (0x100U)
84797 #define RDC_STAT_PDS_SHIFT                       (8U)
84798 /*! PDS - Power Domain Status
84799  *  0b0..Power Down Domain is OFF
84800  *  0b1..Power Down Domain is ON
84801  */
84802 #define RDC_STAT_PDS(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
84803 /*! @} */
84804 
84805 /*! @name INTCTRL - Interrupt and Control */
84806 /*! @{ */
84807 
84808 #define RDC_INTCTRL_RCI_EN_MASK                  (0x1U)
84809 #define RDC_INTCTRL_RCI_EN_SHIFT                 (0U)
84810 /*! RCI_EN - Restoration Complete Interrupt
84811  *  0b0..Interrupt Disabled
84812  *  0b1..Interrupt Enabled
84813  */
84814 #define RDC_INTCTRL_RCI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
84815 /*! @} */
84816 
84817 /*! @name INTSTAT - Interrupt Status */
84818 /*! @{ */
84819 
84820 #define RDC_INTSTAT_INT_MASK                     (0x1U)
84821 #define RDC_INTSTAT_INT_SHIFT                    (0U)
84822 /*! INT - Interrupt Status
84823  *  0b0..No Interrupt Pending
84824  *  0b1..Interrupt Pending
84825  */
84826 #define RDC_INTSTAT_INT(x)                       (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
84827 /*! @} */
84828 
84829 /*! @name MDA - Master Domain Assignment */
84830 /*! @{ */
84831 
84832 #define RDC_MDA_DID_MASK                         (0x3U)
84833 #define RDC_MDA_DID_SHIFT                        (0U)
84834 /*! DID - Domain ID
84835  *  0b00..Master assigned to Processing Domain 0
84836  *  0b01..Master assigned to Processing Domain 1
84837  *  0b10..Master assigned to Processing Domain 2
84838  *  0b11..Master assigned to Processing Domain 3
84839  */
84840 #define RDC_MDA_DID(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
84841 
84842 #define RDC_MDA_LCK_MASK                         (0x80000000U)
84843 #define RDC_MDA_LCK_SHIFT                        (31U)
84844 /*! LCK - Assignment Lock
84845  *  0b0..Not Locked
84846  *  0b1..Locked
84847  */
84848 #define RDC_MDA_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
84849 /*! @} */
84850 
84851 /* The count of RDC_MDA */
84852 #define RDC_MDA_COUNT                            (40U)
84853 
84854 /*! @name PDAP - Peripheral Domain Access Permissions */
84855 /*! @{ */
84856 
84857 #define RDC_PDAP_D0W_MASK                        (0x1U)
84858 #define RDC_PDAP_D0W_SHIFT                       (0U)
84859 /*! D0W - Domain 0 Write Access
84860  *  0b0..No Write Access
84861  *  0b1..Write Access Allowed
84862  */
84863 #define RDC_PDAP_D0W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
84864 
84865 #define RDC_PDAP_D0R_MASK                        (0x2U)
84866 #define RDC_PDAP_D0R_SHIFT                       (1U)
84867 /*! D0R - Domain 0 Read Access
84868  *  0b0..No Read Access
84869  *  0b1..Read Access Allowed
84870  */
84871 #define RDC_PDAP_D0R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
84872 
84873 #define RDC_PDAP_D1W_MASK                        (0x4U)
84874 #define RDC_PDAP_D1W_SHIFT                       (2U)
84875 /*! D1W - Domain 1 Write Access
84876  *  0b0..No Write Access
84877  *  0b1..Write Access Allowed
84878  */
84879 #define RDC_PDAP_D1W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
84880 
84881 #define RDC_PDAP_D1R_MASK                        (0x8U)
84882 #define RDC_PDAP_D1R_SHIFT                       (3U)
84883 /*! D1R - Domain 1 Read Access
84884  *  0b0..No Read Access
84885  *  0b1..Read Access Allowed
84886  */
84887 #define RDC_PDAP_D1R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
84888 
84889 #define RDC_PDAP_D2W_MASK                        (0x10U)
84890 #define RDC_PDAP_D2W_SHIFT                       (4U)
84891 /*! D2W - Domain 2 Write Access
84892  *  0b0..No Write Access
84893  *  0b1..Write Access Allowed
84894  */
84895 #define RDC_PDAP_D2W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK)
84896 
84897 #define RDC_PDAP_D2R_MASK                        (0x20U)
84898 #define RDC_PDAP_D2R_SHIFT                       (5U)
84899 /*! D2R - Domain 2 Read Access
84900  *  0b0..No Read Access
84901  *  0b1..Read Access Allowed
84902  */
84903 #define RDC_PDAP_D2R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK)
84904 
84905 #define RDC_PDAP_D3W_MASK                        (0x40U)
84906 #define RDC_PDAP_D3W_SHIFT                       (6U)
84907 /*! D3W - Domain 3 Write Access
84908  *  0b0..No Write Access
84909  *  0b1..Write Access Allowed
84910  */
84911 #define RDC_PDAP_D3W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK)
84912 
84913 #define RDC_PDAP_D3R_MASK                        (0x80U)
84914 #define RDC_PDAP_D3R_SHIFT                       (7U)
84915 /*! D3R - Domain 3 Read Access
84916  *  0b0..No Read Access
84917  *  0b1..Read Access Allowed
84918  */
84919 #define RDC_PDAP_D3R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK)
84920 
84921 #define RDC_PDAP_SREQ_MASK                       (0x40000000U)
84922 #define RDC_PDAP_SREQ_SHIFT                      (30U)
84923 /*! SREQ - Semaphore Required
84924  *  0b0..Semaphores have no effect
84925  *  0b1..Semaphores are enforced
84926  */
84927 #define RDC_PDAP_SREQ(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
84928 
84929 #define RDC_PDAP_LCK_MASK                        (0x80000000U)
84930 #define RDC_PDAP_LCK_SHIFT                       (31U)
84931 /*! LCK - Peripheral Permissions Lock
84932  *  0b0..Not Locked
84933  *  0b1..Locked
84934  */
84935 #define RDC_PDAP_LCK(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
84936 /*! @} */
84937 
84938 /* The count of RDC_PDAP */
84939 #define RDC_PDAP_COUNT                           (112U)
84940 
84941 /*! @name MRSA - Memory Region Start Address */
84942 /*! @{ */
84943 
84944 #define RDC_MRSA_SADR_MASK                       (0xFFFFFF80U)
84945 #define RDC_MRSA_SADR_SHIFT                      (7U)
84946 /*! SADR - Start address for memory region */
84947 #define RDC_MRSA_SADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
84948 /*! @} */
84949 
84950 /* The count of RDC_MRSA */
84951 #define RDC_MRSA_COUNT                           (77U)
84952 
84953 /*! @name MREA - Memory Region End Address */
84954 /*! @{ */
84955 
84956 #define RDC_MREA_EADR_MASK                       (0xFFFFFF80U)
84957 #define RDC_MREA_EADR_SHIFT                      (7U)
84958 /*! EADR - Upper bound for memory region */
84959 #define RDC_MREA_EADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
84960 /*! @} */
84961 
84962 /* The count of RDC_MREA */
84963 #define RDC_MREA_COUNT                           (77U)
84964 
84965 /*! @name MRC - Memory Region Control */
84966 /*! @{ */
84967 
84968 #define RDC_MRC_D0W_MASK                         (0x1U)
84969 #define RDC_MRC_D0W_SHIFT                        (0U)
84970 /*! D0W - Domain 0 Write Access to Region
84971  *  0b0..Processing Domain 0 does not have Write access to the memory region
84972  *  0b1..Processing Domain 0 has Write access to the memory region
84973  */
84974 #define RDC_MRC_D0W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
84975 
84976 #define RDC_MRC_D0R_MASK                         (0x2U)
84977 #define RDC_MRC_D0R_SHIFT                        (1U)
84978 /*! D0R - Domain 0 Read Access to Region
84979  *  0b0..Processing Domain 0 does not have Read access to the memory region
84980  *  0b1..Processing Domain 0 has Read access to the memory region
84981  */
84982 #define RDC_MRC_D0R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
84983 
84984 #define RDC_MRC_D1W_MASK                         (0x4U)
84985 #define RDC_MRC_D1W_SHIFT                        (2U)
84986 /*! D1W - Domain 1 Write Access to Region
84987  *  0b0..Processing Domain 1 does not have Write access to the memory region
84988  *  0b1..Processing Domain 1 has Write access to the memory region
84989  */
84990 #define RDC_MRC_D1W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
84991 
84992 #define RDC_MRC_D1R_MASK                         (0x8U)
84993 #define RDC_MRC_D1R_SHIFT                        (3U)
84994 /*! D1R - Domain 1 Read Access to Region
84995  *  0b0..Processing Domain 1 does not have Read access to the memory region
84996  *  0b1..Processing Domain 1 has Read access to the memory region
84997  */
84998 #define RDC_MRC_D1R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
84999 
85000 #define RDC_MRC_D2W_MASK                         (0x10U)
85001 #define RDC_MRC_D2W_SHIFT                        (4U)
85002 /*! D2W - Domain 2 Write Access to Region
85003  *  0b0..Processing Domain 2 does not have Write access to the memory region
85004  *  0b1..Processing Domain 2 has Write access to the memory region
85005  */
85006 #define RDC_MRC_D2W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK)
85007 
85008 #define RDC_MRC_D2R_MASK                         (0x20U)
85009 #define RDC_MRC_D2R_SHIFT                        (5U)
85010 /*! D2R - Domain 2 Read Access to Region
85011  *  0b0..Processing Domain 2 does not have Read access to the memory region
85012  *  0b1..Processing Domain 2 has Read access to the memory region
85013  */
85014 #define RDC_MRC_D2R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK)
85015 
85016 #define RDC_MRC_D3W_MASK                         (0x40U)
85017 #define RDC_MRC_D3W_SHIFT                        (6U)
85018 /*! D3W - Domain 3 Write Access to Region
85019  *  0b0..Processing Domain 3 does not have Write access to the memory region
85020  *  0b1..Processing Domain 3 has Read access to the memory region
85021  */
85022 #define RDC_MRC_D3W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK)
85023 
85024 #define RDC_MRC_D3R_MASK                         (0x80U)
85025 #define RDC_MRC_D3R_SHIFT                        (7U)
85026 /*! D3R - Domain 3 Read Access to Region
85027  *  0b0..Processing Domain 3 does not have Read access to the memory region
85028  *  0b1..Processing Domain 3 has Read access to the memory region
85029  */
85030 #define RDC_MRC_D3R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK)
85031 
85032 #define RDC_MRC_ENA_MASK                         (0x40000000U)
85033 #define RDC_MRC_ENA_SHIFT                        (30U)
85034 /*! ENA - Region Enable
85035  *  0b0..Memory region is not defined or restricted.
85036  *  0b1..Memory boundaries, domain permissions and controls are in effect.
85037  */
85038 #define RDC_MRC_ENA(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
85039 
85040 #define RDC_MRC_LCK_MASK                         (0x80000000U)
85041 #define RDC_MRC_LCK_SHIFT                        (31U)
85042 /*! LCK - Region Lock
85043  *  0b0..No Lock. All fields in this register may be modified.
85044  *  0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
85045  */
85046 #define RDC_MRC_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
85047 /*! @} */
85048 
85049 /* The count of RDC_MRC */
85050 #define RDC_MRC_COUNT                            (77U)
85051 
85052 /*! @name MRVS - Memory Region Violation Status */
85053 /*! @{ */
85054 
85055 #define RDC_MRVS_VDID_MASK                       (0x3U)
85056 #define RDC_MRVS_VDID_SHIFT                      (0U)
85057 /*! VDID - Violating Domain ID
85058  *  0b00..Processing Domain 0
85059  *  0b01..Processing Domain 1
85060  *  0b10..Processing Domain 2
85061  *  0b11..Processing Domain 3
85062  */
85063 #define RDC_MRVS_VDID(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
85064 
85065 #define RDC_MRVS_AD_MASK                         (0x10U)
85066 #define RDC_MRVS_AD_SHIFT                        (4U)
85067 /*! AD - Access Denied */
85068 #define RDC_MRVS_AD(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
85069 
85070 #define RDC_MRVS_VADR_MASK                       (0xFFFFFFE0U)
85071 #define RDC_MRVS_VADR_SHIFT                      (5U)
85072 /*! VADR - Violating Address */
85073 #define RDC_MRVS_VADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
85074 /*! @} */
85075 
85076 /* The count of RDC_MRVS */
85077 #define RDC_MRVS_COUNT                           (77U)
85078 
85079 
85080 /*!
85081  * @}
85082  */ /* end of group RDC_Register_Masks */
85083 
85084 
85085 /* RDC - Peripheral instance base addresses */
85086 /** Peripheral RDC base address */
85087 #define RDC_BASE                                 (0x303D0000u)
85088 /** Peripheral RDC base pointer */
85089 #define RDC                                      ((RDC_Type *)RDC_BASE)
85090 /** Array initializer of RDC peripheral base addresses */
85091 #define RDC_BASE_ADDRS                           { RDC_BASE }
85092 /** Array initializer of RDC peripheral base pointers */
85093 #define RDC_BASE_PTRS                            { RDC }
85094 /** Interrupt vectors for the RDC peripheral type */
85095 #define RDC_IRQS                                 { RDC_IRQn }
85096 
85097 /*!
85098  * @}
85099  */ /* end of group RDC_Peripheral_Access_Layer */
85100 
85101 
85102 /* ----------------------------------------------------------------------------
85103    -- RDC_SEMAPHORE Peripheral Access Layer
85104    ---------------------------------------------------------------------------- */
85105 
85106 /*!
85107  * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
85108  * @{
85109  */
85110 
85111 /** RDC_SEMAPHORE - Register Layout Typedef */
85112 typedef struct {
85113   __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x0 */
85114   __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x1 */
85115   __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x2 */
85116   __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x3 */
85117   __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x4 */
85118   __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x5 */
85119   __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x6 */
85120   __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x7 */
85121   __IO uint8_t GATE8;                              /**< Gate Register, offset: 0x8 */
85122   __IO uint8_t GATE9;                              /**< Gate Register, offset: 0x9 */
85123   __IO uint8_t GATE10;                             /**< Gate Register, offset: 0xA */
85124   __IO uint8_t GATE11;                             /**< Gate Register, offset: 0xB */
85125   __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xC */
85126   __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xD */
85127   __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xE */
85128   __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xF */
85129   __IO uint8_t GATE16;                             /**< Gate Register, offset: 0x10 */
85130   __IO uint8_t GATE17;                             /**< Gate Register, offset: 0x11 */
85131   __IO uint8_t GATE18;                             /**< Gate Register, offset: 0x12 */
85132   __IO uint8_t GATE19;                             /**< Gate Register, offset: 0x13 */
85133   __IO uint8_t GATE20;                             /**< Gate Register, offset: 0x14 */
85134   __IO uint8_t GATE21;                             /**< Gate Register, offset: 0x15 */
85135   __IO uint8_t GATE22;                             /**< Gate Register, offset: 0x16 */
85136   __IO uint8_t GATE23;                             /**< Gate Register, offset: 0x17 */
85137   __IO uint8_t GATE24;                             /**< Gate Register, offset: 0x18 */
85138   __IO uint8_t GATE25;                             /**< Gate Register, offset: 0x19 */
85139   __IO uint8_t GATE26;                             /**< Gate Register, offset: 0x1A */
85140   __IO uint8_t GATE27;                             /**< Gate Register, offset: 0x1B */
85141   __IO uint8_t GATE28;                             /**< Gate Register, offset: 0x1C */
85142   __IO uint8_t GATE29;                             /**< Gate Register, offset: 0x1D */
85143   __IO uint8_t GATE30;                             /**< Gate Register, offset: 0x1E */
85144   __IO uint8_t GATE31;                             /**< Gate Register, offset: 0x1F */
85145   __IO uint8_t GATE32;                             /**< Gate Register, offset: 0x20 */
85146   __IO uint8_t GATE33;                             /**< Gate Register, offset: 0x21 */
85147   __IO uint8_t GATE34;                             /**< Gate Register, offset: 0x22 */
85148   __IO uint8_t GATE35;                             /**< Gate Register, offset: 0x23 */
85149   __IO uint8_t GATE36;                             /**< Gate Register, offset: 0x24 */
85150   __IO uint8_t GATE37;                             /**< Gate Register, offset: 0x25 */
85151   __IO uint8_t GATE38;                             /**< Gate Register, offset: 0x26 */
85152   __IO uint8_t GATE39;                             /**< Gate Register, offset: 0x27 */
85153   __IO uint8_t GATE40;                             /**< Gate Register, offset: 0x28 */
85154   __IO uint8_t GATE41;                             /**< Gate Register, offset: 0x29 */
85155   __IO uint8_t GATE42;                             /**< Gate Register, offset: 0x2A */
85156   __IO uint8_t GATE43;                             /**< Gate Register, offset: 0x2B */
85157   __IO uint8_t GATE44;                             /**< Gate Register, offset: 0x2C */
85158   __IO uint8_t GATE45;                             /**< Gate Register, offset: 0x2D */
85159   __IO uint8_t GATE46;                             /**< Gate Register, offset: 0x2E */
85160   __IO uint8_t GATE47;                             /**< Gate Register, offset: 0x2F */
85161   __IO uint8_t GATE48;                             /**< Gate Register, offset: 0x30 */
85162   __IO uint8_t GATE49;                             /**< Gate Register, offset: 0x31 */
85163   __IO uint8_t GATE50;                             /**< Gate Register, offset: 0x32 */
85164   __IO uint8_t GATE51;                             /**< Gate Register, offset: 0x33 */
85165   __IO uint8_t GATE52;                             /**< Gate Register, offset: 0x34 */
85166   __IO uint8_t GATE53;                             /**< Gate Register, offset: 0x35 */
85167   __IO uint8_t GATE54;                             /**< Gate Register, offset: 0x36 */
85168   __IO uint8_t GATE55;                             /**< Gate Register, offset: 0x37 */
85169   __IO uint8_t GATE56;                             /**< Gate Register, offset: 0x38 */
85170   __IO uint8_t GATE57;                             /**< Gate Register, offset: 0x39 */
85171   __IO uint8_t GATE58;                             /**< Gate Register, offset: 0x3A */
85172   __IO uint8_t GATE59;                             /**< Gate Register, offset: 0x3B */
85173   __IO uint8_t GATE60;                             /**< Gate Register, offset: 0x3C */
85174   __IO uint8_t GATE61;                             /**< Gate Register, offset: 0x3D */
85175   __IO uint8_t GATE62;                             /**< Gate Register, offset: 0x3E */
85176   __IO uint8_t GATE63;                             /**< Gate Register, offset: 0x3F */
85177        uint8_t RESERVED_0[2];
85178   union {                                          /* offset: 0x42 */
85179     __IO uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
85180     __IO uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
85181   };
85182 } RDC_SEMAPHORE_Type;
85183 
85184 /* ----------------------------------------------------------------------------
85185    -- RDC_SEMAPHORE Register Masks
85186    ---------------------------------------------------------------------------- */
85187 
85188 /*!
85189  * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
85190  * @{
85191  */
85192 
85193 /*! @name GATE0 - Gate Register */
85194 /*! @{ */
85195 
85196 #define RDC_SEMAPHORE_GATE0_GTFSM_MASK           (0xFU)
85197 #define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT          (0U)
85198 /*! GTFSM - Gate Finite State Machine.
85199  *  0b0000..The gate is unlocked (free).
85200  *  0b0001..The gate has been locked by processor with master_index = 0.
85201  *  0b0010..The gate has been locked by processor with master_index = 1.
85202  *  0b0011..The gate has been locked by processor with master_index = 2.
85203  *  0b0100..The gate has been locked by processor with master_index = 3.
85204  *  0b0101..The gate has been locked by processor with master_index = 4.
85205  *  0b0110..The gate has been locked by processor with master_index = 5.
85206  *  0b0111..The gate has been locked by processor with master_index = 6.
85207  *  0b1000..The gate has been locked by processor with master_index = 7.
85208  *  0b1001..The gate has been locked by processor with master_index = 8.
85209  *  0b1010..The gate has been locked by processor with master_index = 9.
85210  *  0b1011..The gate has been locked by processor with master_index = 10.
85211  *  0b1100..The gate has been locked by processor with master_index = 11.
85212  *  0b1101..The gate has been locked by processor with master_index = 12.
85213  *  0b1110..The gate has been locked by processor with master_index = 13.
85214  *  0b1111..The gate has been locked by processor with master_index = 14.
85215  */
85216 #define RDC_SEMAPHORE_GATE0_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK)
85217 
85218 #define RDC_SEMAPHORE_GATE0_LDOM_MASK            (0x30U)
85219 #define RDC_SEMAPHORE_GATE0_LDOM_SHIFT           (4U)
85220 /*! LDOM
85221  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85222  *  0b01..The gate has been locked by domain 1.
85223  *  0b10..The gate has been locked by domain 2.
85224  *  0b11..The gate has been locked by domain 3.
85225  */
85226 #define RDC_SEMAPHORE_GATE0_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK)
85227 /*! @} */
85228 
85229 /*! @name GATE1 - Gate Register */
85230 /*! @{ */
85231 
85232 #define RDC_SEMAPHORE_GATE1_GTFSM_MASK           (0xFU)
85233 #define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT          (0U)
85234 /*! GTFSM - Gate Finite State Machine.
85235  *  0b0000..The gate is unlocked (free).
85236  *  0b0001..The gate has been locked by processor with master_index = 0.
85237  *  0b0010..The gate has been locked by processor with master_index = 1.
85238  *  0b0011..The gate has been locked by processor with master_index = 2.
85239  *  0b0100..The gate has been locked by processor with master_index = 3.
85240  *  0b0101..The gate has been locked by processor with master_index = 4.
85241  *  0b0110..The gate has been locked by processor with master_index = 5.
85242  *  0b0111..The gate has been locked by processor with master_index = 6.
85243  *  0b1000..The gate has been locked by processor with master_index = 7.
85244  *  0b1001..The gate has been locked by processor with master_index = 8.
85245  *  0b1010..The gate has been locked by processor with master_index = 9.
85246  *  0b1011..The gate has been locked by processor with master_index = 10.
85247  *  0b1100..The gate has been locked by processor with master_index = 11.
85248  *  0b1101..The gate has been locked by processor with master_index = 12.
85249  *  0b1110..The gate has been locked by processor with master_index = 13.
85250  *  0b1111..The gate has been locked by processor with master_index = 14.
85251  */
85252 #define RDC_SEMAPHORE_GATE1_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK)
85253 
85254 #define RDC_SEMAPHORE_GATE1_LDOM_MASK            (0x30U)
85255 #define RDC_SEMAPHORE_GATE1_LDOM_SHIFT           (4U)
85256 /*! LDOM
85257  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85258  *  0b01..The gate has been locked by domain 1.
85259  *  0b10..The gate has been locked by domain 2.
85260  *  0b11..The gate has been locked by domain 3.
85261  */
85262 #define RDC_SEMAPHORE_GATE1_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK)
85263 /*! @} */
85264 
85265 /*! @name GATE2 - Gate Register */
85266 /*! @{ */
85267 
85268 #define RDC_SEMAPHORE_GATE2_GTFSM_MASK           (0xFU)
85269 #define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT          (0U)
85270 /*! GTFSM - Gate Finite State Machine.
85271  *  0b0000..The gate is unlocked (free).
85272  *  0b0001..The gate has been locked by processor with master_index = 0.
85273  *  0b0010..The gate has been locked by processor with master_index = 1.
85274  *  0b0011..The gate has been locked by processor with master_index = 2.
85275  *  0b0100..The gate has been locked by processor with master_index = 3.
85276  *  0b0101..The gate has been locked by processor with master_index = 4.
85277  *  0b0110..The gate has been locked by processor with master_index = 5.
85278  *  0b0111..The gate has been locked by processor with master_index = 6.
85279  *  0b1000..The gate has been locked by processor with master_index = 7.
85280  *  0b1001..The gate has been locked by processor with master_index = 8.
85281  *  0b1010..The gate has been locked by processor with master_index = 9.
85282  *  0b1011..The gate has been locked by processor with master_index = 10.
85283  *  0b1100..The gate has been locked by processor with master_index = 11.
85284  *  0b1101..The gate has been locked by processor with master_index = 12.
85285  *  0b1110..The gate has been locked by processor with master_index = 13.
85286  *  0b1111..The gate has been locked by processor with master_index = 14.
85287  */
85288 #define RDC_SEMAPHORE_GATE2_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK)
85289 
85290 #define RDC_SEMAPHORE_GATE2_LDOM_MASK            (0x30U)
85291 #define RDC_SEMAPHORE_GATE2_LDOM_SHIFT           (4U)
85292 /*! LDOM
85293  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85294  *  0b01..The gate has been locked by domain 1.
85295  *  0b10..The gate has been locked by domain 2.
85296  *  0b11..The gate has been locked by domain 3.
85297  */
85298 #define RDC_SEMAPHORE_GATE2_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK)
85299 /*! @} */
85300 
85301 /*! @name GATE3 - Gate Register */
85302 /*! @{ */
85303 
85304 #define RDC_SEMAPHORE_GATE3_GTFSM_MASK           (0xFU)
85305 #define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT          (0U)
85306 /*! GTFSM - Gate Finite State Machine.
85307  *  0b0000..The gate is unlocked (free).
85308  *  0b0001..The gate has been locked by processor with master_index = 0.
85309  *  0b0010..The gate has been locked by processor with master_index = 1.
85310  *  0b0011..The gate has been locked by processor with master_index = 2.
85311  *  0b0100..The gate has been locked by processor with master_index = 3.
85312  *  0b0101..The gate has been locked by processor with master_index = 4.
85313  *  0b0110..The gate has been locked by processor with master_index = 5.
85314  *  0b0111..The gate has been locked by processor with master_index = 6.
85315  *  0b1000..The gate has been locked by processor with master_index = 7.
85316  *  0b1001..The gate has been locked by processor with master_index = 8.
85317  *  0b1010..The gate has been locked by processor with master_index = 9.
85318  *  0b1011..The gate has been locked by processor with master_index = 10.
85319  *  0b1100..The gate has been locked by processor with master_index = 11.
85320  *  0b1101..The gate has been locked by processor with master_index = 12.
85321  *  0b1110..The gate has been locked by processor with master_index = 13.
85322  *  0b1111..The gate has been locked by processor with master_index = 14.
85323  */
85324 #define RDC_SEMAPHORE_GATE3_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK)
85325 
85326 #define RDC_SEMAPHORE_GATE3_LDOM_MASK            (0x30U)
85327 #define RDC_SEMAPHORE_GATE3_LDOM_SHIFT           (4U)
85328 /*! LDOM
85329  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85330  *  0b01..The gate has been locked by domain 1.
85331  *  0b10..The gate has been locked by domain 2.
85332  *  0b11..The gate has been locked by domain 3.
85333  */
85334 #define RDC_SEMAPHORE_GATE3_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK)
85335 /*! @} */
85336 
85337 /*! @name GATE4 - Gate Register */
85338 /*! @{ */
85339 
85340 #define RDC_SEMAPHORE_GATE4_GTFSM_MASK           (0xFU)
85341 #define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT          (0U)
85342 /*! GTFSM - Gate Finite State Machine.
85343  *  0b0000..The gate is unlocked (free).
85344  *  0b0001..The gate has been locked by processor with master_index = 0.
85345  *  0b0010..The gate has been locked by processor with master_index = 1.
85346  *  0b0011..The gate has been locked by processor with master_index = 2.
85347  *  0b0100..The gate has been locked by processor with master_index = 3.
85348  *  0b0101..The gate has been locked by processor with master_index = 4.
85349  *  0b0110..The gate has been locked by processor with master_index = 5.
85350  *  0b0111..The gate has been locked by processor with master_index = 6.
85351  *  0b1000..The gate has been locked by processor with master_index = 7.
85352  *  0b1001..The gate has been locked by processor with master_index = 8.
85353  *  0b1010..The gate has been locked by processor with master_index = 9.
85354  *  0b1011..The gate has been locked by processor with master_index = 10.
85355  *  0b1100..The gate has been locked by processor with master_index = 11.
85356  *  0b1101..The gate has been locked by processor with master_index = 12.
85357  *  0b1110..The gate has been locked by processor with master_index = 13.
85358  *  0b1111..The gate has been locked by processor with master_index = 14.
85359  */
85360 #define RDC_SEMAPHORE_GATE4_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK)
85361 
85362 #define RDC_SEMAPHORE_GATE4_LDOM_MASK            (0x30U)
85363 #define RDC_SEMAPHORE_GATE4_LDOM_SHIFT           (4U)
85364 /*! LDOM
85365  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85366  *  0b01..The gate has been locked by domain 1.
85367  *  0b10..The gate has been locked by domain 2.
85368  *  0b11..The gate has been locked by domain 3.
85369  */
85370 #define RDC_SEMAPHORE_GATE4_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK)
85371 /*! @} */
85372 
85373 /*! @name GATE5 - Gate Register */
85374 /*! @{ */
85375 
85376 #define RDC_SEMAPHORE_GATE5_GTFSM_MASK           (0xFU)
85377 #define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT          (0U)
85378 /*! GTFSM - Gate Finite State Machine.
85379  *  0b0000..The gate is unlocked (free).
85380  *  0b0001..The gate has been locked by processor with master_index = 0.
85381  *  0b0010..The gate has been locked by processor with master_index = 1.
85382  *  0b0011..The gate has been locked by processor with master_index = 2.
85383  *  0b0100..The gate has been locked by processor with master_index = 3.
85384  *  0b0101..The gate has been locked by processor with master_index = 4.
85385  *  0b0110..The gate has been locked by processor with master_index = 5.
85386  *  0b0111..The gate has been locked by processor with master_index = 6.
85387  *  0b1000..The gate has been locked by processor with master_index = 7.
85388  *  0b1001..The gate has been locked by processor with master_index = 8.
85389  *  0b1010..The gate has been locked by processor with master_index = 9.
85390  *  0b1011..The gate has been locked by processor with master_index = 10.
85391  *  0b1100..The gate has been locked by processor with master_index = 11.
85392  *  0b1101..The gate has been locked by processor with master_index = 12.
85393  *  0b1110..The gate has been locked by processor with master_index = 13.
85394  *  0b1111..The gate has been locked by processor with master_index = 14.
85395  */
85396 #define RDC_SEMAPHORE_GATE5_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK)
85397 
85398 #define RDC_SEMAPHORE_GATE5_LDOM_MASK            (0x30U)
85399 #define RDC_SEMAPHORE_GATE5_LDOM_SHIFT           (4U)
85400 /*! LDOM
85401  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85402  *  0b01..The gate has been locked by domain 1.
85403  *  0b10..The gate has been locked by domain 2.
85404  *  0b11..The gate has been locked by domain 3.
85405  */
85406 #define RDC_SEMAPHORE_GATE5_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK)
85407 /*! @} */
85408 
85409 /*! @name GATE6 - Gate Register */
85410 /*! @{ */
85411 
85412 #define RDC_SEMAPHORE_GATE6_GTFSM_MASK           (0xFU)
85413 #define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT          (0U)
85414 /*! GTFSM - Gate Finite State Machine.
85415  *  0b0000..The gate is unlocked (free).
85416  *  0b0001..The gate has been locked by processor with master_index = 0.
85417  *  0b0010..The gate has been locked by processor with master_index = 1.
85418  *  0b0011..The gate has been locked by processor with master_index = 2.
85419  *  0b0100..The gate has been locked by processor with master_index = 3.
85420  *  0b0101..The gate has been locked by processor with master_index = 4.
85421  *  0b0110..The gate has been locked by processor with master_index = 5.
85422  *  0b0111..The gate has been locked by processor with master_index = 6.
85423  *  0b1000..The gate has been locked by processor with master_index = 7.
85424  *  0b1001..The gate has been locked by processor with master_index = 8.
85425  *  0b1010..The gate has been locked by processor with master_index = 9.
85426  *  0b1011..The gate has been locked by processor with master_index = 10.
85427  *  0b1100..The gate has been locked by processor with master_index = 11.
85428  *  0b1101..The gate has been locked by processor with master_index = 12.
85429  *  0b1110..The gate has been locked by processor with master_index = 13.
85430  *  0b1111..The gate has been locked by processor with master_index = 14.
85431  */
85432 #define RDC_SEMAPHORE_GATE6_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK)
85433 
85434 #define RDC_SEMAPHORE_GATE6_LDOM_MASK            (0x30U)
85435 #define RDC_SEMAPHORE_GATE6_LDOM_SHIFT           (4U)
85436 /*! LDOM
85437  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85438  *  0b01..The gate has been locked by domain 1.
85439  *  0b10..The gate has been locked by domain 2.
85440  *  0b11..The gate has been locked by domain 3.
85441  */
85442 #define RDC_SEMAPHORE_GATE6_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK)
85443 /*! @} */
85444 
85445 /*! @name GATE7 - Gate Register */
85446 /*! @{ */
85447 
85448 #define RDC_SEMAPHORE_GATE7_GTFSM_MASK           (0xFU)
85449 #define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT          (0U)
85450 /*! GTFSM - Gate Finite State Machine.
85451  *  0b0000..The gate is unlocked (free).
85452  *  0b0001..The gate has been locked by processor with master_index = 0.
85453  *  0b0010..The gate has been locked by processor with master_index = 1.
85454  *  0b0011..The gate has been locked by processor with master_index = 2.
85455  *  0b0100..The gate has been locked by processor with master_index = 3.
85456  *  0b0101..The gate has been locked by processor with master_index = 4.
85457  *  0b0110..The gate has been locked by processor with master_index = 5.
85458  *  0b0111..The gate has been locked by processor with master_index = 6.
85459  *  0b1000..The gate has been locked by processor with master_index = 7.
85460  *  0b1001..The gate has been locked by processor with master_index = 8.
85461  *  0b1010..The gate has been locked by processor with master_index = 9.
85462  *  0b1011..The gate has been locked by processor with master_index = 10.
85463  *  0b1100..The gate has been locked by processor with master_index = 11.
85464  *  0b1101..The gate has been locked by processor with master_index = 12.
85465  *  0b1110..The gate has been locked by processor with master_index = 13.
85466  *  0b1111..The gate has been locked by processor with master_index = 14.
85467  */
85468 #define RDC_SEMAPHORE_GATE7_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK)
85469 
85470 #define RDC_SEMAPHORE_GATE7_LDOM_MASK            (0x30U)
85471 #define RDC_SEMAPHORE_GATE7_LDOM_SHIFT           (4U)
85472 /*! LDOM
85473  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85474  *  0b01..The gate has been locked by domain 1.
85475  *  0b10..The gate has been locked by domain 2.
85476  *  0b11..The gate has been locked by domain 3.
85477  */
85478 #define RDC_SEMAPHORE_GATE7_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK)
85479 /*! @} */
85480 
85481 /*! @name GATE8 - Gate Register */
85482 /*! @{ */
85483 
85484 #define RDC_SEMAPHORE_GATE8_GTFSM_MASK           (0xFU)
85485 #define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT          (0U)
85486 /*! GTFSM - Gate Finite State Machine.
85487  *  0b0000..The gate is unlocked (free).
85488  *  0b0001..The gate has been locked by processor with master_index = 0.
85489  *  0b0010..The gate has been locked by processor with master_index = 1.
85490  *  0b0011..The gate has been locked by processor with master_index = 2.
85491  *  0b0100..The gate has been locked by processor with master_index = 3.
85492  *  0b0101..The gate has been locked by processor with master_index = 4.
85493  *  0b0110..The gate has been locked by processor with master_index = 5.
85494  *  0b0111..The gate has been locked by processor with master_index = 6.
85495  *  0b1000..The gate has been locked by processor with master_index = 7.
85496  *  0b1001..The gate has been locked by processor with master_index = 8.
85497  *  0b1010..The gate has been locked by processor with master_index = 9.
85498  *  0b1011..The gate has been locked by processor with master_index = 10.
85499  *  0b1100..The gate has been locked by processor with master_index = 11.
85500  *  0b1101..The gate has been locked by processor with master_index = 12.
85501  *  0b1110..The gate has been locked by processor with master_index = 13.
85502  *  0b1111..The gate has been locked by processor with master_index = 14.
85503  */
85504 #define RDC_SEMAPHORE_GATE8_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK)
85505 
85506 #define RDC_SEMAPHORE_GATE8_LDOM_MASK            (0x30U)
85507 #define RDC_SEMAPHORE_GATE8_LDOM_SHIFT           (4U)
85508 /*! LDOM
85509  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85510  *  0b01..The gate has been locked by domain 1.
85511  *  0b10..The gate has been locked by domain 2.
85512  *  0b11..The gate has been locked by domain 3.
85513  */
85514 #define RDC_SEMAPHORE_GATE8_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK)
85515 /*! @} */
85516 
85517 /*! @name GATE9 - Gate Register */
85518 /*! @{ */
85519 
85520 #define RDC_SEMAPHORE_GATE9_GTFSM_MASK           (0xFU)
85521 #define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT          (0U)
85522 /*! GTFSM - Gate Finite State Machine.
85523  *  0b0000..The gate is unlocked (free).
85524  *  0b0001..The gate has been locked by processor with master_index = 0.
85525  *  0b0010..The gate has been locked by processor with master_index = 1.
85526  *  0b0011..The gate has been locked by processor with master_index = 2.
85527  *  0b0100..The gate has been locked by processor with master_index = 3.
85528  *  0b0101..The gate has been locked by processor with master_index = 4.
85529  *  0b0110..The gate has been locked by processor with master_index = 5.
85530  *  0b0111..The gate has been locked by processor with master_index = 6.
85531  *  0b1000..The gate has been locked by processor with master_index = 7.
85532  *  0b1001..The gate has been locked by processor with master_index = 8.
85533  *  0b1010..The gate has been locked by processor with master_index = 9.
85534  *  0b1011..The gate has been locked by processor with master_index = 10.
85535  *  0b1100..The gate has been locked by processor with master_index = 11.
85536  *  0b1101..The gate has been locked by processor with master_index = 12.
85537  *  0b1110..The gate has been locked by processor with master_index = 13.
85538  *  0b1111..The gate has been locked by processor with master_index = 14.
85539  */
85540 #define RDC_SEMAPHORE_GATE9_GTFSM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK)
85541 
85542 #define RDC_SEMAPHORE_GATE9_LDOM_MASK            (0x30U)
85543 #define RDC_SEMAPHORE_GATE9_LDOM_SHIFT           (4U)
85544 /*! LDOM
85545  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85546  *  0b01..The gate has been locked by domain 1.
85547  *  0b10..The gate has been locked by domain 2.
85548  *  0b11..The gate has been locked by domain 3.
85549  */
85550 #define RDC_SEMAPHORE_GATE9_LDOM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK)
85551 /*! @} */
85552 
85553 /*! @name GATE10 - Gate Register */
85554 /*! @{ */
85555 
85556 #define RDC_SEMAPHORE_GATE10_GTFSM_MASK          (0xFU)
85557 #define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT         (0U)
85558 /*! GTFSM - Gate Finite State Machine.
85559  *  0b0000..The gate is unlocked (free).
85560  *  0b0001..The gate has been locked by processor with master_index = 0.
85561  *  0b0010..The gate has been locked by processor with master_index = 1.
85562  *  0b0011..The gate has been locked by processor with master_index = 2.
85563  *  0b0100..The gate has been locked by processor with master_index = 3.
85564  *  0b0101..The gate has been locked by processor with master_index = 4.
85565  *  0b0110..The gate has been locked by processor with master_index = 5.
85566  *  0b0111..The gate has been locked by processor with master_index = 6.
85567  *  0b1000..The gate has been locked by processor with master_index = 7.
85568  *  0b1001..The gate has been locked by processor with master_index = 8.
85569  *  0b1010..The gate has been locked by processor with master_index = 9.
85570  *  0b1011..The gate has been locked by processor with master_index = 10.
85571  *  0b1100..The gate has been locked by processor with master_index = 11.
85572  *  0b1101..The gate has been locked by processor with master_index = 12.
85573  *  0b1110..The gate has been locked by processor with master_index = 13.
85574  *  0b1111..The gate has been locked by processor with master_index = 14.
85575  */
85576 #define RDC_SEMAPHORE_GATE10_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK)
85577 
85578 #define RDC_SEMAPHORE_GATE10_LDOM_MASK           (0x30U)
85579 #define RDC_SEMAPHORE_GATE10_LDOM_SHIFT          (4U)
85580 /*! LDOM
85581  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85582  *  0b01..The gate has been locked by domain 1.
85583  *  0b10..The gate has been locked by domain 2.
85584  *  0b11..The gate has been locked by domain 3.
85585  */
85586 #define RDC_SEMAPHORE_GATE10_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK)
85587 /*! @} */
85588 
85589 /*! @name GATE11 - Gate Register */
85590 /*! @{ */
85591 
85592 #define RDC_SEMAPHORE_GATE11_GTFSM_MASK          (0xFU)
85593 #define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT         (0U)
85594 /*! GTFSM - Gate Finite State Machine.
85595  *  0b0000..The gate is unlocked (free).
85596  *  0b0001..The gate has been locked by processor with master_index = 0.
85597  *  0b0010..The gate has been locked by processor with master_index = 1.
85598  *  0b0011..The gate has been locked by processor with master_index = 2.
85599  *  0b0100..The gate has been locked by processor with master_index = 3.
85600  *  0b0101..The gate has been locked by processor with master_index = 4.
85601  *  0b0110..The gate has been locked by processor with master_index = 5.
85602  *  0b0111..The gate has been locked by processor with master_index = 6.
85603  *  0b1000..The gate has been locked by processor with master_index = 7.
85604  *  0b1001..The gate has been locked by processor with master_index = 8.
85605  *  0b1010..The gate has been locked by processor with master_index = 9.
85606  *  0b1011..The gate has been locked by processor with master_index = 10.
85607  *  0b1100..The gate has been locked by processor with master_index = 11.
85608  *  0b1101..The gate has been locked by processor with master_index = 12.
85609  *  0b1110..The gate has been locked by processor with master_index = 13.
85610  *  0b1111..The gate has been locked by processor with master_index = 14.
85611  */
85612 #define RDC_SEMAPHORE_GATE11_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK)
85613 
85614 #define RDC_SEMAPHORE_GATE11_LDOM_MASK           (0x30U)
85615 #define RDC_SEMAPHORE_GATE11_LDOM_SHIFT          (4U)
85616 /*! LDOM
85617  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85618  *  0b01..The gate has been locked by domain 1.
85619  *  0b10..The gate has been locked by domain 2.
85620  *  0b11..The gate has been locked by domain 3.
85621  */
85622 #define RDC_SEMAPHORE_GATE11_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK)
85623 /*! @} */
85624 
85625 /*! @name GATE12 - Gate Register */
85626 /*! @{ */
85627 
85628 #define RDC_SEMAPHORE_GATE12_GTFSM_MASK          (0xFU)
85629 #define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT         (0U)
85630 /*! GTFSM - Gate Finite State Machine.
85631  *  0b0000..The gate is unlocked (free).
85632  *  0b0001..The gate has been locked by processor with master_index = 0.
85633  *  0b0010..The gate has been locked by processor with master_index = 1.
85634  *  0b0011..The gate has been locked by processor with master_index = 2.
85635  *  0b0100..The gate has been locked by processor with master_index = 3.
85636  *  0b0101..The gate has been locked by processor with master_index = 4.
85637  *  0b0110..The gate has been locked by processor with master_index = 5.
85638  *  0b0111..The gate has been locked by processor with master_index = 6.
85639  *  0b1000..The gate has been locked by processor with master_index = 7.
85640  *  0b1001..The gate has been locked by processor with master_index = 8.
85641  *  0b1010..The gate has been locked by processor with master_index = 9.
85642  *  0b1011..The gate has been locked by processor with master_index = 10.
85643  *  0b1100..The gate has been locked by processor with master_index = 11.
85644  *  0b1101..The gate has been locked by processor with master_index = 12.
85645  *  0b1110..The gate has been locked by processor with master_index = 13.
85646  *  0b1111..The gate has been locked by processor with master_index = 14.
85647  */
85648 #define RDC_SEMAPHORE_GATE12_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK)
85649 
85650 #define RDC_SEMAPHORE_GATE12_LDOM_MASK           (0x30U)
85651 #define RDC_SEMAPHORE_GATE12_LDOM_SHIFT          (4U)
85652 /*! LDOM
85653  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85654  *  0b01..The gate has been locked by domain 1.
85655  *  0b10..The gate has been locked by domain 2.
85656  *  0b11..The gate has been locked by domain 3.
85657  */
85658 #define RDC_SEMAPHORE_GATE12_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK)
85659 /*! @} */
85660 
85661 /*! @name GATE13 - Gate Register */
85662 /*! @{ */
85663 
85664 #define RDC_SEMAPHORE_GATE13_GTFSM_MASK          (0xFU)
85665 #define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT         (0U)
85666 /*! GTFSM - Gate Finite State Machine.
85667  *  0b0000..The gate is unlocked (free).
85668  *  0b0001..The gate has been locked by processor with master_index = 0.
85669  *  0b0010..The gate has been locked by processor with master_index = 1.
85670  *  0b0011..The gate has been locked by processor with master_index = 2.
85671  *  0b0100..The gate has been locked by processor with master_index = 3.
85672  *  0b0101..The gate has been locked by processor with master_index = 4.
85673  *  0b0110..The gate has been locked by processor with master_index = 5.
85674  *  0b0111..The gate has been locked by processor with master_index = 6.
85675  *  0b1000..The gate has been locked by processor with master_index = 7.
85676  *  0b1001..The gate has been locked by processor with master_index = 8.
85677  *  0b1010..The gate has been locked by processor with master_index = 9.
85678  *  0b1011..The gate has been locked by processor with master_index = 10.
85679  *  0b1100..The gate has been locked by processor with master_index = 11.
85680  *  0b1101..The gate has been locked by processor with master_index = 12.
85681  *  0b1110..The gate has been locked by processor with master_index = 13.
85682  *  0b1111..The gate has been locked by processor with master_index = 14.
85683  */
85684 #define RDC_SEMAPHORE_GATE13_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK)
85685 
85686 #define RDC_SEMAPHORE_GATE13_LDOM_MASK           (0x30U)
85687 #define RDC_SEMAPHORE_GATE13_LDOM_SHIFT          (4U)
85688 /*! LDOM
85689  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85690  *  0b01..The gate has been locked by domain 1.
85691  *  0b10..The gate has been locked by domain 2.
85692  *  0b11..The gate has been locked by domain 3.
85693  */
85694 #define RDC_SEMAPHORE_GATE13_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK)
85695 /*! @} */
85696 
85697 /*! @name GATE14 - Gate Register */
85698 /*! @{ */
85699 
85700 #define RDC_SEMAPHORE_GATE14_GTFSM_MASK          (0xFU)
85701 #define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT         (0U)
85702 /*! GTFSM - Gate Finite State Machine.
85703  *  0b0000..The gate is unlocked (free).
85704  *  0b0001..The gate has been locked by processor with master_index = 0.
85705  *  0b0010..The gate has been locked by processor with master_index = 1.
85706  *  0b0011..The gate has been locked by processor with master_index = 2.
85707  *  0b0100..The gate has been locked by processor with master_index = 3.
85708  *  0b0101..The gate has been locked by processor with master_index = 4.
85709  *  0b0110..The gate has been locked by processor with master_index = 5.
85710  *  0b0111..The gate has been locked by processor with master_index = 6.
85711  *  0b1000..The gate has been locked by processor with master_index = 7.
85712  *  0b1001..The gate has been locked by processor with master_index = 8.
85713  *  0b1010..The gate has been locked by processor with master_index = 9.
85714  *  0b1011..The gate has been locked by processor with master_index = 10.
85715  *  0b1100..The gate has been locked by processor with master_index = 11.
85716  *  0b1101..The gate has been locked by processor with master_index = 12.
85717  *  0b1110..The gate has been locked by processor with master_index = 13.
85718  *  0b1111..The gate has been locked by processor with master_index = 14.
85719  */
85720 #define RDC_SEMAPHORE_GATE14_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK)
85721 
85722 #define RDC_SEMAPHORE_GATE14_LDOM_MASK           (0x30U)
85723 #define RDC_SEMAPHORE_GATE14_LDOM_SHIFT          (4U)
85724 /*! LDOM
85725  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85726  *  0b01..The gate has been locked by domain 1.
85727  *  0b10..The gate has been locked by domain 2.
85728  *  0b11..The gate has been locked by domain 3.
85729  */
85730 #define RDC_SEMAPHORE_GATE14_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK)
85731 /*! @} */
85732 
85733 /*! @name GATE15 - Gate Register */
85734 /*! @{ */
85735 
85736 #define RDC_SEMAPHORE_GATE15_GTFSM_MASK          (0xFU)
85737 #define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT         (0U)
85738 /*! GTFSM - Gate Finite State Machine.
85739  *  0b0000..The gate is unlocked (free).
85740  *  0b0001..The gate has been locked by processor with master_index = 0.
85741  *  0b0010..The gate has been locked by processor with master_index = 1.
85742  *  0b0011..The gate has been locked by processor with master_index = 2.
85743  *  0b0100..The gate has been locked by processor with master_index = 3.
85744  *  0b0101..The gate has been locked by processor with master_index = 4.
85745  *  0b0110..The gate has been locked by processor with master_index = 5.
85746  *  0b0111..The gate has been locked by processor with master_index = 6.
85747  *  0b1000..The gate has been locked by processor with master_index = 7.
85748  *  0b1001..The gate has been locked by processor with master_index = 8.
85749  *  0b1010..The gate has been locked by processor with master_index = 9.
85750  *  0b1011..The gate has been locked by processor with master_index = 10.
85751  *  0b1100..The gate has been locked by processor with master_index = 11.
85752  *  0b1101..The gate has been locked by processor with master_index = 12.
85753  *  0b1110..The gate has been locked by processor with master_index = 13.
85754  *  0b1111..The gate has been locked by processor with master_index = 14.
85755  */
85756 #define RDC_SEMAPHORE_GATE15_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK)
85757 
85758 #define RDC_SEMAPHORE_GATE15_LDOM_MASK           (0x30U)
85759 #define RDC_SEMAPHORE_GATE15_LDOM_SHIFT          (4U)
85760 /*! LDOM
85761  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85762  *  0b01..The gate has been locked by domain 1.
85763  *  0b10..The gate has been locked by domain 2.
85764  *  0b11..The gate has been locked by domain 3.
85765  */
85766 #define RDC_SEMAPHORE_GATE15_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK)
85767 /*! @} */
85768 
85769 /*! @name GATE16 - Gate Register */
85770 /*! @{ */
85771 
85772 #define RDC_SEMAPHORE_GATE16_GTFSM_MASK          (0xFU)
85773 #define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT         (0U)
85774 /*! GTFSM - Gate Finite State Machine.
85775  *  0b0000..The gate is unlocked (free).
85776  *  0b0001..The gate has been locked by processor with master_index = 0.
85777  *  0b0010..The gate has been locked by processor with master_index = 1.
85778  *  0b0011..The gate has been locked by processor with master_index = 2.
85779  *  0b0100..The gate has been locked by processor with master_index = 3.
85780  *  0b0101..The gate has been locked by processor with master_index = 4.
85781  *  0b0110..The gate has been locked by processor with master_index = 5.
85782  *  0b0111..The gate has been locked by processor with master_index = 6.
85783  *  0b1000..The gate has been locked by processor with master_index = 7.
85784  *  0b1001..The gate has been locked by processor with master_index = 8.
85785  *  0b1010..The gate has been locked by processor with master_index = 9.
85786  *  0b1011..The gate has been locked by processor with master_index = 10.
85787  *  0b1100..The gate has been locked by processor with master_index = 11.
85788  *  0b1101..The gate has been locked by processor with master_index = 12.
85789  *  0b1110..The gate has been locked by processor with master_index = 13.
85790  *  0b1111..The gate has been locked by processor with master_index = 14.
85791  */
85792 #define RDC_SEMAPHORE_GATE16_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK)
85793 
85794 #define RDC_SEMAPHORE_GATE16_LDOM_MASK           (0x30U)
85795 #define RDC_SEMAPHORE_GATE16_LDOM_SHIFT          (4U)
85796 /*! LDOM
85797  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85798  *  0b01..The gate has been locked by domain 1.
85799  *  0b10..The gate has been locked by domain 2.
85800  *  0b11..The gate has been locked by domain 3.
85801  */
85802 #define RDC_SEMAPHORE_GATE16_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK)
85803 /*! @} */
85804 
85805 /*! @name GATE17 - Gate Register */
85806 /*! @{ */
85807 
85808 #define RDC_SEMAPHORE_GATE17_GTFSM_MASK          (0xFU)
85809 #define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT         (0U)
85810 /*! GTFSM - Gate Finite State Machine.
85811  *  0b0000..The gate is unlocked (free).
85812  *  0b0001..The gate has been locked by processor with master_index = 0.
85813  *  0b0010..The gate has been locked by processor with master_index = 1.
85814  *  0b0011..The gate has been locked by processor with master_index = 2.
85815  *  0b0100..The gate has been locked by processor with master_index = 3.
85816  *  0b0101..The gate has been locked by processor with master_index = 4.
85817  *  0b0110..The gate has been locked by processor with master_index = 5.
85818  *  0b0111..The gate has been locked by processor with master_index = 6.
85819  *  0b1000..The gate has been locked by processor with master_index = 7.
85820  *  0b1001..The gate has been locked by processor with master_index = 8.
85821  *  0b1010..The gate has been locked by processor with master_index = 9.
85822  *  0b1011..The gate has been locked by processor with master_index = 10.
85823  *  0b1100..The gate has been locked by processor with master_index = 11.
85824  *  0b1101..The gate has been locked by processor with master_index = 12.
85825  *  0b1110..The gate has been locked by processor with master_index = 13.
85826  *  0b1111..The gate has been locked by processor with master_index = 14.
85827  */
85828 #define RDC_SEMAPHORE_GATE17_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK)
85829 
85830 #define RDC_SEMAPHORE_GATE17_LDOM_MASK           (0x30U)
85831 #define RDC_SEMAPHORE_GATE17_LDOM_SHIFT          (4U)
85832 /*! LDOM
85833  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85834  *  0b01..The gate has been locked by domain 1.
85835  *  0b10..The gate has been locked by domain 2.
85836  *  0b11..The gate has been locked by domain 3.
85837  */
85838 #define RDC_SEMAPHORE_GATE17_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK)
85839 /*! @} */
85840 
85841 /*! @name GATE18 - Gate Register */
85842 /*! @{ */
85843 
85844 #define RDC_SEMAPHORE_GATE18_GTFSM_MASK          (0xFU)
85845 #define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT         (0U)
85846 /*! GTFSM - Gate Finite State Machine.
85847  *  0b0000..The gate is unlocked (free).
85848  *  0b0001..The gate has been locked by processor with master_index = 0.
85849  *  0b0010..The gate has been locked by processor with master_index = 1.
85850  *  0b0011..The gate has been locked by processor with master_index = 2.
85851  *  0b0100..The gate has been locked by processor with master_index = 3.
85852  *  0b0101..The gate has been locked by processor with master_index = 4.
85853  *  0b0110..The gate has been locked by processor with master_index = 5.
85854  *  0b0111..The gate has been locked by processor with master_index = 6.
85855  *  0b1000..The gate has been locked by processor with master_index = 7.
85856  *  0b1001..The gate has been locked by processor with master_index = 8.
85857  *  0b1010..The gate has been locked by processor with master_index = 9.
85858  *  0b1011..The gate has been locked by processor with master_index = 10.
85859  *  0b1100..The gate has been locked by processor with master_index = 11.
85860  *  0b1101..The gate has been locked by processor with master_index = 12.
85861  *  0b1110..The gate has been locked by processor with master_index = 13.
85862  *  0b1111..The gate has been locked by processor with master_index = 14.
85863  */
85864 #define RDC_SEMAPHORE_GATE18_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK)
85865 
85866 #define RDC_SEMAPHORE_GATE18_LDOM_MASK           (0x30U)
85867 #define RDC_SEMAPHORE_GATE18_LDOM_SHIFT          (4U)
85868 /*! LDOM
85869  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85870  *  0b01..The gate has been locked by domain 1.
85871  *  0b10..The gate has been locked by domain 2.
85872  *  0b11..The gate has been locked by domain 3.
85873  */
85874 #define RDC_SEMAPHORE_GATE18_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK)
85875 /*! @} */
85876 
85877 /*! @name GATE19 - Gate Register */
85878 /*! @{ */
85879 
85880 #define RDC_SEMAPHORE_GATE19_GTFSM_MASK          (0xFU)
85881 #define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT         (0U)
85882 /*! GTFSM - Gate Finite State Machine.
85883  *  0b0000..The gate is unlocked (free).
85884  *  0b0001..The gate has been locked by processor with master_index = 0.
85885  *  0b0010..The gate has been locked by processor with master_index = 1.
85886  *  0b0011..The gate has been locked by processor with master_index = 2.
85887  *  0b0100..The gate has been locked by processor with master_index = 3.
85888  *  0b0101..The gate has been locked by processor with master_index = 4.
85889  *  0b0110..The gate has been locked by processor with master_index = 5.
85890  *  0b0111..The gate has been locked by processor with master_index = 6.
85891  *  0b1000..The gate has been locked by processor with master_index = 7.
85892  *  0b1001..The gate has been locked by processor with master_index = 8.
85893  *  0b1010..The gate has been locked by processor with master_index = 9.
85894  *  0b1011..The gate has been locked by processor with master_index = 10.
85895  *  0b1100..The gate has been locked by processor with master_index = 11.
85896  *  0b1101..The gate has been locked by processor with master_index = 12.
85897  *  0b1110..The gate has been locked by processor with master_index = 13.
85898  *  0b1111..The gate has been locked by processor with master_index = 14.
85899  */
85900 #define RDC_SEMAPHORE_GATE19_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK)
85901 
85902 #define RDC_SEMAPHORE_GATE19_LDOM_MASK           (0x30U)
85903 #define RDC_SEMAPHORE_GATE19_LDOM_SHIFT          (4U)
85904 /*! LDOM
85905  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85906  *  0b01..The gate has been locked by domain 1.
85907  *  0b10..The gate has been locked by domain 2.
85908  *  0b11..The gate has been locked by domain 3.
85909  */
85910 #define RDC_SEMAPHORE_GATE19_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK)
85911 /*! @} */
85912 
85913 /*! @name GATE20 - Gate Register */
85914 /*! @{ */
85915 
85916 #define RDC_SEMAPHORE_GATE20_GTFSM_MASK          (0xFU)
85917 #define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT         (0U)
85918 /*! GTFSM - Gate Finite State Machine.
85919  *  0b0000..The gate is unlocked (free).
85920  *  0b0001..The gate has been locked by processor with master_index = 0.
85921  *  0b0010..The gate has been locked by processor with master_index = 1.
85922  *  0b0011..The gate has been locked by processor with master_index = 2.
85923  *  0b0100..The gate has been locked by processor with master_index = 3.
85924  *  0b0101..The gate has been locked by processor with master_index = 4.
85925  *  0b0110..The gate has been locked by processor with master_index = 5.
85926  *  0b0111..The gate has been locked by processor with master_index = 6.
85927  *  0b1000..The gate has been locked by processor with master_index = 7.
85928  *  0b1001..The gate has been locked by processor with master_index = 8.
85929  *  0b1010..The gate has been locked by processor with master_index = 9.
85930  *  0b1011..The gate has been locked by processor with master_index = 10.
85931  *  0b1100..The gate has been locked by processor with master_index = 11.
85932  *  0b1101..The gate has been locked by processor with master_index = 12.
85933  *  0b1110..The gate has been locked by processor with master_index = 13.
85934  *  0b1111..The gate has been locked by processor with master_index = 14.
85935  */
85936 #define RDC_SEMAPHORE_GATE20_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK)
85937 
85938 #define RDC_SEMAPHORE_GATE20_LDOM_MASK           (0x30U)
85939 #define RDC_SEMAPHORE_GATE20_LDOM_SHIFT          (4U)
85940 /*! LDOM
85941  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85942  *  0b01..The gate has been locked by domain 1.
85943  *  0b10..The gate has been locked by domain 2.
85944  *  0b11..The gate has been locked by domain 3.
85945  */
85946 #define RDC_SEMAPHORE_GATE20_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK)
85947 /*! @} */
85948 
85949 /*! @name GATE21 - Gate Register */
85950 /*! @{ */
85951 
85952 #define RDC_SEMAPHORE_GATE21_GTFSM_MASK          (0xFU)
85953 #define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT         (0U)
85954 /*! GTFSM - Gate Finite State Machine.
85955  *  0b0000..The gate is unlocked (free).
85956  *  0b0001..The gate has been locked by processor with master_index = 0.
85957  *  0b0010..The gate has been locked by processor with master_index = 1.
85958  *  0b0011..The gate has been locked by processor with master_index = 2.
85959  *  0b0100..The gate has been locked by processor with master_index = 3.
85960  *  0b0101..The gate has been locked by processor with master_index = 4.
85961  *  0b0110..The gate has been locked by processor with master_index = 5.
85962  *  0b0111..The gate has been locked by processor with master_index = 6.
85963  *  0b1000..The gate has been locked by processor with master_index = 7.
85964  *  0b1001..The gate has been locked by processor with master_index = 8.
85965  *  0b1010..The gate has been locked by processor with master_index = 9.
85966  *  0b1011..The gate has been locked by processor with master_index = 10.
85967  *  0b1100..The gate has been locked by processor with master_index = 11.
85968  *  0b1101..The gate has been locked by processor with master_index = 12.
85969  *  0b1110..The gate has been locked by processor with master_index = 13.
85970  *  0b1111..The gate has been locked by processor with master_index = 14.
85971  */
85972 #define RDC_SEMAPHORE_GATE21_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK)
85973 
85974 #define RDC_SEMAPHORE_GATE21_LDOM_MASK           (0x30U)
85975 #define RDC_SEMAPHORE_GATE21_LDOM_SHIFT          (4U)
85976 /*! LDOM
85977  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
85978  *  0b01..The gate has been locked by domain 1.
85979  *  0b10..The gate has been locked by domain 2.
85980  *  0b11..The gate has been locked by domain 3.
85981  */
85982 #define RDC_SEMAPHORE_GATE21_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK)
85983 /*! @} */
85984 
85985 /*! @name GATE22 - Gate Register */
85986 /*! @{ */
85987 
85988 #define RDC_SEMAPHORE_GATE22_GTFSM_MASK          (0xFU)
85989 #define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT         (0U)
85990 /*! GTFSM - Gate Finite State Machine.
85991  *  0b0000..The gate is unlocked (free).
85992  *  0b0001..The gate has been locked by processor with master_index = 0.
85993  *  0b0010..The gate has been locked by processor with master_index = 1.
85994  *  0b0011..The gate has been locked by processor with master_index = 2.
85995  *  0b0100..The gate has been locked by processor with master_index = 3.
85996  *  0b0101..The gate has been locked by processor with master_index = 4.
85997  *  0b0110..The gate has been locked by processor with master_index = 5.
85998  *  0b0111..The gate has been locked by processor with master_index = 6.
85999  *  0b1000..The gate has been locked by processor with master_index = 7.
86000  *  0b1001..The gate has been locked by processor with master_index = 8.
86001  *  0b1010..The gate has been locked by processor with master_index = 9.
86002  *  0b1011..The gate has been locked by processor with master_index = 10.
86003  *  0b1100..The gate has been locked by processor with master_index = 11.
86004  *  0b1101..The gate has been locked by processor with master_index = 12.
86005  *  0b1110..The gate has been locked by processor with master_index = 13.
86006  *  0b1111..The gate has been locked by processor with master_index = 14.
86007  */
86008 #define RDC_SEMAPHORE_GATE22_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK)
86009 
86010 #define RDC_SEMAPHORE_GATE22_LDOM_MASK           (0x30U)
86011 #define RDC_SEMAPHORE_GATE22_LDOM_SHIFT          (4U)
86012 /*! LDOM
86013  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86014  *  0b01..The gate has been locked by domain 1.
86015  *  0b10..The gate has been locked by domain 2.
86016  *  0b11..The gate has been locked by domain 3.
86017  */
86018 #define RDC_SEMAPHORE_GATE22_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK)
86019 /*! @} */
86020 
86021 /*! @name GATE23 - Gate Register */
86022 /*! @{ */
86023 
86024 #define RDC_SEMAPHORE_GATE23_GTFSM_MASK          (0xFU)
86025 #define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT         (0U)
86026 /*! GTFSM - Gate Finite State Machine.
86027  *  0b0000..The gate is unlocked (free).
86028  *  0b0001..The gate has been locked by processor with master_index = 0.
86029  *  0b0010..The gate has been locked by processor with master_index = 1.
86030  *  0b0011..The gate has been locked by processor with master_index = 2.
86031  *  0b0100..The gate has been locked by processor with master_index = 3.
86032  *  0b0101..The gate has been locked by processor with master_index = 4.
86033  *  0b0110..The gate has been locked by processor with master_index = 5.
86034  *  0b0111..The gate has been locked by processor with master_index = 6.
86035  *  0b1000..The gate has been locked by processor with master_index = 7.
86036  *  0b1001..The gate has been locked by processor with master_index = 8.
86037  *  0b1010..The gate has been locked by processor with master_index = 9.
86038  *  0b1011..The gate has been locked by processor with master_index = 10.
86039  *  0b1100..The gate has been locked by processor with master_index = 11.
86040  *  0b1101..The gate has been locked by processor with master_index = 12.
86041  *  0b1110..The gate has been locked by processor with master_index = 13.
86042  *  0b1111..The gate has been locked by processor with master_index = 14.
86043  */
86044 #define RDC_SEMAPHORE_GATE23_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK)
86045 
86046 #define RDC_SEMAPHORE_GATE23_LDOM_MASK           (0x30U)
86047 #define RDC_SEMAPHORE_GATE23_LDOM_SHIFT          (4U)
86048 /*! LDOM
86049  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86050  *  0b01..The gate has been locked by domain 1.
86051  *  0b10..The gate has been locked by domain 2.
86052  *  0b11..The gate has been locked by domain 3.
86053  */
86054 #define RDC_SEMAPHORE_GATE23_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK)
86055 /*! @} */
86056 
86057 /*! @name GATE24 - Gate Register */
86058 /*! @{ */
86059 
86060 #define RDC_SEMAPHORE_GATE24_GTFSM_MASK          (0xFU)
86061 #define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT         (0U)
86062 /*! GTFSM - Gate Finite State Machine.
86063  *  0b0000..The gate is unlocked (free).
86064  *  0b0001..The gate has been locked by processor with master_index = 0.
86065  *  0b0010..The gate has been locked by processor with master_index = 1.
86066  *  0b0011..The gate has been locked by processor with master_index = 2.
86067  *  0b0100..The gate has been locked by processor with master_index = 3.
86068  *  0b0101..The gate has been locked by processor with master_index = 4.
86069  *  0b0110..The gate has been locked by processor with master_index = 5.
86070  *  0b0111..The gate has been locked by processor with master_index = 6.
86071  *  0b1000..The gate has been locked by processor with master_index = 7.
86072  *  0b1001..The gate has been locked by processor with master_index = 8.
86073  *  0b1010..The gate has been locked by processor with master_index = 9.
86074  *  0b1011..The gate has been locked by processor with master_index = 10.
86075  *  0b1100..The gate has been locked by processor with master_index = 11.
86076  *  0b1101..The gate has been locked by processor with master_index = 12.
86077  *  0b1110..The gate has been locked by processor with master_index = 13.
86078  *  0b1111..The gate has been locked by processor with master_index = 14.
86079  */
86080 #define RDC_SEMAPHORE_GATE24_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK)
86081 
86082 #define RDC_SEMAPHORE_GATE24_LDOM_MASK           (0x30U)
86083 #define RDC_SEMAPHORE_GATE24_LDOM_SHIFT          (4U)
86084 /*! LDOM
86085  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86086  *  0b01..The gate has been locked by domain 1.
86087  *  0b10..The gate has been locked by domain 2.
86088  *  0b11..The gate has been locked by domain 3.
86089  */
86090 #define RDC_SEMAPHORE_GATE24_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK)
86091 /*! @} */
86092 
86093 /*! @name GATE25 - Gate Register */
86094 /*! @{ */
86095 
86096 #define RDC_SEMAPHORE_GATE25_GTFSM_MASK          (0xFU)
86097 #define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT         (0U)
86098 /*! GTFSM - Gate Finite State Machine.
86099  *  0b0000..The gate is unlocked (free).
86100  *  0b0001..The gate has been locked by processor with master_index = 0.
86101  *  0b0010..The gate has been locked by processor with master_index = 1.
86102  *  0b0011..The gate has been locked by processor with master_index = 2.
86103  *  0b0100..The gate has been locked by processor with master_index = 3.
86104  *  0b0101..The gate has been locked by processor with master_index = 4.
86105  *  0b0110..The gate has been locked by processor with master_index = 5.
86106  *  0b0111..The gate has been locked by processor with master_index = 6.
86107  *  0b1000..The gate has been locked by processor with master_index = 7.
86108  *  0b1001..The gate has been locked by processor with master_index = 8.
86109  *  0b1010..The gate has been locked by processor with master_index = 9.
86110  *  0b1011..The gate has been locked by processor with master_index = 10.
86111  *  0b1100..The gate has been locked by processor with master_index = 11.
86112  *  0b1101..The gate has been locked by processor with master_index = 12.
86113  *  0b1110..The gate has been locked by processor with master_index = 13.
86114  *  0b1111..The gate has been locked by processor with master_index = 14.
86115  */
86116 #define RDC_SEMAPHORE_GATE25_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK)
86117 
86118 #define RDC_SEMAPHORE_GATE25_LDOM_MASK           (0x30U)
86119 #define RDC_SEMAPHORE_GATE25_LDOM_SHIFT          (4U)
86120 /*! LDOM
86121  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86122  *  0b01..The gate has been locked by domain 1.
86123  *  0b10..The gate has been locked by domain 2.
86124  *  0b11..The gate has been locked by domain 3.
86125  */
86126 #define RDC_SEMAPHORE_GATE25_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK)
86127 /*! @} */
86128 
86129 /*! @name GATE26 - Gate Register */
86130 /*! @{ */
86131 
86132 #define RDC_SEMAPHORE_GATE26_GTFSM_MASK          (0xFU)
86133 #define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT         (0U)
86134 /*! GTFSM - Gate Finite State Machine.
86135  *  0b0000..The gate is unlocked (free).
86136  *  0b0001..The gate has been locked by processor with master_index = 0.
86137  *  0b0010..The gate has been locked by processor with master_index = 1.
86138  *  0b0011..The gate has been locked by processor with master_index = 2.
86139  *  0b0100..The gate has been locked by processor with master_index = 3.
86140  *  0b0101..The gate has been locked by processor with master_index = 4.
86141  *  0b0110..The gate has been locked by processor with master_index = 5.
86142  *  0b0111..The gate has been locked by processor with master_index = 6.
86143  *  0b1000..The gate has been locked by processor with master_index = 7.
86144  *  0b1001..The gate has been locked by processor with master_index = 8.
86145  *  0b1010..The gate has been locked by processor with master_index = 9.
86146  *  0b1011..The gate has been locked by processor with master_index = 10.
86147  *  0b1100..The gate has been locked by processor with master_index = 11.
86148  *  0b1101..The gate has been locked by processor with master_index = 12.
86149  *  0b1110..The gate has been locked by processor with master_index = 13.
86150  *  0b1111..The gate has been locked by processor with master_index = 14.
86151  */
86152 #define RDC_SEMAPHORE_GATE26_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK)
86153 
86154 #define RDC_SEMAPHORE_GATE26_LDOM_MASK           (0x30U)
86155 #define RDC_SEMAPHORE_GATE26_LDOM_SHIFT          (4U)
86156 /*! LDOM
86157  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86158  *  0b01..The gate has been locked by domain 1.
86159  *  0b10..The gate has been locked by domain 2.
86160  *  0b11..The gate has been locked by domain 3.
86161  */
86162 #define RDC_SEMAPHORE_GATE26_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK)
86163 /*! @} */
86164 
86165 /*! @name GATE27 - Gate Register */
86166 /*! @{ */
86167 
86168 #define RDC_SEMAPHORE_GATE27_GTFSM_MASK          (0xFU)
86169 #define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT         (0U)
86170 /*! GTFSM - Gate Finite State Machine.
86171  *  0b0000..The gate is unlocked (free).
86172  *  0b0001..The gate has been locked by processor with master_index = 0.
86173  *  0b0010..The gate has been locked by processor with master_index = 1.
86174  *  0b0011..The gate has been locked by processor with master_index = 2.
86175  *  0b0100..The gate has been locked by processor with master_index = 3.
86176  *  0b0101..The gate has been locked by processor with master_index = 4.
86177  *  0b0110..The gate has been locked by processor with master_index = 5.
86178  *  0b0111..The gate has been locked by processor with master_index = 6.
86179  *  0b1000..The gate has been locked by processor with master_index = 7.
86180  *  0b1001..The gate has been locked by processor with master_index = 8.
86181  *  0b1010..The gate has been locked by processor with master_index = 9.
86182  *  0b1011..The gate has been locked by processor with master_index = 10.
86183  *  0b1100..The gate has been locked by processor with master_index = 11.
86184  *  0b1101..The gate has been locked by processor with master_index = 12.
86185  *  0b1110..The gate has been locked by processor with master_index = 13.
86186  *  0b1111..The gate has been locked by processor with master_index = 14.
86187  */
86188 #define RDC_SEMAPHORE_GATE27_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK)
86189 
86190 #define RDC_SEMAPHORE_GATE27_LDOM_MASK           (0x30U)
86191 #define RDC_SEMAPHORE_GATE27_LDOM_SHIFT          (4U)
86192 /*! LDOM
86193  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86194  *  0b01..The gate has been locked by domain 1.
86195  *  0b10..The gate has been locked by domain 2.
86196  *  0b11..The gate has been locked by domain 3.
86197  */
86198 #define RDC_SEMAPHORE_GATE27_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK)
86199 /*! @} */
86200 
86201 /*! @name GATE28 - Gate Register */
86202 /*! @{ */
86203 
86204 #define RDC_SEMAPHORE_GATE28_GTFSM_MASK          (0xFU)
86205 #define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT         (0U)
86206 /*! GTFSM - Gate Finite State Machine.
86207  *  0b0000..The gate is unlocked (free).
86208  *  0b0001..The gate has been locked by processor with master_index = 0.
86209  *  0b0010..The gate has been locked by processor with master_index = 1.
86210  *  0b0011..The gate has been locked by processor with master_index = 2.
86211  *  0b0100..The gate has been locked by processor with master_index = 3.
86212  *  0b0101..The gate has been locked by processor with master_index = 4.
86213  *  0b0110..The gate has been locked by processor with master_index = 5.
86214  *  0b0111..The gate has been locked by processor with master_index = 6.
86215  *  0b1000..The gate has been locked by processor with master_index = 7.
86216  *  0b1001..The gate has been locked by processor with master_index = 8.
86217  *  0b1010..The gate has been locked by processor with master_index = 9.
86218  *  0b1011..The gate has been locked by processor with master_index = 10.
86219  *  0b1100..The gate has been locked by processor with master_index = 11.
86220  *  0b1101..The gate has been locked by processor with master_index = 12.
86221  *  0b1110..The gate has been locked by processor with master_index = 13.
86222  *  0b1111..The gate has been locked by processor with master_index = 14.
86223  */
86224 #define RDC_SEMAPHORE_GATE28_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK)
86225 
86226 #define RDC_SEMAPHORE_GATE28_LDOM_MASK           (0x30U)
86227 #define RDC_SEMAPHORE_GATE28_LDOM_SHIFT          (4U)
86228 /*! LDOM
86229  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86230  *  0b01..The gate has been locked by domain 1.
86231  *  0b10..The gate has been locked by domain 2.
86232  *  0b11..The gate has been locked by domain 3.
86233  */
86234 #define RDC_SEMAPHORE_GATE28_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK)
86235 /*! @} */
86236 
86237 /*! @name GATE29 - Gate Register */
86238 /*! @{ */
86239 
86240 #define RDC_SEMAPHORE_GATE29_GTFSM_MASK          (0xFU)
86241 #define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT         (0U)
86242 /*! GTFSM - Gate Finite State Machine.
86243  *  0b0000..The gate is unlocked (free).
86244  *  0b0001..The gate has been locked by processor with master_index = 0.
86245  *  0b0010..The gate has been locked by processor with master_index = 1.
86246  *  0b0011..The gate has been locked by processor with master_index = 2.
86247  *  0b0100..The gate has been locked by processor with master_index = 3.
86248  *  0b0101..The gate has been locked by processor with master_index = 4.
86249  *  0b0110..The gate has been locked by processor with master_index = 5.
86250  *  0b0111..The gate has been locked by processor with master_index = 6.
86251  *  0b1000..The gate has been locked by processor with master_index = 7.
86252  *  0b1001..The gate has been locked by processor with master_index = 8.
86253  *  0b1010..The gate has been locked by processor with master_index = 9.
86254  *  0b1011..The gate has been locked by processor with master_index = 10.
86255  *  0b1100..The gate has been locked by processor with master_index = 11.
86256  *  0b1101..The gate has been locked by processor with master_index = 12.
86257  *  0b1110..The gate has been locked by processor with master_index = 13.
86258  *  0b1111..The gate has been locked by processor with master_index = 14.
86259  */
86260 #define RDC_SEMAPHORE_GATE29_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK)
86261 
86262 #define RDC_SEMAPHORE_GATE29_LDOM_MASK           (0x30U)
86263 #define RDC_SEMAPHORE_GATE29_LDOM_SHIFT          (4U)
86264 /*! LDOM
86265  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86266  *  0b01..The gate has been locked by domain 1.
86267  *  0b10..The gate has been locked by domain 2.
86268  *  0b11..The gate has been locked by domain 3.
86269  */
86270 #define RDC_SEMAPHORE_GATE29_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK)
86271 /*! @} */
86272 
86273 /*! @name GATE30 - Gate Register */
86274 /*! @{ */
86275 
86276 #define RDC_SEMAPHORE_GATE30_GTFSM_MASK          (0xFU)
86277 #define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT         (0U)
86278 /*! GTFSM - Gate Finite State Machine.
86279  *  0b0000..The gate is unlocked (free).
86280  *  0b0001..The gate has been locked by processor with master_index = 0.
86281  *  0b0010..The gate has been locked by processor with master_index = 1.
86282  *  0b0011..The gate has been locked by processor with master_index = 2.
86283  *  0b0100..The gate has been locked by processor with master_index = 3.
86284  *  0b0101..The gate has been locked by processor with master_index = 4.
86285  *  0b0110..The gate has been locked by processor with master_index = 5.
86286  *  0b0111..The gate has been locked by processor with master_index = 6.
86287  *  0b1000..The gate has been locked by processor with master_index = 7.
86288  *  0b1001..The gate has been locked by processor with master_index = 8.
86289  *  0b1010..The gate has been locked by processor with master_index = 9.
86290  *  0b1011..The gate has been locked by processor with master_index = 10.
86291  *  0b1100..The gate has been locked by processor with master_index = 11.
86292  *  0b1101..The gate has been locked by processor with master_index = 12.
86293  *  0b1110..The gate has been locked by processor with master_index = 13.
86294  *  0b1111..The gate has been locked by processor with master_index = 14.
86295  */
86296 #define RDC_SEMAPHORE_GATE30_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK)
86297 
86298 #define RDC_SEMAPHORE_GATE30_LDOM_MASK           (0x30U)
86299 #define RDC_SEMAPHORE_GATE30_LDOM_SHIFT          (4U)
86300 /*! LDOM
86301  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86302  *  0b01..The gate has been locked by domain 1.
86303  *  0b10..The gate has been locked by domain 2.
86304  *  0b11..The gate has been locked by domain 3.
86305  */
86306 #define RDC_SEMAPHORE_GATE30_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK)
86307 /*! @} */
86308 
86309 /*! @name GATE31 - Gate Register */
86310 /*! @{ */
86311 
86312 #define RDC_SEMAPHORE_GATE31_GTFSM_MASK          (0xFU)
86313 #define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT         (0U)
86314 /*! GTFSM - Gate Finite State Machine.
86315  *  0b0000..The gate is unlocked (free).
86316  *  0b0001..The gate has been locked by processor with master_index = 0.
86317  *  0b0010..The gate has been locked by processor with master_index = 1.
86318  *  0b0011..The gate has been locked by processor with master_index = 2.
86319  *  0b0100..The gate has been locked by processor with master_index = 3.
86320  *  0b0101..The gate has been locked by processor with master_index = 4.
86321  *  0b0110..The gate has been locked by processor with master_index = 5.
86322  *  0b0111..The gate has been locked by processor with master_index = 6.
86323  *  0b1000..The gate has been locked by processor with master_index = 7.
86324  *  0b1001..The gate has been locked by processor with master_index = 8.
86325  *  0b1010..The gate has been locked by processor with master_index = 9.
86326  *  0b1011..The gate has been locked by processor with master_index = 10.
86327  *  0b1100..The gate has been locked by processor with master_index = 11.
86328  *  0b1101..The gate has been locked by processor with master_index = 12.
86329  *  0b1110..The gate has been locked by processor with master_index = 13.
86330  *  0b1111..The gate has been locked by processor with master_index = 14.
86331  */
86332 #define RDC_SEMAPHORE_GATE31_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK)
86333 
86334 #define RDC_SEMAPHORE_GATE31_LDOM_MASK           (0x30U)
86335 #define RDC_SEMAPHORE_GATE31_LDOM_SHIFT          (4U)
86336 /*! LDOM
86337  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86338  *  0b01..The gate has been locked by domain 1.
86339  *  0b10..The gate has been locked by domain 2.
86340  *  0b11..The gate has been locked by domain 3.
86341  */
86342 #define RDC_SEMAPHORE_GATE31_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK)
86343 /*! @} */
86344 
86345 /*! @name GATE32 - Gate Register */
86346 /*! @{ */
86347 
86348 #define RDC_SEMAPHORE_GATE32_GTFSM_MASK          (0xFU)
86349 #define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT         (0U)
86350 /*! GTFSM - Gate Finite State Machine.
86351  *  0b0000..The gate is unlocked (free).
86352  *  0b0001..The gate has been locked by processor with master_index = 0.
86353  *  0b0010..The gate has been locked by processor with master_index = 1.
86354  *  0b0011..The gate has been locked by processor with master_index = 2.
86355  *  0b0100..The gate has been locked by processor with master_index = 3.
86356  *  0b0101..The gate has been locked by processor with master_index = 4.
86357  *  0b0110..The gate has been locked by processor with master_index = 5.
86358  *  0b0111..The gate has been locked by processor with master_index = 6.
86359  *  0b1000..The gate has been locked by processor with master_index = 7.
86360  *  0b1001..The gate has been locked by processor with master_index = 8.
86361  *  0b1010..The gate has been locked by processor with master_index = 9.
86362  *  0b1011..The gate has been locked by processor with master_index = 10.
86363  *  0b1100..The gate has been locked by processor with master_index = 11.
86364  *  0b1101..The gate has been locked by processor with master_index = 12.
86365  *  0b1110..The gate has been locked by processor with master_index = 13.
86366  *  0b1111..The gate has been locked by processor with master_index = 14.
86367  */
86368 #define RDC_SEMAPHORE_GATE32_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK)
86369 
86370 #define RDC_SEMAPHORE_GATE32_LDOM_MASK           (0x30U)
86371 #define RDC_SEMAPHORE_GATE32_LDOM_SHIFT          (4U)
86372 /*! LDOM
86373  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86374  *  0b01..The gate has been locked by domain 1.
86375  *  0b10..The gate has been locked by domain 2.
86376  *  0b11..The gate has been locked by domain 3.
86377  */
86378 #define RDC_SEMAPHORE_GATE32_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK)
86379 /*! @} */
86380 
86381 /*! @name GATE33 - Gate Register */
86382 /*! @{ */
86383 
86384 #define RDC_SEMAPHORE_GATE33_GTFSM_MASK          (0xFU)
86385 #define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT         (0U)
86386 /*! GTFSM - Gate Finite State Machine.
86387  *  0b0000..The gate is unlocked (free).
86388  *  0b0001..The gate has been locked by processor with master_index = 0.
86389  *  0b0010..The gate has been locked by processor with master_index = 1.
86390  *  0b0011..The gate has been locked by processor with master_index = 2.
86391  *  0b0100..The gate has been locked by processor with master_index = 3.
86392  *  0b0101..The gate has been locked by processor with master_index = 4.
86393  *  0b0110..The gate has been locked by processor with master_index = 5.
86394  *  0b0111..The gate has been locked by processor with master_index = 6.
86395  *  0b1000..The gate has been locked by processor with master_index = 7.
86396  *  0b1001..The gate has been locked by processor with master_index = 8.
86397  *  0b1010..The gate has been locked by processor with master_index = 9.
86398  *  0b1011..The gate has been locked by processor with master_index = 10.
86399  *  0b1100..The gate has been locked by processor with master_index = 11.
86400  *  0b1101..The gate has been locked by processor with master_index = 12.
86401  *  0b1110..The gate has been locked by processor with master_index = 13.
86402  *  0b1111..The gate has been locked by processor with master_index = 14.
86403  */
86404 #define RDC_SEMAPHORE_GATE33_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK)
86405 
86406 #define RDC_SEMAPHORE_GATE33_LDOM_MASK           (0x30U)
86407 #define RDC_SEMAPHORE_GATE33_LDOM_SHIFT          (4U)
86408 /*! LDOM
86409  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86410  *  0b01..The gate has been locked by domain 1.
86411  *  0b10..The gate has been locked by domain 2.
86412  *  0b11..The gate has been locked by domain 3.
86413  */
86414 #define RDC_SEMAPHORE_GATE33_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK)
86415 /*! @} */
86416 
86417 /*! @name GATE34 - Gate Register */
86418 /*! @{ */
86419 
86420 #define RDC_SEMAPHORE_GATE34_GTFSM_MASK          (0xFU)
86421 #define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT         (0U)
86422 /*! GTFSM - Gate Finite State Machine.
86423  *  0b0000..The gate is unlocked (free).
86424  *  0b0001..The gate has been locked by processor with master_index = 0.
86425  *  0b0010..The gate has been locked by processor with master_index = 1.
86426  *  0b0011..The gate has been locked by processor with master_index = 2.
86427  *  0b0100..The gate has been locked by processor with master_index = 3.
86428  *  0b0101..The gate has been locked by processor with master_index = 4.
86429  *  0b0110..The gate has been locked by processor with master_index = 5.
86430  *  0b0111..The gate has been locked by processor with master_index = 6.
86431  *  0b1000..The gate has been locked by processor with master_index = 7.
86432  *  0b1001..The gate has been locked by processor with master_index = 8.
86433  *  0b1010..The gate has been locked by processor with master_index = 9.
86434  *  0b1011..The gate has been locked by processor with master_index = 10.
86435  *  0b1100..The gate has been locked by processor with master_index = 11.
86436  *  0b1101..The gate has been locked by processor with master_index = 12.
86437  *  0b1110..The gate has been locked by processor with master_index = 13.
86438  *  0b1111..The gate has been locked by processor with master_index = 14.
86439  */
86440 #define RDC_SEMAPHORE_GATE34_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK)
86441 
86442 #define RDC_SEMAPHORE_GATE34_LDOM_MASK           (0x30U)
86443 #define RDC_SEMAPHORE_GATE34_LDOM_SHIFT          (4U)
86444 /*! LDOM
86445  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86446  *  0b01..The gate has been locked by domain 1.
86447  *  0b10..The gate has been locked by domain 2.
86448  *  0b11..The gate has been locked by domain 3.
86449  */
86450 #define RDC_SEMAPHORE_GATE34_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK)
86451 /*! @} */
86452 
86453 /*! @name GATE35 - Gate Register */
86454 /*! @{ */
86455 
86456 #define RDC_SEMAPHORE_GATE35_GTFSM_MASK          (0xFU)
86457 #define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT         (0U)
86458 /*! GTFSM - Gate Finite State Machine.
86459  *  0b0000..The gate is unlocked (free).
86460  *  0b0001..The gate has been locked by processor with master_index = 0.
86461  *  0b0010..The gate has been locked by processor with master_index = 1.
86462  *  0b0011..The gate has been locked by processor with master_index = 2.
86463  *  0b0100..The gate has been locked by processor with master_index = 3.
86464  *  0b0101..The gate has been locked by processor with master_index = 4.
86465  *  0b0110..The gate has been locked by processor with master_index = 5.
86466  *  0b0111..The gate has been locked by processor with master_index = 6.
86467  *  0b1000..The gate has been locked by processor with master_index = 7.
86468  *  0b1001..The gate has been locked by processor with master_index = 8.
86469  *  0b1010..The gate has been locked by processor with master_index = 9.
86470  *  0b1011..The gate has been locked by processor with master_index = 10.
86471  *  0b1100..The gate has been locked by processor with master_index = 11.
86472  *  0b1101..The gate has been locked by processor with master_index = 12.
86473  *  0b1110..The gate has been locked by processor with master_index = 13.
86474  *  0b1111..The gate has been locked by processor with master_index = 14.
86475  */
86476 #define RDC_SEMAPHORE_GATE35_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK)
86477 
86478 #define RDC_SEMAPHORE_GATE35_LDOM_MASK           (0x30U)
86479 #define RDC_SEMAPHORE_GATE35_LDOM_SHIFT          (4U)
86480 /*! LDOM
86481  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86482  *  0b01..The gate has been locked by domain 1.
86483  *  0b10..The gate has been locked by domain 2.
86484  *  0b11..The gate has been locked by domain 3.
86485  */
86486 #define RDC_SEMAPHORE_GATE35_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK)
86487 /*! @} */
86488 
86489 /*! @name GATE36 - Gate Register */
86490 /*! @{ */
86491 
86492 #define RDC_SEMAPHORE_GATE36_GTFSM_MASK          (0xFU)
86493 #define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT         (0U)
86494 /*! GTFSM - Gate Finite State Machine.
86495  *  0b0000..The gate is unlocked (free).
86496  *  0b0001..The gate has been locked by processor with master_index = 0.
86497  *  0b0010..The gate has been locked by processor with master_index = 1.
86498  *  0b0011..The gate has been locked by processor with master_index = 2.
86499  *  0b0100..The gate has been locked by processor with master_index = 3.
86500  *  0b0101..The gate has been locked by processor with master_index = 4.
86501  *  0b0110..The gate has been locked by processor with master_index = 5.
86502  *  0b0111..The gate has been locked by processor with master_index = 6.
86503  *  0b1000..The gate has been locked by processor with master_index = 7.
86504  *  0b1001..The gate has been locked by processor with master_index = 8.
86505  *  0b1010..The gate has been locked by processor with master_index = 9.
86506  *  0b1011..The gate has been locked by processor with master_index = 10.
86507  *  0b1100..The gate has been locked by processor with master_index = 11.
86508  *  0b1101..The gate has been locked by processor with master_index = 12.
86509  *  0b1110..The gate has been locked by processor with master_index = 13.
86510  *  0b1111..The gate has been locked by processor with master_index = 14.
86511  */
86512 #define RDC_SEMAPHORE_GATE36_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK)
86513 
86514 #define RDC_SEMAPHORE_GATE36_LDOM_MASK           (0x30U)
86515 #define RDC_SEMAPHORE_GATE36_LDOM_SHIFT          (4U)
86516 /*! LDOM
86517  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86518  *  0b01..The gate has been locked by domain 1.
86519  *  0b10..The gate has been locked by domain 2.
86520  *  0b11..The gate has been locked by domain 3.
86521  */
86522 #define RDC_SEMAPHORE_GATE36_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK)
86523 /*! @} */
86524 
86525 /*! @name GATE37 - Gate Register */
86526 /*! @{ */
86527 
86528 #define RDC_SEMAPHORE_GATE37_GTFSM_MASK          (0xFU)
86529 #define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT         (0U)
86530 /*! GTFSM - Gate Finite State Machine.
86531  *  0b0000..The gate is unlocked (free).
86532  *  0b0001..The gate has been locked by processor with master_index = 0.
86533  *  0b0010..The gate has been locked by processor with master_index = 1.
86534  *  0b0011..The gate has been locked by processor with master_index = 2.
86535  *  0b0100..The gate has been locked by processor with master_index = 3.
86536  *  0b0101..The gate has been locked by processor with master_index = 4.
86537  *  0b0110..The gate has been locked by processor with master_index = 5.
86538  *  0b0111..The gate has been locked by processor with master_index = 6.
86539  *  0b1000..The gate has been locked by processor with master_index = 7.
86540  *  0b1001..The gate has been locked by processor with master_index = 8.
86541  *  0b1010..The gate has been locked by processor with master_index = 9.
86542  *  0b1011..The gate has been locked by processor with master_index = 10.
86543  *  0b1100..The gate has been locked by processor with master_index = 11.
86544  *  0b1101..The gate has been locked by processor with master_index = 12.
86545  *  0b1110..The gate has been locked by processor with master_index = 13.
86546  *  0b1111..The gate has been locked by processor with master_index = 14.
86547  */
86548 #define RDC_SEMAPHORE_GATE37_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK)
86549 
86550 #define RDC_SEMAPHORE_GATE37_LDOM_MASK           (0x30U)
86551 #define RDC_SEMAPHORE_GATE37_LDOM_SHIFT          (4U)
86552 /*! LDOM
86553  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86554  *  0b01..The gate has been locked by domain 1.
86555  *  0b10..The gate has been locked by domain 2.
86556  *  0b11..The gate has been locked by domain 3.
86557  */
86558 #define RDC_SEMAPHORE_GATE37_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK)
86559 /*! @} */
86560 
86561 /*! @name GATE38 - Gate Register */
86562 /*! @{ */
86563 
86564 #define RDC_SEMAPHORE_GATE38_GTFSM_MASK          (0xFU)
86565 #define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT         (0U)
86566 /*! GTFSM - Gate Finite State Machine.
86567  *  0b0000..The gate is unlocked (free).
86568  *  0b0001..The gate has been locked by processor with master_index = 0.
86569  *  0b0010..The gate has been locked by processor with master_index = 1.
86570  *  0b0011..The gate has been locked by processor with master_index = 2.
86571  *  0b0100..The gate has been locked by processor with master_index = 3.
86572  *  0b0101..The gate has been locked by processor with master_index = 4.
86573  *  0b0110..The gate has been locked by processor with master_index = 5.
86574  *  0b0111..The gate has been locked by processor with master_index = 6.
86575  *  0b1000..The gate has been locked by processor with master_index = 7.
86576  *  0b1001..The gate has been locked by processor with master_index = 8.
86577  *  0b1010..The gate has been locked by processor with master_index = 9.
86578  *  0b1011..The gate has been locked by processor with master_index = 10.
86579  *  0b1100..The gate has been locked by processor with master_index = 11.
86580  *  0b1101..The gate has been locked by processor with master_index = 12.
86581  *  0b1110..The gate has been locked by processor with master_index = 13.
86582  *  0b1111..The gate has been locked by processor with master_index = 14.
86583  */
86584 #define RDC_SEMAPHORE_GATE38_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK)
86585 
86586 #define RDC_SEMAPHORE_GATE38_LDOM_MASK           (0x30U)
86587 #define RDC_SEMAPHORE_GATE38_LDOM_SHIFT          (4U)
86588 /*! LDOM
86589  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86590  *  0b01..The gate has been locked by domain 1.
86591  *  0b10..The gate has been locked by domain 2.
86592  *  0b11..The gate has been locked by domain 3.
86593  */
86594 #define RDC_SEMAPHORE_GATE38_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK)
86595 /*! @} */
86596 
86597 /*! @name GATE39 - Gate Register */
86598 /*! @{ */
86599 
86600 #define RDC_SEMAPHORE_GATE39_GTFSM_MASK          (0xFU)
86601 #define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT         (0U)
86602 /*! GTFSM - Gate Finite State Machine.
86603  *  0b0000..The gate is unlocked (free).
86604  *  0b0001..The gate has been locked by processor with master_index = 0.
86605  *  0b0010..The gate has been locked by processor with master_index = 1.
86606  *  0b0011..The gate has been locked by processor with master_index = 2.
86607  *  0b0100..The gate has been locked by processor with master_index = 3.
86608  *  0b0101..The gate has been locked by processor with master_index = 4.
86609  *  0b0110..The gate has been locked by processor with master_index = 5.
86610  *  0b0111..The gate has been locked by processor with master_index = 6.
86611  *  0b1000..The gate has been locked by processor with master_index = 7.
86612  *  0b1001..The gate has been locked by processor with master_index = 8.
86613  *  0b1010..The gate has been locked by processor with master_index = 9.
86614  *  0b1011..The gate has been locked by processor with master_index = 10.
86615  *  0b1100..The gate has been locked by processor with master_index = 11.
86616  *  0b1101..The gate has been locked by processor with master_index = 12.
86617  *  0b1110..The gate has been locked by processor with master_index = 13.
86618  *  0b1111..The gate has been locked by processor with master_index = 14.
86619  */
86620 #define RDC_SEMAPHORE_GATE39_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK)
86621 
86622 #define RDC_SEMAPHORE_GATE39_LDOM_MASK           (0x30U)
86623 #define RDC_SEMAPHORE_GATE39_LDOM_SHIFT          (4U)
86624 /*! LDOM
86625  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86626  *  0b01..The gate has been locked by domain 1.
86627  *  0b10..The gate has been locked by domain 2.
86628  *  0b11..The gate has been locked by domain 3.
86629  */
86630 #define RDC_SEMAPHORE_GATE39_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK)
86631 /*! @} */
86632 
86633 /*! @name GATE40 - Gate Register */
86634 /*! @{ */
86635 
86636 #define RDC_SEMAPHORE_GATE40_GTFSM_MASK          (0xFU)
86637 #define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT         (0U)
86638 /*! GTFSM - Gate Finite State Machine.
86639  *  0b0000..The gate is unlocked (free).
86640  *  0b0001..The gate has been locked by processor with master_index = 0.
86641  *  0b0010..The gate has been locked by processor with master_index = 1.
86642  *  0b0011..The gate has been locked by processor with master_index = 2.
86643  *  0b0100..The gate has been locked by processor with master_index = 3.
86644  *  0b0101..The gate has been locked by processor with master_index = 4.
86645  *  0b0110..The gate has been locked by processor with master_index = 5.
86646  *  0b0111..The gate has been locked by processor with master_index = 6.
86647  *  0b1000..The gate has been locked by processor with master_index = 7.
86648  *  0b1001..The gate has been locked by processor with master_index = 8.
86649  *  0b1010..The gate has been locked by processor with master_index = 9.
86650  *  0b1011..The gate has been locked by processor with master_index = 10.
86651  *  0b1100..The gate has been locked by processor with master_index = 11.
86652  *  0b1101..The gate has been locked by processor with master_index = 12.
86653  *  0b1110..The gate has been locked by processor with master_index = 13.
86654  *  0b1111..The gate has been locked by processor with master_index = 14.
86655  */
86656 #define RDC_SEMAPHORE_GATE40_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK)
86657 
86658 #define RDC_SEMAPHORE_GATE40_LDOM_MASK           (0x30U)
86659 #define RDC_SEMAPHORE_GATE40_LDOM_SHIFT          (4U)
86660 /*! LDOM
86661  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86662  *  0b01..The gate has been locked by domain 1.
86663  *  0b10..The gate has been locked by domain 2.
86664  *  0b11..The gate has been locked by domain 3.
86665  */
86666 #define RDC_SEMAPHORE_GATE40_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK)
86667 /*! @} */
86668 
86669 /*! @name GATE41 - Gate Register */
86670 /*! @{ */
86671 
86672 #define RDC_SEMAPHORE_GATE41_GTFSM_MASK          (0xFU)
86673 #define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT         (0U)
86674 /*! GTFSM - Gate Finite State Machine.
86675  *  0b0000..The gate is unlocked (free).
86676  *  0b0001..The gate has been locked by processor with master_index = 0.
86677  *  0b0010..The gate has been locked by processor with master_index = 1.
86678  *  0b0011..The gate has been locked by processor with master_index = 2.
86679  *  0b0100..The gate has been locked by processor with master_index = 3.
86680  *  0b0101..The gate has been locked by processor with master_index = 4.
86681  *  0b0110..The gate has been locked by processor with master_index = 5.
86682  *  0b0111..The gate has been locked by processor with master_index = 6.
86683  *  0b1000..The gate has been locked by processor with master_index = 7.
86684  *  0b1001..The gate has been locked by processor with master_index = 8.
86685  *  0b1010..The gate has been locked by processor with master_index = 9.
86686  *  0b1011..The gate has been locked by processor with master_index = 10.
86687  *  0b1100..The gate has been locked by processor with master_index = 11.
86688  *  0b1101..The gate has been locked by processor with master_index = 12.
86689  *  0b1110..The gate has been locked by processor with master_index = 13.
86690  *  0b1111..The gate has been locked by processor with master_index = 14.
86691  */
86692 #define RDC_SEMAPHORE_GATE41_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK)
86693 
86694 #define RDC_SEMAPHORE_GATE41_LDOM_MASK           (0x30U)
86695 #define RDC_SEMAPHORE_GATE41_LDOM_SHIFT          (4U)
86696 /*! LDOM
86697  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86698  *  0b01..The gate has been locked by domain 1.
86699  *  0b10..The gate has been locked by domain 2.
86700  *  0b11..The gate has been locked by domain 3.
86701  */
86702 #define RDC_SEMAPHORE_GATE41_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK)
86703 /*! @} */
86704 
86705 /*! @name GATE42 - Gate Register */
86706 /*! @{ */
86707 
86708 #define RDC_SEMAPHORE_GATE42_GTFSM_MASK          (0xFU)
86709 #define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT         (0U)
86710 /*! GTFSM - Gate Finite State Machine.
86711  *  0b0000..The gate is unlocked (free).
86712  *  0b0001..The gate has been locked by processor with master_index = 0.
86713  *  0b0010..The gate has been locked by processor with master_index = 1.
86714  *  0b0011..The gate has been locked by processor with master_index = 2.
86715  *  0b0100..The gate has been locked by processor with master_index = 3.
86716  *  0b0101..The gate has been locked by processor with master_index = 4.
86717  *  0b0110..The gate has been locked by processor with master_index = 5.
86718  *  0b0111..The gate has been locked by processor with master_index = 6.
86719  *  0b1000..The gate has been locked by processor with master_index = 7.
86720  *  0b1001..The gate has been locked by processor with master_index = 8.
86721  *  0b1010..The gate has been locked by processor with master_index = 9.
86722  *  0b1011..The gate has been locked by processor with master_index = 10.
86723  *  0b1100..The gate has been locked by processor with master_index = 11.
86724  *  0b1101..The gate has been locked by processor with master_index = 12.
86725  *  0b1110..The gate has been locked by processor with master_index = 13.
86726  *  0b1111..The gate has been locked by processor with master_index = 14.
86727  */
86728 #define RDC_SEMAPHORE_GATE42_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK)
86729 
86730 #define RDC_SEMAPHORE_GATE42_LDOM_MASK           (0x30U)
86731 #define RDC_SEMAPHORE_GATE42_LDOM_SHIFT          (4U)
86732 /*! LDOM
86733  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86734  *  0b01..The gate has been locked by domain 1.
86735  *  0b10..The gate has been locked by domain 2.
86736  *  0b11..The gate has been locked by domain 3.
86737  */
86738 #define RDC_SEMAPHORE_GATE42_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK)
86739 /*! @} */
86740 
86741 /*! @name GATE43 - Gate Register */
86742 /*! @{ */
86743 
86744 #define RDC_SEMAPHORE_GATE43_GTFSM_MASK          (0xFU)
86745 #define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT         (0U)
86746 /*! GTFSM - Gate Finite State Machine.
86747  *  0b0000..The gate is unlocked (free).
86748  *  0b0001..The gate has been locked by processor with master_index = 0.
86749  *  0b0010..The gate has been locked by processor with master_index = 1.
86750  *  0b0011..The gate has been locked by processor with master_index = 2.
86751  *  0b0100..The gate has been locked by processor with master_index = 3.
86752  *  0b0101..The gate has been locked by processor with master_index = 4.
86753  *  0b0110..The gate has been locked by processor with master_index = 5.
86754  *  0b0111..The gate has been locked by processor with master_index = 6.
86755  *  0b1000..The gate has been locked by processor with master_index = 7.
86756  *  0b1001..The gate has been locked by processor with master_index = 8.
86757  *  0b1010..The gate has been locked by processor with master_index = 9.
86758  *  0b1011..The gate has been locked by processor with master_index = 10.
86759  *  0b1100..The gate has been locked by processor with master_index = 11.
86760  *  0b1101..The gate has been locked by processor with master_index = 12.
86761  *  0b1110..The gate has been locked by processor with master_index = 13.
86762  *  0b1111..The gate has been locked by processor with master_index = 14.
86763  */
86764 #define RDC_SEMAPHORE_GATE43_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK)
86765 
86766 #define RDC_SEMAPHORE_GATE43_LDOM_MASK           (0x30U)
86767 #define RDC_SEMAPHORE_GATE43_LDOM_SHIFT          (4U)
86768 /*! LDOM
86769  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86770  *  0b01..The gate has been locked by domain 1.
86771  *  0b10..The gate has been locked by domain 2.
86772  *  0b11..The gate has been locked by domain 3.
86773  */
86774 #define RDC_SEMAPHORE_GATE43_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK)
86775 /*! @} */
86776 
86777 /*! @name GATE44 - Gate Register */
86778 /*! @{ */
86779 
86780 #define RDC_SEMAPHORE_GATE44_GTFSM_MASK          (0xFU)
86781 #define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT         (0U)
86782 /*! GTFSM - Gate Finite State Machine.
86783  *  0b0000..The gate is unlocked (free).
86784  *  0b0001..The gate has been locked by processor with master_index = 0.
86785  *  0b0010..The gate has been locked by processor with master_index = 1.
86786  *  0b0011..The gate has been locked by processor with master_index = 2.
86787  *  0b0100..The gate has been locked by processor with master_index = 3.
86788  *  0b0101..The gate has been locked by processor with master_index = 4.
86789  *  0b0110..The gate has been locked by processor with master_index = 5.
86790  *  0b0111..The gate has been locked by processor with master_index = 6.
86791  *  0b1000..The gate has been locked by processor with master_index = 7.
86792  *  0b1001..The gate has been locked by processor with master_index = 8.
86793  *  0b1010..The gate has been locked by processor with master_index = 9.
86794  *  0b1011..The gate has been locked by processor with master_index = 10.
86795  *  0b1100..The gate has been locked by processor with master_index = 11.
86796  *  0b1101..The gate has been locked by processor with master_index = 12.
86797  *  0b1110..The gate has been locked by processor with master_index = 13.
86798  *  0b1111..The gate has been locked by processor with master_index = 14.
86799  */
86800 #define RDC_SEMAPHORE_GATE44_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK)
86801 
86802 #define RDC_SEMAPHORE_GATE44_LDOM_MASK           (0x30U)
86803 #define RDC_SEMAPHORE_GATE44_LDOM_SHIFT          (4U)
86804 /*! LDOM
86805  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86806  *  0b01..The gate has been locked by domain 1.
86807  *  0b10..The gate has been locked by domain 2.
86808  *  0b11..The gate has been locked by domain 3.
86809  */
86810 #define RDC_SEMAPHORE_GATE44_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK)
86811 /*! @} */
86812 
86813 /*! @name GATE45 - Gate Register */
86814 /*! @{ */
86815 
86816 #define RDC_SEMAPHORE_GATE45_GTFSM_MASK          (0xFU)
86817 #define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT         (0U)
86818 /*! GTFSM - Gate Finite State Machine.
86819  *  0b0000..The gate is unlocked (free).
86820  *  0b0001..The gate has been locked by processor with master_index = 0.
86821  *  0b0010..The gate has been locked by processor with master_index = 1.
86822  *  0b0011..The gate has been locked by processor with master_index = 2.
86823  *  0b0100..The gate has been locked by processor with master_index = 3.
86824  *  0b0101..The gate has been locked by processor with master_index = 4.
86825  *  0b0110..The gate has been locked by processor with master_index = 5.
86826  *  0b0111..The gate has been locked by processor with master_index = 6.
86827  *  0b1000..The gate has been locked by processor with master_index = 7.
86828  *  0b1001..The gate has been locked by processor with master_index = 8.
86829  *  0b1010..The gate has been locked by processor with master_index = 9.
86830  *  0b1011..The gate has been locked by processor with master_index = 10.
86831  *  0b1100..The gate has been locked by processor with master_index = 11.
86832  *  0b1101..The gate has been locked by processor with master_index = 12.
86833  *  0b1110..The gate has been locked by processor with master_index = 13.
86834  *  0b1111..The gate has been locked by processor with master_index = 14.
86835  */
86836 #define RDC_SEMAPHORE_GATE45_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK)
86837 
86838 #define RDC_SEMAPHORE_GATE45_LDOM_MASK           (0x30U)
86839 #define RDC_SEMAPHORE_GATE45_LDOM_SHIFT          (4U)
86840 /*! LDOM
86841  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86842  *  0b01..The gate has been locked by domain 1.
86843  *  0b10..The gate has been locked by domain 2.
86844  *  0b11..The gate has been locked by domain 3.
86845  */
86846 #define RDC_SEMAPHORE_GATE45_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK)
86847 /*! @} */
86848 
86849 /*! @name GATE46 - Gate Register */
86850 /*! @{ */
86851 
86852 #define RDC_SEMAPHORE_GATE46_GTFSM_MASK          (0xFU)
86853 #define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT         (0U)
86854 /*! GTFSM - Gate Finite State Machine.
86855  *  0b0000..The gate is unlocked (free).
86856  *  0b0001..The gate has been locked by processor with master_index = 0.
86857  *  0b0010..The gate has been locked by processor with master_index = 1.
86858  *  0b0011..The gate has been locked by processor with master_index = 2.
86859  *  0b0100..The gate has been locked by processor with master_index = 3.
86860  *  0b0101..The gate has been locked by processor with master_index = 4.
86861  *  0b0110..The gate has been locked by processor with master_index = 5.
86862  *  0b0111..The gate has been locked by processor with master_index = 6.
86863  *  0b1000..The gate has been locked by processor with master_index = 7.
86864  *  0b1001..The gate has been locked by processor with master_index = 8.
86865  *  0b1010..The gate has been locked by processor with master_index = 9.
86866  *  0b1011..The gate has been locked by processor with master_index = 10.
86867  *  0b1100..The gate has been locked by processor with master_index = 11.
86868  *  0b1101..The gate has been locked by processor with master_index = 12.
86869  *  0b1110..The gate has been locked by processor with master_index = 13.
86870  *  0b1111..The gate has been locked by processor with master_index = 14.
86871  */
86872 #define RDC_SEMAPHORE_GATE46_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK)
86873 
86874 #define RDC_SEMAPHORE_GATE46_LDOM_MASK           (0x30U)
86875 #define RDC_SEMAPHORE_GATE46_LDOM_SHIFT          (4U)
86876 /*! LDOM
86877  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86878  *  0b01..The gate has been locked by domain 1.
86879  *  0b10..The gate has been locked by domain 2.
86880  *  0b11..The gate has been locked by domain 3.
86881  */
86882 #define RDC_SEMAPHORE_GATE46_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK)
86883 /*! @} */
86884 
86885 /*! @name GATE47 - Gate Register */
86886 /*! @{ */
86887 
86888 #define RDC_SEMAPHORE_GATE47_GTFSM_MASK          (0xFU)
86889 #define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT         (0U)
86890 /*! GTFSM - Gate Finite State Machine.
86891  *  0b0000..The gate is unlocked (free).
86892  *  0b0001..The gate has been locked by processor with master_index = 0.
86893  *  0b0010..The gate has been locked by processor with master_index = 1.
86894  *  0b0011..The gate has been locked by processor with master_index = 2.
86895  *  0b0100..The gate has been locked by processor with master_index = 3.
86896  *  0b0101..The gate has been locked by processor with master_index = 4.
86897  *  0b0110..The gate has been locked by processor with master_index = 5.
86898  *  0b0111..The gate has been locked by processor with master_index = 6.
86899  *  0b1000..The gate has been locked by processor with master_index = 7.
86900  *  0b1001..The gate has been locked by processor with master_index = 8.
86901  *  0b1010..The gate has been locked by processor with master_index = 9.
86902  *  0b1011..The gate has been locked by processor with master_index = 10.
86903  *  0b1100..The gate has been locked by processor with master_index = 11.
86904  *  0b1101..The gate has been locked by processor with master_index = 12.
86905  *  0b1110..The gate has been locked by processor with master_index = 13.
86906  *  0b1111..The gate has been locked by processor with master_index = 14.
86907  */
86908 #define RDC_SEMAPHORE_GATE47_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK)
86909 
86910 #define RDC_SEMAPHORE_GATE47_LDOM_MASK           (0x30U)
86911 #define RDC_SEMAPHORE_GATE47_LDOM_SHIFT          (4U)
86912 /*! LDOM
86913  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86914  *  0b01..The gate has been locked by domain 1.
86915  *  0b10..The gate has been locked by domain 2.
86916  *  0b11..The gate has been locked by domain 3.
86917  */
86918 #define RDC_SEMAPHORE_GATE47_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK)
86919 /*! @} */
86920 
86921 /*! @name GATE48 - Gate Register */
86922 /*! @{ */
86923 
86924 #define RDC_SEMAPHORE_GATE48_GTFSM_MASK          (0xFU)
86925 #define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT         (0U)
86926 /*! GTFSM - Gate Finite State Machine.
86927  *  0b0000..The gate is unlocked (free).
86928  *  0b0001..The gate has been locked by processor with master_index = 0.
86929  *  0b0010..The gate has been locked by processor with master_index = 1.
86930  *  0b0011..The gate has been locked by processor with master_index = 2.
86931  *  0b0100..The gate has been locked by processor with master_index = 3.
86932  *  0b0101..The gate has been locked by processor with master_index = 4.
86933  *  0b0110..The gate has been locked by processor with master_index = 5.
86934  *  0b0111..The gate has been locked by processor with master_index = 6.
86935  *  0b1000..The gate has been locked by processor with master_index = 7.
86936  *  0b1001..The gate has been locked by processor with master_index = 8.
86937  *  0b1010..The gate has been locked by processor with master_index = 9.
86938  *  0b1011..The gate has been locked by processor with master_index = 10.
86939  *  0b1100..The gate has been locked by processor with master_index = 11.
86940  *  0b1101..The gate has been locked by processor with master_index = 12.
86941  *  0b1110..The gate has been locked by processor with master_index = 13.
86942  *  0b1111..The gate has been locked by processor with master_index = 14.
86943  */
86944 #define RDC_SEMAPHORE_GATE48_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK)
86945 
86946 #define RDC_SEMAPHORE_GATE48_LDOM_MASK           (0x30U)
86947 #define RDC_SEMAPHORE_GATE48_LDOM_SHIFT          (4U)
86948 /*! LDOM
86949  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86950  *  0b01..The gate has been locked by domain 1.
86951  *  0b10..The gate has been locked by domain 2.
86952  *  0b11..The gate has been locked by domain 3.
86953  */
86954 #define RDC_SEMAPHORE_GATE48_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK)
86955 /*! @} */
86956 
86957 /*! @name GATE49 - Gate Register */
86958 /*! @{ */
86959 
86960 #define RDC_SEMAPHORE_GATE49_GTFSM_MASK          (0xFU)
86961 #define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT         (0U)
86962 /*! GTFSM - Gate Finite State Machine.
86963  *  0b0000..The gate is unlocked (free).
86964  *  0b0001..The gate has been locked by processor with master_index = 0.
86965  *  0b0010..The gate has been locked by processor with master_index = 1.
86966  *  0b0011..The gate has been locked by processor with master_index = 2.
86967  *  0b0100..The gate has been locked by processor with master_index = 3.
86968  *  0b0101..The gate has been locked by processor with master_index = 4.
86969  *  0b0110..The gate has been locked by processor with master_index = 5.
86970  *  0b0111..The gate has been locked by processor with master_index = 6.
86971  *  0b1000..The gate has been locked by processor with master_index = 7.
86972  *  0b1001..The gate has been locked by processor with master_index = 8.
86973  *  0b1010..The gate has been locked by processor with master_index = 9.
86974  *  0b1011..The gate has been locked by processor with master_index = 10.
86975  *  0b1100..The gate has been locked by processor with master_index = 11.
86976  *  0b1101..The gate has been locked by processor with master_index = 12.
86977  *  0b1110..The gate has been locked by processor with master_index = 13.
86978  *  0b1111..The gate has been locked by processor with master_index = 14.
86979  */
86980 #define RDC_SEMAPHORE_GATE49_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK)
86981 
86982 #define RDC_SEMAPHORE_GATE49_LDOM_MASK           (0x30U)
86983 #define RDC_SEMAPHORE_GATE49_LDOM_SHIFT          (4U)
86984 /*! LDOM
86985  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
86986  *  0b01..The gate has been locked by domain 1.
86987  *  0b10..The gate has been locked by domain 2.
86988  *  0b11..The gate has been locked by domain 3.
86989  */
86990 #define RDC_SEMAPHORE_GATE49_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK)
86991 /*! @} */
86992 
86993 /*! @name GATE50 - Gate Register */
86994 /*! @{ */
86995 
86996 #define RDC_SEMAPHORE_GATE50_GTFSM_MASK          (0xFU)
86997 #define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT         (0U)
86998 /*! GTFSM - Gate Finite State Machine.
86999  *  0b0000..The gate is unlocked (free).
87000  *  0b0001..The gate has been locked by processor with master_index = 0.
87001  *  0b0010..The gate has been locked by processor with master_index = 1.
87002  *  0b0011..The gate has been locked by processor with master_index = 2.
87003  *  0b0100..The gate has been locked by processor with master_index = 3.
87004  *  0b0101..The gate has been locked by processor with master_index = 4.
87005  *  0b0110..The gate has been locked by processor with master_index = 5.
87006  *  0b0111..The gate has been locked by processor with master_index = 6.
87007  *  0b1000..The gate has been locked by processor with master_index = 7.
87008  *  0b1001..The gate has been locked by processor with master_index = 8.
87009  *  0b1010..The gate has been locked by processor with master_index = 9.
87010  *  0b1011..The gate has been locked by processor with master_index = 10.
87011  *  0b1100..The gate has been locked by processor with master_index = 11.
87012  *  0b1101..The gate has been locked by processor with master_index = 12.
87013  *  0b1110..The gate has been locked by processor with master_index = 13.
87014  *  0b1111..The gate has been locked by processor with master_index = 14.
87015  */
87016 #define RDC_SEMAPHORE_GATE50_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK)
87017 
87018 #define RDC_SEMAPHORE_GATE50_LDOM_MASK           (0x30U)
87019 #define RDC_SEMAPHORE_GATE50_LDOM_SHIFT          (4U)
87020 /*! LDOM
87021  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87022  *  0b01..The gate has been locked by domain 1.
87023  *  0b10..The gate has been locked by domain 2.
87024  *  0b11..The gate has been locked by domain 3.
87025  */
87026 #define RDC_SEMAPHORE_GATE50_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK)
87027 /*! @} */
87028 
87029 /*! @name GATE51 - Gate Register */
87030 /*! @{ */
87031 
87032 #define RDC_SEMAPHORE_GATE51_GTFSM_MASK          (0xFU)
87033 #define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT         (0U)
87034 /*! GTFSM - Gate Finite State Machine.
87035  *  0b0000..The gate is unlocked (free).
87036  *  0b0001..The gate has been locked by processor with master_index = 0.
87037  *  0b0010..The gate has been locked by processor with master_index = 1.
87038  *  0b0011..The gate has been locked by processor with master_index = 2.
87039  *  0b0100..The gate has been locked by processor with master_index = 3.
87040  *  0b0101..The gate has been locked by processor with master_index = 4.
87041  *  0b0110..The gate has been locked by processor with master_index = 5.
87042  *  0b0111..The gate has been locked by processor with master_index = 6.
87043  *  0b1000..The gate has been locked by processor with master_index = 7.
87044  *  0b1001..The gate has been locked by processor with master_index = 8.
87045  *  0b1010..The gate has been locked by processor with master_index = 9.
87046  *  0b1011..The gate has been locked by processor with master_index = 10.
87047  *  0b1100..The gate has been locked by processor with master_index = 11.
87048  *  0b1101..The gate has been locked by processor with master_index = 12.
87049  *  0b1110..The gate has been locked by processor with master_index = 13.
87050  *  0b1111..The gate has been locked by processor with master_index = 14.
87051  */
87052 #define RDC_SEMAPHORE_GATE51_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK)
87053 
87054 #define RDC_SEMAPHORE_GATE51_LDOM_MASK           (0x30U)
87055 #define RDC_SEMAPHORE_GATE51_LDOM_SHIFT          (4U)
87056 /*! LDOM
87057  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87058  *  0b01..The gate has been locked by domain 1.
87059  *  0b10..The gate has been locked by domain 2.
87060  *  0b11..The gate has been locked by domain 3.
87061  */
87062 #define RDC_SEMAPHORE_GATE51_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK)
87063 /*! @} */
87064 
87065 /*! @name GATE52 - Gate Register */
87066 /*! @{ */
87067 
87068 #define RDC_SEMAPHORE_GATE52_GTFSM_MASK          (0xFU)
87069 #define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT         (0U)
87070 /*! GTFSM - Gate Finite State Machine.
87071  *  0b0000..The gate is unlocked (free).
87072  *  0b0001..The gate has been locked by processor with master_index = 0.
87073  *  0b0010..The gate has been locked by processor with master_index = 1.
87074  *  0b0011..The gate has been locked by processor with master_index = 2.
87075  *  0b0100..The gate has been locked by processor with master_index = 3.
87076  *  0b0101..The gate has been locked by processor with master_index = 4.
87077  *  0b0110..The gate has been locked by processor with master_index = 5.
87078  *  0b0111..The gate has been locked by processor with master_index = 6.
87079  *  0b1000..The gate has been locked by processor with master_index = 7.
87080  *  0b1001..The gate has been locked by processor with master_index = 8.
87081  *  0b1010..The gate has been locked by processor with master_index = 9.
87082  *  0b1011..The gate has been locked by processor with master_index = 10.
87083  *  0b1100..The gate has been locked by processor with master_index = 11.
87084  *  0b1101..The gate has been locked by processor with master_index = 12.
87085  *  0b1110..The gate has been locked by processor with master_index = 13.
87086  *  0b1111..The gate has been locked by processor with master_index = 14.
87087  */
87088 #define RDC_SEMAPHORE_GATE52_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK)
87089 
87090 #define RDC_SEMAPHORE_GATE52_LDOM_MASK           (0x30U)
87091 #define RDC_SEMAPHORE_GATE52_LDOM_SHIFT          (4U)
87092 /*! LDOM
87093  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87094  *  0b01..The gate has been locked by domain 1.
87095  *  0b10..The gate has been locked by domain 2.
87096  *  0b11..The gate has been locked by domain 3.
87097  */
87098 #define RDC_SEMAPHORE_GATE52_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK)
87099 /*! @} */
87100 
87101 /*! @name GATE53 - Gate Register */
87102 /*! @{ */
87103 
87104 #define RDC_SEMAPHORE_GATE53_GTFSM_MASK          (0xFU)
87105 #define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT         (0U)
87106 /*! GTFSM - Gate Finite State Machine.
87107  *  0b0000..The gate is unlocked (free).
87108  *  0b0001..The gate has been locked by processor with master_index = 0.
87109  *  0b0010..The gate has been locked by processor with master_index = 1.
87110  *  0b0011..The gate has been locked by processor with master_index = 2.
87111  *  0b0100..The gate has been locked by processor with master_index = 3.
87112  *  0b0101..The gate has been locked by processor with master_index = 4.
87113  *  0b0110..The gate has been locked by processor with master_index = 5.
87114  *  0b0111..The gate has been locked by processor with master_index = 6.
87115  *  0b1000..The gate has been locked by processor with master_index = 7.
87116  *  0b1001..The gate has been locked by processor with master_index = 8.
87117  *  0b1010..The gate has been locked by processor with master_index = 9.
87118  *  0b1011..The gate has been locked by processor with master_index = 10.
87119  *  0b1100..The gate has been locked by processor with master_index = 11.
87120  *  0b1101..The gate has been locked by processor with master_index = 12.
87121  *  0b1110..The gate has been locked by processor with master_index = 13.
87122  *  0b1111..The gate has been locked by processor with master_index = 14.
87123  */
87124 #define RDC_SEMAPHORE_GATE53_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK)
87125 
87126 #define RDC_SEMAPHORE_GATE53_LDOM_MASK           (0x30U)
87127 #define RDC_SEMAPHORE_GATE53_LDOM_SHIFT          (4U)
87128 /*! LDOM
87129  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87130  *  0b01..The gate has been locked by domain 1.
87131  *  0b10..The gate has been locked by domain 2.
87132  *  0b11..The gate has been locked by domain 3.
87133  */
87134 #define RDC_SEMAPHORE_GATE53_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK)
87135 /*! @} */
87136 
87137 /*! @name GATE54 - Gate Register */
87138 /*! @{ */
87139 
87140 #define RDC_SEMAPHORE_GATE54_GTFSM_MASK          (0xFU)
87141 #define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT         (0U)
87142 /*! GTFSM - Gate Finite State Machine.
87143  *  0b0000..The gate is unlocked (free).
87144  *  0b0001..The gate has been locked by processor with master_index = 0.
87145  *  0b0010..The gate has been locked by processor with master_index = 1.
87146  *  0b0011..The gate has been locked by processor with master_index = 2.
87147  *  0b0100..The gate has been locked by processor with master_index = 3.
87148  *  0b0101..The gate has been locked by processor with master_index = 4.
87149  *  0b0110..The gate has been locked by processor with master_index = 5.
87150  *  0b0111..The gate has been locked by processor with master_index = 6.
87151  *  0b1000..The gate has been locked by processor with master_index = 7.
87152  *  0b1001..The gate has been locked by processor with master_index = 8.
87153  *  0b1010..The gate has been locked by processor with master_index = 9.
87154  *  0b1011..The gate has been locked by processor with master_index = 10.
87155  *  0b1100..The gate has been locked by processor with master_index = 11.
87156  *  0b1101..The gate has been locked by processor with master_index = 12.
87157  *  0b1110..The gate has been locked by processor with master_index = 13.
87158  *  0b1111..The gate has been locked by processor with master_index = 14.
87159  */
87160 #define RDC_SEMAPHORE_GATE54_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK)
87161 
87162 #define RDC_SEMAPHORE_GATE54_LDOM_MASK           (0x30U)
87163 #define RDC_SEMAPHORE_GATE54_LDOM_SHIFT          (4U)
87164 /*! LDOM
87165  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87166  *  0b01..The gate has been locked by domain 1.
87167  *  0b10..The gate has been locked by domain 2.
87168  *  0b11..The gate has been locked by domain 3.
87169  */
87170 #define RDC_SEMAPHORE_GATE54_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK)
87171 /*! @} */
87172 
87173 /*! @name GATE55 - Gate Register */
87174 /*! @{ */
87175 
87176 #define RDC_SEMAPHORE_GATE55_GTFSM_MASK          (0xFU)
87177 #define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT         (0U)
87178 /*! GTFSM - Gate Finite State Machine.
87179  *  0b0000..The gate is unlocked (free).
87180  *  0b0001..The gate has been locked by processor with master_index = 0.
87181  *  0b0010..The gate has been locked by processor with master_index = 1.
87182  *  0b0011..The gate has been locked by processor with master_index = 2.
87183  *  0b0100..The gate has been locked by processor with master_index = 3.
87184  *  0b0101..The gate has been locked by processor with master_index = 4.
87185  *  0b0110..The gate has been locked by processor with master_index = 5.
87186  *  0b0111..The gate has been locked by processor with master_index = 6.
87187  *  0b1000..The gate has been locked by processor with master_index = 7.
87188  *  0b1001..The gate has been locked by processor with master_index = 8.
87189  *  0b1010..The gate has been locked by processor with master_index = 9.
87190  *  0b1011..The gate has been locked by processor with master_index = 10.
87191  *  0b1100..The gate has been locked by processor with master_index = 11.
87192  *  0b1101..The gate has been locked by processor with master_index = 12.
87193  *  0b1110..The gate has been locked by processor with master_index = 13.
87194  *  0b1111..The gate has been locked by processor with master_index = 14.
87195  */
87196 #define RDC_SEMAPHORE_GATE55_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK)
87197 
87198 #define RDC_SEMAPHORE_GATE55_LDOM_MASK           (0x30U)
87199 #define RDC_SEMAPHORE_GATE55_LDOM_SHIFT          (4U)
87200 /*! LDOM
87201  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87202  *  0b01..The gate has been locked by domain 1.
87203  *  0b10..The gate has been locked by domain 2.
87204  *  0b11..The gate has been locked by domain 3.
87205  */
87206 #define RDC_SEMAPHORE_GATE55_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK)
87207 /*! @} */
87208 
87209 /*! @name GATE56 - Gate Register */
87210 /*! @{ */
87211 
87212 #define RDC_SEMAPHORE_GATE56_GTFSM_MASK          (0xFU)
87213 #define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT         (0U)
87214 /*! GTFSM - Gate Finite State Machine.
87215  *  0b0000..The gate is unlocked (free).
87216  *  0b0001..The gate has been locked by processor with master_index = 0.
87217  *  0b0010..The gate has been locked by processor with master_index = 1.
87218  *  0b0011..The gate has been locked by processor with master_index = 2.
87219  *  0b0100..The gate has been locked by processor with master_index = 3.
87220  *  0b0101..The gate has been locked by processor with master_index = 4.
87221  *  0b0110..The gate has been locked by processor with master_index = 5.
87222  *  0b0111..The gate has been locked by processor with master_index = 6.
87223  *  0b1000..The gate has been locked by processor with master_index = 7.
87224  *  0b1001..The gate has been locked by processor with master_index = 8.
87225  *  0b1010..The gate has been locked by processor with master_index = 9.
87226  *  0b1011..The gate has been locked by processor with master_index = 10.
87227  *  0b1100..The gate has been locked by processor with master_index = 11.
87228  *  0b1101..The gate has been locked by processor with master_index = 12.
87229  *  0b1110..The gate has been locked by processor with master_index = 13.
87230  *  0b1111..The gate has been locked by processor with master_index = 14.
87231  */
87232 #define RDC_SEMAPHORE_GATE56_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK)
87233 
87234 #define RDC_SEMAPHORE_GATE56_LDOM_MASK           (0x30U)
87235 #define RDC_SEMAPHORE_GATE56_LDOM_SHIFT          (4U)
87236 /*! LDOM
87237  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87238  *  0b01..The gate has been locked by domain 1.
87239  *  0b10..The gate has been locked by domain 2.
87240  *  0b11..The gate has been locked by domain 3.
87241  */
87242 #define RDC_SEMAPHORE_GATE56_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK)
87243 /*! @} */
87244 
87245 /*! @name GATE57 - Gate Register */
87246 /*! @{ */
87247 
87248 #define RDC_SEMAPHORE_GATE57_GTFSM_MASK          (0xFU)
87249 #define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT         (0U)
87250 /*! GTFSM - Gate Finite State Machine.
87251  *  0b0000..The gate is unlocked (free).
87252  *  0b0001..The gate has been locked by processor with master_index = 0.
87253  *  0b0010..The gate has been locked by processor with master_index = 1.
87254  *  0b0011..The gate has been locked by processor with master_index = 2.
87255  *  0b0100..The gate has been locked by processor with master_index = 3.
87256  *  0b0101..The gate has been locked by processor with master_index = 4.
87257  *  0b0110..The gate has been locked by processor with master_index = 5.
87258  *  0b0111..The gate has been locked by processor with master_index = 6.
87259  *  0b1000..The gate has been locked by processor with master_index = 7.
87260  *  0b1001..The gate has been locked by processor with master_index = 8.
87261  *  0b1010..The gate has been locked by processor with master_index = 9.
87262  *  0b1011..The gate has been locked by processor with master_index = 10.
87263  *  0b1100..The gate has been locked by processor with master_index = 11.
87264  *  0b1101..The gate has been locked by processor with master_index = 12.
87265  *  0b1110..The gate has been locked by processor with master_index = 13.
87266  *  0b1111..The gate has been locked by processor with master_index = 14.
87267  */
87268 #define RDC_SEMAPHORE_GATE57_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK)
87269 
87270 #define RDC_SEMAPHORE_GATE57_LDOM_MASK           (0x30U)
87271 #define RDC_SEMAPHORE_GATE57_LDOM_SHIFT          (4U)
87272 /*! LDOM
87273  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87274  *  0b01..The gate has been locked by domain 1.
87275  *  0b10..The gate has been locked by domain 2.
87276  *  0b11..The gate has been locked by domain 3.
87277  */
87278 #define RDC_SEMAPHORE_GATE57_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK)
87279 /*! @} */
87280 
87281 /*! @name GATE58 - Gate Register */
87282 /*! @{ */
87283 
87284 #define RDC_SEMAPHORE_GATE58_GTFSM_MASK          (0xFU)
87285 #define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT         (0U)
87286 /*! GTFSM - Gate Finite State Machine.
87287  *  0b0000..The gate is unlocked (free).
87288  *  0b0001..The gate has been locked by processor with master_index = 0.
87289  *  0b0010..The gate has been locked by processor with master_index = 1.
87290  *  0b0011..The gate has been locked by processor with master_index = 2.
87291  *  0b0100..The gate has been locked by processor with master_index = 3.
87292  *  0b0101..The gate has been locked by processor with master_index = 4.
87293  *  0b0110..The gate has been locked by processor with master_index = 5.
87294  *  0b0111..The gate has been locked by processor with master_index = 6.
87295  *  0b1000..The gate has been locked by processor with master_index = 7.
87296  *  0b1001..The gate has been locked by processor with master_index = 8.
87297  *  0b1010..The gate has been locked by processor with master_index = 9.
87298  *  0b1011..The gate has been locked by processor with master_index = 10.
87299  *  0b1100..The gate has been locked by processor with master_index = 11.
87300  *  0b1101..The gate has been locked by processor with master_index = 12.
87301  *  0b1110..The gate has been locked by processor with master_index = 13.
87302  *  0b1111..The gate has been locked by processor with master_index = 14.
87303  */
87304 #define RDC_SEMAPHORE_GATE58_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK)
87305 
87306 #define RDC_SEMAPHORE_GATE58_LDOM_MASK           (0x30U)
87307 #define RDC_SEMAPHORE_GATE58_LDOM_SHIFT          (4U)
87308 /*! LDOM
87309  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87310  *  0b01..The gate has been locked by domain 1.
87311  *  0b10..The gate has been locked by domain 2.
87312  *  0b11..The gate has been locked by domain 3.
87313  */
87314 #define RDC_SEMAPHORE_GATE58_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK)
87315 /*! @} */
87316 
87317 /*! @name GATE59 - Gate Register */
87318 /*! @{ */
87319 
87320 #define RDC_SEMAPHORE_GATE59_GTFSM_MASK          (0xFU)
87321 #define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT         (0U)
87322 /*! GTFSM - Gate Finite State Machine.
87323  *  0b0000..The gate is unlocked (free).
87324  *  0b0001..The gate has been locked by processor with master_index = 0.
87325  *  0b0010..The gate has been locked by processor with master_index = 1.
87326  *  0b0011..The gate has been locked by processor with master_index = 2.
87327  *  0b0100..The gate has been locked by processor with master_index = 3.
87328  *  0b0101..The gate has been locked by processor with master_index = 4.
87329  *  0b0110..The gate has been locked by processor with master_index = 5.
87330  *  0b0111..The gate has been locked by processor with master_index = 6.
87331  *  0b1000..The gate has been locked by processor with master_index = 7.
87332  *  0b1001..The gate has been locked by processor with master_index = 8.
87333  *  0b1010..The gate has been locked by processor with master_index = 9.
87334  *  0b1011..The gate has been locked by processor with master_index = 10.
87335  *  0b1100..The gate has been locked by processor with master_index = 11.
87336  *  0b1101..The gate has been locked by processor with master_index = 12.
87337  *  0b1110..The gate has been locked by processor with master_index = 13.
87338  *  0b1111..The gate has been locked by processor with master_index = 14.
87339  */
87340 #define RDC_SEMAPHORE_GATE59_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK)
87341 
87342 #define RDC_SEMAPHORE_GATE59_LDOM_MASK           (0x30U)
87343 #define RDC_SEMAPHORE_GATE59_LDOM_SHIFT          (4U)
87344 /*! LDOM
87345  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87346  *  0b01..The gate has been locked by domain 1.
87347  *  0b10..The gate has been locked by domain 2.
87348  *  0b11..The gate has been locked by domain 3.
87349  */
87350 #define RDC_SEMAPHORE_GATE59_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK)
87351 /*! @} */
87352 
87353 /*! @name GATE60 - Gate Register */
87354 /*! @{ */
87355 
87356 #define RDC_SEMAPHORE_GATE60_GTFSM_MASK          (0xFU)
87357 #define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT         (0U)
87358 /*! GTFSM - Gate Finite State Machine.
87359  *  0b0000..The gate is unlocked (free).
87360  *  0b0001..The gate has been locked by processor with master_index = 0.
87361  *  0b0010..The gate has been locked by processor with master_index = 1.
87362  *  0b0011..The gate has been locked by processor with master_index = 2.
87363  *  0b0100..The gate has been locked by processor with master_index = 3.
87364  *  0b0101..The gate has been locked by processor with master_index = 4.
87365  *  0b0110..The gate has been locked by processor with master_index = 5.
87366  *  0b0111..The gate has been locked by processor with master_index = 6.
87367  *  0b1000..The gate has been locked by processor with master_index = 7.
87368  *  0b1001..The gate has been locked by processor with master_index = 8.
87369  *  0b1010..The gate has been locked by processor with master_index = 9.
87370  *  0b1011..The gate has been locked by processor with master_index = 10.
87371  *  0b1100..The gate has been locked by processor with master_index = 11.
87372  *  0b1101..The gate has been locked by processor with master_index = 12.
87373  *  0b1110..The gate has been locked by processor with master_index = 13.
87374  *  0b1111..The gate has been locked by processor with master_index = 14.
87375  */
87376 #define RDC_SEMAPHORE_GATE60_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK)
87377 
87378 #define RDC_SEMAPHORE_GATE60_LDOM_MASK           (0x30U)
87379 #define RDC_SEMAPHORE_GATE60_LDOM_SHIFT          (4U)
87380 /*! LDOM
87381  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87382  *  0b01..The gate has been locked by domain 1.
87383  *  0b10..The gate has been locked by domain 2.
87384  *  0b11..The gate has been locked by domain 3.
87385  */
87386 #define RDC_SEMAPHORE_GATE60_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK)
87387 /*! @} */
87388 
87389 /*! @name GATE61 - Gate Register */
87390 /*! @{ */
87391 
87392 #define RDC_SEMAPHORE_GATE61_GTFSM_MASK          (0xFU)
87393 #define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT         (0U)
87394 /*! GTFSM - Gate Finite State Machine.
87395  *  0b0000..The gate is unlocked (free).
87396  *  0b0001..The gate has been locked by processor with master_index = 0.
87397  *  0b0010..The gate has been locked by processor with master_index = 1.
87398  *  0b0011..The gate has been locked by processor with master_index = 2.
87399  *  0b0100..The gate has been locked by processor with master_index = 3.
87400  *  0b0101..The gate has been locked by processor with master_index = 4.
87401  *  0b0110..The gate has been locked by processor with master_index = 5.
87402  *  0b0111..The gate has been locked by processor with master_index = 6.
87403  *  0b1000..The gate has been locked by processor with master_index = 7.
87404  *  0b1001..The gate has been locked by processor with master_index = 8.
87405  *  0b1010..The gate has been locked by processor with master_index = 9.
87406  *  0b1011..The gate has been locked by processor with master_index = 10.
87407  *  0b1100..The gate has been locked by processor with master_index = 11.
87408  *  0b1101..The gate has been locked by processor with master_index = 12.
87409  *  0b1110..The gate has been locked by processor with master_index = 13.
87410  *  0b1111..The gate has been locked by processor with master_index = 14.
87411  */
87412 #define RDC_SEMAPHORE_GATE61_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK)
87413 
87414 #define RDC_SEMAPHORE_GATE61_LDOM_MASK           (0x30U)
87415 #define RDC_SEMAPHORE_GATE61_LDOM_SHIFT          (4U)
87416 /*! LDOM
87417  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87418  *  0b01..The gate has been locked by domain 1.
87419  *  0b10..The gate has been locked by domain 2.
87420  *  0b11..The gate has been locked by domain 3.
87421  */
87422 #define RDC_SEMAPHORE_GATE61_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK)
87423 /*! @} */
87424 
87425 /*! @name GATE62 - Gate Register */
87426 /*! @{ */
87427 
87428 #define RDC_SEMAPHORE_GATE62_GTFSM_MASK          (0xFU)
87429 #define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT         (0U)
87430 /*! GTFSM - Gate Finite State Machine.
87431  *  0b0000..The gate is unlocked (free).
87432  *  0b0001..The gate has been locked by processor with master_index = 0.
87433  *  0b0010..The gate has been locked by processor with master_index = 1.
87434  *  0b0011..The gate has been locked by processor with master_index = 2.
87435  *  0b0100..The gate has been locked by processor with master_index = 3.
87436  *  0b0101..The gate has been locked by processor with master_index = 4.
87437  *  0b0110..The gate has been locked by processor with master_index = 5.
87438  *  0b0111..The gate has been locked by processor with master_index = 6.
87439  *  0b1000..The gate has been locked by processor with master_index = 7.
87440  *  0b1001..The gate has been locked by processor with master_index = 8.
87441  *  0b1010..The gate has been locked by processor with master_index = 9.
87442  *  0b1011..The gate has been locked by processor with master_index = 10.
87443  *  0b1100..The gate has been locked by processor with master_index = 11.
87444  *  0b1101..The gate has been locked by processor with master_index = 12.
87445  *  0b1110..The gate has been locked by processor with master_index = 13.
87446  *  0b1111..The gate has been locked by processor with master_index = 14.
87447  */
87448 #define RDC_SEMAPHORE_GATE62_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK)
87449 
87450 #define RDC_SEMAPHORE_GATE62_LDOM_MASK           (0x30U)
87451 #define RDC_SEMAPHORE_GATE62_LDOM_SHIFT          (4U)
87452 /*! LDOM
87453  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87454  *  0b01..The gate has been locked by domain 1.
87455  *  0b10..The gate has been locked by domain 2.
87456  *  0b11..The gate has been locked by domain 3.
87457  */
87458 #define RDC_SEMAPHORE_GATE62_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK)
87459 /*! @} */
87460 
87461 /*! @name GATE63 - Gate Register */
87462 /*! @{ */
87463 
87464 #define RDC_SEMAPHORE_GATE63_GTFSM_MASK          (0xFU)
87465 #define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT         (0U)
87466 /*! GTFSM - Gate Finite State Machine.
87467  *  0b0000..The gate is unlocked (free).
87468  *  0b0001..The gate has been locked by processor with master_index = 0.
87469  *  0b0010..The gate has been locked by processor with master_index = 1.
87470  *  0b0011..The gate has been locked by processor with master_index = 2.
87471  *  0b0100..The gate has been locked by processor with master_index = 3.
87472  *  0b0101..The gate has been locked by processor with master_index = 4.
87473  *  0b0110..The gate has been locked by processor with master_index = 5.
87474  *  0b0111..The gate has been locked by processor with master_index = 6.
87475  *  0b1000..The gate has been locked by processor with master_index = 7.
87476  *  0b1001..The gate has been locked by processor with master_index = 8.
87477  *  0b1010..The gate has been locked by processor with master_index = 9.
87478  *  0b1011..The gate has been locked by processor with master_index = 10.
87479  *  0b1100..The gate has been locked by processor with master_index = 11.
87480  *  0b1101..The gate has been locked by processor with master_index = 12.
87481  *  0b1110..The gate has been locked by processor with master_index = 13.
87482  *  0b1111..The gate has been locked by processor with master_index = 14.
87483  */
87484 #define RDC_SEMAPHORE_GATE63_GTFSM(x)            (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK)
87485 
87486 #define RDC_SEMAPHORE_GATE63_LDOM_MASK           (0x30U)
87487 #define RDC_SEMAPHORE_GATE63_LDOM_SHIFT          (4U)
87488 /*! LDOM
87489  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
87490  *  0b01..The gate has been locked by domain 1.
87491  *  0b10..The gate has been locked by domain 2.
87492  *  0b11..The gate has been locked by domain 3.
87493  */
87494 #define RDC_SEMAPHORE_GATE63_LDOM(x)             (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK)
87495 /*! @} */
87496 
87497 /*! @name RSTGT_R - Reset Gate Read */
87498 /*! @{ */
87499 
87500 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK        (0xFU)
87501 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT       (0U)
87502 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
87503 
87504 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK        (0x30U)
87505 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT       (4U)
87506 /*! RSTGSM
87507  *  0b00..Idle, waiting for the first data pattern write.
87508  *  0b01..Waiting for the second data pattern write.
87509  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
87510  *        this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
87511  *        for only one clock cycle. Software will never be able to observe this state.
87512  *  0b11..This state encoding is never used and therefore reserved.
87513  */
87514 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
87515 
87516 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK        (0xFF00U)
87517 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT       (8U)
87518 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
87519 /*! @} */
87520 
87521 /*! @name RSTGT_W - Reset Gate Write */
87522 /*! @{ */
87523 
87524 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK        (0xFFU)
87525 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT       (0U)
87526 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
87527 
87528 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK        (0xFF00U)
87529 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT       (8U)
87530 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
87531 /*! @} */
87532 
87533 
87534 /*!
87535  * @}
87536  */ /* end of group RDC_SEMAPHORE_Register_Masks */
87537 
87538 
87539 /* RDC_SEMAPHORE - Peripheral instance base addresses */
87540 /** Peripheral RDC_SEMAPHORE1 base address */
87541 #define RDC_SEMAPHORE1_BASE                      (0x303B0000u)
87542 /** Peripheral RDC_SEMAPHORE1 base pointer */
87543 #define RDC_SEMAPHORE1                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
87544 /** Peripheral RDC_SEMAPHORE2 base address */
87545 #define RDC_SEMAPHORE2_BASE                      (0x303C0000u)
87546 /** Peripheral RDC_SEMAPHORE2 base pointer */
87547 #define RDC_SEMAPHORE2                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
87548 /** Array initializer of RDC_SEMAPHORE peripheral base addresses */
87549 #define RDC_SEMAPHORE_BASE_ADDRS                 { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
87550 /** Array initializer of RDC_SEMAPHORE peripheral base pointers */
87551 #define RDC_SEMAPHORE_BASE_PTRS                  { (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
87552 
87553 /*!
87554  * @}
87555  */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
87556 
87557 
87558 /* ----------------------------------------------------------------------------
87559    -- SDMAARM Peripheral Access Layer
87560    ---------------------------------------------------------------------------- */
87561 
87562 /*!
87563  * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer
87564  * @{
87565  */
87566 
87567 /** SDMAARM - Register Layout Typedef */
87568 typedef struct {
87569   __IO uint32_t MC0PTR;                            /**< Arm platform Channel 0 Pointer, offset: 0x0 */
87570   __IO uint32_t INTR;                              /**< Channel Interrupts, offset: 0x4 */
87571   __IO uint32_t STOP_STAT;                         /**< Channel Stop/Channel Status, offset: 0x8 */
87572   __IO uint32_t HSTART;                            /**< Channel Start, offset: 0xC */
87573   __IO uint32_t EVTOVR;                            /**< Channel Event Override, offset: 0x10 */
87574   __IO uint32_t DSPOVR;                            /**< Channel BP Override, offset: 0x14 */
87575   __IO uint32_t HOSTOVR;                           /**< Channel Arm platform Override, offset: 0x18 */
87576   __IO uint32_t EVTPEND;                           /**< Channel Event Pending, offset: 0x1C */
87577        uint8_t RESERVED_0[4];
87578   __I  uint32_t RESET;                             /**< Reset Register, offset: 0x24 */
87579   __I  uint32_t EVTERR;                            /**< DMA Request Error Register, offset: 0x28 */
87580   __IO uint32_t INTRMASK;                          /**< Channel Arm platform Interrupt Mask, offset: 0x2C */
87581   __I  uint32_t PSW;                               /**< Schedule Status, offset: 0x30 */
87582   __I  uint32_t EVTERRDBG;                         /**< DMA Request Error Register, offset: 0x34 */
87583   __IO uint32_t CONFIG;                            /**< Configuration Register, offset: 0x38 */
87584   __IO uint32_t SDMA_LOCK;                         /**< SDMA LOCK, offset: 0x3C */
87585   __IO uint32_t ONCE_ENB;                          /**< OnCE Enable, offset: 0x40 */
87586   __IO uint32_t ONCE_DATA;                         /**< OnCE Data Register, offset: 0x44 */
87587   __IO uint32_t ONCE_INSTR;                        /**< OnCE Instruction Register, offset: 0x48 */
87588   __I  uint32_t ONCE_STAT;                         /**< OnCE Status Register, offset: 0x4C */
87589   __IO uint32_t ONCE_CMD;                          /**< OnCE Command Register, offset: 0x50 */
87590        uint8_t RESERVED_1[4];
87591   __IO uint32_t ILLINSTADDR;                       /**< Illegal Instruction Trap Address, offset: 0x58 */
87592   __IO uint32_t CHN0ADDR;                          /**< Channel 0 Boot Address, offset: 0x5C */
87593   __I  uint32_t EVT_MIRROR;                        /**< DMA Requests, offset: 0x60 */
87594   __I  uint32_t EVT_MIRROR2;                       /**< DMA Requests 2, offset: 0x64 */
87595        uint8_t RESERVED_2[8];
87596   __IO uint32_t XTRIG_CONF1;                       /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */
87597   __IO uint32_t XTRIG_CONF2;                       /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */
87598        uint8_t RESERVED_3[136];
87599   __IO uint32_t SDMA_CHNPRI[32];                   /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */
87600        uint8_t RESERVED_4[128];
87601   __IO uint32_t CHNENBL[48];                       /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */
87602        uint8_t RESERVED_5[3392];
87603   __IO uint32_t DONE0_CONFIG;                      /**< SDMA DONE0 Configuration, offset: 0x1000 */
87604   __IO uint32_t DONE1_CONFIG;                      /**< SDMA DONE1 Configuration, offset: 0x1004 */
87605 } SDMAARM_Type;
87606 
87607 /* ----------------------------------------------------------------------------
87608    -- SDMAARM Register Masks
87609    ---------------------------------------------------------------------------- */
87610 
87611 /*!
87612  * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks
87613  * @{
87614  */
87615 
87616 /*! @name MC0PTR - Arm platform Channel 0 Pointer */
87617 /*! @{ */
87618 
87619 #define SDMAARM_MC0PTR_MC0PTR_MASK               (0xFFFFFFFFU)
87620 #define SDMAARM_MC0PTR_MC0PTR_SHIFT              (0U)
87621 #define SDMAARM_MC0PTR_MC0PTR(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK)
87622 /*! @} */
87623 
87624 /*! @name INTR - Channel Interrupts */
87625 /*! @{ */
87626 
87627 #define SDMAARM_INTR_HI_MASK                     (0xFFFFFFFFU)
87628 #define SDMAARM_INTR_HI_SHIFT                    (0U)
87629 #define SDMAARM_INTR_HI(x)                       (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK)
87630 /*! @} */
87631 
87632 /*! @name STOP_STAT - Channel Stop/Channel Status */
87633 /*! @{ */
87634 
87635 #define SDMAARM_STOP_STAT_HE_MASK                (0xFFFFFFFFU)
87636 #define SDMAARM_STOP_STAT_HE_SHIFT               (0U)
87637 #define SDMAARM_STOP_STAT_HE(x)                  (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK)
87638 /*! @} */
87639 
87640 /*! @name HSTART - Channel Start */
87641 /*! @{ */
87642 
87643 #define SDMAARM_HSTART_HSTART_HE_MASK            (0xFFFFFFFFU)
87644 #define SDMAARM_HSTART_HSTART_HE_SHIFT           (0U)
87645 #define SDMAARM_HSTART_HSTART_HE(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK)
87646 /*! @} */
87647 
87648 /*! @name EVTOVR - Channel Event Override */
87649 /*! @{ */
87650 
87651 #define SDMAARM_EVTOVR_EO_MASK                   (0xFFFFFFFFU)
87652 #define SDMAARM_EVTOVR_EO_SHIFT                  (0U)
87653 #define SDMAARM_EVTOVR_EO(x)                     (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK)
87654 /*! @} */
87655 
87656 /*! @name DSPOVR - Channel BP Override */
87657 /*! @{ */
87658 
87659 #define SDMAARM_DSPOVR_DO_MASK                   (0xFFFFFFFFU)
87660 #define SDMAARM_DSPOVR_DO_SHIFT                  (0U)
87661 /*! DO
87662  *  0b00000000000000000000000000000000..- Reserved
87663  *  0b00000000000000000000000000000001..- Reset value.
87664  */
87665 #define SDMAARM_DSPOVR_DO(x)                     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK)
87666 /*! @} */
87667 
87668 /*! @name HOSTOVR - Channel Arm platform Override */
87669 /*! @{ */
87670 
87671 #define SDMAARM_HOSTOVR_HO_MASK                  (0xFFFFFFFFU)
87672 #define SDMAARM_HOSTOVR_HO_SHIFT                 (0U)
87673 #define SDMAARM_HOSTOVR_HO(x)                    (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK)
87674 /*! @} */
87675 
87676 /*! @name EVTPEND - Channel Event Pending */
87677 /*! @{ */
87678 
87679 #define SDMAARM_EVTPEND_EP_MASK                  (0xFFFFFFFFU)
87680 #define SDMAARM_EVTPEND_EP_SHIFT                 (0U)
87681 #define SDMAARM_EVTPEND_EP(x)                    (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK)
87682 /*! @} */
87683 
87684 /*! @name RESET - Reset Register */
87685 /*! @{ */
87686 
87687 #define SDMAARM_RESET_RESET_MASK                 (0x1U)
87688 #define SDMAARM_RESET_RESET_SHIFT                (0U)
87689 #define SDMAARM_RESET_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK)
87690 
87691 #define SDMAARM_RESET_RESCHED_MASK               (0x2U)
87692 #define SDMAARM_RESET_RESCHED_SHIFT              (1U)
87693 #define SDMAARM_RESET_RESCHED(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK)
87694 /*! @} */
87695 
87696 /*! @name EVTERR - DMA Request Error Register */
87697 /*! @{ */
87698 
87699 #define SDMAARM_EVTERR_CHNERR_MASK               (0xFFFFFFFFU)
87700 #define SDMAARM_EVTERR_CHNERR_SHIFT              (0U)
87701 #define SDMAARM_EVTERR_CHNERR(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK)
87702 /*! @} */
87703 
87704 /*! @name INTRMASK - Channel Arm platform Interrupt Mask */
87705 /*! @{ */
87706 
87707 #define SDMAARM_INTRMASK_HIMASK_MASK             (0xFFFFFFFFU)
87708 #define SDMAARM_INTRMASK_HIMASK_SHIFT            (0U)
87709 #define SDMAARM_INTRMASK_HIMASK(x)               (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK)
87710 /*! @} */
87711 
87712 /*! @name PSW - Schedule Status */
87713 /*! @{ */
87714 
87715 #define SDMAARM_PSW_CCR_MASK                     (0xFU)
87716 #define SDMAARM_PSW_CCR_SHIFT                    (0U)
87717 #define SDMAARM_PSW_CCR(x)                       (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK)
87718 
87719 #define SDMAARM_PSW_CCP_MASK                     (0xF0U)
87720 #define SDMAARM_PSW_CCP_SHIFT                    (4U)
87721 /*! CCP
87722  *  0b0000..No running channel
87723  *  0b0001..Active channel priority
87724  */
87725 #define SDMAARM_PSW_CCP(x)                       (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK)
87726 
87727 #define SDMAARM_PSW_NCR_MASK                     (0x1F00U)
87728 #define SDMAARM_PSW_NCR_SHIFT                    (8U)
87729 #define SDMAARM_PSW_NCR(x)                       (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK)
87730 
87731 #define SDMAARM_PSW_NCP_MASK                     (0xE000U)
87732 #define SDMAARM_PSW_NCP_SHIFT                    (13U)
87733 /*! NCP
87734  *  0b000..No running channel
87735  *  0b001..Active channel priority
87736  */
87737 #define SDMAARM_PSW_NCP(x)                       (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK)
87738 /*! @} */
87739 
87740 /*! @name EVTERRDBG - DMA Request Error Register */
87741 /*! @{ */
87742 
87743 #define SDMAARM_EVTERRDBG_CHNERR_MASK            (0xFFFFFFFFU)
87744 #define SDMAARM_EVTERRDBG_CHNERR_SHIFT           (0U)
87745 #define SDMAARM_EVTERRDBG_CHNERR(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK)
87746 /*! @} */
87747 
87748 /*! @name CONFIG - Configuration Register */
87749 /*! @{ */
87750 
87751 #define SDMAARM_CONFIG_CSM_MASK                  (0x3U)
87752 #define SDMAARM_CONFIG_CSM_SHIFT                 (0U)
87753 /*! CSM
87754  *  0b00..static
87755  *  0b01..dynamic low power
87756  *  0b10..dynamic with no loop
87757  *  0b11..dynamic
87758  */
87759 #define SDMAARM_CONFIG_CSM(x)                    (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK)
87760 
87761 #define SDMAARM_CONFIG_ACR_MASK                  (0x10U)
87762 #define SDMAARM_CONFIG_ACR_SHIFT                 (4U)
87763 /*! ACR
87764  *  0b0..Arm platform DMA interface frequency equals twice core frequency
87765  *  0b1..Arm platform DMA interface frequency equals core frequency
87766  */
87767 #define SDMAARM_CONFIG_ACR(x)                    (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK)
87768 
87769 #define SDMAARM_CONFIG_RTDOBS_MASK               (0x800U)
87770 #define SDMAARM_CONFIG_RTDOBS_SHIFT              (11U)
87771 /*! RTDOBS
87772  *  0b0..RTD pins disabled
87773  *  0b1..RTD pins enabled
87774  */
87775 #define SDMAARM_CONFIG_RTDOBS(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK)
87776 
87777 #define SDMAARM_CONFIG_DSPDMA_MASK               (0x1000U)
87778 #define SDMAARM_CONFIG_DSPDMA_SHIFT              (12U)
87779 /*! DSPDMA
87780  *  0b0..- Reset Value
87781  *  0b1..- Reserved
87782  */
87783 #define SDMAARM_CONFIG_DSPDMA(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK)
87784 /*! @} */
87785 
87786 /*! @name SDMA_LOCK - SDMA LOCK */
87787 /*! @{ */
87788 
87789 #define SDMAARM_SDMA_LOCK_LOCK_MASK              (0x1U)
87790 #define SDMAARM_SDMA_LOCK_LOCK_SHIFT             (0U)
87791 /*! LOCK
87792  *  0b0..LOCK disengaged.
87793  *  0b1..LOCK enabled.
87794  */
87795 #define SDMAARM_SDMA_LOCK_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK)
87796 
87797 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK   (0x2U)
87798 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT  (1U)
87799 /*! SRESET_LOCK_CLR
87800  *  0b0..Software Reset does not clear the LOCK bit.
87801  *  0b1..Software Reset clears the LOCK bit.
87802  */
87803 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK)
87804 /*! @} */
87805 
87806 /*! @name ONCE_ENB - OnCE Enable */
87807 /*! @{ */
87808 
87809 #define SDMAARM_ONCE_ENB_ENB_MASK                (0x1U)
87810 #define SDMAARM_ONCE_ENB_ENB_SHIFT               (0U)
87811 #define SDMAARM_ONCE_ENB_ENB(x)                  (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK)
87812 /*! @} */
87813 
87814 /*! @name ONCE_DATA - OnCE Data Register */
87815 /*! @{ */
87816 
87817 #define SDMAARM_ONCE_DATA_DATA_MASK              (0xFFFFFFFFU)
87818 #define SDMAARM_ONCE_DATA_DATA_SHIFT             (0U)
87819 #define SDMAARM_ONCE_DATA_DATA(x)                (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK)
87820 /*! @} */
87821 
87822 /*! @name ONCE_INSTR - OnCE Instruction Register */
87823 /*! @{ */
87824 
87825 #define SDMAARM_ONCE_INSTR_INSTR_MASK            (0xFFFFU)
87826 #define SDMAARM_ONCE_INSTR_INSTR_SHIFT           (0U)
87827 #define SDMAARM_ONCE_INSTR_INSTR(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK)
87828 /*! @} */
87829 
87830 /*! @name ONCE_STAT - OnCE Status Register */
87831 /*! @{ */
87832 
87833 #define SDMAARM_ONCE_STAT_ECDR_MASK              (0x7U)
87834 #define SDMAARM_ONCE_STAT_ECDR_SHIFT             (0U)
87835 /*! ECDR
87836  *  0b000..1 matched addra_cond
87837  *  0b001..1 matched addrb_cond
87838  *  0b010..1 matched data_cond
87839  */
87840 #define SDMAARM_ONCE_STAT_ECDR(x)                (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK)
87841 
87842 #define SDMAARM_ONCE_STAT_MST_MASK               (0x80U)
87843 #define SDMAARM_ONCE_STAT_MST_SHIFT              (7U)
87844 /*! MST
87845  *  0b0..The JTAG interface controls the OnCE.
87846  *  0b1..The Arm platform peripheral interface controls the OnCE.
87847  */
87848 #define SDMAARM_ONCE_STAT_MST(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK)
87849 
87850 #define SDMAARM_ONCE_STAT_SWB_MASK               (0x100U)
87851 #define SDMAARM_ONCE_STAT_SWB_SHIFT              (8U)
87852 #define SDMAARM_ONCE_STAT_SWB(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK)
87853 
87854 #define SDMAARM_ONCE_STAT_ODR_MASK               (0x200U)
87855 #define SDMAARM_ONCE_STAT_ODR_SHIFT              (9U)
87856 #define SDMAARM_ONCE_STAT_ODR(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK)
87857 
87858 #define SDMAARM_ONCE_STAT_EDR_MASK               (0x400U)
87859 #define SDMAARM_ONCE_STAT_EDR_SHIFT              (10U)
87860 #define SDMAARM_ONCE_STAT_EDR(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK)
87861 
87862 #define SDMAARM_ONCE_STAT_RCV_MASK               (0x800U)
87863 #define SDMAARM_ONCE_STAT_RCV_SHIFT              (11U)
87864 #define SDMAARM_ONCE_STAT_RCV(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK)
87865 
87866 #define SDMAARM_ONCE_STAT_PST_MASK               (0xF000U)
87867 #define SDMAARM_ONCE_STAT_PST_SHIFT              (12U)
87868 /*! PST
87869  *  0b0000..Program
87870  *  0b0001..Data
87871  *  0b0010..Change of Flow
87872  *  0b0011..Change of Flow in Loop
87873  *  0b0100..Debug
87874  *  0b0101..Functional Unit
87875  *  0b0110..Sleep
87876  *  0b0111..Save
87877  *  0b1000..Program in Sleep
87878  *  0b1001..Data in Sleep
87879  *  0b0010..Change of Flow in Sleep
87880  *  0b0011..Change Flow in Loop in Sleep
87881  *  0b1100..Debug in Sleep
87882  *  0b1101..Functional Unit in Sleep
87883  *  0b1110..Sleep after Reset
87884  *  0b1111..Restore
87885  */
87886 #define SDMAARM_ONCE_STAT_PST(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK)
87887 /*! @} */
87888 
87889 /*! @name ONCE_CMD - OnCE Command Register */
87890 /*! @{ */
87891 
87892 #define SDMAARM_ONCE_CMD_CMD_MASK                (0xFU)
87893 #define SDMAARM_ONCE_CMD_CMD_SHIFT               (0U)
87894 /*! CMD
87895  *  0b0000..rstatus
87896  *  0b0001..dmov
87897  *  0b0010..exec_once
87898  *  0b0011..run_core
87899  *  0b0100..exec_core
87900  *  0b0101..debug_rqst
87901  *  0b0110..rbuffer
87902  */
87903 #define SDMAARM_ONCE_CMD_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK)
87904 /*! @} */
87905 
87906 /*! @name ILLINSTADDR - Illegal Instruction Trap Address */
87907 /*! @{ */
87908 
87909 #define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK     (0x3FFFU)
87910 #define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT    (0U)
87911 #define SDMAARM_ILLINSTADDR_ILLINSTADDR(x)       (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK)
87912 /*! @} */
87913 
87914 /*! @name CHN0ADDR - Channel 0 Boot Address */
87915 /*! @{ */
87916 
87917 #define SDMAARM_CHN0ADDR_CHN0ADDR_MASK           (0x3FFFU)
87918 #define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT          (0U)
87919 #define SDMAARM_CHN0ADDR_CHN0ADDR(x)             (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK)
87920 
87921 #define SDMAARM_CHN0ADDR_SMSZ_MASK               (0x4000U)
87922 #define SDMAARM_CHN0ADDR_SMSZ_SHIFT              (14U)
87923 /*! SMSZ
87924  *  0b0..24 words per context
87925  *  0b1..32 words per context
87926  */
87927 #define SDMAARM_CHN0ADDR_SMSZ(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK)
87928 /*! @} */
87929 
87930 /*! @name EVT_MIRROR - DMA Requests */
87931 /*! @{ */
87932 
87933 #define SDMAARM_EVT_MIRROR_EVENTS_MASK           (0xFFFFFFFFU)
87934 #define SDMAARM_EVT_MIRROR_EVENTS_SHIFT          (0U)
87935 /*! EVENTS
87936  *  0b00000000000000000000000000000000..DMA request event not pending
87937  *  0b00000000000000000000000000000001..DMA request event pending
87938  */
87939 #define SDMAARM_EVT_MIRROR_EVENTS(x)             (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK)
87940 /*! @} */
87941 
87942 /*! @name EVT_MIRROR2 - DMA Requests 2 */
87943 /*! @{ */
87944 
87945 #define SDMAARM_EVT_MIRROR2_EVENTS_MASK          (0xFFFFU)
87946 #define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT         (0U)
87947 /*! EVENTS
87948  *  0b0000000000000000..- DMA request event not pending
87949  */
87950 #define SDMAARM_EVT_MIRROR2_EVENTS(x)            (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK)
87951 /*! @} */
87952 
87953 /*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */
87954 /*! @{ */
87955 
87956 #define SDMAARM_XTRIG_CONF1_NUM0_MASK            (0x3FU)
87957 #define SDMAARM_XTRIG_CONF1_NUM0_SHIFT           (0U)
87958 #define SDMAARM_XTRIG_CONF1_NUM0(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK)
87959 
87960 #define SDMAARM_XTRIG_CONF1_CNF0_MASK            (0x40U)
87961 #define SDMAARM_XTRIG_CONF1_CNF0_SHIFT           (6U)
87962 /*! CNF0
87963  *  0b0..channel
87964  *  0b1..DMA request
87965  */
87966 #define SDMAARM_XTRIG_CONF1_CNF0(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK)
87967 
87968 #define SDMAARM_XTRIG_CONF1_NUM1_MASK            (0x3F00U)
87969 #define SDMAARM_XTRIG_CONF1_NUM1_SHIFT           (8U)
87970 #define SDMAARM_XTRIG_CONF1_NUM1(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK)
87971 
87972 #define SDMAARM_XTRIG_CONF1_CNF1_MASK            (0x4000U)
87973 #define SDMAARM_XTRIG_CONF1_CNF1_SHIFT           (14U)
87974 /*! CNF1
87975  *  0b0..channel
87976  *  0b1..DMA request
87977  */
87978 #define SDMAARM_XTRIG_CONF1_CNF1(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK)
87979 
87980 #define SDMAARM_XTRIG_CONF1_NUM2_MASK            (0x3F0000U)
87981 #define SDMAARM_XTRIG_CONF1_NUM2_SHIFT           (16U)
87982 #define SDMAARM_XTRIG_CONF1_NUM2(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK)
87983 
87984 #define SDMAARM_XTRIG_CONF1_CNF2_MASK            (0x400000U)
87985 #define SDMAARM_XTRIG_CONF1_CNF2_SHIFT           (22U)
87986 /*! CNF2
87987  *  0b0..channel
87988  *  0b1..DMA request
87989  */
87990 #define SDMAARM_XTRIG_CONF1_CNF2(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK)
87991 
87992 #define SDMAARM_XTRIG_CONF1_NUM3_MASK            (0x3F000000U)
87993 #define SDMAARM_XTRIG_CONF1_NUM3_SHIFT           (24U)
87994 #define SDMAARM_XTRIG_CONF1_NUM3(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK)
87995 
87996 #define SDMAARM_XTRIG_CONF1_CNF3_MASK            (0x40000000U)
87997 #define SDMAARM_XTRIG_CONF1_CNF3_SHIFT           (30U)
87998 /*! CNF3
87999  *  0b0..channel
88000  *  0b1..DMA request
88001  */
88002 #define SDMAARM_XTRIG_CONF1_CNF3(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK)
88003 /*! @} */
88004 
88005 /*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */
88006 /*! @{ */
88007 
88008 #define SDMAARM_XTRIG_CONF2_NUM4_MASK            (0x3FU)
88009 #define SDMAARM_XTRIG_CONF2_NUM4_SHIFT           (0U)
88010 #define SDMAARM_XTRIG_CONF2_NUM4(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK)
88011 
88012 #define SDMAARM_XTRIG_CONF2_CNF4_MASK            (0x40U)
88013 #define SDMAARM_XTRIG_CONF2_CNF4_SHIFT           (6U)
88014 /*! CNF4
88015  *  0b0..channel
88016  *  0b1..DMA request
88017  */
88018 #define SDMAARM_XTRIG_CONF2_CNF4(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK)
88019 
88020 #define SDMAARM_XTRIG_CONF2_NUM5_MASK            (0x3F00U)
88021 #define SDMAARM_XTRIG_CONF2_NUM5_SHIFT           (8U)
88022 #define SDMAARM_XTRIG_CONF2_NUM5(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK)
88023 
88024 #define SDMAARM_XTRIG_CONF2_CNF5_MASK            (0x4000U)
88025 #define SDMAARM_XTRIG_CONF2_CNF5_SHIFT           (14U)
88026 /*! CNF5
88027  *  0b0..channel
88028  *  0b1..DMA request
88029  */
88030 #define SDMAARM_XTRIG_CONF2_CNF5(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK)
88031 
88032 #define SDMAARM_XTRIG_CONF2_NUM6_MASK            (0x3F0000U)
88033 #define SDMAARM_XTRIG_CONF2_NUM6_SHIFT           (16U)
88034 #define SDMAARM_XTRIG_CONF2_NUM6(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK)
88035 
88036 #define SDMAARM_XTRIG_CONF2_CNF6_MASK            (0x400000U)
88037 #define SDMAARM_XTRIG_CONF2_CNF6_SHIFT           (22U)
88038 /*! CNF6
88039  *  0b0..channel
88040  *  0b1..DMA request
88041  */
88042 #define SDMAARM_XTRIG_CONF2_CNF6(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK)
88043 
88044 #define SDMAARM_XTRIG_CONF2_NUM7_MASK            (0x3F000000U)
88045 #define SDMAARM_XTRIG_CONF2_NUM7_SHIFT           (24U)
88046 #define SDMAARM_XTRIG_CONF2_NUM7(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK)
88047 
88048 #define SDMAARM_XTRIG_CONF2_CNF7_MASK            (0x40000000U)
88049 #define SDMAARM_XTRIG_CONF2_CNF7_SHIFT           (30U)
88050 /*! CNF7
88051  *  0b0..channel
88052  *  0b1..DMA request
88053  */
88054 #define SDMAARM_XTRIG_CONF2_CNF7(x)              (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK)
88055 /*! @} */
88056 
88057 /*! @name SDMA_CHNPRI - Channel Priority Registers */
88058 /*! @{ */
88059 
88060 #define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK         (0x7U)
88061 #define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT        (0U)
88062 #define SDMAARM_SDMA_CHNPRI_CHNPRIn(x)           (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK)
88063 /*! @} */
88064 
88065 /* The count of SDMAARM_SDMA_CHNPRI */
88066 #define SDMAARM_SDMA_CHNPRI_COUNT                (32U)
88067 
88068 /*! @name CHNENBL - Channel Enable RAM */
88069 /*! @{ */
88070 
88071 #define SDMAARM_CHNENBL_ENBLn_MASK               (0xFFFFFFFFU)
88072 #define SDMAARM_CHNENBL_ENBLn_SHIFT              (0U)
88073 #define SDMAARM_CHNENBL_ENBLn(x)                 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK)
88074 /*! @} */
88075 
88076 /* The count of SDMAARM_CHNENBL */
88077 #define SDMAARM_CHNENBL_COUNT                    (48U)
88078 
88079 /*! @name DONE0_CONFIG - SDMA DONE0 Configuration */
88080 /*! @{ */
88081 
88082 #define SDMAARM_DONE0_CONFIG_CH_SEL0_MASK        (0x1FU)
88083 #define SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT       (0U)
88084 #define SDMAARM_DONE0_CONFIG_CH_SEL0(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL0_MASK)
88085 
88086 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK   (0x40U)
88087 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT  (6U)
88088 /*! SW_DONE_DIS0
88089  *  0b0..Enable
88090  *  0b1..Disable
88091  */
88092 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK)
88093 
88094 #define SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK      (0x80U)
88095 #define SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT     (7U)
88096 /*! DONE_SEL0
88097  *  0b0..HW
88098  *  0b1..SW
88099  */
88100 #define SDMAARM_DONE0_CONFIG_DONE_SEL0(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK)
88101 
88102 #define SDMAARM_DONE0_CONFIG_CH_SEL1_MASK        (0x1F00U)
88103 #define SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT       (8U)
88104 #define SDMAARM_DONE0_CONFIG_CH_SEL1(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL1_MASK)
88105 
88106 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK   (0x4000U)
88107 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT  (14U)
88108 /*! SW_DONE_DIS1
88109  *  0b0..Enable
88110  *  0b1..Disable
88111  */
88112 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK)
88113 
88114 #define SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK      (0x8000U)
88115 #define SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT     (15U)
88116 /*! DONE_SEL1
88117  *  0b0..HW
88118  *  0b1..SW
88119  */
88120 #define SDMAARM_DONE0_CONFIG_DONE_SEL1(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK)
88121 
88122 #define SDMAARM_DONE0_CONFIG_CH_SEL2_MASK        (0x1F0000U)
88123 #define SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT       (16U)
88124 #define SDMAARM_DONE0_CONFIG_CH_SEL2(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL2_MASK)
88125 
88126 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK   (0x400000U)
88127 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT  (22U)
88128 /*! SW_DONE_DIS2
88129  *  0b0..Enable
88130  *  0b1..Disable
88131  */
88132 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK)
88133 
88134 #define SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK      (0x800000U)
88135 #define SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT     (23U)
88136 /*! DONE_SEL2
88137  *  0b0..HW
88138  *  0b1..SW
88139  */
88140 #define SDMAARM_DONE0_CONFIG_DONE_SEL2(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK)
88141 
88142 #define SDMAARM_DONE0_CONFIG_CH_SEL3_MASK        (0x1F000000U)
88143 #define SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT       (24U)
88144 #define SDMAARM_DONE0_CONFIG_CH_SEL3(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL3_MASK)
88145 
88146 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK   (0x40000000U)
88147 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT  (30U)
88148 /*! SW_DONE_DIS3
88149  *  0b0..Enable
88150  *  0b1..Disable
88151  */
88152 #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK)
88153 
88154 #define SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK      (0x80000000U)
88155 #define SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT     (31U)
88156 /*! DONE_SEL3
88157  *  0b0..HW
88158  *  0b1..SW
88159  */
88160 #define SDMAARM_DONE0_CONFIG_DONE_SEL3(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK)
88161 /*! @} */
88162 
88163 /*! @name DONE1_CONFIG - SDMA DONE1 Configuration */
88164 /*! @{ */
88165 
88166 #define SDMAARM_DONE1_CONFIG_CH_SEL4_MASK        (0x1FU)
88167 #define SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT       (0U)
88168 #define SDMAARM_DONE1_CONFIG_CH_SEL4(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL4_MASK)
88169 
88170 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK   (0x40U)
88171 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT  (6U)
88172 /*! SW_DONE_DIS4
88173  *  0b0..Enable
88174  *  0b1..Disable
88175  */
88176 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK)
88177 
88178 #define SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK      (0x80U)
88179 #define SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT     (7U)
88180 /*! DONE_SEL4
88181  *  0b0..HW
88182  *  0b1..SW
88183  */
88184 #define SDMAARM_DONE1_CONFIG_DONE_SEL4(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK)
88185 
88186 #define SDMAARM_DONE1_CONFIG_CH_SEL5_MASK        (0x1F00U)
88187 #define SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT       (8U)
88188 #define SDMAARM_DONE1_CONFIG_CH_SEL5(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL5_MASK)
88189 
88190 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK   (0x4000U)
88191 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT  (14U)
88192 /*! SW_DONE_DIS5
88193  *  0b0..Enable
88194  *  0b1..Disable
88195  */
88196 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK)
88197 
88198 #define SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK      (0x8000U)
88199 #define SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT     (15U)
88200 /*! DONE_SEL5
88201  *  0b0..HW
88202  *  0b1..SW
88203  */
88204 #define SDMAARM_DONE1_CONFIG_DONE_SEL5(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK)
88205 
88206 #define SDMAARM_DONE1_CONFIG_CH_SEL6_MASK        (0x1F0000U)
88207 #define SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT       (16U)
88208 #define SDMAARM_DONE1_CONFIG_CH_SEL6(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL6_MASK)
88209 
88210 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK   (0x400000U)
88211 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT  (22U)
88212 /*! SW_DONE_DIS6
88213  *  0b0..Enable
88214  *  0b1..Disable
88215  */
88216 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK)
88217 
88218 #define SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK      (0x800000U)
88219 #define SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT     (23U)
88220 /*! DONE_SEL6
88221  *  0b0..HW
88222  *  0b1..SW
88223  */
88224 #define SDMAARM_DONE1_CONFIG_DONE_SEL6(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK)
88225 
88226 #define SDMAARM_DONE1_CONFIG_CH_SEL7_MASK        (0x1F000000U)
88227 #define SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT       (24U)
88228 #define SDMAARM_DONE1_CONFIG_CH_SEL7(x)          (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL7_MASK)
88229 
88230 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK   (0x40000000U)
88231 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT  (30U)
88232 /*! SW_DONE_DIS7
88233  *  0b0..Enable
88234  *  0b1..Disable
88235  */
88236 #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7(x)     (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK)
88237 
88238 #define SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK      (0x80000000U)
88239 #define SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT     (31U)
88240 /*! DONE_SEL7
88241  *  0b0..HW
88242  *  0b1..SW
88243  */
88244 #define SDMAARM_DONE1_CONFIG_DONE_SEL7(x)        (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK)
88245 /*! @} */
88246 
88247 
88248 /*!
88249  * @}
88250  */ /* end of group SDMAARM_Register_Masks */
88251 
88252 
88253 /* SDMAARM - Peripheral instance base addresses */
88254 /** Peripheral SDMAARM1 base address */
88255 #define SDMAARM1_BASE                            (0x30BD0000u)
88256 /** Peripheral SDMAARM1 base pointer */
88257 #define SDMAARM1                                 ((SDMAARM_Type *)SDMAARM1_BASE)
88258 /** Peripheral SDMAARM2 base address */
88259 #define SDMAARM2_BASE                            (0x30E10000u)
88260 /** Peripheral SDMAARM2 base pointer */
88261 #define SDMAARM2                                 ((SDMAARM_Type *)SDMAARM2_BASE)
88262 /** Peripheral SDMAARM3 base address */
88263 #define SDMAARM3_BASE                            (0x30E00000u)
88264 /** Peripheral SDMAARM3 base pointer */
88265 #define SDMAARM3                                 ((SDMAARM_Type *)SDMAARM3_BASE)
88266 /** Array initializer of SDMAARM peripheral base addresses */
88267 #define SDMAARM_BASE_ADDRS                       { SDMAARM1_BASE, SDMAARM2_BASE, SDMAARM3_BASE }
88268 /** Array initializer of SDMAARM peripheral base pointers */
88269 #define SDMAARM_BASE_PTRS                        { SDMAARM1, SDMAARM2, SDMAARM3 }
88270 /** Interrupt vectors for the SDMAARM peripheral type */
88271 #define SDMAARM_IRQS                             { SDMA1_IRQn, SDMA2_IRQn, SDMA3_IRQn }
88272 
88273 /*!
88274  * @}
88275  */ /* end of group SDMAARM_Peripheral_Access_Layer */
88276 
88277 
88278 /* ----------------------------------------------------------------------------
88279    -- SEMA4 Peripheral Access Layer
88280    ---------------------------------------------------------------------------- */
88281 
88282 /*!
88283  * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
88284  * @{
88285  */
88286 
88287 /** SEMA4 - Register Layout Typedef */
88288 typedef struct {
88289   __IO uint8_t Gate00;                             /**< Semaphores Gate 0 Register, offset: 0x0 */
88290   __IO uint8_t Gate01;                             /**< Semaphores Gate 1 Register, offset: 0x1 */
88291   __IO uint8_t Gate02;                             /**< Semaphores Gate 2 Register, offset: 0x2 */
88292   __IO uint8_t Gate03;                             /**< Semaphores Gate 3 Register, offset: 0x3 */
88293   __IO uint8_t Gate04;                             /**< Semaphores Gate 4 Register, offset: 0x4 */
88294   __IO uint8_t Gate05;                             /**< Semaphores Gate 5 Register, offset: 0x5 */
88295   __IO uint8_t Gate06;                             /**< Semaphores Gate 6 Register, offset: 0x6 */
88296   __IO uint8_t Gate07;                             /**< Semaphores Gate 7 Register, offset: 0x7 */
88297   __IO uint8_t Gate08;                             /**< Semaphores Gate 8 Register, offset: 0x8 */
88298   __IO uint8_t Gate09;                             /**< Semaphores Gate 9 Register, offset: 0x9 */
88299   __IO uint8_t Gate10;                             /**< Semaphores Gate 10 Register, offset: 0xA */
88300   __IO uint8_t Gate11;                             /**< Semaphores Gate 11 Register, offset: 0xB */
88301   __IO uint8_t Gate12;                             /**< Semaphores Gate 12 Register, offset: 0xC */
88302   __IO uint8_t Gate13;                             /**< Semaphores Gate 13 Register, offset: 0xD */
88303   __IO uint8_t Gate14;                             /**< Semaphores Gate 14 Register, offset: 0xE */
88304   __IO uint8_t Gate15;                             /**< Semaphores Gate 15 Register, offset: 0xF */
88305        uint8_t RESERVED_0[48];
88306   struct {                                         /* offset: 0x40, array step: 0x8 */
88307     __IO uint16_t CPINE;                             /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
88308          uint8_t RESERVED_0[6];
88309   } CPINE[2];
88310        uint8_t RESERVED_1[48];
88311   struct {                                         /* offset: 0x80, array step: 0x8 */
88312     __I  uint16_t CPNTF;                             /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
88313          uint8_t RESERVED_0[6];
88314   } CPNTF[2];
88315        uint8_t RESERVED_2[112];
88316   __IO uint16_t RSTGT;                             /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
88317        uint8_t RESERVED_3[2];
88318   __IO uint16_t RSTNTF;                            /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
88319 } SEMA4_Type;
88320 
88321 /* ----------------------------------------------------------------------------
88322    -- SEMA4 Register Masks
88323    ---------------------------------------------------------------------------- */
88324 
88325 /*!
88326  * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
88327  * @{
88328  */
88329 
88330 /*! @name Gate00 - Semaphores Gate 0 Register */
88331 /*! @{ */
88332 
88333 #define SEMA4_Gate00_GTFSM_MASK                  (0x3U)
88334 #define SEMA4_Gate00_GTFSM_SHIFT                 (0U)
88335 /*! GTFSM - Gate Finite State Machine.
88336  *  0b00..The gate is unlocked (free).
88337  *  0b01..The gate has been locked by processor 0.
88338  *  0b10..The gate has been locked by processor 1.
88339  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88340  *        operation" and do not affect the gate state machine.
88341  */
88342 #define SEMA4_Gate00_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK)
88343 /*! @} */
88344 
88345 /*! @name Gate01 - Semaphores Gate 1 Register */
88346 /*! @{ */
88347 
88348 #define SEMA4_Gate01_GTFSM_MASK                  (0x3U)
88349 #define SEMA4_Gate01_GTFSM_SHIFT                 (0U)
88350 /*! GTFSM - Gate Finite State Machine.
88351  *  0b00..The gate is unlocked (free).
88352  *  0b01..The gate has been locked by processor 0.
88353  *  0b10..The gate has been locked by processor 1.
88354  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88355  *        operation" and do not affect the gate state machine.
88356  */
88357 #define SEMA4_Gate01_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK)
88358 /*! @} */
88359 
88360 /*! @name Gate02 - Semaphores Gate 2 Register */
88361 /*! @{ */
88362 
88363 #define SEMA4_Gate02_GTFSM_MASK                  (0x3U)
88364 #define SEMA4_Gate02_GTFSM_SHIFT                 (0U)
88365 /*! GTFSM - Gate Finite State Machine.
88366  *  0b00..The gate is unlocked (free).
88367  *  0b01..The gate has been locked by processor 0.
88368  *  0b10..The gate has been locked by processor 1.
88369  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88370  *        operation" and do not affect the gate state machine.
88371  */
88372 #define SEMA4_Gate02_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK)
88373 /*! @} */
88374 
88375 /*! @name Gate03 - Semaphores Gate 3 Register */
88376 /*! @{ */
88377 
88378 #define SEMA4_Gate03_GTFSM_MASK                  (0x3U)
88379 #define SEMA4_Gate03_GTFSM_SHIFT                 (0U)
88380 /*! GTFSM - Gate Finite State Machine.
88381  *  0b00..The gate is unlocked (free).
88382  *  0b01..The gate has been locked by processor 0.
88383  *  0b10..The gate has been locked by processor 1.
88384  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88385  *        operation" and do not affect the gate state machine.
88386  */
88387 #define SEMA4_Gate03_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK)
88388 /*! @} */
88389 
88390 /*! @name Gate04 - Semaphores Gate 4 Register */
88391 /*! @{ */
88392 
88393 #define SEMA4_Gate04_GTFSM_MASK                  (0x3U)
88394 #define SEMA4_Gate04_GTFSM_SHIFT                 (0U)
88395 /*! GTFSM - Gate Finite State Machine.
88396  *  0b00..The gate is unlocked (free).
88397  *  0b01..The gate has been locked by processor 0.
88398  *  0b10..The gate has been locked by processor 1.
88399  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88400  *        operation" and do not affect the gate state machine.
88401  */
88402 #define SEMA4_Gate04_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK)
88403 /*! @} */
88404 
88405 /*! @name Gate05 - Semaphores Gate 5 Register */
88406 /*! @{ */
88407 
88408 #define SEMA4_Gate05_GTFSM_MASK                  (0x3U)
88409 #define SEMA4_Gate05_GTFSM_SHIFT                 (0U)
88410 /*! GTFSM - Gate Finite State Machine.
88411  *  0b00..The gate is unlocked (free).
88412  *  0b01..The gate has been locked by processor 0.
88413  *  0b10..The gate has been locked by processor 1.
88414  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88415  *        operation" and do not affect the gate state machine.
88416  */
88417 #define SEMA4_Gate05_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK)
88418 /*! @} */
88419 
88420 /*! @name Gate06 - Semaphores Gate 6 Register */
88421 /*! @{ */
88422 
88423 #define SEMA4_Gate06_GTFSM_MASK                  (0x3U)
88424 #define SEMA4_Gate06_GTFSM_SHIFT                 (0U)
88425 /*! GTFSM - Gate Finite State Machine.
88426  *  0b00..The gate is unlocked (free).
88427  *  0b01..The gate has been locked by processor 0.
88428  *  0b10..The gate has been locked by processor 1.
88429  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88430  *        operation" and do not affect the gate state machine.
88431  */
88432 #define SEMA4_Gate06_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK)
88433 /*! @} */
88434 
88435 /*! @name Gate07 - Semaphores Gate 7 Register */
88436 /*! @{ */
88437 
88438 #define SEMA4_Gate07_GTFSM_MASK                  (0x3U)
88439 #define SEMA4_Gate07_GTFSM_SHIFT                 (0U)
88440 /*! GTFSM - Gate Finite State Machine.
88441  *  0b00..The gate is unlocked (free).
88442  *  0b01..The gate has been locked by processor 0.
88443  *  0b10..The gate has been locked by processor 1.
88444  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88445  *        operation" and do not affect the gate state machine.
88446  */
88447 #define SEMA4_Gate07_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK)
88448 /*! @} */
88449 
88450 /*! @name Gate08 - Semaphores Gate 8 Register */
88451 /*! @{ */
88452 
88453 #define SEMA4_Gate08_GTFSM_MASK                  (0x3U)
88454 #define SEMA4_Gate08_GTFSM_SHIFT                 (0U)
88455 /*! GTFSM - Gate Finite State Machine.
88456  *  0b00..The gate is unlocked (free).
88457  *  0b01..The gate has been locked by processor 0.
88458  *  0b10..The gate has been locked by processor 1.
88459  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88460  *        operation" and do not affect the gate state machine.
88461  */
88462 #define SEMA4_Gate08_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK)
88463 /*! @} */
88464 
88465 /*! @name Gate09 - Semaphores Gate 9 Register */
88466 /*! @{ */
88467 
88468 #define SEMA4_Gate09_GTFSM_MASK                  (0x3U)
88469 #define SEMA4_Gate09_GTFSM_SHIFT                 (0U)
88470 /*! GTFSM - Gate Finite State Machine.
88471  *  0b00..The gate is unlocked (free).
88472  *  0b01..The gate has been locked by processor 0.
88473  *  0b10..The gate has been locked by processor 1.
88474  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88475  *        operation" and do not affect the gate state machine.
88476  */
88477 #define SEMA4_Gate09_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK)
88478 /*! @} */
88479 
88480 /*! @name Gate10 - Semaphores Gate 10 Register */
88481 /*! @{ */
88482 
88483 #define SEMA4_Gate10_GTFSM_MASK                  (0x3U)
88484 #define SEMA4_Gate10_GTFSM_SHIFT                 (0U)
88485 /*! GTFSM - Gate Finite State Machine.
88486  *  0b00..The gate is unlocked (free).
88487  *  0b01..The gate has been locked by processor 0.
88488  *  0b10..The gate has been locked by processor 1.
88489  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88490  *        operation" and do not affect the gate state machine.
88491  */
88492 #define SEMA4_Gate10_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK)
88493 /*! @} */
88494 
88495 /*! @name Gate11 - Semaphores Gate 11 Register */
88496 /*! @{ */
88497 
88498 #define SEMA4_Gate11_GTFSM_MASK                  (0x3U)
88499 #define SEMA4_Gate11_GTFSM_SHIFT                 (0U)
88500 /*! GTFSM - Gate Finite State Machine.
88501  *  0b00..The gate is unlocked (free).
88502  *  0b01..The gate has been locked by processor 0.
88503  *  0b10..The gate has been locked by processor 1.
88504  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88505  *        operation" and do not affect the gate state machine.
88506  */
88507 #define SEMA4_Gate11_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK)
88508 /*! @} */
88509 
88510 /*! @name Gate12 - Semaphores Gate 12 Register */
88511 /*! @{ */
88512 
88513 #define SEMA4_Gate12_GTFSM_MASK                  (0x3U)
88514 #define SEMA4_Gate12_GTFSM_SHIFT                 (0U)
88515 /*! GTFSM - Gate Finite State Machine.
88516  *  0b00..The gate is unlocked (free).
88517  *  0b01..The gate has been locked by processor 0.
88518  *  0b10..The gate has been locked by processor 1.
88519  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88520  *        operation" and do not affect the gate state machine.
88521  */
88522 #define SEMA4_Gate12_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK)
88523 /*! @} */
88524 
88525 /*! @name Gate13 - Semaphores Gate 13 Register */
88526 /*! @{ */
88527 
88528 #define SEMA4_Gate13_GTFSM_MASK                  (0x3U)
88529 #define SEMA4_Gate13_GTFSM_SHIFT                 (0U)
88530 /*! GTFSM - Gate Finite State Machine.
88531  *  0b00..The gate is unlocked (free).
88532  *  0b01..The gate has been locked by processor 0.
88533  *  0b10..The gate has been locked by processor 1.
88534  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88535  *        operation" and do not affect the gate state machine.
88536  */
88537 #define SEMA4_Gate13_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK)
88538 /*! @} */
88539 
88540 /*! @name Gate14 - Semaphores Gate 14 Register */
88541 /*! @{ */
88542 
88543 #define SEMA4_Gate14_GTFSM_MASK                  (0x3U)
88544 #define SEMA4_Gate14_GTFSM_SHIFT                 (0U)
88545 /*! GTFSM - Gate Finite State Machine.
88546  *  0b00..The gate is unlocked (free).
88547  *  0b01..The gate has been locked by processor 0.
88548  *  0b10..The gate has been locked by processor 1.
88549  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88550  *        operation" and do not affect the gate state machine.
88551  */
88552 #define SEMA4_Gate14_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK)
88553 /*! @} */
88554 
88555 /*! @name Gate15 - Semaphores Gate 15 Register */
88556 /*! @{ */
88557 
88558 #define SEMA4_Gate15_GTFSM_MASK                  (0x3U)
88559 #define SEMA4_Gate15_GTFSM_SHIFT                 (0U)
88560 /*! GTFSM - Gate Finite State Machine.
88561  *  0b00..The gate is unlocked (free).
88562  *  0b01..The gate has been locked by processor 0.
88563  *  0b10..The gate has been locked by processor 1.
88564  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
88565  *        operation" and do not affect the gate state machine.
88566  */
88567 #define SEMA4_Gate15_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK)
88568 /*! @} */
88569 
88570 /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
88571 /*! @{ */
88572 
88573 #define SEMA4_CPINE_INE7_MASK                    (0x1U)
88574 #define SEMA4_CPINE_INE7_SHIFT                   (0U)
88575 /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
88576  *    of an interrupt notification from a failed attempt to lock gate 7.
88577  *  0b0..The generation of the notification interrupt is disabled.
88578  *  0b1..The generation of the notification interrupt is enabled.
88579  */
88580 #define SEMA4_CPINE_INE7(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
88581 
88582 #define SEMA4_CPINE_INE6_MASK                    (0x2U)
88583 #define SEMA4_CPINE_INE6_SHIFT                   (1U)
88584 /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
88585  *    of an interrupt notification from a failed attempt to lock gate 6.
88586  *  0b0..The generation of the notification interrupt is disabled.
88587  *  0b1..The generation of the notification interrupt is enabled.
88588  */
88589 #define SEMA4_CPINE_INE6(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
88590 
88591 #define SEMA4_CPINE_INE5_MASK                    (0x4U)
88592 #define SEMA4_CPINE_INE5_SHIFT                   (2U)
88593 /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
88594  *    of an interrupt notification from a failed attempt to lock gate 5.
88595  *  0b0..The generation of the notification interrupt is disabled.
88596  *  0b1..The generation of the notification interrupt is enabled.
88597  */
88598 #define SEMA4_CPINE_INE5(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
88599 
88600 #define SEMA4_CPINE_INE4_MASK                    (0x8U)
88601 #define SEMA4_CPINE_INE4_SHIFT                   (3U)
88602 /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
88603  *    of an interrupt notification from a failed attempt to lock gate 4.
88604  *  0b0..The generation of the notification interrupt is disabled.
88605  *  0b1..The generation of the notification interrupt is enabled.
88606  */
88607 #define SEMA4_CPINE_INE4(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
88608 
88609 #define SEMA4_CPINE_INE3_MASK                    (0x10U)
88610 #define SEMA4_CPINE_INE3_SHIFT                   (4U)
88611 /*! INE3
88612  *  0b0..The generation of the notification interrupt is disabled.
88613  *  0b1..The generation of the notification interrupt is enabled.
88614  */
88615 #define SEMA4_CPINE_INE3(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
88616 
88617 #define SEMA4_CPINE_INE2_MASK                    (0x20U)
88618 #define SEMA4_CPINE_INE2_SHIFT                   (5U)
88619 /*! INE2
88620  *  0b0..The generation of the notification interrupt is disabled.
88621  *  0b1..The generation of the notification interrupt is enabled.
88622  */
88623 #define SEMA4_CPINE_INE2(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
88624 
88625 #define SEMA4_CPINE_INE1_MASK                    (0x40U)
88626 #define SEMA4_CPINE_INE1_SHIFT                   (6U)
88627 /*! INE1
88628  *  0b0..The generation of the notification interrupt is disabled.
88629  *  0b1..The generation of the notification interrupt is enabled.
88630  */
88631 #define SEMA4_CPINE_INE1(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
88632 
88633 #define SEMA4_CPINE_INE0_MASK                    (0x80U)
88634 #define SEMA4_CPINE_INE0_SHIFT                   (7U)
88635 /*! INE0
88636  *  0b0..The generation of the notification interrupt is disabled.
88637  *  0b1..The generation of the notification interrupt is enabled.
88638  */
88639 #define SEMA4_CPINE_INE0(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
88640 
88641 #define SEMA4_CPINE_INE15_MASK                   (0x100U)
88642 #define SEMA4_CPINE_INE15_SHIFT                  (8U)
88643 /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
88644  *    generation of an interrupt notification from a failed attempt to lock gate 15.
88645  *  0b0..The generation of the notification interrupt is disabled.
88646  *  0b1..The generation of the notification interrupt is enabled.
88647  */
88648 #define SEMA4_CPINE_INE15(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
88649 
88650 #define SEMA4_CPINE_INE14_MASK                   (0x200U)
88651 #define SEMA4_CPINE_INE14_SHIFT                  (9U)
88652 /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
88653  *    generation of an interrupt notification from a failed attempt to lock gate 14.
88654  *  0b0..The generation of the notification interrupt is disabled.
88655  *  0b1..The generation of the notification interrupt is enabled.
88656  */
88657 #define SEMA4_CPINE_INE14(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
88658 
88659 #define SEMA4_CPINE_INE13_MASK                   (0x400U)
88660 #define SEMA4_CPINE_INE13_SHIFT                  (10U)
88661 /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
88662  *    generation of an interrupt notification from a failed attempt to lock gate 13.
88663  *  0b0..The generation of the notification interrupt is disabled.
88664  *  0b1..The generation of the notification interrupt is enabled.
88665  */
88666 #define SEMA4_CPINE_INE13(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
88667 
88668 #define SEMA4_CPINE_INE12_MASK                   (0x800U)
88669 #define SEMA4_CPINE_INE12_SHIFT                  (11U)
88670 /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
88671  *    generation of an interrupt notification from a failed attempt to lock gate 12.
88672  *  0b0..The generation of the notification interrupt is disabled.
88673  *  0b1..The generation of the notification interrupt is enabled.
88674  */
88675 #define SEMA4_CPINE_INE12(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
88676 
88677 #define SEMA4_CPINE_INE11_MASK                   (0x1000U)
88678 #define SEMA4_CPINE_INE11_SHIFT                  (12U)
88679 /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
88680  *    generation of an interrupt notification from a failed attempt to lock gate 11.
88681  *  0b0..The generation of the notification interrupt is disabled.
88682  *  0b1..The generation of the notification interrupt is enabled.
88683  */
88684 #define SEMA4_CPINE_INE11(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
88685 
88686 #define SEMA4_CPINE_INE10_MASK                   (0x2000U)
88687 #define SEMA4_CPINE_INE10_SHIFT                  (13U)
88688 /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
88689  *    generation of an interrupt notification from a failed attempt to lock gate 10.
88690  *  0b0..The generation of the notification interrupt is disabled.
88691  *  0b1..The generation of the notification interrupt is enabled.
88692  */
88693 #define SEMA4_CPINE_INE10(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
88694 
88695 #define SEMA4_CPINE_INE9_MASK                    (0x4000U)
88696 #define SEMA4_CPINE_INE9_SHIFT                   (14U)
88697 /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
88698  *    of an interrupt notification from a failed attempt to lock gate 9.
88699  *  0b0..The generation of the notification interrupt is disabled.
88700  *  0b1..The generation of the notification interrupt is enabled.
88701  */
88702 #define SEMA4_CPINE_INE9(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
88703 
88704 #define SEMA4_CPINE_INE8_MASK                    (0x8000U)
88705 #define SEMA4_CPINE_INE8_SHIFT                   (15U)
88706 /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
88707  *    of an interrupt notification from a failed attempt to lock gate 8.
88708  *  0b0..The generation of the notification interrupt is disabled.
88709  *  0b1..The generation of the notification interrupt is enabled.
88710  */
88711 #define SEMA4_CPINE_INE8(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
88712 /*! @} */
88713 
88714 /* The count of SEMA4_CPINE */
88715 #define SEMA4_CPINE_COUNT                        (2U)
88716 
88717 /*! @name CPNTF - Semaphores Processor n IRQ Notification */
88718 /*! @{ */
88719 
88720 #define SEMA4_CPNTF_GN7_MASK                     (0x1U)
88721 #define SEMA4_CPNTF_GN7_SHIFT                    (0U)
88722 #define SEMA4_CPNTF_GN7(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
88723 
88724 #define SEMA4_CPNTF_GN6_MASK                     (0x2U)
88725 #define SEMA4_CPNTF_GN6_SHIFT                    (1U)
88726 #define SEMA4_CPNTF_GN6(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
88727 
88728 #define SEMA4_CPNTF_GN5_MASK                     (0x4U)
88729 #define SEMA4_CPNTF_GN5_SHIFT                    (2U)
88730 #define SEMA4_CPNTF_GN5(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
88731 
88732 #define SEMA4_CPNTF_GN4_MASK                     (0x8U)
88733 #define SEMA4_CPNTF_GN4_SHIFT                    (3U)
88734 #define SEMA4_CPNTF_GN4(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
88735 
88736 #define SEMA4_CPNTF_GN3_MASK                     (0x10U)
88737 #define SEMA4_CPNTF_GN3_SHIFT                    (4U)
88738 #define SEMA4_CPNTF_GN3(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
88739 
88740 #define SEMA4_CPNTF_GN2_MASK                     (0x20U)
88741 #define SEMA4_CPNTF_GN2_SHIFT                    (5U)
88742 #define SEMA4_CPNTF_GN2(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
88743 
88744 #define SEMA4_CPNTF_GN1_MASK                     (0x40U)
88745 #define SEMA4_CPNTF_GN1_SHIFT                    (6U)
88746 #define SEMA4_CPNTF_GN1(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
88747 
88748 #define SEMA4_CPNTF_GN0_MASK                     (0x80U)
88749 #define SEMA4_CPNTF_GN0_SHIFT                    (7U)
88750 #define SEMA4_CPNTF_GN0(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
88751 
88752 #define SEMA4_CPNTF_GN15_MASK                    (0x100U)
88753 #define SEMA4_CPNTF_GN15_SHIFT                   (8U)
88754 #define SEMA4_CPNTF_GN15(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
88755 
88756 #define SEMA4_CPNTF_GN14_MASK                    (0x200U)
88757 #define SEMA4_CPNTF_GN14_SHIFT                   (9U)
88758 #define SEMA4_CPNTF_GN14(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
88759 
88760 #define SEMA4_CPNTF_GN13_MASK                    (0x400U)
88761 #define SEMA4_CPNTF_GN13_SHIFT                   (10U)
88762 #define SEMA4_CPNTF_GN13(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
88763 
88764 #define SEMA4_CPNTF_GN12_MASK                    (0x800U)
88765 #define SEMA4_CPNTF_GN12_SHIFT                   (11U)
88766 #define SEMA4_CPNTF_GN12(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
88767 
88768 #define SEMA4_CPNTF_GN11_MASK                    (0x1000U)
88769 #define SEMA4_CPNTF_GN11_SHIFT                   (12U)
88770 #define SEMA4_CPNTF_GN11(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
88771 
88772 #define SEMA4_CPNTF_GN10_MASK                    (0x2000U)
88773 #define SEMA4_CPNTF_GN10_SHIFT                   (13U)
88774 #define SEMA4_CPNTF_GN10(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
88775 
88776 #define SEMA4_CPNTF_GN9_MASK                     (0x4000U)
88777 #define SEMA4_CPNTF_GN9_SHIFT                    (14U)
88778 #define SEMA4_CPNTF_GN9(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
88779 
88780 #define SEMA4_CPNTF_GN8_MASK                     (0x8000U)
88781 #define SEMA4_CPNTF_GN8_SHIFT                    (15U)
88782 #define SEMA4_CPNTF_GN8(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
88783 /*! @} */
88784 
88785 /* The count of SEMA4_CPNTF */
88786 #define SEMA4_CPNTF_COUNT                        (2U)
88787 
88788 /*! @name RSTGT - Semaphores (Secure) Reset Gate n */
88789 /*! @{ */
88790 
88791 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    (0xFFU)
88792 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   (0U)
88793 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
88794 
88795 #define SEMA4_RSTGT_RSTGTN_MASK                  (0xFF00U)
88796 #define SEMA4_RSTGT_RSTGTN_SHIFT                 (8U)
88797 #define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
88798 /*! @} */
88799 
88800 /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
88801 /*! @{ */
88802 
88803 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   (0xFFU)
88804 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  (0U)
88805 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
88806 
88807 #define SEMA4_RSTNTF_RSTNTN_MASK                 (0xFF00U)
88808 #define SEMA4_RSTNTF_RSTNTN_SHIFT                (8U)
88809 #define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
88810 /*! @} */
88811 
88812 
88813 /*!
88814  * @}
88815  */ /* end of group SEMA4_Register_Masks */
88816 
88817 
88818 /* SEMA4 - Peripheral instance base addresses */
88819 /** Peripheral SEMA4 base address */
88820 #define SEMA4_BASE                               (0x30AC0000u)
88821 /** Peripheral SEMA4 base pointer */
88822 #define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
88823 /** Array initializer of SEMA4 peripheral base addresses */
88824 #define SEMA4_BASE_ADDRS                         { SEMA4_BASE }
88825 /** Array initializer of SEMA4 peripheral base pointers */
88826 #define SEMA4_BASE_PTRS                          { SEMA4 }
88827 
88828 /*!
88829  * @}
88830  */ /* end of group SEMA4_Peripheral_Access_Layer */
88831 
88832 
88833 /* ----------------------------------------------------------------------------
88834    -- SNVS Peripheral Access Layer
88835    ---------------------------------------------------------------------------- */
88836 
88837 /*!
88838  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
88839  * @{
88840  */
88841 
88842 /** SNVS - Register Layout Typedef */
88843 typedef struct {
88844        uint8_t RESERVED_0[4];
88845   __IO uint32_t HPCOMR;                            /**< SNVS_HP Command Register, offset: 0x4 */
88846   __IO uint32_t HPCR;                              /**< SNVS_HP Control Register, offset: 0x8 */
88847        uint8_t RESERVED_1[8];
88848   __IO uint32_t HPSR;                              /**< SNVS_HP Status Register, offset: 0x14 */
88849        uint8_t RESERVED_2[12];
88850   __IO uint32_t HPRTCMR;                           /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
88851   __IO uint32_t HPRTCLR;                           /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
88852   __IO uint32_t HPTAMR;                            /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
88853   __IO uint32_t HPTALR;                            /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
88854   __IO uint32_t LPLR;                              /**< SNVS_LP Lock Register, offset: 0x34 */
88855   __IO uint32_t LPCR;                              /**< SNVS_LP Control Register, offset: 0x38 */
88856        uint8_t RESERVED_3[16];
88857   __IO uint32_t LPSR;                              /**< SNVS_LP Status Register, offset: 0x4C */
88858        uint8_t RESERVED_4[12];
88859   __IO uint32_t LPSMCMR;                           /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
88860   __IO uint32_t LPSMCLR;                           /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
88861   __IO uint32_t LPPGDR;                            /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
88862   __IO uint32_t LPGPR0_LEGACY_ALIAS;               /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
88863        uint8_t RESERVED_5[36];
88864   __IO uint32_t LPGPR_ALIAS[4];                    /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
88865        uint8_t RESERVED_6[96];
88866   __IO uint32_t LPGPR[4];                          /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
88867        uint8_t RESERVED_7[2792];
88868   __I  uint32_t HPVIDR1;                           /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
88869   __I  uint32_t HPVIDR2;                           /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
88870 } SNVS_Type;
88871 
88872 /* ----------------------------------------------------------------------------
88873    -- SNVS Register Masks
88874    ---------------------------------------------------------------------------- */
88875 
88876 /*!
88877  * @addtogroup SNVS_Register_Masks SNVS Register Masks
88878  * @{
88879  */
88880 
88881 /*! @name HPCOMR - SNVS_HP Command Register */
88882 /*! @{ */
88883 
88884 #define SNVS_HPCOMR_LP_SWR_MASK                  (0x10U)
88885 #define SNVS_HPCOMR_LP_SWR_SHIFT                 (4U)
88886 /*! LP_SWR
88887  *  0b0..No Action
88888  *  0b1..Reset LP section
88889  */
88890 #define SNVS_HPCOMR_LP_SWR(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
88891 
88892 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              (0x20U)
88893 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             (5U)
88894 /*! LP_SWR_DIS
88895  *  0b0..LP software reset is enabled
88896  *  0b1..LP software reset is disabled
88897  */
88898 #define SNVS_HPCOMR_LP_SWR_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
88899 
88900 #define SNVS_HPCOMR_NPSWA_EN_MASK                (0x80000000U)
88901 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               (31U)
88902 #define SNVS_HPCOMR_NPSWA_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
88903 /*! @} */
88904 
88905 /*! @name HPCR - SNVS_HP Control Register */
88906 /*! @{ */
88907 
88908 #define SNVS_HPCR_RTC_EN_MASK                    (0x1U)
88909 #define SNVS_HPCR_RTC_EN_SHIFT                   (0U)
88910 /*! RTC_EN
88911  *  0b0..RTC is disabled
88912  *  0b1..RTC is enabled
88913  */
88914 #define SNVS_HPCR_RTC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
88915 
88916 #define SNVS_HPCR_HPTA_EN_MASK                   (0x2U)
88917 #define SNVS_HPCR_HPTA_EN_SHIFT                  (1U)
88918 /*! HPTA_EN
88919  *  0b0..HP Time Alarm Interrupt is disabled
88920  *  0b1..HP Time Alarm Interrupt is enabled
88921  */
88922 #define SNVS_HPCR_HPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
88923 
88924 #define SNVS_HPCR_HPCALB_EN_MASK                 (0x100U)
88925 #define SNVS_HPCR_HPCALB_EN_SHIFT                (8U)
88926 /*! HPCALB_EN
88927  *  0b0..HP Timer calibration disabled
88928  *  0b1..HP Timer calibration enabled
88929  */
88930 #define SNVS_HPCR_HPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
88931 
88932 #define SNVS_HPCR_HPCALB_VAL_MASK                (0x7C00U)
88933 #define SNVS_HPCR_HPCALB_VAL_SHIFT               (10U)
88934 /*! HPCALB_VAL
88935  *  0b00000..+0 counts per each 32768 ticks of the counter
88936  *  0b00001..+1 counts per each 32768 ticks of the counter
88937  *  0b00010..+2 counts per each 32768 ticks of the counter
88938  *  0b01111..+15 counts per each 32768 ticks of the counter
88939  *  0b10000..-16 counts per each 32768 ticks of the counter
88940  *  0b10001..-15 counts per each 32768 ticks of the counter
88941  *  0b11110..-2 counts per each 32768 ticks of the counter
88942  *  0b11111..-1 counts per each 32768 ticks of the counter
88943  */
88944 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
88945 
88946 #define SNVS_HPCR_BTN_CONFIG_MASK                (0x7000000U)
88947 #define SNVS_HPCR_BTN_CONFIG_SHIFT               (24U)
88948 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
88949 
88950 #define SNVS_HPCR_BTN_MASK_MASK                  (0x8000000U)
88951 #define SNVS_HPCR_BTN_MASK_SHIFT                 (27U)
88952 #define SNVS_HPCR_BTN_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
88953 /*! @} */
88954 
88955 /*! @name HPSR - SNVS_HP Status Register */
88956 /*! @{ */
88957 
88958 #define SNVS_HPSR_HPTA_MASK                      (0x1U)
88959 #define SNVS_HPSR_HPTA_SHIFT                     (0U)
88960 /*! HPTA
88961  *  0b0..No time alarm interrupt occurred.
88962  *  0b1..A time alarm interrupt occurred.
88963  */
88964 #define SNVS_HPSR_HPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
88965 
88966 #define SNVS_HPSR_LPDIS_MASK                     (0x10U)
88967 #define SNVS_HPSR_LPDIS_SHIFT                    (4U)
88968 #define SNVS_HPSR_LPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
88969 
88970 #define SNVS_HPSR_BTN_MASK                       (0x40U)
88971 #define SNVS_HPSR_BTN_SHIFT                      (6U)
88972 #define SNVS_HPSR_BTN(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
88973 
88974 #define SNVS_HPSR_BI_MASK                        (0x80U)
88975 #define SNVS_HPSR_BI_SHIFT                       (7U)
88976 #define SNVS_HPSR_BI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
88977 /*! @} */
88978 
88979 /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
88980 /*! @{ */
88981 
88982 #define SNVS_HPRTCMR_RTC_MASK                    (0x7FFFU)
88983 #define SNVS_HPRTCMR_RTC_SHIFT                   (0U)
88984 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
88985 /*! @} */
88986 
88987 /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
88988 /*! @{ */
88989 
88990 #define SNVS_HPRTCLR_RTC_MASK                    (0xFFFFFFFFU)
88991 #define SNVS_HPRTCLR_RTC_SHIFT                   (0U)
88992 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
88993 /*! @} */
88994 
88995 /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
88996 /*! @{ */
88997 
88998 #define SNVS_HPTAMR_HPTA_MS_MASK                 (0x7FFFU)
88999 #define SNVS_HPTAMR_HPTA_MS_SHIFT                (0U)
89000 #define SNVS_HPTAMR_HPTA_MS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
89001 /*! @} */
89002 
89003 /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
89004 /*! @{ */
89005 
89006 #define SNVS_HPTALR_HPTA_LS_MASK                 (0xFFFFFFFFU)
89007 #define SNVS_HPTALR_HPTA_LS_SHIFT                (0U)
89008 #define SNVS_HPTALR_HPTA_LS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
89009 /*! @} */
89010 
89011 /*! @name LPLR - SNVS_LP Lock Register */
89012 /*! @{ */
89013 
89014 #define SNVS_LPLR_MC_HL_MASK                     (0x10U)
89015 #define SNVS_LPLR_MC_HL_SHIFT                    (4U)
89016 /*! MC_HL
89017  *  0b0..Write access (increment) is allowed.
89018  *  0b1..Write access (increment) is not allowed.
89019  */
89020 #define SNVS_LPLR_MC_HL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
89021 
89022 #define SNVS_LPLR_GPR_HL_MASK                    (0x20U)
89023 #define SNVS_LPLR_GPR_HL_SHIFT                   (5U)
89024 /*! GPR_HL
89025  *  0b0..Write access is allowed.
89026  *  0b1..Write access is not allowed.
89027  */
89028 #define SNVS_LPLR_GPR_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
89029 /*! @} */
89030 
89031 /*! @name LPCR - SNVS_LP Control Register */
89032 /*! @{ */
89033 
89034 #define SNVS_LPCR_MC_ENV_MASK                    (0x4U)
89035 #define SNVS_LPCR_MC_ENV_SHIFT                   (2U)
89036 /*! MC_ENV
89037  *  0b0..MC is disabled or invalid.
89038  *  0b1..MC is enabled and valid.
89039  */
89040 #define SNVS_LPCR_MC_ENV(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
89041 
89042 #define SNVS_LPCR_LPWUI_EN_MASK                  (0x8U)
89043 #define SNVS_LPCR_LPWUI_EN_SHIFT                 (3U)
89044 #define SNVS_LPCR_LPWUI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
89045 
89046 #define SNVS_LPCR_DP_EN_MASK                     (0x20U)
89047 #define SNVS_LPCR_DP_EN_SHIFT                    (5U)
89048 /*! DP_EN
89049  *  0b0..Smart PMIC enabled.
89050  *  0b1..Dumb PMIC enabled.
89051  */
89052 #define SNVS_LPCR_DP_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
89053 
89054 #define SNVS_LPCR_TOP_MASK                       (0x40U)
89055 #define SNVS_LPCR_TOP_SHIFT                      (6U)
89056 /*! TOP
89057  *  0b0..Leave system power on.
89058  *  0b1..Turn off system power.
89059  */
89060 #define SNVS_LPCR_TOP(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
89061 
89062 #define SNVS_LPCR_PWR_GLITCH_EN_MASK             (0x80U)
89063 #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT            (7U)
89064 #define SNVS_LPCR_PWR_GLITCH_EN(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
89065 
89066 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            (0x30000U)
89067 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           (16U)
89068 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
89069 
89070 #define SNVS_LPCR_DEBOUNCE_MASK                  (0xC0000U)
89071 #define SNVS_LPCR_DEBOUNCE_SHIFT                 (18U)
89072 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
89073 
89074 #define SNVS_LPCR_ON_TIME_MASK                   (0x300000U)
89075 #define SNVS_LPCR_ON_TIME_SHIFT                  (20U)
89076 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
89077 
89078 #define SNVS_LPCR_PK_EN_MASK                     (0x400000U)
89079 #define SNVS_LPCR_PK_EN_SHIFT                    (22U)
89080 #define SNVS_LPCR_PK_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
89081 
89082 #define SNVS_LPCR_PK_OVERRIDE_MASK               (0x800000U)
89083 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              (23U)
89084 #define SNVS_LPCR_PK_OVERRIDE(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
89085 /*! @} */
89086 
89087 /*! @name LPSR - SNVS_LP Status Register */
89088 /*! @{ */
89089 
89090 #define SNVS_LPSR_MCR_MASK                       (0x4U)
89091 #define SNVS_LPSR_MCR_SHIFT                      (2U)
89092 /*! MCR
89093  *  0b0..MC has not reached its maximum value.
89094  *  0b1..MC has reached its maximum value.
89095  */
89096 #define SNVS_LPSR_MCR(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
89097 
89098 #define SNVS_LPSR_EO_MASK                        (0x20000U)
89099 #define SNVS_LPSR_EO_SHIFT                       (17U)
89100 /*! EO
89101  *  0b0..Emergency off was not detected.
89102  *  0b1..Emergency off was detected.
89103  */
89104 #define SNVS_LPSR_EO(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
89105 
89106 #define SNVS_LPSR_SPOF_MASK                      (0x40000U)
89107 #define SNVS_LPSR_SPOF_SHIFT                     (18U)
89108 /*! SPOF
89109  *  0b0..Set Power Off was not detected.
89110  *  0b1..Set Power Off was detected.
89111  */
89112 #define SNVS_LPSR_SPOF(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
89113 /*! @} */
89114 
89115 /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
89116 /*! @{ */
89117 
89118 #define SNVS_LPSMCMR_MON_COUNTER_MASK            (0xFFFFU)
89119 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           (0U)
89120 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
89121 
89122 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            (0xFFFF0000U)
89123 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           (16U)
89124 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
89125 /*! @} */
89126 
89127 /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
89128 /*! @{ */
89129 
89130 #define SNVS_LPSMCLR_MON_COUNTER_MASK            (0xFFFFFFFFU)
89131 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           (0U)
89132 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
89133 /*! @} */
89134 
89135 /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */
89136 /*! @{ */
89137 
89138 #define SNVS_LPPGDR_PGD_MASK                     (0xFFFFFFFFU)
89139 #define SNVS_LPPGDR_PGD_SHIFT                    (0U)
89140 #define SNVS_LPPGDR_PGD(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
89141 /*! @} */
89142 
89143 /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
89144 /*! @{ */
89145 
89146 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK        (0xFFFFFFFFU)
89147 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT       (0U)
89148 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
89149 /*! @} */
89150 
89151 /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
89152 /*! @{ */
89153 
89154 #define SNVS_LPGPR_ALIAS_GPR_MASK                (0xFFFFFFFFU)
89155 #define SNVS_LPGPR_ALIAS_GPR_SHIFT               (0U)
89156 #define SNVS_LPGPR_ALIAS_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
89157 /*! @} */
89158 
89159 /* The count of SNVS_LPGPR_ALIAS */
89160 #define SNVS_LPGPR_ALIAS_COUNT                   (4U)
89161 
89162 /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
89163 /*! @{ */
89164 
89165 #define SNVS_LPGPR_GPR_MASK                      (0xFFFFFFFFU)
89166 #define SNVS_LPGPR_GPR_SHIFT                     (0U)
89167 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
89168 /*! @} */
89169 
89170 /* The count of SNVS_LPGPR */
89171 #define SNVS_LPGPR_COUNT                         (4U)
89172 
89173 /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
89174 /*! @{ */
89175 
89176 #define SNVS_HPVIDR1_MINOR_REV_MASK              (0xFFU)
89177 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             (0U)
89178 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
89179 
89180 #define SNVS_HPVIDR1_MAJOR_REV_MASK              (0xFF00U)
89181 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             (8U)
89182 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
89183 
89184 #define SNVS_HPVIDR1_IP_ID_MASK                  (0xFFFF0000U)
89185 #define SNVS_HPVIDR1_IP_ID_SHIFT                 (16U)
89186 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
89187 /*! @} */
89188 
89189 /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
89190 /*! @{ */
89191 
89192 #define SNVS_HPVIDR2_CONFIG_OPT_MASK             (0xFFU)
89193 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT            (0U)
89194 #define SNVS_HPVIDR2_CONFIG_OPT(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
89195 
89196 #define SNVS_HPVIDR2_ECO_REV_MASK                (0xFF00U)
89197 #define SNVS_HPVIDR2_ECO_REV_SHIFT               (8U)
89198 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
89199 
89200 #define SNVS_HPVIDR2_INTG_OPT_MASK               (0xFF0000U)
89201 #define SNVS_HPVIDR2_INTG_OPT_SHIFT              (16U)
89202 #define SNVS_HPVIDR2_INTG_OPT(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
89203 
89204 #define SNVS_HPVIDR2_IP_ERA_MASK                 (0xFF000000U)
89205 #define SNVS_HPVIDR2_IP_ERA_SHIFT                (24U)
89206 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
89207 /*! @} */
89208 
89209 
89210 /*!
89211  * @}
89212  */ /* end of group SNVS_Register_Masks */
89213 
89214 
89215 /* SNVS - Peripheral instance base addresses */
89216 /** Peripheral SNVS base address */
89217 #define SNVS_BASE                                (0x30370000u)
89218 /** Peripheral SNVS base pointer */
89219 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
89220 /** Array initializer of SNVS peripheral base addresses */
89221 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
89222 /** Array initializer of SNVS peripheral base pointers */
89223 #define SNVS_BASE_PTRS                           { SNVS }
89224 
89225 /*!
89226  * @}
89227  */ /* end of group SNVS_Peripheral_Access_Layer */
89228 
89229 
89230 /* ----------------------------------------------------------------------------
89231    -- SPBA Peripheral Access Layer
89232    ---------------------------------------------------------------------------- */
89233 
89234 /*!
89235  * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer
89236  * @{
89237  */
89238 
89239 /** SPBA - Register Layout Typedef */
89240 typedef struct {
89241   __IO uint32_t PRR[32];                           /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */
89242 } SPBA_Type;
89243 
89244 /* ----------------------------------------------------------------------------
89245    -- SPBA Register Masks
89246    ---------------------------------------------------------------------------- */
89247 
89248 /*!
89249  * @addtogroup SPBA_Register_Masks SPBA Register Masks
89250  * @{
89251  */
89252 
89253 /*! @name PRR - Peripheral Rights Register */
89254 /*! @{ */
89255 
89256 #define SPBA_PRR_RARA_MASK                       (0x1U)
89257 #define SPBA_PRR_RARA_SHIFT                      (0U)
89258 /*! RARA
89259  *  0b0..Access to peripheral is not allowed.
89260  *  0b1..Access to peripheral is granted.
89261  */
89262 #define SPBA_PRR_RARA(x)                         (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK)
89263 
89264 #define SPBA_PRR_RARB_MASK                       (0x2U)
89265 #define SPBA_PRR_RARB_SHIFT                      (1U)
89266 /*! RARB
89267  *  0b0..Access to peripheral is not allowed.
89268  *  0b1..Access to peripheral is granted.
89269  */
89270 #define SPBA_PRR_RARB(x)                         (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK)
89271 
89272 #define SPBA_PRR_RARC_MASK                       (0x4U)
89273 #define SPBA_PRR_RARC_SHIFT                      (2U)
89274 /*! RARC
89275  *  0b0..Access to peripheral is not allowed.
89276  *  0b1..Access to peripheral is granted.
89277  */
89278 #define SPBA_PRR_RARC(x)                         (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK)
89279 
89280 #define SPBA_PRR_ROI_MASK                        (0x30000U)
89281 #define SPBA_PRR_ROI_SHIFT                       (16U)
89282 /*! ROI
89283  *  0b00..Unowned resource.
89284  *  0b01..The resource is owned by master A port.
89285  *  0b10..The resource is owned by master B port.
89286  *  0b11..The resource is owned by master C port.
89287  */
89288 #define SPBA_PRR_ROI(x)                          (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK)
89289 
89290 #define SPBA_PRR_RMO_MASK                        (0xC0000000U)
89291 #define SPBA_PRR_RMO_SHIFT                       (30U)
89292 /*! RMO
89293  *  0b00..The resource is unowned.
89294  *  0b01..Reserved.
89295  *  0b10..The resource is owned by another master.
89296  *  0b11..The resource is owned by the requesting master.
89297  */
89298 #define SPBA_PRR_RMO(x)                          (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK)
89299 /*! @} */
89300 
89301 /* The count of SPBA_PRR */
89302 #define SPBA_PRR_COUNT                           (32U)
89303 
89304 
89305 /*!
89306  * @}
89307  */ /* end of group SPBA_Register_Masks */
89308 
89309 
89310 /* SPBA - Peripheral instance base addresses */
89311 /** Peripheral SPBA1 base address */
89312 #define SPBA1_BASE                               (0x308F0000u)
89313 /** Peripheral SPBA1 base pointer */
89314 #define SPBA1                                    ((SPBA_Type *)SPBA1_BASE)
89315 /** Peripheral SPBA2 base address */
89316 #define SPBA2_BASE                               (0x30CF0000u)
89317 /** Peripheral SPBA2 base pointer */
89318 #define SPBA2                                    ((SPBA_Type *)SPBA2_BASE)
89319 /** Array initializer of SPBA peripheral base addresses */
89320 #define SPBA_BASE_ADDRS                          { SPBA1_BASE, SPBA2_BASE }
89321 /** Array initializer of SPBA peripheral base pointers */
89322 #define SPBA_BASE_PTRS                           { SPBA1, SPBA2 }
89323 
89324 /*!
89325  * @}
89326  */ /* end of group SPBA_Peripheral_Access_Layer */
89327 
89328 
89329 /* ----------------------------------------------------------------------------
89330    -- SRC Peripheral Access Layer
89331    ---------------------------------------------------------------------------- */
89332 
89333 /*!
89334  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
89335  * @{
89336  */
89337 
89338 /** SRC - Register Layout Typedef */
89339 typedef struct {
89340   __IO uint32_t SCR;                               /**< SRC Reset Control Register, offset: 0x0 */
89341   __IO uint32_t A53RCR0;                           /**< A53 Reset Control Register, offset: 0x4 */
89342   __IO uint32_t A53RCR1;                           /**< A53 Reset Control Register, offset: 0x8 */
89343   __IO uint32_t M7RCR;                             /**< M7 Reset Control Register, offset: 0xC */
89344        uint8_t RESERVED_0[8];
89345   __IO uint32_t SUPERMIX_RCR;                      /**< SUPERMIX Reset Control Register, offset: 0x18 */
89346   __IO uint32_t AUDIOMIX_RCR;                      /**< AUDIOMIX Reset Control Register, offset: 0x1C */
89347   __IO uint32_t USBPHY1_RCR;                       /**< USB PHY1 Reset Control Register, offset: 0x20 */
89348   __IO uint32_t USBPHY2_RCR;                       /**< USB PHY2 Reset Control Register, offset: 0x24 */
89349   __IO uint32_t MLMIX_RCR;                         /**< MLMIX Reset Control Register, offset: 0x28 */
89350   __IO uint32_t PCIEPHY_RCR;                       /**< PCIE PHY Reset Control Register, offset: 0x2C */
89351   __IO uint32_t HDMI_RCR;                          /**< HDMI Reset Control Register, offset: 0x30 */
89352   __IO uint32_t MEDIA_RCR;                         /**< MEDIAMIX Reset Control Register, offset: 0x34 */
89353   __IO uint32_t GPU2D_RCR;                         /**< GPU2D Reset Control Register, offset: 0x38 */
89354   __IO uint32_t GPU3D_RCR;                         /**< GPU3D Reset Control Register, offset: 0x3C */
89355   __IO uint32_t GPU_RCR;                           /**< GPU Reset Control Register, offset: 0x40 */
89356   __IO uint32_t VPU_RCR;                           /**< VPU Reset Control Register, offset: 0x44 */
89357   __IO uint32_t VPU_G1_RCR;                        /**< VPU G1 Reset Control Register, offset: 0x48 */
89358   __IO uint32_t VPU_G2_RCR;                        /**< VPU G2 Reset Control Register, offset: 0x4C */
89359   __IO uint32_t VPUVC8KE_RCR;                      /**< VPU VC8000E Reset Control Register, offset: 0x50 */
89360   __IO uint32_t NOC_RCR;                           /**< NOC Wrapper Reset Control Register, offset: 0x54 */
89361   __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x58 */
89362   __IO uint32_t SRSR;                              /**< SRC Reset Status Register, offset: 0x5C */
89363        uint8_t RESERVED_1[8];
89364   __IO uint32_t SISR;                              /**< SRC Interrupt Status Register, offset: 0x68 */
89365   __IO uint32_t SIMR;                              /**< SRC Interrupt Mask Register, offset: 0x6C */
89366   __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0x70 */
89367   __IO uint32_t GPR1;                              /**< SRC General Purpose Register 1, offset: 0x74 */
89368   __IO uint32_t GPR2;                              /**< SRC General Purpose Register 2, offset: 0x78 */
89369   __IO uint32_t GPR3;                              /**< SRC General Purpose Register 3, offset: 0x7C */
89370   __IO uint32_t GPR4;                              /**< SRC General Purpose Register 4, offset: 0x80 */
89371   __IO uint32_t GPR5;                              /**< SRC General Purpose Register 5, offset: 0x84 */
89372   __IO uint32_t GPR6;                              /**< SRC General Purpose Register 6, offset: 0x88 */
89373   __IO uint32_t GPR7;                              /**< SRC General Purpose Register 7, offset: 0x8C */
89374   __IO uint32_t GPR8;                              /**< SRC General Purpose Register 8, offset: 0x90 */
89375        uint32_t GPR9;                              /**< SRC General Purpose Register 9, offset: 0x94 */
89376        uint32_t GPR10;                             /**< SRC General Purpose Register 10, offset: 0x98 */
89377        uint8_t RESERVED_2[3940];
89378   __IO uint32_t DDRC_RCR;                          /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */
89379        uint8_t RESERVED_3[4];
89380   __IO uint32_t HDMIPHY_RCR;                       /**< HDMIPHY Reset Control Register, offset: 0x1008 */
89381   __IO uint32_t MIPIPHY1_RCR;                      /**< MIPI PHY1 Reset Control Register, offset: 0x100C */
89382   __IO uint32_t MIPIPHY2_RCR;                      /**< MIPI PHY2 Reset Control Register, offset: 0x1010 */
89383   __IO uint32_t HSIO_RCR;                          /**< HSIO Reset Control Register, offset: 0x1014 */
89384   __IO uint32_t MEDIAISPDWP_RCR;                   /**< MEDIAMIX ISP and Dewarp Reset Control Register, offset: 0x1018 */
89385 } SRC_Type;
89386 
89387 /* ----------------------------------------------------------------------------
89388    -- SRC Register Masks
89389    ---------------------------------------------------------------------------- */
89390 
89391 /*!
89392  * @addtogroup SRC_Register_Masks SRC Register Masks
89393  * @{
89394  */
89395 
89396 /*! @name SCR - SRC Reset Control Register */
89397 /*! @{ */
89398 
89399 #define SRC_SCR_MASK_TEMPSENSE_RESET_MASK        (0xF0U)
89400 #define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT       (4U)
89401 /*! MASK_TEMPSENSE_RESET
89402  *  0b0101..tempsense_reset is masked
89403  *  0b1010..tempsense_reset is not masked
89404  */
89405 #define SRC_SCR_MASK_TEMPSENSE_RESET(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK)
89406 
89407 #define SRC_SCR_DOMAIN0_MASK                     (0x1000000U)
89408 #define SRC_SCR_DOMAIN0_SHIFT                    (24U)
89409 /*! DOMAIN0
89410  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89411  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89412  */
89413 #define SRC_SCR_DOMAIN0(x)                       (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK)
89414 
89415 #define SRC_SCR_DOMAIN1_MASK                     (0x2000000U)
89416 #define SRC_SCR_DOMAIN1_SHIFT                    (25U)
89417 /*! DOMAIN1
89418  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89419  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89420  */
89421 #define SRC_SCR_DOMAIN1(x)                       (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK)
89422 
89423 #define SRC_SCR_DOMAIN2_MASK                     (0x4000000U)
89424 #define SRC_SCR_DOMAIN2_SHIFT                    (26U)
89425 /*! DOMAIN2
89426  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
89427  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
89428  */
89429 #define SRC_SCR_DOMAIN2(x)                       (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK)
89430 
89431 #define SRC_SCR_DOMAIN3_MASK                     (0x8000000U)
89432 #define SRC_SCR_DOMAIN3_SHIFT                    (27U)
89433 /*! DOMAIN3
89434  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
89435  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
89436  */
89437 #define SRC_SCR_DOMAIN3(x)                       (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK)
89438 
89439 #define SRC_SCR_LOCK_MASK                        (0x40000000U)
89440 #define SRC_SCR_LOCK_SHIFT                       (30U)
89441 /*! LOCK
89442  *  0b0..[31] and [27:24] bits can be modified
89443  *  0b1..[31] and [27:24] bits cannot be modified
89444  */
89445 #define SRC_SCR_LOCK(x)                          (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK)
89446 
89447 #define SRC_SCR_DOM_EN_MASK                      (0x80000000U)
89448 #define SRC_SCR_DOM_EN_SHIFT                     (31U)
89449 /*! DOM_EN
89450  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
89451  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
89452  *       the masters from the domains specified in [27:24] area.
89453  */
89454 #define SRC_SCR_DOM_EN(x)                        (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK)
89455 /*! @} */
89456 
89457 /*! @name A53RCR0 - A53 Reset Control Register */
89458 /*! @{ */
89459 
89460 #define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK     (0x1U)
89461 #define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT    (0U)
89462 /*! A53_CORE_POR_RESET0
89463  *  0b0..do not assert core0 reset
89464  *  0b1..assert core0 reset
89465  */
89466 #define SRC_A53RCR0_A53_CORE_POR_RESET0(x)       (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK)
89467 
89468 #define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK     (0x2U)
89469 #define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT    (1U)
89470 /*! A53_CORE_POR_RESET1
89471  *  0b0..do not assert core1 reset
89472  *  0b1..assert core1 reset
89473  */
89474 #define SRC_A53RCR0_A53_CORE_POR_RESET1(x)       (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK)
89475 
89476 #define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK     (0x4U)
89477 #define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT    (2U)
89478 /*! A53_CORE_POR_RESET2
89479  *  0b0..do not assert core2 reset
89480  *  0b1..assert core2 reset
89481  */
89482 #define SRC_A53RCR0_A53_CORE_POR_RESET2(x)       (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK)
89483 
89484 #define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK     (0x8U)
89485 #define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT    (3U)
89486 /*! A53_CORE_POR_RESET3
89487  *  0b0..do not assert core3 reset
89488  *  0b1..assert core3 reset
89489  */
89490 #define SRC_A53RCR0_A53_CORE_POR_RESET3(x)       (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK)
89491 
89492 #define SRC_A53RCR0_A53_CORE_RESET0_MASK         (0x10U)
89493 #define SRC_A53RCR0_A53_CORE_RESET0_SHIFT        (4U)
89494 /*! A53_CORE_RESET0
89495  *  0b0..do not assert core0 reset
89496  *  0b1..assert core0 reset
89497  */
89498 #define SRC_A53RCR0_A53_CORE_RESET0(x)           (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK)
89499 
89500 #define SRC_A53RCR0_A53_CORE_RESET1_MASK         (0x20U)
89501 #define SRC_A53RCR0_A53_CORE_RESET1_SHIFT        (5U)
89502 /*! A53_CORE_RESET1
89503  *  0b0..do not assert core1 reset
89504  *  0b1..assert core1 reset
89505  */
89506 #define SRC_A53RCR0_A53_CORE_RESET1(x)           (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK)
89507 
89508 #define SRC_A53RCR0_A53_CORE_RESET2_MASK         (0x40U)
89509 #define SRC_A53RCR0_A53_CORE_RESET2_SHIFT        (6U)
89510 /*! A53_CORE_RESET2
89511  *  0b0..do not assert core2 reset
89512  *  0b1..assert core2 reset
89513  */
89514 #define SRC_A53RCR0_A53_CORE_RESET2(x)           (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK)
89515 
89516 #define SRC_A53RCR0_A53_CORE_RESET3_MASK         (0x80U)
89517 #define SRC_A53RCR0_A53_CORE_RESET3_SHIFT        (7U)
89518 /*! A53_CORE_RESET3
89519  *  0b0..do not assert core3 reset
89520  *  0b1..assert core3 reset
89521  */
89522 #define SRC_A53RCR0_A53_CORE_RESET3(x)           (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK)
89523 
89524 #define SRC_A53RCR0_A53_DBG_RESET0_MASK          (0x100U)
89525 #define SRC_A53RCR0_A53_DBG_RESET0_SHIFT         (8U)
89526 /*! A53_DBG_RESET0
89527  *  0b0..do not assert core0 debug reset
89528  *  0b1..assert core0 debug reset
89529  */
89530 #define SRC_A53RCR0_A53_DBG_RESET0(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK)
89531 
89532 #define SRC_A53RCR0_A53_DBG_RESET1_MASK          (0x200U)
89533 #define SRC_A53RCR0_A53_DBG_RESET1_SHIFT         (9U)
89534 /*! A53_DBG_RESET1
89535  *  0b0..do not assert core1 debug reset
89536  *  0b1..assert core1 debug reset
89537  */
89538 #define SRC_A53RCR0_A53_DBG_RESET1(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK)
89539 
89540 #define SRC_A53RCR0_A53_DBG_RESET2_MASK          (0x400U)
89541 #define SRC_A53RCR0_A53_DBG_RESET2_SHIFT         (10U)
89542 /*! A53_DBG_RESET2
89543  *  0b0..do not assert core2 debug reset
89544  *  0b1..assert core2 debug reset
89545  */
89546 #define SRC_A53RCR0_A53_DBG_RESET2(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK)
89547 
89548 #define SRC_A53RCR0_A53_DBG_RESET3_MASK          (0x800U)
89549 #define SRC_A53RCR0_A53_DBG_RESET3_SHIFT         (11U)
89550 /*! A53_DBG_RESET3
89551  *  0b0..do not assert core3 debug reset
89552  *  0b1..assert core3 debug reset
89553  */
89554 #define SRC_A53RCR0_A53_DBG_RESET3(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK)
89555 
89556 #define SRC_A53RCR0_A53_ETM_RESET0_MASK          (0x1000U)
89557 #define SRC_A53RCR0_A53_ETM_RESET0_SHIFT         (12U)
89558 /*! A53_ETM_RESET0
89559  *  0b0..do not assert core0 ETM reset
89560  *  0b1..assert core0 ETM reset
89561  */
89562 #define SRC_A53RCR0_A53_ETM_RESET0(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK)
89563 
89564 #define SRC_A53RCR0_A53_ETM_RESET1_MASK          (0x2000U)
89565 #define SRC_A53RCR0_A53_ETM_RESET1_SHIFT         (13U)
89566 /*! A53_ETM_RESET1
89567  *  0b0..do not assert core1 ETM reset
89568  *  0b1..assert core1 ETM reset
89569  */
89570 #define SRC_A53RCR0_A53_ETM_RESET1(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK)
89571 
89572 #define SRC_A53RCR0_A53_ETM_RESET2_MASK          (0x4000U)
89573 #define SRC_A53RCR0_A53_ETM_RESET2_SHIFT         (14U)
89574 /*! A53_ETM_RESET2
89575  *  0b0..do not assert core2 ETM reset
89576  *  0b1..assert core2 ETM reset
89577  */
89578 #define SRC_A53RCR0_A53_ETM_RESET2(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK)
89579 
89580 #define SRC_A53RCR0_A53_ETM_RESET3_MASK          (0x8000U)
89581 #define SRC_A53RCR0_A53_ETM_RESET3_SHIFT         (15U)
89582 /*! A53_ETM_RESET3
89583  *  0b0..do not assert core3 ETM reset
89584  *  0b1..assert core3 ETM reset
89585  */
89586 #define SRC_A53RCR0_A53_ETM_RESET3(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK)
89587 
89588 #define SRC_A53RCR0_MASK_WDOG1_RST_MASK          (0xF0000U)
89589 #define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT         (16U)
89590 /*! MASK_WDOG1_RST
89591  *  0b0101..wdog1_rst_b is masked
89592  *  0b1010..wdog1_rst_b is not masked
89593  */
89594 #define SRC_A53RCR0_MASK_WDOG1_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK)
89595 
89596 #define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK       (0x100000U)
89597 #define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT      (20U)
89598 /*! A53_SOC_DBG_RESET
89599  *  0b0..do not assert system level debug reset
89600  *  0b1..assert system level debug reset
89601  */
89602 #define SRC_A53RCR0_A53_SOC_DBG_RESET(x)         (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK)
89603 
89604 #define SRC_A53RCR0_A53_L2RESET_MASK             (0x200000U)
89605 #define SRC_A53RCR0_A53_L2RESET_SHIFT            (21U)
89606 /*! A53_L2RESET
89607  *  0b0..do not assert SCU reset
89608  *  0b1..assert SCU reset
89609  */
89610 #define SRC_A53RCR0_A53_L2RESET(x)               (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK)
89611 
89612 #define SRC_A53RCR0_DOMAIN0_MASK                 (0x1000000U)
89613 #define SRC_A53RCR0_DOMAIN0_SHIFT                (24U)
89614 /*! DOMAIN0
89615  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89616  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89617  */
89618 #define SRC_A53RCR0_DOMAIN0(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK)
89619 
89620 #define SRC_A53RCR0_DOMAIN1_MASK                 (0x2000000U)
89621 #define SRC_A53RCR0_DOMAIN1_SHIFT                (25U)
89622 /*! DOMAIN1
89623  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89624  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89625  */
89626 #define SRC_A53RCR0_DOMAIN1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK)
89627 
89628 #define SRC_A53RCR0_DOMAIN2_MASK                 (0x4000000U)
89629 #define SRC_A53RCR0_DOMAIN2_SHIFT                (26U)
89630 /*! DOMAIN2
89631  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
89632  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
89633  */
89634 #define SRC_A53RCR0_DOMAIN2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK)
89635 
89636 #define SRC_A53RCR0_DOMAIN3_MASK                 (0x8000000U)
89637 #define SRC_A53RCR0_DOMAIN3_SHIFT                (27U)
89638 /*! DOMAIN3
89639  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
89640  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
89641  */
89642 #define SRC_A53RCR0_DOMAIN3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK)
89643 
89644 #define SRC_A53RCR0_LOCK_MASK                    (0x40000000U)
89645 #define SRC_A53RCR0_LOCK_SHIFT                   (30U)
89646 /*! LOCK
89647  *  0b0..[31] and [27:24] bits can be modified
89648  *  0b1..[31] and [27:24] bits cannot be modified
89649  */
89650 #define SRC_A53RCR0_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK)
89651 
89652 #define SRC_A53RCR0_DOM_EN_MASK                  (0x80000000U)
89653 #define SRC_A53RCR0_DOM_EN_SHIFT                 (31U)
89654 /*! DOM_EN
89655  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
89656  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
89657  *       the masters from the domains specified in [27:24] area.
89658  */
89659 #define SRC_A53RCR0_DOM_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK)
89660 /*! @} */
89661 
89662 /*! @name A53RCR1 - A53 Reset Control Register */
89663 /*! @{ */
89664 
89665 #define SRC_A53RCR1_A53_CORE0_ENABLE_MASK        (0x1U)
89666 #define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT       (0U)
89667 #define SRC_A53RCR1_A53_CORE0_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK)
89668 
89669 #define SRC_A53RCR1_A53_CORE1_ENABLE_MASK        (0x2U)
89670 #define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT       (1U)
89671 /*! A53_CORE1_ENABLE
89672  *  0b0..core1 is disabled
89673  *  0b1..core1 is enabled
89674  */
89675 #define SRC_A53RCR1_A53_CORE1_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK)
89676 
89677 #define SRC_A53RCR1_A53_CORE2_ENABLE_MASK        (0x4U)
89678 #define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT       (2U)
89679 /*! A53_CORE2_ENABLE
89680  *  0b0..core2 is disabled
89681  *  0b1..core2 is enabled
89682  */
89683 #define SRC_A53RCR1_A53_CORE2_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK)
89684 
89685 #define SRC_A53RCR1_A53_CORE3_ENABLE_MASK        (0x8U)
89686 #define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT       (3U)
89687 /*! A53_CORE3_ENABLE
89688  *  0b0..core3 is disabled
89689  *  0b1..core3 is enabled
89690  */
89691 #define SRC_A53RCR1_A53_CORE3_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK)
89692 
89693 #define SRC_A53RCR1_A53_RST_SLOW_MASK            (0x70U)
89694 #define SRC_A53RCR1_A53_RST_SLOW_SHIFT           (4U)
89695 /*! A53_RST_SLOW - A53_RST_SLOW */
89696 #define SRC_A53RCR1_A53_RST_SLOW(x)              (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK)
89697 
89698 #define SRC_A53RCR1_DOMAIN0_MASK                 (0x1000000U)
89699 #define SRC_A53RCR1_DOMAIN0_SHIFT                (24U)
89700 /*! DOMAIN0
89701  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89702  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89703  */
89704 #define SRC_A53RCR1_DOMAIN0(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK)
89705 
89706 #define SRC_A53RCR1_DOMAIN1_MASK                 (0x2000000U)
89707 #define SRC_A53RCR1_DOMAIN1_SHIFT                (25U)
89708 /*! DOMAIN1
89709  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89710  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89711  */
89712 #define SRC_A53RCR1_DOMAIN1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK)
89713 
89714 #define SRC_A53RCR1_DOMAIN2_MASK                 (0x4000000U)
89715 #define SRC_A53RCR1_DOMAIN2_SHIFT                (26U)
89716 /*! DOMAIN2
89717  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
89718  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
89719  */
89720 #define SRC_A53RCR1_DOMAIN2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK)
89721 
89722 #define SRC_A53RCR1_DOMAIN3_MASK                 (0x8000000U)
89723 #define SRC_A53RCR1_DOMAIN3_SHIFT                (27U)
89724 /*! DOMAIN3
89725  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
89726  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
89727  */
89728 #define SRC_A53RCR1_DOMAIN3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK)
89729 
89730 #define SRC_A53RCR1_LOCK_MASK                    (0x40000000U)
89731 #define SRC_A53RCR1_LOCK_SHIFT                   (30U)
89732 /*! LOCK
89733  *  0b0..[31] and [27:24] bits can be modified
89734  *  0b1..[31] and [27:24] bits cannot be modified
89735  */
89736 #define SRC_A53RCR1_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK)
89737 
89738 #define SRC_A53RCR1_DOM_EN_MASK                  (0x80000000U)
89739 #define SRC_A53RCR1_DOM_EN_SHIFT                 (31U)
89740 /*! DOM_EN
89741  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
89742  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
89743  *       the masters from the domains specified in [27:24] area.
89744  */
89745 #define SRC_A53RCR1_DOM_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK)
89746 /*! @} */
89747 
89748 /*! @name M7RCR - M7 Reset Control Register */
89749 /*! @{ */
89750 
89751 #define SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK       (0x1U)
89752 #define SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT      (0U)
89753 /*! SW_M7C_NON_SCLR_RST
89754  *  0b0..do not assert M7 core reset
89755  *  0b1..assert M7 core reset
89756  */
89757 #define SRC_M7RCR_SW_M7C_NON_SCLR_RST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT)) & SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK)
89758 
89759 #define SRC_M7RCR_SW_M7C_RST_MASK                (0x2U)
89760 #define SRC_M7RCR_SW_M7C_RST_SHIFT               (1U)
89761 /*! SW_M7C_RST
89762  *  0b0..do not assert M7 core reset
89763  *  0b1..assert M7 core reset
89764  */
89765 #define SRC_M7RCR_SW_M7C_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_RST_SHIFT)) & SRC_M7RCR_SW_M7C_RST_MASK)
89766 
89767 #define SRC_M7RCR_ENABLE_M7_MASK                 (0x8U)
89768 #define SRC_M7RCR_ENABLE_M7_SHIFT                (3U)
89769 /*! ENABLE_M7
89770  *  0b0..M7 is disabled
89771  *  0b1..M7 is enabled
89772  */
89773 #define SRC_M7RCR_ENABLE_M7(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_ENABLE_M7_SHIFT)) & SRC_M7RCR_ENABLE_M7_MASK)
89774 
89775 #define SRC_M7RCR_MASK_WDOG3_RST_MASK            (0xF0U)
89776 #define SRC_M7RCR_MASK_WDOG3_RST_SHIFT           (4U)
89777 /*! MASK_WDOG3_RST
89778  *  0b0101..wdog3_rst_b is masked
89779  *  0b1010..wdog3_rst_b is not masked
89780  */
89781 #define SRC_M7RCR_MASK_WDOG3_RST(x)              (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M7RCR_MASK_WDOG3_RST_MASK)
89782 
89783 #define SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK       (0x100U)
89784 #define SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT      (8U)
89785 /*! WDOG3_RST_OPTION_M7
89786  *  0b0..wdgo3_rst_b Reset M7 core only
89787  *  0b1..Reset both M7 core and platform
89788  */
89789 #define SRC_M7RCR_WDOG3_RST_OPTION_M7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK)
89790 
89791 #define SRC_M7RCR_WDOG3_RST_OPTION_MASK          (0x200U)
89792 #define SRC_M7RCR_WDOG3_RST_OPTION_SHIFT         (9U)
89793 /*! WDOG3_RST_OPTION
89794  *  0b0..Wdog3_rst_b asserts M7 reset
89795  *  0b1..Wdog3_rst_b asserts global reset
89796  */
89797 #define SRC_M7RCR_WDOG3_RST_OPTION(x)            (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_MASK)
89798 
89799 #define SRC_M7RCR_DOMAIN0_MASK                   (0x1000000U)
89800 #define SRC_M7RCR_DOMAIN0_SHIFT                  (24U)
89801 /*! DOMAIN0
89802  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89803  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89804  */
89805 #define SRC_M7RCR_DOMAIN0(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN0_SHIFT)) & SRC_M7RCR_DOMAIN0_MASK)
89806 
89807 #define SRC_M7RCR_DOMAIN1_MASK                   (0x2000000U)
89808 #define SRC_M7RCR_DOMAIN1_SHIFT                  (25U)
89809 /*! DOMAIN1
89810  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89811  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89812  */
89813 #define SRC_M7RCR_DOMAIN1(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN1_SHIFT)) & SRC_M7RCR_DOMAIN1_MASK)
89814 
89815 #define SRC_M7RCR_DOMAIN2_MASK                   (0x4000000U)
89816 #define SRC_M7RCR_DOMAIN2_SHIFT                  (26U)
89817 /*! DOMAIN2
89818  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
89819  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
89820  */
89821 #define SRC_M7RCR_DOMAIN2(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN2_SHIFT)) & SRC_M7RCR_DOMAIN2_MASK)
89822 
89823 #define SRC_M7RCR_DOMAIN3_MASK                   (0x8000000U)
89824 #define SRC_M7RCR_DOMAIN3_SHIFT                  (27U)
89825 /*! DOMAIN3
89826  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
89827  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
89828  */
89829 #define SRC_M7RCR_DOMAIN3(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN3_SHIFT)) & SRC_M7RCR_DOMAIN3_MASK)
89830 
89831 #define SRC_M7RCR_LOCK_MASK                      (0x40000000U)
89832 #define SRC_M7RCR_LOCK_SHIFT                     (30U)
89833 /*! LOCK
89834  *  0b0..[31] and [27:24] bits can be modified
89835  *  0b1..[31] and [27:24] bits cannot be modified
89836  */
89837 #define SRC_M7RCR_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_LOCK_SHIFT)) & SRC_M7RCR_LOCK_MASK)
89838 
89839 #define SRC_M7RCR_DOM_EN_MASK                    (0x80000000U)
89840 #define SRC_M7RCR_DOM_EN_SHIFT                   (31U)
89841 /*! DOM_EN
89842  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
89843  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
89844  *       the masters from the domains specified in [27:24] area.
89845  */
89846 #define SRC_M7RCR_DOM_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOM_EN_SHIFT)) & SRC_M7RCR_DOM_EN_MASK)
89847 /*! @} */
89848 
89849 /*! @name SUPERMIX_RCR - SUPERMIX Reset Control Register */
89850 /*! @{ */
89851 
89852 #define SRC_SUPERMIX_RCR_SUPERMIX_RESET_MASK     (0x1U)
89853 #define SRC_SUPERMIX_RCR_SUPERMIX_RESET_SHIFT    (0U)
89854 /*! SUPERMIX_RESET
89855  *  0b0..Do not assert SUPERMIX reset
89856  *  0b1..Assert SUPERMIX reset
89857  */
89858 #define SRC_SUPERMIX_RCR_SUPERMIX_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_SUPERMIX_RESET_SHIFT)) & SRC_SUPERMIX_RCR_SUPERMIX_RESET_MASK)
89859 
89860 #define SRC_SUPERMIX_RCR_DOMAIN0_MASK            (0x1000000U)
89861 #define SRC_SUPERMIX_RCR_DOMAIN0_SHIFT           (24U)
89862 /*! DOMAIN0
89863  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89864  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89865  */
89866 #define SRC_SUPERMIX_RCR_DOMAIN0(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN0_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN0_MASK)
89867 
89868 #define SRC_SUPERMIX_RCR_DOMAIN1_MASK            (0x2000000U)
89869 #define SRC_SUPERMIX_RCR_DOMAIN1_SHIFT           (25U)
89870 /*! DOMAIN1
89871  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89872  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89873  */
89874 #define SRC_SUPERMIX_RCR_DOMAIN1(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN1_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN1_MASK)
89875 
89876 #define SRC_SUPERMIX_RCR_DOMAIN2_MASK            (0x4000000U)
89877 #define SRC_SUPERMIX_RCR_DOMAIN2_SHIFT           (26U)
89878 /*! DOMAIN2
89879  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
89880  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
89881  */
89882 #define SRC_SUPERMIX_RCR_DOMAIN2(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN2_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN2_MASK)
89883 
89884 #define SRC_SUPERMIX_RCR_DOMAIN3_MASK            (0x8000000U)
89885 #define SRC_SUPERMIX_RCR_DOMAIN3_SHIFT           (27U)
89886 /*! DOMAIN3
89887  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
89888  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
89889  */
89890 #define SRC_SUPERMIX_RCR_DOMAIN3(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN3_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN3_MASK)
89891 
89892 #define SRC_SUPERMIX_RCR_LOCK_MASK               (0x40000000U)
89893 #define SRC_SUPERMIX_RCR_LOCK_SHIFT              (30U)
89894 /*! LOCK
89895  *  0b0..[31] and [27:24] bits can be modified
89896  *  0b1..[31] and [27:24] bits cannot be modified
89897  */
89898 #define SRC_SUPERMIX_RCR_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_LOCK_SHIFT)) & SRC_SUPERMIX_RCR_LOCK_MASK)
89899 
89900 #define SRC_SUPERMIX_RCR_DOM_EN_MASK             (0x80000000U)
89901 #define SRC_SUPERMIX_RCR_DOM_EN_SHIFT            (31U)
89902 /*! DOM_EN
89903  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
89904  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
89905  *       the masters from the domains specified in [27:24] area.
89906  */
89907 #define SRC_SUPERMIX_RCR_DOM_EN(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOM_EN_SHIFT)) & SRC_SUPERMIX_RCR_DOM_EN_MASK)
89908 /*! @} */
89909 
89910 /*! @name AUDIOMIX_RCR - AUDIOMIX Reset Control Register */
89911 /*! @{ */
89912 
89913 #define SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_MASK     (0x1U)
89914 #define SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_SHIFT    (0U)
89915 /*! AUDIOMIX_RESET
89916  *  0b0..Do not assert AUDIOMIX reset
89917  *  0b1..Assert AUDIOMIX reset
89918  */
89919 #define SRC_AUDIOMIX_RCR_AUDIOMIX_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_SHIFT)) & SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_MASK)
89920 
89921 #define SRC_AUDIOMIX_RCR_DOMAIN0_MASK            (0x1000000U)
89922 #define SRC_AUDIOMIX_RCR_DOMAIN0_SHIFT           (24U)
89923 /*! DOMAIN0
89924  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89925  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89926  */
89927 #define SRC_AUDIOMIX_RCR_DOMAIN0(x)              (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN0_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN0_MASK)
89928 
89929 #define SRC_AUDIOMIX_RCR_DOMAIN1_MASK            (0x2000000U)
89930 #define SRC_AUDIOMIX_RCR_DOMAIN1_SHIFT           (25U)
89931 /*! DOMAIN1
89932  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89933  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89934  */
89935 #define SRC_AUDIOMIX_RCR_DOMAIN1(x)              (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN1_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN1_MASK)
89936 
89937 #define SRC_AUDIOMIX_RCR_DOMAIN2_MASK            (0x4000000U)
89938 #define SRC_AUDIOMIX_RCR_DOMAIN2_SHIFT           (26U)
89939 /*! DOMAIN2
89940  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
89941  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
89942  */
89943 #define SRC_AUDIOMIX_RCR_DOMAIN2(x)              (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN2_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN2_MASK)
89944 
89945 #define SRC_AUDIOMIX_RCR_DOMAIN3_MASK            (0x8000000U)
89946 #define SRC_AUDIOMIX_RCR_DOMAIN3_SHIFT           (27U)
89947 /*! DOMAIN3
89948  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
89949  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
89950  */
89951 #define SRC_AUDIOMIX_RCR_DOMAIN3(x)              (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN3_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN3_MASK)
89952 
89953 #define SRC_AUDIOMIX_RCR_LOCK_MASK               (0x40000000U)
89954 #define SRC_AUDIOMIX_RCR_LOCK_SHIFT              (30U)
89955 /*! LOCK
89956  *  0b0..[31] and [27:24] bits can be modified
89957  *  0b1..[31] and [27:24] bits cannot be modified
89958  */
89959 #define SRC_AUDIOMIX_RCR_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_LOCK_SHIFT)) & SRC_AUDIOMIX_RCR_LOCK_MASK)
89960 
89961 #define SRC_AUDIOMIX_RCR_DOM_EN_MASK             (0x80000000U)
89962 #define SRC_AUDIOMIX_RCR_DOM_EN_SHIFT            (31U)
89963 /*! DOM_EN
89964  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
89965  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
89966  *       the masters from the domains specified in [27:24] area.
89967  */
89968 #define SRC_AUDIOMIX_RCR_DOM_EN(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOM_EN_SHIFT)) & SRC_AUDIOMIX_RCR_DOM_EN_MASK)
89969 /*! @} */
89970 
89971 /*! @name USBPHY1_RCR - USB PHY1 Reset Control Register */
89972 /*! @{ */
89973 
89974 #define SRC_USBPHY1_RCR_USB1_PHY_RESET_MASK      (0x1U)
89975 #define SRC_USBPHY1_RCR_USB1_PHY_RESET_SHIFT     (0U)
89976 /*! USB1_PHY_RESET
89977  *  0b0..Don't reset USB 1 PHY
89978  *  0b1..Reset USB 1 PHY
89979  */
89980 #define SRC_USBPHY1_RCR_USB1_PHY_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_USB1_PHY_RESET_SHIFT)) & SRC_USBPHY1_RCR_USB1_PHY_RESET_MASK)
89981 
89982 #define SRC_USBPHY1_RCR_DOMAIN0_MASK             (0x1000000U)
89983 #define SRC_USBPHY1_RCR_DOMAIN0_SHIFT            (24U)
89984 /*! DOMAIN0
89985  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
89986  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
89987  */
89988 #define SRC_USBPHY1_RCR_DOMAIN0(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN0_MASK)
89989 
89990 #define SRC_USBPHY1_RCR_DOMAIN1_MASK             (0x2000000U)
89991 #define SRC_USBPHY1_RCR_DOMAIN1_SHIFT            (25U)
89992 /*! DOMAIN1
89993  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
89994  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
89995  */
89996 #define SRC_USBPHY1_RCR_DOMAIN1(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN1_MASK)
89997 
89998 #define SRC_USBPHY1_RCR_DOMAIN2_MASK             (0x4000000U)
89999 #define SRC_USBPHY1_RCR_DOMAIN2_SHIFT            (26U)
90000 /*! DOMAIN2
90001  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90002  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90003  */
90004 #define SRC_USBPHY1_RCR_DOMAIN2(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN2_MASK)
90005 
90006 #define SRC_USBPHY1_RCR_DOMAIN3_MASK             (0x8000000U)
90007 #define SRC_USBPHY1_RCR_DOMAIN3_SHIFT            (27U)
90008 /*! DOMAIN3
90009  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90010  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90011  */
90012 #define SRC_USBPHY1_RCR_DOMAIN3(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN3_MASK)
90013 
90014 #define SRC_USBPHY1_RCR_LOCK_MASK                (0x40000000U)
90015 #define SRC_USBPHY1_RCR_LOCK_SHIFT               (30U)
90016 /*! LOCK
90017  *  0b0..[31] and [27:24] bits can be modified
90018  *  0b1..[31] and [27:24] bits cannot be modified
90019  */
90020 #define SRC_USBPHY1_RCR_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_LOCK_SHIFT)) & SRC_USBPHY1_RCR_LOCK_MASK)
90021 
90022 #define SRC_USBPHY1_RCR_DOM_EN_MASK              (0x80000000U)
90023 #define SRC_USBPHY1_RCR_DOM_EN_SHIFT             (31U)
90024 /*! DOM_EN
90025  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90026  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90027  *       the masters from the domains specified in [27:24] area.
90028  */
90029 #define SRC_USBPHY1_RCR_DOM_EN(x)                (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBPHY1_RCR_DOM_EN_MASK)
90030 /*! @} */
90031 
90032 /*! @name USBPHY2_RCR - USB PHY2 Reset Control Register */
90033 /*! @{ */
90034 
90035 #define SRC_USBPHY2_RCR_USB2_PHY_RESET_MASK      (0x1U)
90036 #define SRC_USBPHY2_RCR_USB2_PHY_RESET_SHIFT     (0U)
90037 /*! USB2_PHY_RESET
90038  *  0b0..Don't reset USB 2 PHY
90039  *  0b1..Reset USB 2 PHY
90040  */
90041 #define SRC_USBPHY2_RCR_USB2_PHY_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_USB2_PHY_RESET_SHIFT)) & SRC_USBPHY2_RCR_USB2_PHY_RESET_MASK)
90042 
90043 #define SRC_USBPHY2_RCR_DOMAIN0_MASK             (0x1000000U)
90044 #define SRC_USBPHY2_RCR_DOMAIN0_SHIFT            (24U)
90045 /*! DOMAIN0
90046  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90047  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90048  */
90049 #define SRC_USBPHY2_RCR_DOMAIN0(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN0_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN0_MASK)
90050 
90051 #define SRC_USBPHY2_RCR_DOMAIN1_MASK             (0x2000000U)
90052 #define SRC_USBPHY2_RCR_DOMAIN1_SHIFT            (25U)
90053 /*! DOMAIN1
90054  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90055  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90056  */
90057 #define SRC_USBPHY2_RCR_DOMAIN1(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN1_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN1_MASK)
90058 
90059 #define SRC_USBPHY2_RCR_DOMAIN2_MASK             (0x4000000U)
90060 #define SRC_USBPHY2_RCR_DOMAIN2_SHIFT            (26U)
90061 /*! DOMAIN2
90062  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90063  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90064  */
90065 #define SRC_USBPHY2_RCR_DOMAIN2(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN2_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN2_MASK)
90066 
90067 #define SRC_USBPHY2_RCR_DOMAIN3_MASK             (0x8000000U)
90068 #define SRC_USBPHY2_RCR_DOMAIN3_SHIFT            (27U)
90069 /*! DOMAIN3
90070  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90071  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90072  */
90073 #define SRC_USBPHY2_RCR_DOMAIN3(x)               (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN3_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN3_MASK)
90074 
90075 #define SRC_USBPHY2_RCR_LOCK_MASK                (0x40000000U)
90076 #define SRC_USBPHY2_RCR_LOCK_SHIFT               (30U)
90077 /*! LOCK
90078  *  0b0..[31] and [27:24] bits can be modified
90079  *  0b1..[31] and [27:24] bits cannot be modified
90080  */
90081 #define SRC_USBPHY2_RCR_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_LOCK_SHIFT)) & SRC_USBPHY2_RCR_LOCK_MASK)
90082 
90083 #define SRC_USBPHY2_RCR_DOM_EN_MASK              (0x80000000U)
90084 #define SRC_USBPHY2_RCR_DOM_EN_SHIFT             (31U)
90085 /*! DOM_EN
90086  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90087  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90088  *       the masters from the domains specified in [27:24] area.
90089  */
90090 #define SRC_USBPHY2_RCR_DOM_EN(x)                (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOM_EN_SHIFT)) & SRC_USBPHY2_RCR_DOM_EN_MASK)
90091 /*! @} */
90092 
90093 /*! @name MLMIX_RCR - MLMIX Reset Control Register */
90094 /*! @{ */
90095 
90096 #define SRC_MLMIX_RCR_MLMIX_RESET_MASK           (0x1U)
90097 #define SRC_MLMIX_RCR_MLMIX_RESET_SHIFT          (0U)
90098 /*! MLMIX_RESET
90099  *  0b0..Do not assert MLMIX reset
90100  *  0b1..Assert MLMIX reset
90101  */
90102 #define SRC_MLMIX_RCR_MLMIX_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_MLMIX_RESET_SHIFT)) & SRC_MLMIX_RCR_MLMIX_RESET_MASK)
90103 
90104 #define SRC_MLMIX_RCR_DOMAIN0_MASK               (0x1000000U)
90105 #define SRC_MLMIX_RCR_DOMAIN0_SHIFT              (24U)
90106 /*! DOMAIN0
90107  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90108  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90109  */
90110 #define SRC_MLMIX_RCR_DOMAIN0(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN0_SHIFT)) & SRC_MLMIX_RCR_DOMAIN0_MASK)
90111 
90112 #define SRC_MLMIX_RCR_DOMAIN1_MASK               (0x2000000U)
90113 #define SRC_MLMIX_RCR_DOMAIN1_SHIFT              (25U)
90114 /*! DOMAIN1
90115  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90116  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90117  */
90118 #define SRC_MLMIX_RCR_DOMAIN1(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN1_SHIFT)) & SRC_MLMIX_RCR_DOMAIN1_MASK)
90119 
90120 #define SRC_MLMIX_RCR_DOMAIN2_MASK               (0x4000000U)
90121 #define SRC_MLMIX_RCR_DOMAIN2_SHIFT              (26U)
90122 /*! DOMAIN2
90123  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90124  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90125  */
90126 #define SRC_MLMIX_RCR_DOMAIN2(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN2_SHIFT)) & SRC_MLMIX_RCR_DOMAIN2_MASK)
90127 
90128 #define SRC_MLMIX_RCR_DOMAIN3_MASK               (0x8000000U)
90129 #define SRC_MLMIX_RCR_DOMAIN3_SHIFT              (27U)
90130 /*! DOMAIN3
90131  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90132  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90133  */
90134 #define SRC_MLMIX_RCR_DOMAIN3(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN3_SHIFT)) & SRC_MLMIX_RCR_DOMAIN3_MASK)
90135 
90136 #define SRC_MLMIX_RCR_LOCK_MASK                  (0x40000000U)
90137 #define SRC_MLMIX_RCR_LOCK_SHIFT                 (30U)
90138 /*! LOCK
90139  *  0b0..[31] and [27:24] bits can be modified
90140  *  0b1..[31] and [27:24] bits cannot be modified
90141  */
90142 #define SRC_MLMIX_RCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_LOCK_SHIFT)) & SRC_MLMIX_RCR_LOCK_MASK)
90143 
90144 #define SRC_MLMIX_RCR_DOM_EN_MASK                (0x80000000U)
90145 #define SRC_MLMIX_RCR_DOM_EN_SHIFT               (31U)
90146 /*! DOM_EN
90147  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90148  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90149  *       the masters from the domains specified in [27:24] area.
90150  */
90151 #define SRC_MLMIX_RCR_DOM_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOM_EN_SHIFT)) & SRC_MLMIX_RCR_DOM_EN_MASK)
90152 /*! @} */
90153 
90154 /*! @name PCIEPHY_RCR - PCIE PHY Reset Control Register */
90155 /*! @{ */
90156 
90157 #define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_MASK (0x1U)
90158 #define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_SHIFT (0U)
90159 #define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_MASK)
90160 
90161 #define SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_MASK      (0x4U)
90162 #define SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_SHIFT     (2U)
90163 #define SRC_PCIEPHY_RCR_PCIEPHY_BTNRST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_MASK)
90164 
90165 #define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK       (0x8U)
90166 #define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT      (3U)
90167 #define SRC_PCIEPHY_RCR_PCIEPHY_PERST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK)
90168 
90169 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U)
90170 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U)
90171 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK)
90172 
90173 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK  (0x20U)
90174 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U)
90175 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST(x)    (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK)
90176 
90177 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK   (0x40U)
90178 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT  (6U)
90179 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN(x)     (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK)
90180 
90181 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U)
90182 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U)
90183 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY(x)  (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK)
90184 
90185 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U)
90186 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U)
90187 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER(x)  (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK)
90188 
90189 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U)
90190 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U)
90191 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT(x)   (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK)
90192 
90193 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK  (0x400U)
90194 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U)
90195 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME(x)    (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK)
90196 
90197 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U)
90198 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U)
90199 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK)
90200 
90201 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U)
90202 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U)
90203 #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX(x)  (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK)
90204 
90205 #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK   (0x4000U)
90206 #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT  (14U)
90207 #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT(x)     (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK)
90208 
90209 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U)
90210 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U)
90211 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK)
90212 
90213 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U)
90214 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U)
90215 #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK)
90216 
90217 #define SRC_PCIEPHY_RCR_DOMAIN0_MASK             (0x1000000U)
90218 #define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT            (24U)
90219 /*! DOMAIN0
90220  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90221  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90222  */
90223 #define SRC_PCIEPHY_RCR_DOMAIN0(x)               (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN0_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN0_MASK)
90224 
90225 #define SRC_PCIEPHY_RCR_DOMAIN1_MASK             (0x2000000U)
90226 #define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT            (25U)
90227 /*! DOMAIN1
90228  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90229  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90230  */
90231 #define SRC_PCIEPHY_RCR_DOMAIN1(x)               (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN1_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN1_MASK)
90232 
90233 #define SRC_PCIEPHY_RCR_DOMAIN2_MASK             (0x4000000U)
90234 #define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT            (26U)
90235 /*! DOMAIN2
90236  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90237  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90238  */
90239 #define SRC_PCIEPHY_RCR_DOMAIN2(x)               (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN2_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN2_MASK)
90240 
90241 #define SRC_PCIEPHY_RCR_DOMAIN3_MASK             (0x8000000U)
90242 #define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT            (27U)
90243 /*! DOMAIN3
90244  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90245  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90246  */
90247 #define SRC_PCIEPHY_RCR_DOMAIN3(x)               (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN3_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN3_MASK)
90248 
90249 #define SRC_PCIEPHY_RCR_LOCK_MASK                (0x40000000U)
90250 #define SRC_PCIEPHY_RCR_LOCK_SHIFT               (30U)
90251 /*! LOCK
90252  *  0b0..[31] and [27:24] bits can be modified
90253  *  0b1..[31] and [27:24] bits cannot be modified
90254  */
90255 #define SRC_PCIEPHY_RCR_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_LOCK_SHIFT)) & SRC_PCIEPHY_RCR_LOCK_MASK)
90256 
90257 #define SRC_PCIEPHY_RCR_DOM_EN_MASK              (0x80000000U)
90258 #define SRC_PCIEPHY_RCR_DOM_EN_SHIFT             (31U)
90259 /*! DOM_EN
90260  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90261  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90262  *       the masters from the domains specified in [27:24] area.
90263  */
90264 #define SRC_PCIEPHY_RCR_DOM_EN(x)                (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOM_EN_SHIFT)) & SRC_PCIEPHY_RCR_DOM_EN_MASK)
90265 /*! @} */
90266 
90267 /*! @name HDMI_RCR - HDMI Reset Control Register */
90268 /*! @{ */
90269 
90270 #define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK     (0x1U)
90271 #define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT    (0U)
90272 #define SRC_HDMI_RCR_HDMI_PHY_APB_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT)) & SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK)
90273 
90274 #define SRC_HDMI_RCR_DOMAIN0_MASK                (0x1000000U)
90275 #define SRC_HDMI_RCR_DOMAIN0_SHIFT               (24U)
90276 /*! DOMAIN0
90277  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90278  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90279  */
90280 #define SRC_HDMI_RCR_DOMAIN0(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN0_SHIFT)) & SRC_HDMI_RCR_DOMAIN0_MASK)
90281 
90282 #define SRC_HDMI_RCR_DOMAIN1_MASK                (0x2000000U)
90283 #define SRC_HDMI_RCR_DOMAIN1_SHIFT               (25U)
90284 /*! DOMAIN1
90285  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90286  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90287  */
90288 #define SRC_HDMI_RCR_DOMAIN1(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN1_SHIFT)) & SRC_HDMI_RCR_DOMAIN1_MASK)
90289 
90290 #define SRC_HDMI_RCR_DOMAIN2_MASK                (0x4000000U)
90291 #define SRC_HDMI_RCR_DOMAIN2_SHIFT               (26U)
90292 /*! DOMAIN2
90293  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90294  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90295  */
90296 #define SRC_HDMI_RCR_DOMAIN2(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN2_SHIFT)) & SRC_HDMI_RCR_DOMAIN2_MASK)
90297 
90298 #define SRC_HDMI_RCR_DOMAIN3_MASK                (0x8000000U)
90299 #define SRC_HDMI_RCR_DOMAIN3_SHIFT               (27U)
90300 /*! DOMAIN3
90301  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90302  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90303  */
90304 #define SRC_HDMI_RCR_DOMAIN3(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN3_SHIFT)) & SRC_HDMI_RCR_DOMAIN3_MASK)
90305 
90306 #define SRC_HDMI_RCR_LOCK_MASK                   (0x40000000U)
90307 #define SRC_HDMI_RCR_LOCK_SHIFT                  (30U)
90308 /*! LOCK
90309  *  0b0..[31] and [27:24] bits can be modified
90310  *  0b1..[31] and [27:24] bits cannot be modified
90311  */
90312 #define SRC_HDMI_RCR_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_LOCK_SHIFT)) & SRC_HDMI_RCR_LOCK_MASK)
90313 
90314 #define SRC_HDMI_RCR_DOM_EN_MASK                 (0x80000000U)
90315 #define SRC_HDMI_RCR_DOM_EN_SHIFT                (31U)
90316 /*! DOM_EN
90317  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90318  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90319  *       the masters from the domains specified in [27:24] area.
90320  */
90321 #define SRC_HDMI_RCR_DOM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOM_EN_SHIFT)) & SRC_HDMI_RCR_DOM_EN_MASK)
90322 /*! @} */
90323 
90324 /*! @name MEDIA_RCR - MEDIAMIX Reset Control Register */
90325 /*! @{ */
90326 
90327 #define SRC_MEDIA_RCR_MEDIAMIX_RESET_MASK        (0x1U)
90328 #define SRC_MEDIA_RCR_MEDIAMIX_RESET_SHIFT       (0U)
90329 /*! MEDIAMIX_RESET
90330  *  0b0..Don't reset MEDIAMIX
90331  *  0b1..Reset MEDIAMIX
90332  */
90333 #define SRC_MEDIA_RCR_MEDIAMIX_RESET(x)          (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_MEDIAMIX_RESET_SHIFT)) & SRC_MEDIA_RCR_MEDIAMIX_RESET_MASK)
90334 
90335 #define SRC_MEDIA_RCR_DOMAIN0_MASK               (0x1000000U)
90336 #define SRC_MEDIA_RCR_DOMAIN0_SHIFT              (24U)
90337 /*! DOMAIN0
90338  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90339  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90340  */
90341 #define SRC_MEDIA_RCR_DOMAIN0(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN0_SHIFT)) & SRC_MEDIA_RCR_DOMAIN0_MASK)
90342 
90343 #define SRC_MEDIA_RCR_DOMAIN1_MASK               (0x2000000U)
90344 #define SRC_MEDIA_RCR_DOMAIN1_SHIFT              (25U)
90345 /*! DOMAIN1
90346  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90347  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90348  */
90349 #define SRC_MEDIA_RCR_DOMAIN1(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN1_SHIFT)) & SRC_MEDIA_RCR_DOMAIN1_MASK)
90350 
90351 #define SRC_MEDIA_RCR_DOMAIN2_MASK               (0x4000000U)
90352 #define SRC_MEDIA_RCR_DOMAIN2_SHIFT              (26U)
90353 /*! DOMAIN2
90354  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90355  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90356  */
90357 #define SRC_MEDIA_RCR_DOMAIN2(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN2_SHIFT)) & SRC_MEDIA_RCR_DOMAIN2_MASK)
90358 
90359 #define SRC_MEDIA_RCR_DOMAIN3_MASK               (0x8000000U)
90360 #define SRC_MEDIA_RCR_DOMAIN3_SHIFT              (27U)
90361 /*! DOMAIN3
90362  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90363  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90364  */
90365 #define SRC_MEDIA_RCR_DOMAIN3(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN3_SHIFT)) & SRC_MEDIA_RCR_DOMAIN3_MASK)
90366 
90367 #define SRC_MEDIA_RCR_LOCK_MASK                  (0x40000000U)
90368 #define SRC_MEDIA_RCR_LOCK_SHIFT                 (30U)
90369 /*! LOCK
90370  *  0b0..[31] and [27:24] bits can be modified
90371  *  0b1..[31] and [27:24] bits cannot be modified
90372  */
90373 #define SRC_MEDIA_RCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_LOCK_SHIFT)) & SRC_MEDIA_RCR_LOCK_MASK)
90374 
90375 #define SRC_MEDIA_RCR_DOM_EN_MASK                (0x80000000U)
90376 #define SRC_MEDIA_RCR_DOM_EN_SHIFT               (31U)
90377 /*! DOM_EN
90378  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90379  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90380  *       the masters from the domains specified in [27:24] area.
90381  */
90382 #define SRC_MEDIA_RCR_DOM_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOM_EN_SHIFT)) & SRC_MEDIA_RCR_DOM_EN_MASK)
90383 /*! @} */
90384 
90385 /*! @name GPU2D_RCR - GPU2D Reset Control Register */
90386 /*! @{ */
90387 
90388 #define SRC_GPU2D_RCR_GPU2D_RESET_MASK           (0x1U)
90389 #define SRC_GPU2D_RCR_GPU2D_RESET_SHIFT          (0U)
90390 #define SRC_GPU2D_RCR_GPU2D_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_GPU2D_RESET_SHIFT)) & SRC_GPU2D_RCR_GPU2D_RESET_MASK)
90391 
90392 #define SRC_GPU2D_RCR_DOMAIN0_MASK               (0x1000000U)
90393 #define SRC_GPU2D_RCR_DOMAIN0_SHIFT              (24U)
90394 /*! DOMAIN0
90395  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90396  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90397  */
90398 #define SRC_GPU2D_RCR_DOMAIN0(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN0_SHIFT)) & SRC_GPU2D_RCR_DOMAIN0_MASK)
90399 
90400 #define SRC_GPU2D_RCR_DOMAIN1_MASK               (0x2000000U)
90401 #define SRC_GPU2D_RCR_DOMAIN1_SHIFT              (25U)
90402 /*! DOMAIN1
90403  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90404  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90405  */
90406 #define SRC_GPU2D_RCR_DOMAIN1(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN1_SHIFT)) & SRC_GPU2D_RCR_DOMAIN1_MASK)
90407 
90408 #define SRC_GPU2D_RCR_DOMAIN2_MASK               (0x4000000U)
90409 #define SRC_GPU2D_RCR_DOMAIN2_SHIFT              (26U)
90410 /*! DOMAIN2
90411  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90412  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90413  */
90414 #define SRC_GPU2D_RCR_DOMAIN2(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN2_SHIFT)) & SRC_GPU2D_RCR_DOMAIN2_MASK)
90415 
90416 #define SRC_GPU2D_RCR_DOMAIN3_MASK               (0x8000000U)
90417 #define SRC_GPU2D_RCR_DOMAIN3_SHIFT              (27U)
90418 /*! DOMAIN3
90419  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90420  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90421  */
90422 #define SRC_GPU2D_RCR_DOMAIN3(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN3_SHIFT)) & SRC_GPU2D_RCR_DOMAIN3_MASK)
90423 
90424 #define SRC_GPU2D_RCR_LOCK_MASK                  (0x40000000U)
90425 #define SRC_GPU2D_RCR_LOCK_SHIFT                 (30U)
90426 /*! LOCK
90427  *  0b0..[31] and [27:24] bits can be modified
90428  *  0b1..[31] and [27:24] bits cannot be modified
90429  */
90430 #define SRC_GPU2D_RCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_LOCK_SHIFT)) & SRC_GPU2D_RCR_LOCK_MASK)
90431 
90432 #define SRC_GPU2D_RCR_DOM_EN_MASK                (0x80000000U)
90433 #define SRC_GPU2D_RCR_DOM_EN_SHIFT               (31U)
90434 /*! DOM_EN
90435  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90436  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90437  *       the masters from the domains specified in [27:24] area.
90438  */
90439 #define SRC_GPU2D_RCR_DOM_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOM_EN_SHIFT)) & SRC_GPU2D_RCR_DOM_EN_MASK)
90440 /*! @} */
90441 
90442 /*! @name GPU3D_RCR - GPU3D Reset Control Register */
90443 /*! @{ */
90444 
90445 #define SRC_GPU3D_RCR_GPU3D_RESET_MASK           (0x1U)
90446 #define SRC_GPU3D_RCR_GPU3D_RESET_SHIFT          (0U)
90447 #define SRC_GPU3D_RCR_GPU3D_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_GPU3D_RESET_SHIFT)) & SRC_GPU3D_RCR_GPU3D_RESET_MASK)
90448 
90449 #define SRC_GPU3D_RCR_DOMAIN0_MASK               (0x1000000U)
90450 #define SRC_GPU3D_RCR_DOMAIN0_SHIFT              (24U)
90451 /*! DOMAIN0
90452  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90453  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90454  */
90455 #define SRC_GPU3D_RCR_DOMAIN0(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN0_SHIFT)) & SRC_GPU3D_RCR_DOMAIN0_MASK)
90456 
90457 #define SRC_GPU3D_RCR_DOMAIN1_MASK               (0x2000000U)
90458 #define SRC_GPU3D_RCR_DOMAIN1_SHIFT              (25U)
90459 /*! DOMAIN1
90460  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90461  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90462  */
90463 #define SRC_GPU3D_RCR_DOMAIN1(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN1_SHIFT)) & SRC_GPU3D_RCR_DOMAIN1_MASK)
90464 
90465 #define SRC_GPU3D_RCR_DOMAIN2_MASK               (0x4000000U)
90466 #define SRC_GPU3D_RCR_DOMAIN2_SHIFT              (26U)
90467 /*! DOMAIN2
90468  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90469  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90470  */
90471 #define SRC_GPU3D_RCR_DOMAIN2(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN2_SHIFT)) & SRC_GPU3D_RCR_DOMAIN2_MASK)
90472 
90473 #define SRC_GPU3D_RCR_DOMAIN3_MASK               (0x8000000U)
90474 #define SRC_GPU3D_RCR_DOMAIN3_SHIFT              (27U)
90475 /*! DOMAIN3
90476  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90477  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90478  */
90479 #define SRC_GPU3D_RCR_DOMAIN3(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN3_SHIFT)) & SRC_GPU3D_RCR_DOMAIN3_MASK)
90480 
90481 #define SRC_GPU3D_RCR_LOCK_MASK                  (0x40000000U)
90482 #define SRC_GPU3D_RCR_LOCK_SHIFT                 (30U)
90483 /*! LOCK
90484  *  0b0..[31] and [27:24] bits can be modified
90485  *  0b1..[31] and [27:24] bits cannot be modified
90486  */
90487 #define SRC_GPU3D_RCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_LOCK_SHIFT)) & SRC_GPU3D_RCR_LOCK_MASK)
90488 
90489 #define SRC_GPU3D_RCR_DOM_EN_MASK                (0x80000000U)
90490 #define SRC_GPU3D_RCR_DOM_EN_SHIFT               (31U)
90491 /*! DOM_EN
90492  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90493  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90494  *       the masters from the domains specified in [27:24] area.
90495  */
90496 #define SRC_GPU3D_RCR_DOM_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOM_EN_SHIFT)) & SRC_GPU3D_RCR_DOM_EN_MASK)
90497 /*! @} */
90498 
90499 /*! @name GPU_RCR - GPU Reset Control Register */
90500 /*! @{ */
90501 
90502 #define SRC_GPU_RCR_GPU_RESET_MASK               (0x1U)
90503 #define SRC_GPU_RCR_GPU_RESET_SHIFT              (0U)
90504 #define SRC_GPU_RCR_GPU_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK)
90505 
90506 #define SRC_GPU_RCR_DOMAIN0_MASK                 (0x1000000U)
90507 #define SRC_GPU_RCR_DOMAIN0_SHIFT                (24U)
90508 /*! DOMAIN0
90509  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90510  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90511  */
90512 #define SRC_GPU_RCR_DOMAIN0(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK)
90513 
90514 #define SRC_GPU_RCR_DOMAIN1_MASK                 (0x2000000U)
90515 #define SRC_GPU_RCR_DOMAIN1_SHIFT                (25U)
90516 /*! DOMAIN1
90517  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90518  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90519  */
90520 #define SRC_GPU_RCR_DOMAIN1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK)
90521 
90522 #define SRC_GPU_RCR_DOMAIN2_MASK                 (0x4000000U)
90523 #define SRC_GPU_RCR_DOMAIN2_SHIFT                (26U)
90524 /*! DOMAIN2
90525  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90526  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90527  */
90528 #define SRC_GPU_RCR_DOMAIN2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK)
90529 
90530 #define SRC_GPU_RCR_DOMAIN3_MASK                 (0x8000000U)
90531 #define SRC_GPU_RCR_DOMAIN3_SHIFT                (27U)
90532 /*! DOMAIN3
90533  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90534  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90535  */
90536 #define SRC_GPU_RCR_DOMAIN3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK)
90537 
90538 #define SRC_GPU_RCR_LOCK_MASK                    (0x40000000U)
90539 #define SRC_GPU_RCR_LOCK_SHIFT                   (30U)
90540 /*! LOCK
90541  *  0b0..[31] and [27:24] bits can be modified
90542  *  0b1..[31] and [27:24] bits cannot be modified
90543  */
90544 #define SRC_GPU_RCR_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK)
90545 
90546 #define SRC_GPU_RCR_DOM_EN_MASK                  (0x80000000U)
90547 #define SRC_GPU_RCR_DOM_EN_SHIFT                 (31U)
90548 /*! DOM_EN
90549  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90550  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90551  *       the masters from the domains specified in [27:24] area.
90552  */
90553 #define SRC_GPU_RCR_DOM_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK)
90554 /*! @} */
90555 
90556 /*! @name VPU_RCR - VPU Reset Control Register */
90557 /*! @{ */
90558 
90559 #define SRC_VPU_RCR_VPU_RESET_MASK               (0x1U)
90560 #define SRC_VPU_RCR_VPU_RESET_SHIFT              (0U)
90561 #define SRC_VPU_RCR_VPU_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_VPU_RESET_SHIFT)) & SRC_VPU_RCR_VPU_RESET_MASK)
90562 
90563 #define SRC_VPU_RCR_DOMAIN0_MASK                 (0x1000000U)
90564 #define SRC_VPU_RCR_DOMAIN0_SHIFT                (24U)
90565 /*! DOMAIN0
90566  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90567  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90568  */
90569 #define SRC_VPU_RCR_DOMAIN0(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN0_SHIFT)) & SRC_VPU_RCR_DOMAIN0_MASK)
90570 
90571 #define SRC_VPU_RCR_DOMAIN1_MASK                 (0x2000000U)
90572 #define SRC_VPU_RCR_DOMAIN1_SHIFT                (25U)
90573 /*! DOMAIN1
90574  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90575  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90576  */
90577 #define SRC_VPU_RCR_DOMAIN1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN1_SHIFT)) & SRC_VPU_RCR_DOMAIN1_MASK)
90578 
90579 #define SRC_VPU_RCR_DOMAIN2_MASK                 (0x4000000U)
90580 #define SRC_VPU_RCR_DOMAIN2_SHIFT                (26U)
90581 /*! DOMAIN2
90582  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90583  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90584  */
90585 #define SRC_VPU_RCR_DOMAIN2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN2_SHIFT)) & SRC_VPU_RCR_DOMAIN2_MASK)
90586 
90587 #define SRC_VPU_RCR_DOMAIN3_MASK                 (0x8000000U)
90588 #define SRC_VPU_RCR_DOMAIN3_SHIFT                (27U)
90589 /*! DOMAIN3
90590  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90591  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90592  */
90593 #define SRC_VPU_RCR_DOMAIN3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN3_SHIFT)) & SRC_VPU_RCR_DOMAIN3_MASK)
90594 
90595 #define SRC_VPU_RCR_LOCK_MASK                    (0x40000000U)
90596 #define SRC_VPU_RCR_LOCK_SHIFT                   (30U)
90597 /*! LOCK
90598  *  0b0..[31] and [27:24] bits can be modified
90599  *  0b1..[31] and [27:24] bits cannot be modified
90600  */
90601 #define SRC_VPU_RCR_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_LOCK_SHIFT)) & SRC_VPU_RCR_LOCK_MASK)
90602 
90603 #define SRC_VPU_RCR_DOM_EN_MASK                  (0x80000000U)
90604 #define SRC_VPU_RCR_DOM_EN_SHIFT                 (31U)
90605 /*! DOM_EN
90606  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90607  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90608  *       the masters from the domains specified in [27:24] area.
90609  */
90610 #define SRC_VPU_RCR_DOM_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOM_EN_SHIFT)) & SRC_VPU_RCR_DOM_EN_MASK)
90611 /*! @} */
90612 
90613 /*! @name VPU_G1_RCR - VPU G1 Reset Control Register */
90614 /*! @{ */
90615 
90616 #define SRC_VPU_G1_RCR_VPU_G1_RESET_MASK         (0x1U)
90617 #define SRC_VPU_G1_RCR_VPU_G1_RESET_SHIFT        (0U)
90618 #define SRC_VPU_G1_RCR_VPU_G1_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_VPU_G1_RESET_SHIFT)) & SRC_VPU_G1_RCR_VPU_G1_RESET_MASK)
90619 
90620 #define SRC_VPU_G1_RCR_DOMAIN0_MASK              (0x1000000U)
90621 #define SRC_VPU_G1_RCR_DOMAIN0_SHIFT             (24U)
90622 /*! DOMAIN0
90623  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90624  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90625  */
90626 #define SRC_VPU_G1_RCR_DOMAIN0(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN0_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN0_MASK)
90627 
90628 #define SRC_VPU_G1_RCR_DOMAIN1_MASK              (0x2000000U)
90629 #define SRC_VPU_G1_RCR_DOMAIN1_SHIFT             (25U)
90630 /*! DOMAIN1
90631  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90632  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90633  */
90634 #define SRC_VPU_G1_RCR_DOMAIN1(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN1_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN1_MASK)
90635 
90636 #define SRC_VPU_G1_RCR_DOMAIN2_MASK              (0x4000000U)
90637 #define SRC_VPU_G1_RCR_DOMAIN2_SHIFT             (26U)
90638 /*! DOMAIN2
90639  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90640  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90641  */
90642 #define SRC_VPU_G1_RCR_DOMAIN2(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN2_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN2_MASK)
90643 
90644 #define SRC_VPU_G1_RCR_DOMAIN3_MASK              (0x8000000U)
90645 #define SRC_VPU_G1_RCR_DOMAIN3_SHIFT             (27U)
90646 /*! DOMAIN3
90647  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90648  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90649  */
90650 #define SRC_VPU_G1_RCR_DOMAIN3(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN3_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN3_MASK)
90651 
90652 #define SRC_VPU_G1_RCR_LOCK_MASK                 (0x40000000U)
90653 #define SRC_VPU_G1_RCR_LOCK_SHIFT                (30U)
90654 /*! LOCK
90655  *  0b0..[31] and [27:24] bits can be modified
90656  *  0b1..[31] and [27:24] bits cannot be modified
90657  */
90658 #define SRC_VPU_G1_RCR_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_LOCK_SHIFT)) & SRC_VPU_G1_RCR_LOCK_MASK)
90659 
90660 #define SRC_VPU_G1_RCR_DOM_EN_MASK               (0x80000000U)
90661 #define SRC_VPU_G1_RCR_DOM_EN_SHIFT              (31U)
90662 /*! DOM_EN
90663  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90664  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90665  *       the masters from the domains specified in [27:24] area.
90666  */
90667 #define SRC_VPU_G1_RCR_DOM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOM_EN_SHIFT)) & SRC_VPU_G1_RCR_DOM_EN_MASK)
90668 /*! @} */
90669 
90670 /*! @name VPU_G2_RCR - VPU G2 Reset Control Register */
90671 /*! @{ */
90672 
90673 #define SRC_VPU_G2_RCR_VPU_G2_RESET_MASK         (0x1U)
90674 #define SRC_VPU_G2_RCR_VPU_G2_RESET_SHIFT        (0U)
90675 #define SRC_VPU_G2_RCR_VPU_G2_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_VPU_G2_RESET_SHIFT)) & SRC_VPU_G2_RCR_VPU_G2_RESET_MASK)
90676 
90677 #define SRC_VPU_G2_RCR_DOMAIN0_MASK              (0x1000000U)
90678 #define SRC_VPU_G2_RCR_DOMAIN0_SHIFT             (24U)
90679 /*! DOMAIN0
90680  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90681  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90682  */
90683 #define SRC_VPU_G2_RCR_DOMAIN0(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN0_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN0_MASK)
90684 
90685 #define SRC_VPU_G2_RCR_DOMAIN1_MASK              (0x2000000U)
90686 #define SRC_VPU_G2_RCR_DOMAIN1_SHIFT             (25U)
90687 /*! DOMAIN1
90688  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90689  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90690  */
90691 #define SRC_VPU_G2_RCR_DOMAIN1(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN1_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN1_MASK)
90692 
90693 #define SRC_VPU_G2_RCR_DOMAIN2_MASK              (0x4000000U)
90694 #define SRC_VPU_G2_RCR_DOMAIN2_SHIFT             (26U)
90695 /*! DOMAIN2
90696  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90697  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90698  */
90699 #define SRC_VPU_G2_RCR_DOMAIN2(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN2_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN2_MASK)
90700 
90701 #define SRC_VPU_G2_RCR_DOMAIN3_MASK              (0x8000000U)
90702 #define SRC_VPU_G2_RCR_DOMAIN3_SHIFT             (27U)
90703 /*! DOMAIN3
90704  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90705  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90706  */
90707 #define SRC_VPU_G2_RCR_DOMAIN3(x)                (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN3_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN3_MASK)
90708 
90709 #define SRC_VPU_G2_RCR_LOCK_MASK                 (0x40000000U)
90710 #define SRC_VPU_G2_RCR_LOCK_SHIFT                (30U)
90711 /*! LOCK
90712  *  0b0..[31] and [27:24] bits can be modified
90713  *  0b1..[31] and [27:24] bits cannot be modified
90714  */
90715 #define SRC_VPU_G2_RCR_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_LOCK_SHIFT)) & SRC_VPU_G2_RCR_LOCK_MASK)
90716 
90717 #define SRC_VPU_G2_RCR_DOM_EN_MASK               (0x80000000U)
90718 #define SRC_VPU_G2_RCR_DOM_EN_SHIFT              (31U)
90719 /*! DOM_EN
90720  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90721  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90722  *       the masters from the domains specified in [27:24] area.
90723  */
90724 #define SRC_VPU_G2_RCR_DOM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOM_EN_SHIFT)) & SRC_VPU_G2_RCR_DOM_EN_MASK)
90725 /*! @} */
90726 
90727 /*! @name VPUVC8KE_RCR - VPU VC8000E Reset Control Register */
90728 /*! @{ */
90729 
90730 #define SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_MASK (0x1U)
90731 #define SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_SHIFT (0U)
90732 #define SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET(x)   (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_SHIFT)) & SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_MASK)
90733 
90734 #define SRC_VPUVC8KE_RCR_DOMAIN0_MASK            (0x1000000U)
90735 #define SRC_VPUVC8KE_RCR_DOMAIN0_SHIFT           (24U)
90736 /*! DOMAIN0
90737  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90738  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90739  */
90740 #define SRC_VPUVC8KE_RCR_DOMAIN0(x)              (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN0_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN0_MASK)
90741 
90742 #define SRC_VPUVC8KE_RCR_DOMAIN1_MASK            (0x2000000U)
90743 #define SRC_VPUVC8KE_RCR_DOMAIN1_SHIFT           (25U)
90744 /*! DOMAIN1
90745  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90746  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90747  */
90748 #define SRC_VPUVC8KE_RCR_DOMAIN1(x)              (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN1_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN1_MASK)
90749 
90750 #define SRC_VPUVC8KE_RCR_DOMAIN2_MASK            (0x4000000U)
90751 #define SRC_VPUVC8KE_RCR_DOMAIN2_SHIFT           (26U)
90752 /*! DOMAIN2
90753  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90754  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90755  */
90756 #define SRC_VPUVC8KE_RCR_DOMAIN2(x)              (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN2_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN2_MASK)
90757 
90758 #define SRC_VPUVC8KE_RCR_DOMAIN3_MASK            (0x8000000U)
90759 #define SRC_VPUVC8KE_RCR_DOMAIN3_SHIFT           (27U)
90760 /*! DOMAIN3
90761  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90762  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90763  */
90764 #define SRC_VPUVC8KE_RCR_DOMAIN3(x)              (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN3_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN3_MASK)
90765 
90766 #define SRC_VPUVC8KE_RCR_LOCK_MASK               (0x40000000U)
90767 #define SRC_VPUVC8KE_RCR_LOCK_SHIFT              (30U)
90768 /*! LOCK
90769  *  0b0..[31] and [27:24] bits can be modified
90770  *  0b1..[31] and [27:24] bits cannot be modified
90771  */
90772 #define SRC_VPUVC8KE_RCR_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_LOCK_SHIFT)) & SRC_VPUVC8KE_RCR_LOCK_MASK)
90773 
90774 #define SRC_VPUVC8KE_RCR_DOM_EN_MASK             (0x80000000U)
90775 #define SRC_VPUVC8KE_RCR_DOM_EN_SHIFT            (31U)
90776 /*! DOM_EN
90777  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90778  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90779  *       the masters from the domains specified in [27:24] area.
90780  */
90781 #define SRC_VPUVC8KE_RCR_DOM_EN(x)               (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOM_EN_SHIFT)) & SRC_VPUVC8KE_RCR_DOM_EN_MASK)
90782 /*! @} */
90783 
90784 /*! @name NOC_RCR - NOC Wrapper Reset Control Register */
90785 /*! @{ */
90786 
90787 #define SRC_NOC_RCR_NOC_RESET_MASK               (0x1U)
90788 #define SRC_NOC_RCR_NOC_RESET_SHIFT              (0U)
90789 #define SRC_NOC_RCR_NOC_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_NOC_RESET_SHIFT)) & SRC_NOC_RCR_NOC_RESET_MASK)
90790 
90791 #define SRC_NOC_RCR_DOMAIN0_MASK                 (0x1000000U)
90792 #define SRC_NOC_RCR_DOMAIN0_SHIFT                (24U)
90793 /*! DOMAIN0
90794  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
90795  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
90796  */
90797 #define SRC_NOC_RCR_DOMAIN0(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN0_SHIFT)) & SRC_NOC_RCR_DOMAIN0_MASK)
90798 
90799 #define SRC_NOC_RCR_DOMAIN1_MASK                 (0x2000000U)
90800 #define SRC_NOC_RCR_DOMAIN1_SHIFT                (25U)
90801 /*! DOMAIN1
90802  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
90803  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
90804  */
90805 #define SRC_NOC_RCR_DOMAIN1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN1_SHIFT)) & SRC_NOC_RCR_DOMAIN1_MASK)
90806 
90807 #define SRC_NOC_RCR_DOMAIN2_MASK                 (0x4000000U)
90808 #define SRC_NOC_RCR_DOMAIN2_SHIFT                (26U)
90809 /*! DOMAIN2
90810  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
90811  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
90812  */
90813 #define SRC_NOC_RCR_DOMAIN2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN2_SHIFT)) & SRC_NOC_RCR_DOMAIN2_MASK)
90814 
90815 #define SRC_NOC_RCR_DOMAIN3_MASK                 (0x8000000U)
90816 #define SRC_NOC_RCR_DOMAIN3_SHIFT                (27U)
90817 /*! DOMAIN3
90818  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
90819  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
90820  */
90821 #define SRC_NOC_RCR_DOMAIN3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN3_SHIFT)) & SRC_NOC_RCR_DOMAIN3_MASK)
90822 
90823 #define SRC_NOC_RCR_LOCK_MASK                    (0x40000000U)
90824 #define SRC_NOC_RCR_LOCK_SHIFT                   (30U)
90825 /*! LOCK
90826  *  0b0..[31] and [27:24] bits can be modified
90827  *  0b1..[31] and [27:24] bits cannot be modified
90828  */
90829 #define SRC_NOC_RCR_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_LOCK_SHIFT)) & SRC_NOC_RCR_LOCK_MASK)
90830 
90831 #define SRC_NOC_RCR_DOM_EN_MASK                  (0x80000000U)
90832 #define SRC_NOC_RCR_DOM_EN_SHIFT                 (31U)
90833 /*! DOM_EN
90834  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
90835  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
90836  *       the masters from the domains specified in [27:24] area.
90837  */
90838 #define SRC_NOC_RCR_DOM_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOM_EN_SHIFT)) & SRC_NOC_RCR_DOM_EN_MASK)
90839 /*! @} */
90840 
90841 /*! @name SBMR1 - SRC Boot Mode Register 1 */
90842 /*! @{ */
90843 
90844 #define SRC_SBMR1_BOOT_CFG_MASK                  (0xFFFFFU)
90845 #define SRC_SBMR1_BOOT_CFG_SHIFT                 (0U)
90846 #define SRC_SBMR1_BOOT_CFG(x)                    (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK)
90847 /*! @} */
90848 
90849 /*! @name SRSR - SRC Reset Status Register */
90850 /*! @{ */
90851 
90852 #define SRC_SRSR_ipp_reset_b_MASK                (0x1U)
90853 #define SRC_SRSR_ipp_reset_b_SHIFT               (0U)
90854 /*! ipp_reset_b
90855  *  0b0..Reset is not a result of ipp_reset_b pin.
90856  *  0b1..Reset is a result of ipp_reset_b pin.
90857  */
90858 #define SRC_SRSR_ipp_reset_b(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_reset_b_SHIFT)) & SRC_SRSR_ipp_reset_b_MASK)
90859 
90860 #define SRC_SRSR_csu_reset_b_MASK                (0x4U)
90861 #define SRC_SRSR_csu_reset_b_SHIFT               (2U)
90862 /*! csu_reset_b
90863  *  0b0..Reset is not a result of the csu_reset_b event.
90864  *  0b1..Reset is a result of the csu_reset_b event.
90865  */
90866 #define SRC_SRSR_csu_reset_b(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_csu_reset_b_SHIFT)) & SRC_SRSR_csu_reset_b_MASK)
90867 
90868 #define SRC_SRSR_ipp_user_reset_b_MASK           (0x8U)
90869 #define SRC_SRSR_ipp_user_reset_b_SHIFT          (3U)
90870 /*! ipp_user_reset_b
90871  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
90872  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
90873  */
90874 #define SRC_SRSR_ipp_user_reset_b(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_user_reset_b_SHIFT)) & SRC_SRSR_ipp_user_reset_b_MASK)
90875 
90876 #define SRC_SRSR_wdog1_rst_b_MASK                (0x10U)
90877 #define SRC_SRSR_wdog1_rst_b_SHIFT               (4U)
90878 /*! wdog1_rst_b
90879  *  0b0..Reset is not a result of the watchdog1 time-out event.
90880  *  0b1..Reset is a result of the watchdog1 time-out event.
90881  */
90882 #define SRC_SRSR_wdog1_rst_b(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog1_rst_b_SHIFT)) & SRC_SRSR_wdog1_rst_b_MASK)
90883 
90884 #define SRC_SRSR_jtag_rst_b_MASK                 (0x20U)
90885 #define SRC_SRSR_jtag_rst_b_SHIFT                (5U)
90886 /*! jtag_rst_b
90887  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
90888  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
90889  */
90890 #define SRC_SRSR_jtag_rst_b(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_rst_b_SHIFT)) & SRC_SRSR_jtag_rst_b_MASK)
90891 
90892 #define SRC_SRSR_jtag_sw_rst_MASK                (0x40U)
90893 #define SRC_SRSR_jtag_sw_rst_SHIFT               (6U)
90894 /*! jtag_sw_rst
90895  *  0b0..Reset is not a result of software reset from JTAG.
90896  *  0b1..Reset is a result of software reset from JTAG.
90897  */
90898 #define SRC_SRSR_jtag_sw_rst(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_sw_rst_SHIFT)) & SRC_SRSR_jtag_sw_rst_MASK)
90899 
90900 #define SRC_SRSR_wdog3_rst_b_MASK                (0x80U)
90901 #define SRC_SRSR_wdog3_rst_b_SHIFT               (7U)
90902 /*! wdog3_rst_b
90903  *  0b0..Reset is not a result of the watchdog3 time-out event.
90904  *  0b1..Reset is a result of the watchdog3 time-out event.
90905  */
90906 #define SRC_SRSR_wdog3_rst_b(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog3_rst_b_SHIFT)) & SRC_SRSR_wdog3_rst_b_MASK)
90907 
90908 #define SRC_SRSR_wdog2_rst_b_MASK                (0x100U)
90909 #define SRC_SRSR_wdog2_rst_b_SHIFT               (8U)
90910 /*! wdog2_rst_b
90911  *  0b0..Reset is not a result of the watchdog4 time-out event.
90912  *  0b1..Reset is a result of the watchdog4 time-out event.
90913  */
90914 #define SRC_SRSR_wdog2_rst_b(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog2_rst_b_SHIFT)) & SRC_SRSR_wdog2_rst_b_MASK)
90915 
90916 #define SRC_SRSR_tempsense_rst_b_MASK            (0x200U)
90917 #define SRC_SRSR_tempsense_rst_b_SHIFT           (9U)
90918 /*! tempsense_rst_b
90919  *  0b0..Reset is not a result of software reset from Temperature Sensor.
90920  *  0b1..Reset is a result of software reset from Temperature Sensor.
90921  */
90922 #define SRC_SRSR_tempsense_rst_b(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_tempsense_rst_b_SHIFT)) & SRC_SRSR_tempsense_rst_b_MASK)
90923 /*! @} */
90924 
90925 /*! @name SISR - SRC Interrupt Status Register */
90926 /*! @{ */
90927 
90928 #define SRC_SISR_USBPHY1_PASSED_RESET_MASK       (0x4U)
90929 #define SRC_SISR_USBPHY1_PASSED_RESET_SHIFT      (2U)
90930 /*! USBPHY1_PASSED_RESET
90931  *  0b0..Interrupt generated not due to USB PHY1 passed reset
90932  *  0b1..Interrupt generated due to USB PHY1 passed reset
90933  */
90934 #define SRC_SISR_USBPHY1_PASSED_RESET(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SISR_USBPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_USBPHY1_PASSED_RESET_MASK)
90935 
90936 #define SRC_SISR_USBPHY2_PASSED_RESET_MASK       (0x8U)
90937 #define SRC_SISR_USBPHY2_PASSED_RESET_SHIFT      (3U)
90938 /*! USBPHY2_PASSED_RESET
90939  *  0b0..Interrupt generated not due to USB PHY2 passed reset
90940  *  0b1..Interrupt generated due to USB PHY2 passed reset
90941  */
90942 #define SRC_SISR_USBPHY2_PASSED_RESET(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SISR_USBPHY2_PASSED_RESET_SHIFT)) & SRC_SISR_USBPHY2_PASSED_RESET_MASK)
90943 
90944 #define SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK     (0x20U)
90945 #define SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT    (5U)
90946 /*! PCIE1_PHY_PASSED_RESET
90947  *  0b0..Interrupt generated not due to PCIE1 PHY passed reset
90948  *  0b1..Interrupt generated due to PCIE1 PHY passed reset
90949  */
90950 #define SRC_SISR_PCIE1_PHY_PASSED_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK)
90951 
90952 #define SRC_SISR_DISPLAY_PASSED_RESET_MASK       (0x80U)
90953 #define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT      (7U)
90954 /*! DISPLAY_PASSED_RESET
90955  *  0b0..Interrupt generated not due to DISPLAY passed reset
90956  *  0b1..Interrupt generated due to DISPLAY passed reset
90957  */
90958 #define SRC_SISR_DISPLAY_PASSED_RESET(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK)
90959 
90960 #define SRC_SISR_M7C_PASSED_RESET_MASK           (0x100U)
90961 #define SRC_SISR_M7C_PASSED_RESET_SHIFT          (8U)
90962 /*! M7C_PASSED_RESET
90963  *  0b0..interrupt generated not due to m7core reset
90964  *  0b1..interrupt generated due to m7core reset
90965  */
90966 #define SRC_SISR_M7C_PASSED_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M7C_PASSED_RESET_SHIFT)) & SRC_SISR_M7C_PASSED_RESET_MASK)
90967 
90968 #define SRC_SISR_M7P_PASSED_RESET_MASK           (0x200U)
90969 #define SRC_SISR_M7P_PASSED_RESET_SHIFT          (9U)
90970 /*! M7P_PASSED_RESET
90971  *  0b0..interrupt generated not due to m7 platform reset
90972  *  0b1..interrupt generated due to m7 platform reset
90973  */
90974 #define SRC_SISR_M7P_PASSED_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M7P_PASSED_RESET_SHIFT)) & SRC_SISR_M7P_PASSED_RESET_MASK)
90975 
90976 #define SRC_SISR_GPU_PASSED_RESET_MASK           (0x400U)
90977 #define SRC_SISR_GPU_PASSED_RESET_SHIFT          (10U)
90978 /*! GPU_PASSED_RESET
90979  *  0b0..interrupt generated not due to GPU reset
90980  *  0b1..interrupt generated due to GPU reset
90981  */
90982 #define SRC_SISR_GPU_PASSED_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK)
90983 
90984 #define SRC_SISR_VPU_PASSED_RESET_MASK           (0x800U)
90985 #define SRC_SISR_VPU_PASSED_RESET_SHIFT          (11U)
90986 /*! VPU_PASSED_RESET
90987  *  0b0..interrupt generated not due to VPU reset
90988  *  0b1..interrupt generated due to VPU reset
90989  */
90990 #define SRC_SISR_VPU_PASSED_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SISR_VPU_PASSED_RESET_SHIFT)) & SRC_SISR_VPU_PASSED_RESET_MASK)
90991 /*! @} */
90992 
90993 /*! @name SIMR - SRC Interrupt Mask Register */
90994 /*! @{ */
90995 
90996 #define SRC_SIMR_MASK_USBPHY1_PASSED_RESET_MASK  (0x4U)
90997 #define SRC_SIMR_MASK_USBPHY1_PASSED_RESET_SHIFT (2U)
90998 /*! MASK_USBPHY1_PASSED_RESET
90999  *  0b0..do not mask interrupt due to USB PHY1 passed reset - interrupt will be created
91000  *  0b1..mask interrupt due to USB PHY1 passed reset
91001  */
91002 #define SRC_SIMR_MASK_USBPHY1_PASSED_RESET(x)    (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_USBPHY1_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_USBPHY1_PASSED_RESET_MASK)
91003 
91004 #define SRC_SIMR_MASK_USBPHY2_PASSED_RESET_MASK  (0x8U)
91005 #define SRC_SIMR_MASK_USBPHY2_PASSED_RESET_SHIFT (3U)
91006 /*! MASK_USBPHY2_PASSED_RESET
91007  *  0b0..do not mask interrupt due to USB PHY2 passed reset - interrupt will be created
91008  *  0b1..mask interrupt due to USB PHY2 passed reset
91009  */
91010 #define SRC_SIMR_MASK_USBPHY2_PASSED_RESET(x)    (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_USBPHY2_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_USBPHY2_PASSED_RESET_MASK)
91011 
91012 #define SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_MASK (0x20U)
91013 #define SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_SHIFT (5U)
91014 /*! MASK_PCIE_PHY_PASSED_RESET
91015  *  0b0..do not mask interrupt due to PCIE PHY passed reset - interrupt will be created
91016  *  0b1..mask interrupt due to PCIE PHY passed reset
91017  */
91018 #define SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET(x)   (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_MASK)
91019 
91020 #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK  (0x80U)
91021 #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U)
91022 /*! MASK_DISPLAY_PASSED_RESET
91023  *  0b0..do not mask interrupt due to display passed reset - interrupt will be created
91024  *  0b1..mask interrupt due to display passed reset
91025  */
91026 #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x)    (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK)
91027 
91028 #define SRC_SIMR_MASK_M7C_PASSED_RESET_MASK      (0x100U)
91029 #define SRC_SIMR_MASK_M7C_PASSED_RESET_SHIFT     (8U)
91030 /*! MASK_M7C_PASSED_RESET
91031  *  0b0..do not mask interrupt due to m7 core passed reset - interrupt will be created
91032  *  0b1..mask interrupt due to m7 core passed reset
91033  */
91034 #define SRC_SIMR_MASK_M7C_PASSED_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M7C_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M7C_PASSED_RESET_MASK)
91035 
91036 #define SRC_SIMR_MASK_M7P_PASSED_RESET_MASK      (0x200U)
91037 #define SRC_SIMR_MASK_M7P_PASSED_RESET_SHIFT     (9U)
91038 /*! MASK_M7P_PASSED_RESET
91039  *  0b0..do not mask interrupt due to m7 platform passed reset - interrupt will be created
91040  *  0b1..mask interrupt due to m7 platform passed reset
91041  */
91042 #define SRC_SIMR_MASK_M7P_PASSED_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M7P_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M7P_PASSED_RESET_MASK)
91043 
91044 #define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK      (0x400U)
91045 #define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT     (10U)
91046 /*! MASK_GPU_PASSED_RESET
91047  *  0b0..do not mask interrupt due to GPU passed reset - interrupt will be created
91048  *  0b1..mask interrupt due to GPU passed reset
91049  */
91050 #define SRC_SIMR_MASK_GPU_PASSED_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK)
91051 
91052 #define SRC_SIMR_MASK_VPU_PASSED_RESET_MASK      (0x800U)
91053 #define SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT     (11U)
91054 /*! MASK_VPU_PASSED_RESET
91055  *  0b0..do not mask interrupt due to VPU passed reset - interrupt will be created
91056  *  0b1..mask interrupt due to VPU passed reset
91057  */
91058 #define SRC_SIMR_MASK_VPU_PASSED_RESET(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_VPU_PASSED_RESET_MASK)
91059 /*! @} */
91060 
91061 /*! @name SBMR2 - SRC Boot Mode Register 2 */
91062 /*! @{ */
91063 
91064 #define SRC_SBMR2_SEC_CONFIG_MASK                (0x3U)
91065 #define SRC_SBMR2_SEC_CONFIG_SHIFT               (0U)
91066 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
91067 
91068 #define SRC_SBMR2_BT_FUSE_SEL_MASK               (0x10U)
91069 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              (4U)
91070 #define SRC_SBMR2_BT_FUSE_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
91071 
91072 #define SRC_SBMR2_FORCE_COLD_BOOT_MASK           (0xE0U)
91073 #define SRC_SBMR2_FORCE_COLD_BOOT_SHIFT          (5U)
91074 #define SRC_SBMR2_FORCE_COLD_BOOT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FORCE_COLD_BOOT_MASK)
91075 
91076 #define SRC_SBMR2_IPP_BOOT_MODE_MASK             (0xF000000U)
91077 #define SRC_SBMR2_IPP_BOOT_MODE_SHIFT            (24U)
91078 #define SRC_SBMR2_IPP_BOOT_MODE(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_SBMR2_IPP_BOOT_MODE_MASK)
91079 /*! @} */
91080 
91081 /*! @name GPR1 - SRC General Purpose Register 1 */
91082 /*! @{ */
91083 
91084 #define SRC_GPR1_C0_START_ADDRH_MASK             (0xFFFFU)
91085 #define SRC_GPR1_C0_START_ADDRH_SHIFT            (0U)
91086 #define SRC_GPR1_C0_START_ADDRH(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR1_C0_START_ADDRH_SHIFT)) & SRC_GPR1_C0_START_ADDRH_MASK)
91087 /*! @} */
91088 
91089 /*! @name GPR2 - SRC General Purpose Register 2 */
91090 /*! @{ */
91091 
91092 #define SRC_GPR2_C0_START_ADDRL_MASK             (0x3FFFFFU)
91093 #define SRC_GPR2_C0_START_ADDRL_SHIFT            (0U)
91094 #define SRC_GPR2_C0_START_ADDRL(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR2_C0_START_ADDRL_SHIFT)) & SRC_GPR2_C0_START_ADDRL_MASK)
91095 /*! @} */
91096 
91097 /*! @name GPR3 - SRC General Purpose Register 3 */
91098 /*! @{ */
91099 
91100 #define SRC_GPR3_C1_START_ADDRH_MASK             (0xFFFFU)
91101 #define SRC_GPR3_C1_START_ADDRH_SHIFT            (0U)
91102 #define SRC_GPR3_C1_START_ADDRH(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR3_C1_START_ADDRH_SHIFT)) & SRC_GPR3_C1_START_ADDRH_MASK)
91103 /*! @} */
91104 
91105 /*! @name GPR4 - SRC General Purpose Register 4 */
91106 /*! @{ */
91107 
91108 #define SRC_GPR4_C1_START_ADDRL_MASK             (0x3FFFFFU)
91109 #define SRC_GPR4_C1_START_ADDRL_SHIFT            (0U)
91110 #define SRC_GPR4_C1_START_ADDRL(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR4_C1_START_ADDRL_SHIFT)) & SRC_GPR4_C1_START_ADDRL_MASK)
91111 /*! @} */
91112 
91113 /*! @name GPR5 - SRC General Purpose Register 5 */
91114 /*! @{ */
91115 
91116 #define SRC_GPR5_C2_START_ADDRH_MASK             (0xFFFFU)
91117 #define SRC_GPR5_C2_START_ADDRH_SHIFT            (0U)
91118 #define SRC_GPR5_C2_START_ADDRH(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR5_C2_START_ADDRH_SHIFT)) & SRC_GPR5_C2_START_ADDRH_MASK)
91119 /*! @} */
91120 
91121 /*! @name GPR6 - SRC General Purpose Register 6 */
91122 /*! @{ */
91123 
91124 #define SRC_GPR6_C2_START_ADDRL_MASK             (0x3FFFFFU)
91125 #define SRC_GPR6_C2_START_ADDRL_SHIFT            (0U)
91126 #define SRC_GPR6_C2_START_ADDRL(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR6_C2_START_ADDRL_SHIFT)) & SRC_GPR6_C2_START_ADDRL_MASK)
91127 /*! @} */
91128 
91129 /*! @name GPR7 - SRC General Purpose Register 7 */
91130 /*! @{ */
91131 
91132 #define SRC_GPR7_C3_START_ADDRH_MASK             (0xFFFFU)
91133 #define SRC_GPR7_C3_START_ADDRH_SHIFT            (0U)
91134 #define SRC_GPR7_C3_START_ADDRH(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR7_C3_START_ADDRH_SHIFT)) & SRC_GPR7_C3_START_ADDRH_MASK)
91135 /*! @} */
91136 
91137 /*! @name GPR8 - SRC General Purpose Register 8 */
91138 /*! @{ */
91139 
91140 #define SRC_GPR8_C3_START_ADDRL_MASK             (0x3FFFFFU)
91141 #define SRC_GPR8_C3_START_ADDRL_SHIFT            (0U)
91142 #define SRC_GPR8_C3_START_ADDRL(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR8_C3_START_ADDRL_SHIFT)) & SRC_GPR8_C3_START_ADDRL_MASK)
91143 /*! @} */
91144 
91145 /*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */
91146 /*! @{ */
91147 
91148 #define SRC_DDRC_RCR_DDRC1_PRST_MASK             (0x1U)
91149 #define SRC_DDRC_RCR_DDRC1_PRST_SHIFT            (0U)
91150 /*! DDRC1_PRST
91151  *  0b0..De-assert DDR Controller preset and DDR PHY reset reset
91152  *  0b1..Assert DDR Controller preset and DDR PHY reset
91153  */
91154 #define SRC_DDRC_RCR_DDRC1_PRST(x)               (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK)
91155 
91156 #define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK         (0x2U)
91157 #define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT        (1U)
91158 /*! DDRC1_CORE_RST
91159  *  0b0..De-assert DDR controller aresetn and core_ddrc_rstn
91160  *  0b1..Assert DDR Controller preset and DDR PHY reset
91161  */
91162 #define SRC_DDRC_RCR_DDRC1_CORE_RST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK)
91163 
91164 #define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK        (0x4U)
91165 #define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT       (2U)
91166 /*! DDRC1_PHY_RESET
91167  *  0b0..De-assert DDR controller
91168  *  0b1..Assert DDR Controller
91169  */
91170 #define SRC_DDRC_RCR_DDRC1_PHY_RESET(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK)
91171 
91172 #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK      (0x8U)
91173 #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT     (3U)
91174 /*! DDRC1_PHY_PWROKIN
91175  *  0b0..De-assert DDR controller
91176  *  0b1..Assert DDR Controller
91177  */
91178 #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK)
91179 
91180 #define SRC_DDRC_RCR_DDRC1_SYS_RST_MASK          (0x10U)
91181 #define SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT         (4U)
91182 #define SRC_DDRC_RCR_DDRC1_SYS_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_SYS_RST_MASK)
91183 
91184 #define SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK         (0x20U)
91185 #define SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT        (5U)
91186 #define SRC_DDRC_RCR_DDRC1_PHY_WRST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK)
91187 
91188 #define SRC_DDRC_RCR_DOMAIN0_MASK                (0x1000000U)
91189 #define SRC_DDRC_RCR_DOMAIN0_SHIFT               (24U)
91190 /*! DOMAIN0
91191  *  0b0..This register is not assigned to domain0. The master from domain0 cannot write to this register.
91192  *  0b1..This register is assigned to domain0. The master from domain0 can write to this register
91193  */
91194 #define SRC_DDRC_RCR_DOMAIN0(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK)
91195 
91196 #define SRC_DDRC_RCR_DOMAIN1_MASK                (0x2000000U)
91197 #define SRC_DDRC_RCR_DOMAIN1_SHIFT               (25U)
91198 /*! DOMAIN1
91199  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
91200  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
91201  */
91202 #define SRC_DDRC_RCR_DOMAIN1(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK)
91203 
91204 #define SRC_DDRC_RCR_DOMAIN2_MASK                (0x4000000U)
91205 #define SRC_DDRC_RCR_DOMAIN2_SHIFT               (26U)
91206 /*! DOMAIN2
91207  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
91208  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
91209  */
91210 #define SRC_DDRC_RCR_DOMAIN2(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK)
91211 
91212 #define SRC_DDRC_RCR_DOMAIN3_MASK                (0x8000000U)
91213 #define SRC_DDRC_RCR_DOMAIN3_SHIFT               (27U)
91214 /*! DOMAIN3
91215  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
91216  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
91217  */
91218 #define SRC_DDRC_RCR_DOMAIN3(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK)
91219 
91220 #define SRC_DDRC_RCR_LOCK_MASK                   (0x40000000U)
91221 #define SRC_DDRC_RCR_LOCK_SHIFT                  (30U)
91222 /*! LOCK
91223  *  0b0..[31] and [27:24] bits can be modified
91224  *  0b1..[31] and [27:24] bits cannot be modified
91225  */
91226 #define SRC_DDRC_RCR_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK)
91227 
91228 #define SRC_DDRC_RCR_DOM_EN_MASK                 (0x80000000U)
91229 #define SRC_DDRC_RCR_DOM_EN_SHIFT                (31U)
91230 /*! DOM_EN
91231  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
91232  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
91233  *       the masters from the domains specified in [27:24] area.
91234  */
91235 #define SRC_DDRC_RCR_DOM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK)
91236 /*! @} */
91237 
91238 /*! @name HDMIPHY_RCR - HDMIPHY Reset Control Register */
91239 /*! @{ */
91240 
91241 #define SRC_HDMIPHY_RCR_HDMIPHY_RESET_MASK       (0x1U)
91242 #define SRC_HDMIPHY_RCR_HDMIPHY_RESET_SHIFT      (0U)
91243 /*! HDMIPHY_RESET
91244  *  0b0..Do not assert HDMI PHY reset
91245  *  0b1..Assert HDMI PHY reset
91246  */
91247 #define SRC_HDMIPHY_RCR_HDMIPHY_RESET(x)         (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_HDMIPHY_RESET_SHIFT)) & SRC_HDMIPHY_RCR_HDMIPHY_RESET_MASK)
91248 
91249 #define SRC_HDMIPHY_RCR_DOMAIN0_MASK             (0x1000000U)
91250 #define SRC_HDMIPHY_RCR_DOMAIN0_SHIFT            (24U)
91251 /*! DOMAIN0
91252  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
91253  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
91254  */
91255 #define SRC_HDMIPHY_RCR_DOMAIN0(x)               (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN0_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN0_MASK)
91256 
91257 #define SRC_HDMIPHY_RCR_DOMAIN1_MASK             (0x2000000U)
91258 #define SRC_HDMIPHY_RCR_DOMAIN1_SHIFT            (25U)
91259 /*! DOMAIN1
91260  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
91261  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
91262  */
91263 #define SRC_HDMIPHY_RCR_DOMAIN1(x)               (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN1_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN1_MASK)
91264 
91265 #define SRC_HDMIPHY_RCR_DOMAIN2_MASK             (0x4000000U)
91266 #define SRC_HDMIPHY_RCR_DOMAIN2_SHIFT            (26U)
91267 /*! DOMAIN2
91268  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
91269  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
91270  */
91271 #define SRC_HDMIPHY_RCR_DOMAIN2(x)               (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN2_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN2_MASK)
91272 
91273 #define SRC_HDMIPHY_RCR_DOMAIN3_MASK             (0x8000000U)
91274 #define SRC_HDMIPHY_RCR_DOMAIN3_SHIFT            (27U)
91275 /*! DOMAIN3
91276  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
91277  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
91278  */
91279 #define SRC_HDMIPHY_RCR_DOMAIN3(x)               (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN3_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN3_MASK)
91280 
91281 #define SRC_HDMIPHY_RCR_LOCK_MASK                (0x40000000U)
91282 #define SRC_HDMIPHY_RCR_LOCK_SHIFT               (30U)
91283 /*! LOCK
91284  *  0b0..[31] and [27:24] bits can be modified
91285  *  0b1..[31] and [27:24] bits cannot be modified
91286  */
91287 #define SRC_HDMIPHY_RCR_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_LOCK_SHIFT)) & SRC_HDMIPHY_RCR_LOCK_MASK)
91288 
91289 #define SRC_HDMIPHY_RCR_DOM_EN_MASK              (0x80000000U)
91290 #define SRC_HDMIPHY_RCR_DOM_EN_SHIFT             (31U)
91291 /*! DOM_EN
91292  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
91293  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
91294  *       the masters from the domains specified in [27:24] area.
91295  */
91296 #define SRC_HDMIPHY_RCR_DOM_EN(x)                (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOM_EN_SHIFT)) & SRC_HDMIPHY_RCR_DOM_EN_MASK)
91297 /*! @} */
91298 
91299 /*! @name MIPIPHY1_RCR - MIPI PHY1 Reset Control Register */
91300 /*! @{ */
91301 
91302 #define SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_MASK     (0x1U)
91303 #define SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_SHIFT    (0U)
91304 /*! MIPIPHY1_RESET
91305  *  0b0..Do not assert MIPI PHY1 reset
91306  *  0b1..Assert MIPI PHY1 reset
91307  */
91308 #define SRC_MIPIPHY1_RCR_MIPIPHY1_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_MASK)
91309 
91310 #define SRC_MIPIPHY1_RCR_DOMAIN0_MASK            (0x1000000U)
91311 #define SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT           (24U)
91312 /*! DOMAIN0
91313  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
91314  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
91315  */
91316 #define SRC_MIPIPHY1_RCR_DOMAIN0(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN0_MASK)
91317 
91318 #define SRC_MIPIPHY1_RCR_DOMAIN1_MASK            (0x2000000U)
91319 #define SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT           (25U)
91320 /*! DOMAIN1
91321  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
91322  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
91323  */
91324 #define SRC_MIPIPHY1_RCR_DOMAIN1(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN1_MASK)
91325 
91326 #define SRC_MIPIPHY1_RCR_DOMAIN2_MASK            (0x4000000U)
91327 #define SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT           (26U)
91328 /*! DOMAIN2
91329  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
91330  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
91331  */
91332 #define SRC_MIPIPHY1_RCR_DOMAIN2(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN2_MASK)
91333 
91334 #define SRC_MIPIPHY1_RCR_DOMAIN3_MASK            (0x8000000U)
91335 #define SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT           (27U)
91336 /*! DOMAIN3
91337  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
91338  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
91339  */
91340 #define SRC_MIPIPHY1_RCR_DOMAIN3(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN3_MASK)
91341 
91342 #define SRC_MIPIPHY1_RCR_LOCK_MASK               (0x40000000U)
91343 #define SRC_MIPIPHY1_RCR_LOCK_SHIFT              (30U)
91344 /*! LOCK
91345  *  0b0..[31] and [27:24] bits can be modified
91346  *  0b1..[31] and [27:24] bits cannot be modified
91347  */
91348 #define SRC_MIPIPHY1_RCR_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_LOCK_SHIFT)) & SRC_MIPIPHY1_RCR_LOCK_MASK)
91349 
91350 #define SRC_MIPIPHY1_RCR_DOM_EN_MASK             (0x80000000U)
91351 #define SRC_MIPIPHY1_RCR_DOM_EN_SHIFT            (31U)
91352 /*! DOM_EN
91353  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
91354  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
91355  *       the masters from the domains specified in [27:24] area.
91356  */
91357 #define SRC_MIPIPHY1_RCR_DOM_EN(x)               (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY1_RCR_DOM_EN_MASK)
91358 /*! @} */
91359 
91360 /*! @name MIPIPHY2_RCR - MIPI PHY2 Reset Control Register */
91361 /*! @{ */
91362 
91363 #define SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_MASK     (0x1U)
91364 #define SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_SHIFT    (0U)
91365 /*! MIPIPHY2_RESET
91366  *  0b0..Do not assert MIPI PHY2 reset
91367  *  0b1..Assert MIPI PHY2 reset
91368  */
91369 #define SRC_MIPIPHY2_RCR_MIPIPHY2_RESET(x)       (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_MASK)
91370 
91371 #define SRC_MIPIPHY2_RCR_DOMAIN0_MASK            (0x1000000U)
91372 #define SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT           (24U)
91373 /*! DOMAIN0
91374  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
91375  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
91376  */
91377 #define SRC_MIPIPHY2_RCR_DOMAIN0(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN0_MASK)
91378 
91379 #define SRC_MIPIPHY2_RCR_DOMAIN1_MASK            (0x2000000U)
91380 #define SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT           (25U)
91381 /*! DOMAIN1
91382  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
91383  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
91384  */
91385 #define SRC_MIPIPHY2_RCR_DOMAIN1(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN1_MASK)
91386 
91387 #define SRC_MIPIPHY2_RCR_DOMAIN2_MASK            (0x4000000U)
91388 #define SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT           (26U)
91389 /*! DOMAIN2
91390  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
91391  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
91392  */
91393 #define SRC_MIPIPHY2_RCR_DOMAIN2(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN2_MASK)
91394 
91395 #define SRC_MIPIPHY2_RCR_DOMAIN3_MASK            (0x8000000U)
91396 #define SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT           (27U)
91397 /*! DOMAIN3
91398  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
91399  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
91400  */
91401 #define SRC_MIPIPHY2_RCR_DOMAIN3(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN3_MASK)
91402 
91403 #define SRC_MIPIPHY2_RCR_LOCK_MASK               (0x40000000U)
91404 #define SRC_MIPIPHY2_RCR_LOCK_SHIFT              (30U)
91405 /*! LOCK
91406  *  0b0..[31] and [27:24] bits can be modified
91407  *  0b1..[31] and [27:24] bits cannot be modified
91408  */
91409 #define SRC_MIPIPHY2_RCR_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_LOCK_SHIFT)) & SRC_MIPIPHY2_RCR_LOCK_MASK)
91410 
91411 #define SRC_MIPIPHY2_RCR_DOM_EN_MASK             (0x80000000U)
91412 #define SRC_MIPIPHY2_RCR_DOM_EN_SHIFT            (31U)
91413 /*! DOM_EN
91414  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
91415  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
91416  *       the masters from the domains specified in [27:24] area.
91417  */
91418 #define SRC_MIPIPHY2_RCR_DOM_EN(x)               (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY2_RCR_DOM_EN_MASK)
91419 /*! @} */
91420 
91421 /*! @name HSIO_RCR - HSIO Reset Control Register */
91422 /*! @{ */
91423 
91424 #define SRC_HSIO_RCR_HSIO_RESET_MASK             (0x1U)
91425 #define SRC_HSIO_RCR_HSIO_RESET_SHIFT            (0U)
91426 /*! HSIO_RESET
91427  *  0b0..Do not assert HSIOMIX reset
91428  *  0b1..Assert HSIOMIX reset
91429  */
91430 #define SRC_HSIO_RCR_HSIO_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_HSIO_RESET_SHIFT)) & SRC_HSIO_RCR_HSIO_RESET_MASK)
91431 
91432 #define SRC_HSIO_RCR_DOMAIN0_MASK                (0x1000000U)
91433 #define SRC_HSIO_RCR_DOMAIN0_SHIFT               (24U)
91434 /*! DOMAIN0
91435  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
91436  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
91437  */
91438 #define SRC_HSIO_RCR_DOMAIN0(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN0_SHIFT)) & SRC_HSIO_RCR_DOMAIN0_MASK)
91439 
91440 #define SRC_HSIO_RCR_DOMAIN1_MASK                (0x2000000U)
91441 #define SRC_HSIO_RCR_DOMAIN1_SHIFT               (25U)
91442 /*! DOMAIN1
91443  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
91444  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
91445  */
91446 #define SRC_HSIO_RCR_DOMAIN1(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN1_SHIFT)) & SRC_HSIO_RCR_DOMAIN1_MASK)
91447 
91448 #define SRC_HSIO_RCR_DOMAIN2_MASK                (0x4000000U)
91449 #define SRC_HSIO_RCR_DOMAIN2_SHIFT               (26U)
91450 /*! DOMAIN2
91451  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
91452  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
91453  */
91454 #define SRC_HSIO_RCR_DOMAIN2(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN2_SHIFT)) & SRC_HSIO_RCR_DOMAIN2_MASK)
91455 
91456 #define SRC_HSIO_RCR_DOMAIN3_MASK                (0x8000000U)
91457 #define SRC_HSIO_RCR_DOMAIN3_SHIFT               (27U)
91458 /*! DOMAIN3
91459  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
91460  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
91461  */
91462 #define SRC_HSIO_RCR_DOMAIN3(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN3_SHIFT)) & SRC_HSIO_RCR_DOMAIN3_MASK)
91463 
91464 #define SRC_HSIO_RCR_LOCK_MASK                   (0x40000000U)
91465 #define SRC_HSIO_RCR_LOCK_SHIFT                  (30U)
91466 /*! LOCK
91467  *  0b0..[31] and [27:24] bits can be modified
91468  *  0b1..[31] and [27:24] bits cannot be modified
91469  */
91470 #define SRC_HSIO_RCR_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_LOCK_SHIFT)) & SRC_HSIO_RCR_LOCK_MASK)
91471 
91472 #define SRC_HSIO_RCR_DOM_EN_MASK                 (0x80000000U)
91473 #define SRC_HSIO_RCR_DOM_EN_SHIFT                (31U)
91474 /*! DOM_EN
91475  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
91476  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
91477  *       the masters from the domains specified in [27:24] area.
91478  */
91479 #define SRC_HSIO_RCR_DOM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOM_EN_SHIFT)) & SRC_HSIO_RCR_DOM_EN_MASK)
91480 /*! @} */
91481 
91482 /*! @name MEDIAISPDWP_RCR - MEDIAMIX ISP and Dewarp Reset Control Register */
91483 /*! @{ */
91484 
91485 #define SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_MASK (0x1U)
91486 #define SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_SHIFT (0U)
91487 /*! MEDIAISPDWP_RESET
91488  *  0b0..Do not assert MEDIAMIX ISP and Dewarp reset
91489  *  0b1..Assert MEDIAMIX ISP and Dewarp reset
91490  */
91491 #define SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_SHIFT)) & SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_MASK)
91492 
91493 #define SRC_MEDIAISPDWP_RCR_DOMAIN0_MASK         (0x1000000U)
91494 #define SRC_MEDIAISPDWP_RCR_DOMAIN0_SHIFT        (24U)
91495 /*! DOMAIN0
91496  *  0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
91497  *  0b1..This register is assigned to domain0. The master from domain3 can write to this register
91498  */
91499 #define SRC_MEDIAISPDWP_RCR_DOMAIN0(x)           (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN0_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN0_MASK)
91500 
91501 #define SRC_MEDIAISPDWP_RCR_DOMAIN1_MASK         (0x2000000U)
91502 #define SRC_MEDIAISPDWP_RCR_DOMAIN1_SHIFT        (25U)
91503 /*! DOMAIN1
91504  *  0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
91505  *  0b1..This register is assigned to domain1. The master from domain1 can write to this register
91506  */
91507 #define SRC_MEDIAISPDWP_RCR_DOMAIN1(x)           (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN1_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN1_MASK)
91508 
91509 #define SRC_MEDIAISPDWP_RCR_DOMAIN2_MASK         (0x4000000U)
91510 #define SRC_MEDIAISPDWP_RCR_DOMAIN2_SHIFT        (26U)
91511 /*! DOMAIN2
91512  *  0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
91513  *  0b1..This register is assigned to domain2. The master from domain2 can write to this register
91514  */
91515 #define SRC_MEDIAISPDWP_RCR_DOMAIN2(x)           (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN2_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN2_MASK)
91516 
91517 #define SRC_MEDIAISPDWP_RCR_DOMAIN3_MASK         (0x8000000U)
91518 #define SRC_MEDIAISPDWP_RCR_DOMAIN3_SHIFT        (27U)
91519 /*! DOMAIN3
91520  *  0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
91521  *  0b1..This register is assigned to domain3. The master from domain3 can write to this register
91522  */
91523 #define SRC_MEDIAISPDWP_RCR_DOMAIN3(x)           (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN3_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN3_MASK)
91524 
91525 #define SRC_MEDIAISPDWP_RCR_LOCK_MASK            (0x40000000U)
91526 #define SRC_MEDIAISPDWP_RCR_LOCK_SHIFT           (30U)
91527 /*! LOCK
91528  *  0b0..[31] and [27:24] bits can be modified
91529  *  0b1..[31] and [27:24] bits cannot be modified
91530  */
91531 #define SRC_MEDIAISPDWP_RCR_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_LOCK_SHIFT)) & SRC_MEDIAISPDWP_RCR_LOCK_MASK)
91532 
91533 #define SRC_MEDIAISPDWP_RCR_DOM_EN_MASK          (0x80000000U)
91534 #define SRC_MEDIAISPDWP_RCR_DOM_EN_SHIFT         (31U)
91535 /*! DOM_EN
91536  *  0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
91537  *  0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
91538  *       the masters from the domains specified in [27:24] area.
91539  */
91540 #define SRC_MEDIAISPDWP_RCR_DOM_EN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOM_EN_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOM_EN_MASK)
91541 /*! @} */
91542 
91543 
91544 /*!
91545  * @}
91546  */ /* end of group SRC_Register_Masks */
91547 
91548 
91549 /* SRC - Peripheral instance base addresses */
91550 /** Peripheral SRC base address */
91551 #define SRC_BASE                                 (0x30390000u)
91552 /** Peripheral SRC base pointer */
91553 #define SRC                                      ((SRC_Type *)SRC_BASE)
91554 /** Array initializer of SRC peripheral base addresses */
91555 #define SRC_BASE_ADDRS                           { SRC_BASE }
91556 /** Array initializer of SRC peripheral base pointers */
91557 #define SRC_BASE_PTRS                            { SRC }
91558 
91559 /*!
91560  * @}
91561  */ /* end of group SRC_Peripheral_Access_Layer */
91562 
91563 
91564 /* ----------------------------------------------------------------------------
91565    -- SYS_CTR_COMPARE Peripheral Access Layer
91566    ---------------------------------------------------------------------------- */
91567 
91568 /*!
91569  * @addtogroup SYS_CTR_COMPARE_Peripheral_Access_Layer SYS_CTR_COMPARE Peripheral Access Layer
91570  * @{
91571  */
91572 
91573 /** SYS_CTR_COMPARE - Register Layout Typedef */
91574 typedef struct {
91575        uint8_t RESERVED_0[32];
91576   __I  uint32_t CMPCVL0;                           /**< Compare Count Value Low Register, offset: 0x20 */
91577   __I  uint32_t CMPCVH0;                           /**< Compare Count Value High Register, offset: 0x24 */
91578        uint8_t RESERVED_1[4];
91579   __IO uint32_t CMPCR0;                            /**< Compare Control Register, offset: 0x2C */
91580        uint8_t RESERVED_2[240];
91581   __I  uint32_t CMPCVL1;                           /**< Compare Count Value Low Register, offset: 0x120 */
91582   __I  uint32_t CMPCVH1;                           /**< Compare Count Value High Register, offset: 0x124 */
91583        uint8_t RESERVED_3[4];
91584   __IO uint32_t CMPCR;                             /**< Compare Control Register, offset: 0x12C */
91585        uint8_t RESERVED_4[3744];
91586   __I  uint32_t CNTID0;                            /**< Counter ID Register, offset: 0xFD0 */
91587 } SYS_CTR_COMPARE_Type;
91588 
91589 /* ----------------------------------------------------------------------------
91590    -- SYS_CTR_COMPARE Register Masks
91591    ---------------------------------------------------------------------------- */
91592 
91593 /*!
91594  * @addtogroup SYS_CTR_COMPARE_Register_Masks SYS_CTR_COMPARE Register Masks
91595  * @{
91596  */
91597 
91598 /*! @name CMPCVL0 - Compare Count Value Low Register */
91599 /*! @{ */
91600 
91601 #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK      (0xFFFFFFFFU)
91602 #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT     (0U)
91603 #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK)
91604 /*! @} */
91605 
91606 /*! @name CMPCVH0 - Compare Count Value High Register */
91607 /*! @{ */
91608 
91609 #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK      (0x1FFFFFFU)
91610 #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT     (0U)
91611 #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK)
91612 /*! @} */
91613 
91614 /*! @name CMPCR0 - Compare Control Register */
91615 /*! @{ */
91616 
91617 #define SYS_CTR_COMPARE_CMPCR0_EN_MASK           (0x1U)
91618 #define SYS_CTR_COMPARE_CMPCR0_EN_SHIFT          (0U)
91619 /*! EN
91620  *  0b0..Compare disabled
91621  *  0b1..Compare enabled
91622  */
91623 #define SYS_CTR_COMPARE_CMPCR0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_EN_MASK)
91624 
91625 #define SYS_CTR_COMPARE_CMPCR0_IMASK_MASK        (0x2U)
91626 #define SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT       (1U)
91627 /*! IMASK
91628  *  0b0..Interrupt output signal is not masked.
91629  *  0b1..Interrupt output signal is masked.
91630  */
91631 #define SYS_CTR_COMPARE_CMPCR0_IMASK(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_IMASK_MASK)
91632 
91633 #define SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK        (0x4U)
91634 #define SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT       (2U)
91635 /*! ISTAT
91636  *  0b0..Counter value is less than the compare value or compare is disabled.
91637  *  0b1..Counter value is greater than or equal to the compare value and compare is enabled.
91638  */
91639 #define SYS_CTR_COMPARE_CMPCR0_ISTAT(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK)
91640 /*! @} */
91641 
91642 /*! @name CMPCVL1 - Compare Count Value Low Register */
91643 /*! @{ */
91644 
91645 #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK      (0xFFFFFFFFU)
91646 #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT     (0U)
91647 #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK)
91648 /*! @} */
91649 
91650 /*! @name CMPCVH1 - Compare Count Value High Register */
91651 /*! @{ */
91652 
91653 #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK      (0x1FFFFFFU)
91654 #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT     (0U)
91655 #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK)
91656 /*! @} */
91657 
91658 /*! @name CMPCR - Compare Control Register */
91659 /*! @{ */
91660 
91661 #define SYS_CTR_COMPARE_CMPCR_EN_MASK            (0x1U)
91662 #define SYS_CTR_COMPARE_CMPCR_EN_SHIFT           (0U)
91663 /*! EN
91664  *  0b0..Compare disabled
91665  *  0b1..Compare enabled
91666  */
91667 #define SYS_CTR_COMPARE_CMPCR_EN(x)              (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR_EN_MASK)
91668 
91669 #define SYS_CTR_COMPARE_CMPCR_IMASK_MASK         (0x2U)
91670 #define SYS_CTR_COMPARE_CMPCR_IMASK_SHIFT        (1U)
91671 /*! IMASK
91672  *  0b0..Interrupt output signal is not masked.
91673  *  0b1..Interrupt output signal is masked.
91674  */
91675 #define SYS_CTR_COMPARE_CMPCR_IMASK(x)           (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR_IMASK_MASK)
91676 
91677 #define SYS_CTR_COMPARE_CMPCR_ISTAT_MASK         (0x4U)
91678 #define SYS_CTR_COMPARE_CMPCR_ISTAT_SHIFT        (2U)
91679 /*! ISTAT
91680  *  0b0..Counter value is less than the compare value or compare is disabled.
91681  *  0b1..Counter value is greater than or equal to the compare value and compare is enabled.
91682  */
91683 #define SYS_CTR_COMPARE_CMPCR_ISTAT(x)           (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR_ISTAT_MASK)
91684 /*! @} */
91685 
91686 /*! @name CNTID0 - Counter ID Register */
91687 /*! @{ */
91688 
91689 #define SYS_CTR_COMPARE_CNTID0_CNTID_MASK        (0xFFFFFFFFU)
91690 #define SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT       (0U)
91691 #define SYS_CTR_COMPARE_CNTID0_CNTID(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT)) & SYS_CTR_COMPARE_CNTID0_CNTID_MASK)
91692 /*! @} */
91693 
91694 
91695 /*!
91696  * @}
91697  */ /* end of group SYS_CTR_COMPARE_Register_Masks */
91698 
91699 
91700 /* SYS_CTR_COMPARE - Peripheral instance base addresses */
91701 /** Peripheral SYS_CTR_COMPARE base address */
91702 #define SYS_CTR_COMPARE_BASE                     (0x306B0000u)
91703 /** Peripheral SYS_CTR_COMPARE base pointer */
91704 #define SYS_CTR_COMPARE                          ((SYS_CTR_COMPARE_Type *)SYS_CTR_COMPARE_BASE)
91705 /** Array initializer of SYS_CTR_COMPARE peripheral base addresses */
91706 #define SYS_CTR_COMPARE_BASE_ADDRS               { SYS_CTR_COMPARE_BASE }
91707 /** Array initializer of SYS_CTR_COMPARE peripheral base pointers */
91708 #define SYS_CTR_COMPARE_BASE_PTRS                { SYS_CTR_COMPARE }
91709 
91710 /*!
91711  * @}
91712  */ /* end of group SYS_CTR_COMPARE_Peripheral_Access_Layer */
91713 
91714 
91715 /* ----------------------------------------------------------------------------
91716    -- SYS_CTR_CONTROL Peripheral Access Layer
91717    ---------------------------------------------------------------------------- */
91718 
91719 /*!
91720  * @addtogroup SYS_CTR_CONTROL_Peripheral_Access_Layer SYS_CTR_CONTROL Peripheral Access Layer
91721  * @{
91722  */
91723 
91724 /** SYS_CTR_CONTROL - Register Layout Typedef */
91725 typedef struct {
91726   __IO uint32_t CNTCR;                             /**< Counter Control Register, offset: 0x0 */
91727   __I  uint32_t CNTSR;                             /**< Counter Status Register, offset: 0x4 */
91728   __IO uint32_t CNTCV0;                            /**< Counter Count Value Low Register, offset: 0x8 */
91729   __IO uint32_t CNTCV1;                            /**< Counter Count Value High Register, offset: 0xC */
91730        uint8_t RESERVED_0[16];
91731   __I  uint32_t CNTFID0;                           /**< Frequency Modes Table 0 Register, offset: 0x20 */
91732   __I  uint32_t CNTFID1;                           /**< Frequency Modes Table 1 Register, offset: 0x24 */
91733   __I  uint32_t CNTFID2;                           /**< Frequency Modes Table 2 Register, offset: 0x28 */
91734        uint8_t RESERVED_1[4004];
91735   __I  uint32_t CNTID0;                            /**< Counter ID Register, offset: 0xFD0 */
91736 } SYS_CTR_CONTROL_Type;
91737 
91738 /* ----------------------------------------------------------------------------
91739    -- SYS_CTR_CONTROL Register Masks
91740    ---------------------------------------------------------------------------- */
91741 
91742 /*!
91743  * @addtogroup SYS_CTR_CONTROL_Register_Masks SYS_CTR_CONTROL Register Masks
91744  * @{
91745  */
91746 
91747 /*! @name CNTCR - Counter Control Register */
91748 /*! @{ */
91749 
91750 #define SYS_CTR_CONTROL_CNTCR_EN_MASK            (0x1U)
91751 #define SYS_CTR_CONTROL_CNTCR_EN_SHIFT           (0U)
91752 /*! EN
91753  *  0b0..Counter disabled
91754  *  0b1..Counter enabled
91755  */
91756 #define SYS_CTR_CONTROL_CNTCR_EN(x)              (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR_EN_MASK)
91757 
91758 #define SYS_CTR_CONTROL_CNTCR_HDBG_MASK          (0x2U)
91759 #define SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT         (1U)
91760 /*! HDBG
91761  *  0b0..The assertion of the debug input is ignored.
91762  *  0b1..The assertion of the debug input causes the System Counter to halt.
91763  */
91764 #define SYS_CTR_CONTROL_CNTCR_HDBG(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT)) & SYS_CTR_CONTROL_CNTCR_HDBG_MASK)
91765 
91766 #define SYS_CTR_CONTROL_CNTCR_FCR0_MASK          (0x100U)
91767 #define SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT         (8U)
91768 /*! FCR0
91769  *  0b0..No change.
91770  *  0b1..Select frequency modes table entry 0, the base frequency.
91771  */
91772 #define SYS_CTR_CONTROL_CNTCR_FCR0(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR0_MASK)
91773 
91774 #define SYS_CTR_CONTROL_CNTCR_FCR1_MASK          (0x200U)
91775 #define SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT         (9U)
91776 /*! FCR1
91777  *  0b0..No change.
91778  *  0b1..Select frequency modes table entry 1, the base frequency.
91779  */
91780 #define SYS_CTR_CONTROL_CNTCR_FCR1(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR1_MASK)
91781 /*! @} */
91782 
91783 /*! @name CNTSR - Counter Status Register */
91784 /*! @{ */
91785 
91786 #define SYS_CTR_CONTROL_CNTSR_DBGH_MASK          (0x1U)
91787 #define SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT         (0U)
91788 /*! DBGH
91789  *  0b0..Counter is not halted by debug.
91790  *  0b1..Counter is halted by debug.
91791  */
91792 #define SYS_CTR_CONTROL_CNTSR_DBGH(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT)) & SYS_CTR_CONTROL_CNTSR_DBGH_MASK)
91793 
91794 #define SYS_CTR_CONTROL_CNTSR_FCA0_MASK          (0x100U)
91795 #define SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT         (8U)
91796 /*! FCA0
91797  *  0b0..Base frequency is not selected.
91798  *  0b1..Base frequency is selected.
91799  */
91800 #define SYS_CTR_CONTROL_CNTSR_FCA0(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA0_MASK)
91801 
91802 #define SYS_CTR_CONTROL_CNTSR_FCA1_MASK          (0x200U)
91803 #define SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT         (9U)
91804 /*! FCA1
91805  *  0b0..Base frequency is not selected.
91806  *  0b1..Base frequency is selected.
91807  */
91808 #define SYS_CTR_CONTROL_CNTSR_FCA1(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA1_MASK)
91809 /*! @} */
91810 
91811 /*! @name CNTCV0 - Counter Count Value Low Register */
91812 /*! @{ */
91813 
91814 #define SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK       (0xFFFFFFFFU)
91815 #define SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT      (0U)
91816 #define SYS_CTR_CONTROL_CNTCV0_CNTCV0(x)         (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK)
91817 /*! @} */
91818 
91819 /*! @name CNTCV1 - Counter Count Value High Register */
91820 /*! @{ */
91821 
91822 #define SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK       (0x1FFFFFFU)
91823 #define SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT      (0U)
91824 #define SYS_CTR_CONTROL_CNTCV1_CNTCV1(x)         (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK)
91825 /*! @} */
91826 
91827 /*! @name CNTFID0 - Frequency Modes Table 0 Register */
91828 /*! @{ */
91829 
91830 #define SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK     (0xFFFFFFFFU)
91831 #define SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT    (0U)
91832 #define SYS_CTR_CONTROL_CNTFID0_CNTFID0(x)       (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT)) & SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK)
91833 /*! @} */
91834 
91835 /*! @name CNTFID1 - Frequency Modes Table 1 Register */
91836 /*! @{ */
91837 
91838 #define SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK     (0xFFFFFFFFU)
91839 #define SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT    (0U)
91840 #define SYS_CTR_CONTROL_CNTFID1_CNTFID1(x)       (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT)) & SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK)
91841 /*! @} */
91842 
91843 /*! @name CNTFID2 - Frequency Modes Table 2 Register */
91844 /*! @{ */
91845 
91846 #define SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK     (0xFFFFFFFFU)
91847 #define SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT    (0U)
91848 #define SYS_CTR_CONTROL_CNTFID2_CNTFID2(x)       (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT)) & SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK)
91849 /*! @} */
91850 
91851 /*! @name CNTID0 - Counter ID Register */
91852 /*! @{ */
91853 
91854 #define SYS_CTR_CONTROL_CNTID0_CNTID_MASK        (0xFFFFFFFFU)
91855 #define SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT       (0U)
91856 #define SYS_CTR_CONTROL_CNTID0_CNTID(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT)) & SYS_CTR_CONTROL_CNTID0_CNTID_MASK)
91857 /*! @} */
91858 
91859 
91860 /*!
91861  * @}
91862  */ /* end of group SYS_CTR_CONTROL_Register_Masks */
91863 
91864 
91865 /* SYS_CTR_CONTROL - Peripheral instance base addresses */
91866 /** Peripheral SYS_CTR_CONTROL base address */
91867 #define SYS_CTR_CONTROL_BASE                     (0x306C0000u)
91868 /** Peripheral SYS_CTR_CONTROL base pointer */
91869 #define SYS_CTR_CONTROL                          ((SYS_CTR_CONTROL_Type *)SYS_CTR_CONTROL_BASE)
91870 /** Array initializer of SYS_CTR_CONTROL peripheral base addresses */
91871 #define SYS_CTR_CONTROL_BASE_ADDRS               { SYS_CTR_CONTROL_BASE }
91872 /** Array initializer of SYS_CTR_CONTROL peripheral base pointers */
91873 #define SYS_CTR_CONTROL_BASE_PTRS                { SYS_CTR_CONTROL }
91874 
91875 /*!
91876  * @}
91877  */ /* end of group SYS_CTR_CONTROL_Peripheral_Access_Layer */
91878 
91879 
91880 /* ----------------------------------------------------------------------------
91881    -- SYS_CTR_READ Peripheral Access Layer
91882    ---------------------------------------------------------------------------- */
91883 
91884 /*!
91885  * @addtogroup SYS_CTR_READ_Peripheral_Access_Layer SYS_CTR_READ Peripheral Access Layer
91886  * @{
91887  */
91888 
91889 /** SYS_CTR_READ - Register Layout Typedef */
91890 typedef struct {
91891   __I  uint32_t CNTCV0;                            /**< Counter Count Value Low Register, offset: 0x0 */
91892   __I  uint32_t CNTCV1;                            /**< Counter Count Value High Register, offset: 0x4 */
91893        uint8_t RESERVED_0[4040];
91894   __I  uint32_t CNTID0;                            /**< Counter ID Register, offset: 0xFD0 */
91895 } SYS_CTR_READ_Type;
91896 
91897 /* ----------------------------------------------------------------------------
91898    -- SYS_CTR_READ Register Masks
91899    ---------------------------------------------------------------------------- */
91900 
91901 /*!
91902  * @addtogroup SYS_CTR_READ_Register_Masks SYS_CTR_READ Register Masks
91903  * @{
91904  */
91905 
91906 /*! @name CNTCV0 - Counter Count Value Low Register */
91907 /*! @{ */
91908 
91909 #define SYS_CTR_READ_CNTCV0_CNTCV0_MASK          (0xFFFFFFFFU)
91910 #define SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT         (0U)
91911 #define SYS_CTR_READ_CNTCV0_CNTCV0(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_READ_CNTCV0_CNTCV0_MASK)
91912 /*! @} */
91913 
91914 /*! @name CNTCV1 - Counter Count Value High Register */
91915 /*! @{ */
91916 
91917 #define SYS_CTR_READ_CNTCV1_CNTCV1_MASK          (0x1FFFFFFU)
91918 #define SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT         (0U)
91919 #define SYS_CTR_READ_CNTCV1_CNTCV1(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_READ_CNTCV1_CNTCV1_MASK)
91920 /*! @} */
91921 
91922 /*! @name CNTID0 - Counter ID Register */
91923 /*! @{ */
91924 
91925 #define SYS_CTR_READ_CNTID0_CNTID_MASK           (0xFFFFFFFFU)
91926 #define SYS_CTR_READ_CNTID0_CNTID_SHIFT          (0U)
91927 #define SYS_CTR_READ_CNTID0_CNTID(x)             (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTID0_CNTID_SHIFT)) & SYS_CTR_READ_CNTID0_CNTID_MASK)
91928 /*! @} */
91929 
91930 
91931 /*!
91932  * @}
91933  */ /* end of group SYS_CTR_READ_Register_Masks */
91934 
91935 
91936 /* SYS_CTR_READ - Peripheral instance base addresses */
91937 /** Peripheral SYS_CTR_READ base address */
91938 #define SYS_CTR_READ_BASE                        (0x306A0000u)
91939 /** Peripheral SYS_CTR_READ base pointer */
91940 #define SYS_CTR_READ                             ((SYS_CTR_READ_Type *)SYS_CTR_READ_BASE)
91941 /** Array initializer of SYS_CTR_READ peripheral base addresses */
91942 #define SYS_CTR_READ_BASE_ADDRS                  { SYS_CTR_READ_BASE }
91943 /** Array initializer of SYS_CTR_READ peripheral base pointers */
91944 #define SYS_CTR_READ_BASE_PTRS                   { SYS_CTR_READ }
91945 
91946 /*!
91947  * @}
91948  */ /* end of group SYS_CTR_READ_Peripheral_Access_Layer */
91949 
91950 
91951 /* ----------------------------------------------------------------------------
91952    -- TMU Peripheral Access Layer
91953    ---------------------------------------------------------------------------- */
91954 
91955 /*!
91956  * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer
91957  * @{
91958  */
91959 
91960 /** TMU - Register Layout Typedef */
91961 typedef struct {
91962   __IO uint32_t TER;                               /**< TMU Enable register, offset: 0x0 */
91963   __IO uint32_t TPS;                               /**< TMU Probe Select register, offset: 0x4 */
91964   __IO uint32_t TIER;                              /**< TMU Interrupt Enable register, offset: 0x8 */
91965   __IO uint32_t TIDR;                              /**< TMU Interrupt Detect register, offset: 0xC */
91966   __IO uint32_t TMHTITR;                           /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x10 */
91967   __IO uint32_t TMHTATR;                           /**< TMU Monitor High Temperature Average threshold register, offset: 0x14 */
91968   __IO uint32_t TMHTACTR;                          /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x18 */
91969   __I  uint32_t TSCR;                              /**< TMU Sensor Calibration register, offset: 0x1C */
91970   __I  uint32_t TRITSR;                            /**< TMU Report Immediate Temperature Site register n, offset: 0x20 */
91971   __I  uint32_t TRATSR;                            /**< TMU Report Average Temperature Site register n, offset: 0x24 */
91972 } TMU_Type;
91973 
91974 /* ----------------------------------------------------------------------------
91975    -- TMU Register Masks
91976    ---------------------------------------------------------------------------- */
91977 
91978 /*!
91979  * @addtogroup TMU_Register_Masks TMU Register Masks
91980  * @{
91981  */
91982 
91983 /*! @name TER - TMU Enable register */
91984 /*! @{ */
91985 
91986 #define TMU_TER_ALPF_MASK                        (0x3U)
91987 #define TMU_TER_ALPF_SHIFT                       (0U)
91988 /*! ALPF
91989  *  0b00..1.0
91990  *  0b01..0.5
91991  *  0b10..0.25
91992  *  0b11..0.125
91993  */
91994 #define TMU_TER_ALPF(x)                          (((uint32_t)(((uint32_t)(x)) << TMU_TER_ALPF_SHIFT)) & TMU_TER_ALPF_MASK)
91995 
91996 #define TMU_TER_ADC_PD_MASK                      (0x40000000U)
91997 #define TMU_TER_ADC_PD_SHIFT                     (30U)
91998 /*! ADC_PD
91999  *  0b0..normal operating mode
92000  *  0b1..power down mode
92001  */
92002 #define TMU_TER_ADC_PD(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TER_ADC_PD_SHIFT)) & TMU_TER_ADC_PD_MASK)
92003 
92004 #define TMU_TER_EN_MASK                          (0x80000000U)
92005 #define TMU_TER_EN_SHIFT                         (31U)
92006 /*! EN
92007  *  0b0..Disable
92008  *  0b1..Enable
92009  */
92010 #define TMU_TER_EN(x)                            (((uint32_t)(((uint32_t)(x)) << TMU_TER_EN_SHIFT)) & TMU_TER_EN_MASK)
92011 /*! @} */
92012 
92013 /*! @name TPS - TMU Probe Select register */
92014 /*! @{ */
92015 
92016 #define TMU_TPS_PROBE_SEL_MASK                   (0xC0000000U)
92017 #define TMU_TPS_PROBE_SEL_SHIFT                  (30U)
92018 /*! PROBE_SEL
92019  *  0b00..select the main probe only
92020  *  0b01..select the remote probe(near A53) only
92021  *  0b1x..select both 2 probes
92022  */
92023 #define TMU_TPS_PROBE_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TPS_PROBE_SEL_SHIFT)) & TMU_TPS_PROBE_SEL_MASK)
92024 /*! @} */
92025 
92026 /*! @name TIER - TMU Interrupt Enable register */
92027 /*! @{ */
92028 
92029 #define TMU_TIER_ATCTEIE0_MASK                   (0x2000000U)
92030 #define TMU_TIER_ATCTEIE0_SHIFT                  (25U)
92031 /*! ATCTEIE0
92032  *  0b0..Disabled.
92033  *  0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
92034  */
92035 #define TMU_TIER_ATCTEIE0(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE0_SHIFT)) & TMU_TIER_ATCTEIE0_MASK)
92036 
92037 #define TMU_TIER_ATTEIE0_MASK                    (0x4000000U)
92038 #define TMU_TIER_ATTEIE0_SHIFT                   (26U)
92039 /*! ATTEIE0
92040  *  0b0..Disabled.
92041  *  0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
92042  */
92043 #define TMU_TIER_ATTEIE0(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE0_SHIFT)) & TMU_TIER_ATTEIE0_MASK)
92044 
92045 #define TMU_TIER_ITTEIE0_MASK                    (0x8000000U)
92046 #define TMU_TIER_ITTEIE0_SHIFT                   (27U)
92047 /*! ITTEIE0
92048  *  0b0..Disabled.
92049  *  0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
92050  */
92051 #define TMU_TIER_ITTEIE0(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE0_SHIFT)) & TMU_TIER_ITTEIE0_MASK)
92052 
92053 #define TMU_TIER_ATCTEIE1_MASK                   (0x20000000U)
92054 #define TMU_TIER_ATCTEIE1_SHIFT                  (29U)
92055 /*! ATCTEIE1
92056  *  0b0..Disabled.
92057  *  0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
92058  */
92059 #define TMU_TIER_ATCTEIE1(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE1_SHIFT)) & TMU_TIER_ATCTEIE1_MASK)
92060 
92061 #define TMU_TIER_ATTEIE1_MASK                    (0x40000000U)
92062 #define TMU_TIER_ATTEIE1_SHIFT                   (30U)
92063 /*! ATTEIE1
92064  *  0b0..Disabled.
92065  *  0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
92066  */
92067 #define TMU_TIER_ATTEIE1(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE1_SHIFT)) & TMU_TIER_ATTEIE1_MASK)
92068 
92069 #define TMU_TIER_ITTEIE1_MASK                    (0x80000000U)
92070 #define TMU_TIER_ITTEIE1_SHIFT                   (31U)
92071 /*! ITTEIE1
92072  *  0b0..Disabled.
92073  *  0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
92074  */
92075 #define TMU_TIER_ITTEIE1(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE1_SHIFT)) & TMU_TIER_ITTEIE1_MASK)
92076 /*! @} */
92077 
92078 /*! @name TIDR - TMU Interrupt Detect register */
92079 /*! @{ */
92080 
92081 #define TMU_TIDR_ATCTE0_MASK                     (0x2000000U)
92082 #define TMU_TIDR_ATCTE0_SHIFT                    (25U)
92083 /*! ATCTE0
92084  *  0b0..No threshold exceeded.
92085  *  0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
92086  */
92087 #define TMU_TIDR_ATCTE0(x)                       (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE0_SHIFT)) & TMU_TIDR_ATCTE0_MASK)
92088 
92089 #define TMU_TIDR_ATTE0_MASK                      (0x4000000U)
92090 #define TMU_TIDR_ATTE0_SHIFT                     (26U)
92091 /*! ATTE0
92092  *  0b0..No threshold exceeded.
92093  *  0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded.
92094  */
92095 #define TMU_TIDR_ATTE0(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE0_SHIFT)) & TMU_TIDR_ATTE0_MASK)
92096 
92097 #define TMU_TIDR_ITTE0_MASK                      (0x8000000U)
92098 #define TMU_TIDR_ITTE0_SHIFT                     (27U)
92099 /*! ITTE0
92100  *  0b0..No threshold exceeded.
92101  *  0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-of-range
92102  *       measured temperature above 125 degree C.
92103  */
92104 #define TMU_TIDR_ITTE0(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE0_SHIFT)) & TMU_TIDR_ITTE0_MASK)
92105 
92106 #define TMU_TIDR_ATCTE1_MASK                     (0x20000000U)
92107 #define TMU_TIDR_ATCTE1_SHIFT                    (29U)
92108 /*! ATCTE1
92109  *  0b0..No threshold exceeded.
92110  *  0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
92111  */
92112 #define TMU_TIDR_ATCTE1(x)                       (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE1_SHIFT)) & TMU_TIDR_ATCTE1_MASK)
92113 
92114 #define TMU_TIDR_ATTE1_MASK                      (0x40000000U)
92115 #define TMU_TIDR_ATTE1_SHIFT                     (30U)
92116 /*! ATTE1
92117  *  0b0..No threshold exceeded.
92118  *  0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded.
92119  */
92120 #define TMU_TIDR_ATTE1(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE1_SHIFT)) & TMU_TIDR_ATTE1_MASK)
92121 
92122 #define TMU_TIDR_ITTE1_MASK                      (0x80000000U)
92123 #define TMU_TIDR_ITTE1_SHIFT                     (31U)
92124 /*! ITTE1
92125  *  0b0..No threshold exceeded.
92126  *  0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-of-range
92127  *       measured temperature above 125 degree C.
92128  */
92129 #define TMU_TIDR_ITTE1(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE1_SHIFT)) & TMU_TIDR_ITTE1_MASK)
92130 /*! @} */
92131 
92132 /*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */
92133 /*! @{ */
92134 
92135 #define TMU_TMHTITR_TEMP0_MASK                   (0xFFU)
92136 #define TMU_TMHTITR_TEMP0_SHIFT                  (0U)
92137 #define TMU_TMHTITR_TEMP0(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP0_SHIFT)) & TMU_TMHTITR_TEMP0_MASK)
92138 
92139 #define TMU_TMHTITR_TEMP1_MASK                   (0xFF0000U)
92140 #define TMU_TMHTITR_TEMP1_SHIFT                  (16U)
92141 #define TMU_TMHTITR_TEMP1(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP1_SHIFT)) & TMU_TMHTITR_TEMP1_MASK)
92142 
92143 #define TMU_TMHTITR_EN0_MASK                     (0x40000000U)
92144 #define TMU_TMHTITR_EN0_SHIFT                    (30U)
92145 /*! EN0
92146  *  0b0..Disabled.
92147  *  0b1..Threshold enabled.
92148  */
92149 #define TMU_TMHTITR_EN0(x)                       (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN0_SHIFT)) & TMU_TMHTITR_EN0_MASK)
92150 
92151 #define TMU_TMHTITR_EN1_MASK                     (0x80000000U)
92152 #define TMU_TMHTITR_EN1_SHIFT                    (31U)
92153 /*! EN1
92154  *  0b0..Disabled.
92155  *  0b1..Threshold enabled.
92156  */
92157 #define TMU_TMHTITR_EN1(x)                       (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN1_SHIFT)) & TMU_TMHTITR_EN1_MASK)
92158 /*! @} */
92159 
92160 /*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */
92161 /*! @{ */
92162 
92163 #define TMU_TMHTATR_TEMP0_MASK                   (0xFFU)
92164 #define TMU_TMHTATR_TEMP0_SHIFT                  (0U)
92165 #define TMU_TMHTATR_TEMP0(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP0_SHIFT)) & TMU_TMHTATR_TEMP0_MASK)
92166 
92167 #define TMU_TMHTATR_TEMP1_MASK                   (0xFF0000U)
92168 #define TMU_TMHTATR_TEMP1_SHIFT                  (16U)
92169 #define TMU_TMHTATR_TEMP1(x)                     (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP1_SHIFT)) & TMU_TMHTATR_TEMP1_MASK)
92170 
92171 #define TMU_TMHTATR_EN0_MASK                     (0x40000000U)
92172 #define TMU_TMHTATR_EN0_SHIFT                    (30U)
92173 /*! EN0
92174  *  0b0..Disabled.
92175  *  0b1..Threshold enabled.
92176  */
92177 #define TMU_TMHTATR_EN0(x)                       (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN0_SHIFT)) & TMU_TMHTATR_EN0_MASK)
92178 
92179 #define TMU_TMHTATR_EN1_MASK                     (0x80000000U)
92180 #define TMU_TMHTATR_EN1_SHIFT                    (31U)
92181 /*! EN1
92182  *  0b0..Disabled.
92183  *  0b1..Threshold enabled.
92184  */
92185 #define TMU_TMHTATR_EN1(x)                       (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN1_SHIFT)) & TMU_TMHTATR_EN1_MASK)
92186 /*! @} */
92187 
92188 /*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */
92189 /*! @{ */
92190 
92191 #define TMU_TMHTACTR_TEMP0_MASK                  (0xFFU)
92192 #define TMU_TMHTACTR_TEMP0_SHIFT                 (0U)
92193 #define TMU_TMHTACTR_TEMP0(x)                    (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP0_SHIFT)) & TMU_TMHTACTR_TEMP0_MASK)
92194 
92195 #define TMU_TMHTACTR_TEMP1_MASK                  (0xFF0000U)
92196 #define TMU_TMHTACTR_TEMP1_SHIFT                 (16U)
92197 #define TMU_TMHTACTR_TEMP1(x)                    (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP1_SHIFT)) & TMU_TMHTACTR_TEMP1_MASK)
92198 
92199 #define TMU_TMHTACTR_EN0_MASK                    (0x40000000U)
92200 #define TMU_TMHTACTR_EN0_SHIFT                   (30U)
92201 /*! EN0
92202  *  0b0..Disabled.
92203  *  0b1..Threshold enabled.
92204  */
92205 #define TMU_TMHTACTR_EN0(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN0_SHIFT)) & TMU_TMHTACTR_EN0_MASK)
92206 
92207 #define TMU_TMHTACTR_EN1_MASK                    (0x80000000U)
92208 #define TMU_TMHTACTR_EN1_SHIFT                   (31U)
92209 /*! EN1
92210  *  0b0..Disabled.
92211  *  0b1..Threshold enabled.
92212  */
92213 #define TMU_TMHTACTR_EN1(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN1_SHIFT)) & TMU_TMHTACTR_EN1_MASK)
92214 /*! @} */
92215 
92216 /*! @name TSCR - TMU Sensor Calibration register */
92217 /*! @{ */
92218 
92219 #define TMU_TSCR_SNSR0_MASK                      (0xFFFU)
92220 #define TMU_TSCR_SNSR0_SHIFT                     (0U)
92221 #define TMU_TSCR_SNSR0(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_SNSR0_SHIFT)) & TMU_TSCR_SNSR0_MASK)
92222 
92223 #define TMU_TSCR_SNSR1_MASK                      (0xFFF0000U)
92224 #define TMU_TSCR_SNSR1_SHIFT                     (16U)
92225 #define TMU_TSCR_SNSR1(x)                        (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_SNSR1_SHIFT)) & TMU_TSCR_SNSR1_MASK)
92226 
92227 #define TMU_TSCR_V0_MASK                         (0x40000000U)
92228 #define TMU_TSCR_V0_SHIFT                        (30U)
92229 /*! V0
92230  *  0b0..Not ready. First measurement still pending.
92231  *  0b1..Ready. Extra 1us delay is needed to read the first [SNSR0] value after this bit is set.
92232  */
92233 #define TMU_TSCR_V0(x)                           (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_V0_SHIFT)) & TMU_TSCR_V0_MASK)
92234 
92235 #define TMU_TSCR_V1_MASK                         (0x80000000U)
92236 #define TMU_TSCR_V1_SHIFT                        (31U)
92237 /*! V1
92238  *  0b0..Not ready. First measurement still pending.
92239  *  0b1..Ready. Extra 1us delay is needed to read the first [SNSR1] value after this bit is set.
92240  */
92241 #define TMU_TSCR_V1(x)                           (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_V1_SHIFT)) & TMU_TSCR_V1_MASK)
92242 /*! @} */
92243 
92244 /*! @name TRITSR - TMU Report Immediate Temperature Site register n */
92245 /*! @{ */
92246 
92247 #define TMU_TRITSR_TEMP0_MASK                    (0xFFU)
92248 #define TMU_TRITSR_TEMP0_SHIFT                   (0U)
92249 #define TMU_TRITSR_TEMP0(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP0_SHIFT)) & TMU_TRITSR_TEMP0_MASK)
92250 
92251 #define TMU_TRITSR_TEMP1_MASK                    (0xFF0000U)
92252 #define TMU_TRITSR_TEMP1_SHIFT                   (16U)
92253 #define TMU_TRITSR_TEMP1(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP1_SHIFT)) & TMU_TRITSR_TEMP1_MASK)
92254 
92255 #define TMU_TRITSR_V0_MASK                       (0x40000000U)
92256 #define TMU_TRITSR_V0_SHIFT                      (30U)
92257 /*! V0
92258  *  0b0..Not ready. First measurement still pending.
92259  *  0b1..Ready. Extra 1us delay is needed to read the first [TEMP0] value after this bit is set.
92260  */
92261 #define TMU_TRITSR_V0(x)                         (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V0_SHIFT)) & TMU_TRITSR_V0_MASK)
92262 
92263 #define TMU_TRITSR_V1_MASK                       (0x80000000U)
92264 #define TMU_TRITSR_V1_SHIFT                      (31U)
92265 /*! V1
92266  *  0b0..Not ready. First measurement still pending.
92267  *  0b1..Ready. Extra 1us delay is needed to read the first [TEMP1] value after this bit is set.
92268  */
92269 #define TMU_TRITSR_V1(x)                         (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V1_SHIFT)) & TMU_TRITSR_V1_MASK)
92270 /*! @} */
92271 
92272 /*! @name TRATSR - TMU Report Average Temperature Site register n */
92273 /*! @{ */
92274 
92275 #define TMU_TRATSR_TEMP0_MASK                    (0xFFU)
92276 #define TMU_TRATSR_TEMP0_SHIFT                   (0U)
92277 #define TMU_TRATSR_TEMP0(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP0_SHIFT)) & TMU_TRATSR_TEMP0_MASK)
92278 
92279 #define TMU_TRATSR_TEMP1_MASK                    (0xFF0000U)
92280 #define TMU_TRATSR_TEMP1_SHIFT                   (16U)
92281 #define TMU_TRATSR_TEMP1(x)                      (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP1_SHIFT)) & TMU_TRATSR_TEMP1_MASK)
92282 
92283 #define TMU_TRATSR_V0_MASK                       (0x40000000U)
92284 #define TMU_TRATSR_V0_SHIFT                      (30U)
92285 /*! V0
92286  *  0b0..Not ready. First measurement still pending.
92287  *  0b1..Ready. Extra 1us delay is needed to read the first [TEMP0] value after this bit is set.
92288  */
92289 #define TMU_TRATSR_V0(x)                         (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V0_SHIFT)) & TMU_TRATSR_V0_MASK)
92290 
92291 #define TMU_TRATSR_V1_MASK                       (0x80000000U)
92292 #define TMU_TRATSR_V1_SHIFT                      (31U)
92293 /*! V1
92294  *  0b0..Not ready. First measurement still pending.
92295  *  0b1..Ready. Extra 1us delay is needed to read the first [TEMP1] value after this bit is set.
92296  */
92297 #define TMU_TRATSR_V1(x)                         (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V1_SHIFT)) & TMU_TRATSR_V1_MASK)
92298 /*! @} */
92299 
92300 
92301 /*!
92302  * @}
92303  */ /* end of group TMU_Register_Masks */
92304 
92305 
92306 /* TMU - Peripheral instance base addresses */
92307 /** Peripheral TMU base address */
92308 #define TMU_BASE                                 (0x30260000u)
92309 /** Peripheral TMU base pointer */
92310 #define TMU                                      ((TMU_Type *)TMU_BASE)
92311 /** Array initializer of TMU peripheral base addresses */
92312 #define TMU_BASE_ADDRS                           { TMU_BASE }
92313 /** Array initializer of TMU peripheral base pointers */
92314 #define TMU_BASE_PTRS                            { TMU }
92315 
92316 /*!
92317  * @}
92318  */ /* end of group TMU_Peripheral_Access_Layer */
92319 
92320 
92321 /* ----------------------------------------------------------------------------
92322    -- UART Peripheral Access Layer
92323    ---------------------------------------------------------------------------- */
92324 
92325 /*!
92326  * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
92327  * @{
92328  */
92329 
92330 /** UART - Register Layout Typedef */
92331 typedef struct {
92332   __I  uint32_t URXD;                              /**< UART Receiver Register, offset: 0x0 */
92333        uint8_t RESERVED_0[60];
92334   __O  uint32_t UTXD;                              /**< UART Transmitter Register, offset: 0x40 */
92335        uint8_t RESERVED_1[60];
92336   __IO uint32_t UCR1;                              /**< UART Control Register 1, offset: 0x80 */
92337   __IO uint32_t UCR2;                              /**< UART Control Register 2, offset: 0x84 */
92338   __IO uint32_t UCR3;                              /**< UART Control Register 3, offset: 0x88 */
92339   __IO uint32_t UCR4;                              /**< UART Control Register 4, offset: 0x8C */
92340   __IO uint32_t UFCR;                              /**< UART FIFO Control Register, offset: 0x90 */
92341   __IO uint32_t USR1;                              /**< UART Status Register 1, offset: 0x94 */
92342   __IO uint32_t USR2;                              /**< UART Status Register 2, offset: 0x98 */
92343   __IO uint32_t UESC;                              /**< UART Escape Character Register, offset: 0x9C */
92344   __IO uint32_t UTIM;                              /**< UART Escape Timer Register, offset: 0xA0 */
92345   __IO uint32_t UBIR;                              /**< UART BRM Incremental Register, offset: 0xA4 */
92346   __IO uint32_t UBMR;                              /**< UART BRM Modulator Register, offset: 0xA8 */
92347   __I  uint32_t UBRC;                              /**< UART Baud Rate Count Register, offset: 0xAC */
92348   __IO uint32_t ONEMS;                             /**< UART One Millisecond Register, offset: 0xB0 */
92349   __IO uint32_t UTS;                               /**< UART Test Register, offset: 0xB4 */
92350   __IO uint32_t UMCR;                              /**< UART RS-485 Mode Control Register, offset: 0xB8 */
92351 } UART_Type;
92352 
92353 /* ----------------------------------------------------------------------------
92354    -- UART Register Masks
92355    ---------------------------------------------------------------------------- */
92356 
92357 /*!
92358  * @addtogroup UART_Register_Masks UART Register Masks
92359  * @{
92360  */
92361 
92362 /*! @name URXD - UART Receiver Register */
92363 /*! @{ */
92364 
92365 #define UART_URXD_RX_DATA_MASK                   (0xFFU)
92366 #define UART_URXD_RX_DATA_SHIFT                  (0U)
92367 #define UART_URXD_RX_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK)
92368 
92369 #define UART_URXD_PRERR_MASK                     (0x400U)
92370 #define UART_URXD_PRERR_SHIFT                    (10U)
92371 /*! PRERR
92372  *  0b0..= No parity error was detected for data in the RX_DATA field
92373  *  0b1..= A parity error was detected for data in the RX_DATA field
92374  */
92375 #define UART_URXD_PRERR(x)                       (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK)
92376 
92377 #define UART_URXD_BRK_MASK                       (0x800U)
92378 #define UART_URXD_BRK_SHIFT                      (11U)
92379 /*! BRK
92380  *  0b0..The current character is not a BREAK character
92381  *  0b1..The current character is a BREAK character
92382  */
92383 #define UART_URXD_BRK(x)                         (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK)
92384 
92385 #define UART_URXD_FRMERR_MASK                    (0x1000U)
92386 #define UART_URXD_FRMERR_SHIFT                   (12U)
92387 /*! FRMERR
92388  *  0b0..The current character has no framing error
92389  *  0b1..The current character has a framing error
92390  */
92391 #define UART_URXD_FRMERR(x)                      (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK)
92392 
92393 #define UART_URXD_OVRRUN_MASK                    (0x2000U)
92394 #define UART_URXD_OVRRUN_SHIFT                   (13U)
92395 /*! OVRRUN
92396  *  0b0..No RxFIFO overrun was detected
92397  *  0b1..A RxFIFO overrun was detected
92398  */
92399 #define UART_URXD_OVRRUN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK)
92400 
92401 #define UART_URXD_ERR_MASK                       (0x4000U)
92402 #define UART_URXD_ERR_SHIFT                      (14U)
92403 /*! ERR
92404  *  0b0..No error status was detected
92405  *  0b1..An error status was detected
92406  */
92407 #define UART_URXD_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK)
92408 
92409 #define UART_URXD_CHARRDY_MASK                   (0x8000U)
92410 #define UART_URXD_CHARRDY_SHIFT                  (15U)
92411 /*! CHARRDY
92412  *  0b0..Character in RX_DATA field and associated flags are invalid.
92413  *  0b1..Character in RX_DATA field and associated flags valid and ready for reading.
92414  */
92415 #define UART_URXD_CHARRDY(x)                     (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK)
92416 /*! @} */
92417 
92418 /*! @name UTXD - UART Transmitter Register */
92419 /*! @{ */
92420 
92421 #define UART_UTXD_TX_DATA_MASK                   (0xFFU)
92422 #define UART_UTXD_TX_DATA_SHIFT                  (0U)
92423 #define UART_UTXD_TX_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK)
92424 /*! @} */
92425 
92426 /*! @name UCR1 - UART Control Register 1 */
92427 /*! @{ */
92428 
92429 #define UART_UCR1_UARTEN_MASK                    (0x1U)
92430 #define UART_UCR1_UARTEN_SHIFT                   (0U)
92431 /*! UARTEN
92432  *  0b0..Disable the UART
92433  *  0b1..Enable the UART
92434  */
92435 #define UART_UCR1_UARTEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK)
92436 
92437 #define UART_UCR1_DOZE_MASK                      (0x2U)
92438 #define UART_UCR1_DOZE_SHIFT                     (1U)
92439 /*! DOZE
92440  *  0b0..The UART is enabled when in DOZE state
92441  *  0b1..The UART is disabled when in DOZE state
92442  */
92443 #define UART_UCR1_DOZE(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK)
92444 
92445 #define UART_UCR1_ATDMAEN_MASK                   (0x4U)
92446 #define UART_UCR1_ATDMAEN_SHIFT                  (2U)
92447 /*! ATDMAEN
92448  *  0b0..Disable AGTIM DMA request
92449  *  0b1..Enable AGTIM DMA request
92450  */
92451 #define UART_UCR1_ATDMAEN(x)                     (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK)
92452 
92453 #define UART_UCR1_TXDMAEN_MASK                   (0x8U)
92454 #define UART_UCR1_TXDMAEN_SHIFT                  (3U)
92455 /*! TXDMAEN
92456  *  0b0..Disable transmit DMA request
92457  *  0b1..Enable transmit DMA request
92458  */
92459 #define UART_UCR1_TXDMAEN(x)                     (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK)
92460 
92461 #define UART_UCR1_SNDBRK_MASK                    (0x10U)
92462 #define UART_UCR1_SNDBRK_SHIFT                   (4U)
92463 /*! SNDBRK
92464  *  0b0..Do not send a BREAK character
92465  *  0b1..Send a BREAK character (continuous 0s)
92466  */
92467 #define UART_UCR1_SNDBRK(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK)
92468 
92469 #define UART_UCR1_RTSDEN_MASK                    (0x20U)
92470 #define UART_UCR1_RTSDEN_SHIFT                   (5U)
92471 /*! RTSDEN
92472  *  0b0..Disable RTSD interrupt
92473  *  0b1..Enable RTSD interrupt
92474  */
92475 #define UART_UCR1_RTSDEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK)
92476 
92477 #define UART_UCR1_TXMPTYEN_MASK                  (0x40U)
92478 #define UART_UCR1_TXMPTYEN_SHIFT                 (6U)
92479 /*! TXMPTYEN
92480  *  0b0..Disable the transmitter FIFO empty interrupt
92481  *  0b1..Enable the transmitter FIFO empty interrupt
92482  */
92483 #define UART_UCR1_TXMPTYEN(x)                    (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK)
92484 
92485 #define UART_UCR1_IREN_MASK                      (0x80U)
92486 #define UART_UCR1_IREN_SHIFT                     (7U)
92487 /*! IREN
92488  *  0b0..Disable the IR interface
92489  *  0b1..Enable the IR interface
92490  */
92491 #define UART_UCR1_IREN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK)
92492 
92493 #define UART_UCR1_RXDMAEN_MASK                   (0x100U)
92494 #define UART_UCR1_RXDMAEN_SHIFT                  (8U)
92495 /*! RXDMAEN
92496  *  0b0..Disable DMA request
92497  *  0b1..Enable DMA request
92498  */
92499 #define UART_UCR1_RXDMAEN(x)                     (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK)
92500 
92501 #define UART_UCR1_RRDYEN_MASK                    (0x200U)
92502 #define UART_UCR1_RRDYEN_SHIFT                   (9U)
92503 /*! RRDYEN
92504  *  0b0..Disables the RRDY interrupt
92505  *  0b1..Enables the RRDY interrupt
92506  */
92507 #define UART_UCR1_RRDYEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK)
92508 
92509 #define UART_UCR1_ICD_MASK                       (0xC00U)
92510 #define UART_UCR1_ICD_SHIFT                      (10U)
92511 /*! ICD
92512  *  0b00..Idle for more than 4 frames
92513  *  0b01..Idle for more than 8 frames
92514  *  0b10..Idle for more than 16 frames
92515  *  0b11..Idle for more than 32 frames
92516  */
92517 #define UART_UCR1_ICD(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK)
92518 
92519 #define UART_UCR1_IDEN_MASK                      (0x1000U)
92520 #define UART_UCR1_IDEN_SHIFT                     (12U)
92521 /*! IDEN
92522  *  0b0..Disable the IDLE interrupt
92523  *  0b1..Enable the IDLE interrupt
92524  */
92525 #define UART_UCR1_IDEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK)
92526 
92527 #define UART_UCR1_TRDYEN_MASK                    (0x2000U)
92528 #define UART_UCR1_TRDYEN_SHIFT                   (13U)
92529 /*! TRDYEN
92530  *  0b0..Disable the transmitter ready interrupt
92531  *  0b1..Enable the transmitter ready interrupt
92532  */
92533 #define UART_UCR1_TRDYEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK)
92534 
92535 #define UART_UCR1_ADBR_MASK                      (0x4000U)
92536 #define UART_UCR1_ADBR_SHIFT                     (14U)
92537 /*! ADBR
92538  *  0b0..Disable automatic detection of baud rate
92539  *  0b1..Enable automatic detection of baud rate
92540  */
92541 #define UART_UCR1_ADBR(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK)
92542 
92543 #define UART_UCR1_ADEN_MASK                      (0x8000U)
92544 #define UART_UCR1_ADEN_SHIFT                     (15U)
92545 /*! ADEN
92546  *  0b0..Disable the automatic baud rate detection interrupt
92547  *  0b1..Enable the automatic baud rate detection interrupt
92548  */
92549 #define UART_UCR1_ADEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK)
92550 /*! @} */
92551 
92552 /*! @name UCR2 - UART Control Register 2 */
92553 /*! @{ */
92554 
92555 #define UART_UCR2_SRST_MASK                      (0x1U)
92556 #define UART_UCR2_SRST_SHIFT                     (0U)
92557 /*! SRST
92558  *  0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3].
92559  *  0b1..No reset
92560  */
92561 #define UART_UCR2_SRST(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK)
92562 
92563 #define UART_UCR2_RXEN_MASK                      (0x2U)
92564 #define UART_UCR2_RXEN_SHIFT                     (1U)
92565 /*! RXEN
92566  *  0b0..Disable the receiver
92567  *  0b1..Enable the receiver
92568  */
92569 #define UART_UCR2_RXEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK)
92570 
92571 #define UART_UCR2_TXEN_MASK                      (0x4U)
92572 #define UART_UCR2_TXEN_SHIFT                     (2U)
92573 /*! TXEN
92574  *  0b0..Disable the transmitter
92575  *  0b1..Enable the transmitter
92576  */
92577 #define UART_UCR2_TXEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK)
92578 
92579 #define UART_UCR2_ATEN_MASK                      (0x8U)
92580 #define UART_UCR2_ATEN_SHIFT                     (3U)
92581 /*! ATEN
92582  *  0b0..AGTIM interrupt disabled
92583  *  0b1..AGTIM interrupt enabled
92584  */
92585 #define UART_UCR2_ATEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK)
92586 
92587 #define UART_UCR2_RTSEN_MASK                     (0x10U)
92588 #define UART_UCR2_RTSEN_SHIFT                    (4U)
92589 /*! RTSEN
92590  *  0b0..Disable request to send interrupt
92591  *  0b1..Enable request to send interrupt
92592  */
92593 #define UART_UCR2_RTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK)
92594 
92595 #define UART_UCR2_WS_MASK                        (0x20U)
92596 #define UART_UCR2_WS_SHIFT                       (5U)
92597 /*! WS
92598  *  0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits)
92599  *  0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits)
92600  */
92601 #define UART_UCR2_WS(x)                          (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK)
92602 
92603 #define UART_UCR2_STPB_MASK                      (0x40U)
92604 #define UART_UCR2_STPB_SHIFT                     (6U)
92605 /*! STPB
92606  *  0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits.
92607  *  0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits.
92608  */
92609 #define UART_UCR2_STPB(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK)
92610 
92611 #define UART_UCR2_PROE_MASK                      (0x80U)
92612 #define UART_UCR2_PROE_SHIFT                     (7U)
92613 /*! PROE
92614  *  0b0..Even parity
92615  *  0b1..Odd parity
92616  */
92617 #define UART_UCR2_PROE(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK)
92618 
92619 #define UART_UCR2_PREN_MASK                      (0x100U)
92620 #define UART_UCR2_PREN_SHIFT                     (8U)
92621 /*! PREN
92622  *  0b0..Disable parity generator and checker
92623  *  0b1..Enable parity generator and checker
92624  */
92625 #define UART_UCR2_PREN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK)
92626 
92627 #define UART_UCR2_RTEC_MASK                      (0x600U)
92628 #define UART_UCR2_RTEC_SHIFT                     (9U)
92629 /*! RTEC
92630  *  0b00..Trigger interrupt on a rising edge
92631  *  0b01..Trigger interrupt on a falling edge
92632  *  0b1x..Trigger interrupt on any edge
92633  */
92634 #define UART_UCR2_RTEC(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK)
92635 
92636 #define UART_UCR2_ESCEN_MASK                     (0x800U)
92637 #define UART_UCR2_ESCEN_SHIFT                    (11U)
92638 /*! ESCEN
92639  *  0b0..Disable escape sequence detection
92640  *  0b1..Enable escape sequence detection
92641  */
92642 #define UART_UCR2_ESCEN(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK)
92643 
92644 #define UART_UCR2_CTS_MASK                       (0x1000U)
92645 #define UART_UCR2_CTS_SHIFT                      (12U)
92646 /*! CTS
92647  *  0b0..The CTS_B pin is high (inactive)
92648  *  0b1..The CTS_B pin is low (active)
92649  */
92650 #define UART_UCR2_CTS(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK)
92651 
92652 #define UART_UCR2_CTSC_MASK                      (0x2000U)
92653 #define UART_UCR2_CTSC_SHIFT                     (13U)
92654 /*! CTSC
92655  *  0b0..The CTS_B pin is controlled by the CTS bit
92656  *  0b1..The CTS_B pin is controlled by the receiver
92657  */
92658 #define UART_UCR2_CTSC(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK)
92659 
92660 #define UART_UCR2_IRTS_MASK                      (0x4000U)
92661 #define UART_UCR2_IRTS_SHIFT                     (14U)
92662 /*! IRTS
92663  *  0b0..Transmit only when the RTS pin is asserted
92664  *  0b1..Ignore the RTS pin
92665  */
92666 #define UART_UCR2_IRTS(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK)
92667 
92668 #define UART_UCR2_ESCI_MASK                      (0x8000U)
92669 #define UART_UCR2_ESCI_SHIFT                     (15U)
92670 /*! ESCI
92671  *  0b0..Disable the escape sequence interrupt
92672  *  0b1..Enable the escape sequence interrupt
92673  */
92674 #define UART_UCR2_ESCI(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK)
92675 /*! @} */
92676 
92677 /*! @name UCR3 - UART Control Register 3 */
92678 /*! @{ */
92679 
92680 #define UART_UCR3_ACIEN_MASK                     (0x1U)
92681 #define UART_UCR3_ACIEN_SHIFT                    (0U)
92682 /*! ACIEN
92683  *  0b0..ACST interrupt disabled
92684  *  0b1..ACST interrupt enabled
92685  */
92686 #define UART_UCR3_ACIEN(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK)
92687 
92688 #define UART_UCR3_INVT_MASK                      (0x2U)
92689 #define UART_UCR3_INVT_SHIFT                     (1U)
92690 /*! INVT
92691  *  0b0..TXD is not inverted
92692  *  0b1..TXD is inverted
92693  *  0b0..TXD Active low transmission
92694  *  0b1..TXD Active high transmission
92695  */
92696 #define UART_UCR3_INVT(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK)
92697 
92698 #define UART_UCR3_RXDMUXSEL_MASK                 (0x4U)
92699 #define UART_UCR3_RXDMUXSEL_SHIFT                (2U)
92700 #define UART_UCR3_RXDMUXSEL(x)                   (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK)
92701 
92702 #define UART_UCR3_DTRDEN_MASK                    (0x8U)
92703 #define UART_UCR3_DTRDEN_SHIFT                   (3U)
92704 #define UART_UCR3_DTRDEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK)
92705 
92706 #define UART_UCR3_AWAKEN_MASK                    (0x10U)
92707 #define UART_UCR3_AWAKEN_SHIFT                   (4U)
92708 /*! AWAKEN
92709  *  0b0..Disable the AWAKE interrupt
92710  *  0b1..Enable the AWAKE interrupt
92711  */
92712 #define UART_UCR3_AWAKEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK)
92713 
92714 #define UART_UCR3_AIRINTEN_MASK                  (0x20U)
92715 #define UART_UCR3_AIRINTEN_SHIFT                 (5U)
92716 /*! AIRINTEN
92717  *  0b0..Disable the AIRINT interrupt
92718  *  0b1..Enable the AIRINT interrupt
92719  */
92720 #define UART_UCR3_AIRINTEN(x)                    (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK)
92721 
92722 #define UART_UCR3_RXDSEN_MASK                    (0x40U)
92723 #define UART_UCR3_RXDSEN_SHIFT                   (6U)
92724 /*! RXDSEN
92725  *  0b0..Disable the RXDS interrupt
92726  *  0b1..Enable the RXDS interrupt
92727  */
92728 #define UART_UCR3_RXDSEN(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK)
92729 
92730 #define UART_UCR3_ADNIMP_MASK                    (0x80U)
92731 #define UART_UCR3_ADNIMP_SHIFT                   (7U)
92732 /*! ADNIMP
92733  *  0b0..Autobaud detection new features selected
92734  *  0b1..Keep old autobaud detection mechanism
92735  */
92736 #define UART_UCR3_ADNIMP(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK)
92737 
92738 #define UART_UCR3_RI_MASK                        (0x100U)
92739 #define UART_UCR3_RI_SHIFT                       (8U)
92740 #define UART_UCR3_RI(x)                          (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK)
92741 
92742 #define UART_UCR3_DCD_MASK                       (0x200U)
92743 #define UART_UCR3_DCD_SHIFT                      (9U)
92744 #define UART_UCR3_DCD(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK)
92745 
92746 #define UART_UCR3_DSR_MASK                       (0x400U)
92747 #define UART_UCR3_DSR_SHIFT                      (10U)
92748 #define UART_UCR3_DSR(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK)
92749 
92750 #define UART_UCR3_FRAERREN_MASK                  (0x800U)
92751 #define UART_UCR3_FRAERREN_SHIFT                 (11U)
92752 /*! FRAERREN
92753  *  0b0..Disable the frame error interrupt
92754  *  0b1..Enable the frame error interrupt
92755  */
92756 #define UART_UCR3_FRAERREN(x)                    (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK)
92757 
92758 #define UART_UCR3_PARERREN_MASK                  (0x1000U)
92759 #define UART_UCR3_PARERREN_SHIFT                 (12U)
92760 /*! PARERREN
92761  *  0b0..Disable the parity error interrupt
92762  *  0b1..Enable the parity error interrupt
92763  */
92764 #define UART_UCR3_PARERREN(x)                    (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK)
92765 
92766 #define UART_UCR3_DTREN_MASK                     (0x2000U)
92767 #define UART_UCR3_DTREN_SHIFT                    (13U)
92768 #define UART_UCR3_DTREN(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK)
92769 
92770 #define UART_UCR3_DPEC_MASK                      (0xC000U)
92771 #define UART_UCR3_DPEC_SHIFT                     (14U)
92772 #define UART_UCR3_DPEC(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK)
92773 /*! @} */
92774 
92775 /*! @name UCR4 - UART Control Register 4 */
92776 /*! @{ */
92777 
92778 #define UART_UCR4_DREN_MASK                      (0x1U)
92779 #define UART_UCR4_DREN_SHIFT                     (0U)
92780 /*! DREN
92781  *  0b0..Disable RDR interrupt
92782  *  0b1..Enable RDR interrupt
92783  */
92784 #define UART_UCR4_DREN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK)
92785 
92786 #define UART_UCR4_OREN_MASK                      (0x2U)
92787 #define UART_UCR4_OREN_SHIFT                     (1U)
92788 /*! OREN
92789  *  0b0..Disable ORE interrupt
92790  *  0b1..Enable ORE interrupt
92791  */
92792 #define UART_UCR4_OREN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK)
92793 
92794 #define UART_UCR4_BKEN_MASK                      (0x4U)
92795 #define UART_UCR4_BKEN_SHIFT                     (2U)
92796 /*! BKEN
92797  *  0b0..Disable the BRCD interrupt
92798  *  0b1..Enable the BRCD interrupt
92799  */
92800 #define UART_UCR4_BKEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK)
92801 
92802 #define UART_UCR4_TCEN_MASK                      (0x8U)
92803 #define UART_UCR4_TCEN_SHIFT                     (3U)
92804 /*! TCEN
92805  *  0b0..Disable TXDC interrupt
92806  *  0b1..Enable TXDC interrupt
92807  */
92808 #define UART_UCR4_TCEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK)
92809 
92810 #define UART_UCR4_LPBYP_MASK                     (0x10U)
92811 #define UART_UCR4_LPBYP_SHIFT                    (4U)
92812 /*! LPBYP
92813  *  0b0..Low power features enabled
92814  *  0b1..Low power features disabled
92815  */
92816 #define UART_UCR4_LPBYP(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK)
92817 
92818 #define UART_UCR4_IRSC_MASK                      (0x20U)
92819 #define UART_UCR4_IRSC_SHIFT                     (5U)
92820 /*! IRSC
92821  *  0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation
92822  *  0b1..The vote logic uses the UART reference clock
92823  */
92824 #define UART_UCR4_IRSC(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK)
92825 
92826 #define UART_UCR4_IDDMAEN_MASK                   (0x40U)
92827 #define UART_UCR4_IDDMAEN_SHIFT                  (6U)
92828 /*! IDDMAEN
92829  *  0b0..DMA IDLE interrupt disabled
92830  *  0b1..DMA IDLE interrupt enabled
92831  */
92832 #define UART_UCR4_IDDMAEN(x)                     (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK)
92833 
92834 #define UART_UCR4_WKEN_MASK                      (0x80U)
92835 #define UART_UCR4_WKEN_SHIFT                     (7U)
92836 /*! WKEN
92837  *  0b0..Disable the WAKE interrupt
92838  *  0b1..Enable the WAKE interrupt
92839  */
92840 #define UART_UCR4_WKEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK)
92841 
92842 #define UART_UCR4_ENIRI_MASK                     (0x100U)
92843 #define UART_UCR4_ENIRI_SHIFT                    (8U)
92844 /*! ENIRI
92845  *  0b0..Serial infrared Interrupt disabled
92846  *  0b1..Serial infrared Interrupt enabled
92847  */
92848 #define UART_UCR4_ENIRI(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK)
92849 
92850 #define UART_UCR4_INVR_MASK                      (0x200U)
92851 #define UART_UCR4_INVR_SHIFT                     (9U)
92852 /*! INVR
92853  *  0b0..RXD input is not inverted
92854  *  0b1..RXD input is inverted
92855  *  0b0..RXD active low detection
92856  *  0b1..RXD active high detection
92857  */
92858 #define UART_UCR4_INVR(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK)
92859 
92860 #define UART_UCR4_CTSTL_MASK                     (0xFC00U)
92861 #define UART_UCR4_CTSTL_SHIFT                    (10U)
92862 /*! CTSTL
92863  *  0b000000..0 characters received
92864  *  0b000001..1 characters in the RxFIFO
92865  *  0b100000..32 characters in the RxFIFO (maximum)
92866  */
92867 #define UART_UCR4_CTSTL(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK)
92868 /*! @} */
92869 
92870 /*! @name UFCR - UART FIFO Control Register */
92871 /*! @{ */
92872 
92873 #define UART_UFCR_RXTL_MASK                      (0x3FU)
92874 #define UART_UFCR_RXTL_SHIFT                     (0U)
92875 /*! RXTL
92876  *  0b000000..0 characters received
92877  *  0b000001..RxFIFO has 1 character
92878  *  0b011111..RxFIFO has 31 characters
92879  *  0b100000..RxFIFO has 32 characters (maximum)
92880  */
92881 #define UART_UFCR_RXTL(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK)
92882 
92883 #define UART_UFCR_DCEDTE_MASK                    (0x40U)
92884 #define UART_UFCR_DCEDTE_SHIFT                   (6U)
92885 /*! DCEDTE
92886  *  0b0..DCE mode selected
92887  *  0b1..DTE mode selected
92888  */
92889 #define UART_UFCR_DCEDTE(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK)
92890 
92891 #define UART_UFCR_RFDIV_MASK                     (0x380U)
92892 #define UART_UFCR_RFDIV_SHIFT                    (7U)
92893 /*! RFDIV
92894  *  0b000..Divide input clock by 6
92895  *  0b001..Divide input clock by 5
92896  *  0b010..Divide input clock by 4
92897  *  0b011..Divide input clock by 3
92898  *  0b100..Divide input clock by 2
92899  *  0b101..Divide input clock by 1
92900  *  0b110..Divide input clock by 7
92901  *  0b111..Reserved
92902  */
92903 #define UART_UFCR_RFDIV(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK)
92904 
92905 #define UART_UFCR_TXTL_MASK                      (0xFC00U)
92906 #define UART_UFCR_TXTL_SHIFT                     (10U)
92907 /*! TXTL
92908  *  0b000000..Reserved
92909  *  0b000001..Reserved
92910  *  0b000010..TxFIFO has 2 or fewer characters
92911  *  0b011111..TxFIFO has 31 or fewer characters
92912  *  0b100000..TxFIFO has 32 characters (maximum)
92913  */
92914 #define UART_UFCR_TXTL(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK)
92915 /*! @} */
92916 
92917 /*! @name USR1 - UART Status Register 1 */
92918 /*! @{ */
92919 
92920 #define UART_USR1_SAD_MASK                       (0x8U)
92921 #define UART_USR1_SAD_SHIFT                      (3U)
92922 /*! SAD
92923  *  0b0..No slave address detected
92924  *  0b1..Slave address detected
92925  */
92926 #define UART_USR1_SAD(x)                         (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK)
92927 
92928 #define UART_USR1_AWAKE_MASK                     (0x10U)
92929 #define UART_USR1_AWAKE_SHIFT                    (4U)
92930 /*! AWAKE
92931  *  0b0..No falling edge was detected on the RXD Serial pin
92932  *  0b1..A falling edge was detected on the RXD Serial pin
92933  */
92934 #define UART_USR1_AWAKE(x)                       (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK)
92935 
92936 #define UART_USR1_AIRINT_MASK                    (0x20U)
92937 #define UART_USR1_AIRINT_SHIFT                   (5U)
92938 /*! AIRINT
92939  *  0b0..No pulse was detected on the RXD IrDA pin
92940  *  0b1..A pulse was detected on the RXD IrDA pin
92941  */
92942 #define UART_USR1_AIRINT(x)                      (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK)
92943 
92944 #define UART_USR1_RXDS_MASK                      (0x40U)
92945 #define UART_USR1_RXDS_SHIFT                     (6U)
92946 /*! RXDS
92947  *  0b0..Receive in progress
92948  *  0b1..Receiver is IDLE
92949  */
92950 #define UART_USR1_RXDS(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK)
92951 
92952 #define UART_USR1_DTRD_MASK                      (0x80U)
92953 #define UART_USR1_DTRD_SHIFT                     (7U)
92954 #define UART_USR1_DTRD(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK)
92955 
92956 #define UART_USR1_AGTIM_MASK                     (0x100U)
92957 #define UART_USR1_AGTIM_SHIFT                    (8U)
92958 /*! AGTIM
92959  *  0b0..AGTIM is not active
92960  *  0b1..AGTIM is active (write 1 to clear)
92961  */
92962 #define UART_USR1_AGTIM(x)                       (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK)
92963 
92964 #define UART_USR1_RRDY_MASK                      (0x200U)
92965 #define UART_USR1_RRDY_SHIFT                     (9U)
92966 /*! RRDY
92967  *  0b0..No character ready
92968  *  0b1..Character(s) ready (interrupt posted)
92969  */
92970 #define UART_USR1_RRDY(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK)
92971 
92972 #define UART_USR1_FRAMERR_MASK                   (0x400U)
92973 #define UART_USR1_FRAMERR_SHIFT                  (10U)
92974 /*! FRAMERR
92975  *  0b0..No frame error detected
92976  *  0b1..Frame error detected (write 1 to clear)
92977  */
92978 #define UART_USR1_FRAMERR(x)                     (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK)
92979 
92980 #define UART_USR1_ESCF_MASK                      (0x800U)
92981 #define UART_USR1_ESCF_SHIFT                     (11U)
92982 /*! ESCF
92983  *  0b0..No escape sequence detected
92984  *  0b1..Escape sequence detected (write 1 to clear).
92985  */
92986 #define UART_USR1_ESCF(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK)
92987 
92988 #define UART_USR1_RTSD_MASK                      (0x1000U)
92989 #define UART_USR1_RTSD_SHIFT                     (12U)
92990 /*! RTSD
92991  *  0b0..RTS_B pin did not change state since last cleared
92992  *  0b1..RTS_B pin changed state (write 1 to clear)
92993  */
92994 #define UART_USR1_RTSD(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK)
92995 
92996 #define UART_USR1_TRDY_MASK                      (0x2000U)
92997 #define UART_USR1_TRDY_SHIFT                     (13U)
92998 /*! TRDY
92999  *  0b0..The transmitter does not require data
93000  *  0b1..The transmitter requires data (interrupt posted)
93001  */
93002 #define UART_USR1_TRDY(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK)
93003 
93004 #define UART_USR1_RTSS_MASK                      (0x4000U)
93005 #define UART_USR1_RTSS_SHIFT                     (14U)
93006 /*! RTSS
93007  *  0b0..The RTS_B module input is high (inactive)
93008  *  0b1..The RTS_B module input is low (active)
93009  */
93010 #define UART_USR1_RTSS(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK)
93011 
93012 #define UART_USR1_PARITYERR_MASK                 (0x8000U)
93013 #define UART_USR1_PARITYERR_SHIFT                (15U)
93014 /*! PARITYERR
93015  *  0b0..No parity error detected
93016  *  0b1..Parity error detected (write 1 to clear)
93017  */
93018 #define UART_USR1_PARITYERR(x)                   (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK)
93019 /*! @} */
93020 
93021 /*! @name USR2 - UART Status Register 2 */
93022 /*! @{ */
93023 
93024 #define UART_USR2_RDR_MASK                       (0x1U)
93025 #define UART_USR2_RDR_SHIFT                      (0U)
93026 /*! RDR
93027  *  0b0..No receive data ready
93028  *  0b1..Receive data ready
93029  */
93030 #define UART_USR2_RDR(x)                         (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK)
93031 
93032 #define UART_USR2_ORE_MASK                       (0x2U)
93033 #define UART_USR2_ORE_SHIFT                      (1U)
93034 /*! ORE
93035  *  0b0..No overrun error
93036  *  0b1..Overrun error (write 1 to clear)
93037  */
93038 #define UART_USR2_ORE(x)                         (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK)
93039 
93040 #define UART_USR2_BRCD_MASK                      (0x4U)
93041 #define UART_USR2_BRCD_SHIFT                     (2U)
93042 /*! BRCD
93043  *  0b0..No BREAK condition was detected
93044  *  0b1..A BREAK condition was detected (write 1 to clear)
93045  */
93046 #define UART_USR2_BRCD(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK)
93047 
93048 #define UART_USR2_TXDC_MASK                      (0x8U)
93049 #define UART_USR2_TXDC_SHIFT                     (3U)
93050 /*! TXDC
93051  *  0b0..Transmit is incomplete
93052  *  0b1..Transmit is complete
93053  */
93054 #define UART_USR2_TXDC(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK)
93055 
93056 #define UART_USR2_RTSF_MASK                      (0x10U)
93057 #define UART_USR2_RTSF_SHIFT                     (4U)
93058 /*! RTSF
93059  *  0b0..Programmed edge not detected on RTS_B
93060  *  0b1..Programmed edge detected on RTS_B (write 1 to clear)
93061  */
93062 #define UART_USR2_RTSF(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK)
93063 
93064 #define UART_USR2_DCDIN_MASK                     (0x20U)
93065 #define UART_USR2_DCDIN_SHIFT                    (5U)
93066 #define UART_USR2_DCDIN(x)                       (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK)
93067 
93068 #define UART_USR2_DCDDELT_MASK                   (0x40U)
93069 #define UART_USR2_DCDDELT_SHIFT                  (6U)
93070 #define UART_USR2_DCDDELT(x)                     (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK)
93071 
93072 #define UART_USR2_WAKE_MASK                      (0x80U)
93073 #define UART_USR2_WAKE_SHIFT                     (7U)
93074 /*! WAKE
93075  *  0b0..start bit not detected
93076  *  0b1..start bit detected (write 1 to clear)
93077  */
93078 #define UART_USR2_WAKE(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK)
93079 
93080 #define UART_USR2_IRINT_MASK                     (0x100U)
93081 #define UART_USR2_IRINT_SHIFT                    (8U)
93082 /*! IRINT
93083  *  0b0..no edge detected
93084  *  0b1..valid edge detected (write 1 to clear)
93085  */
93086 #define UART_USR2_IRINT(x)                       (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK)
93087 
93088 #define UART_USR2_RIIN_MASK                      (0x200U)
93089 #define UART_USR2_RIIN_SHIFT                     (9U)
93090 #define UART_USR2_RIIN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK)
93091 
93092 #define UART_USR2_RIDELT_MASK                    (0x400U)
93093 #define UART_USR2_RIDELT_SHIFT                   (10U)
93094 #define UART_USR2_RIDELT(x)                      (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK)
93095 
93096 #define UART_USR2_ACST_MASK                      (0x800U)
93097 #define UART_USR2_ACST_SHIFT                     (11U)
93098 /*! ACST
93099  *  0b0..Measurement of bit length not finished (in autobaud)
93100  *  0b1..Measurement of bit length finished (in autobaud). (write 1 to clear)
93101  */
93102 #define UART_USR2_ACST(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK)
93103 
93104 #define UART_USR2_IDLE_MASK                      (0x1000U)
93105 #define UART_USR2_IDLE_SHIFT                     (12U)
93106 /*! IDLE
93107  *  0b0..No idle condition detected
93108  *  0b1..Idle condition detected (write 1 to clear)
93109  */
93110 #define UART_USR2_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK)
93111 
93112 #define UART_USR2_DTRF_MASK                      (0x2000U)
93113 #define UART_USR2_DTRF_SHIFT                     (13U)
93114 #define UART_USR2_DTRF(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK)
93115 
93116 #define UART_USR2_TXFE_MASK                      (0x4000U)
93117 #define UART_USR2_TXFE_SHIFT                     (14U)
93118 /*! TXFE
93119  *  0b0..The transmit buffer (TxFIFO) is not empty
93120  *  0b1..The transmit buffer (TxFIFO) is empty
93121  */
93122 #define UART_USR2_TXFE(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK)
93123 
93124 #define UART_USR2_ADET_MASK                      (0x8000U)
93125 #define UART_USR2_ADET_SHIFT                     (15U)
93126 /*! ADET
93127  *  0b0..ASCII "A" or "a" was not received
93128  *  0b1..ASCII "A" or "a" was received (write 1 to clear)
93129  */
93130 #define UART_USR2_ADET(x)                        (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK)
93131 /*! @} */
93132 
93133 /*! @name UESC - UART Escape Character Register */
93134 /*! @{ */
93135 
93136 #define UART_UESC_ESC_CHAR_MASK                  (0xFFU)
93137 #define UART_UESC_ESC_CHAR_SHIFT                 (0U)
93138 #define UART_UESC_ESC_CHAR(x)                    (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK)
93139 /*! @} */
93140 
93141 /*! @name UTIM - UART Escape Timer Register */
93142 /*! @{ */
93143 
93144 #define UART_UTIM_TIM_MASK                       (0xFFFU)
93145 #define UART_UTIM_TIM_SHIFT                      (0U)
93146 #define UART_UTIM_TIM(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK)
93147 /*! @} */
93148 
93149 /*! @name UBIR - UART BRM Incremental Register */
93150 /*! @{ */
93151 
93152 #define UART_UBIR_INC_MASK                       (0xFFFFU)
93153 #define UART_UBIR_INC_SHIFT                      (0U)
93154 #define UART_UBIR_INC(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK)
93155 /*! @} */
93156 
93157 /*! @name UBMR - UART BRM Modulator Register */
93158 /*! @{ */
93159 
93160 #define UART_UBMR_MOD_MASK                       (0xFFFFU)
93161 #define UART_UBMR_MOD_SHIFT                      (0U)
93162 #define UART_UBMR_MOD(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK)
93163 /*! @} */
93164 
93165 /*! @name UBRC - UART Baud Rate Count Register */
93166 /*! @{ */
93167 
93168 #define UART_UBRC_BCNT_MASK                      (0xFFFFU)
93169 #define UART_UBRC_BCNT_SHIFT                     (0U)
93170 #define UART_UBRC_BCNT(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK)
93171 /*! @} */
93172 
93173 /*! @name ONEMS - UART One Millisecond Register */
93174 /*! @{ */
93175 
93176 #define UART_ONEMS_ONEMS_MASK                    (0xFFFFFFU)
93177 #define UART_ONEMS_ONEMS_SHIFT                   (0U)
93178 #define UART_ONEMS_ONEMS(x)                      (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK)
93179 /*! @} */
93180 
93181 /*! @name UTS - UART Test Register */
93182 /*! @{ */
93183 
93184 #define UART_UTS_SOFTRST_MASK                    (0x1U)
93185 #define UART_UTS_SOFTRST_SHIFT                   (0U)
93186 /*! SOFTRST
93187  *  0b0..Software reset inactive
93188  *  0b1..Software reset active
93189  */
93190 #define UART_UTS_SOFTRST(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK)
93191 
93192 #define UART_UTS_RXFULL_MASK                     (0x8U)
93193 #define UART_UTS_RXFULL_SHIFT                    (3U)
93194 /*! RXFULL
93195  *  0b0..The RxFIFO is not full
93196  *  0b1..The RxFIFO is full
93197  */
93198 #define UART_UTS_RXFULL(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK)
93199 
93200 #define UART_UTS_TXFULL_MASK                     (0x10U)
93201 #define UART_UTS_TXFULL_SHIFT                    (4U)
93202 /*! TXFULL
93203  *  0b0..The TxFIFO is not full
93204  *  0b1..The TxFIFO is full
93205  */
93206 #define UART_UTS_TXFULL(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK)
93207 
93208 #define UART_UTS_RXEMPTY_MASK                    (0x20U)
93209 #define UART_UTS_RXEMPTY_SHIFT                   (5U)
93210 /*! RXEMPTY
93211  *  0b0..The RxFIFO is not empty
93212  *  0b1..The RxFIFO is empty
93213  */
93214 #define UART_UTS_RXEMPTY(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK)
93215 
93216 #define UART_UTS_TXEMPTY_MASK                    (0x40U)
93217 #define UART_UTS_TXEMPTY_SHIFT                   (6U)
93218 /*! TXEMPTY
93219  *  0b0..The TxFIFO is not empty
93220  *  0b1..The TxFIFO is empty
93221  */
93222 #define UART_UTS_TXEMPTY(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK)
93223 
93224 #define UART_UTS_RXDBG_MASK                      (0x200U)
93225 #define UART_UTS_RXDBG_SHIFT                     (9U)
93226 /*! RXDBG
93227  *  0b0..rx fifo read pointer does not increment
93228  *  0b1..rx_fifo read pointer increments as normal
93229  */
93230 #define UART_UTS_RXDBG(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK)
93231 
93232 #define UART_UTS_LOOPIR_MASK                     (0x400U)
93233 #define UART_UTS_LOOPIR_SHIFT                    (10U)
93234 /*! LOOPIR
93235  *  0b0..No IR loop
93236  *  0b1..Connect IR transmitter to IR receiver
93237  */
93238 #define UART_UTS_LOOPIR(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK)
93239 
93240 #define UART_UTS_DBGEN_MASK                      (0x800U)
93241 #define UART_UTS_DBGEN_SHIFT                     (11U)
93242 /*! DBGEN
93243  *  0b0..UART will go into debug mode when debug_req is HIGH
93244  *  0b1..UART will not go into debug mode even if debug_req is HIGH
93245  */
93246 #define UART_UTS_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK)
93247 
93248 #define UART_UTS_LOOP_MASK                       (0x1000U)
93249 #define UART_UTS_LOOP_SHIFT                      (12U)
93250 /*! LOOP
93251  *  0b0..Normal receiver operation
93252  *  0b1..Internally connect the transmitter output to the receiver input
93253  */
93254 #define UART_UTS_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK)
93255 
93256 #define UART_UTS_FRCPERR_MASK                    (0x2000U)
93257 #define UART_UTS_FRCPERR_SHIFT                   (13U)
93258 /*! FRCPERR
93259  *  0b0..Generate normal parity
93260  *  0b1..Generate inverted parity (error)
93261  */
93262 #define UART_UTS_FRCPERR(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK)
93263 /*! @} */
93264 
93265 /*! @name UMCR - UART RS-485 Mode Control Register */
93266 /*! @{ */
93267 
93268 #define UART_UMCR_MDEN_MASK                      (0x1U)
93269 #define UART_UMCR_MDEN_SHIFT                     (0U)
93270 /*! MDEN
93271  *  0b0..Normal RS-232 or IrDA mode, see for detail.
93272  *  0b1..Enable RS-485 mode, see for detail
93273  */
93274 #define UART_UMCR_MDEN(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK)
93275 
93276 #define UART_UMCR_SLAM_MASK                      (0x2U)
93277 #define UART_UMCR_SLAM_SHIFT                     (1U)
93278 /*! SLAM
93279  *  0b0..Select Normal Address Detect mode
93280  *  0b1..Select Automatic Address Detect mode
93281  */
93282 #define UART_UMCR_SLAM(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK)
93283 
93284 #define UART_UMCR_TXB8_MASK                      (0x4U)
93285 #define UART_UMCR_TXB8_SHIFT                     (2U)
93286 /*! TXB8
93287  *  0b0..0 will be transmitted as the RS485 9th data bit
93288  *  0b1..1 will be transmitted as the RS485 9th data bit
93289  */
93290 #define UART_UMCR_TXB8(x)                        (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK)
93291 
93292 #define UART_UMCR_SADEN_MASK                     (0x8U)
93293 #define UART_UMCR_SADEN_SHIFT                    (3U)
93294 /*! SADEN
93295  *  0b0..Disable RS-485 Slave Address Detected Interrupt
93296  *  0b1..Enable RS-485 Slave Address Detected Interrupt
93297  */
93298 #define UART_UMCR_SADEN(x)                       (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK)
93299 
93300 #define UART_UMCR_SLADDR_MASK                    (0xFF00U)
93301 #define UART_UMCR_SLADDR_SHIFT                   (8U)
93302 #define UART_UMCR_SLADDR(x)                      (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK)
93303 /*! @} */
93304 
93305 
93306 /*!
93307  * @}
93308  */ /* end of group UART_Register_Masks */
93309 
93310 
93311 /* UART - Peripheral instance base addresses */
93312 /** Peripheral UART1 base address */
93313 #define UART1_BASE                               (0x30860000u)
93314 /** Peripheral UART1 base pointer */
93315 #define UART1                                    ((UART_Type *)UART1_BASE)
93316 /** Peripheral UART2 base address */
93317 #define UART2_BASE                               (0x30890000u)
93318 /** Peripheral UART2 base pointer */
93319 #define UART2                                    ((UART_Type *)UART2_BASE)
93320 /** Peripheral UART3 base address */
93321 #define UART3_BASE                               (0x30880000u)
93322 /** Peripheral UART3 base pointer */
93323 #define UART3                                    ((UART_Type *)UART3_BASE)
93324 /** Peripheral UART4 base address */
93325 #define UART4_BASE                               (0x30A60000u)
93326 /** Peripheral UART4 base pointer */
93327 #define UART4                                    ((UART_Type *)UART4_BASE)
93328 /** Array initializer of UART peripheral base addresses */
93329 #define UART_BASE_ADDRS                          { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
93330 /** Array initializer of UART peripheral base pointers */
93331 #define UART_BASE_PTRS                           { (UART_Type *)0u, UART1, UART2, UART3, UART4 }
93332 /** Interrupt vectors for the UART peripheral type */
93333 #define UART_IRQS                                { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn }
93334 
93335 /*!
93336  * @}
93337  */ /* end of group UART_Peripheral_Access_Layer */
93338 
93339 
93340 /* ----------------------------------------------------------------------------
93341    -- USB Peripheral Access Layer
93342    ---------------------------------------------------------------------------- */
93343 
93344 /*!
93345  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
93346  * @{
93347  */
93348 
93349 /** USB - Register Layout Typedef */
93350 typedef struct {
93351   __I  uint32_t CAPLENGTH;                         /**< Capability registers length and Host Controller Operational Registers, offset: 0x0 */
93352   __I  uint32_t HCSPARAMS1;                        /**< Structural Parameters 1 Register, offset: 0x4 */
93353   __I  uint32_t HCSPARAMS2;                        /**< Structural Parameters 2 Register, offset: 0x8 */
93354   __I  uint32_t HCSPARAMS3;                        /**< Structural Parameters 3 Register, offset: 0xC */
93355   __I  uint32_t HCCPARAMS1;                        /**< Capability Parameters 1 Register, offset: 0x10 */
93356   __I  uint32_t DBOFF;                             /**< Doorbell Offset Register, offset: 0x14 */
93357   __I  uint32_t RTSOFF;                            /**< Runtime Register Space Offset Register, offset: 0x18 */
93358   __I  uint32_t HCCPARAMS2;                        /**< Host Controller Capability Parameters 2, offset: 0x1C */
93359   __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x20 */
93360   __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x24 */
93361   __I  uint32_t PAGESIZE;                          /**< Page Size Register, offset: 0x28 */
93362        uint8_t RESERVED_0[8];
93363   __IO uint32_t DNCTRL;                            /**< Device Notification Register, offset: 0x34 */
93364   __IO uint32_t CRCR_LO;                           /**< CRCR_LO, offset: 0x38 */
93365   __IO uint32_t CRCR_HI;                           /**< offset: 0x3C */
93366        uint8_t RESERVED_1[16];
93367   __IO uint32_t DCBAAP_LO;                         /**< DCBAAP_LO, offset: 0x50 */
93368   __IO uint32_t DCBAAP_HI;                         /**< DCBAAP_HI, offset: 0x54 */
93369   __IO uint32_t CONFIG;                            /**< Configuration Register, offset: 0x58 */
93370        uint8_t RESERVED_2[964];
93371   __IO uint32_t PORTSC_20;                         /**< Port Status and Control Register, offset: 0x420 */
93372   __IO uint32_t PORTPMSC_20;                       /**< USB3 Port Power Management Status and Control Register, offset: 0x424 */
93373        uint32_t PORTLI_20;                         /**< offset: 0x428 */
93374   __IO uint32_t PORTHLPMC_20;                      /**< offset: 0x42C */
93375   __IO uint32_t PORTSC_30;                         /**< offset: 0x430 */
93376   __IO uint32_t PORTPMSC_30;                       /**< USB3 Port Power Management Status and Control Register, offset: 0x434 */
93377   __I  uint32_t PORTLI_30;                         /**< Port Link Info Register, offset: 0x438 */
93378        uint32_t PORTHLPMC_30;                      /**< USB2 Port Hardware LPM Control Register, offset: 0x43C */
93379   __I  uint32_t MFINDEX;                           /**< Microframe Index Register, offset: 0x440 */
93380        uint8_t RESERVED_3[28];
93381   __IO uint32_t IMAN;                              /**< Interrupter Management Register, offset: 0x460 */
93382   __IO uint32_t IMOD;                              /**< Interrupter Moderation Register, offset: 0x464 */
93383   __IO uint32_t ERSTSZ;                            /**< ERSTSZ, offset: 0x468 */
93384        uint8_t RESERVED_4[4];
93385   __IO uint32_t ERSTBA_LO;                         /**< ERSTBA_LO, offset: 0x470 */
93386   __IO uint32_t ERSTBA_HI;                         /**< ERSTBA_HI, offset: 0x474 */
93387   __IO uint32_t ERDP_LO;                           /**< ERDP_LO, offset: 0x478 */
93388   __IO uint32_t ERDP_HI;                           /**< ERDP_HI, offset: 0x47C */
93389   __IO uint32_t DB;                                /**< Doorbell Register, offset: 0x480 */
93390        uint8_t RESERVED_5[1020];
93391   __IO uint32_t USBLEGSUP;                         /**< USBLEGSUP, offset: 0x880 */
93392   __IO uint32_t USBLEGCTLSTS;                      /**< USBLEGCTLSTS, offset: 0x884 */
93393        uint8_t RESERVED_6[8];
93394   __I  uint32_t SUPTPRT2_DW0;                      /**< SUPTPRT2_DW0, offset: 0x890 */
93395   __I  uint32_t SUPTPRT2_DW1;                      /**< SUPTPRT2_DW1 Register, offset: 0x894 */
93396   __I  uint32_t SUPTPRT2_DW2;                      /**< xHCI Supported Protocol Capability_ Data Word 2, offset: 0x898 */
93397   __I  uint32_t SUPTPRT2_DW3;                      /**< SUPTPRT2_DW3 Register, offset: 0x89C */
93398   __I  uint32_t SUPTPRT3_DW0;                      /**< offset: 0x8A0 */
93399   __I  uint32_t SUPTPRT3_DW1;                      /**< SUPTPRT3_DW1 Register, offset: 0x8A4 */
93400   __I  uint32_t SUPTPRT3_DW2;                      /**< SUPTPRT3_DW2, offset: 0x8A8 */
93401   __I  uint32_t SUPTPRT3_DW3;                      /**< SUPTPRT3_DW3, offset: 0x8AC */
93402        uint8_t RESERVED_7[47184];
93403   __IO uint32_t GSBUSCFG0;                         /**< Global SoC Bus Configuration Register 0, offset: 0xC100 */
93404   __IO uint32_t GSBUSCFG1;                         /**< Global SoC Bus Configuration Register 1, offset: 0xC104 */
93405   __IO uint32_t GTXTHRCFG;                         /**< Global Tx Threshold Control Register, offset: 0xC108 */
93406   __IO uint32_t GRXTHRCFG;                         /**< Global Rx Threshold Control Register, offset: 0xC10C */
93407   __IO uint32_t GCTL;                              /**< Global Core Control Register, offset: 0xC110 */
93408        uint8_t RESERVED_8[4];
93409   __IO uint32_t GSTS;                              /**< Global Status Register, offset: 0xC118 */
93410   __IO uint32_t GUCTL1;                            /**< offset: 0xC11C */
93411        uint8_t RESERVED_9[8];
93412   __IO uint32_t GUID;                              /**< Global User ID Register, offset: 0xC128 */
93413   __IO uint32_t GUCTL;                             /**< Global User Control Register, offset: 0xC12C */
93414   __I  uint32_t GBUSERRADDRLO;                     /**< Gobal SoC Bus Error Address Register - Low, offset: 0xC130 */
93415   __I  uint32_t GBUSERRADDRHI;                     /**< Gobal SoC Bus Error Address Register - High, offset: 0xC134 */
93416   __IO uint32_t GPRTBIMAPLO;                       /**< Global SS Port to Bus Instance Mapping Register - Low, offset: 0xC138 */
93417   __IO uint32_t GPRTBIMAPHI;                       /**< Global SS Port to Bus Instance Mapping Register - High, offset: 0xC13C */
93418   __I  uint32_t GHWPARAMS0;                        /**< Global Hardware Parameters Register 0, offset: 0xC140 */
93419   __I  uint32_t GHWPARAMS1;                        /**< Global Hardware Parameters Register 1, offset: 0xC144 */
93420   __I  uint32_t GHWPARAMS2;                        /**< Global Hardware Parameters Register 2, offset: 0xC148 */
93421   __I  uint32_t GHWPARAMS3;                        /**< Global Hardware Parameters Register 3, offset: 0xC14C */
93422   __I  uint32_t GHWPARAMS4;                        /**< Global Hardware Parameters Register 4, offset: 0xC150 */
93423   __I  uint32_t GHWPARAMS5;                        /**< Global Hardware Parameters Register 5, offset: 0xC154 */
93424   __I  uint32_t GHWPARAMS6;                        /**< Global Hardware Parameters Register 6, offset: 0xC158 */
93425   __I  uint32_t GHWPARAMS7;                        /**< Global Hardware Parameters Register 7, offset: 0xC15C */
93426        uint8_t RESERVED_10[32];
93427   __IO uint32_t GPRTBIMAP_HSLO;                    /**< Global High-Speed Port to Bus Instance Mapping Register - Low, offset: 0xC180 */
93428   __IO uint32_t GPRTBIMAP_HSHI;                    /**< Global High-Speed Port to Bus Instance Mapping Register - High, offset: 0xC184 */
93429   __IO uint32_t GPRTBIMAP_FSLO;                    /**< Global Full-Speed Port to Bus Instance Mapping Register - Low, offset: 0xC188 */
93430   __IO uint32_t GPRTBIMAP_FSHI;                    /**< Global Full-Speed Port to Bus Instance Mapping Register - High, offset: 0xC18C */
93431        uint8_t RESERVED_11[12];
93432   __IO uint32_t GUCTL2;                            /**< Global User Control Register 2, offset: 0xC19C */
93433        uint8_t RESERVED_12[96];
93434   __IO uint32_t GUSB2PHYCFG;                       /**< Global USB2 PHY Configuration Register, offset: 0xC200 */
93435        uint8_t RESERVED_13[124];
93436   __I  uint32_t GUSB2PHYACC_ULPI;                  /**< Global USB 2.0 UTMI PHY vendor control register, offset: 0xC280 */
93437        uint8_t RESERVED_14[60];
93438   __IO uint32_t GUSB3PIPECTL;                      /**< Global USB 3.0 PIPE control register, offset: 0xC2C0 */
93439        uint8_t RESERVED_15[60];
93440   __IO uint32_t GTXFIFOSIZ[8];                     /**< Global transmit FIFO size register, array offset: 0xC300, array step: 0x4 */
93441        uint8_t RESERVED_16[96];
93442   __IO uint32_t GRXFIFOSIZ[3];                     /**< Global receive FIFO size register, array offset: 0xC380, array step: 0x4 */
93443        uint8_t RESERVED_17[116];
93444   __IO uint32_t GEVNTADRLO;                        /**< Global Event Buffer Address (Low) Register, offset: 0xC400 */
93445   __IO uint32_t GEVNTADRHI;                        /**< Global Event Buffer Address (High) Register, offset: 0xC404 */
93446   __IO uint32_t GEVNTSIZ;                          /**< Global event buffer size register, offset: 0xC408 */
93447   __IO uint32_t GEVNTCOUNT;                        /**< Global event buffer count register, offset: 0xC40C */
93448        uint8_t RESERVED_18[496];
93449   __I  uint32_t GHWPARAMS8;                        /**< Global Hardware Parameters Register 8, offset: 0xC600 */
93450        uint8_t RESERVED_19[12];
93451   __IO uint32_t GTXFIFOPRIDEV;                     /**< Global Device TX FIFO DMA Priority Register, offset: 0xC610 */
93452        uint8_t RESERVED_20[4];
93453   __IO uint32_t GTXFIFOPRIHST;                     /**< Global Host TX FIFO DMA Priority Register, offset: 0xC618 */
93454   __IO uint32_t GRXFIFOPRIHST;                     /**< Global Host RX FIFO DMA Priority Register, offset: 0xC61C */
93455   __IO uint32_t GFIFOPRIDBC;                       /**< Global Host Debug Capability DMA Priority Register, offset: 0xC620 */
93456   __IO uint32_t GDMAHLRATIO;                       /**< offset: 0xC624 */
93457        uint8_t RESERVED_21[8];
93458   __IO uint32_t GFLADJ;                            /**< Global Frame Length Adjustment Register, offset: 0xC630 */
93459        uint8_t RESERVED_22[204];
93460   __IO uint32_t DCFG;                              /**< Device Configuration Register, offset: 0xC700 */
93461   __IO uint32_t DCTL;                              /**< Device control register, offset: 0xC704 */
93462   __IO uint32_t DEVTEN;                            /**< Device Event Enable Register, offset: 0xC708 */
93463   __IO uint32_t DSTS;                              /**< Device Status Register, offset: 0xC70C */
93464   __IO uint32_t DGCMDPAR;                          /**< Device Generic Command Parameter Register, offset: 0xC710 */
93465   __IO uint32_t DGCMD;                             /**< offset: 0xC714 */
93466        uint8_t RESERVED_23[8];
93467   __IO uint32_t DALEPENA;                          /**< Device Active USB Endpoint Enable Register, offset: 0xC720 */
93468        uint8_t RESERVED_24[220];
93469   __IO uint32_t DEPCMDPAR2;                        /**< Device physical endpoint-n command parameter 2 register, offset: 0xC800 */
93470   __IO uint32_t DEPCMDPAR1;                        /**< Device Physical Endpoint-n Command Parameter 1 Register, offset: 0xC804 */
93471   __IO uint32_t DEPCMDPAR0;                        /**< Device Physical Endpoint-n Command Parameter 0 Register, offset: 0xC808 */
93472   __IO uint32_t DEPCMD;                            /**< Device Physical Endpoint-n Command Register, offset: 0xC80C */
93473        uint8_t RESERVED_25[496];
93474   __IO uint32_t DEV_IMOD;                          /**< Device Interrupt Moderation Register, offset: 0xCA00 */
93475        uint8_t RESERVED_26[556];
93476   __IO uint32_t BCFG;                              /**< BCFG, offset: 0xCC30 */
93477        uint8_t RESERVED_27[4];
93478   __IO uint32_t BCEVT;                             /**< BCEVT, offset: 0xCC38 */
93479   __IO uint32_t BCEVTEN;                           /**< BCEVTEN, offset: 0xCC3C */
93480 } USB_Type;
93481 
93482 /* ----------------------------------------------------------------------------
93483    -- USB Register Masks
93484    ---------------------------------------------------------------------------- */
93485 
93486 /*!
93487  * @addtogroup USB_Register_Masks USB Register Masks
93488  * @{
93489  */
93490 
93491 /*! @name CAPLENGTH - Capability registers length and Host Controller Operational Registers */
93492 /*! @{ */
93493 
93494 #define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
93495 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
93496 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint32_t)(((uint32_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
93497 
93498 #define USB_CAPLENGTH_HCIVERSION_MASK            (0xFFFF0000U)
93499 #define USB_CAPLENGTH_HCIVERSION_SHIFT           (16U)
93500 #define USB_CAPLENGTH_HCIVERSION(x)              (((uint32_t)(((uint32_t)(x)) << USB_CAPLENGTH_HCIVERSION_SHIFT)) & USB_CAPLENGTH_HCIVERSION_MASK)
93501 /*! @} */
93502 
93503 /*! @name HCSPARAMS1 - Structural Parameters 1 Register */
93504 /*! @{ */
93505 
93506 #define USB_HCSPARAMS1_MAXSLOTS_MASK             (0xFFU)
93507 #define USB_HCSPARAMS1_MAXSLOTS_SHIFT            (0U)
93508 #define USB_HCSPARAMS1_MAXSLOTS(x)               (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS1_MAXSLOTS_SHIFT)) & USB_HCSPARAMS1_MAXSLOTS_MASK)
93509 
93510 #define USB_HCSPARAMS1_MAXINTRS_MASK             (0x7FF00U)
93511 #define USB_HCSPARAMS1_MAXINTRS_SHIFT            (8U)
93512 #define USB_HCSPARAMS1_MAXINTRS(x)               (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS1_MAXINTRS_SHIFT)) & USB_HCSPARAMS1_MAXINTRS_MASK)
93513 
93514 #define USB_HCSPARAMS1_MAXPORTS_MASK             (0xFF000000U)
93515 #define USB_HCSPARAMS1_MAXPORTS_SHIFT            (24U)
93516 #define USB_HCSPARAMS1_MAXPORTS(x)               (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS1_MAXPORTS_SHIFT)) & USB_HCSPARAMS1_MAXPORTS_MASK)
93517 /*! @} */
93518 
93519 /*! @name HCSPARAMS2 - Structural Parameters 2 Register */
93520 /*! @{ */
93521 
93522 #define USB_HCSPARAMS2_IST_MASK                  (0xFU)
93523 #define USB_HCSPARAMS2_IST_SHIFT                 (0U)
93524 #define USB_HCSPARAMS2_IST(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_IST_SHIFT)) & USB_HCSPARAMS2_IST_MASK)
93525 
93526 #define USB_HCSPARAMS2_ERSTMAX_MASK              (0xF0U)
93527 #define USB_HCSPARAMS2_ERSTMAX_SHIFT             (4U)
93528 #define USB_HCSPARAMS2_ERSTMAX(x)                (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_ERSTMAX_SHIFT)) & USB_HCSPARAMS2_ERSTMAX_MASK)
93529 
93530 #define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK (0x3E00000U)
93531 #define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_SHIFT (21U)
93532 #define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI(x)   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_SHIFT)) & USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK)
93533 
93534 #define USB_HCSPARAMS2_SPR_MASK                  (0x4000000U)
93535 #define USB_HCSPARAMS2_SPR_SHIFT                 (26U)
93536 #define USB_HCSPARAMS2_SPR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_SPR_SHIFT)) & USB_HCSPARAMS2_SPR_MASK)
93537 
93538 #define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK    (0xF8000000U)
93539 #define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_SHIFT   (27U)
93540 #define USB_HCSPARAMS2_MAXSCRATCHPADBUFS(x)      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_MAXSCRATCHPADBUFS_SHIFT)) & USB_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK)
93541 /*! @} */
93542 
93543 /*! @name HCSPARAMS3 - Structural Parameters 3 Register */
93544 /*! @{ */
93545 
93546 #define USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK   (0xFFU)
93547 #define USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_SHIFT  (0U)
93548 #define USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_SHIFT)) & USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK)
93549 
93550 #define USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK   (0xFFFF0000U)
93551 #define USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_SHIFT  (16U)
93552 #define USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_SHIFT)) & USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK)
93553 /*! @} */
93554 
93555 /*! @name HCCPARAMS1 - Capability Parameters 1 Register */
93556 /*! @{ */
93557 
93558 #define USB_HCCPARAMS1_AC64_MASK                 (0x1U)
93559 #define USB_HCCPARAMS1_AC64_SHIFT                (0U)
93560 #define USB_HCCPARAMS1_AC64(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_AC64_SHIFT)) & USB_HCCPARAMS1_AC64_MASK)
93561 
93562 #define USB_HCCPARAMS1_BNC_MASK                  (0x2U)
93563 #define USB_HCCPARAMS1_BNC_SHIFT                 (1U)
93564 #define USB_HCCPARAMS1_BNC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_BNC_SHIFT)) & USB_HCCPARAMS1_BNC_MASK)
93565 
93566 #define USB_HCCPARAMS1_CSZ_MASK                  (0x4U)
93567 #define USB_HCCPARAMS1_CSZ_SHIFT                 (2U)
93568 #define USB_HCCPARAMS1_CSZ(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_CSZ_SHIFT)) & USB_HCCPARAMS1_CSZ_MASK)
93569 
93570 #define USB_HCCPARAMS1_PPC_MASK                  (0x8U)
93571 #define USB_HCCPARAMS1_PPC_SHIFT                 (3U)
93572 #define USB_HCCPARAMS1_PPC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_PPC_SHIFT)) & USB_HCCPARAMS1_PPC_MASK)
93573 
93574 #define USB_HCCPARAMS1_PIND_MASK                 (0x10U)
93575 #define USB_HCCPARAMS1_PIND_SHIFT                (4U)
93576 #define USB_HCCPARAMS1_PIND(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_PIND_SHIFT)) & USB_HCCPARAMS1_PIND_MASK)
93577 
93578 #define USB_HCCPARAMS1_LHRC_MASK                 (0x20U)
93579 #define USB_HCCPARAMS1_LHRC_SHIFT                (5U)
93580 #define USB_HCCPARAMS1_LHRC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_LHRC_SHIFT)) & USB_HCCPARAMS1_LHRC_MASK)
93581 
93582 #define USB_HCCPARAMS1_LTC_MASK                  (0x40U)
93583 #define USB_HCCPARAMS1_LTC_SHIFT                 (6U)
93584 #define USB_HCCPARAMS1_LTC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_LTC_SHIFT)) & USB_HCCPARAMS1_LTC_MASK)
93585 
93586 #define USB_HCCPARAMS1_NSS_MASK                  (0x80U)
93587 #define USB_HCCPARAMS1_NSS_SHIFT                 (7U)
93588 #define USB_HCCPARAMS1_NSS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_NSS_SHIFT)) & USB_HCCPARAMS1_NSS_MASK)
93589 
93590 #define USB_HCCPARAMS1_PAE_MASK                  (0x100U)
93591 #define USB_HCCPARAMS1_PAE_SHIFT                 (8U)
93592 #define USB_HCCPARAMS1_PAE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_PAE_SHIFT)) & USB_HCCPARAMS1_PAE_MASK)
93593 
93594 #define USB_HCCPARAMS1_SPC_MASK                  (0x200U)
93595 #define USB_HCCPARAMS1_SPC_SHIFT                 (9U)
93596 #define USB_HCCPARAMS1_SPC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_SPC_SHIFT)) & USB_HCCPARAMS1_SPC_MASK)
93597 
93598 #define USB_HCCPARAMS1_SEC_MASK                  (0x400U)
93599 #define USB_HCCPARAMS1_SEC_SHIFT                 (10U)
93600 #define USB_HCCPARAMS1_SEC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_SEC_SHIFT)) & USB_HCCPARAMS1_SEC_MASK)
93601 
93602 #define USB_HCCPARAMS1_CFC_MASK                  (0x800U)
93603 #define USB_HCCPARAMS1_CFC_SHIFT                 (11U)
93604 #define USB_HCCPARAMS1_CFC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_CFC_SHIFT)) & USB_HCCPARAMS1_CFC_MASK)
93605 
93606 #define USB_HCCPARAMS1_MAXPSASIZE_MASK           (0xF000U)
93607 #define USB_HCCPARAMS1_MAXPSASIZE_SHIFT          (12U)
93608 #define USB_HCCPARAMS1_MAXPSASIZE(x)             (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_MAXPSASIZE_SHIFT)) & USB_HCCPARAMS1_MAXPSASIZE_MASK)
93609 
93610 #define USB_HCCPARAMS1_XECP_MASK                 (0xFFFF0000U)
93611 #define USB_HCCPARAMS1_XECP_SHIFT                (16U)
93612 #define USB_HCCPARAMS1_XECP(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_XECP_SHIFT)) & USB_HCCPARAMS1_XECP_MASK)
93613 /*! @} */
93614 
93615 /*! @name DBOFF - Doorbell Offset Register */
93616 /*! @{ */
93617 
93618 #define USB_DBOFF_DOORBELL_ARRAY_OFFSET_MASK     (0xFFFFFFFCU)
93619 #define USB_DBOFF_DOORBELL_ARRAY_OFFSET_SHIFT    (2U)
93620 #define USB_DBOFF_DOORBELL_ARRAY_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << USB_DBOFF_DOORBELL_ARRAY_OFFSET_SHIFT)) & USB_DBOFF_DOORBELL_ARRAY_OFFSET_MASK)
93621 /*! @} */
93622 
93623 /*! @name RTSOFF - Runtime Register Space Offset Register */
93624 /*! @{ */
93625 
93626 #define USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK (0xFFFFFFE0U)
93627 #define USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_SHIFT (5U)
93628 #define USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_SHIFT)) & USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK)
93629 /*! @} */
93630 
93631 /*! @name HCCPARAMS2 - Host Controller Capability Parameters 2 */
93632 /*! @{ */
93633 
93634 #define USB_HCCPARAMS2_U3C_MASK                  (0x1U)
93635 #define USB_HCCPARAMS2_U3C_SHIFT                 (0U)
93636 #define USB_HCCPARAMS2_U3C(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_U3C_SHIFT)) & USB_HCCPARAMS2_U3C_MASK)
93637 
93638 #define USB_HCCPARAMS2_CMC_MASK                  (0x2U)
93639 #define USB_HCCPARAMS2_CMC_SHIFT                 (1U)
93640 #define USB_HCCPARAMS2_CMC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_CMC_SHIFT)) & USB_HCCPARAMS2_CMC_MASK)
93641 
93642 #define USB_HCCPARAMS2_FSC_MASK                  (0x4U)
93643 #define USB_HCCPARAMS2_FSC_SHIFT                 (2U)
93644 #define USB_HCCPARAMS2_FSC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_FSC_SHIFT)) & USB_HCCPARAMS2_FSC_MASK)
93645 
93646 #define USB_HCCPARAMS2_CTC_MASK                  (0x8U)
93647 #define USB_HCCPARAMS2_CTC_SHIFT                 (3U)
93648 #define USB_HCCPARAMS2_CTC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_CTC_SHIFT)) & USB_HCCPARAMS2_CTC_MASK)
93649 
93650 #define USB_HCCPARAMS2_LEC_MASK                  (0x10U)
93651 #define USB_HCCPARAMS2_LEC_SHIFT                 (4U)
93652 #define USB_HCCPARAMS2_LEC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_LEC_SHIFT)) & USB_HCCPARAMS2_LEC_MASK)
93653 
93654 #define USB_HCCPARAMS2_CIC_MASK                  (0x20U)
93655 #define USB_HCCPARAMS2_CIC_SHIFT                 (5U)
93656 #define USB_HCCPARAMS2_CIC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_CIC_SHIFT)) & USB_HCCPARAMS2_CIC_MASK)
93657 /*! @} */
93658 
93659 /*! @name USBCMD - USB Command Register */
93660 /*! @{ */
93661 
93662 #define USB_USBCMD_R_S_MASK                      (0x1U)
93663 #define USB_USBCMD_R_S_SHIFT                     (0U)
93664 #define USB_USBCMD_R_S(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_R_S_SHIFT)) & USB_USBCMD_R_S_MASK)
93665 
93666 #define USB_USBCMD_HCRST_MASK                    (0x2U)
93667 #define USB_USBCMD_HCRST_SHIFT                   (1U)
93668 #define USB_USBCMD_HCRST(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_HCRST_SHIFT)) & USB_USBCMD_HCRST_MASK)
93669 
93670 #define USB_USBCMD_INTE_MASK                     (0x4U)
93671 #define USB_USBCMD_INTE_SHIFT                    (2U)
93672 #define USB_USBCMD_INTE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_INTE_SHIFT)) & USB_USBCMD_INTE_MASK)
93673 
93674 #define USB_USBCMD_HSEE_MASK                     (0x8U)
93675 #define USB_USBCMD_HSEE_SHIFT                    (3U)
93676 #define USB_USBCMD_HSEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_HSEE_SHIFT)) & USB_USBCMD_HSEE_MASK)
93677 
93678 #define USB_USBCMD_LHCRST_MASK                   (0x80U)
93679 #define USB_USBCMD_LHCRST_SHIFT                  (7U)
93680 #define USB_USBCMD_LHCRST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_LHCRST_SHIFT)) & USB_USBCMD_LHCRST_MASK)
93681 
93682 #define USB_USBCMD_CSS_MASK                      (0x100U)
93683 #define USB_USBCMD_CSS_SHIFT                     (8U)
93684 #define USB_USBCMD_CSS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_CSS_SHIFT)) & USB_USBCMD_CSS_MASK)
93685 
93686 #define USB_USBCMD_CRS_MASK                      (0x200U)
93687 #define USB_USBCMD_CRS_SHIFT                     (9U)
93688 #define USB_USBCMD_CRS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_CRS_SHIFT)) & USB_USBCMD_CRS_MASK)
93689 
93690 #define USB_USBCMD_EWE_MASK                      (0x400U)
93691 #define USB_USBCMD_EWE_SHIFT                     (10U)
93692 #define USB_USBCMD_EWE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_EWE_SHIFT)) & USB_USBCMD_EWE_MASK)
93693 
93694 #define USB_USBCMD_EU3S_MASK                     (0x800U)
93695 #define USB_USBCMD_EU3S_SHIFT                    (11U)
93696 #define USB_USBCMD_EU3S(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_EU3S_SHIFT)) & USB_USBCMD_EU3S_MASK)
93697 
93698 #define USB_USBCMD_CME_MASK                      (0x2000U)
93699 #define USB_USBCMD_CME_SHIFT                     (13U)
93700 #define USB_USBCMD_CME(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_CME_SHIFT)) & USB_USBCMD_CME_MASK)
93701 /*! @} */
93702 
93703 /*! @name USBSTS - USB Status Register */
93704 /*! @{ */
93705 
93706 #define USB_USBSTS_HCH_MASK                      (0x1U)
93707 #define USB_USBSTS_HCH_SHIFT                     (0U)
93708 #define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
93709 
93710 #define USB_USBSTS_HSE_MASK                      (0x4U)
93711 #define USB_USBSTS_HSE_SHIFT                     (2U)
93712 #define USB_USBSTS_HSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HSE_SHIFT)) & USB_USBSTS_HSE_MASK)
93713 
93714 #define USB_USBSTS_EINT_MASK                     (0x8U)
93715 #define USB_USBSTS_EINT_SHIFT                    (3U)
93716 #define USB_USBSTS_EINT(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_EINT_SHIFT)) & USB_USBSTS_EINT_MASK)
93717 
93718 #define USB_USBSTS_PCD_MASK                      (0x10U)
93719 #define USB_USBSTS_PCD_SHIFT                     (4U)
93720 #define USB_USBSTS_PCD(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCD_SHIFT)) & USB_USBSTS_PCD_MASK)
93721 
93722 #define USB_USBSTS_SSS_MASK                      (0x100U)
93723 #define USB_USBSTS_SSS_SHIFT                     (8U)
93724 #define USB_USBSTS_SSS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SSS_SHIFT)) & USB_USBSTS_SSS_MASK)
93725 
93726 #define USB_USBSTS_RSS_MASK                      (0x200U)
93727 #define USB_USBSTS_RSS_SHIFT                     (9U)
93728 #define USB_USBSTS_RSS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RSS_SHIFT)) & USB_USBSTS_RSS_MASK)
93729 
93730 #define USB_USBSTS_SRE_MASK                      (0x400U)
93731 #define USB_USBSTS_SRE_SHIFT                     (10U)
93732 #define USB_USBSTS_SRE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRE_SHIFT)) & USB_USBSTS_SRE_MASK)
93733 
93734 #define USB_USBSTS_CNR_MASK                      (0x800U)
93735 #define USB_USBSTS_CNR_SHIFT                     (11U)
93736 #define USB_USBSTS_CNR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_CNR_SHIFT)) & USB_USBSTS_CNR_MASK)
93737 
93738 #define USB_USBSTS_HCE_MASK                      (0x1000U)
93739 #define USB_USBSTS_HCE_SHIFT                     (12U)
93740 #define USB_USBSTS_HCE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCE_SHIFT)) & USB_USBSTS_HCE_MASK)
93741 /*! @} */
93742 
93743 /*! @name PAGESIZE - Page Size Register */
93744 /*! @{ */
93745 
93746 #define USB_PAGESIZE_PAGE_SIZE_MASK              (0xFFFFU)
93747 #define USB_PAGESIZE_PAGE_SIZE_SHIFT             (0U)
93748 #define USB_PAGESIZE_PAGE_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << USB_PAGESIZE_PAGE_SIZE_SHIFT)) & USB_PAGESIZE_PAGE_SIZE_MASK)
93749 /*! @} */
93750 
93751 /*! @name DNCTRL - Device Notification Register */
93752 /*! @{ */
93753 
93754 #define USB_DNCTRL_N0_N15_MASK                   (0xFFFFU)
93755 #define USB_DNCTRL_N0_N15_SHIFT                  (0U)
93756 #define USB_DNCTRL_N0_N15(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DNCTRL_N0_N15_SHIFT)) & USB_DNCTRL_N0_N15_MASK)
93757 /*! @} */
93758 
93759 /*! @name CRCR_LO - CRCR_LO */
93760 /*! @{ */
93761 
93762 #define USB_CRCR_LO_RCS_MASK                     (0x1U)
93763 #define USB_CRCR_LO_RCS_SHIFT                    (0U)
93764 #define USB_CRCR_LO_RCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_RCS_SHIFT)) & USB_CRCR_LO_RCS_MASK)
93765 
93766 #define USB_CRCR_LO_CS_MASK                      (0x2U)
93767 #define USB_CRCR_LO_CS_SHIFT                     (1U)
93768 #define USB_CRCR_LO_CS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CS_SHIFT)) & USB_CRCR_LO_CS_MASK)
93769 
93770 #define USB_CRCR_LO_CA_MASK                      (0x4U)
93771 #define USB_CRCR_LO_CA_SHIFT                     (2U)
93772 #define USB_CRCR_LO_CA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CA_SHIFT)) & USB_CRCR_LO_CA_MASK)
93773 
93774 #define USB_CRCR_LO_CRR_MASK                     (0x8U)
93775 #define USB_CRCR_LO_CRR_SHIFT                    (3U)
93776 #define USB_CRCR_LO_CRR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CRR_SHIFT)) & USB_CRCR_LO_CRR_MASK)
93777 
93778 #define USB_CRCR_LO_CMD_RING_PNTR_MASK           (0xFFFFFFC0U)
93779 #define USB_CRCR_LO_CMD_RING_PNTR_SHIFT          (6U)
93780 #define USB_CRCR_LO_CMD_RING_PNTR(x)             (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CMD_RING_PNTR_SHIFT)) & USB_CRCR_LO_CMD_RING_PNTR_MASK)
93781 /*! @} */
93782 
93783 /*! @name CRCR_HI -  */
93784 /*! @{ */
93785 
93786 #define USB_CRCR_HI_CMD_RING_PNTR_MASK           (0xFFFFFFFFU)
93787 #define USB_CRCR_HI_CMD_RING_PNTR_SHIFT          (0U)
93788 #define USB_CRCR_HI_CMD_RING_PNTR(x)             (((uint32_t)(((uint32_t)(x)) << USB_CRCR_HI_CMD_RING_PNTR_SHIFT)) & USB_CRCR_HI_CMD_RING_PNTR_MASK)
93789 /*! @} */
93790 
93791 /*! @name DCBAAP_LO - DCBAAP_LO */
93792 /*! @{ */
93793 
93794 #define USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK   (0xFFFFFFC0U)
93795 #define USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_SHIFT  (6U)
93796 #define USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP(x)     (((uint32_t)(((uint32_t)(x)) << USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_SHIFT)) & USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK)
93797 /*! @} */
93798 
93799 /*! @name DCBAAP_HI - DCBAAP_HI */
93800 /*! @{ */
93801 
93802 #define USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_MASK   (0xFFFFFFFFU)
93803 #define USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_SHIFT  (0U)
93804 #define USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP(x)     (((uint32_t)(((uint32_t)(x)) << USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_SHIFT)) & USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_MASK)
93805 /*! @} */
93806 
93807 /*! @name CONFIG - Configuration Register */
93808 /*! @{ */
93809 
93810 #define USB_CONFIG_MAXSLOTSEN_MASK               (0xFFU)
93811 #define USB_CONFIG_MAXSLOTSEN_SHIFT              (0U)
93812 #define USB_CONFIG_MAXSLOTSEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_CONFIG_MAXSLOTSEN_SHIFT)) & USB_CONFIG_MAXSLOTSEN_MASK)
93813 
93814 #define USB_CONFIG_U3E_MASK                      (0x100U)
93815 #define USB_CONFIG_U3E_SHIFT                     (8U)
93816 #define USB_CONFIG_U3E(x)                        (((uint32_t)(((uint32_t)(x)) << USB_CONFIG_U3E_SHIFT)) & USB_CONFIG_U3E_MASK)
93817 
93818 #define USB_CONFIG_CIE_MASK                      (0x200U)
93819 #define USB_CONFIG_CIE_SHIFT                     (9U)
93820 #define USB_CONFIG_CIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_CONFIG_CIE_SHIFT)) & USB_CONFIG_CIE_MASK)
93821 /*! @} */
93822 
93823 /*! @name PORTSC_20 - Port Status and Control Register */
93824 /*! @{ */
93825 
93826 #define USB_PORTSC_20_CCS_MASK                   (0x1U)
93827 #define USB_PORTSC_20_CCS_SHIFT                  (0U)
93828 #define USB_PORTSC_20_CCS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_CCS_SHIFT)) & USB_PORTSC_20_CCS_MASK)
93829 
93830 #define USB_PORTSC_20_PED_MASK                   (0x2U)
93831 #define USB_PORTSC_20_PED_SHIFT                  (1U)
93832 /*! PED - PED */
93833 #define USB_PORTSC_20_PED(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PED_SHIFT)) & USB_PORTSC_20_PED_MASK)
93834 
93835 #define USB_PORTSC_20_OCA_MASK                   (0x8U)
93836 #define USB_PORTSC_20_OCA_SHIFT                  (3U)
93837 /*! OCA - OCA */
93838 #define USB_PORTSC_20_OCA(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_OCA_SHIFT)) & USB_PORTSC_20_OCA_MASK)
93839 
93840 #define USB_PORTSC_20_PR_MASK                    (0x10U)
93841 #define USB_PORTSC_20_PR_SHIFT                   (4U)
93842 /*! PR - PR */
93843 #define USB_PORTSC_20_PR(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PR_SHIFT)) & USB_PORTSC_20_PR_MASK)
93844 
93845 #define USB_PORTSC_20_PLS_MASK                   (0x1E0U)
93846 #define USB_PORTSC_20_PLS_SHIFT                  (5U)
93847 /*! PLS - PLS */
93848 #define USB_PORTSC_20_PLS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PLS_SHIFT)) & USB_PORTSC_20_PLS_MASK)
93849 
93850 #define USB_PORTSC_20_PP_MASK                    (0x200U)
93851 #define USB_PORTSC_20_PP_SHIFT                   (9U)
93852 /*! PP - PP */
93853 #define USB_PORTSC_20_PP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PP_SHIFT)) & USB_PORTSC_20_PP_MASK)
93854 
93855 #define USB_PORTSC_20_PORTSPEED_MASK             (0x3C00U)
93856 #define USB_PORTSC_20_PORTSPEED_SHIFT            (10U)
93857 /*! PORTSPEED - PORTSPEED */
93858 #define USB_PORTSC_20_PORTSPEED(x)               (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PORTSPEED_SHIFT)) & USB_PORTSC_20_PORTSPEED_MASK)
93859 
93860 #define USB_PORTSC_20_PIC_MASK                   (0xC000U)
93861 #define USB_PORTSC_20_PIC_SHIFT                  (14U)
93862 /*! PIC - PIC */
93863 #define USB_PORTSC_20_PIC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PIC_SHIFT)) & USB_PORTSC_20_PIC_MASK)
93864 
93865 #define USB_PORTSC_20_LWS_MASK                   (0x10000U)
93866 #define USB_PORTSC_20_LWS_SHIFT                  (16U)
93867 /*! LWS - LWS */
93868 #define USB_PORTSC_20_LWS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_LWS_SHIFT)) & USB_PORTSC_20_LWS_MASK)
93869 
93870 #define USB_PORTSC_20_CSC_MASK                   (0x20000U)
93871 #define USB_PORTSC_20_CSC_SHIFT                  (17U)
93872 /*! CSC - CSC */
93873 #define USB_PORTSC_20_CSC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_CSC_SHIFT)) & USB_PORTSC_20_CSC_MASK)
93874 
93875 #define USB_PORTSC_20_PEC_MASK                   (0x40000U)
93876 #define USB_PORTSC_20_PEC_SHIFT                  (18U)
93877 #define USB_PORTSC_20_PEC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PEC_SHIFT)) & USB_PORTSC_20_PEC_MASK)
93878 
93879 #define USB_PORTSC_20_OCC_MASK                   (0x100000U)
93880 #define USB_PORTSC_20_OCC_SHIFT                  (20U)
93881 /*! OCC - OCC */
93882 #define USB_PORTSC_20_OCC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_OCC_SHIFT)) & USB_PORTSC_20_OCC_MASK)
93883 
93884 #define USB_PORTSC_20_PRC_MASK                   (0x200000U)
93885 #define USB_PORTSC_20_PRC_SHIFT                  (21U)
93886 /*! PRC - PRC */
93887 #define USB_PORTSC_20_PRC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PRC_SHIFT)) & USB_PORTSC_20_PRC_MASK)
93888 
93889 #define USB_PORTSC_20_PLC_MASK                   (0x400000U)
93890 #define USB_PORTSC_20_PLC_SHIFT                  (22U)
93891 /*! PLC - PLC */
93892 #define USB_PORTSC_20_PLC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PLC_SHIFT)) & USB_PORTSC_20_PLC_MASK)
93893 
93894 #define USB_PORTSC_20_CAS_MASK                   (0x1000000U)
93895 #define USB_PORTSC_20_CAS_SHIFT                  (24U)
93896 /*! CAS - CAS */
93897 #define USB_PORTSC_20_CAS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_CAS_SHIFT)) & USB_PORTSC_20_CAS_MASK)
93898 
93899 #define USB_PORTSC_20_WCE_MASK                   (0x2000000U)
93900 #define USB_PORTSC_20_WCE_SHIFT                  (25U)
93901 /*! WCE - WCE */
93902 #define USB_PORTSC_20_WCE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_WCE_SHIFT)) & USB_PORTSC_20_WCE_MASK)
93903 
93904 #define USB_PORTSC_20_WDE_MASK                   (0x4000000U)
93905 #define USB_PORTSC_20_WDE_SHIFT                  (26U)
93906 /*! WDE - WDE */
93907 #define USB_PORTSC_20_WDE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_WDE_SHIFT)) & USB_PORTSC_20_WDE_MASK)
93908 
93909 #define USB_PORTSC_20_WOE_MASK                   (0x8000000U)
93910 #define USB_PORTSC_20_WOE_SHIFT                  (27U)
93911 /*! WOE - WOE */
93912 #define USB_PORTSC_20_WOE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_WOE_SHIFT)) & USB_PORTSC_20_WOE_MASK)
93913 
93914 #define USB_PORTSC_20_DR_MASK                    (0x40000000U)
93915 #define USB_PORTSC_20_DR_SHIFT                   (30U)
93916 /*! DR - Reset value */
93917 #define USB_PORTSC_20_DR(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_DR_SHIFT)) & USB_PORTSC_20_DR_MASK)
93918 /*! @} */
93919 
93920 /*! @name PORTPMSC_20 - USB3 Port Power Management Status and Control Register */
93921 /*! @{ */
93922 
93923 #define USB_PORTPMSC_20_L1S_MASK                 (0x7U)
93924 #define USB_PORTPMSC_20_L1S_SHIFT                (0U)
93925 /*! L1S - L1 Status (L1S) */
93926 #define USB_PORTPMSC_20_L1S(x)                   (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_L1S_SHIFT)) & USB_PORTPMSC_20_L1S_MASK)
93927 
93928 #define USB_PORTPMSC_20_RWE_MASK                 (0x8U)
93929 #define USB_PORTPMSC_20_RWE_SHIFT                (3U)
93930 /*! RWE - RWE Port Test Control */
93931 #define USB_PORTPMSC_20_RWE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_RWE_SHIFT)) & USB_PORTPMSC_20_RWE_MASK)
93932 
93933 #define USB_PORTPMSC_20_HIRD_MASK                (0xF0U)
93934 #define USB_PORTPMSC_20_HIRD_SHIFT               (4U)
93935 #define USB_PORTPMSC_20_HIRD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_HIRD_SHIFT)) & USB_PORTPMSC_20_HIRD_MASK)
93936 
93937 #define USB_PORTPMSC_20_L1DSLOT_MASK             (0xFF00U)
93938 #define USB_PORTPMSC_20_L1DSLOT_SHIFT            (8U)
93939 #define USB_PORTPMSC_20_L1DSLOT(x)               (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_L1DSLOT_SHIFT)) & USB_PORTPMSC_20_L1DSLOT_MASK)
93940 
93941 #define USB_PORTPMSC_20_HLE_MASK                 (0x10000U)
93942 #define USB_PORTPMSC_20_HLE_SHIFT                (16U)
93943 #define USB_PORTPMSC_20_HLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_HLE_SHIFT)) & USB_PORTPMSC_20_HLE_MASK)
93944 
93945 #define USB_PORTPMSC_20_PRTTSTCTRL_MASK          (0xF0000000U)
93946 #define USB_PORTPMSC_20_PRTTSTCTRL_SHIFT         (28U)
93947 #define USB_PORTPMSC_20_PRTTSTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_PRTTSTCTRL_SHIFT)) & USB_PORTPMSC_20_PRTTSTCTRL_MASK)
93948 /*! @} */
93949 
93950 /*! @name PORTHLPMC_20 -  */
93951 /*! @{ */
93952 
93953 #define USB_PORTHLPMC_20_HIRDM_MASK              (0x3U)
93954 #define USB_PORTHLPMC_20_HIRDM_SHIFT             (0U)
93955 #define USB_PORTHLPMC_20_HIRDM(x)                (((uint32_t)(((uint32_t)(x)) << USB_PORTHLPMC_20_HIRDM_SHIFT)) & USB_PORTHLPMC_20_HIRDM_MASK)
93956 
93957 #define USB_PORTHLPMC_20_L1_TIMEOUT_MASK         (0x3FCU)
93958 #define USB_PORTHLPMC_20_L1_TIMEOUT_SHIFT        (2U)
93959 #define USB_PORTHLPMC_20_L1_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << USB_PORTHLPMC_20_L1_TIMEOUT_SHIFT)) & USB_PORTHLPMC_20_L1_TIMEOUT_MASK)
93960 
93961 #define USB_PORTHLPMC_20_HIRDD_MASK              (0x3C00U)
93962 #define USB_PORTHLPMC_20_HIRDD_SHIFT             (10U)
93963 #define USB_PORTHLPMC_20_HIRDD(x)                (((uint32_t)(((uint32_t)(x)) << USB_PORTHLPMC_20_HIRDD_SHIFT)) & USB_PORTHLPMC_20_HIRDD_MASK)
93964 /*! @} */
93965 
93966 /*! @name PORTSC_30 -  */
93967 /*! @{ */
93968 
93969 #define USB_PORTSC_30_CCS_MASK                   (0x1U)
93970 #define USB_PORTSC_30_CCS_SHIFT                  (0U)
93971 #define USB_PORTSC_30_CCS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CCS_SHIFT)) & USB_PORTSC_30_CCS_MASK)
93972 
93973 #define USB_PORTSC_30_PED_MASK                   (0x2U)
93974 #define USB_PORTSC_30_PED_SHIFT                  (1U)
93975 #define USB_PORTSC_30_PED(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PED_SHIFT)) & USB_PORTSC_30_PED_MASK)
93976 
93977 #define USB_PORTSC_30_OCA_MASK                   (0x8U)
93978 #define USB_PORTSC_30_OCA_SHIFT                  (3U)
93979 #define USB_PORTSC_30_OCA(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_OCA_SHIFT)) & USB_PORTSC_30_OCA_MASK)
93980 
93981 #define USB_PORTSC_30_PR_MASK                    (0x10U)
93982 #define USB_PORTSC_30_PR_SHIFT                   (4U)
93983 #define USB_PORTSC_30_PR(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PR_SHIFT)) & USB_PORTSC_30_PR_MASK)
93984 
93985 #define USB_PORTSC_30_PLS_MASK                   (0x1E0U)
93986 #define USB_PORTSC_30_PLS_SHIFT                  (5U)
93987 #define USB_PORTSC_30_PLS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PLS_SHIFT)) & USB_PORTSC_30_PLS_MASK)
93988 
93989 #define USB_PORTSC_30_PP_MASK                    (0x200U)
93990 #define USB_PORTSC_30_PP_SHIFT                   (9U)
93991 #define USB_PORTSC_30_PP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PP_SHIFT)) & USB_PORTSC_30_PP_MASK)
93992 
93993 #define USB_PORTSC_30_PORTSPEED_MASK             (0x3C00U)
93994 #define USB_PORTSC_30_PORTSPEED_SHIFT            (10U)
93995 #define USB_PORTSC_30_PORTSPEED(x)               (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PORTSPEED_SHIFT)) & USB_PORTSC_30_PORTSPEED_MASK)
93996 
93997 #define USB_PORTSC_30_PIC_MASK                   (0xC000U)
93998 #define USB_PORTSC_30_PIC_SHIFT                  (14U)
93999 #define USB_PORTSC_30_PIC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PIC_SHIFT)) & USB_PORTSC_30_PIC_MASK)
94000 
94001 #define USB_PORTSC_30_LWS_MASK                   (0x10000U)
94002 #define USB_PORTSC_30_LWS_SHIFT                  (16U)
94003 #define USB_PORTSC_30_LWS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_LWS_SHIFT)) & USB_PORTSC_30_LWS_MASK)
94004 
94005 #define USB_PORTSC_30_CSC_MASK                   (0x20000U)
94006 #define USB_PORTSC_30_CSC_SHIFT                  (17U)
94007 #define USB_PORTSC_30_CSC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CSC_SHIFT)) & USB_PORTSC_30_CSC_MASK)
94008 
94009 #define USB_PORTSC_30_PEC_MASK                   (0x40000U)
94010 #define USB_PORTSC_30_PEC_SHIFT                  (18U)
94011 #define USB_PORTSC_30_PEC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PEC_SHIFT)) & USB_PORTSC_30_PEC_MASK)
94012 
94013 #define USB_PORTSC_30_WRC_MASK                   (0x80000U)
94014 #define USB_PORTSC_30_WRC_SHIFT                  (19U)
94015 #define USB_PORTSC_30_WRC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WRC_SHIFT)) & USB_PORTSC_30_WRC_MASK)
94016 
94017 #define USB_PORTSC_30_OCC_MASK                   (0x100000U)
94018 #define USB_PORTSC_30_OCC_SHIFT                  (20U)
94019 #define USB_PORTSC_30_OCC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_OCC_SHIFT)) & USB_PORTSC_30_OCC_MASK)
94020 
94021 #define USB_PORTSC_30_PRC_MASK                   (0x200000U)
94022 #define USB_PORTSC_30_PRC_SHIFT                  (21U)
94023 /*! PRC - PRC */
94024 #define USB_PORTSC_30_PRC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PRC_SHIFT)) & USB_PORTSC_30_PRC_MASK)
94025 
94026 #define USB_PORTSC_30_PLC_MASK                   (0x400000U)
94027 #define USB_PORTSC_30_PLC_SHIFT                  (22U)
94028 /*! PLC - PLC */
94029 #define USB_PORTSC_30_PLC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PLC_SHIFT)) & USB_PORTSC_30_PLC_MASK)
94030 
94031 #define USB_PORTSC_30_CEC_MASK                   (0x800000U)
94032 #define USB_PORTSC_30_CEC_SHIFT                  (23U)
94033 /*! CEC - CEC */
94034 #define USB_PORTSC_30_CEC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CEC_SHIFT)) & USB_PORTSC_30_CEC_MASK)
94035 
94036 #define USB_PORTSC_30_CAS_MASK                   (0x1000000U)
94037 #define USB_PORTSC_30_CAS_SHIFT                  (24U)
94038 /*! CAS - Cold Attach Status */
94039 #define USB_PORTSC_30_CAS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CAS_SHIFT)) & USB_PORTSC_30_CAS_MASK)
94040 
94041 #define USB_PORTSC_30_WCE_MASK                   (0x2000000U)
94042 #define USB_PORTSC_30_WCE_SHIFT                  (25U)
94043 /*! WCE - WCE */
94044 #define USB_PORTSC_30_WCE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WCE_SHIFT)) & USB_PORTSC_30_WCE_MASK)
94045 
94046 #define USB_PORTSC_30_WDE_MASK                   (0x4000000U)
94047 #define USB_PORTSC_30_WDE_SHIFT                  (26U)
94048 /*! WDE - WDE */
94049 #define USB_PORTSC_30_WDE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WDE_SHIFT)) & USB_PORTSC_30_WDE_MASK)
94050 
94051 #define USB_PORTSC_30_WOE_MASK                   (0x8000000U)
94052 #define USB_PORTSC_30_WOE_SHIFT                  (27U)
94053 /*! WOE - WOE */
94054 #define USB_PORTSC_30_WOE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WOE_SHIFT)) & USB_PORTSC_30_WOE_MASK)
94055 
94056 #define USB_PORTSC_30_DR_MASK                    (0x40000000U)
94057 #define USB_PORTSC_30_DR_SHIFT                   (30U)
94058 #define USB_PORTSC_30_DR(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_DR_SHIFT)) & USB_PORTSC_30_DR_MASK)
94059 
94060 #define USB_PORTSC_30_WPR_MASK                   (0x80000000U)
94061 #define USB_PORTSC_30_WPR_SHIFT                  (31U)
94062 #define USB_PORTSC_30_WPR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WPR_SHIFT)) & USB_PORTSC_30_WPR_MASK)
94063 /*! @} */
94064 
94065 /*! @name PORTPMSC_30 - USB3 Port Power Management Status and Control Register */
94066 /*! @{ */
94067 
94068 #define USB_PORTPMSC_30_U1_TIMEOUT_MASK          (0xFFU)
94069 #define USB_PORTPMSC_30_U1_TIMEOUT_SHIFT         (0U)
94070 /*! U1_TIMEOUT - U1_TIMEOUT */
94071 #define USB_PORTPMSC_30_U1_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_30_U1_TIMEOUT_SHIFT)) & USB_PORTPMSC_30_U1_TIMEOUT_MASK)
94072 
94073 #define USB_PORTPMSC_30_U2_TIMEOUT_MASK          (0xFF00U)
94074 #define USB_PORTPMSC_30_U2_TIMEOUT_SHIFT         (8U)
94075 /*! U2_TIMEOUT - U2_TIMEOUT */
94076 #define USB_PORTPMSC_30_U2_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_30_U2_TIMEOUT_SHIFT)) & USB_PORTPMSC_30_U2_TIMEOUT_MASK)
94077 
94078 #define USB_PORTPMSC_30_FLA_MASK                 (0x10000U)
94079 #define USB_PORTPMSC_30_FLA_SHIFT                (16U)
94080 #define USB_PORTPMSC_30_FLA(x)                   (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_30_FLA_SHIFT)) & USB_PORTPMSC_30_FLA_MASK)
94081 /*! @} */
94082 
94083 /*! @name PORTLI_30 - Port Link Info Register */
94084 /*! @{ */
94085 
94086 #define USB_PORTLI_30_LINK_ERROR_COUNT_MASK      (0xFFFFU)
94087 #define USB_PORTLI_30_LINK_ERROR_COUNT_SHIFT     (0U)
94088 /*! LINK_ERROR_COUNT - LINK_ERROR_COUNT */
94089 #define USB_PORTLI_30_LINK_ERROR_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << USB_PORTLI_30_LINK_ERROR_COUNT_SHIFT)) & USB_PORTLI_30_LINK_ERROR_COUNT_MASK)
94090 /*! @} */
94091 
94092 /*! @name MFINDEX - Microframe Index Register */
94093 /*! @{ */
94094 
94095 #define USB_MFINDEX_MICROFRAME_INDEX_MASK        (0x3FFFU)
94096 #define USB_MFINDEX_MICROFRAME_INDEX_SHIFT       (0U)
94097 #define USB_MFINDEX_MICROFRAME_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << USB_MFINDEX_MICROFRAME_INDEX_SHIFT)) & USB_MFINDEX_MICROFRAME_INDEX_MASK)
94098 /*! @} */
94099 
94100 /*! @name IMAN - Interrupter Management Register */
94101 /*! @{ */
94102 
94103 #define USB_IMAN_IP_MASK                         (0x1U)
94104 #define USB_IMAN_IP_SHIFT                        (0U)
94105 /*! IP - IP Interrupt Pending */
94106 #define USB_IMAN_IP(x)                           (((uint32_t)(((uint32_t)(x)) << USB_IMAN_IP_SHIFT)) & USB_IMAN_IP_MASK)
94107 
94108 #define USB_IMAN_IE_MASK                         (0x2U)
94109 #define USB_IMAN_IE_SHIFT                        (1U)
94110 #define USB_IMAN_IE(x)                           (((uint32_t)(((uint32_t)(x)) << USB_IMAN_IE_SHIFT)) & USB_IMAN_IE_MASK)
94111 /*! @} */
94112 
94113 /*! @name IMOD - Interrupter Moderation Register */
94114 /*! @{ */
94115 
94116 #define USB_IMOD_IMODI_MASK                      (0xFFFFU)
94117 #define USB_IMOD_IMODI_SHIFT                     (0U)
94118 #define USB_IMOD_IMODI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_IMOD_IMODI_SHIFT)) & USB_IMOD_IMODI_MASK)
94119 
94120 #define USB_IMOD_IMODC_MASK                      (0xFFFF0000U)
94121 #define USB_IMOD_IMODC_SHIFT                     (16U)
94122 #define USB_IMOD_IMODC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_IMOD_IMODC_SHIFT)) & USB_IMOD_IMODC_MASK)
94123 /*! @} */
94124 
94125 /*! @name ERSTSZ - ERSTSZ */
94126 /*! @{ */
94127 
94128 #define USB_ERSTSZ_ERS_TABLE_SIZE_MASK           (0xFFFFU)
94129 #define USB_ERSTSZ_ERS_TABLE_SIZE_SHIFT          (0U)
94130 #define USB_ERSTSZ_ERS_TABLE_SIZE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ERSTSZ_ERS_TABLE_SIZE_SHIFT)) & USB_ERSTSZ_ERS_TABLE_SIZE_MASK)
94131 /*! @} */
94132 
94133 /*! @name ERSTBA_LO - ERSTBA_LO */
94134 /*! @{ */
94135 
94136 #define USB_ERSTBA_LO_ERS_TABLE_BAR_MASK         (0xFFFFFFC0U)
94137 #define USB_ERSTBA_LO_ERS_TABLE_BAR_SHIFT        (6U)
94138 #define USB_ERSTBA_LO_ERS_TABLE_BAR(x)           (((uint32_t)(((uint32_t)(x)) << USB_ERSTBA_LO_ERS_TABLE_BAR_SHIFT)) & USB_ERSTBA_LO_ERS_TABLE_BAR_MASK)
94139 /*! @} */
94140 
94141 /*! @name ERSTBA_HI - ERSTBA_HI */
94142 /*! @{ */
94143 
94144 #define USB_ERSTBA_HI_ERS_TABLE_BAR_MASK         (0xFFFFFFFFU)
94145 #define USB_ERSTBA_HI_ERS_TABLE_BAR_SHIFT        (0U)
94146 #define USB_ERSTBA_HI_ERS_TABLE_BAR(x)           (((uint32_t)(((uint32_t)(x)) << USB_ERSTBA_HI_ERS_TABLE_BAR_SHIFT)) & USB_ERSTBA_HI_ERS_TABLE_BAR_MASK)
94147 /*! @} */
94148 
94149 /*! @name ERDP_LO - ERDP_LO */
94150 /*! @{ */
94151 
94152 #define USB_ERDP_LO_DESI_MASK                    (0x7U)
94153 #define USB_ERDP_LO_DESI_SHIFT                   (0U)
94154 #define USB_ERDP_LO_DESI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_ERDP_LO_DESI_SHIFT)) & USB_ERDP_LO_DESI_MASK)
94155 
94156 #define USB_ERDP_LO_EHB_MASK                     (0x8U)
94157 #define USB_ERDP_LO_EHB_SHIFT                    (3U)
94158 /*! EHB - EHB */
94159 #define USB_ERDP_LO_EHB(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ERDP_LO_EHB_SHIFT)) & USB_ERDP_LO_EHB_MASK)
94160 
94161 #define USB_ERDP_LO_ERD_PNTR_MASK                (0xFFFFFFF0U)
94162 #define USB_ERDP_LO_ERD_PNTR_SHIFT               (4U)
94163 /*! ERD_PNTR - ERD_PNTR */
94164 #define USB_ERDP_LO_ERD_PNTR(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ERDP_LO_ERD_PNTR_SHIFT)) & USB_ERDP_LO_ERD_PNTR_MASK)
94165 /*! @} */
94166 
94167 /*! @name ERDP_HI - ERDP_HI */
94168 /*! @{ */
94169 
94170 #define USB_ERDP_HI_ERD_PNTR_MASK                (0xFFFFFFFFU)
94171 #define USB_ERDP_HI_ERD_PNTR_SHIFT               (0U)
94172 #define USB_ERDP_HI_ERD_PNTR(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ERDP_HI_ERD_PNTR_SHIFT)) & USB_ERDP_HI_ERD_PNTR_MASK)
94173 /*! @} */
94174 
94175 /*! @name DB - Doorbell Register */
94176 /*! @{ */
94177 
94178 #define USB_DB_DB_TARGET_MASK                    (0xFFU)
94179 #define USB_DB_DB_TARGET_SHIFT                   (0U)
94180 #define USB_DB_DB_TARGET(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DB_DB_TARGET_SHIFT)) & USB_DB_DB_TARGET_MASK)
94181 
94182 #define USB_DB_DB_STREAM_ID_MASK                 (0xFFFF0000U)
94183 #define USB_DB_DB_STREAM_ID_SHIFT                (16U)
94184 #define USB_DB_DB_STREAM_ID(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DB_DB_STREAM_ID_SHIFT)) & USB_DB_DB_STREAM_ID_MASK)
94185 /*! @} */
94186 
94187 /*! @name USBLEGSUP - USBLEGSUP */
94188 /*! @{ */
94189 
94190 #define USB_USBLEGSUP_CAPABILITY_ID_MASK         (0xFFU)
94191 #define USB_USBLEGSUP_CAPABILITY_ID_SHIFT        (0U)
94192 #define USB_USBLEGSUP_CAPABILITY_ID(x)           (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_CAPABILITY_ID_SHIFT)) & USB_USBLEGSUP_CAPABILITY_ID_MASK)
94193 
94194 #define USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK (0xFF00U)
94195 #define USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_SHIFT (8U)
94196 #define USB_USBLEGSUP_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_SHIFT)) & USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK)
94197 
94198 #define USB_USBLEGSUP_HC_BIOS_OWNED_MASK         (0x10000U)
94199 #define USB_USBLEGSUP_HC_BIOS_OWNED_SHIFT        (16U)
94200 #define USB_USBLEGSUP_HC_BIOS_OWNED(x)           (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_HC_BIOS_OWNED_SHIFT)) & USB_USBLEGSUP_HC_BIOS_OWNED_MASK)
94201 
94202 #define USB_USBLEGSUP_HC_OS_OWNED_MASK           (0x1000000U)
94203 #define USB_USBLEGSUP_HC_OS_OWNED_SHIFT          (24U)
94204 #define USB_USBLEGSUP_HC_OS_OWNED(x)             (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_HC_OS_OWNED_SHIFT)) & USB_USBLEGSUP_HC_OS_OWNED_MASK)
94205 /*! @} */
94206 
94207 /*! @name USBLEGCTLSTS - USBLEGCTLSTS */
94208 /*! @{ */
94209 
94210 #define USB_USBLEGCTLSTS_USB_SMI_ENABLE_MASK     (0x1U)
94211 #define USB_USBLEGCTLSTS_USB_SMI_ENABLE_SHIFT    (0U)
94212 #define USB_USBLEGCTLSTS_USB_SMI_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_USB_SMI_ENABLE_SHIFT)) & USB_USBLEGCTLSTS_USB_SMI_ENABLE_MASK)
94213 
94214 #define USB_USBLEGCTLSTS_SMI_ON_HOST_E_MASK      (0x10U)
94215 #define USB_USBLEGCTLSTS_SMI_ON_HOST_E_SHIFT     (4U)
94216 #define USB_USBLEGCTLSTS_SMI_ON_HOST_E(x)        (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_HOST_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_HOST_E_MASK)
94217 
94218 #define USB_USBLEGCTLSTS_SMI_ON_OS_E_MASK        (0x2000U)
94219 #define USB_USBLEGCTLSTS_SMI_ON_OS_E_SHIFT       (13U)
94220 #define USB_USBLEGCTLSTS_SMI_ON_OS_E(x)          (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_OS_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_OS_E_MASK)
94221 
94222 #define USB_USBLEGCTLSTS_SMI_ON_PCI_E_MASK       (0x4000U)
94223 #define USB_USBLEGCTLSTS_SMI_ON_PCI_E_SHIFT      (14U)
94224 #define USB_USBLEGCTLSTS_SMI_ON_PCI_E(x)         (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_PCI_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_PCI_E_MASK)
94225 
94226 #define USB_USBLEGCTLSTS_SMI_ON_BAR_E_MASK       (0x8000U)
94227 #define USB_USBLEGCTLSTS_SMI_ON_BAR_E_SHIFT      (15U)
94228 #define USB_USBLEGCTLSTS_SMI_ON_BAR_E(x)         (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_BAR_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_BAR_E_MASK)
94229 
94230 #define USB_USBLEGCTLSTS_SMI_ON_EVENT_MASK       (0x10000U)
94231 #define USB_USBLEGCTLSTS_SMI_ON_EVENT_SHIFT      (16U)
94232 #define USB_USBLEGCTLSTS_SMI_ON_EVENT(x)         (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_EVENT_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_EVENT_MASK)
94233 
94234 #define USB_USBLEGCTLSTS_SMI_ON_HOST_MASK        (0x100000U)
94235 #define USB_USBLEGCTLSTS_SMI_ON_HOST_SHIFT       (20U)
94236 #define USB_USBLEGCTLSTS_SMI_ON_HOST(x)          (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_HOST_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_HOST_MASK)
94237 
94238 #define USB_USBLEGCTLSTS_SMI_ON_OS_MASK          (0x20000000U)
94239 #define USB_USBLEGCTLSTS_SMI_ON_OS_SHIFT         (29U)
94240 #define USB_USBLEGCTLSTS_SMI_ON_OS(x)            (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_OS_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_OS_MASK)
94241 
94242 #define USB_USBLEGCTLSTS_SMI_ON_PCI_MASK         (0x40000000U)
94243 #define USB_USBLEGCTLSTS_SMI_ON_PCI_SHIFT        (30U)
94244 #define USB_USBLEGCTLSTS_SMI_ON_PCI(x)           (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_PCI_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_PCI_MASK)
94245 
94246 #define USB_USBLEGCTLSTS_SMI_ON_BAR_MASK         (0x80000000U)
94247 #define USB_USBLEGCTLSTS_SMI_ON_BAR_SHIFT        (31U)
94248 #define USB_USBLEGCTLSTS_SMI_ON_BAR(x)           (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_BAR_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_BAR_MASK)
94249 /*! @} */
94250 
94251 /*! @name SUPTPRT2_DW0 - SUPTPRT2_DW0 */
94252 /*! @{ */
94253 
94254 #define USB_SUPTPRT2_DW0_CAPABILITY_ID_MASK      (0xFFU)
94255 #define USB_SUPTPRT2_DW0_CAPABILITY_ID_SHIFT     (0U)
94256 #define USB_SUPTPRT2_DW0_CAPABILITY_ID(x)        (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_CAPABILITY_ID_SHIFT)) & USB_SUPTPRT2_DW0_CAPABILITY_ID_MASK)
94257 
94258 #define USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK (0xFF00U)
94259 #define USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_SHIFT (8U)
94260 #define USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_SHIFT)) & USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK)
94261 
94262 #define USB_SUPTPRT2_DW0_MINOR_REVISION_MASK     (0xFF0000U)
94263 #define USB_SUPTPRT2_DW0_MINOR_REVISION_SHIFT    (16U)
94264 #define USB_SUPTPRT2_DW0_MINOR_REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_MINOR_REVISION_SHIFT)) & USB_SUPTPRT2_DW0_MINOR_REVISION_MASK)
94265 
94266 #define USB_SUPTPRT2_DW0_MAJOR_REVISION_MASK     (0xFF000000U)
94267 #define USB_SUPTPRT2_DW0_MAJOR_REVISION_SHIFT    (24U)
94268 #define USB_SUPTPRT2_DW0_MAJOR_REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_MAJOR_REVISION_SHIFT)) & USB_SUPTPRT2_DW0_MAJOR_REVISION_MASK)
94269 /*! @} */
94270 
94271 /*! @name SUPTPRT2_DW1 - SUPTPRT2_DW1 Register */
94272 /*! @{ */
94273 
94274 #define USB_SUPTPRT2_DW1_NAME_STRING_MASK        (0xFFFFFFFFU)
94275 #define USB_SUPTPRT2_DW1_NAME_STRING_SHIFT       (0U)
94276 #define USB_SUPTPRT2_DW1_NAME_STRING(x)          (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW1_NAME_STRING_SHIFT)) & USB_SUPTPRT2_DW1_NAME_STRING_MASK)
94277 /*! @} */
94278 
94279 /*! @name SUPTPRT2_DW2 - xHCI Supported Protocol Capability_ Data Word 2 */
94280 /*! @{ */
94281 
94282 #define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK (0xFFU)
94283 #define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_SHIFT (0U)
94284 #define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_SHIFT)) & USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK)
94285 
94286 #define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK (0xFF00U)
94287 #define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_SHIFT (8U)
94288 #define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_SHIFT)) & USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK)
94289 
94290 #define USB_SUPTPRT2_DW2_HSO_MASK                (0x20000U)
94291 #define USB_SUPTPRT2_DW2_HSO_SHIFT               (17U)
94292 #define USB_SUPTPRT2_DW2_HSO(x)                  (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_HSO_SHIFT)) & USB_SUPTPRT2_DW2_HSO_MASK)
94293 
94294 #define USB_SUPTPRT2_DW2_IHI_MASK                (0x40000U)
94295 #define USB_SUPTPRT2_DW2_IHI_SHIFT               (18U)
94296 #define USB_SUPTPRT2_DW2_IHI(x)                  (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_IHI_SHIFT)) & USB_SUPTPRT2_DW2_IHI_MASK)
94297 
94298 #define USB_SUPTPRT2_DW2_HLC_MASK                (0x80000U)
94299 #define USB_SUPTPRT2_DW2_HLC_SHIFT               (19U)
94300 #define USB_SUPTPRT2_DW2_HLC(x)                  (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_HLC_SHIFT)) & USB_SUPTPRT2_DW2_HLC_MASK)
94301 
94302 #define USB_SUPTPRT2_DW2_BLC_MASK                (0x100000U)
94303 #define USB_SUPTPRT2_DW2_BLC_SHIFT               (20U)
94304 /*! BLC - BESL LPM Capability */
94305 #define USB_SUPTPRT2_DW2_BLC(x)                  (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_BLC_SHIFT)) & USB_SUPTPRT2_DW2_BLC_MASK)
94306 
94307 #define USB_SUPTPRT2_DW2_MHD_MASK                (0xE000000U)
94308 #define USB_SUPTPRT2_DW2_MHD_SHIFT               (25U)
94309 /*! MHD - Hub Depth */
94310 #define USB_SUPTPRT2_DW2_MHD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_MHD_SHIFT)) & USB_SUPTPRT2_DW2_MHD_MASK)
94311 
94312 #define USB_SUPTPRT2_DW2_PSIC_MASK               (0xF0000000U)
94313 #define USB_SUPTPRT2_DW2_PSIC_SHIFT              (28U)
94314 #define USB_SUPTPRT2_DW2_PSIC(x)                 (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_PSIC_SHIFT)) & USB_SUPTPRT2_DW2_PSIC_MASK)
94315 /*! @} */
94316 
94317 /*! @name SUPTPRT2_DW3 - SUPTPRT2_DW3 Register */
94318 /*! @{ */
94319 
94320 #define USB_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK      (0x1FU)
94321 #define USB_SUPTPRT2_DW3_PROTCL_SLT_TY_SHIFT     (0U)
94322 #define USB_SUPTPRT2_DW3_PROTCL_SLT_TY(x)        (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW3_PROTCL_SLT_TY_SHIFT)) & USB_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK)
94323 /*! @} */
94324 
94325 /*! @name SUPTPRT3_DW0 -  */
94326 /*! @{ */
94327 
94328 #define USB_SUPTPRT3_DW0_CAPABILITY_ID_MASK      (0xFFU)
94329 #define USB_SUPTPRT3_DW0_CAPABILITY_ID_SHIFT     (0U)
94330 #define USB_SUPTPRT3_DW0_CAPABILITY_ID(x)        (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_CAPABILITY_ID_SHIFT)) & USB_SUPTPRT3_DW0_CAPABILITY_ID_MASK)
94331 
94332 #define USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK (0xFF00U)
94333 #define USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_SHIFT (8U)
94334 #define USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_SHIFT)) & USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK)
94335 
94336 #define USB_SUPTPRT3_DW0_MINOR_REVISION_MASK     (0xFF0000U)
94337 #define USB_SUPTPRT3_DW0_MINOR_REVISION_SHIFT    (16U)
94338 #define USB_SUPTPRT3_DW0_MINOR_REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_MINOR_REVISION_SHIFT)) & USB_SUPTPRT3_DW0_MINOR_REVISION_MASK)
94339 
94340 #define USB_SUPTPRT3_DW0_MAJOR_REVISION_MASK     (0xFF000000U)
94341 #define USB_SUPTPRT3_DW0_MAJOR_REVISION_SHIFT    (24U)
94342 #define USB_SUPTPRT3_DW0_MAJOR_REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_MAJOR_REVISION_SHIFT)) & USB_SUPTPRT3_DW0_MAJOR_REVISION_MASK)
94343 /*! @} */
94344 
94345 /*! @name SUPTPRT3_DW1 - SUPTPRT3_DW1 Register */
94346 /*! @{ */
94347 
94348 #define USB_SUPTPRT3_DW1_NAME_STRING_MASK        (0xFFFFFFFFU)
94349 #define USB_SUPTPRT3_DW1_NAME_STRING_SHIFT       (0U)
94350 /*! NAME_STRING - NAME_STRING */
94351 #define USB_SUPTPRT3_DW1_NAME_STRING(x)          (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW1_NAME_STRING_SHIFT)) & USB_SUPTPRT3_DW1_NAME_STRING_MASK)
94352 /*! @} */
94353 
94354 /*! @name SUPTPRT3_DW2 - SUPTPRT3_DW2 */
94355 /*! @{ */
94356 
94357 #define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK (0xFFU)
94358 #define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_SHIFT (0U)
94359 /*! COMPATIBLE_PORT_OFFSET - COMPATIBLE_PORT_OFFSET */
94360 #define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_SHIFT)) & USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK)
94361 
94362 #define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK (0xFF00U)
94363 #define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_SHIFT (8U)
94364 /*! COMPATIBLE_PORT_COUNT - COMPATIBLE_PORT_COUNT */
94365 #define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_SHIFT)) & USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK)
94366 
94367 #define USB_SUPTPRT3_DW2_MHD_MASK                (0xE000000U)
94368 #define USB_SUPTPRT3_DW2_MHD_SHIFT               (25U)
94369 /*! MHD - Hub Depth */
94370 #define USB_SUPTPRT3_DW2_MHD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_MHD_SHIFT)) & USB_SUPTPRT3_DW2_MHD_MASK)
94371 
94372 #define USB_SUPTPRT3_DW2_PSIC_MASK               (0xF0000000U)
94373 #define USB_SUPTPRT3_DW2_PSIC_SHIFT              (28U)
94374 #define USB_SUPTPRT3_DW2_PSIC(x)                 (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_PSIC_SHIFT)) & USB_SUPTPRT3_DW2_PSIC_MASK)
94375 /*! @} */
94376 
94377 /*! @name SUPTPRT3_DW3 - SUPTPRT3_DW3 */
94378 /*! @{ */
94379 
94380 #define USB_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK      (0x1FU)
94381 #define USB_SUPTPRT3_DW3_PROTCL_SLT_TY_SHIFT     (0U)
94382 /*! PROTCL_SLT_TY - Protocol Slot Type */
94383 #define USB_SUPTPRT3_DW3_PROTCL_SLT_TY(x)        (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW3_PROTCL_SLT_TY_SHIFT)) & USB_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK)
94384 /*! @} */
94385 
94386 /*! @name GSBUSCFG0 - Global SoC Bus Configuration Register 0 */
94387 /*! @{ */
94388 
94389 #define USB_GSBUSCFG0_INCRBRSTENA_MASK           (0x1U)
94390 #define USB_GSBUSCFG0_INCRBRSTENA_SHIFT          (0U)
94391 /*! INCRBRSTENA - INCRBRSTENA */
94392 #define USB_GSBUSCFG0_INCRBRSTENA(x)             (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCRBRSTENA_SHIFT)) & USB_GSBUSCFG0_INCRBRSTENA_MASK)
94393 
94394 #define USB_GSBUSCFG0_INCR4BRSTENA_MASK          (0x2U)
94395 #define USB_GSBUSCFG0_INCR4BRSTENA_SHIFT         (1U)
94396 /*! INCR4BRSTENA - INCR4BRSTENA */
94397 #define USB_GSBUSCFG0_INCR4BRSTENA(x)            (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR4BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR4BRSTENA_MASK)
94398 
94399 #define USB_GSBUSCFG0_INCR8BRSTENA_MASK          (0x4U)
94400 #define USB_GSBUSCFG0_INCR8BRSTENA_SHIFT         (2U)
94401 /*! INCR8BRSTENA - INCR8BRSTENA */
94402 #define USB_GSBUSCFG0_INCR8BRSTENA(x)            (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR8BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR8BRSTENA_MASK)
94403 
94404 #define USB_GSBUSCFG0_INCR16BRSTENA_MASK         (0x8U)
94405 #define USB_GSBUSCFG0_INCR16BRSTENA_SHIFT        (3U)
94406 /*! INCR16BRSTENA - INCR16BRSTENA */
94407 #define USB_GSBUSCFG0_INCR16BRSTENA(x)           (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR16BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR16BRSTENA_MASK)
94408 
94409 #define USB_GSBUSCFG0_INCR32BRSTENA_MASK         (0x10U)
94410 #define USB_GSBUSCFG0_INCR32BRSTENA_SHIFT        (4U)
94411 /*! INCR32BRSTENA - INCR32BRSTENA */
94412 #define USB_GSBUSCFG0_INCR32BRSTENA(x)           (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR32BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR32BRSTENA_MASK)
94413 
94414 #define USB_GSBUSCFG0_INCR64BRSTENA_MASK         (0x20U)
94415 #define USB_GSBUSCFG0_INCR64BRSTENA_SHIFT        (5U)
94416 #define USB_GSBUSCFG0_INCR64BRSTENA(x)           (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR64BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR64BRSTENA_MASK)
94417 
94418 #define USB_GSBUSCFG0_INCR128BRSTENA_MASK        (0x40U)
94419 #define USB_GSBUSCFG0_INCR128BRSTENA_SHIFT       (6U)
94420 #define USB_GSBUSCFG0_INCR128BRSTENA(x)          (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR128BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR128BRSTENA_MASK)
94421 
94422 #define USB_GSBUSCFG0_INCR256BRSTENA_MASK        (0x80U)
94423 #define USB_GSBUSCFG0_INCR256BRSTENA_SHIFT       (7U)
94424 #define USB_GSBUSCFG0_INCR256BRSTENA(x)          (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR256BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR256BRSTENA_MASK)
94425 
94426 #define USB_GSBUSCFG0_DESBIGEND_MASK             (0x400U)
94427 #define USB_GSBUSCFG0_DESBIGEND_SHIFT            (10U)
94428 #define USB_GSBUSCFG0_DESBIGEND(x)               (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DESBIGEND_SHIFT)) & USB_GSBUSCFG0_DESBIGEND_MASK)
94429 
94430 #define USB_GSBUSCFG0_DATBIGEND_MASK             (0x800U)
94431 #define USB_GSBUSCFG0_DATBIGEND_SHIFT            (11U)
94432 #define USB_GSBUSCFG0_DATBIGEND(x)               (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DATBIGEND_SHIFT)) & USB_GSBUSCFG0_DATBIGEND_MASK)
94433 
94434 #define USB_GSBUSCFG0_DESWRREQINFO_MASK          (0xF0000U)
94435 #define USB_GSBUSCFG0_DESWRREQINFO_SHIFT         (16U)
94436 #define USB_GSBUSCFG0_DESWRREQINFO(x)            (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DESWRREQINFO_SHIFT)) & USB_GSBUSCFG0_DESWRREQINFO_MASK)
94437 
94438 #define USB_GSBUSCFG0_DATWRREQINFO_MASK          (0xF00000U)
94439 #define USB_GSBUSCFG0_DATWRREQINFO_SHIFT         (20U)
94440 #define USB_GSBUSCFG0_DATWRREQINFO(x)            (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DATWRREQINFO_SHIFT)) & USB_GSBUSCFG0_DATWRREQINFO_MASK)
94441 
94442 #define USB_GSBUSCFG0_DESRDREQINFO_MASK          (0xF000000U)
94443 #define USB_GSBUSCFG0_DESRDREQINFO_SHIFT         (24U)
94444 #define USB_GSBUSCFG0_DESRDREQINFO(x)            (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DESRDREQINFO_SHIFT)) & USB_GSBUSCFG0_DESRDREQINFO_MASK)
94445 
94446 #define USB_GSBUSCFG0_DATRDREQINFO_MASK          (0xF0000000U)
94447 #define USB_GSBUSCFG0_DATRDREQINFO_SHIFT         (28U)
94448 #define USB_GSBUSCFG0_DATRDREQINFO(x)            (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DATRDREQINFO_SHIFT)) & USB_GSBUSCFG0_DATRDREQINFO_MASK)
94449 /*! @} */
94450 
94451 /*! @name GSBUSCFG1 - Global SoC Bus Configuration Register 1 */
94452 /*! @{ */
94453 
94454 #define USB_GSBUSCFG1_PIPETRANSLIMIT_MASK        (0xF00U)
94455 #define USB_GSBUSCFG1_PIPETRANSLIMIT_SHIFT       (8U)
94456 #define USB_GSBUSCFG1_PIPETRANSLIMIT(x)          (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG1_PIPETRANSLIMIT_SHIFT)) & USB_GSBUSCFG1_PIPETRANSLIMIT_MASK)
94457 
94458 #define USB_GSBUSCFG1_EN1KPAGE_MASK              (0x1000U)
94459 #define USB_GSBUSCFG1_EN1KPAGE_SHIFT             (12U)
94460 #define USB_GSBUSCFG1_EN1KPAGE(x)                (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG1_EN1KPAGE_SHIFT)) & USB_GSBUSCFG1_EN1KPAGE_MASK)
94461 /*! @} */
94462 
94463 /*! @name GTXTHRCFG - Global Tx Threshold Control Register */
94464 /*! @{ */
94465 
94466 #define USB_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK     (0xFF0000U)
94467 #define USB_GTXTHRCFG_USBMAXTXBURSTSIZE_SHIFT    (16U)
94468 #define USB_GTXTHRCFG_USBMAXTXBURSTSIZE(x)       (((uint32_t)(((uint32_t)(x)) << USB_GTXTHRCFG_USBMAXTXBURSTSIZE_SHIFT)) & USB_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK)
94469 
94470 #define USB_GTXTHRCFG_USBTXPKTCNT_MASK           (0xF000000U)
94471 #define USB_GTXTHRCFG_USBTXPKTCNT_SHIFT          (24U)
94472 #define USB_GTXTHRCFG_USBTXPKTCNT(x)             (((uint32_t)(((uint32_t)(x)) << USB_GTXTHRCFG_USBTXPKTCNT_SHIFT)) & USB_GTXTHRCFG_USBTXPKTCNT_MASK)
94473 
94474 #define USB_GTXTHRCFG_USBTXPKTCNTSEL_MASK        (0x20000000U)
94475 #define USB_GTXTHRCFG_USBTXPKTCNTSEL_SHIFT       (29U)
94476 #define USB_GTXTHRCFG_USBTXPKTCNTSEL(x)          (((uint32_t)(((uint32_t)(x)) << USB_GTXTHRCFG_USBTXPKTCNTSEL_SHIFT)) & USB_GTXTHRCFG_USBTXPKTCNTSEL_MASK)
94477 /*! @} */
94478 
94479 /*! @name GRXTHRCFG - Global Rx Threshold Control Register */
94480 /*! @{ */
94481 
94482 #define USB_GRXTHRCFG_RESVISOCOUTSPC_MASK        (0x1FFFU)
94483 #define USB_GRXTHRCFG_RESVISOCOUTSPC_SHIFT       (0U)
94484 #define USB_GRXTHRCFG_RESVISOCOUTSPC(x)          (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_RESVISOCOUTSPC_SHIFT)) & USB_GRXTHRCFG_RESVISOCOUTSPC_MASK)
94485 
94486 #define USB_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK     (0xF80000U)
94487 #define USB_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT    (19U)
94488 #define USB_GRXTHRCFG_USBMAXRXBURSTSIZE(x)       (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT)) & USB_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK)
94489 
94490 #define USB_GRXTHRCFG_USBRXPKTCNT_MASK           (0xF000000U)
94491 #define USB_GRXTHRCFG_USBRXPKTCNT_SHIFT          (24U)
94492 #define USB_GRXTHRCFG_USBRXPKTCNT(x)             (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_USBRXPKTCNT_SHIFT)) & USB_GRXTHRCFG_USBRXPKTCNT_MASK)
94493 
94494 #define USB_GRXTHRCFG_USBRXPKTCNTSEL_MASK        (0x20000000U)
94495 #define USB_GRXTHRCFG_USBRXPKTCNTSEL_SHIFT       (29U)
94496 #define USB_GRXTHRCFG_USBRXPKTCNTSEL(x)          (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_USBRXPKTCNTSEL_SHIFT)) & USB_GRXTHRCFG_USBRXPKTCNTSEL_MASK)
94497 /*! @} */
94498 
94499 /*! @name GCTL - Global Core Control Register */
94500 /*! @{ */
94501 
94502 #define USB_GCTL_DSBLCLKGTNG_MASK                (0x1U)
94503 #define USB_GCTL_DSBLCLKGTNG_SHIFT               (0U)
94504 #define USB_GCTL_DSBLCLKGTNG(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GCTL_DSBLCLKGTNG_SHIFT)) & USB_GCTL_DSBLCLKGTNG_MASK)
94505 
94506 #define USB_GCTL_GBLHIBERNATIONEN_MASK           (0x2U)
94507 #define USB_GCTL_GBLHIBERNATIONEN_SHIFT          (1U)
94508 #define USB_GCTL_GBLHIBERNATIONEN(x)             (((uint32_t)(((uint32_t)(x)) << USB_GCTL_GBLHIBERNATIONEN_SHIFT)) & USB_GCTL_GBLHIBERNATIONEN_MASK)
94509 
94510 #define USB_GCTL_U2EXIT_LFPS_MASK                (0x4U)
94511 #define USB_GCTL_U2EXIT_LFPS_SHIFT               (2U)
94512 #define USB_GCTL_U2EXIT_LFPS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GCTL_U2EXIT_LFPS_SHIFT)) & USB_GCTL_U2EXIT_LFPS_MASK)
94513 
94514 #define USB_GCTL_DISSCRAMBLE_MASK                (0x8U)
94515 #define USB_GCTL_DISSCRAMBLE_SHIFT               (3U)
94516 #define USB_GCTL_DISSCRAMBLE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GCTL_DISSCRAMBLE_SHIFT)) & USB_GCTL_DISSCRAMBLE_MASK)
94517 
94518 #define USB_GCTL_SCALEDOWN_MASK                  (0x30U)
94519 #define USB_GCTL_SCALEDOWN_SHIFT                 (4U)
94520 #define USB_GCTL_SCALEDOWN(x)                    (((uint32_t)(((uint32_t)(x)) << USB_GCTL_SCALEDOWN_SHIFT)) & USB_GCTL_SCALEDOWN_MASK)
94521 
94522 #define USB_GCTL_RAMCLKSEL_MASK                  (0xC0U)
94523 #define USB_GCTL_RAMCLKSEL_SHIFT                 (6U)
94524 #define USB_GCTL_RAMCLKSEL(x)                    (((uint32_t)(((uint32_t)(x)) << USB_GCTL_RAMCLKSEL_SHIFT)) & USB_GCTL_RAMCLKSEL_MASK)
94525 
94526 #define USB_GCTL_DEBUGATTACH_MASK                (0x100U)
94527 #define USB_GCTL_DEBUGATTACH_SHIFT               (8U)
94528 #define USB_GCTL_DEBUGATTACH(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GCTL_DEBUGATTACH_SHIFT)) & USB_GCTL_DEBUGATTACH_MASK)
94529 
94530 #define USB_GCTL_U1U2TIMERSCALE_MASK             (0x200U)
94531 #define USB_GCTL_U1U2TIMERSCALE_SHIFT            (9U)
94532 #define USB_GCTL_U1U2TIMERSCALE(x)               (((uint32_t)(((uint32_t)(x)) << USB_GCTL_U1U2TIMERSCALE_SHIFT)) & USB_GCTL_U1U2TIMERSCALE_MASK)
94533 
94534 #define USB_GCTL_SOFITPSYNC_MASK                 (0x400U)
94535 #define USB_GCTL_SOFITPSYNC_SHIFT                (10U)
94536 #define USB_GCTL_SOFITPSYNC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_GCTL_SOFITPSYNC_SHIFT)) & USB_GCTL_SOFITPSYNC_MASK)
94537 
94538 #define USB_GCTL_CORESOFTRESET_MASK              (0x800U)
94539 #define USB_GCTL_CORESOFTRESET_SHIFT             (11U)
94540 #define USB_GCTL_CORESOFTRESET(x)                (((uint32_t)(((uint32_t)(x)) << USB_GCTL_CORESOFTRESET_SHIFT)) & USB_GCTL_CORESOFTRESET_MASK)
94541 
94542 #define USB_GCTL_PRTCAPDIR_MASK                  (0x3000U)
94543 #define USB_GCTL_PRTCAPDIR_SHIFT                 (12U)
94544 #define USB_GCTL_PRTCAPDIR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_GCTL_PRTCAPDIR_SHIFT)) & USB_GCTL_PRTCAPDIR_MASK)
94545 
94546 #define USB_GCTL_FRMSCLDWN_MASK                  (0xC000U)
94547 #define USB_GCTL_FRMSCLDWN_SHIFT                 (14U)
94548 #define USB_GCTL_FRMSCLDWN(x)                    (((uint32_t)(((uint32_t)(x)) << USB_GCTL_FRMSCLDWN_SHIFT)) & USB_GCTL_FRMSCLDWN_MASK)
94549 
94550 #define USB_GCTL_U2RSTECN_MASK                   (0x10000U)
94551 #define USB_GCTL_U2RSTECN_SHIFT                  (16U)
94552 #define USB_GCTL_U2RSTECN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_GCTL_U2RSTECN_SHIFT)) & USB_GCTL_U2RSTECN_MASK)
94553 
94554 #define USB_GCTL_BYPSSETADDR_MASK                (0x20000U)
94555 #define USB_GCTL_BYPSSETADDR_SHIFT               (17U)
94556 #define USB_GCTL_BYPSSETADDR(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GCTL_BYPSSETADDR_SHIFT)) & USB_GCTL_BYPSSETADDR_MASK)
94557 
94558 #define USB_GCTL_MASTERFILTBYPASS_MASK           (0x40000U)
94559 #define USB_GCTL_MASTERFILTBYPASS_SHIFT          (18U)
94560 #define USB_GCTL_MASTERFILTBYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USB_GCTL_MASTERFILTBYPASS_SHIFT)) & USB_GCTL_MASTERFILTBYPASS_MASK)
94561 
94562 #define USB_GCTL_PWRDNSCALE_MASK                 (0xFFF80000U)
94563 #define USB_GCTL_PWRDNSCALE_SHIFT                (19U)
94564 #define USB_GCTL_PWRDNSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_GCTL_PWRDNSCALE_SHIFT)) & USB_GCTL_PWRDNSCALE_MASK)
94565 /*! @} */
94566 
94567 /*! @name GSTS - Global Status Register */
94568 /*! @{ */
94569 
94570 #define USB_GSTS_CURMOD_MASK                     (0x3U)
94571 #define USB_GSTS_CURMOD_SHIFT                    (0U)
94572 #define USB_GSTS_CURMOD(x)                       (((uint32_t)(((uint32_t)(x)) << USB_GSTS_CURMOD_SHIFT)) & USB_GSTS_CURMOD_MASK)
94573 
94574 #define USB_GSTS_BUSERRADDRVLD_MASK              (0x10U)
94575 #define USB_GSTS_BUSERRADDRVLD_SHIFT             (4U)
94576 #define USB_GSTS_BUSERRADDRVLD(x)                (((uint32_t)(((uint32_t)(x)) << USB_GSTS_BUSERRADDRVLD_SHIFT)) & USB_GSTS_BUSERRADDRVLD_MASK)
94577 
94578 #define USB_GSTS_CSRTIMEOUT_MASK                 (0x20U)
94579 #define USB_GSTS_CSRTIMEOUT_SHIFT                (5U)
94580 #define USB_GSTS_CSRTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_GSTS_CSRTIMEOUT_SHIFT)) & USB_GSTS_CSRTIMEOUT_MASK)
94581 
94582 #define USB_GSTS_DEVICE_IP_MASK                  (0x40U)
94583 #define USB_GSTS_DEVICE_IP_SHIFT                 (6U)
94584 #define USB_GSTS_DEVICE_IP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_GSTS_DEVICE_IP_SHIFT)) & USB_GSTS_DEVICE_IP_MASK)
94585 
94586 #define USB_GSTS_HOST_IP_MASK                    (0x80U)
94587 #define USB_GSTS_HOST_IP_SHIFT                   (7U)
94588 #define USB_GSTS_HOST_IP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_GSTS_HOST_IP_SHIFT)) & USB_GSTS_HOST_IP_MASK)
94589 
94590 #define USB_GSTS_BC_IP_MASK                      (0x200U)
94591 #define USB_GSTS_BC_IP_SHIFT                     (9U)
94592 #define USB_GSTS_BC_IP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_GSTS_BC_IP_SHIFT)) & USB_GSTS_BC_IP_MASK)
94593 
94594 #define USB_GSTS_SSIC_IP_MASK                    (0x800U)
94595 #define USB_GSTS_SSIC_IP_SHIFT                   (11U)
94596 #define USB_GSTS_SSIC_IP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_GSTS_SSIC_IP_SHIFT)) & USB_GSTS_SSIC_IP_MASK)
94597 
94598 #define USB_GSTS_CBELT_MASK                      (0xFFF00000U)
94599 #define USB_GSTS_CBELT_SHIFT                     (20U)
94600 #define USB_GSTS_CBELT(x)                        (((uint32_t)(((uint32_t)(x)) << USB_GSTS_CBELT_SHIFT)) & USB_GSTS_CBELT_MASK)
94601 /*! @} */
94602 
94603 /*! @name GUCTL1 -  */
94604 /*! @{ */
94605 
94606 #define USB_GUCTL1_LOA_FILTER_EN_MASK            (0x1U)
94607 #define USB_GUCTL1_LOA_FILTER_EN_SHIFT           (0U)
94608 #define USB_GUCTL1_LOA_FILTER_EN(x)              (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_LOA_FILTER_EN_SHIFT)) & USB_GUCTL1_LOA_FILTER_EN_MASK)
94609 
94610 #define USB_GUCTL1_OVRLD_L1_SUSP_COM_MASK        (0x2U)
94611 #define USB_GUCTL1_OVRLD_L1_SUSP_COM_SHIFT       (1U)
94612 #define USB_GUCTL1_OVRLD_L1_SUSP_COM(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_OVRLD_L1_SUSP_COM_SHIFT)) & USB_GUCTL1_OVRLD_L1_SUSP_COM_MASK)
94613 
94614 #define USB_GUCTL1_HC_PARCHK_DISABLE_MASK        (0x4U)
94615 #define USB_GUCTL1_HC_PARCHK_DISABLE_SHIFT       (2U)
94616 #define USB_GUCTL1_HC_PARCHK_DISABLE(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_HC_PARCHK_DISABLE_SHIFT)) & USB_GUCTL1_HC_PARCHK_DISABLE_MASK)
94617 
94618 #define USB_GUCTL1_HC_ERRATA_ENABLE_MASK         (0x8U)
94619 #define USB_GUCTL1_HC_ERRATA_ENABLE_SHIFT        (3U)
94620 #define USB_GUCTL1_HC_ERRATA_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_HC_ERRATA_ENABLE_SHIFT)) & USB_GUCTL1_HC_ERRATA_ENABLE_MASK)
94621 
94622 #define USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK   (0xF0U)
94623 #define USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_SHIFT  (4U)
94624 #define USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST(x)     (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_SHIFT)) & USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK)
94625 
94626 #define USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_MASK (0x100U)
94627 #define USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_SHIFT (8U)
94628 #define USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST(x)  (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_SHIFT)) & USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_MASK)
94629 
94630 #define USB_GUCTL1_DEV_HS_NYET_BULK_SPR_MASK     (0x200U)
94631 #define USB_GUCTL1_DEV_HS_NYET_BULK_SPR_SHIFT    (9U)
94632 #define USB_GUCTL1_DEV_HS_NYET_BULK_SPR(x)       (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_HS_NYET_BULK_SPR_SHIFT)) & USB_GUCTL1_DEV_HS_NYET_BULK_SPR_MASK)
94633 
94634 #define USB_GUCTL1_RESUME_OPMODE_HS_HOST_MASK    (0x400U)
94635 #define USB_GUCTL1_RESUME_OPMODE_HS_HOST_SHIFT   (10U)
94636 #define USB_GUCTL1_RESUME_OPMODE_HS_HOST(x)      (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_RESUME_OPMODE_HS_HOST_SHIFT)) & USB_GUCTL1_RESUME_OPMODE_HS_HOST_MASK)
94637 
94638 #define USB_GUCTL1_PARKMODE_DISABLE_FSLS_MASK    (0x8000U)
94639 #define USB_GUCTL1_PARKMODE_DISABLE_FSLS_SHIFT   (15U)
94640 #define USB_GUCTL1_PARKMODE_DISABLE_FSLS(x)      (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_PARKMODE_DISABLE_FSLS_SHIFT)) & USB_GUCTL1_PARKMODE_DISABLE_FSLS_MASK)
94641 
94642 #define USB_GUCTL1_PARKMODE_DISABLE_HS_MASK      (0x10000U)
94643 #define USB_GUCTL1_PARKMODE_DISABLE_HS_SHIFT     (16U)
94644 #define USB_GUCTL1_PARKMODE_DISABLE_HS(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_PARKMODE_DISABLE_HS_SHIFT)) & USB_GUCTL1_PARKMODE_DISABLE_HS_MASK)
94645 
94646 #define USB_GUCTL1_PARKMODE_DISABLE_SS_MASK      (0x20000U)
94647 #define USB_GUCTL1_PARKMODE_DISABLE_SS_SHIFT     (17U)
94648 #define USB_GUCTL1_PARKMODE_DISABLE_SS(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_PARKMODE_DISABLE_SS_SHIFT)) & USB_GUCTL1_PARKMODE_DISABLE_SS_MASK)
94649 
94650 #define USB_GUCTL1_NAK_PER_ENH_HS_MASK           (0x40000U)
94651 #define USB_GUCTL1_NAK_PER_ENH_HS_SHIFT          (18U)
94652 #define USB_GUCTL1_NAK_PER_ENH_HS(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_NAK_PER_ENH_HS_SHIFT)) & USB_GUCTL1_NAK_PER_ENH_HS_MASK)
94653 
94654 #define USB_GUCTL1_NAK_PER_ENH_FS_MASK           (0x80000U)
94655 #define USB_GUCTL1_NAK_PER_ENH_FS_SHIFT          (19U)
94656 #define USB_GUCTL1_NAK_PER_ENH_FS(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_NAK_PER_ENH_FS_SHIFT)) & USB_GUCTL1_NAK_PER_ENH_FS_MASK)
94657 
94658 #define USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_MASK    (0x100000U)
94659 #define USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_SHIFT   (20U)
94660 #define USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS(x)      (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_SHIFT)) & USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_MASK)
94661 
94662 #define USB_GUCTL1_IP_GAP_ADD_ON_MASK            (0xE00000U)
94663 #define USB_GUCTL1_IP_GAP_ADD_ON_SHIFT           (21U)
94664 #define USB_GUCTL1_IP_GAP_ADD_ON(x)              (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_IP_GAP_ADD_ON_SHIFT)) & USB_GUCTL1_IP_GAP_ADD_ON_MASK)
94665 
94666 #define USB_GUCTL1_DEV_L1_EXIT_BY_HW_MASK        (0x1000000U)
94667 #define USB_GUCTL1_DEV_L1_EXIT_BY_HW_SHIFT       (24U)
94668 #define USB_GUCTL1_DEV_L1_EXIT_BY_HW(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_L1_EXIT_BY_HW_SHIFT)) & USB_GUCTL1_DEV_L1_EXIT_BY_HW_MASK)
94669 
94670 #define USB_GUCTL1_P3_IN_U2_MASK                 (0x2000000U)
94671 #define USB_GUCTL1_P3_IN_U2_SHIFT                (25U)
94672 #define USB_GUCTL1_P3_IN_U2(x)                   (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_P3_IN_U2_SHIFT)) & USB_GUCTL1_P3_IN_U2_MASK)
94673 
94674 #define USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_MASK (0x4000000U)
94675 #define USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_SHIFT (26U)
94676 #define USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_SHIFT)) & USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_MASK)
94677 
94678 #define USB_GUCTL1_DEV_TRB_OUT_SPR_IND_MASK      (0x8000000U)
94679 #define USB_GUCTL1_DEV_TRB_OUT_SPR_IND_SHIFT     (27U)
94680 #define USB_GUCTL1_DEV_TRB_OUT_SPR_IND(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_TRB_OUT_SPR_IND_SHIFT)) & USB_GUCTL1_DEV_TRB_OUT_SPR_IND_MASK)
94681 
94682 #define USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_MASK   (0x10000000U)
94683 #define USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_SHIFT  (28U)
94684 #define USB_GUCTL1_TX_IPGAP_LINECHECK_DIS(x)     (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_SHIFT)) & USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_MASK)
94685 
94686 #define USB_GUCTL1_FILTER_SE0_FSLS_EOP_MASK      (0x20000000U)
94687 #define USB_GUCTL1_FILTER_SE0_FSLS_EOP_SHIFT     (29U)
94688 #define USB_GUCTL1_FILTER_SE0_FSLS_EOP(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_FILTER_SE0_FSLS_EOP_SHIFT)) & USB_GUCTL1_FILTER_SE0_FSLS_EOP_MASK)
94689 
94690 #define USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_MASK   (0x40000000U)
94691 #define USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_SHIFT  (30U)
94692 #define USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_SHIFT)) & USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_MASK)
94693 
94694 #define USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_MASK    (0x80000000U)
94695 #define USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_SHIFT   (31U)
94696 #define USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT(x)      (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_SHIFT)) & USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_MASK)
94697 /*! @} */
94698 
94699 /*! @name GUID - Global User ID Register */
94700 /*! @{ */
94701 
94702 #define USB_GUID_USERID_MASK                     (0xFFFFFFFFU)
94703 #define USB_GUID_USERID_SHIFT                    (0U)
94704 #define USB_GUID_USERID(x)                       (((uint32_t)(((uint32_t)(x)) << USB_GUID_USERID_SHIFT)) & USB_GUID_USERID_MASK)
94705 /*! @} */
94706 
94707 /*! @name GUCTL - Global User Control Register */
94708 /*! @{ */
94709 
94710 #define USB_GUCTL_DTFT_MASK                      (0x1FFU)
94711 #define USB_GUCTL_DTFT_SHIFT                     (0U)
94712 #define USB_GUCTL_DTFT(x)                        (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_DTFT_SHIFT)) & USB_GUCTL_DTFT_MASK)
94713 
94714 #define USB_GUCTL_DTCT_MASK                      (0x600U)
94715 #define USB_GUCTL_DTCT_SHIFT                     (9U)
94716 #define USB_GUCTL_DTCT(x)                        (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_DTCT_SHIFT)) & USB_GUCTL_DTCT_MASK)
94717 
94718 #define USB_GUCTL_INSRTEXTRFSBODI_MASK           (0x800U)
94719 #define USB_GUCTL_INSRTEXTRFSBODI_SHIFT          (11U)
94720 #define USB_GUCTL_INSRTEXTRFSBODI(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_INSRTEXTRFSBODI_SHIFT)) & USB_GUCTL_INSRTEXTRFSBODI_MASK)
94721 
94722 #define USB_GUCTL_EXTCAPSUPPTEN_MASK             (0x1000U)
94723 #define USB_GUCTL_EXTCAPSUPPTEN_SHIFT            (12U)
94724 #define USB_GUCTL_EXTCAPSUPPTEN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_EXTCAPSUPPTEN_SHIFT)) & USB_GUCTL_EXTCAPSUPPTEN_MASK)
94725 
94726 #define USB_GUCTL_ENOVERLAPCHK_MASK              (0x2000U)
94727 #define USB_GUCTL_ENOVERLAPCHK_SHIFT             (13U)
94728 #define USB_GUCTL_ENOVERLAPCHK(x)                (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_ENOVERLAPCHK_SHIFT)) & USB_GUCTL_ENOVERLAPCHK_MASK)
94729 
94730 #define USB_GUCTL_USBHSTINAUTORETRYEN_MASK       (0x4000U)
94731 #define USB_GUCTL_USBHSTINAUTORETRYEN_SHIFT      (14U)
94732 #define USB_GUCTL_USBHSTINAUTORETRYEN(x)         (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_USBHSTINAUTORETRYEN_SHIFT)) & USB_GUCTL_USBHSTINAUTORETRYEN_MASK)
94733 
94734 #define USB_GUCTL_RESBWHSEPS_MASK                (0x10000U)
94735 #define USB_GUCTL_RESBWHSEPS_SHIFT               (16U)
94736 #define USB_GUCTL_RESBWHSEPS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_RESBWHSEPS_SHIFT)) & USB_GUCTL_RESBWHSEPS_MASK)
94737 
94738 #define USB_GUCTL_SPRSCTRLTRANSEN_MASK           (0x20000U)
94739 #define USB_GUCTL_SPRSCTRLTRANSEN_SHIFT          (17U)
94740 #define USB_GUCTL_SPRSCTRLTRANSEN(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_SPRSCTRLTRANSEN_SHIFT)) & USB_GUCTL_SPRSCTRLTRANSEN_MASK)
94741 
94742 #define USB_GUCTL_NOEXTRDL_MASK                  (0x200000U)
94743 #define USB_GUCTL_NOEXTRDL_SHIFT                 (21U)
94744 #define USB_GUCTL_NOEXTRDL(x)                    (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_NOEXTRDL_SHIFT)) & USB_GUCTL_NOEXTRDL_MASK)
94745 
94746 #define USB_GUCTL_REFCLKPER_MASK                 (0xFFC00000U)
94747 #define USB_GUCTL_REFCLKPER_SHIFT                (22U)
94748 #define USB_GUCTL_REFCLKPER(x)                   (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_REFCLKPER_SHIFT)) & USB_GUCTL_REFCLKPER_MASK)
94749 /*! @} */
94750 
94751 /*! @name GBUSERRADDRLO - Gobal SoC Bus Error Address Register - Low */
94752 /*! @{ */
94753 
94754 #define USB_GBUSERRADDRLO_BUSERRADDR_MASK        (0xFFFFFFFFU)
94755 #define USB_GBUSERRADDRLO_BUSERRADDR_SHIFT       (0U)
94756 #define USB_GBUSERRADDRLO_BUSERRADDR(x)          (((uint32_t)(((uint32_t)(x)) << USB_GBUSERRADDRLO_BUSERRADDR_SHIFT)) & USB_GBUSERRADDRLO_BUSERRADDR_MASK)
94757 /*! @} */
94758 
94759 /*! @name GBUSERRADDRHI - Gobal SoC Bus Error Address Register - High */
94760 /*! @{ */
94761 
94762 #define USB_GBUSERRADDRHI_BUSERRADDR_MASK        (0xFFFFFFFFU)
94763 #define USB_GBUSERRADDRHI_BUSERRADDR_SHIFT       (0U)
94764 #define USB_GBUSERRADDRHI_BUSERRADDR(x)          (((uint32_t)(((uint32_t)(x)) << USB_GBUSERRADDRHI_BUSERRADDR_SHIFT)) & USB_GBUSERRADDRHI_BUSERRADDR_MASK)
94765 /*! @} */
94766 
94767 /*! @name GPRTBIMAPLO - Global SS Port to Bus Instance Mapping Register - Low */
94768 /*! @{ */
94769 
94770 #define USB_GPRTBIMAPLO_BINUM1_MASK              (0xFU)
94771 #define USB_GPRTBIMAPLO_BINUM1_SHIFT             (0U)
94772 #define USB_GPRTBIMAPLO_BINUM1(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM1_SHIFT)) & USB_GPRTBIMAPLO_BINUM1_MASK)
94773 
94774 #define USB_GPRTBIMAPLO_BINUM2_MASK              (0xF0U)
94775 #define USB_GPRTBIMAPLO_BINUM2_SHIFT             (4U)
94776 #define USB_GPRTBIMAPLO_BINUM2(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM2_SHIFT)) & USB_GPRTBIMAPLO_BINUM2_MASK)
94777 
94778 #define USB_GPRTBIMAPLO_BINUM3_MASK              (0xF00U)
94779 #define USB_GPRTBIMAPLO_BINUM3_SHIFT             (8U)
94780 #define USB_GPRTBIMAPLO_BINUM3(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM3_SHIFT)) & USB_GPRTBIMAPLO_BINUM3_MASK)
94781 
94782 #define USB_GPRTBIMAPLO_BINUM4_MASK              (0xF000U)
94783 #define USB_GPRTBIMAPLO_BINUM4_SHIFT             (12U)
94784 #define USB_GPRTBIMAPLO_BINUM4(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM4_SHIFT)) & USB_GPRTBIMAPLO_BINUM4_MASK)
94785 
94786 #define USB_GPRTBIMAPLO_BINUM5_MASK              (0xF0000U)
94787 #define USB_GPRTBIMAPLO_BINUM5_SHIFT             (16U)
94788 #define USB_GPRTBIMAPLO_BINUM5(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM5_SHIFT)) & USB_GPRTBIMAPLO_BINUM5_MASK)
94789 
94790 #define USB_GPRTBIMAPLO_BINUM6_MASK              (0xF00000U)
94791 #define USB_GPRTBIMAPLO_BINUM6_SHIFT             (20U)
94792 #define USB_GPRTBIMAPLO_BINUM6(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM6_SHIFT)) & USB_GPRTBIMAPLO_BINUM6_MASK)
94793 
94794 #define USB_GPRTBIMAPLO_BINUM7_MASK              (0xF000000U)
94795 #define USB_GPRTBIMAPLO_BINUM7_SHIFT             (24U)
94796 #define USB_GPRTBIMAPLO_BINUM7(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM7_SHIFT)) & USB_GPRTBIMAPLO_BINUM7_MASK)
94797 
94798 #define USB_GPRTBIMAPLO_BINUM8_MASK              (0xF0000000U)
94799 #define USB_GPRTBIMAPLO_BINUM8_SHIFT             (28U)
94800 #define USB_GPRTBIMAPLO_BINUM8(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM8_SHIFT)) & USB_GPRTBIMAPLO_BINUM8_MASK)
94801 /*! @} */
94802 
94803 /*! @name GPRTBIMAPHI - Global SS Port to Bus Instance Mapping Register - High */
94804 /*! @{ */
94805 
94806 #define USB_GPRTBIMAPHI_BINUM9_MASK              (0xFU)
94807 #define USB_GPRTBIMAPHI_BINUM9_SHIFT             (0U)
94808 #define USB_GPRTBIMAPHI_BINUM9(x)                (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM9_SHIFT)) & USB_GPRTBIMAPHI_BINUM9_MASK)
94809 
94810 #define USB_GPRTBIMAPHI_BINUM10_MASK             (0xF0U)
94811 #define USB_GPRTBIMAPHI_BINUM10_SHIFT            (4U)
94812 #define USB_GPRTBIMAPHI_BINUM10(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM10_SHIFT)) & USB_GPRTBIMAPHI_BINUM10_MASK)
94813 
94814 #define USB_GPRTBIMAPHI_BINUM11_MASK             (0xF00U)
94815 #define USB_GPRTBIMAPHI_BINUM11_SHIFT            (8U)
94816 #define USB_GPRTBIMAPHI_BINUM11(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM11_SHIFT)) & USB_GPRTBIMAPHI_BINUM11_MASK)
94817 
94818 #define USB_GPRTBIMAPHI_BINUM12_MASK             (0xF000U)
94819 #define USB_GPRTBIMAPHI_BINUM12_SHIFT            (12U)
94820 #define USB_GPRTBIMAPHI_BINUM12(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM12_SHIFT)) & USB_GPRTBIMAPHI_BINUM12_MASK)
94821 
94822 #define USB_GPRTBIMAPHI_BINUM13_MASK             (0xF0000U)
94823 #define USB_GPRTBIMAPHI_BINUM13_SHIFT            (16U)
94824 #define USB_GPRTBIMAPHI_BINUM13(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM13_SHIFT)) & USB_GPRTBIMAPHI_BINUM13_MASK)
94825 
94826 #define USB_GPRTBIMAPHI_BINUM14_MASK             (0xF00000U)
94827 #define USB_GPRTBIMAPHI_BINUM14_SHIFT            (20U)
94828 #define USB_GPRTBIMAPHI_BINUM14(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM14_SHIFT)) & USB_GPRTBIMAPHI_BINUM14_MASK)
94829 
94830 #define USB_GPRTBIMAPHI_BINUM15_MASK             (0xF000000U)
94831 #define USB_GPRTBIMAPHI_BINUM15_SHIFT            (24U)
94832 #define USB_GPRTBIMAPHI_BINUM15(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM15_SHIFT)) & USB_GPRTBIMAPHI_BINUM15_MASK)
94833 /*! @} */
94834 
94835 /*! @name GHWPARAMS0 - Global Hardware Parameters Register 0 */
94836 /*! @{ */
94837 
94838 #define USB_GHWPARAMS0_GHWPARAMS0_2_0_MASK       (0x7U)
94839 #define USB_GHWPARAMS0_GHWPARAMS0_2_0_SHIFT      (0U)
94840 #define USB_GHWPARAMS0_GHWPARAMS0_2_0(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_2_0_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_2_0_MASK)
94841 
94842 #define USB_GHWPARAMS0_GHWPARAMS0_5_3_MASK       (0x38U)
94843 #define USB_GHWPARAMS0_GHWPARAMS0_5_3_SHIFT      (3U)
94844 #define USB_GHWPARAMS0_GHWPARAMS0_5_3(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_5_3_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_5_3_MASK)
94845 
94846 #define USB_GHWPARAMS0_GHWPARAMS0_7_6_MASK       (0xC0U)
94847 #define USB_GHWPARAMS0_GHWPARAMS0_7_6_SHIFT      (6U)
94848 #define USB_GHWPARAMS0_GHWPARAMS0_7_6(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_7_6_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_7_6_MASK)
94849 
94850 #define USB_GHWPARAMS0_GHWPARAMS0_15_8_MASK      (0xFF00U)
94851 #define USB_GHWPARAMS0_GHWPARAMS0_15_8_SHIFT     (8U)
94852 #define USB_GHWPARAMS0_GHWPARAMS0_15_8(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_15_8_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_15_8_MASK)
94853 
94854 #define USB_GHWPARAMS0_GHWPARAMS0_23_16_MASK     (0xFF0000U)
94855 #define USB_GHWPARAMS0_GHWPARAMS0_23_16_SHIFT    (16U)
94856 #define USB_GHWPARAMS0_GHWPARAMS0_23_16(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_23_16_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_23_16_MASK)
94857 
94858 #define USB_GHWPARAMS0_GHWPARAMS0_31_24_MASK     (0xFF000000U)
94859 #define USB_GHWPARAMS0_GHWPARAMS0_31_24_SHIFT    (24U)
94860 #define USB_GHWPARAMS0_GHWPARAMS0_31_24(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_31_24_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_31_24_MASK)
94861 /*! @} */
94862 
94863 /*! @name GHWPARAMS1 - Global Hardware Parameters Register 1 */
94864 /*! @{ */
94865 
94866 #define USB_GHWPARAMS1_GHWPARAMS1_2_0_MASK       (0x7U)
94867 #define USB_GHWPARAMS1_GHWPARAMS1_2_0_SHIFT      (0U)
94868 #define USB_GHWPARAMS1_GHWPARAMS1_2_0(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_2_0_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_2_0_MASK)
94869 
94870 #define USB_GHWPARAMS1_GHWPARAMS1_5_3_MASK       (0x38U)
94871 #define USB_GHWPARAMS1_GHWPARAMS1_5_3_SHIFT      (3U)
94872 #define USB_GHWPARAMS1_GHWPARAMS1_5_3(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_5_3_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_5_3_MASK)
94873 
94874 #define USB_GHWPARAMS1_GHWPARAMS1_8_6_MASK       (0x1C0U)
94875 #define USB_GHWPARAMS1_GHWPARAMS1_8_6_SHIFT      (6U)
94876 #define USB_GHWPARAMS1_GHWPARAMS1_8_6(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_8_6_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_8_6_MASK)
94877 
94878 #define USB_GHWPARAMS1_GHWPARAMS1_11_9_MASK      (0xE00U)
94879 #define USB_GHWPARAMS1_GHWPARAMS1_11_9_SHIFT     (9U)
94880 #define USB_GHWPARAMS1_GHWPARAMS1_11_9(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_11_9_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_11_9_MASK)
94881 
94882 #define USB_GHWPARAMS1_GHWPARAMS1_14_12_MASK     (0x7000U)
94883 #define USB_GHWPARAMS1_GHWPARAMS1_14_12_SHIFT    (12U)
94884 #define USB_GHWPARAMS1_GHWPARAMS1_14_12(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_14_12_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_14_12_MASK)
94885 
94886 #define USB_GHWPARAMS1_GHWPARAMS1_20_15_MASK     (0x1F8000U)
94887 #define USB_GHWPARAMS1_GHWPARAMS1_20_15_SHIFT    (15U)
94888 #define USB_GHWPARAMS1_GHWPARAMS1_20_15(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_20_15_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_20_15_MASK)
94889 
94890 #define USB_GHWPARAMS1_GHWPARAMS1_22_21_MASK     (0x600000U)
94891 #define USB_GHWPARAMS1_GHWPARAMS1_22_21_SHIFT    (21U)
94892 #define USB_GHWPARAMS1_GHWPARAMS1_22_21(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_22_21_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_22_21_MASK)
94893 
94894 #define USB_GHWPARAMS1_GHWPARAMS1_23_MASK        (0x800000U)
94895 #define USB_GHWPARAMS1_GHWPARAMS1_23_SHIFT       (23U)
94896 #define USB_GHWPARAMS1_GHWPARAMS1_23(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_23_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_23_MASK)
94897 
94898 #define USB_GHWPARAMS1_GHWPARAMS1_25_24_MASK     (0x3000000U)
94899 #define USB_GHWPARAMS1_GHWPARAMS1_25_24_SHIFT    (24U)
94900 #define USB_GHWPARAMS1_GHWPARAMS1_25_24(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_25_24_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_25_24_MASK)
94901 
94902 #define USB_GHWPARAMS1_GHWPARAMS1_26_MASK        (0x4000000U)
94903 #define USB_GHWPARAMS1_GHWPARAMS1_26_SHIFT       (26U)
94904 #define USB_GHWPARAMS1_GHWPARAMS1_26(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_26_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_26_MASK)
94905 
94906 #define USB_GHWPARAMS1_GHWPARAMS1_27_MASK        (0x8000000U)
94907 #define USB_GHWPARAMS1_GHWPARAMS1_27_SHIFT       (27U)
94908 #define USB_GHWPARAMS1_GHWPARAMS1_27(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_27_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_27_MASK)
94909 
94910 #define USB_GHWPARAMS1_GHWPARAMS1_28_MASK        (0x10000000U)
94911 #define USB_GHWPARAMS1_GHWPARAMS1_28_SHIFT       (28U)
94912 #define USB_GHWPARAMS1_GHWPARAMS1_28(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_28_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_28_MASK)
94913 
94914 #define USB_GHWPARAMS1_GHWPARAMS1_30_MASK        (0x40000000U)
94915 #define USB_GHWPARAMS1_GHWPARAMS1_30_SHIFT       (30U)
94916 #define USB_GHWPARAMS1_GHWPARAMS1_30(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_30_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_30_MASK)
94917 
94918 #define USB_GHWPARAMS1_GHWPARAMS1_31_MASK        (0x80000000U)
94919 #define USB_GHWPARAMS1_GHWPARAMS1_31_SHIFT       (31U)
94920 #define USB_GHWPARAMS1_GHWPARAMS1_31(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_31_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_31_MASK)
94921 /*! @} */
94922 
94923 /*! @name GHWPARAMS2 - Global Hardware Parameters Register 2 */
94924 /*! @{ */
94925 
94926 #define USB_GHWPARAMS2_GHWPARAMS2_31_0_MASK      (0xFFFFFFFFU)
94927 #define USB_GHWPARAMS2_GHWPARAMS2_31_0_SHIFT     (0U)
94928 #define USB_GHWPARAMS2_GHWPARAMS2_31_0(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS2_GHWPARAMS2_31_0_SHIFT)) & USB_GHWPARAMS2_GHWPARAMS2_31_0_MASK)
94929 /*! @} */
94930 
94931 /*! @name GHWPARAMS3 - Global Hardware Parameters Register 3 */
94932 /*! @{ */
94933 
94934 #define USB_GHWPARAMS3_GHWPARAMS3_1_0_MASK       (0x3U)
94935 #define USB_GHWPARAMS3_GHWPARAMS3_1_0_SHIFT      (0U)
94936 #define USB_GHWPARAMS3_GHWPARAMS3_1_0(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_1_0_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_1_0_MASK)
94937 
94938 #define USB_GHWPARAMS3_GHWPARAMS3_3_2_MASK       (0xCU)
94939 #define USB_GHWPARAMS3_GHWPARAMS3_3_2_SHIFT      (2U)
94940 #define USB_GHWPARAMS3_GHWPARAMS3_3_2(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_3_2_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_3_2_MASK)
94941 
94942 #define USB_GHWPARAMS3_GHWPARAMS3_5_4_MASK       (0x30U)
94943 #define USB_GHWPARAMS3_GHWPARAMS3_5_4_SHIFT      (4U)
94944 #define USB_GHWPARAMS3_GHWPARAMS3_5_4(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_5_4_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_5_4_MASK)
94945 
94946 #define USB_GHWPARAMS3_GHWPARAMS3_7_6_MASK       (0xC0U)
94947 #define USB_GHWPARAMS3_GHWPARAMS3_7_6_SHIFT      (6U)
94948 #define USB_GHWPARAMS3_GHWPARAMS3_7_6(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_7_6_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_7_6_MASK)
94949 
94950 #define USB_GHWPARAMS3_GHWPARAMS3_10_MASK        (0x400U)
94951 #define USB_GHWPARAMS3_GHWPARAMS3_10_SHIFT       (10U)
94952 #define USB_GHWPARAMS3_GHWPARAMS3_10(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_10_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_10_MASK)
94953 
94954 #define USB_GHWPARAMS3_GHWPARAMS3_11_MASK        (0x800U)
94955 #define USB_GHWPARAMS3_GHWPARAMS3_11_SHIFT       (11U)
94956 #define USB_GHWPARAMS3_GHWPARAMS3_11(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_11_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_11_MASK)
94957 
94958 #define USB_GHWPARAMS3_GHWPARAMS3_17_12_MASK     (0x3F000U)
94959 #define USB_GHWPARAMS3_GHWPARAMS3_17_12_SHIFT    (12U)
94960 #define USB_GHWPARAMS3_GHWPARAMS3_17_12(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_17_12_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_17_12_MASK)
94961 
94962 #define USB_GHWPARAMS3_GHWPARAMS3_22_18_MASK     (0x7C0000U)
94963 #define USB_GHWPARAMS3_GHWPARAMS3_22_18_SHIFT    (18U)
94964 #define USB_GHWPARAMS3_GHWPARAMS3_22_18(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_22_18_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_22_18_MASK)
94965 
94966 #define USB_GHWPARAMS3_GHWPARAMS3_30_23_MASK     (0x7F800000U)
94967 #define USB_GHWPARAMS3_GHWPARAMS3_30_23_SHIFT    (23U)
94968 #define USB_GHWPARAMS3_GHWPARAMS3_30_23(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_30_23_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_30_23_MASK)
94969 /*! @} */
94970 
94971 /*! @name GHWPARAMS4 - Global Hardware Parameters Register 4 */
94972 /*! @{ */
94973 
94974 #define USB_GHWPARAMS4_GHWPARAMS4_5_0_MASK       (0x3FU)
94975 #define USB_GHWPARAMS4_GHWPARAMS4_5_0_SHIFT      (0U)
94976 #define USB_GHWPARAMS4_GHWPARAMS4_5_0(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_5_0_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_5_0_MASK)
94977 
94978 #define USB_GHWPARAMS4_GHWPARAMS4_8_7_MASK       (0x180U)
94979 #define USB_GHWPARAMS4_GHWPARAMS4_8_7_SHIFT      (7U)
94980 #define USB_GHWPARAMS4_GHWPARAMS4_8_7(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_8_7_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_8_7_MASK)
94981 
94982 #define USB_GHWPARAMS4_GHWPARAMS4_10_9_MASK      (0x600U)
94983 #define USB_GHWPARAMS4_GHWPARAMS4_10_9_SHIFT     (9U)
94984 #define USB_GHWPARAMS4_GHWPARAMS4_10_9(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_10_9_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_10_9_MASK)
94985 
94986 #define USB_GHWPARAMS4_GHWPARAMS4_11_MASK        (0x800U)
94987 #define USB_GHWPARAMS4_GHWPARAMS4_11_SHIFT       (11U)
94988 #define USB_GHWPARAMS4_GHWPARAMS4_11(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_11_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_11_MASK)
94989 
94990 #define USB_GHWPARAMS4_GHWPARAMS4_12_MASK        (0x1000U)
94991 #define USB_GHWPARAMS4_GHWPARAMS4_12_SHIFT       (12U)
94992 #define USB_GHWPARAMS4_GHWPARAMS4_12(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_12_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_12_MASK)
94993 
94994 #define USB_GHWPARAMS4_GHWPARAMS4_16_13_MASK     (0x1E000U)
94995 #define USB_GHWPARAMS4_GHWPARAMS4_16_13_SHIFT    (13U)
94996 #define USB_GHWPARAMS4_GHWPARAMS4_16_13(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_16_13_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_16_13_MASK)
94997 
94998 #define USB_GHWPARAMS4_GHWPARAMS4_20_17_MASK     (0x1E0000U)
94999 #define USB_GHWPARAMS4_GHWPARAMS4_20_17_SHIFT    (17U)
95000 #define USB_GHWPARAMS4_GHWPARAMS4_20_17(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_20_17_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_20_17_MASK)
95001 
95002 #define USB_GHWPARAMS4_GHWPARAMS4_21_MASK        (0x200000U)
95003 #define USB_GHWPARAMS4_GHWPARAMS4_21_SHIFT       (21U)
95004 #define USB_GHWPARAMS4_GHWPARAMS4_21(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_21_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_21_MASK)
95005 
95006 #define USB_GHWPARAMS4_GHWPARAMS4_23_MASK        (0x800000U)
95007 #define USB_GHWPARAMS4_GHWPARAMS4_23_SHIFT       (23U)
95008 #define USB_GHWPARAMS4_GHWPARAMS4_23(x)          (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_23_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_23_MASK)
95009 
95010 #define USB_GHWPARAMS4_GHWPARAMS4_27_24_MASK     (0xF000000U)
95011 #define USB_GHWPARAMS4_GHWPARAMS4_27_24_SHIFT    (24U)
95012 #define USB_GHWPARAMS4_GHWPARAMS4_27_24(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_27_24_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_27_24_MASK)
95013 
95014 #define USB_GHWPARAMS4_GHWPARAMS4_31_28_MASK     (0xF0000000U)
95015 #define USB_GHWPARAMS4_GHWPARAMS4_31_28_SHIFT    (28U)
95016 #define USB_GHWPARAMS4_GHWPARAMS4_31_28(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_31_28_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_31_28_MASK)
95017 /*! @} */
95018 
95019 /*! @name GHWPARAMS5 - Global Hardware Parameters Register 5 */
95020 /*! @{ */
95021 
95022 #define USB_GHWPARAMS5_GHWPARAMS5_3_0_MASK       (0xFU)
95023 #define USB_GHWPARAMS5_GHWPARAMS5_3_0_SHIFT      (0U)
95024 #define USB_GHWPARAMS5_GHWPARAMS5_3_0(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_3_0_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_3_0_MASK)
95025 
95026 #define USB_GHWPARAMS5_GHWPARAMS5_9_4_MASK       (0x3F0U)
95027 #define USB_GHWPARAMS5_GHWPARAMS5_9_4_SHIFT      (4U)
95028 #define USB_GHWPARAMS5_GHWPARAMS5_9_4(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_9_4_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_9_4_MASK)
95029 
95030 #define USB_GHWPARAMS5_GHWPARAMS5_15_10_MASK     (0xFC00U)
95031 #define USB_GHWPARAMS5_GHWPARAMS5_15_10_SHIFT    (10U)
95032 #define USB_GHWPARAMS5_GHWPARAMS5_15_10(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_15_10_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_15_10_MASK)
95033 
95034 #define USB_GHWPARAMS5_GHWPARAMS5_21_16_MASK     (0x3F0000U)
95035 #define USB_GHWPARAMS5_GHWPARAMS5_21_16_SHIFT    (16U)
95036 #define USB_GHWPARAMS5_GHWPARAMS5_21_16(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_21_16_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_21_16_MASK)
95037 
95038 #define USB_GHWPARAMS5_GHWPARAMS5_27_22_MASK     (0xFC00000U)
95039 #define USB_GHWPARAMS5_GHWPARAMS5_27_22_SHIFT    (22U)
95040 #define USB_GHWPARAMS5_GHWPARAMS5_27_22(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_27_22_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_27_22_MASK)
95041 /*! @} */
95042 
95043 /*! @name GHWPARAMS6 - Global Hardware Parameters Register 6 */
95044 /*! @{ */
95045 
95046 #define USB_GHWPARAMS6_GHWPARAMS6_5_0_MASK       (0x3FU)
95047 #define USB_GHWPARAMS6_GHWPARAMS6_5_0_SHIFT      (0U)
95048 #define USB_GHWPARAMS6_GHWPARAMS6_5_0(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_5_0_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_5_0_MASK)
95049 
95050 #define USB_GHWPARAMS6_GHWPARAMS6_6_MASK         (0x40U)
95051 #define USB_GHWPARAMS6_GHWPARAMS6_6_SHIFT        (6U)
95052 #define USB_GHWPARAMS6_GHWPARAMS6_6(x)           (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_6_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_6_MASK)
95053 
95054 #define USB_GHWPARAMS6_GHWPARAMS6_7_MASK         (0x80U)
95055 #define USB_GHWPARAMS6_GHWPARAMS6_7_SHIFT        (7U)
95056 #define USB_GHWPARAMS6_GHWPARAMS6_7(x)           (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_7_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_7_MASK)
95057 
95058 #define USB_GHWPARAMS6_GHWPARAMS6_9_8_MASK       (0x300U)
95059 #define USB_GHWPARAMS6_GHWPARAMS6_9_8_SHIFT      (8U)
95060 #define USB_GHWPARAMS6_GHWPARAMS6_9_8(x)         (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_9_8_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_9_8_MASK)
95061 
95062 #define USB_GHWPARAMS6_BCSUPPORT_MASK            (0x4000U)
95063 #define USB_GHWPARAMS6_BCSUPPORT_SHIFT           (14U)
95064 #define USB_GHWPARAMS6_BCSUPPORT(x)              (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_BCSUPPORT_SHIFT)) & USB_GHWPARAMS6_BCSUPPORT_MASK)
95065 
95066 #define USB_GHWPARAMS6_BUSFLTRSSUPPORT_MASK      (0x8000U)
95067 #define USB_GHWPARAMS6_BUSFLTRSSUPPORT_SHIFT     (15U)
95068 #define USB_GHWPARAMS6_BUSFLTRSSUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_BUSFLTRSSUPPORT_SHIFT)) & USB_GHWPARAMS6_BUSFLTRSSUPPORT_MASK)
95069 
95070 #define USB_GHWPARAMS6_GHWPARAMS6_31_16_MASK     (0xFFFF0000U)
95071 #define USB_GHWPARAMS6_GHWPARAMS6_31_16_SHIFT    (16U)
95072 #define USB_GHWPARAMS6_GHWPARAMS6_31_16(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_31_16_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_31_16_MASK)
95073 /*! @} */
95074 
95075 /*! @name GHWPARAMS7 - Global Hardware Parameters Register 7 */
95076 /*! @{ */
95077 
95078 #define USB_GHWPARAMS7_GHWPARAMS7_15_0_MASK      (0xFFFFU)
95079 #define USB_GHWPARAMS7_GHWPARAMS7_15_0_SHIFT     (0U)
95080 #define USB_GHWPARAMS7_GHWPARAMS7_15_0(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS7_GHWPARAMS7_15_0_SHIFT)) & USB_GHWPARAMS7_GHWPARAMS7_15_0_MASK)
95081 
95082 #define USB_GHWPARAMS7_GHWPARAMS7_31_16_MASK     (0xFFFF0000U)
95083 #define USB_GHWPARAMS7_GHWPARAMS7_31_16_SHIFT    (16U)
95084 #define USB_GHWPARAMS7_GHWPARAMS7_31_16(x)       (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS7_GHWPARAMS7_31_16_SHIFT)) & USB_GHWPARAMS7_GHWPARAMS7_31_16_MASK)
95085 /*! @} */
95086 
95087 /*! @name GPRTBIMAP_HSLO - Global High-Speed Port to Bus Instance Mapping Register - Low */
95088 /*! @{ */
95089 
95090 #define USB_GPRTBIMAP_HSLO_BINUM1_MASK           (0xFU)
95091 #define USB_GPRTBIMAP_HSLO_BINUM1_SHIFT          (0U)
95092 #define USB_GPRTBIMAP_HSLO_BINUM1(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM1_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM1_MASK)
95093 
95094 #define USB_GPRTBIMAP_HSLO_BINUM2_MASK           (0xF0U)
95095 #define USB_GPRTBIMAP_HSLO_BINUM2_SHIFT          (4U)
95096 #define USB_GPRTBIMAP_HSLO_BINUM2(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM2_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM2_MASK)
95097 
95098 #define USB_GPRTBIMAP_HSLO_BINUM3_MASK           (0xF00U)
95099 #define USB_GPRTBIMAP_HSLO_BINUM3_SHIFT          (8U)
95100 #define USB_GPRTBIMAP_HSLO_BINUM3(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM3_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM3_MASK)
95101 
95102 #define USB_GPRTBIMAP_HSLO_BINUM4_MASK           (0xF000U)
95103 #define USB_GPRTBIMAP_HSLO_BINUM4_SHIFT          (12U)
95104 #define USB_GPRTBIMAP_HSLO_BINUM4(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM4_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM4_MASK)
95105 
95106 #define USB_GPRTBIMAP_HSLO_BINUM5_MASK           (0xF0000U)
95107 #define USB_GPRTBIMAP_HSLO_BINUM5_SHIFT          (16U)
95108 #define USB_GPRTBIMAP_HSLO_BINUM5(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM5_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM5_MASK)
95109 
95110 #define USB_GPRTBIMAP_HSLO_BINUM6_MASK           (0xF00000U)
95111 #define USB_GPRTBIMAP_HSLO_BINUM6_SHIFT          (20U)
95112 #define USB_GPRTBIMAP_HSLO_BINUM6(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM6_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM6_MASK)
95113 
95114 #define USB_GPRTBIMAP_HSLO_BINUM7_MASK           (0xF000000U)
95115 #define USB_GPRTBIMAP_HSLO_BINUM7_SHIFT          (24U)
95116 #define USB_GPRTBIMAP_HSLO_BINUM7(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM7_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM7_MASK)
95117 
95118 #define USB_GPRTBIMAP_HSLO_BINUM8_MASK           (0xF0000000U)
95119 #define USB_GPRTBIMAP_HSLO_BINUM8_SHIFT          (28U)
95120 #define USB_GPRTBIMAP_HSLO_BINUM8(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM8_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM8_MASK)
95121 /*! @} */
95122 
95123 /*! @name GPRTBIMAP_HSHI - Global High-Speed Port to Bus Instance Mapping Register - High */
95124 /*! @{ */
95125 
95126 #define USB_GPRTBIMAP_HSHI_BINUM9_MASK           (0xFU)
95127 #define USB_GPRTBIMAP_HSHI_BINUM9_SHIFT          (0U)
95128 #define USB_GPRTBIMAP_HSHI_BINUM9(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM9_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM9_MASK)
95129 
95130 #define USB_GPRTBIMAP_HSHI_BINUM10_MASK          (0xF0U)
95131 #define USB_GPRTBIMAP_HSHI_BINUM10_SHIFT         (4U)
95132 #define USB_GPRTBIMAP_HSHI_BINUM10(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM10_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM10_MASK)
95133 
95134 #define USB_GPRTBIMAP_HSHI_BINUM11_MASK          (0xF00U)
95135 #define USB_GPRTBIMAP_HSHI_BINUM11_SHIFT         (8U)
95136 #define USB_GPRTBIMAP_HSHI_BINUM11(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM11_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM11_MASK)
95137 
95138 #define USB_GPRTBIMAP_HSHI_BINUM12_MASK          (0xF000U)
95139 #define USB_GPRTBIMAP_HSHI_BINUM12_SHIFT         (12U)
95140 #define USB_GPRTBIMAP_HSHI_BINUM12(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM12_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM12_MASK)
95141 
95142 #define USB_GPRTBIMAP_HSHI_BINUM13_MASK          (0xF0000U)
95143 #define USB_GPRTBIMAP_HSHI_BINUM13_SHIFT         (16U)
95144 #define USB_GPRTBIMAP_HSHI_BINUM13(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM13_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM13_MASK)
95145 
95146 #define USB_GPRTBIMAP_HSHI_BINUM14_MASK          (0xF00000U)
95147 #define USB_GPRTBIMAP_HSHI_BINUM14_SHIFT         (20U)
95148 #define USB_GPRTBIMAP_HSHI_BINUM14(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM14_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM14_MASK)
95149 
95150 #define USB_GPRTBIMAP_HSHI_BINUM15_MASK          (0xF000000U)
95151 #define USB_GPRTBIMAP_HSHI_BINUM15_SHIFT         (24U)
95152 #define USB_GPRTBIMAP_HSHI_BINUM15(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM15_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM15_MASK)
95153 /*! @} */
95154 
95155 /*! @name GPRTBIMAP_FSLO - Global Full-Speed Port to Bus Instance Mapping Register - Low */
95156 /*! @{ */
95157 
95158 #define USB_GPRTBIMAP_FSLO_BINUM1_MASK           (0xFU)
95159 #define USB_GPRTBIMAP_FSLO_BINUM1_SHIFT          (0U)
95160 #define USB_GPRTBIMAP_FSLO_BINUM1(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM1_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM1_MASK)
95161 
95162 #define USB_GPRTBIMAP_FSLO_BINUM2_MASK           (0xF0U)
95163 #define USB_GPRTBIMAP_FSLO_BINUM2_SHIFT          (4U)
95164 #define USB_GPRTBIMAP_FSLO_BINUM2(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM2_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM2_MASK)
95165 
95166 #define USB_GPRTBIMAP_FSLO_BINUM3_MASK           (0xF00U)
95167 #define USB_GPRTBIMAP_FSLO_BINUM3_SHIFT          (8U)
95168 #define USB_GPRTBIMAP_FSLO_BINUM3(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM3_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM3_MASK)
95169 
95170 #define USB_GPRTBIMAP_FSLO_BINUM4_MASK           (0xF000U)
95171 #define USB_GPRTBIMAP_FSLO_BINUM4_SHIFT          (12U)
95172 #define USB_GPRTBIMAP_FSLO_BINUM4(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM4_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM4_MASK)
95173 
95174 #define USB_GPRTBIMAP_FSLO_BINUM5_MASK           (0xF0000U)
95175 #define USB_GPRTBIMAP_FSLO_BINUM5_SHIFT          (16U)
95176 #define USB_GPRTBIMAP_FSLO_BINUM5(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM5_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM5_MASK)
95177 
95178 #define USB_GPRTBIMAP_FSLO_BINUM6_MASK           (0xF00000U)
95179 #define USB_GPRTBIMAP_FSLO_BINUM6_SHIFT          (20U)
95180 #define USB_GPRTBIMAP_FSLO_BINUM6(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM6_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM6_MASK)
95181 
95182 #define USB_GPRTBIMAP_FSLO_BINUM7_MASK           (0xF000000U)
95183 #define USB_GPRTBIMAP_FSLO_BINUM7_SHIFT          (24U)
95184 #define USB_GPRTBIMAP_FSLO_BINUM7(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM7_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM7_MASK)
95185 
95186 #define USB_GPRTBIMAP_FSLO_BINUM8_MASK           (0xF0000000U)
95187 #define USB_GPRTBIMAP_FSLO_BINUM8_SHIFT          (28U)
95188 #define USB_GPRTBIMAP_FSLO_BINUM8(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM8_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM8_MASK)
95189 /*! @} */
95190 
95191 /*! @name GPRTBIMAP_FSHI - Global Full-Speed Port to Bus Instance Mapping Register - High */
95192 /*! @{ */
95193 
95194 #define USB_GPRTBIMAP_FSHI_BINUM9_MASK           (0xFU)
95195 #define USB_GPRTBIMAP_FSHI_BINUM9_SHIFT          (0U)
95196 #define USB_GPRTBIMAP_FSHI_BINUM9(x)             (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM9_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM9_MASK)
95197 
95198 #define USB_GPRTBIMAP_FSHI_BINUM10_MASK          (0xF0U)
95199 #define USB_GPRTBIMAP_FSHI_BINUM10_SHIFT         (4U)
95200 #define USB_GPRTBIMAP_FSHI_BINUM10(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM10_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM10_MASK)
95201 
95202 #define USB_GPRTBIMAP_FSHI_BINUM11_MASK          (0xF00U)
95203 #define USB_GPRTBIMAP_FSHI_BINUM11_SHIFT         (8U)
95204 #define USB_GPRTBIMAP_FSHI_BINUM11(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM11_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM11_MASK)
95205 
95206 #define USB_GPRTBIMAP_FSHI_BINUM12_MASK          (0xF000U)
95207 #define USB_GPRTBIMAP_FSHI_BINUM12_SHIFT         (12U)
95208 #define USB_GPRTBIMAP_FSHI_BINUM12(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM12_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM12_MASK)
95209 
95210 #define USB_GPRTBIMAP_FSHI_BINUM13_MASK          (0xF0000U)
95211 #define USB_GPRTBIMAP_FSHI_BINUM13_SHIFT         (16U)
95212 #define USB_GPRTBIMAP_FSHI_BINUM13(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM13_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM13_MASK)
95213 
95214 #define USB_GPRTBIMAP_FSHI_BINUM14_MASK          (0xF00000U)
95215 #define USB_GPRTBIMAP_FSHI_BINUM14_SHIFT         (20U)
95216 #define USB_GPRTBIMAP_FSHI_BINUM14(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM14_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM14_MASK)
95217 
95218 #define USB_GPRTBIMAP_FSHI_BINUM15_MASK          (0xF000000U)
95219 #define USB_GPRTBIMAP_FSHI_BINUM15_SHIFT         (24U)
95220 #define USB_GPRTBIMAP_FSHI_BINUM15(x)            (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM15_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM15_MASK)
95221 /*! @} */
95222 
95223 /*! @name GUCTL2 - Global User Control Register 2 */
95224 /*! @{ */
95225 
95226 #define USB_GUCTL2_TXPINGDURATION_MASK           (0x1FU)
95227 #define USB_GUCTL2_TXPINGDURATION_SHIFT          (0U)
95228 #define USB_GUCTL2_TXPINGDURATION(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_TXPINGDURATION_SHIFT)) & USB_GUCTL2_TXPINGDURATION_MASK)
95229 
95230 #define USB_GUCTL2_RXPINGDURATION_MASK           (0x7E0U)
95231 #define USB_GUCTL2_RXPINGDURATION_SHIFT          (5U)
95232 #define USB_GUCTL2_RXPINGDURATION(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_RXPINGDURATION_SHIFT)) & USB_GUCTL2_RXPINGDURATION_MASK)
95233 
95234 #define USB_GUCTL2_DISABLECFC_MASK               (0x800U)
95235 #define USB_GUCTL2_DISABLECFC_SHIFT              (11U)
95236 #define USB_GUCTL2_DISABLECFC(x)                 (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_DISABLECFC_SHIFT)) & USB_GUCTL2_DISABLECFC_MASK)
95237 
95238 #define USB_GUCTL2_ENABLEEPCACHEEVICT_MASK       (0x1000U)
95239 #define USB_GUCTL2_ENABLEEPCACHEEVICT_SHIFT      (12U)
95240 #define USB_GUCTL2_ENABLEEPCACHEEVICT(x)         (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_ENABLEEPCACHEEVICT_SHIFT)) & USB_GUCTL2_ENABLEEPCACHEEVICT_MASK)
95241 
95242 #define USB_GUCTL2_RST_ACTBITLATER_MASK          (0x4000U)
95243 #define USB_GUCTL2_RST_ACTBITLATER_SHIFT         (14U)
95244 #define USB_GUCTL2_RST_ACTBITLATER(x)            (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_RST_ACTBITLATER_SHIFT)) & USB_GUCTL2_RST_ACTBITLATER_MASK)
95245 
95246 #define USB_GUCTL2_NOLOWPWRDUR_MASK              (0x78000U)
95247 #define USB_GUCTL2_NOLOWPWRDUR_SHIFT             (15U)
95248 #define USB_GUCTL2_NOLOWPWRDUR(x)                (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_NOLOWPWRDUR_SHIFT)) & USB_GUCTL2_NOLOWPWRDUR_MASK)
95249 
95250 #define USB_GUCTL2_EN_HP_PM_TIMER_MASK           (0x3F80000U)
95251 #define USB_GUCTL2_EN_HP_PM_TIMER_SHIFT          (19U)
95252 #define USB_GUCTL2_EN_HP_PM_TIMER(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_EN_HP_PM_TIMER_SHIFT)) & USB_GUCTL2_EN_HP_PM_TIMER_MASK)
95253 /*! @} */
95254 
95255 /*! @name GUSB2PHYCFG - Global USB2 PHY Configuration Register */
95256 /*! @{ */
95257 
95258 #define USB_GUSB2PHYCFG_TOUTCAL_MASK             (0x7U)
95259 #define USB_GUSB2PHYCFG_TOUTCAL_SHIFT            (0U)
95260 #define USB_GUSB2PHYCFG_TOUTCAL(x)               (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_TOUTCAL_SHIFT)) & USB_GUSB2PHYCFG_TOUTCAL_MASK)
95261 
95262 #define USB_GUSB2PHYCFG_PHYIF_MASK               (0x8U)
95263 #define USB_GUSB2PHYCFG_PHYIF_SHIFT              (3U)
95264 #define USB_GUSB2PHYCFG_PHYIF(x)                 (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_PHYIF_SHIFT)) & USB_GUSB2PHYCFG_PHYIF_MASK)
95265 
95266 #define USB_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK       (0x10U)
95267 #define USB_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT      (4U)
95268 #define USB_GUSB2PHYCFG_ULPI_UTMI_SEL(x)         (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT)) & USB_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK)
95269 
95270 #define USB_GUSB2PHYCFG_FSINTF_MASK              (0x20U)
95271 #define USB_GUSB2PHYCFG_FSINTF_SHIFT             (5U)
95272 #define USB_GUSB2PHYCFG_FSINTF(x)                (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_FSINTF_SHIFT)) & USB_GUSB2PHYCFG_FSINTF_MASK)
95273 
95274 #define USB_GUSB2PHYCFG_SUSPENDUSB20_MASK        (0x40U)
95275 #define USB_GUSB2PHYCFG_SUSPENDUSB20_SHIFT       (6U)
95276 #define USB_GUSB2PHYCFG_SUSPENDUSB20(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_SUSPENDUSB20_SHIFT)) & USB_GUSB2PHYCFG_SUSPENDUSB20_MASK)
95277 
95278 #define USB_GUSB2PHYCFG_PHYSEL_MASK              (0x80U)
95279 #define USB_GUSB2PHYCFG_PHYSEL_SHIFT             (7U)
95280 #define USB_GUSB2PHYCFG_PHYSEL(x)                (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_PHYSEL_SHIFT)) & USB_GUSB2PHYCFG_PHYSEL_MASK)
95281 
95282 #define USB_GUSB2PHYCFG_ENBLSLPM_MASK            (0x100U)
95283 #define USB_GUSB2PHYCFG_ENBLSLPM_SHIFT           (8U)
95284 #define USB_GUSB2PHYCFG_ENBLSLPM(x)              (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ENBLSLPM_SHIFT)) & USB_GUSB2PHYCFG_ENBLSLPM_MASK)
95285 
95286 #define USB_GUSB2PHYCFG_XCVRDLY_MASK             (0x200U)
95287 #define USB_GUSB2PHYCFG_XCVRDLY_SHIFT            (9U)
95288 #define USB_GUSB2PHYCFG_XCVRDLY(x)               (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_XCVRDLY_SHIFT)) & USB_GUSB2PHYCFG_XCVRDLY_MASK)
95289 
95290 #define USB_GUSB2PHYCFG_USBTRDTIM_MASK           (0x3C00U)
95291 #define USB_GUSB2PHYCFG_USBTRDTIM_SHIFT          (10U)
95292 #define USB_GUSB2PHYCFG_USBTRDTIM(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_USBTRDTIM_SHIFT)) & USB_GUSB2PHYCFG_USBTRDTIM_MASK)
95293 
95294 #define USB_GUSB2PHYCFG_ULPIAUTORES_MASK         (0x8000U)
95295 #define USB_GUSB2PHYCFG_ULPIAUTORES_SHIFT        (15U)
95296 #define USB_GUSB2PHYCFG_ULPIAUTORES(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPIAUTORES_SHIFT)) & USB_GUSB2PHYCFG_ULPIAUTORES_MASK)
95297 
95298 #define USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK      (0x20000U)
95299 #define USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT     (17U)
95300 #define USB_GUSB2PHYCFG_ULPIEXTVBUSDRV(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT)) & USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK)
95301 
95302 #define USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_MASK (0x40000U)
95303 #define USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHIFT (18U)
95304 #define USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR(x)  (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHIFT)) & USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_MASK)
95305 
95306 #define USB_GUSB2PHYCFG_LSIPD_MASK               (0x380000U)
95307 #define USB_GUSB2PHYCFG_LSIPD_SHIFT              (19U)
95308 #define USB_GUSB2PHYCFG_LSIPD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_LSIPD_SHIFT)) & USB_GUSB2PHYCFG_LSIPD_MASK)
95309 
95310 #define USB_GUSB2PHYCFG_LSTRD_MASK               (0x1C00000U)
95311 #define USB_GUSB2PHYCFG_LSTRD_SHIFT              (22U)
95312 #define USB_GUSB2PHYCFG_LSTRD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_LSTRD_SHIFT)) & USB_GUSB2PHYCFG_LSTRD_MASK)
95313 
95314 #define USB_GUSB2PHYCFG_INV_SEL_HSIC_MASK        (0x4000000U)
95315 #define USB_GUSB2PHYCFG_INV_SEL_HSIC_SHIFT       (26U)
95316 #define USB_GUSB2PHYCFG_INV_SEL_HSIC(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_INV_SEL_HSIC_SHIFT)) & USB_GUSB2PHYCFG_INV_SEL_HSIC_MASK)
95317 
95318 #define USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK  (0x18000000U)
95319 #define USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_SHIFT (27U)
95320 #define USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ(x)    (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_SHIFT)) & USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK)
95321 
95322 #define USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_MASK (0x20000000U)
95323 #define USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_SHIFT (29U)
95324 #define USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_SHIFT)) & USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_MASK)
95325 
95326 #define USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_MASK   (0x40000000U)
95327 #define USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_SHIFT  (30U)
95328 #define USB_GUSB2PHYCFG_U2_FREECLK_EXISTS(x)     (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_SHIFT)) & USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_MASK)
95329 
95330 #define USB_GUSB2PHYCFG_PHYSOFTRST_MASK          (0x80000000U)
95331 #define USB_GUSB2PHYCFG_PHYSOFTRST_SHIFT         (31U)
95332 #define USB_GUSB2PHYCFG_PHYSOFTRST(x)            (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_PHYSOFTRST_SHIFT)) & USB_GUSB2PHYCFG_PHYSOFTRST_MASK)
95333 /*! @} */
95334 
95335 /*! @name GUSB2PHYACC_ULPI - Global USB 2.0 UTMI PHY vendor control register */
95336 /*! @{ */
95337 
95338 #define USB_GUSB2PHYACC_ULPI_REGDATA_MASK        (0xFFU)
95339 #define USB_GUSB2PHYACC_ULPI_REGDATA_SHIFT       (0U)
95340 #define USB_GUSB2PHYACC_ULPI_REGDATA(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_REGDATA_SHIFT)) & USB_GUSB2PHYACC_ULPI_REGDATA_MASK)
95341 
95342 #define USB_GUSB2PHYACC_ULPI_EXTREGADDR_MASK     (0xFF00U)
95343 #define USB_GUSB2PHYACC_ULPI_EXTREGADDR_SHIFT    (8U)
95344 #define USB_GUSB2PHYACC_ULPI_EXTREGADDR(x)       (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_EXTREGADDR_SHIFT)) & USB_GUSB2PHYACC_ULPI_EXTREGADDR_MASK)
95345 
95346 #define USB_GUSB2PHYACC_ULPI_REGADDR_MASK        (0x3F0000U)
95347 #define USB_GUSB2PHYACC_ULPI_REGADDR_SHIFT       (16U)
95348 #define USB_GUSB2PHYACC_ULPI_REGADDR(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_REGADDR_SHIFT)) & USB_GUSB2PHYACC_ULPI_REGADDR_MASK)
95349 
95350 #define USB_GUSB2PHYACC_ULPI_REGWR_MASK          (0x400000U)
95351 #define USB_GUSB2PHYACC_ULPI_REGWR_SHIFT         (22U)
95352 #define USB_GUSB2PHYACC_ULPI_REGWR(x)            (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_REGWR_SHIFT)) & USB_GUSB2PHYACC_ULPI_REGWR_MASK)
95353 
95354 #define USB_GUSB2PHYACC_ULPI_VSTSBSY_MASK        (0x800000U)
95355 #define USB_GUSB2PHYACC_ULPI_VSTSBSY_SHIFT       (23U)
95356 #define USB_GUSB2PHYACC_ULPI_VSTSBSY(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_VSTSBSY_SHIFT)) & USB_GUSB2PHYACC_ULPI_VSTSBSY_MASK)
95357 
95358 #define USB_GUSB2PHYACC_ULPI_VSTSDONE_MASK       (0x1000000U)
95359 #define USB_GUSB2PHYACC_ULPI_VSTSDONE_SHIFT      (24U)
95360 #define USB_GUSB2PHYACC_ULPI_VSTSDONE(x)         (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_VSTSDONE_SHIFT)) & USB_GUSB2PHYACC_ULPI_VSTSDONE_MASK)
95361 
95362 #define USB_GUSB2PHYACC_ULPI_NEWREGREQ_MASK      (0x2000000U)
95363 #define USB_GUSB2PHYACC_ULPI_NEWREGREQ_SHIFT     (25U)
95364 #define USB_GUSB2PHYACC_ULPI_NEWREGREQ(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_NEWREGREQ_SHIFT)) & USB_GUSB2PHYACC_ULPI_NEWREGREQ_MASK)
95365 
95366 #define USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_MASK    (0x4000000U)
95367 #define USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_SHIFT   (26U)
95368 #define USB_GUSB2PHYACC_ULPI_DISUIPIDRVR(x)      (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_SHIFT)) & USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_MASK)
95369 /*! @} */
95370 
95371 /*! @name GUSB3PIPECTL - Global USB 3.0 PIPE control register */
95372 /*! @{ */
95373 
95374 #define USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_MASK (0x1U)
95375 #define USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHIFT (0U)
95376 #define USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHIFT)) & USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_MASK)
95377 
95378 #define USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK  (0x6U)
95379 #define USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_SHIFT (1U)
95380 #define USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS(x)    (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_SHIFT)) & USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK)
95381 
95382 #define USB_GUSB3PIPECTL_TX_MARGIN_MASK          (0x38U)
95383 #define USB_GUSB3PIPECTL_TX_MARGIN_SHIFT         (3U)
95384 #define USB_GUSB3PIPECTL_TX_MARGIN(x)            (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_TX_MARGIN_SHIFT)) & USB_GUSB3PIPECTL_TX_MARGIN_MASK)
95385 
95386 #define USB_GUSB3PIPECTL_TX_SWING_MASK           (0x40U)
95387 #define USB_GUSB3PIPECTL_TX_SWING_SHIFT          (6U)
95388 #define USB_GUSB3PIPECTL_TX_SWING(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_TX_SWING_SHIFT)) & USB_GUSB3PIPECTL_TX_SWING_MASK)
95389 
95390 #define USB_GUSB3PIPECTL_SSICEN_MASK             (0x80U)
95391 #define USB_GUSB3PIPECTL_SSICEN_SHIFT            (7U)
95392 #define USB_GUSB3PIPECTL_SSICEN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SSICEN_SHIFT)) & USB_GUSB3PIPECTL_SSICEN_MASK)
95393 
95394 #define USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_MASK (0x100U)
95395 #define USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_SHIFT (8U)
95396 #define USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_SHIFT)) & USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_MASK)
95397 
95398 #define USB_GUSB3PIPECTL_LFPSFILTER_MASK         (0x200U)
95399 #define USB_GUSB3PIPECTL_LFPSFILTER_SHIFT        (9U)
95400 #define USB_GUSB3PIPECTL_LFPSFILTER(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_LFPSFILTER_SHIFT)) & USB_GUSB3PIPECTL_LFPSFILTER_MASK)
95401 
95402 #define USB_GUSB3PIPECTL_P3EXSIGP2_MASK          (0x400U)
95403 #define USB_GUSB3PIPECTL_P3EXSIGP2_SHIFT         (10U)
95404 #define USB_GUSB3PIPECTL_P3EXSIGP2(x)            (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_P3EXSIGP2_SHIFT)) & USB_GUSB3PIPECTL_P3EXSIGP2_MASK)
95405 
95406 #define USB_GUSB3PIPECTL_P3P2TRANOK_MASK         (0x800U)
95407 #define USB_GUSB3PIPECTL_P3P2TRANOK_SHIFT        (11U)
95408 #define USB_GUSB3PIPECTL_P3P2TRANOK(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_P3P2TRANOK_SHIFT)) & USB_GUSB3PIPECTL_P3P2TRANOK_MASK)
95409 
95410 #define USB_GUSB3PIPECTL_LFPSP0ALGN_MASK         (0x1000U)
95411 #define USB_GUSB3PIPECTL_LFPSP0ALGN_SHIFT        (12U)
95412 #define USB_GUSB3PIPECTL_LFPSP0ALGN(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_LFPSP0ALGN_SHIFT)) & USB_GUSB3PIPECTL_LFPSP0ALGN_MASK)
95413 
95414 #define USB_GUSB3PIPECTL_SKIPRXDET_MASK          (0x2000U)
95415 #define USB_GUSB3PIPECTL_SKIPRXDET_SHIFT         (13U)
95416 #define USB_GUSB3PIPECTL_SKIPRXDET(x)            (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SKIPRXDET_SHIFT)) & USB_GUSB3PIPECTL_SKIPRXDET_MASK)
95417 
95418 #define USB_GUSB3PIPECTL_ABORTRXDETINU2_MASK     (0x4000U)
95419 #define USB_GUSB3PIPECTL_ABORTRXDETINU2_SHIFT    (14U)
95420 #define USB_GUSB3PIPECTL_ABORTRXDETINU2(x)       (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_ABORTRXDETINU2_SHIFT)) & USB_GUSB3PIPECTL_ABORTRXDETINU2_MASK)
95421 
95422 #define USB_GUSB3PIPECTL_DATWIDTH_MASK           (0x18000U)
95423 #define USB_GUSB3PIPECTL_DATWIDTH_SHIFT          (15U)
95424 #define USB_GUSB3PIPECTL_DATWIDTH(x)             (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DATWIDTH_SHIFT)) & USB_GUSB3PIPECTL_DATWIDTH_MASK)
95425 
95426 #define USB_GUSB3PIPECTL_SUSPENDENABLE_MASK      (0x20000U)
95427 #define USB_GUSB3PIPECTL_SUSPENDENABLE_SHIFT     (17U)
95428 #define USB_GUSB3PIPECTL_SUSPENDENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SUSPENDENABLE_SHIFT)) & USB_GUSB3PIPECTL_SUSPENDENABLE_MASK)
95429 
95430 #define USB_GUSB3PIPECTL_DELAYP1TRANS_MASK       (0x40000U)
95431 #define USB_GUSB3PIPECTL_DELAYP1TRANS_SHIFT      (18U)
95432 #define USB_GUSB3PIPECTL_DELAYP1TRANS(x)         (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DELAYP1TRANS_SHIFT)) & USB_GUSB3PIPECTL_DELAYP1TRANS_MASK)
95433 
95434 #define USB_GUSB3PIPECTL_DELAYP1P2P3_MASK        (0x380000U)
95435 #define USB_GUSB3PIPECTL_DELAYP1P2P3_SHIFT       (19U)
95436 #define USB_GUSB3PIPECTL_DELAYP1P2P3(x)          (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DELAYP1P2P3_SHIFT)) & USB_GUSB3PIPECTL_DELAYP1P2P3_MASK)
95437 
95438 #define USB_GUSB3PIPECTL_DISRXDETU3RXDET_MASK    (0x400000U)
95439 #define USB_GUSB3PIPECTL_DISRXDETU3RXDET_SHIFT   (22U)
95440 #define USB_GUSB3PIPECTL_DISRXDETU3RXDET(x)      (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DISRXDETU3RXDET_SHIFT)) & USB_GUSB3PIPECTL_DISRXDETU3RXDET_MASK)
95441 
95442 #define USB_GUSB3PIPECTL_STARTRXDETU3RXDET_MASK  (0x800000U)
95443 #define USB_GUSB3PIPECTL_STARTRXDETU3RXDET_SHIFT (23U)
95444 #define USB_GUSB3PIPECTL_STARTRXDETU3RXDET(x)    (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_STARTRXDETU3RXDET_SHIFT)) & USB_GUSB3PIPECTL_STARTRXDETU3RXDET_MASK)
95445 
95446 #define USB_GUSB3PIPECTL_REQUEST_P1P2P3_MASK     (0x1000000U)
95447 #define USB_GUSB3PIPECTL_REQUEST_P1P2P3_SHIFT    (24U)
95448 #define USB_GUSB3PIPECTL_REQUEST_P1P2P3(x)       (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_REQUEST_P1P2P3_SHIFT)) & USB_GUSB3PIPECTL_REQUEST_P1P2P3_MASK)
95449 
95450 #define USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_MASK (0x2000000U)
95451 #define USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_SHIFT (25U)
95452 #define USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_SHIFT)) & USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_MASK)
95453 
95454 #define USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_MASK (0x4000000U)
95455 #define USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_SHIFT (26U)
95456 #define USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_SHIFT)) & USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_MASK)
95457 
95458 #define USB_GUSB3PIPECTL_UX_EXIT_IN_PX_MASK      (0x8000000U)
95459 #define USB_GUSB3PIPECTL_UX_EXIT_IN_PX_SHIFT     (27U)
95460 #define USB_GUSB3PIPECTL_UX_EXIT_IN_PX(x)        (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_UX_EXIT_IN_PX_SHIFT)) & USB_GUSB3PIPECTL_UX_EXIT_IN_PX_MASK)
95461 
95462 #define USB_GUSB3PIPECTL_DISRXDETP3_MASK         (0x10000000U)
95463 #define USB_GUSB3PIPECTL_DISRXDETP3_SHIFT        (28U)
95464 #define USB_GUSB3PIPECTL_DISRXDETP3(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DISRXDETP3_SHIFT)) & USB_GUSB3PIPECTL_DISRXDETP3_MASK)
95465 
95466 #define USB_GUSB3PIPECTL_U2P3OK_MASK             (0x20000000U)
95467 #define USB_GUSB3PIPECTL_U2P3OK_SHIFT            (29U)
95468 #define USB_GUSB3PIPECTL_U2P3OK(x)               (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_U2P3OK_SHIFT)) & USB_GUSB3PIPECTL_U2P3OK_MASK)
95469 
95470 #define USB_GUSB3PIPECTL_HSTPRTCMPL_MASK         (0x40000000U)
95471 #define USB_GUSB3PIPECTL_HSTPRTCMPL_SHIFT        (30U)
95472 #define USB_GUSB3PIPECTL_HSTPRTCMPL(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_HSTPRTCMPL_SHIFT)) & USB_GUSB3PIPECTL_HSTPRTCMPL_MASK)
95473 
95474 #define USB_GUSB3PIPECTL_PHYSOFTRST_MASK         (0x80000000U)
95475 #define USB_GUSB3PIPECTL_PHYSOFTRST_SHIFT        (31U)
95476 #define USB_GUSB3PIPECTL_PHYSOFTRST(x)           (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_PHYSOFTRST_SHIFT)) & USB_GUSB3PIPECTL_PHYSOFTRST_MASK)
95477 /*! @} */
95478 
95479 /*! @name GTXFIFOSIZ - Global transmit FIFO size register */
95480 /*! @{ */
95481 
95482 #define USB_GTXFIFOSIZ_TXFDEP_N_MASK             (0xFFFFU)
95483 #define USB_GTXFIFOSIZ_TXFDEP_N_SHIFT            (0U)
95484 /*! TXFDEP_N - TXFIFO depth */
95485 #define USB_GTXFIFOSIZ_TXFDEP_N(x)               (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOSIZ_TXFDEP_N_SHIFT)) & USB_GTXFIFOSIZ_TXFDEP_N_MASK)
95486 
95487 #define USB_GTXFIFOSIZ_TXFSTADDR_N_MASK          (0xFFFF0000U)
95488 #define USB_GTXFIFOSIZ_TXFSTADDR_N_SHIFT         (16U)
95489 #define USB_GTXFIFOSIZ_TXFSTADDR_N(x)            (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOSIZ_TXFSTADDR_N_SHIFT)) & USB_GTXFIFOSIZ_TXFSTADDR_N_MASK)
95490 /*! @} */
95491 
95492 /* The count of USB_GTXFIFOSIZ */
95493 #define USB_GTXFIFOSIZ_COUNT                     (8U)
95494 
95495 /*! @name GRXFIFOSIZ - Global receive FIFO size register */
95496 /*! @{ */
95497 
95498 #define USB_GRXFIFOSIZ_RXFDEP_N_MASK             (0xFFFFU)
95499 #define USB_GRXFIFOSIZ_RXFDEP_N_SHIFT            (0U)
95500 #define USB_GRXFIFOSIZ_RXFDEP_N(x)               (((uint32_t)(((uint32_t)(x)) << USB_GRXFIFOSIZ_RXFDEP_N_SHIFT)) & USB_GRXFIFOSIZ_RXFDEP_N_MASK)
95501 
95502 #define USB_GRXFIFOSIZ_RXFSTADDR_N_MASK          (0xFFFF0000U)
95503 #define USB_GRXFIFOSIZ_RXFSTADDR_N_SHIFT         (16U)
95504 #define USB_GRXFIFOSIZ_RXFSTADDR_N(x)            (((uint32_t)(((uint32_t)(x)) << USB_GRXFIFOSIZ_RXFSTADDR_N_SHIFT)) & USB_GRXFIFOSIZ_RXFSTADDR_N_MASK)
95505 /*! @} */
95506 
95507 /* The count of USB_GRXFIFOSIZ */
95508 #define USB_GRXFIFOSIZ_COUNT                     (3U)
95509 
95510 /*! @name GEVNTADRLO - Global Event Buffer Address (Low) Register */
95511 /*! @{ */
95512 
95513 #define USB_GEVNTADRLO_EVNTADRLO_MASK            (0xFFFFFFFFU)
95514 #define USB_GEVNTADRLO_EVNTADRLO_SHIFT           (0U)
95515 #define USB_GEVNTADRLO_EVNTADRLO(x)              (((uint32_t)(((uint32_t)(x)) << USB_GEVNTADRLO_EVNTADRLO_SHIFT)) & USB_GEVNTADRLO_EVNTADRLO_MASK)
95516 /*! @} */
95517 
95518 /*! @name GEVNTADRHI - Global Event Buffer Address (High) Register */
95519 /*! @{ */
95520 
95521 #define USB_GEVNTADRHI_EVNTADRHI_MASK            (0xFFFFFFFFU)
95522 #define USB_GEVNTADRHI_EVNTADRHI_SHIFT           (0U)
95523 #define USB_GEVNTADRHI_EVNTADRHI(x)              (((uint32_t)(((uint32_t)(x)) << USB_GEVNTADRHI_EVNTADRHI_SHIFT)) & USB_GEVNTADRHI_EVNTADRHI_MASK)
95524 /*! @} */
95525 
95526 /*! @name GEVNTSIZ - Global event buffer size register */
95527 /*! @{ */
95528 
95529 #define USB_GEVNTSIZ_EVENTSIZ_MASK               (0xFFFFU)
95530 #define USB_GEVNTSIZ_EVENTSIZ_SHIFT              (0U)
95531 #define USB_GEVNTSIZ_EVENTSIZ(x)                 (((uint32_t)(((uint32_t)(x)) << USB_GEVNTSIZ_EVENTSIZ_SHIFT)) & USB_GEVNTSIZ_EVENTSIZ_MASK)
95532 
95533 #define USB_GEVNTSIZ_EVNTINTRPTMASK_MASK         (0x80000000U)
95534 #define USB_GEVNTSIZ_EVNTINTRPTMASK_SHIFT        (31U)
95535 #define USB_GEVNTSIZ_EVNTINTRPTMASK(x)           (((uint32_t)(((uint32_t)(x)) << USB_GEVNTSIZ_EVNTINTRPTMASK_SHIFT)) & USB_GEVNTSIZ_EVNTINTRPTMASK_MASK)
95536 /*! @} */
95537 
95538 /*! @name GEVNTCOUNT - Global event buffer count register */
95539 /*! @{ */
95540 
95541 #define USB_GEVNTCOUNT_EVNTCOUNT_MASK            (0xFFFFU)
95542 #define USB_GEVNTCOUNT_EVNTCOUNT_SHIFT           (0U)
95543 #define USB_GEVNTCOUNT_EVNTCOUNT(x)              (((uint32_t)(((uint32_t)(x)) << USB_GEVNTCOUNT_EVNTCOUNT_SHIFT)) & USB_GEVNTCOUNT_EVNTCOUNT_MASK)
95544 
95545 #define USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_MASK    (0x80000000U)
95546 #define USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_SHIFT   (31U)
95547 #define USB_GEVNTCOUNT_EVNT_HANDLER_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_SHIFT)) & USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_MASK)
95548 /*! @} */
95549 
95550 /*! @name GHWPARAMS8 - Global Hardware Parameters Register 8 */
95551 /*! @{ */
95552 
95553 #define USB_GHWPARAMS8_GHWPARAMS8_32_0_MASK      (0xFFFFFFFFU)
95554 #define USB_GHWPARAMS8_GHWPARAMS8_32_0_SHIFT     (0U)
95555 #define USB_GHWPARAMS8_GHWPARAMS8_32_0(x)        (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS8_GHWPARAMS8_32_0_SHIFT)) & USB_GHWPARAMS8_GHWPARAMS8_32_0_MASK)
95556 /*! @} */
95557 
95558 /*! @name GTXFIFOPRIDEV - Global Device TX FIFO DMA Priority Register */
95559 /*! @{ */
95560 
95561 #define USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_MASK     (0xFFU)
95562 #define USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_SHIFT    (0U)
95563 #define USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV(x)       (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_SHIFT)) & USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_MASK)
95564 /*! @} */
95565 
95566 /*! @name GTXFIFOPRIHST - Global Host TX FIFO DMA Priority Register */
95567 /*! @{ */
95568 
95569 #define USB_GTXFIFOPRIHST_GTXFIFOPRIHST_MASK     (0xFU)
95570 #define USB_GTXFIFOPRIHST_GTXFIFOPRIHST_SHIFT    (0U)
95571 #define USB_GTXFIFOPRIHST_GTXFIFOPRIHST(x)       (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOPRIHST_GTXFIFOPRIHST_SHIFT)) & USB_GTXFIFOPRIHST_GTXFIFOPRIHST_MASK)
95572 /*! @} */
95573 
95574 /*! @name GRXFIFOPRIHST - Global Host RX FIFO DMA Priority Register */
95575 /*! @{ */
95576 
95577 #define USB_GRXFIFOPRIHST_GRXFIFOPRIHST_MASK     (0x7U)
95578 #define USB_GRXFIFOPRIHST_GRXFIFOPRIHST_SHIFT    (0U)
95579 #define USB_GRXFIFOPRIHST_GRXFIFOPRIHST(x)       (((uint32_t)(((uint32_t)(x)) << USB_GRXFIFOPRIHST_GRXFIFOPRIHST_SHIFT)) & USB_GRXFIFOPRIHST_GRXFIFOPRIHST_MASK)
95580 /*! @} */
95581 
95582 /*! @name GFIFOPRIDBC - Global Host Debug Capability DMA Priority Register */
95583 /*! @{ */
95584 
95585 #define USB_GFIFOPRIDBC_GFIFOPRIDBC_MASK         (0x3U)
95586 #define USB_GFIFOPRIDBC_GFIFOPRIDBC_SHIFT        (0U)
95587 #define USB_GFIFOPRIDBC_GFIFOPRIDBC(x)           (((uint32_t)(((uint32_t)(x)) << USB_GFIFOPRIDBC_GFIFOPRIDBC_SHIFT)) & USB_GFIFOPRIDBC_GFIFOPRIDBC_MASK)
95588 /*! @} */
95589 
95590 /*! @name GDMAHLRATIO -  */
95591 /*! @{ */
95592 
95593 #define USB_GDMAHLRATIO_HSTTXFIFO_MASK           (0x1FU)
95594 #define USB_GDMAHLRATIO_HSTTXFIFO_SHIFT          (0U)
95595 #define USB_GDMAHLRATIO_HSTTXFIFO(x)             (((uint32_t)(((uint32_t)(x)) << USB_GDMAHLRATIO_HSTTXFIFO_SHIFT)) & USB_GDMAHLRATIO_HSTTXFIFO_MASK)
95596 
95597 #define USB_GDMAHLRATIO_HSTRXFIFO_MASK           (0x1F00U)
95598 #define USB_GDMAHLRATIO_HSTRXFIFO_SHIFT          (8U)
95599 #define USB_GDMAHLRATIO_HSTRXFIFO(x)             (((uint32_t)(((uint32_t)(x)) << USB_GDMAHLRATIO_HSTRXFIFO_SHIFT)) & USB_GDMAHLRATIO_HSTRXFIFO_MASK)
95600 /*! @} */
95601 
95602 /*! @name GFLADJ - Global Frame Length Adjustment Register */
95603 /*! @{ */
95604 
95605 #define USB_GFLADJ_GFLADJ_30MHZ_MASK             (0x3FU)
95606 #define USB_GFLADJ_GFLADJ_30MHZ_SHIFT            (0U)
95607 #define USB_GFLADJ_GFLADJ_30MHZ(x)               (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_30MHZ_SHIFT)) & USB_GFLADJ_GFLADJ_30MHZ_MASK)
95608 
95609 #define USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_MASK   (0x80U)
95610 #define USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_SHIFT  (7U)
95611 #define USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL(x)     (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_SHIFT)) & USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_MASK)
95612 
95613 #define USB_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK      (0x3FFF00U)
95614 #define USB_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT     (8U)
95615 #define USB_GFLADJ_GFLADJ_REFCLK_FLADJ(x)        (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK)
95616 
95617 #define USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_MASK    (0x800000U)
95618 #define USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_SHIFT   (23U)
95619 #define USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_MASK)
95620 
95621 #define USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK (0x7F000000U)
95622 #define USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_SHIFT (24U)
95623 #define USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR(x)  (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK)
95624 
95625 #define USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_MASK (0x80000000U)
95626 #define USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_SHIFT (31U)
95627 #define USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_MASK)
95628 /*! @} */
95629 
95630 /*! @name DCFG - Device Configuration Register */
95631 /*! @{ */
95632 
95633 #define USB_DCFG_DEVSPD_MASK                     (0x7U)
95634 #define USB_DCFG_DEVSPD_SHIFT                    (0U)
95635 /*! DEVSPD
95636  *  0b001..
95637  *  0b000..
95638  *  0b100..
95639  */
95640 #define USB_DCFG_DEVSPD(x)                       (((uint32_t)(((uint32_t)(x)) << USB_DCFG_DEVSPD_SHIFT)) & USB_DCFG_DEVSPD_MASK)
95641 
95642 #define USB_DCFG_DEVADDR_MASK                    (0x3F8U)
95643 #define USB_DCFG_DEVADDR_SHIFT                   (3U)
95644 #define USB_DCFG_DEVADDR(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCFG_DEVADDR_SHIFT)) & USB_DCFG_DEVADDR_MASK)
95645 
95646 #define USB_DCFG_INTRNUM_MASK                    (0x1F000U)
95647 #define USB_DCFG_INTRNUM_SHIFT                   (12U)
95648 #define USB_DCFG_INTRNUM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCFG_INTRNUM_SHIFT)) & USB_DCFG_INTRNUM_MASK)
95649 
95650 #define USB_DCFG_NUMP_MASK                       (0x3E0000U)
95651 #define USB_DCFG_NUMP_SHIFT                      (17U)
95652 #define USB_DCFG_NUMP(x)                         (((uint32_t)(((uint32_t)(x)) << USB_DCFG_NUMP_SHIFT)) & USB_DCFG_NUMP_MASK)
95653 
95654 #define USB_DCFG_LPMCAP_MASK                     (0x400000U)
95655 #define USB_DCFG_LPMCAP_SHIFT                    (22U)
95656 #define USB_DCFG_LPMCAP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_DCFG_LPMCAP_SHIFT)) & USB_DCFG_LPMCAP_MASK)
95657 
95658 #define USB_DCFG_IGNSTRMPP_MASK                  (0x800000U)
95659 #define USB_DCFG_IGNSTRMPP_SHIFT                 (23U)
95660 #define USB_DCFG_IGNSTRMPP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_DCFG_IGNSTRMPP_SHIFT)) & USB_DCFG_IGNSTRMPP_MASK)
95661 /*! @} */
95662 
95663 /*! @name DCTL - Device control register */
95664 /*! @{ */
95665 
95666 #define USB_DCTL_TSTCTL_MASK                     (0x1EU)
95667 #define USB_DCTL_TSTCTL_SHIFT                    (1U)
95668 #define USB_DCTL_TSTCTL(x)                       (((uint32_t)(((uint32_t)(x)) << USB_DCTL_TSTCTL_SHIFT)) & USB_DCTL_TSTCTL_MASK)
95669 
95670 #define USB_DCTL_ULSTCHNGREQ_MASK                (0x1E0U)
95671 #define USB_DCTL_ULSTCHNGREQ_SHIFT               (5U)
95672 #define USB_DCTL_ULSTCHNGREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DCTL_ULSTCHNGREQ_SHIFT)) & USB_DCTL_ULSTCHNGREQ_MASK)
95673 
95674 #define USB_DCTL_ACCEPTU1ENA_MASK                (0x200U)
95675 #define USB_DCTL_ACCEPTU1ENA_SHIFT               (9U)
95676 #define USB_DCTL_ACCEPTU1ENA(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DCTL_ACCEPTU1ENA_SHIFT)) & USB_DCTL_ACCEPTU1ENA_MASK)
95677 
95678 #define USB_DCTL_INITU1ENA_MASK                  (0x400U)
95679 #define USB_DCTL_INITU1ENA_SHIFT                 (10U)
95680 #define USB_DCTL_INITU1ENA(x)                    (((uint32_t)(((uint32_t)(x)) << USB_DCTL_INITU1ENA_SHIFT)) & USB_DCTL_INITU1ENA_MASK)
95681 
95682 #define USB_DCTL_ACCEPTU2ENA_MASK                (0x800U)
95683 #define USB_DCTL_ACCEPTU2ENA_SHIFT               (11U)
95684 #define USB_DCTL_ACCEPTU2ENA(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DCTL_ACCEPTU2ENA_SHIFT)) & USB_DCTL_ACCEPTU2ENA_MASK)
95685 
95686 #define USB_DCTL_INITU2ENA_MASK                  (0x1000U)
95687 #define USB_DCTL_INITU2ENA_SHIFT                 (12U)
95688 #define USB_DCTL_INITU2ENA(x)                    (((uint32_t)(((uint32_t)(x)) << USB_DCTL_INITU2ENA_SHIFT)) & USB_DCTL_INITU2ENA_MASK)
95689 
95690 #define USB_DCTL_CSS_MASK                        (0x10000U)
95691 #define USB_DCTL_CSS_SHIFT                       (16U)
95692 #define USB_DCTL_CSS(x)                          (((uint32_t)(((uint32_t)(x)) << USB_DCTL_CSS_SHIFT)) & USB_DCTL_CSS_MASK)
95693 
95694 #define USB_DCTL_CRS_MASK                        (0x20000U)
95695 #define USB_DCTL_CRS_SHIFT                       (17U)
95696 #define USB_DCTL_CRS(x)                          (((uint32_t)(((uint32_t)(x)) << USB_DCTL_CRS_SHIFT)) & USB_DCTL_CRS_MASK)
95697 
95698 #define USB_DCTL_L1HIBERNATIONEN_MASK            (0x40000U)
95699 #define USB_DCTL_L1HIBERNATIONEN_SHIFT           (18U)
95700 #define USB_DCTL_L1HIBERNATIONEN(x)              (((uint32_t)(((uint32_t)(x)) << USB_DCTL_L1HIBERNATIONEN_SHIFT)) & USB_DCTL_L1HIBERNATIONEN_MASK)
95701 
95702 #define USB_DCTL_KEEPCONNECT_MASK                (0x80000U)
95703 #define USB_DCTL_KEEPCONNECT_SHIFT               (19U)
95704 #define USB_DCTL_KEEPCONNECT(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DCTL_KEEPCONNECT_SHIFT)) & USB_DCTL_KEEPCONNECT_MASK)
95705 
95706 #define USB_DCTL_LPM_NYET_THRES_MASK             (0xF00000U)
95707 #define USB_DCTL_LPM_NYET_THRES_SHIFT            (20U)
95708 #define USB_DCTL_LPM_NYET_THRES(x)               (((uint32_t)(((uint32_t)(x)) << USB_DCTL_LPM_NYET_THRES_SHIFT)) & USB_DCTL_LPM_NYET_THRES_MASK)
95709 
95710 #define USB_DCTL_HIRDTHRES_MASK                  (0x1F000000U)
95711 #define USB_DCTL_HIRDTHRES_SHIFT                 (24U)
95712 #define USB_DCTL_HIRDTHRES(x)                    (((uint32_t)(((uint32_t)(x)) << USB_DCTL_HIRDTHRES_SHIFT)) & USB_DCTL_HIRDTHRES_MASK)
95713 
95714 #define USB_DCTL_CSFTRST_MASK                    (0x40000000U)
95715 #define USB_DCTL_CSFTRST_SHIFT                   (30U)
95716 #define USB_DCTL_CSFTRST(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCTL_CSFTRST_SHIFT)) & USB_DCTL_CSFTRST_MASK)
95717 
95718 #define USB_DCTL_RUN_STOP_MASK                   (0x80000000U)
95719 #define USB_DCTL_RUN_STOP_SHIFT                  (31U)
95720 #define USB_DCTL_RUN_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCTL_RUN_STOP_SHIFT)) & USB_DCTL_RUN_STOP_MASK)
95721 /*! @} */
95722 
95723 /*! @name DEVTEN - Device Event Enable Register */
95724 /*! @{ */
95725 
95726 #define USB_DEVTEN_DISSCONNEVTEN_MASK            (0x1U)
95727 #define USB_DEVTEN_DISSCONNEVTEN_SHIFT           (0U)
95728 #define USB_DEVTEN_DISSCONNEVTEN(x)              (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_DISSCONNEVTEN_SHIFT)) & USB_DEVTEN_DISSCONNEVTEN_MASK)
95729 
95730 #define USB_DEVTEN_USBRSTEVTEN_MASK              (0x2U)
95731 #define USB_DEVTEN_USBRSTEVTEN_SHIFT             (1U)
95732 #define USB_DEVTEN_USBRSTEVTEN(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_USBRSTEVTEN_SHIFT)) & USB_DEVTEN_USBRSTEVTEN_MASK)
95733 
95734 #define USB_DEVTEN_CONNECTDONEEVTEN_MASK         (0x4U)
95735 #define USB_DEVTEN_CONNECTDONEEVTEN_SHIFT        (2U)
95736 #define USB_DEVTEN_CONNECTDONEEVTEN(x)           (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_CONNECTDONEEVTEN_SHIFT)) & USB_DEVTEN_CONNECTDONEEVTEN_MASK)
95737 
95738 #define USB_DEVTEN_ULSTCNGEN_MASK                (0x8U)
95739 #define USB_DEVTEN_ULSTCNGEN_SHIFT               (3U)
95740 #define USB_DEVTEN_ULSTCNGEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_ULSTCNGEN_SHIFT)) & USB_DEVTEN_ULSTCNGEN_MASK)
95741 
95742 #define USB_DEVTEN_WKUPEVTEN_MASK                (0x10U)
95743 #define USB_DEVTEN_WKUPEVTEN_SHIFT               (4U)
95744 #define USB_DEVTEN_WKUPEVTEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_WKUPEVTEN_SHIFT)) & USB_DEVTEN_WKUPEVTEN_MASK)
95745 
95746 #define USB_DEVTEN_HIBERNATIONREQEVTEN_MASK      (0x20U)
95747 #define USB_DEVTEN_HIBERNATIONREQEVTEN_SHIFT     (5U)
95748 #define USB_DEVTEN_HIBERNATIONREQEVTEN(x)        (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_HIBERNATIONREQEVTEN_SHIFT)) & USB_DEVTEN_HIBERNATIONREQEVTEN_MASK)
95749 
95750 #define USB_DEVTEN_U3L2L1SUSPEN_MASK             (0x40U)
95751 #define USB_DEVTEN_U3L2L1SUSPEN_SHIFT            (6U)
95752 #define USB_DEVTEN_U3L2L1SUSPEN(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_U3L2L1SUSPEN_SHIFT)) & USB_DEVTEN_U3L2L1SUSPEN_MASK)
95753 
95754 #define USB_DEVTEN_SOFTEVTEN_MASK                (0x80U)
95755 #define USB_DEVTEN_SOFTEVTEN_SHIFT               (7U)
95756 #define USB_DEVTEN_SOFTEVTEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_SOFTEVTEN_SHIFT)) & USB_DEVTEN_SOFTEVTEN_MASK)
95757 
95758 #define USB_DEVTEN_L1SUSPEN_MASK                 (0x100U)
95759 #define USB_DEVTEN_L1SUSPEN_SHIFT                (8U)
95760 #define USB_DEVTEN_L1SUSPEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_L1SUSPEN_SHIFT)) & USB_DEVTEN_L1SUSPEN_MASK)
95761 
95762 #define USB_DEVTEN_ERRTICERREVTEN_MASK           (0x200U)
95763 #define USB_DEVTEN_ERRTICERREVTEN_SHIFT          (9U)
95764 #define USB_DEVTEN_ERRTICERREVTEN(x)             (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_ERRTICERREVTEN_SHIFT)) & USB_DEVTEN_ERRTICERREVTEN_MASK)
95765 
95766 #define USB_DEVTEN_VENDEVTSTRCVDEN_MASK          (0x1000U)
95767 #define USB_DEVTEN_VENDEVTSTRCVDEN_SHIFT         (12U)
95768 #define USB_DEVTEN_VENDEVTSTRCVDEN(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_VENDEVTSTRCVDEN_SHIFT)) & USB_DEVTEN_VENDEVTSTRCVDEN_MASK)
95769 
95770 #define USB_DEVTEN_L1WKUPEVTEN_MASK              (0x4000U)
95771 #define USB_DEVTEN_L1WKUPEVTEN_SHIFT             (14U)
95772 #define USB_DEVTEN_L1WKUPEVTEN(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_L1WKUPEVTEN_SHIFT)) & USB_DEVTEN_L1WKUPEVTEN_MASK)
95773 
95774 #define USB_DEVTEN_ECCERREN_MASK                 (0x10000U)
95775 #define USB_DEVTEN_ECCERREN_SHIFT                (16U)
95776 #define USB_DEVTEN_ECCERREN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_ECCERREN_SHIFT)) & USB_DEVTEN_ECCERREN_MASK)
95777 /*! @} */
95778 
95779 /*! @name DSTS - Device Status Register */
95780 /*! @{ */
95781 
95782 #define USB_DSTS_CONNECTSPD_MASK                 (0x7U)
95783 #define USB_DSTS_CONNECTSPD_SHIFT                (0U)
95784 /*! CONNECTSPD
95785  *  0b001..
95786  *  0b000..
95787  *  0b100..
95788  */
95789 #define USB_DSTS_CONNECTSPD(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DSTS_CONNECTSPD_SHIFT)) & USB_DSTS_CONNECTSPD_MASK)
95790 
95791 #define USB_DSTS_SOFFN_MASK                      (0x1FFF8U)
95792 #define USB_DSTS_SOFFN_SHIFT                     (3U)
95793 #define USB_DSTS_SOFFN(x)                        (((uint32_t)(((uint32_t)(x)) << USB_DSTS_SOFFN_SHIFT)) & USB_DSTS_SOFFN_MASK)
95794 
95795 #define USB_DSTS_RXFIFOEMPTY_MASK                (0x20000U)
95796 #define USB_DSTS_RXFIFOEMPTY_SHIFT               (17U)
95797 #define USB_DSTS_RXFIFOEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DSTS_RXFIFOEMPTY_SHIFT)) & USB_DSTS_RXFIFOEMPTY_MASK)
95798 
95799 #define USB_DSTS_USBLNKST_MASK                   (0x3C0000U)
95800 #define USB_DSTS_USBLNKST_SHIFT                  (18U)
95801 #define USB_DSTS_USBLNKST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DSTS_USBLNKST_SHIFT)) & USB_DSTS_USBLNKST_MASK)
95802 
95803 #define USB_DSTS_DEVCTRLHLT_MASK                 (0x400000U)
95804 #define USB_DSTS_DEVCTRLHLT_SHIFT                (22U)
95805 #define USB_DSTS_DEVCTRLHLT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DSTS_DEVCTRLHLT_SHIFT)) & USB_DSTS_DEVCTRLHLT_MASK)
95806 
95807 #define USB_DSTS_COREIDLE_MASK                   (0x800000U)
95808 #define USB_DSTS_COREIDLE_SHIFT                  (23U)
95809 #define USB_DSTS_COREIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DSTS_COREIDLE_SHIFT)) & USB_DSTS_COREIDLE_MASK)
95810 
95811 #define USB_DSTS_SSS_MASK                        (0x1000000U)
95812 #define USB_DSTS_SSS_SHIFT                       (24U)
95813 #define USB_DSTS_SSS(x)                          (((uint32_t)(((uint32_t)(x)) << USB_DSTS_SSS_SHIFT)) & USB_DSTS_SSS_MASK)
95814 
95815 #define USB_DSTS_RSS_MASK                        (0x2000000U)
95816 #define USB_DSTS_RSS_SHIFT                       (25U)
95817 #define USB_DSTS_RSS(x)                          (((uint32_t)(((uint32_t)(x)) << USB_DSTS_RSS_SHIFT)) & USB_DSTS_RSS_MASK)
95818 
95819 #define USB_DSTS_SRE_MASK                        (0x10000000U)
95820 #define USB_DSTS_SRE_SHIFT                       (28U)
95821 #define USB_DSTS_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << USB_DSTS_SRE_SHIFT)) & USB_DSTS_SRE_MASK)
95822 
95823 #define USB_DSTS_DCNRD_MASK                      (0x20000000U)
95824 #define USB_DSTS_DCNRD_SHIFT                     (29U)
95825 #define USB_DSTS_DCNRD(x)                        (((uint32_t)(((uint32_t)(x)) << USB_DSTS_DCNRD_SHIFT)) & USB_DSTS_DCNRD_MASK)
95826 /*! @} */
95827 
95828 /*! @name DGCMDPAR - Device Generic Command Parameter Register */
95829 /*! @{ */
95830 
95831 #define USB_DGCMDPAR_PARAMETER_MASK              (0xFFFFFFFFU)
95832 #define USB_DGCMDPAR_PARAMETER_SHIFT             (0U)
95833 #define USB_DGCMDPAR_PARAMETER(x)                (((uint32_t)(((uint32_t)(x)) << USB_DGCMDPAR_PARAMETER_SHIFT)) & USB_DGCMDPAR_PARAMETER_MASK)
95834 /*! @} */
95835 
95836 /*! @name DGCMD -  */
95837 /*! @{ */
95838 
95839 #define USB_DGCMD_CMDTYP_MASK                    (0xFFU)
95840 #define USB_DGCMD_CMDTYP_SHIFT                   (0U)
95841 #define USB_DGCMD_CMDTYP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDTYP_SHIFT)) & USB_DGCMD_CMDTYP_MASK)
95842 
95843 #define USB_DGCMD_CMDIOC_MASK                    (0x100U)
95844 #define USB_DGCMD_CMDIOC_SHIFT                   (8U)
95845 #define USB_DGCMD_CMDIOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDIOC_SHIFT)) & USB_DGCMD_CMDIOC_MASK)
95846 
95847 #define USB_DGCMD_CMDACT_MASK                    (0x400U)
95848 #define USB_DGCMD_CMDACT_SHIFT                   (10U)
95849 #define USB_DGCMD_CMDACT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDACT_SHIFT)) & USB_DGCMD_CMDACT_MASK)
95850 
95851 #define USB_DGCMD_CMDSTATUS_MASK                 (0xF000U)
95852 #define USB_DGCMD_CMDSTATUS_SHIFT                (12U)
95853 #define USB_DGCMD_CMDSTATUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDSTATUS_SHIFT)) & USB_DGCMD_CMDSTATUS_MASK)
95854 /*! @} */
95855 
95856 /*! @name DALEPENA - Device Active USB Endpoint Enable Register */
95857 /*! @{ */
95858 
95859 #define USB_DALEPENA_USBACTEP_MASK               (0xFFFFFFFFU)
95860 #define USB_DALEPENA_USBACTEP_SHIFT              (0U)
95861 #define USB_DALEPENA_USBACTEP(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DALEPENA_USBACTEP_SHIFT)) & USB_DALEPENA_USBACTEP_MASK)
95862 /*! @} */
95863 
95864 /*! @name DEPCMDPAR2 - Device physical endpoint-n command parameter 2 register */
95865 /*! @{ */
95866 
95867 #define USB_DEPCMDPAR2_PARAMETER_MASK            (0xFFFFFFFFU)
95868 #define USB_DEPCMDPAR2_PARAMETER_SHIFT           (0U)
95869 #define USB_DEPCMDPAR2_PARAMETER(x)              (((uint32_t)(((uint32_t)(x)) << USB_DEPCMDPAR2_PARAMETER_SHIFT)) & USB_DEPCMDPAR2_PARAMETER_MASK)
95870 /*! @} */
95871 
95872 /*! @name DEPCMDPAR1 - Device Physical Endpoint-n Command Parameter 1 Register */
95873 /*! @{ */
95874 
95875 #define USB_DEPCMDPAR1_PARAMETER_MASK            (0xFFFFFFFFU)
95876 #define USB_DEPCMDPAR1_PARAMETER_SHIFT           (0U)
95877 #define USB_DEPCMDPAR1_PARAMETER(x)              (((uint32_t)(((uint32_t)(x)) << USB_DEPCMDPAR1_PARAMETER_SHIFT)) & USB_DEPCMDPAR1_PARAMETER_MASK)
95878 /*! @} */
95879 
95880 /*! @name DEPCMDPAR0 - Device Physical Endpoint-n Command Parameter 0 Register */
95881 /*! @{ */
95882 
95883 #define USB_DEPCMDPAR0_PARAMETER_MASK            (0xFFFFFFFFU)
95884 #define USB_DEPCMDPAR0_PARAMETER_SHIFT           (0U)
95885 #define USB_DEPCMDPAR0_PARAMETER(x)              (((uint32_t)(((uint32_t)(x)) << USB_DEPCMDPAR0_PARAMETER_SHIFT)) & USB_DEPCMDPAR0_PARAMETER_MASK)
95886 /*! @} */
95887 
95888 /*! @name DEPCMD - Device Physical Endpoint-n Command Register */
95889 /*! @{ */
95890 
95891 #define USB_DEPCMD_CMDTYP_MASK                   (0xFU)
95892 #define USB_DEPCMD_CMDTYP_SHIFT                  (0U)
95893 #define USB_DEPCMD_CMDTYP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDTYP_SHIFT)) & USB_DEPCMD_CMDTYP_MASK)
95894 
95895 #define USB_DEPCMD_CMDIOC_MASK                   (0x100U)
95896 #define USB_DEPCMD_CMDIOC_SHIFT                  (8U)
95897 #define USB_DEPCMD_CMDIOC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDIOC_SHIFT)) & USB_DEPCMD_CMDIOC_MASK)
95898 
95899 #define USB_DEPCMD_CMDACT_MASK                   (0x400U)
95900 #define USB_DEPCMD_CMDACT_SHIFT                  (10U)
95901 #define USB_DEPCMD_CMDACT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDACT_SHIFT)) & USB_DEPCMD_CMDACT_MASK)
95902 
95903 #define USB_DEPCMD_HIPRI_FORCERM_MASK            (0x800U)
95904 #define USB_DEPCMD_HIPRI_FORCERM_SHIFT           (11U)
95905 #define USB_DEPCMD_HIPRI_FORCERM(x)              (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_HIPRI_FORCERM_SHIFT)) & USB_DEPCMD_HIPRI_FORCERM_MASK)
95906 
95907 #define USB_DEPCMD_CMDSTATUS_MASK                (0xF000U)
95908 #define USB_DEPCMD_CMDSTATUS_SHIFT               (12U)
95909 #define USB_DEPCMD_CMDSTATUS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDSTATUS_SHIFT)) & USB_DEPCMD_CMDSTATUS_MASK)
95910 
95911 #define USB_DEPCMD_COMMANDPARAM_MASK             (0xFFFF0000U)
95912 #define USB_DEPCMD_COMMANDPARAM_SHIFT            (16U)
95913 #define USB_DEPCMD_COMMANDPARAM(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_COMMANDPARAM_SHIFT)) & USB_DEPCMD_COMMANDPARAM_MASK)
95914 /*! @} */
95915 
95916 /*! @name DEV_IMOD - Device Interrupt Moderation Register */
95917 /*! @{ */
95918 
95919 #define USB_DEV_IMOD_DEVICE_IMODI_MASK           (0xFFFFU)
95920 #define USB_DEV_IMOD_DEVICE_IMODI_SHIFT          (0U)
95921 #define USB_DEV_IMOD_DEVICE_IMODI(x)             (((uint32_t)(((uint32_t)(x)) << USB_DEV_IMOD_DEVICE_IMODI_SHIFT)) & USB_DEV_IMOD_DEVICE_IMODI_MASK)
95922 
95923 #define USB_DEV_IMOD_DEVICE_IMODC_MASK           (0xFFFF0000U)
95924 #define USB_DEV_IMOD_DEVICE_IMODC_SHIFT          (16U)
95925 #define USB_DEV_IMOD_DEVICE_IMODC(x)             (((uint32_t)(((uint32_t)(x)) << USB_DEV_IMOD_DEVICE_IMODC_SHIFT)) & USB_DEV_IMOD_DEVICE_IMODC_MASK)
95926 /*! @} */
95927 
95928 /*! @name BCFG - BCFG */
95929 /*! @{ */
95930 
95931 #define USB_BCFG_CHIRP_EN_MASK                   (0x1U)
95932 #define USB_BCFG_CHIRP_EN_SHIFT                  (0U)
95933 #define USB_BCFG_CHIRP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_BCFG_CHIRP_EN_SHIFT)) & USB_BCFG_CHIRP_EN_MASK)
95934 
95935 #define USB_BCFG_IDDIG_SEL_MASK                  (0x2U)
95936 #define USB_BCFG_IDDIG_SEL_SHIFT                 (1U)
95937 #define USB_BCFG_IDDIG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << USB_BCFG_IDDIG_SEL_SHIFT)) & USB_BCFG_IDDIG_SEL_MASK)
95938 /*! @} */
95939 
95940 /*! @name BCEVT - BCEVT */
95941 /*! @{ */
95942 
95943 #define USB_BCEVT_MULTVALIDBC_MASK               (0x1FU)
95944 #define USB_BCEVT_MULTVALIDBC_SHIFT              (0U)
95945 #define USB_BCEVT_MULTVALIDBC(x)                 (((uint32_t)(((uint32_t)(x)) << USB_BCEVT_MULTVALIDBC_SHIFT)) & USB_BCEVT_MULTVALIDBC_MASK)
95946 
95947 #define USB_BCEVT_MV_CHNGEVNT_MASK               (0x1000000U)
95948 #define USB_BCEVT_MV_CHNGEVNT_SHIFT              (24U)
95949 #define USB_BCEVT_MV_CHNGEVNT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_BCEVT_MV_CHNGEVNT_SHIFT)) & USB_BCEVT_MV_CHNGEVNT_MASK)
95950 /*! @} */
95951 
95952 /*! @name BCEVTEN - BCEVTEN */
95953 /*! @{ */
95954 
95955 #define USB_BCEVTEN_MV_CHNGEVNTENA_MASK          (0x1000000U)
95956 #define USB_BCEVTEN_MV_CHNGEVNTENA_SHIFT         (24U)
95957 #define USB_BCEVTEN_MV_CHNGEVNTENA(x)            (((uint32_t)(((uint32_t)(x)) << USB_BCEVTEN_MV_CHNGEVNTENA_SHIFT)) & USB_BCEVTEN_MV_CHNGEVNTENA_MASK)
95958 /*! @} */
95959 
95960 
95961 /*!
95962  * @}
95963  */ /* end of group USB_Register_Masks */
95964 
95965 
95966 /* USB - Peripheral instance base addresses */
95967 /** Peripheral USB1 base address */
95968 #define USB1_BASE                                (0x38100000u)
95969 /** Peripheral USB1 base pointer */
95970 #define USB1                                     ((USB_Type *)USB1_BASE)
95971 /** Peripheral USB2 base address */
95972 #define USB2_BASE                                (0x38200000u)
95973 /** Peripheral USB2 base pointer */
95974 #define USB2                                     ((USB_Type *)USB2_BASE)
95975 /** Array initializer of USB peripheral base addresses */
95976 #define USB_BASE_ADDRS                           { USB1_BASE, USB2_BASE }
95977 /** Array initializer of USB peripheral base pointers */
95978 #define USB_BASE_PTRS                            { USB1, USB2 }
95979 
95980 /*!
95981  * @}
95982  */ /* end of group USB_Peripheral_Access_Layer */
95983 
95984 
95985 /* ----------------------------------------------------------------------------
95986    -- USDHC Peripheral Access Layer
95987    ---------------------------------------------------------------------------- */
95988 
95989 /*!
95990  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
95991  * @{
95992  */
95993 
95994 /** USDHC - Register Layout Typedef */
95995 typedef struct {
95996   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
95997   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
95998   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
95999   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
96000   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
96001   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
96002   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
96003   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
96004   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
96005   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
96006   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
96007   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
96008   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
96009   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
96010   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
96011   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
96012   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
96013   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
96014   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
96015        uint8_t RESERVED_0[4];
96016   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
96017   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
96018   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
96019        uint8_t RESERVED_1[4];
96020   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
96021   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
96022   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
96023        uint8_t RESERVED_2[4];
96024   __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
96025   __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
96026        uint8_t RESERVED_3[72];
96027   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
96028   __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
96029   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
96030   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
96031        uint8_t RESERVED_4[48];
96032   __I  uint32_t CQVER;                             /**< Command Queuing Version, offset: 0x100 */
96033   __I  uint32_t CQCAP;                             /**< Command Queuing Capabilities, offset: 0x104 */
96034   __IO uint32_t CQCFG;                             /**< Command Queuing Configuration, offset: 0x108 */
96035   __IO uint32_t CQCTL;                             /**< Command Queuing Control, offset: 0x10C */
96036   __IO uint32_t CQIS;                              /**< Command Queuing Interrupt Status, offset: 0x110 */
96037   __IO uint32_t CQISTE;                            /**< Command Queuing Interrupt Status Enable, offset: 0x114 */
96038   __IO uint32_t CQISGE;                            /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */
96039   __IO uint32_t CQIC;                              /**< Command Queuing Interrupt Coalescing, offset: 0x11C */
96040   __IO uint32_t CQTDLBA;                           /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */
96041   __IO uint32_t CQTDLBAU;                          /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */
96042   __IO uint32_t CQTDBR;                            /**< Command Queuing Task Doorbell, offset: 0x128 */
96043   __IO uint32_t CQTCN;                             /**< Command Queuing Task Completion Notification, offset: 0x12C */
96044   __I  uint32_t CQDQS;                             /**< Command Queuing Device Queue Status, offset: 0x130 */
96045   __I  uint32_t CQDPT;                             /**< Command Queuing Device Pending Tasks, offset: 0x134 */
96046   __IO uint32_t CQTCLR;                            /**< Command Queuing Task Clear, offset: 0x138 */
96047        uint8_t RESERVED_5[4];
96048   __IO uint32_t CQSSC1;                            /**< Command Queuing Send Status Configuration 1, offset: 0x140 */
96049   __IO uint32_t CQSSC2;                            /**< Command Queuing Send Status Configuration 2, offset: 0x144 */
96050   __I  uint32_t CQCRDCT;                           /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */
96051        uint8_t RESERVED_6[4];
96052   __IO uint32_t CQRMEM;                            /**< Command Queuing Response Mode Error Mask, offset: 0x150 */
96053   __I  uint32_t CQTERRI;                           /**< Command Queuing Task Error Information, offset: 0x154 */
96054   __I  uint32_t CQCRI;                             /**< Command Queuing Command Response Index, offset: 0x158 */
96055   __I  uint32_t CQCRA;                             /**< Command Queuing Command Response Argument, offset: 0x15C */
96056 } USDHC_Type;
96057 
96058 /* ----------------------------------------------------------------------------
96059    -- USDHC Register Masks
96060    ---------------------------------------------------------------------------- */
96061 
96062 /*!
96063  * @addtogroup USDHC_Register_Masks USDHC Register Masks
96064  * @{
96065  */
96066 
96067 /*! @name DS_ADDR - DMA System Address */
96068 /*! @{ */
96069 
96070 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
96071 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
96072 /*! DS_ADDR - System address */
96073 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
96074 /*! @} */
96075 
96076 /*! @name BLK_ATT - Block Attributes */
96077 /*! @{ */
96078 
96079 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
96080 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
96081 /*! BLKSIZE - Transfer block size
96082  *  0b1000000000000..4096 bytes
96083  *  0b0100000000000..2048 bytes
96084  *  0b0001000000000..512 bytes
96085  *  0b0000111111111..511 bytes
96086  *  0b0000000000100..4 bytes
96087  *  0b0000000000011..3 bytes
96088  *  0b0000000000010..2 bytes
96089  *  0b0000000000001..1 byte
96090  *  0b0000000000000..No data transfer
96091  */
96092 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
96093 
96094 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
96095 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
96096 /*! BLKCNT - Blocks count for current transfer
96097  *  0b1111111111111111..65535 blocks
96098  *  0b0000000000000010..2 blocks
96099  *  0b0000000000000001..1 block
96100  *  0b0000000000000000..Stop count
96101  */
96102 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
96103 /*! @} */
96104 
96105 /*! @name CMD_ARG - Command Argument */
96106 /*! @{ */
96107 
96108 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
96109 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
96110 /*! CMDARG - Command argument */
96111 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
96112 /*! @} */
96113 
96114 /*! @name CMD_XFR_TYP - Command Transfer Type */
96115 /*! @{ */
96116 
96117 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
96118 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
96119 /*! RSPTYP - Response type select
96120  *  0b00..No response
96121  *  0b01..Response length 136
96122  *  0b10..Response length 48
96123  *  0b11..Response length 48, check busy after response
96124  */
96125 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
96126 
96127 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
96128 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
96129 /*! CCCEN - Command CRC check enable
96130  *  0b1..Enables command CRC check
96131  *  0b0..Disables command CRC check
96132  */
96133 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
96134 
96135 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
96136 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
96137 /*! CICEN - Command index check enable
96138  *  0b1..Enables command index check
96139  *  0b0..Disable command index check
96140  */
96141 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
96142 
96143 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
96144 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
96145 /*! DPSEL - Data present select
96146  *  0b1..Data present
96147  *  0b0..No data present
96148  */
96149 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
96150 
96151 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
96152 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
96153 /*! CMDTYP - Command type
96154  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
96155  *  0b10..Resume CMD52 for writing function select in CCCR
96156  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
96157  *  0b00..Normal other commands
96158  */
96159 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
96160 
96161 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
96162 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
96163 /*! CMDINX - Command index */
96164 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
96165 /*! @} */
96166 
96167 /*! @name CMD_RSP0 - Command Response0 */
96168 /*! @{ */
96169 
96170 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
96171 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
96172 /*! CMDRSP0 - Command response 0 */
96173 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
96174 /*! @} */
96175 
96176 /*! @name CMD_RSP1 - Command Response1 */
96177 /*! @{ */
96178 
96179 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
96180 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
96181 /*! CMDRSP1 - Command response 1 */
96182 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
96183 /*! @} */
96184 
96185 /*! @name CMD_RSP2 - Command Response2 */
96186 /*! @{ */
96187 
96188 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
96189 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
96190 /*! CMDRSP2 - Command response 2 */
96191 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
96192 /*! @} */
96193 
96194 /*! @name CMD_RSP3 - Command Response3 */
96195 /*! @{ */
96196 
96197 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
96198 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
96199 /*! CMDRSP3 - Command response 3 */
96200 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
96201 /*! @} */
96202 
96203 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
96204 /*! @{ */
96205 
96206 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
96207 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
96208 /*! DATCONT - Data content */
96209 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
96210 /*! @} */
96211 
96212 /*! @name PRES_STATE - Present State */
96213 /*! @{ */
96214 
96215 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
96216 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
96217 /*! CIHB - Command inhibit (CMD)
96218  *  0b1..Cannot issue command
96219  *  0b0..Can issue command using only CMD line
96220  */
96221 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
96222 
96223 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
96224 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
96225 /*! CDIHB - Command Inhibit Data (DATA)
96226  *  0b1..Cannot issue command that uses the DATA line
96227  *  0b0..Can issue command that uses the DATA line
96228  */
96229 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
96230 
96231 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
96232 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
96233 /*! DLA - Data line active
96234  *  0b1..DATA line active
96235  *  0b0..DATA line inactive
96236  */
96237 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
96238 
96239 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
96240 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
96241 /*! SDSTB - SD clock stable
96242  *  0b1..Clock is stable.
96243  *  0b0..Clock is changing frequency and not stable.
96244  */
96245 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
96246 
96247 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
96248 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
96249 /*! IPGOFF - Peripheral clock gated off internally
96250  *  0b1..Peripheral clock is gated off.
96251  *  0b0..Peripheral clock is active.
96252  */
96253 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
96254 
96255 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
96256 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
96257 /*! HCKOFF - HCLK gated off internally
96258  *  0b1..HCLK is gated off.
96259  *  0b0..HCLK is active.
96260  */
96261 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
96262 
96263 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
96264 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
96265 /*! PEROFF - IPG_PERCLK gated off internally
96266  *  0b1..IPG_PERCLK is gated off.
96267  *  0b0..IPG_PERCLK is active.
96268  */
96269 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
96270 
96271 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
96272 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
96273 /*! SDOFF - SD clock gated off internally
96274  *  0b1..SD clock is gated off.
96275  *  0b0..SD clock is active.
96276  */
96277 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
96278 
96279 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
96280 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
96281 /*! WTA - Write transfer active
96282  *  0b1..Transferring data
96283  *  0b0..No valid data
96284  */
96285 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
96286 
96287 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
96288 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
96289 /*! RTA - Read transfer active
96290  *  0b1..Transferring data
96291  *  0b0..No valid data
96292  */
96293 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
96294 
96295 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
96296 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
96297 /*! BWEN - Buffer write enable
96298  *  0b1..Write enable
96299  *  0b0..Write disable
96300  */
96301 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
96302 
96303 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
96304 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
96305 /*! BREN - Buffer read enable
96306  *  0b1..Read enable
96307  *  0b0..Read disable
96308  */
96309 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
96310 
96311 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
96312 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
96313 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)
96314  *  0b1..Sampling clock needs re-tuning
96315  *  0b0..Fixed or well tuned sampling clock
96316  */
96317 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
96318 
96319 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
96320 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
96321 /*! TSCD - Tap select change done
96322  *  0b1..Delay cell select change is finished.
96323  *  0b0..Delay cell select change is not finished.
96324  */
96325 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
96326 
96327 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
96328 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
96329 /*! CINST - Card inserted
96330  *  0b1..Card inserted
96331  *  0b0..Power on reset or no card
96332  */
96333 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
96334 
96335 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
96336 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
96337 /*! CDPL - Card detect pin level
96338  *  0b1..Card present (CD_B = 0)
96339  *  0b0..No card present (CD_B = 1)
96340  */
96341 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
96342 
96343 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
96344 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
96345 /*! WPSPL - Write protect switch pin level
96346  *  0b1..Write enabled (WP = 0)
96347  *  0b0..Write protected (WP = 1)
96348  */
96349 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
96350 
96351 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
96352 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
96353 /*! CLSL - CMD line signal level */
96354 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
96355 
96356 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
96357 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
96358 /*! DLSL - DATA[7:0] line signal level
96359  *  0b00000111..Data 7 line signal level
96360  *  0b00000110..Data 6 line signal level
96361  *  0b00000101..Data 5 line signal level
96362  *  0b00000100..Data 4 line signal level
96363  *  0b00000011..Data 3 line signal level
96364  *  0b00000010..Data 2 line signal level
96365  *  0b00000001..Data 1 line signal level
96366  *  0b00000000..Data 0 line signal level
96367  */
96368 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
96369 /*! @} */
96370 
96371 /*! @name PROT_CTRL - Protocol Control */
96372 /*! @{ */
96373 
96374 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
96375 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
96376 /*! DTW - Data transfer width
96377  *  0b10..8-bit mode
96378  *  0b01..4-bit mode
96379  *  0b00..1-bit mode
96380  *  0b11..Reserved
96381  */
96382 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
96383 
96384 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
96385 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
96386 /*! D3CD - DATA3 as card detection pin
96387  *  0b1..DATA3 as card detection pin
96388  *  0b0..DATA3 does not monitor card insertion
96389  */
96390 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
96391 
96392 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
96393 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
96394 /*! EMODE - Endian mode
96395  *  0b00..Big endian mode
96396  *  0b01..Half word big endian mode
96397  *  0b10..Little endian mode
96398  *  0b11..Reserved
96399  */
96400 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
96401 
96402 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
96403 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
96404 /*! CDTL - Card detect test level
96405  *  0b1..Card detect test level is 1, card inserted
96406  *  0b0..Card detect test level is 0, no card inserted
96407  */
96408 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
96409 
96410 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
96411 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
96412 /*! CDSS - Card detect signal selection
96413  *  0b1..Card detection test level is selected (for test purpose).
96414  *  0b0..Card detection level is selected (for normal purpose).
96415  */
96416 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
96417 
96418 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
96419 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
96420 /*! DMASEL - DMA select
96421  *  0b00..No DMA or simple DMA is selected.
96422  *  0b01..ADMA1 is selected.
96423  *  0b10..ADMA2 is selected.
96424  *  0b11..Reserved
96425  */
96426 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
96427 
96428 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
96429 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
96430 /*! SABGREQ - Stop at block gap request
96431  *  0b1..Stop
96432  *  0b0..Transfer
96433  */
96434 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
96435 
96436 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
96437 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
96438 /*! CREQ - Continue request
96439  *  0b1..Restart
96440  *  0b0..No effect
96441  */
96442 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
96443 
96444 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
96445 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
96446 /*! RWCTL - Read wait control
96447  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
96448  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
96449  */
96450 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
96451 
96452 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
96453 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
96454 /*! IABG - Interrupt at block gap
96455  *  0b1..Enables interrupt at block gap
96456  *  0b0..Disables interrupt at block gap
96457  */
96458 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
96459 
96460 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
96461 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
96462 /*! RD_DONE_NO_8CLK - Read performed number 8 clock */
96463 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
96464 
96465 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
96466 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
96467 /*! WECINT - Wakeup event enable on card interrupt
96468  *  0b1..Enables wakeup event enable on card interrupt
96469  *  0b0..Disables wakeup event enable on card interrupt
96470  */
96471 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
96472 
96473 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
96474 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
96475 /*! WECINS - Wakeup event enable on SD card insertion
96476  *  0b1..Enable wakeup event enable on SD card insertion
96477  *  0b0..Disable wakeup event enable on SD card insertion
96478  */
96479 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
96480 
96481 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
96482 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
96483 /*! WECRM - Wakeup event enable on SD card removal
96484  *  0b1..Enables wakeup event enable on SD card removal
96485  *  0b0..Disables wakeup event enable on SD card removal
96486  */
96487 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
96488 
96489 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
96490 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
96491 /*! NON_EXACT_BLK_RD - Non-exact block read
96492  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
96493  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
96494  */
96495 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
96496 /*! @} */
96497 
96498 /*! @name SYS_CTRL - System Control */
96499 /*! @{ */
96500 
96501 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
96502 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
96503 /*! DVS - Divisor
96504  *  0b0000..Divide-by-1
96505  *  0b0001..Divide-by-2
96506  *  0b1110..Divide-by-15
96507  *  0b1111..Divide-by-16
96508  */
96509 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
96510 
96511 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
96512 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
96513 /*! SDCLKFS - SDCLK frequency select */
96514 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
96515 
96516 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
96517 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
96518 /*! DTOCV - Data timeout counter value
96519  *  0b1111..SDCLK x 2 31 recommend to use for HS400 mode
96520  *  0b1110..SDCLK x 2 30 recommend to use for HS200/SDR104 mode
96521  *  0b1101..SDCLK x 2 29 recommend to use for other speed mode except HS400/HS200/SDR104 mode
96522  *  0b0011..SDCLK x 2 19
96523  *  0b0010..SDCLK x 2 18
96524  *  0b0001..SDCLK x 2 33
96525  *  0b0000..SDCLK x 2 32
96526  */
96527 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
96528 
96529 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
96530 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
96531 /*! IPP_RST_N - Hardware reset */
96532 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
96533 
96534 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
96535 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
96536 /*! RSTA - Software reset for all
96537  *  0b1..Reset
96538  *  0b0..No reset
96539  */
96540 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
96541 
96542 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
96543 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
96544 /*! RSTC - Software reset for CMD line
96545  *  0b1..Reset
96546  *  0b0..No reset
96547  */
96548 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
96549 
96550 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
96551 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
96552 /*! RSTD - Software reset for data line
96553  *  0b1..Reset
96554  *  0b0..No reset
96555  */
96556 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
96557 
96558 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
96559 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
96560 /*! INITA - Initialization active */
96561 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
96562 
96563 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
96564 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
96565 /*! RSTT - Reset tuning */
96566 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
96567 /*! @} */
96568 
96569 /*! @name INT_STATUS - Interrupt Status */
96570 /*! @{ */
96571 
96572 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
96573 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
96574 /*! CC - Command complete
96575  *  0b1..Command complete
96576  *  0b0..Command not complete
96577  */
96578 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
96579 
96580 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
96581 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
96582 /*! TC - Transfer complete
96583  *  0b1..Transfer complete
96584  *  0b0..Transfer does not complete
96585  */
96586 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
96587 
96588 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
96589 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
96590 /*! BGE - Block gap event
96591  *  0b1..Transaction stopped at block gap
96592  *  0b0..No block gap event
96593  */
96594 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
96595 
96596 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
96597 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
96598 /*! DINT - DMA interrupt
96599  *  0b1..DMA interrupt is generated.
96600  *  0b0..No DMA interrupt
96601  */
96602 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
96603 
96604 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
96605 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
96606 /*! BWR - Buffer write ready
96607  *  0b1..Ready to write buffer
96608  *  0b0..Not ready to write buffer
96609  */
96610 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
96611 
96612 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
96613 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
96614 /*! BRR - Buffer read ready
96615  *  0b1..Ready to read buffer
96616  *  0b0..Not ready to read buffer
96617  */
96618 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
96619 
96620 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
96621 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
96622 /*! CINS - Card insertion
96623  *  0b1..Card inserted
96624  *  0b0..Card state unstable or removed
96625  */
96626 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
96627 
96628 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
96629 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
96630 /*! CRM - Card removal
96631  *  0b1..Card removed
96632  *  0b0..Card state unstable or inserted
96633  */
96634 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
96635 
96636 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
96637 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
96638 /*! CINT - Card interrupt
96639  *  0b1..Generate card interrupt
96640  *  0b0..No card interrupt
96641  */
96642 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
96643 
96644 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
96645 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
96646 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
96647  *  0b1..Re-tuning should be performed.
96648  *  0b0..Re-tuning is not required.
96649  */
96650 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
96651 
96652 #define USDHC_INT_STATUS_TP_MASK                 (0x2000U)
96653 #define USDHC_INT_STATUS_TP_SHIFT                (13U)
96654 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) */
96655 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
96656 
96657 #define USDHC_INT_STATUS_CQI_MASK                (0x4000U)
96658 #define USDHC_INT_STATUS_CQI_SHIFT               (14U)
96659 /*! CQI - Command queuing interrupt */
96660 #define USDHC_INT_STATUS_CQI(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)
96661 
96662 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
96663 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
96664 /*! CTOE - Command timeout error
96665  *  0b1..Time out
96666  *  0b0..No error
96667  */
96668 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
96669 
96670 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
96671 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
96672 /*! CCE - Command CRC error
96673  *  0b1..CRC error generated
96674  *  0b0..No error
96675  */
96676 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
96677 
96678 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
96679 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
96680 /*! CEBE - Command end bit error
96681  *  0b1..End bit error generated
96682  *  0b0..No error
96683  */
96684 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
96685 
96686 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
96687 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
96688 /*! CIE - Command index error
96689  *  0b1..Error
96690  *  0b0..No error
96691  */
96692 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
96693 
96694 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
96695 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
96696 /*! DTOE - Data timeout error
96697  *  0b1..Time out
96698  *  0b0..No error
96699  */
96700 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
96701 
96702 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
96703 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
96704 /*! DCE - Data CRC error
96705  *  0b1..Error
96706  *  0b0..No error
96707  */
96708 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
96709 
96710 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
96711 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
96712 /*! DEBE - Data end bit error
96713  *  0b1..Error
96714  *  0b0..No error
96715  */
96716 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
96717 
96718 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
96719 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
96720 /*! AC12E - Auto CMD12 error
96721  *  0b1..Error
96722  *  0b0..No error
96723  */
96724 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
96725 
96726 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
96727 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
96728 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) */
96729 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
96730 
96731 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
96732 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
96733 /*! DMAE - DMA error
96734  *  0b1..Error
96735  *  0b0..No error
96736  */
96737 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
96738 /*! @} */
96739 
96740 /*! @name INT_STATUS_EN - Interrupt Status Enable */
96741 /*! @{ */
96742 
96743 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
96744 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
96745 /*! CCSEN - Command complete status enable
96746  *  0b1..Enabled
96747  *  0b0..Masked
96748  */
96749 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
96750 
96751 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
96752 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
96753 /*! TCSEN - Transfer complete status enable
96754  *  0b1..Enabled
96755  *  0b0..Masked
96756  */
96757 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
96758 
96759 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
96760 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
96761 /*! BGESEN - Block gap event status enable
96762  *  0b1..Enabled
96763  *  0b0..Masked
96764  */
96765 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
96766 
96767 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
96768 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
96769 /*! DINTSEN - DMA interrupt status enable
96770  *  0b1..Enabled
96771  *  0b0..Masked
96772  */
96773 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
96774 
96775 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
96776 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
96777 /*! BWRSEN - Buffer write ready status enable
96778  *  0b1..Enabled
96779  *  0b0..Masked
96780  */
96781 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
96782 
96783 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
96784 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
96785 /*! BRRSEN - Buffer read ready status enable
96786  *  0b1..Enabled
96787  *  0b0..Masked
96788  */
96789 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
96790 
96791 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
96792 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
96793 /*! CINSSEN - Card insertion status enable
96794  *  0b1..Enabled
96795  *  0b0..Masked
96796  */
96797 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
96798 
96799 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
96800 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
96801 /*! CRMSEN - Card removal status enable
96802  *  0b1..Enabled
96803  *  0b0..Masked
96804  */
96805 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
96806 
96807 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
96808 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
96809 /*! CINTSEN - Card interrupt status enable
96810  *  0b1..Enabled
96811  *  0b0..Masked
96812  */
96813 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
96814 
96815 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
96816 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
96817 /*! RTESEN - Re-tuning event status enable
96818  *  0b1..Enabled
96819  *  0b0..Masked
96820  */
96821 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
96822 
96823 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x2000U)
96824 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (13U)
96825 /*! TPSEN - Tuning pass status enable
96826  *  0b1..Enabled
96827  *  0b0..Masked
96828  */
96829 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
96830 
96831 #define USDHC_INT_STATUS_EN_CQISEN_MASK          (0x4000U)
96832 #define USDHC_INT_STATUS_EN_CQISEN_SHIFT         (14U)
96833 /*! CQISEN - Command queuing status enable
96834  *  0b1..Enabled
96835  *  0b0..Masked
96836  */
96837 #define USDHC_INT_STATUS_EN_CQISEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)
96838 
96839 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
96840 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
96841 /*! CTOESEN - Command timeout error status enable
96842  *  0b1..Enabled
96843  *  0b0..Masked
96844  */
96845 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
96846 
96847 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
96848 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
96849 /*! CCESEN - Command CRC error status enable
96850  *  0b1..Enabled
96851  *  0b0..Masked
96852  */
96853 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
96854 
96855 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
96856 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
96857 /*! CEBESEN - Command end bit error status enable
96858  *  0b1..Enabled
96859  *  0b0..Masked
96860  */
96861 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
96862 
96863 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
96864 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
96865 /*! CIESEN - Command index error status enable
96866  *  0b1..Enabled
96867  *  0b0..Masked
96868  */
96869 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
96870 
96871 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
96872 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
96873 /*! DTOESEN - Data timeout error status enable
96874  *  0b1..Enabled
96875  *  0b0..Masked
96876  */
96877 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
96878 
96879 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
96880 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
96881 /*! DCESEN - Data CRC error status enable
96882  *  0b1..Enabled
96883  *  0b0..Masked
96884  */
96885 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
96886 
96887 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
96888 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
96889 /*! DEBESEN - Data end bit error status enable
96890  *  0b1..Enabled
96891  *  0b0..Masked
96892  */
96893 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
96894 
96895 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
96896 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
96897 /*! AC12ESEN - Auto CMD12 error status enable
96898  *  0b1..Enabled
96899  *  0b0..Masked
96900  */
96901 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
96902 
96903 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
96904 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
96905 /*! TNESEN - Tuning error status enable
96906  *  0b1..Enabled
96907  *  0b0..Masked
96908  */
96909 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
96910 
96911 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
96912 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
96913 /*! DMAESEN - DMA error status enable
96914  *  0b1..Enabled
96915  *  0b0..Masked
96916  */
96917 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
96918 /*! @} */
96919 
96920 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
96921 /*! @{ */
96922 
96923 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
96924 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
96925 /*! CCIEN - Command complete interrupt enable
96926  *  0b1..Enabled
96927  *  0b0..Masked
96928  */
96929 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
96930 
96931 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
96932 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
96933 /*! TCIEN - Transfer complete interrupt enable
96934  *  0b1..Enabled
96935  *  0b0..Masked
96936  */
96937 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
96938 
96939 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
96940 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
96941 /*! BGEIEN - Block gap event interrupt enable
96942  *  0b1..Enabled
96943  *  0b0..Masked
96944  */
96945 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
96946 
96947 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
96948 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
96949 /*! DINTIEN - DMA interrupt enable
96950  *  0b1..Enabled
96951  *  0b0..Masked
96952  */
96953 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
96954 
96955 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
96956 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
96957 /*! BWRIEN - Buffer write ready interrupt enable
96958  *  0b1..Enabled
96959  *  0b0..Masked
96960  */
96961 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
96962 
96963 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
96964 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
96965 /*! BRRIEN - Buffer read ready interrupt enable
96966  *  0b1..Enabled
96967  *  0b0..Masked
96968  */
96969 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
96970 
96971 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
96972 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
96973 /*! CINSIEN - Card insertion interrupt enable
96974  *  0b1..Enabled
96975  *  0b0..Masked
96976  */
96977 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
96978 
96979 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
96980 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
96981 /*! CRMIEN - Card removal interrupt enable
96982  *  0b1..Enabled
96983  *  0b0..Masked
96984  */
96985 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
96986 
96987 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
96988 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
96989 /*! CINTIEN - Card interrupt enable
96990  *  0b1..Enabled
96991  *  0b0..Masked
96992  */
96993 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
96994 
96995 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
96996 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
96997 /*! RTEIEN - Re-tuning event interrupt enable
96998  *  0b1..Enabled
96999  *  0b0..Masked
97000  */
97001 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
97002 
97003 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x2000U)
97004 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (13U)
97005 /*! TPIEN - Tuning pass interrupt enable
97006  *  0b1..Enabled
97007  *  0b0..Masked
97008  */
97009 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
97010 
97011 #define USDHC_INT_SIGNAL_EN_CQIIEN_MASK          (0x4000U)
97012 #define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT         (14U)
97013 /*! CQIIEN - Command queuing signal enable
97014  *  0b1..Enabled
97015  *  0b0..Masked
97016  */
97017 #define USDHC_INT_SIGNAL_EN_CQIIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)
97018 
97019 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
97020 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
97021 /*! CTOEIEN - Command timeout error interrupt enable
97022  *  0b1..Enabled
97023  *  0b0..Masked
97024  */
97025 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
97026 
97027 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
97028 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
97029 /*! CCEIEN - Command CRC error interrupt enable
97030  *  0b1..Enabled
97031  *  0b0..Masked
97032  */
97033 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
97034 
97035 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
97036 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
97037 /*! CEBEIEN - Command end bit error interrupt enable
97038  *  0b1..Enabled
97039  *  0b0..Masked
97040  */
97041 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
97042 
97043 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
97044 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
97045 /*! CIEIEN - Command index error interrupt enable
97046  *  0b1..Enabled
97047  *  0b0..Masked
97048  */
97049 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
97050 
97051 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
97052 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
97053 /*! DTOEIEN - Data timeout error interrupt enable
97054  *  0b1..Enabled
97055  *  0b0..Masked
97056  */
97057 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
97058 
97059 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
97060 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
97061 /*! DCEIEN - Data CRC error interrupt enable
97062  *  0b1..Enabled
97063  *  0b0..Masked
97064  */
97065 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
97066 
97067 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
97068 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
97069 /*! DEBEIEN - Data end bit error interrupt enable
97070  *  0b1..Enabled
97071  *  0b0..Masked
97072  */
97073 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
97074 
97075 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
97076 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
97077 /*! AC12EIEN - Auto CMD12 error interrupt enable
97078  *  0b1..Enabled
97079  *  0b0..Masked
97080  */
97081 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
97082 
97083 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
97084 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
97085 /*! TNEIEN - Tuning error interrupt enable
97086  *  0b1..Enabled
97087  *  0b0..Masked
97088  */
97089 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
97090 
97091 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
97092 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
97093 /*! DMAEIEN - DMA error interrupt enable
97094  *  0b1..Enable
97095  *  0b0..Masked
97096  */
97097 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
97098 /*! @} */
97099 
97100 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
97101 /*! @{ */
97102 
97103 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
97104 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
97105 /*! AC12NE - Auto CMD12 not executed
97106  *  0b1..Not executed
97107  *  0b0..Executed
97108  */
97109 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
97110 
97111 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
97112 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
97113 /*! AC12TOE - Auto CMD12 / 23 timeout error
97114  *  0b1..Time out
97115  *  0b0..No error
97116  */
97117 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
97118 
97119 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
97120 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
97121 /*! AC12EBE - Auto CMD12 / 23 end bit error
97122  *  0b1..End bit error generated
97123  *  0b0..No error
97124  */
97125 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
97126 
97127 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
97128 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
97129 /*! AC12CE - Auto CMD12 / 23 CRC error
97130  *  0b1..CRC error met in Auto CMD12/23 response
97131  *  0b0..No CRC error
97132  */
97133 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
97134 
97135 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
97136 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
97137 /*! AC12IE - Auto CMD12 / 23 index error
97138  *  0b1..Error, the CMD index in response is not CMD12/23
97139  *  0b0..No error
97140  */
97141 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
97142 
97143 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
97144 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
97145 /*! CNIBAC12E - Command not issued by Auto CMD12 error
97146  *  0b1..Not issued
97147  *  0b0..No error
97148  */
97149 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
97150 
97151 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
97152 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
97153 /*! EXECUTE_TUNING - Execute tuning
97154  *  0b1..Start tuning procedure
97155  *  0b0..Tuning procedure is aborted
97156  */
97157 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
97158 
97159 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
97160 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
97161 /*! SMP_CLK_SEL - Sample clock select
97162  *  0b1..Tuned clock is used to sample data
97163  *  0b0..Fixed clock is used to sample data
97164  */
97165 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
97166 /*! @} */
97167 
97168 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
97169 /*! @{ */
97170 
97171 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
97172 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
97173 /*! SDR50_SUPPORT - SDR50 support */
97174 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
97175 
97176 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
97177 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
97178 /*! SDR104_SUPPORT - SDR104 support */
97179 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
97180 
97181 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
97182 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
97183 /*! DDR50_SUPPORT - DDR50 support */
97184 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
97185 
97186 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
97187 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
97188 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
97189  *  0b1..SDR50 supports tuning
97190  *  0b0..SDR50 does not support tuning
97191  */
97192 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
97193 
97194 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
97195 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
97196 /*! MBL - Max block length
97197  *  0b000..512 bytes
97198  *  0b001..1024 bytes
97199  *  0b010..2048 bytes
97200  *  0b011..4096 bytes
97201  */
97202 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
97203 
97204 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
97205 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
97206 /*! ADMAS - ADMA support
97207  *  0b1..Advanced DMA supported
97208  *  0b0..Advanced DMA not supported
97209  */
97210 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
97211 
97212 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
97213 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
97214 /*! HSS - High speed support
97215  *  0b1..High speed supported
97216  *  0b0..High speed not supported
97217  */
97218 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
97219 
97220 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
97221 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
97222 /*! DMAS - DMA support
97223  *  0b1..DMA supported
97224  *  0b0..DMA not supported
97225  */
97226 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
97227 
97228 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
97229 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
97230 /*! SRS - Suspend / resume support
97231  *  0b1..Supported
97232  *  0b0..Not supported
97233  */
97234 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
97235 
97236 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
97237 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
97238 /*! VS33 - Voltage support 3.3 V
97239  *  0b1..3.3 V supported
97240  *  0b0..3.3 V not supported
97241  */
97242 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
97243 
97244 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
97245 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
97246 /*! VS30 - Voltage support 3.0 V
97247  *  0b1..3.0 V supported
97248  *  0b0..3.0 V not supported
97249  */
97250 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
97251 
97252 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
97253 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
97254 /*! VS18 - Voltage support 1.8 V
97255  *  0b1..1.8 V supported
97256  *  0b0..1.8 V not supported
97257  */
97258 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
97259 /*! @} */
97260 
97261 /*! @name WTMK_LVL - Watermark Level */
97262 /*! @{ */
97263 
97264 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
97265 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
97266 /*! RD_WML - Read watermark level */
97267 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
97268 
97269 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
97270 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
97271 /*! WR_WML - Write watermark level */
97272 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
97273 /*! @} */
97274 
97275 /*! @name MIX_CTRL - Mixer Control */
97276 /*! @{ */
97277 
97278 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
97279 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
97280 /*! DMAEN - DMA enable
97281  *  0b1..Enable
97282  *  0b0..Disable
97283  */
97284 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
97285 
97286 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
97287 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
97288 /*! BCEN - Block count enable
97289  *  0b1..Enable
97290  *  0b0..Disable
97291  */
97292 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
97293 
97294 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
97295 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
97296 /*! AC12EN - Auto CMD12 enable
97297  *  0b1..Enable
97298  *  0b0..Disable
97299  */
97300 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
97301 
97302 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
97303 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
97304 /*! DDR_EN - Dual data rate mode selection */
97305 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
97306 
97307 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
97308 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
97309 /*! DTDSEL - Data transfer direction select
97310  *  0b1..Read (Card to host)
97311  *  0b0..Write (Host to card)
97312  */
97313 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
97314 
97315 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
97316 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
97317 /*! MSBSEL - Multi / Single block select
97318  *  0b1..Multiple blocks
97319  *  0b0..Single block
97320  */
97321 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
97322 
97323 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
97324 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
97325 /*! NIBBLE_POS - Nibble position indication */
97326 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
97327 
97328 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
97329 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
97330 /*! AC23EN - Auto CMD23 enable */
97331 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
97332 
97333 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
97334 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
97335 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
97336  *  0b1..Execute tuning
97337  *  0b0..Not tuned or tuning completed
97338  */
97339 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
97340 
97341 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
97342 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
97343 /*! SMP_CLK_SEL - Clock selection
97344  *  0b1..Tuned clock is used to sample data / cmd
97345  *  0b0..Fixed clock is used to sample data / cmd
97346  */
97347 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
97348 
97349 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
97350 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
97351 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
97352  *  0b1..Enable auto tuning
97353  *  0b0..Disable auto tuning
97354  */
97355 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
97356 
97357 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
97358 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
97359 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
97360  *  0b1..Feedback clock comes from the ipp_card_clk_out
97361  *  0b0..Feedback clock comes from the loopback CLK
97362  */
97363 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
97364 
97365 #define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
97366 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
97367 /*! HS400_MODE - Enable HS400 mode */
97368 #define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
97369 
97370 #define USDHC_MIX_CTRL_EN_HS400_MODE_MASK        (0x8000000U)
97371 #define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT       (27U)
97372 /*! EN_HS400_MODE - Enable enhance HS400 mode */
97373 #define USDHC_MIX_CTRL_EN_HS400_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
97374 /*! @} */
97375 
97376 /*! @name FORCE_EVENT - Force Event */
97377 /*! @{ */
97378 
97379 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
97380 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
97381 /*! FEVTAC12NE - Force event auto command 12 not executed */
97382 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
97383 
97384 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
97385 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
97386 /*! FEVTAC12TOE - Force event auto command 12 time out error */
97387 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
97388 
97389 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
97390 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
97391 /*! FEVTAC12CE - Force event auto command 12 CRC error */
97392 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
97393 
97394 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
97395 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
97396 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */
97397 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
97398 
97399 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
97400 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
97401 /*! FEVTAC12IE - Force event Auto Command 12 index error */
97402 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
97403 
97404 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
97405 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
97406 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */
97407 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
97408 
97409 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
97410 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
97411 /*! FEVTCTOE - Force event command time out error */
97412 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
97413 
97414 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
97415 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
97416 /*! FEVTCCE - Force event command CRC error */
97417 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
97418 
97419 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
97420 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
97421 /*! FEVTCEBE - Force event command end bit error */
97422 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
97423 
97424 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
97425 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
97426 /*! FEVTCIE - Force event command index error */
97427 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
97428 
97429 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
97430 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
97431 /*! FEVTDTOE - Force event data time out error */
97432 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
97433 
97434 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
97435 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
97436 /*! FEVTDCE - Force event data CRC error */
97437 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
97438 
97439 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
97440 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
97441 /*! FEVTDEBE - Force event data end bit error */
97442 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
97443 
97444 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
97445 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
97446 /*! FEVTAC12E - Force event Auto Command 12 error */
97447 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
97448 
97449 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
97450 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
97451 /*! FEVTTNE - Force tuning error */
97452 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
97453 
97454 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
97455 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
97456 /*! FEVTDMAE - Force event DMA error */
97457 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
97458 
97459 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
97460 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
97461 /*! FEVTCINT - Force event card interrupt */
97462 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
97463 /*! @} */
97464 
97465 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
97466 /*! @{ */
97467 
97468 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
97469 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
97470 /*! ADMAES - ADMA error state (when ADMA error is occurred) */
97471 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
97472 
97473 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
97474 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
97475 /*! ADMALME - ADMA length mismatch error
97476  *  0b1..Error
97477  *  0b0..No error
97478  */
97479 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
97480 
97481 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
97482 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
97483 /*! ADMADCE - ADMA descriptor error
97484  *  0b1..Error
97485  *  0b0..No error
97486  */
97487 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
97488 /*! @} */
97489 
97490 /*! @name ADMA_SYS_ADDR - ADMA System Address */
97491 /*! @{ */
97492 
97493 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
97494 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
97495 /*! ADS_ADDR - ADMA system address */
97496 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
97497 /*! @} */
97498 
97499 /*! @name DLL_CTRL - DLL (Delay Line) Control */
97500 /*! @{ */
97501 
97502 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
97503 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
97504 /*! DLL_CTRL_ENABLE - DLL and delay chain */
97505 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
97506 
97507 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
97508 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
97509 /*! DLL_CTRL_RESET - DLL reset */
97510 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
97511 
97512 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
97513 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
97514 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */
97515 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
97516 
97517 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
97518 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
97519 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */
97520 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
97521 
97522 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
97523 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
97524 /*! DLL_CTRL_GATE_UPDATE - DLL gate update */
97525 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
97526 
97527 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
97528 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
97529 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */
97530 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
97531 
97532 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
97533 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
97534 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */
97535 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
97536 
97537 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
97538 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
97539 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */
97540 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
97541 
97542 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
97543 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
97544 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */
97545 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
97546 
97547 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
97548 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
97549 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */
97550 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
97551 /*! @} */
97552 
97553 /*! @name DLL_STATUS - DLL Status */
97554 /*! @{ */
97555 
97556 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
97557 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
97558 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */
97559 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
97560 
97561 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
97562 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
97563 /*! DLL_STS_REF_LOCK - Reference DLL lock status */
97564 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
97565 
97566 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
97567 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
97568 /*! DLL_STS_SLV_SEL - Slave delay line select status */
97569 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
97570 
97571 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
97572 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
97573 /*! DLL_STS_REF_SEL - Reference delay line select taps */
97574 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
97575 /*! @} */
97576 
97577 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
97578 /*! @{ */
97579 
97580 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
97581 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
97582 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */
97583 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
97584 
97585 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
97586 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
97587 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */
97588 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
97589 
97590 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
97591 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
97592 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */
97593 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
97594 
97595 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
97596 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
97597 /*! NXT_ERR - NXT error */
97598 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
97599 
97600 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
97601 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
97602 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */
97603 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
97604 
97605 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
97606 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
97607 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */
97608 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
97609 
97610 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
97611 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
97612 /*! TAP_SEL_PRE - TAP_SEL_PRE */
97613 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
97614 
97615 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
97616 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
97617 /*! PRE_ERR - PRE error */
97618 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
97619 /*! @} */
97620 
97621 /*! @name STROBE_DLL_CTRL - Strobe DLL control */
97622 /*! @{ */
97623 
97624 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
97625 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
97626 /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */
97627 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
97628 
97629 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
97630 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
97631 /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */
97632 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
97633 
97634 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
97635 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
97636 /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */
97637 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
97638 
97639 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
97640 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
97641 /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */
97642 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
97643 
97644 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
97645 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
97646 /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */
97647 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
97648 
97649 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
97650 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
97651 /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */
97652 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
97653 
97654 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
97655 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
97656 /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */
97657 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
97658 
97659 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
97660 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
97661 /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */
97662 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
97663 
97664 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
97665 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
97666 /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */
97667 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
97668 /*! @} */
97669 
97670 /*! @name STROBE_DLL_STATUS - Strobe DLL status */
97671 /*! @{ */
97672 
97673 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
97674 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
97675 /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */
97676 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
97677 
97678 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
97679 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
97680 /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */
97681 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
97682 
97683 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
97684 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
97685 /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */
97686 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
97687 
97688 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
97689 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
97690 /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */
97691 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
97692 /*! @} */
97693 
97694 /*! @name VEND_SPEC - Vendor Specific Register */
97695 /*! @{ */
97696 
97697 #define USDHC_VEND_SPEC_EXT_DMA_EN_MASK          (0x1U)
97698 #define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT         (0U)
97699 /*! EXT_DMA_EN - External DMA request enable
97700  *  0b0..In any scenario, uSDHC does not send out external DMA request.
97701  *  0b1..When internal DMA is not active, the external DMA request is sent out.
97702  */
97703 #define USDHC_VEND_SPEC_EXT_DMA_EN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK)
97704 
97705 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
97706 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
97707 /*! VSELECT - Voltage selection
97708  *  0b1..Change the voltage to low voltage range, around 1.8 V
97709  *  0b0..Change the voltage to high voltage range, around 3.0 V
97710  */
97711 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
97712 
97713 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
97714 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
97715 /*! CONFLICT_CHK_EN - Conflict check enable
97716  *  0b0..Conflict check disable
97717  *  0b1..Conflict check enable
97718  */
97719 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
97720 
97721 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
97722 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
97723 /*! AC12_WR_CHKBUSY_EN - Check busy enable
97724  *  0b0..Do not check busy after auto CMD12 for write data packet
97725  *  0b1..Check busy after auto CMD12 for write data packet
97726  */
97727 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
97728 
97729 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
97730 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
97731 /*! FRC_SDCLK_ON - Force CLK
97732  *  0b0..CLK active or inactive is fully controlled by the hardware.
97733  *  0b1..Force CLK active
97734  */
97735 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
97736 
97737 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
97738 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
97739 /*! CRC_CHK_DIS - CRC Check Disable
97740  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
97741  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
97742  */
97743 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
97744 
97745 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
97746 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
97747 /*! CMD_BYTE_EN - Byte access
97748  *  0b0..Disable
97749  *  0b1..Enable
97750  */
97751 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
97752 /*! @} */
97753 
97754 /*! @name MMC_BOOT - MMC Boot */
97755 /*! @{ */
97756 
97757 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
97758 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
97759 /*! DTOCV_ACK - DTOCV_ACK
97760  *  0b0000..SDCLK x 2^32
97761  *  0b0001..SDCLK x 2^33
97762  *  0b0010..SDCLK x 2^18
97763  *  0b0011..SDCLK x 2^19
97764  *  0b0100..SDCLK x 2^20
97765  *  0b0101..SDCLK x 2^21
97766  *  0b0110..SDCLK x 2^22
97767  *  0b0111..SDCLK x 2^23
97768  *  0b1110..SDCLK x 2^30
97769  *  0b1111..SDCLK x 2^31
97770  */
97771 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
97772 
97773 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
97774 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
97775 /*! BOOT_ACK - BOOT ACK
97776  *  0b0..No ack
97777  *  0b1..Ack
97778  */
97779 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
97780 
97781 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
97782 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
97783 /*! BOOT_MODE - Boot mode
97784  *  0b0..Normal boot
97785  *  0b1..Alternative boot
97786  */
97787 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
97788 
97789 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
97790 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
97791 /*! BOOT_EN - Boot enable
97792  *  0b0..Fast boot disable
97793  *  0b1..Fast boot enable
97794  */
97795 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
97796 
97797 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
97798 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
97799 /*! AUTO_SABG_EN - Auto stop at block gap */
97800 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
97801 
97802 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
97803 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
97804 /*! DISABLE_TIME_OUT - Time out
97805  *  0b0..Enable time out
97806  *  0b1..Disable time out
97807  */
97808 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
97809 
97810 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
97811 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
97812 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */
97813 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
97814 /*! @} */
97815 
97816 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
97817 /*! @{ */
97818 
97819 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
97820 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
97821 /*! CARD_INT_D3_TEST - Card interrupt detection test
97822  *  0b0..Check the card interrupt only when DATA3 is high.
97823  *  0b1..Check the card interrupt by ignoring the status of DATA3.
97824  */
97825 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
97826 
97827 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
97828 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
97829 /*! TUNING_8bit_EN - Tuning 8bit enable */
97830 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
97831 
97832 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
97833 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
97834 /*! TUNING_1bit_EN - Tuning 1bit enable */
97835 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
97836 
97837 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
97838 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
97839 /*! TUNING_CMD_EN - Tuning command enable
97840  *  0b0..Auto tuning circuit does not check the CMD line.
97841  *  0b1..Auto tuning circuit checks the CMD line.
97842  */
97843 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
97844 
97845 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
97846 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
97847 /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */
97848 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
97849 
97850 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
97851 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
97852 /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */
97853 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
97854 
97855 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
97856 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
97857 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
97858  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
97859  *  0b0..Disable
97860  */
97861 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
97862 
97863 #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
97864 #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
97865 /*! EN_32K_CLK - Enable 32khz clock for card detection */
97866 #define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)
97867 
97868 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK      (0xFFFF0000U)
97869 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT     (16U)
97870 /*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */
97871 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
97872 /*! @} */
97873 
97874 /*! @name TUNING_CTRL - Tuning Control */
97875 /*! @{ */
97876 
97877 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
97878 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
97879 /*! TUNING_START_TAP - Tuning start */
97880 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
97881 
97882 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
97883 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
97884 /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */
97885 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
97886 
97887 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
97888 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
97889 /*! TUNING_COUNTER - Tuning counter */
97890 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
97891 
97892 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
97893 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
97894 /*! TUNING_STEP - TUNING_STEP */
97895 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
97896 
97897 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
97898 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
97899 /*! TUNING_WINDOW - Data window */
97900 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
97901 
97902 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
97903 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
97904 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */
97905 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
97906 /*! @} */
97907 
97908 /*! @name CQVER - Command Queuing Version */
97909 /*! @{ */
97910 
97911 #define USDHC_CQVER_VERSION_SUFFIX_MASK          (0xFU)
97912 #define USDHC_CQVER_VERSION_SUFFIX_SHIFT         (0U)
97913 /*! VERSION_SUFFIX - e •MMC version suffix */
97914 #define USDHC_CQVER_VERSION_SUFFIX(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK)
97915 
97916 #define USDHC_CQVER_MINOR_VN_MASK                (0xF0U)
97917 #define USDHC_CQVER_MINOR_VN_SHIFT               (4U)
97918 /*! MINOR_VN - e •MMC minor version number */
97919 #define USDHC_CQVER_MINOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK)
97920 
97921 #define USDHC_CQVER_MAJOR_VN_MASK                (0xF00U)
97922 #define USDHC_CQVER_MAJOR_VN_SHIFT               (8U)
97923 /*! MAJOR_VN - e •MMC major version number */
97924 #define USDHC_CQVER_MAJOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK)
97925 /*! @} */
97926 
97927 /*! @name CQCAP - Command Queuing Capabilities */
97928 /*! @{ */
97929 
97930 #define USDHC_CQCAP_ITCFVAL_MASK                 (0x3FFU)
97931 #define USDHC_CQCAP_ITCFVAL_SHIFT                (0U)
97932 /*! ITCFVAL - Internal timer clock frequency value */
97933 #define USDHC_CQCAP_ITCFVAL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK)
97934 
97935 #define USDHC_CQCAP_ITCFMUL_MASK                 (0xF000U)
97936 #define USDHC_CQCAP_ITCFMUL_SHIFT                (12U)
97937 /*! ITCFMUL - Internal timer clock frequency multiplier
97938  *  0b0001..0.001 MHz
97939  *  0b0010..0.01 MHz
97940  *  0b0011..0.1 MHz
97941  *  0b0100..1 MHz
97942  *  0b0101..10 MHz
97943  *  0b0110-0b1001..Reserved
97944  */
97945 #define USDHC_CQCAP_ITCFMUL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK)
97946 /*! @} */
97947 
97948 /*! @name CQCFG - Command Queuing Configuration */
97949 /*! @{ */
97950 
97951 #define USDHC_CQCFG_CQUE_MASK                    (0x1U)
97952 #define USDHC_CQCFG_CQUE_SHIFT                   (0U)
97953 /*! CQUE - Command queuing enable */
97954 #define USDHC_CQCFG_CQUE(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK)
97955 
97956 #define USDHC_CQCFG_TDS_MASK                     (0x100U)
97957 #define USDHC_CQCFG_TDS_SHIFT                    (8U)
97958 /*! TDS - Task descriptor size
97959  *  0b0..Task descriptor size is 64 bits
97960  *  0b1..Task descriptor size is 128 bits
97961  */
97962 #define USDHC_CQCFG_TDS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK)
97963 
97964 #define USDHC_CQCFG_DCMDE_MASK                   (0x1000U)
97965 #define USDHC_CQCFG_DCMDE_SHIFT                  (12U)
97966 /*! DCMDE - Direct command (DCMD) enable
97967  *  0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor
97968  *  0b1..Task descriptor in slot #31 is a DCMD Task Descriptor
97969  */
97970 #define USDHC_CQCFG_DCMDE(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK)
97971 /*! @} */
97972 
97973 /*! @name CQCTL - Command Queuing Control */
97974 /*! @{ */
97975 
97976 #define USDHC_CQCTL_HALT_MASK                    (0x1U)
97977 #define USDHC_CQCTL_HALT_SHIFT                   (0U)
97978 /*! HALT - Halt */
97979 #define USDHC_CQCTL_HALT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK)
97980 
97981 #define USDHC_CQCTL_CLEAR_MASK                   (0x100U)
97982 #define USDHC_CQCTL_CLEAR_SHIFT                  (8U)
97983 /*! CLEAR - Clear all tasks */
97984 #define USDHC_CQCTL_CLEAR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK)
97985 /*! @} */
97986 
97987 /*! @name CQIS - Command Queuing Interrupt Status */
97988 /*! @{ */
97989 
97990 #define USDHC_CQIS_HAC_MASK                      (0x1U)
97991 #define USDHC_CQIS_HAC_SHIFT                     (0U)
97992 /*! HAC - Halt complete interrupt */
97993 #define USDHC_CQIS_HAC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK)
97994 
97995 #define USDHC_CQIS_TCC_MASK                      (0x2U)
97996 #define USDHC_CQIS_TCC_SHIFT                     (1U)
97997 /*! TCC - Task complete interrupt */
97998 #define USDHC_CQIS_TCC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK)
97999 
98000 #define USDHC_CQIS_RED_MASK                      (0x4U)
98001 #define USDHC_CQIS_RED_SHIFT                     (2U)
98002 /*! RED - Response error detected interrupt */
98003 #define USDHC_CQIS_RED(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK)
98004 
98005 #define USDHC_CQIS_TCL_MASK                      (0x8U)
98006 #define USDHC_CQIS_TCL_SHIFT                     (3U)
98007 /*! TCL - Task cleared */
98008 #define USDHC_CQIS_TCL(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK)
98009 /*! @} */
98010 
98011 /*! @name CQISTE - Command Queuing Interrupt Status Enable */
98012 /*! @{ */
98013 
98014 #define USDHC_CQISTE_HAC_STE_MASK                (0x1U)
98015 #define USDHC_CQISTE_HAC_STE_SHIFT               (0U)
98016 /*! HAC_STE - Halt complete status enable
98017  *  0b0..CQIS[HAC] is disabled
98018  *  0b1..CQIS[HAC] is set when its interrupt condition is active
98019  */
98020 #define USDHC_CQISTE_HAC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK)
98021 
98022 #define USDHC_CQISTE_TCC_STE_MASK                (0x2U)
98023 #define USDHC_CQISTE_TCC_STE_SHIFT               (1U)
98024 /*! TCC_STE - Task complete status enable
98025  *  0b0..CQIS[TCC] is disabled
98026  *  0b1..CQIS[TCC] is set when its interrupt condition is active
98027  */
98028 #define USDHC_CQISTE_TCC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK)
98029 
98030 #define USDHC_CQISTE_RED_STE_MASK                (0x4U)
98031 #define USDHC_CQISTE_RED_STE_SHIFT               (2U)
98032 /*! RED_STE - Response error detected status enable
98033  *  0b0..CQIS[RED] is disabled
98034  *  0b1..CQIS[RED] is set when its interrupt condition is active
98035  */
98036 #define USDHC_CQISTE_RED_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK)
98037 
98038 #define USDHC_CQISTE_TCL_STE_MASK                (0x8U)
98039 #define USDHC_CQISTE_TCL_STE_SHIFT               (3U)
98040 /*! TCL_STE - Task cleared status enable
98041  *  0b0..CQIS[TCL] is disabled
98042  *  0b1..CQIS[TCL] is set when its interrupt condition is active
98043  */
98044 #define USDHC_CQISTE_TCL_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK)
98045 /*! @} */
98046 
98047 /*! @name CQISGE - Command Queuing Interrupt Signal Enable */
98048 /*! @{ */
98049 
98050 #define USDHC_CQISGE_HAC_SGE_MASK                (0x1U)
98051 #define USDHC_CQISGE_HAC_SGE_SHIFT               (0U)
98052 /*! HAC_SGE - Halt complete signal enable */
98053 #define USDHC_CQISGE_HAC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK)
98054 
98055 #define USDHC_CQISGE_TCC_SGE_MASK                (0x2U)
98056 #define USDHC_CQISGE_TCC_SGE_SHIFT               (1U)
98057 /*! TCC_SGE - Task complete signal enable */
98058 #define USDHC_CQISGE_TCC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK)
98059 
98060 #define USDHC_CQISGE_RED_SGE_MASK                (0x4U)
98061 #define USDHC_CQISGE_RED_SGE_SHIFT               (2U)
98062 /*! RED_SGE - Response error detected signal enable */
98063 #define USDHC_CQISGE_RED_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK)
98064 
98065 #define USDHC_CQISGE_TCL_SGE_MASK                (0x8U)
98066 #define USDHC_CQISGE_TCL_SGE_SHIFT               (3U)
98067 /*! TCL_SGE - Task cleared signal enable */
98068 #define USDHC_CQISGE_TCL_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK)
98069 /*! @} */
98070 
98071 /*! @name CQIC - Command Queuing Interrupt Coalescing */
98072 /*! @{ */
98073 
98074 #define USDHC_CQIC_ICTOVAL_MASK                  (0x7FU)
98075 #define USDHC_CQIC_ICTOVAL_SHIFT                 (0U)
98076 /*! ICTOVAL - Interrupt coalescing timeout value */
98077 #define USDHC_CQIC_ICTOVAL(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK)
98078 
98079 #define USDHC_CQIC_ICTOVALWEN_MASK               (0x80U)
98080 #define USDHC_CQIC_ICTOVALWEN_SHIFT              (7U)
98081 /*! ICTOVALWEN - Interrupt coalescing timeout value write enable */
98082 #define USDHC_CQIC_ICTOVALWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK)
98083 
98084 #define USDHC_CQIC_ICCTH_MASK                    (0x1F00U)
98085 #define USDHC_CQIC_ICCTH_SHIFT                   (8U)
98086 /*! ICCTH - Interrupt coalescing counter threshold */
98087 #define USDHC_CQIC_ICCTH(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK)
98088 
98089 #define USDHC_CQIC_ICCTHWEN_MASK                 (0x8000U)
98090 #define USDHC_CQIC_ICCTHWEN_SHIFT                (15U)
98091 /*! ICCTHWEN - Interrupt coalescing counter threshold write enable */
98092 #define USDHC_CQIC_ICCTHWEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK)
98093 
98094 #define USDHC_CQIC_ICCTR_MASK                    (0x10000U)
98095 #define USDHC_CQIC_ICCTR_SHIFT                   (16U)
98096 /*! ICCTR - Counter and timer reset */
98097 #define USDHC_CQIC_ICCTR(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK)
98098 
98099 #define USDHC_CQIC_ICSB_MASK                     (0x100000U)
98100 #define USDHC_CQIC_ICSB_SHIFT                    (20U)
98101 /*! ICSB - Interrupt coalescing status
98102  *  0b0..No task completions have occurred since last counter reset (IC counter =0)
98103  *  0b1..At least one task completion has been counted (IC counter >0)
98104  */
98105 #define USDHC_CQIC_ICSB(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK)
98106 
98107 #define USDHC_CQIC_ICENDIS_MASK                  (0x80000000U)
98108 #define USDHC_CQIC_ICENDIS_SHIFT                 (31U)
98109 /*! ICENDIS - Interrupt coalescing enable/disable */
98110 #define USDHC_CQIC_ICENDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK)
98111 /*! @} */
98112 
98113 /*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */
98114 /*! @{ */
98115 
98116 #define USDHC_CQTDLBA_TDLBA_MASK                 (0xFFFFFFFFU)
98117 #define USDHC_CQTDLBA_TDLBA_SHIFT                (0U)
98118 /*! TDLBA - Task descriptor list base address */
98119 #define USDHC_CQTDLBA_TDLBA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK)
98120 /*! @} */
98121 
98122 /*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */
98123 /*! @{ */
98124 
98125 #define USDHC_CQTDLBAU_TDLBAU_MASK               (0xFFFFFFFFU)
98126 #define USDHC_CQTDLBAU_TDLBAU_SHIFT              (0U)
98127 /*! TDLBAU - Task descriptor list base address */
98128 #define USDHC_CQTDLBAU_TDLBAU(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK)
98129 /*! @} */
98130 
98131 /*! @name CQTDBR - Command Queuing Task Doorbell */
98132 /*! @{ */
98133 
98134 #define USDHC_CQTDBR_TDBR_MASK                   (0xFFFFFFFFU)
98135 #define USDHC_CQTDBR_TDBR_SHIFT                  (0U)
98136 /*! TDBR - Task doorbell */
98137 #define USDHC_CQTDBR_TDBR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK)
98138 /*! @} */
98139 
98140 /*! @name CQTCN - Command Queuing Task Completion Notification */
98141 /*! @{ */
98142 
98143 #define USDHC_CQTCN_TCN_MASK                     (0xFFFFFFFFU)
98144 #define USDHC_CQTCN_TCN_SHIFT                    (0U)
98145 /*! TCN - Task complete notification */
98146 #define USDHC_CQTCN_TCN(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK)
98147 /*! @} */
98148 
98149 /*! @name CQDQS - Command Queuing Device Queue Status */
98150 /*! @{ */
98151 
98152 #define USDHC_CQDQS_DQS_MASK                     (0xFFFFFFFFU)
98153 #define USDHC_CQDQS_DQS_SHIFT                    (0U)
98154 /*! DQS - Device queue status */
98155 #define USDHC_CQDQS_DQS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK)
98156 /*! @} */
98157 
98158 /*! @name CQDPT - Command Queuing Device Pending Tasks */
98159 /*! @{ */
98160 
98161 #define USDHC_CQDPT_DPT_MASK                     (0xFFFFFFFFU)
98162 #define USDHC_CQDPT_DPT_SHIFT                    (0U)
98163 /*! DPT - Device pending tasks */
98164 #define USDHC_CQDPT_DPT(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK)
98165 /*! @} */
98166 
98167 /*! @name CQTCLR - Command Queuing Task Clear */
98168 /*! @{ */
98169 
98170 #define USDHC_CQTCLR_TCLR_MASK                   (0xFFFFFFFFU)
98171 #define USDHC_CQTCLR_TCLR_SHIFT                  (0U)
98172 /*! TCLR - Task clear */
98173 #define USDHC_CQTCLR_TCLR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK)
98174 /*! @} */
98175 
98176 /*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */
98177 /*! @{ */
98178 
98179 #define USDHC_CQSSC1_CIT_MASK                    (0xFFFFU)
98180 #define USDHC_CQSSC1_CIT_SHIFT                   (0U)
98181 /*! CIT - Send status command idle timer */
98182 #define USDHC_CQSSC1_CIT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK)
98183 
98184 #define USDHC_CQSSC1_CBC_MASK                    (0xF0000U)
98185 #define USDHC_CQSSC1_CBC_SHIFT                   (16U)
98186 /*! CBC - Send status command block counter */
98187 #define USDHC_CQSSC1_CBC(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK)
98188 /*! @} */
98189 
98190 /*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */
98191 /*! @{ */
98192 
98193 #define USDHC_CQSSC2_SSC2_MASK                   (0xFFFFU)
98194 #define USDHC_CQSSC2_SSC2_SHIFT                  (0U)
98195 /*! SSC2 - Send queue status RCA */
98196 #define USDHC_CQSSC2_SSC2(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK)
98197 /*! @} */
98198 
98199 /*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */
98200 /*! @{ */
98201 
98202 #define USDHC_CQCRDCT_CRDCT_MASK                 (0xFFFFFFFFU)
98203 #define USDHC_CQCRDCT_CRDCT_SHIFT                (0U)
98204 /*! CRDCT - Direct command last response */
98205 #define USDHC_CQCRDCT_CRDCT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK)
98206 /*! @} */
98207 
98208 /*! @name CQRMEM - Command Queuing Response Mode Error Mask */
98209 /*! @{ */
98210 
98211 #define USDHC_CQRMEM_RMEM_MASK                   (0xFFFFFFFFU)
98212 #define USDHC_CQRMEM_RMEM_SHIFT                  (0U)
98213 /*! RMEM - Response mode error mask
98214  *  0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored
98215  *  0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated
98216  */
98217 #define USDHC_CQRMEM_RMEM(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK)
98218 /*! @} */
98219 
98220 /*! @name CQTERRI - Command Queuing Task Error Information */
98221 /*! @{ */
98222 
98223 #define USDHC_CQTERRI_RMECI_MASK                 (0x3FU)
98224 #define USDHC_CQTERRI_RMECI_SHIFT                (0U)
98225 /*! RMECI - Response mode error command index */
98226 #define USDHC_CQTERRI_RMECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK)
98227 
98228 #define USDHC_CQTERRI_RMETID_MASK                (0x1F00U)
98229 #define USDHC_CQTERRI_RMETID_SHIFT               (8U)
98230 /*! RMETID - Response mode error task ID */
98231 #define USDHC_CQTERRI_RMETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK)
98232 
98233 #define USDHC_CQTERRI_RMEFV_MASK                 (0x8000U)
98234 #define USDHC_CQTERRI_RMEFV_SHIFT                (15U)
98235 /*! RMEFV - Response mode error fields valid */
98236 #define USDHC_CQTERRI_RMEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK)
98237 
98238 #define USDHC_CQTERRI_DTECI_MASK                 (0x3F0000U)
98239 #define USDHC_CQTERRI_DTECI_SHIFT                (16U)
98240 /*! DTECI - Data transfer error command index */
98241 #define USDHC_CQTERRI_DTECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK)
98242 
98243 #define USDHC_CQTERRI_DTETID_MASK                (0x1F000000U)
98244 #define USDHC_CQTERRI_DTETID_SHIFT               (24U)
98245 /*! DTETID - Data transfer error task ID */
98246 #define USDHC_CQTERRI_DTETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK)
98247 
98248 #define USDHC_CQTERRI_DTEFV_MASK                 (0x80000000U)
98249 #define USDHC_CQTERRI_DTEFV_SHIFT                (31U)
98250 /*! DTEFV - Data transfer error fields valid */
98251 #define USDHC_CQTERRI_DTEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK)
98252 /*! @} */
98253 
98254 /*! @name CQCRI - Command Queuing Command Response Index */
98255 /*! @{ */
98256 
98257 #define USDHC_CQCRI_LCMDRI_MASK                  (0x3FU)
98258 #define USDHC_CQCRI_LCMDRI_SHIFT                 (0U)
98259 /*! LCMDRI - Last command response index */
98260 #define USDHC_CQCRI_LCMDRI(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK)
98261 /*! @} */
98262 
98263 /*! @name CQCRA - Command Queuing Command Response Argument */
98264 /*! @{ */
98265 
98266 #define USDHC_CQCRA_LCMDRA_MASK                  (0xFFFFFFFFU)
98267 #define USDHC_CQCRA_LCMDRA_SHIFT                 (0U)
98268 /*! LCMDRA - Last command response argument */
98269 #define USDHC_CQCRA_LCMDRA(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK)
98270 /*! @} */
98271 
98272 
98273 /*!
98274  * @}
98275  */ /* end of group USDHC_Register_Masks */
98276 
98277 
98278 /* USDHC - Peripheral instance base addresses */
98279 /** Peripheral USDHC1 base address */
98280 #define USDHC1_BASE                              (0x30B40000u)
98281 /** Peripheral USDHC1 base pointer */
98282 #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
98283 /** Peripheral USDHC2 base address */
98284 #define USDHC2_BASE                              (0x30B50000u)
98285 /** Peripheral USDHC2 base pointer */
98286 #define USDHC2                                   ((USDHC_Type *)USDHC2_BASE)
98287 /** Peripheral USDHC3 base address */
98288 #define USDHC3_BASE                              (0x30B60000u)
98289 /** Peripheral USDHC3 base pointer */
98290 #define USDHC3                                   ((USDHC_Type *)USDHC3_BASE)
98291 /** Array initializer of USDHC peripheral base addresses */
98292 #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE }
98293 /** Array initializer of USDHC peripheral base pointers */
98294 #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 }
98295 /** Interrupt vectors for the USDHC peripheral type */
98296 #define USDHC_IRQS                               { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn, USDHC3_IRQn }
98297 
98298 /*!
98299  * @}
98300  */ /* end of group USDHC_Peripheral_Access_Layer */
98301 
98302 
98303 /* ----------------------------------------------------------------------------
98304    -- VIDEOPACKETIZER Peripheral Access Layer
98305    ---------------------------------------------------------------------------- */
98306 
98307 /*!
98308  * @addtogroup VIDEOPACKETIZER_Peripheral_Access_Layer VIDEOPACKETIZER Peripheral Access Layer
98309  * @{
98310  */
98311 
98312 /** VIDEOPACKETIZER - Register Layout Typedef */
98313 typedef struct {
98314   __I  uint8_t VP_STATUS;                          /**< Video Packetizer Packing Phase Status Register, offset: 0x0 */
98315   __IO uint8_t VP_PR_CD;                           /**< Video Packetizer Pixel Repetition and Color Depth Register, offset: 0x1 */
98316   __IO uint8_t VP_STUFF;                           /**< Video Packetizer Stuffing and Default Packing Phase Register, offset: 0x2 */
98317   __IO uint8_t VP_REMAP;                           /**< Video Packetizer YCbCr 422 Remapping Register, offset: 0x3 */
98318   __IO uint8_t VP_CONF;                            /**< Video Packetizer Output and Enable Configuration Register, offset: 0x4 */
98319        uint8_t RESERVED_0[2];
98320   __IO uint8_t VP_MASK;                            /**< Video Packetizer Interrupt Mask Register, offset: 0x7 */
98321 } VIDEOPACKETIZER_Type;
98322 
98323 /* ----------------------------------------------------------------------------
98324    -- VIDEOPACKETIZER Register Masks
98325    ---------------------------------------------------------------------------- */
98326 
98327 /*!
98328  * @addtogroup VIDEOPACKETIZER_Register_Masks VIDEOPACKETIZER Register Masks
98329  * @{
98330  */
98331 
98332 /*! @name VP_STATUS - Video Packetizer Packing Phase Status Register */
98333 /*! @{ */
98334 
98335 #define VIDEOPACKETIZER_VP_STATUS_packing_phase_MASK (0xFU)
98336 #define VIDEOPACKETIZER_VP_STATUS_packing_phase_SHIFT (0U)
98337 /*! packing_phase - Read only register that holds the "packing phase" output of the Video Packetizer block. */
98338 #define VIDEOPACKETIZER_VP_STATUS_packing_phase(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STATUS_packing_phase_SHIFT)) & VIDEOPACKETIZER_VP_STATUS_packing_phase_MASK)
98339 /*! @} */
98340 
98341 /*! @name VP_PR_CD - Video Packetizer Pixel Repetition and Color Depth Register */
98342 /*! @{ */
98343 
98344 #define VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_MASK (0xFU)
98345 #define VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_SHIFT (0U)
98346 /*! desired_pr_factor - Desired pixel repetition factor configuration. */
98347 #define VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_SHIFT)) & VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_MASK)
98348 
98349 #define VIDEOPACKETIZER_VP_PR_CD_color_depth_MASK (0xF0U)
98350 #define VIDEOPACKETIZER_VP_PR_CD_color_depth_SHIFT (4U)
98351 /*! color_depth - The Color depth configuration is described as the following, with the action
98352  *    stated corresponding to color_depth[3:0]: - 0000b: 24 bits per pixel video (8 bits per component).
98353  */
98354 #define VIDEOPACKETIZER_VP_PR_CD_color_depth(x)  (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_PR_CD_color_depth_SHIFT)) & VIDEOPACKETIZER_VP_PR_CD_color_depth_MASK)
98355 /*! @} */
98356 
98357 /*! @name VP_STUFF - Video Packetizer Stuffing and Default Packing Phase Register */
98358 /*! @{ */
98359 
98360 #define VIDEOPACKETIZER_VP_STUFF_pr_stuffing_MASK (0x1U)
98361 #define VIDEOPACKETIZER_VP_STUFF_pr_stuffing_SHIFT (0U)
98362 /*! pr_stuffing - Pixel repeater stuffing control. */
98363 #define VIDEOPACKETIZER_VP_STUFF_pr_stuffing(x)  (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_pr_stuffing_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_pr_stuffing_MASK)
98364 
98365 #define VIDEOPACKETIZER_VP_STUFF_pp_stuffing_MASK (0x2U)
98366 #define VIDEOPACKETIZER_VP_STUFF_pp_stuffing_SHIFT (1U)
98367 /*! pp_stuffing - Pixel packing stuffing control. */
98368 #define VIDEOPACKETIZER_VP_STUFF_pp_stuffing(x)  (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_pp_stuffing_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_pp_stuffing_MASK)
98369 
98370 #define VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_MASK (0x4U)
98371 #define VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_SHIFT (2U)
98372 /*! ycc422_stuffing - YCbCr 422 remap stuffing control. */
98373 #define VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_MASK)
98374 
98375 #define VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_MASK (0x8U)
98376 #define VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_SHIFT (3U)
98377 /*! icx_goto_p0_st - Reserved. */
98378 #define VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_MASK)
98379 
98380 #define VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_MASK (0x10U)
98381 #define VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_SHIFT (4U)
98382 /*! ifix_pp_to_last - Reserved. */
98383 #define VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_MASK)
98384 
98385 #define VIDEOPACKETIZER_VP_STUFF_idefault_phase_MASK (0x20U)
98386 #define VIDEOPACKETIZER_VP_STUFF_idefault_phase_SHIFT (5U)
98387 /*! idefault_phase - Controls the default phase packing machine used according to HDMI 1. */
98388 #define VIDEOPACKETIZER_VP_STUFF_idefault_phase(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_idefault_phase_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_idefault_phase_MASK)
98389 /*! @} */
98390 
98391 /*! @name VP_REMAP - Video Packetizer YCbCr 422 Remapping Register */
98392 /*! @{ */
98393 
98394 #define VIDEOPACKETIZER_VP_REMAP_ycc422_size_MASK (0x3U)
98395 #define VIDEOPACKETIZER_VP_REMAP_ycc422_size_SHIFT (0U)
98396 /*! ycc422_size - YCbCr 422 remap input video size ycc422_size[1:0] 00b: YCbCr 422 16-bit input
98397  *    video (8 bits per component) 01b: YCbCr 422 20-bit input video (10 bits per component) 10b: YCbCr
98398  *    422 24-bit input video (12 bits per component) 11b: Reserved.
98399  */
98400 #define VIDEOPACKETIZER_VP_REMAP_ycc422_size(x)  (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_REMAP_ycc422_size_SHIFT)) & VIDEOPACKETIZER_VP_REMAP_ycc422_size_MASK)
98401 /*! @} */
98402 
98403 /*! @name VP_CONF - Video Packetizer Output and Enable Configuration Register */
98404 /*! @{ */
98405 
98406 #define VIDEOPACKETIZER_VP_CONF_output_selector_0_MASK (0x1U)
98407 #define VIDEOPACKETIZER_VP_CONF_output_selector_0_SHIFT (0U)
98408 /*! output_selector_0 - Video Packetizer output selection 0b: Data from pixel packing block 1b: Data from YCbCr 422 remap block */
98409 #define VIDEOPACKETIZER_VP_CONF_output_selector_0(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_output_selector_0_SHIFT)) & VIDEOPACKETIZER_VP_CONF_output_selector_0_MASK)
98410 
98411 #define VIDEOPACKETIZER_VP_CONF_output_selector_1_MASK (0x2U)
98412 #define VIDEOPACKETIZER_VP_CONF_output_selector_1_SHIFT (1U)
98413 /*! output_selector_1 - When set to 1'b1, Data from pixel packing block Note: the use of this field is deprecated */
98414 #define VIDEOPACKETIZER_VP_CONF_output_selector_1(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_output_selector_1_SHIFT)) & VIDEOPACKETIZER_VP_CONF_output_selector_1_MASK)
98415 
98416 #define VIDEOPACKETIZER_VP_CONF_bypass_select_MASK (0x4U)
98417 #define VIDEOPACKETIZER_VP_CONF_bypass_select_SHIFT (2U)
98418 /*! bypass_select - bypass_select 0b: Data from pixel repeater block 1b: Data from input of Video Packetizer block */
98419 #define VIDEOPACKETIZER_VP_CONF_bypass_select(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_bypass_select_SHIFT)) & VIDEOPACKETIZER_VP_CONF_bypass_select_MASK)
98420 
98421 #define VIDEOPACKETIZER_VP_CONF_ycc422_en_MASK   (0x8U)
98422 #define VIDEOPACKETIZER_VP_CONF_ycc422_en_SHIFT  (3U)
98423 /*! ycc422_en - YCbCr 422 select enable. */
98424 #define VIDEOPACKETIZER_VP_CONF_ycc422_en(x)     (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_ycc422_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_ycc422_en_MASK)
98425 
98426 #define VIDEOPACKETIZER_VP_CONF_pr_en_MASK       (0x10U)
98427 #define VIDEOPACKETIZER_VP_CONF_pr_en_SHIFT      (4U)
98428 /*! pr_en - Pixel repeater enable. */
98429 #define VIDEOPACKETIZER_VP_CONF_pr_en(x)         (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_pr_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_pr_en_MASK)
98430 
98431 #define VIDEOPACKETIZER_VP_CONF_pp_en_MASK       (0x20U)
98432 #define VIDEOPACKETIZER_VP_CONF_pp_en_SHIFT      (5U)
98433 /*! pp_en - Pixel packing enable. */
98434 #define VIDEOPACKETIZER_VP_CONF_pp_en(x)         (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_pp_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_pp_en_MASK)
98435 
98436 #define VIDEOPACKETIZER_VP_CONF_bypass_en_MASK   (0x40U)
98437 #define VIDEOPACKETIZER_VP_CONF_bypass_en_SHIFT  (6U)
98438 /*! bypass_en - When set to 1'b1, Pixel packing enable. */
98439 #define VIDEOPACKETIZER_VP_CONF_bypass_en(x)     (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_bypass_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_bypass_en_MASK)
98440 /*! @} */
98441 
98442 /*! @name VP_MASK - Video Packetizer Interrupt Mask Register */
98443 /*! @{ */
98444 
98445 #define VIDEOPACKETIZER_VP_MASK_spare_1_MASK     (0x1U)
98446 #define VIDEOPACKETIZER_VP_MASK_spare_1_SHIFT    (0U)
98447 /*! spare_1 - Reserved as "spare" bit with no associated functionality. */
98448 #define VIDEOPACKETIZER_VP_MASK_spare_1(x)       (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_spare_1_SHIFT)) & VIDEOPACKETIZER_VP_MASK_spare_1_MASK)
98449 
98450 #define VIDEOPACKETIZER_VP_MASK_spare_2_MASK     (0x2U)
98451 #define VIDEOPACKETIZER_VP_MASK_spare_2_SHIFT    (1U)
98452 /*! spare_2 - Reserved as "spare" bit with no associated functionality. */
98453 #define VIDEOPACKETIZER_VP_MASK_spare_2(x)       (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_spare_2_SHIFT)) & VIDEOPACKETIZER_VP_MASK_spare_2_MASK)
98454 
98455 #define VIDEOPACKETIZER_VP_MASK_ointemptyremap_MASK (0x4U)
98456 #define VIDEOPACKETIZER_VP_MASK_ointemptyremap_SHIFT (2U)
98457 /*! ointemptyremap - Mask bit for Video Packetizer pixel YCbCr 422 re-mapper FIFO empty */
98458 #define VIDEOPACKETIZER_VP_MASK_ointemptyremap(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointemptyremap_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointemptyremap_MASK)
98459 
98460 #define VIDEOPACKETIZER_VP_MASK_ointfullremap_MASK (0x8U)
98461 #define VIDEOPACKETIZER_VP_MASK_ointfullremap_SHIFT (3U)
98462 /*! ointfullremap - Mask bit for Video Packetizer pixel YCbCr 422 re-mapper FIFO full */
98463 #define VIDEOPACKETIZER_VP_MASK_ointfullremap(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointfullremap_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointfullremap_MASK)
98464 
98465 #define VIDEOPACKETIZER_VP_MASK_ointemptypp_MASK (0x10U)
98466 #define VIDEOPACKETIZER_VP_MASK_ointemptypp_SHIFT (4U)
98467 /*! ointemptypp - Mask bit for Video Packetizer pixel packing FIFO empty */
98468 #define VIDEOPACKETIZER_VP_MASK_ointemptypp(x)   (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointemptypp_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointemptypp_MASK)
98469 
98470 #define VIDEOPACKETIZER_VP_MASK_ointfullpp_MASK  (0x20U)
98471 #define VIDEOPACKETIZER_VP_MASK_ointfullpp_SHIFT (5U)
98472 /*! ointfullpp - Mask bit for Video Packetizer pixel packing FIFO full */
98473 #define VIDEOPACKETIZER_VP_MASK_ointfullpp(x)    (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointfullpp_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointfullpp_MASK)
98474 
98475 #define VIDEOPACKETIZER_VP_MASK_ointemptyrepet_MASK (0x40U)
98476 #define VIDEOPACKETIZER_VP_MASK_ointemptyrepet_SHIFT (6U)
98477 /*! ointemptyrepet - Mask bit for Video Packetizer pixel repeater FIFO empty */
98478 #define VIDEOPACKETIZER_VP_MASK_ointemptyrepet(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointemptyrepet_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointemptyrepet_MASK)
98479 
98480 #define VIDEOPACKETIZER_VP_MASK_ointfullrepet_MASK (0x80U)
98481 #define VIDEOPACKETIZER_VP_MASK_ointfullrepet_SHIFT (7U)
98482 /*! ointfullrepet - Mask bit for Video Packetizer pixel repeater FIFO full */
98483 #define VIDEOPACKETIZER_VP_MASK_ointfullrepet(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointfullrepet_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointfullrepet_MASK)
98484 /*! @} */
98485 
98486 
98487 /*!
98488  * @}
98489  */ /* end of group VIDEOPACKETIZER_Register_Masks */
98490 
98491 
98492 /* VIDEOPACKETIZER - Peripheral instance base addresses */
98493 /** Peripheral VIDEOPACKETIZER base address */
98494 #define VIDEOPACKETIZER_BASE                     (0x32FD8800u)
98495 /** Peripheral VIDEOPACKETIZER base pointer */
98496 #define VIDEOPACKETIZER                          ((VIDEOPACKETIZER_Type *)VIDEOPACKETIZER_BASE)
98497 /** Array initializer of VIDEOPACKETIZER peripheral base addresses */
98498 #define VIDEOPACKETIZER_BASE_ADDRS               { VIDEOPACKETIZER_BASE }
98499 /** Array initializer of VIDEOPACKETIZER peripheral base pointers */
98500 #define VIDEOPACKETIZER_BASE_PTRS                { VIDEOPACKETIZER }
98501 
98502 /*!
98503  * @}
98504  */ /* end of group VIDEOPACKETIZER_Peripheral_Access_Layer */
98505 
98506 
98507 /* ----------------------------------------------------------------------------
98508    -- VIDEOSAMPLER Peripheral Access Layer
98509    ---------------------------------------------------------------------------- */
98510 
98511 /*!
98512  * @addtogroup VIDEOSAMPLER_Peripheral_Access_Layer VIDEOSAMPLER Peripheral Access Layer
98513  * @{
98514  */
98515 
98516 /** VIDEOSAMPLER - Register Layout Typedef */
98517 typedef struct {
98518   __IO uint8_t TX_INVID0;                          /**< Video Input Mapping and Internal Data Enable Configuration Register, offset: 0x0 */
98519   __IO uint8_t TX_INSTUFFING;                      /**< Video Input Stuffing Enable Register, offset: 0x1 */
98520   __IO uint8_t TX_GYDATA0;                         /**< Video Input gy Data Channel Stuffing Register 0, offset: 0x2 */
98521   __IO uint8_t TX_GYDATA1;                         /**< Video Input gy Data Channel Stuffing Register 1, offset: 0x3 */
98522   __IO uint8_t TX_RCRDATA0;                        /**< Video Input rcr Data Channel Stuffing Register 0, offset: 0x4 */
98523   __IO uint8_t TX_RCRDATA1;                        /**< Video Input rcr Data Channel Stuffing Register 1, offset: 0x5 */
98524   __IO uint8_t TX_BCBDATA0;                        /**< Video Input bcb Data Channel Stuffing Register 0, offset: 0x6 */
98525   __IO uint8_t TX_BCBDATA1;                        /**< Video Input bcb Data Channel Stuffing Register 1, offset: 0x7 */
98526 } VIDEOSAMPLER_Type;
98527 
98528 /* ----------------------------------------------------------------------------
98529    -- VIDEOSAMPLER Register Masks
98530    ---------------------------------------------------------------------------- */
98531 
98532 /*!
98533  * @addtogroup VIDEOSAMPLER_Register_Masks VIDEOSAMPLER Register Masks
98534  * @{
98535  */
98536 
98537 /*! @name TX_INVID0 - Video Input Mapping and Internal Data Enable Configuration Register */
98538 /*! @{ */
98539 
98540 #define VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_MASK (0x1FU)
98541 #define VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_SHIFT (0U)
98542 /*! video_mapping - Video Input mapping (color space/color depth): 0x01: RGB 4:4:4/8 bits 0x03: RGB
98543  *    4:4:4/10 bits 0x05: RGB 4:4:4/12 bits 0x07: RGB 4:4:4/16 bits 0x09: YCbCr 4:4:4 or 4:2:0/8
98544  *    bits 0x0B: YCbCr 4:4:4 or 4:2:0/10 bits 0x0D: YCbCr 4:4:4 or 4:2:0/12 bits 0x0F: YCbCr 4:4:4 or
98545  *    4:2:0/16 bits 0x16: YCbCr 4:2:2/8 bits 0x14: YCbCr 4:2:2/10 bits 0x12: YCbCr 4:2:2/12 bits
98546  *    0x17: YCbCr 4:4:4 (IPI)/8 bits 0x18: YCbCr 4:4:4 (IPI)/10 bits 0x19: YCbCr 4:4:4 (IPI)/12 bits
98547  *    0x1A: YCbCr 4:4:4 (IPI)/16 bits 0x1B: YCbCr 4:2:2 (IPI)/12 bits 0x1C: YCbCr 4:2:0 (IPI)/8 bits
98548  *    0x1D: YCbCr 4:2:0 (IPI)/10 bits 0x1E: YCbCr 4:2:0 (IPI)/12 bits 0x1F: YCbCr 4:2:0 (IPI)/16 bits
98549  *    Note: IPI means Image Pixel Interface and it is a proprietary interface used on SNPS MIPI
98550  *    Controllers.
98551  */
98552 #define VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING(x)  (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_SHIFT)) & VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_MASK)
98553 
98554 #define VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_MASK (0x80U)
98555 #define VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_SHIFT (7U)
98556 /*! internal_de_generator - Internal data enable (DE) generator enable. */
98557 #define VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_SHIFT)) & VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_MASK)
98558 /*! @} */
98559 
98560 /*! @name TX_INSTUFFING - Video Input Stuffing Enable Register */
98561 /*! @{ */
98562 
98563 #define VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_MASK (0x1U)
98564 #define VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_SHIFT (0U)
98565 /*! gydata_stuffing - - 0b: When the dataen signal is low, the value in the gydata[15:0] output is
98566  *    the one sampled from the corresponding input data.
98567  */
98568 #define VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_SHIFT)) & VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_MASK)
98569 
98570 #define VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_MASK (0x2U)
98571 #define VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_SHIFT (1U)
98572 /*! rcrdata_stuffing - - 0b: When the dataen signal is low, the value in the rcrdata[15:0] output is
98573  *    the one sampled from the corresponding input data.
98574  */
98575 #define VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_SHIFT)) & VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_MASK)
98576 
98577 #define VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_MASK (0x4U)
98578 #define VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_SHIFT (2U)
98579 /*! bcbdata_stuffing - - 0b: When the dataen signal is low, the value in the bcbdata[15:0] output is
98580  *    the one sampled from the corresponding input data.
98581  */
98582 #define VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_SHIFT)) & VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_MASK)
98583 /*! @} */
98584 
98585 /*! @name TX_GYDATA0 - Video Input gy Data Channel Stuffing Register 0 */
98586 /*! @{ */
98587 
98588 #define VIDEOSAMPLER_TX_GYDATA0_GYDATA_MASK      (0xFFU)
98589 #define VIDEOSAMPLER_TX_GYDATA0_GYDATA_SHIFT     (0U)
98590 /*! gydata - This register defines the value of gydata[7:0] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b. */
98591 #define VIDEOSAMPLER_TX_GYDATA0_GYDATA(x)        (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_GYDATA0_GYDATA_SHIFT)) & VIDEOSAMPLER_TX_GYDATA0_GYDATA_MASK)
98592 /*! @} */
98593 
98594 /*! @name TX_GYDATA1 - Video Input gy Data Channel Stuffing Register 1 */
98595 /*! @{ */
98596 
98597 #define VIDEOSAMPLER_TX_GYDATA1_GYDATA_MASK      (0xFFU)
98598 #define VIDEOSAMPLER_TX_GYDATA1_GYDATA_SHIFT     (0U)
98599 /*! gydata - This register defines the value of gydata[15:8] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b. */
98600 #define VIDEOSAMPLER_TX_GYDATA1_GYDATA(x)        (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_GYDATA1_GYDATA_SHIFT)) & VIDEOSAMPLER_TX_GYDATA1_GYDATA_MASK)
98601 /*! @} */
98602 
98603 /*! @name TX_RCRDATA0 - Video Input rcr Data Channel Stuffing Register 0 */
98604 /*! @{ */
98605 
98606 #define VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_MASK    (0xFFU)
98607 #define VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_SHIFT   (0U)
98608 /*! rcrdata - This register defines the value of rcrydata[7:0] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b. */
98609 #define VIDEOSAMPLER_TX_RCRDATA0_RCRDATA(x)      (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_SHIFT)) & VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_MASK)
98610 /*! @} */
98611 
98612 /*! @name TX_RCRDATA1 - Video Input rcr Data Channel Stuffing Register 1 */
98613 /*! @{ */
98614 
98615 #define VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_MASK    (0xFFU)
98616 #define VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_SHIFT   (0U)
98617 /*! rcrdata - This register defines the value of rcrydata[15:8] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b. */
98618 #define VIDEOSAMPLER_TX_RCRDATA1_RCRDATA(x)      (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_SHIFT)) & VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_MASK)
98619 /*! @} */
98620 
98621 /*! @name TX_BCBDATA0 - Video Input bcb Data Channel Stuffing Register 0 */
98622 /*! @{ */
98623 
98624 #define VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_MASK    (0xFFU)
98625 #define VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_SHIFT   (0U)
98626 /*! bcbdata - This register defines the value of bcbdata[7:0] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b. */
98627 #define VIDEOSAMPLER_TX_BCBDATA0_BCBDATA(x)      (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_SHIFT)) & VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_MASK)
98628 /*! @} */
98629 
98630 /*! @name TX_BCBDATA1 - Video Input bcb Data Channel Stuffing Register 1 */
98631 /*! @{ */
98632 
98633 #define VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_MASK    (0xFFU)
98634 #define VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_SHIFT   (0U)
98635 /*! bcbdata - This register defines the value of bcbdata[15:8] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b. */
98636 #define VIDEOSAMPLER_TX_BCBDATA1_BCBDATA(x)      (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_SHIFT)) & VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_MASK)
98637 /*! @} */
98638 
98639 
98640 /*!
98641  * @}
98642  */ /* end of group VIDEOSAMPLER_Register_Masks */
98643 
98644 
98645 /* VIDEOSAMPLER - Peripheral instance base addresses */
98646 /** Peripheral VIDEOSAMPLER base address */
98647 #define VIDEOSAMPLER_BASE                        (0x32FD8200u)
98648 /** Peripheral VIDEOSAMPLER base pointer */
98649 #define VIDEOSAMPLER                             ((VIDEOSAMPLER_Type *)VIDEOSAMPLER_BASE)
98650 /** Array initializer of VIDEOSAMPLER peripheral base addresses */
98651 #define VIDEOSAMPLER_BASE_ADDRS                  { VIDEOSAMPLER_BASE }
98652 /** Array initializer of VIDEOSAMPLER peripheral base pointers */
98653 #define VIDEOSAMPLER_BASE_PTRS                   { VIDEOSAMPLER }
98654 
98655 /*!
98656  * @}
98657  */ /* end of group VIDEOSAMPLER_Peripheral_Access_Layer */
98658 
98659 
98660 /* ----------------------------------------------------------------------------
98661    -- VPU_BLK_CTL Peripheral Access Layer
98662    ---------------------------------------------------------------------------- */
98663 
98664 /*!
98665  * @addtogroup VPU_BLK_CTL_Peripheral_Access_Layer VPU_BLK_CTL Peripheral Access Layer
98666  * @{
98667  */
98668 
98669 /** VPU_BLK_CTL - Register Layout Typedef */
98670 typedef struct {
98671   __IO uint32_t BLK_SFT_RSTN_CSR;                  /**< VPUMIX block soft reset control, offset: 0x0 */
98672   __IO uint32_t BLK_CLK_EN_CSR;                    /**< VPUMIX block clock enable control, offset: 0x4 */
98673   __IO uint32_t G1_FUSE_DEC_CSR;                   /**< VPUMIX G1 fuse_dec control, offset: 0x8 */
98674   __IO uint32_t G1_FUSE_PP_CSR;                    /**< VPUMIX G1 fuse_pp control, offset: 0xC */
98675   __IO uint32_t G2_FUSE_DEC_CSR;                   /**< VPUMIX G2 fuse_dec control, offset: 0x10 */
98676   __IO uint32_t VC8000E_FUSE_ENC_CSR;              /**< VPUMIX VC8000E fuse_enc control, offset: 0x14 */
98677   __IO uint32_t VPU_CACHE_EN_CSR;                  /**< VPUMIX block cache enable control, offset: 0x18 */
98678   __I  uint32_t VPU_NO_PENDING_CSR;                /**< VPUMIX block pending transaction status, offset: 0x1C */
98679   __IO uint32_t G1_OTR_BEAT_LIMIT_CSR;             /**< VPUMIX G1 outstanding read beat limit control, offset: 0x20 */
98680   __IO uint32_t G2_OTR_BEAT_LIMIT_CSR;             /**< VPUMIX G2 outstanding read beat limit control, offset: 0x24 */
98681   __IO uint32_t VC8000E_OTR_BEAT_LIMIT_CSR;        /**< VPUMIX VC8000E outstanding read beat limit control, offset: 0x28 */
98682 } VPU_BLK_CTL_Type;
98683 
98684 /* ----------------------------------------------------------------------------
98685    -- VPU_BLK_CTL Register Masks
98686    ---------------------------------------------------------------------------- */
98687 
98688 /*!
98689  * @addtogroup VPU_BLK_CTL_Register_Masks VPU_BLK_CTL Register Masks
98690  * @{
98691  */
98692 
98693 /*! @name BLK_SFT_RSTN_CSR - VPUMIX block soft reset control */
98694 /*! @{ */
98695 
98696 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_MASK (0x1U)
98697 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_SHIFT (0U)
98698 /*! G2_SFT_RSTN
98699  *  0b1..Normal
98700  *  0b0..Reset
98701  */
98702 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_SHIFT)) & VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_MASK)
98703 
98704 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_MASK (0x2U)
98705 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_SHIFT (1U)
98706 /*! G1_SFT_RSTN
98707  *  0b1..Normal
98708  *  0b0..Reset
98709  */
98710 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_SHIFT)) & VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_MASK)
98711 
98712 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_MASK (0x4U)
98713 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_SHIFT (2U)
98714 /*! VC8000E_SFT_RSTN
98715  *  0b1..Normal
98716  *  0b0..Reset
98717  */
98718 #define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_SHIFT)) & VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_MASK)
98719 /*! @} */
98720 
98721 /*! @name BLK_CLK_EN_CSR - VPUMIX block clock enable control */
98722 /*! @{ */
98723 
98724 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_MASK (0x1U)
98725 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_SHIFT (0U)
98726 /*! G2_CLK_EN
98727  *  0b1..Enable
98728  *  0b0..Disable
98729  */
98730 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_MASK)
98731 
98732 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_MASK (0x2U)
98733 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_SHIFT (1U)
98734 /*! G1_CLK_EN
98735  *  0b1..Enable
98736  *  0b0..Disable
98737  */
98738 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_MASK)
98739 
98740 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_MASK (0x4U)
98741 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_SHIFT (2U)
98742 /*! VC8000E_CLK_EN
98743  *  0b1..Enable
98744  *  0b0..Disable
98745  */
98746 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_MASK)
98747 
98748 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_MASK (0x8U)
98749 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_SHIFT (3U)
98750 /*! MAIN_CLK_EN
98751  *  0b1..Enable
98752  *  0b0..Disable
98753  */
98754 #define VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_MASK)
98755 /*! @} */
98756 
98757 /*! @name G1_FUSE_DEC_CSR - VPUMIX G1 fuse_dec control */
98758 /*! @{ */
98759 
98760 #define VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_MASK (0xFFFFFFFFU)
98761 #define VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_SHIFT (0U)
98762 /*! G1_FUSE_DEC
98763  *  0b00000000000000000000000000000001..Enable
98764  *  0b00000000000000000000000000000000..Disable
98765  */
98766 #define VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_SHIFT)) & VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_MASK)
98767 /*! @} */
98768 
98769 /*! @name G1_FUSE_PP_CSR - VPUMIX G1 fuse_pp control */
98770 /*! @{ */
98771 
98772 #define VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_MASK (0xFFFFFFFFU)
98773 #define VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_SHIFT (0U)
98774 /*! G1_FUSE_PP
98775  *  0b00000000000000000000000000000001..Enable
98776  *  0b00000000000000000000000000000000..Disable
98777  */
98778 #define VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_SHIFT)) & VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_MASK)
98779 /*! @} */
98780 
98781 /*! @name G2_FUSE_DEC_CSR - VPUMIX G2 fuse_dec control */
98782 /*! @{ */
98783 
98784 #define VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_MASK (0xFFFFFFFFU)
98785 #define VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_SHIFT (0U)
98786 /*! G2_FUSE_DEC
98787  *  0b00000000000000000000000000000001..Enable
98788  *  0b00000000000000000000000000000000..Disable
98789  */
98790 #define VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_SHIFT)) & VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_MASK)
98791 /*! @} */
98792 
98793 /*! @name VC8000E_FUSE_ENC_CSR - VPUMIX VC8000E fuse_enc control */
98794 /*! @{ */
98795 
98796 #define VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_MASK (0xFFFFFFFFU)
98797 #define VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_SHIFT (0U)
98798 /*! VC8000E_FUSE_ENC
98799  *  0b00000000000000000000000000000001..Enable
98800  *  0b00000000000000000000000000000000..Disable
98801  */
98802 #define VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_SHIFT)) & VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_MASK)
98803 /*! @} */
98804 
98805 /*! @name VPU_CACHE_EN_CSR - VPUMIX block cache enable control */
98806 /*! @{ */
98807 
98808 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_MASK (0x1U)
98809 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_SHIFT (0U)
98810 /*! G1_ARCACHE_EN
98811  *  0b1..Enable
98812  *  0b0..Disable
98813  */
98814 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_MASK)
98815 
98816 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_MASK (0x2U)
98817 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_SHIFT (1U)
98818 /*! G1_AWCACHE_EN
98819  *  0b1..Enable
98820  *  0b0..Disable
98821  */
98822 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_MASK)
98823 
98824 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_MASK (0x4U)
98825 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_SHIFT (2U)
98826 /*! G2_ARCACHE_EN
98827  *  0b1..Enable
98828  *  0b0..Disable
98829  */
98830 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_MASK)
98831 
98832 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_MASK (0x8U)
98833 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_SHIFT (3U)
98834 /*! G2_AWCACHE_EN
98835  *  0b1..Enable
98836  *  0b0..Disable
98837  */
98838 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_MASK)
98839 
98840 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_MASK (0x10U)
98841 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_SHIFT (4U)
98842 /*! VC8000E_ARCACHE_EN
98843  *  0b1..Enable
98844  *  0b0..Disable
98845  */
98846 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_MASK)
98847 
98848 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_MASK (0x20U)
98849 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_SHIFT (5U)
98850 /*! VC8000E_AWCACHE_EN
98851  *  0b1..Enable
98852  *  0b0..Disable
98853  */
98854 #define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_MASK)
98855 /*! @} */
98856 
98857 /*! @name VPU_NO_PENDING_CSR - VPUMIX block pending transaction status */
98858 /*! @{ */
98859 
98860 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_MASK (0x1U)
98861 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_SHIFT (0U)
98862 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_SHIFT)) & VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_MASK)
98863 
98864 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_MASK (0x2U)
98865 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_SHIFT (1U)
98866 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_SHIFT)) & VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_MASK)
98867 
98868 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_MASK (0x4U)
98869 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_SHIFT (2U)
98870 #define VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_SHIFT)) & VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_MASK)
98871 /*! @} */
98872 
98873 /*! @name G1_OTR_BEAT_LIMIT_CSR - VPUMIX G1 outstanding read beat limit control */
98874 /*! @{ */
98875 
98876 #define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_MASK (0xFFFFU)
98877 #define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_SHIFT (0U)
98878 #define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_SHIFT)) & VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_MASK)
98879 
98880 #define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_MASK (0x10000U)
98881 #define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_SHIFT (16U)
98882 #define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_SHIFT)) & VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_MASK)
98883 /*! @} */
98884 
98885 /*! @name G2_OTR_BEAT_LIMIT_CSR - VPUMIX G2 outstanding read beat limit control */
98886 /*! @{ */
98887 
98888 #define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_MASK (0xFFFFU)
98889 #define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_SHIFT (0U)
98890 #define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_SHIFT)) & VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_MASK)
98891 
98892 #define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_MASK (0x10000U)
98893 #define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_SHIFT (16U)
98894 #define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_SHIFT)) & VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_MASK)
98895 /*! @} */
98896 
98897 /*! @name VC8000E_OTR_BEAT_LIMIT_CSR - VPUMIX VC8000E outstanding read beat limit control */
98898 /*! @{ */
98899 
98900 #define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_MASK (0xFFFFU)
98901 #define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_SHIFT (0U)
98902 #define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_SHIFT)) & VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_MASK)
98903 
98904 #define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_MASK (0x10000U)
98905 #define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_SHIFT (16U)
98906 #define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_SHIFT)) & VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_MASK)
98907 /*! @} */
98908 
98909 
98910 /*!
98911  * @}
98912  */ /* end of group VPU_BLK_CTL_Register_Masks */
98913 
98914 
98915 /* VPU_BLK_CTL - Peripheral instance base addresses */
98916 /** Peripheral VPU_BLK_CTRL base address */
98917 #define VPU_BLK_CTRL_BASE                        (0x38330000u)
98918 /** Peripheral VPU_BLK_CTRL base pointer */
98919 #define VPU_BLK_CTRL                             ((VPU_BLK_CTL_Type *)VPU_BLK_CTRL_BASE)
98920 /** Array initializer of VPU_BLK_CTL peripheral base addresses */
98921 #define VPU_BLK_CTL_BASE_ADDRS                   { VPU_BLK_CTRL_BASE }
98922 /** Array initializer of VPU_BLK_CTL peripheral base pointers */
98923 #define VPU_BLK_CTL_BASE_PTRS                    { VPU_BLK_CTRL }
98924 
98925 /*!
98926  * @}
98927  */ /* end of group VPU_BLK_CTL_Peripheral_Access_Layer */
98928 
98929 
98930 /* ----------------------------------------------------------------------------
98931    -- VPU_G1 Peripheral Access Layer
98932    ---------------------------------------------------------------------------- */
98933 
98934 /*!
98935  * @addtogroup VPU_G1_Peripheral_Access_Layer VPU_G1 Peripheral Access Layer
98936  * @{
98937  */
98938 
98939 /** VPU_G1 - Register Layout Typedef */
98940 typedef struct {
98941        uint8_t RESERVED_0[4];
98942   __IO uint32_t SWREG1;                            /**< Interrupt register decoder, offset: 0x4 */
98943   __IO uint32_t SWREG2;                            /**< Device configuration register decoder, offset: 0x8 */
98944   __IO uint32_t SWREG3;                            /**< Decoder control register 0 (decmode,picture type etc), offset: 0xC */
98945        uint8_t RESERVED_1[32];
98946   __IO uint32_t SWREG12;                           /**< Base address for RLC data (RLC) / stream start address/decoded end addr register (VLC), offset: 0x30 */
98947   __IO uint32_t SWREG13;                           /**< Base address for decoded picture, offset: 0x34 */
98948        uint8_t RESERVED_2[104];
98949   __IO uint32_t SWREG40;                           /**< Base address for standard dependent tables, offset: 0xA0 */
98950   __IO uint32_t SWREG41;                           /**< Base address for direct mode motion vectors, offset: 0xA4 */
98951        uint8_t RESERVED_3[24];
98952   __IO uint32_t SWREG48;                           /**< Error concealment register, offset: 0xC0 */
98953   __IO uint32_t SWREG49;                           /**< Prediction filter tap register for H264, offset: 0xC4 */
98954   __I  uint32_t SWREG50;                           /**< Synthesis configuration register decoder 0, offset: 0xC8 */
98955   __IO uint32_t SWREG51;                           /**< Reference picture buffer control register, offset: 0xCC */
98956   __I  uint32_t SWREG52;                           /**< Reference picture buffer information register 1, offset: 0xD0 */
98957   __I  uint32_t SWREG53;                           /**< Reference picture buffer information register 2, offset: 0xD4 */
98958   __I  uint32_t SWREG54;                           /**< Synthesis configuration register decoder 1, offset: 0xD8 */
98959   __IO uint32_t SWREG55;                           /**< Reference picture buffer 2 / Advanced prefetch control register, offset: 0xDC */
98960   __I  uint32_t SWREG56;                           /**< Reference buffer information register 3, offset: 0xE0 */
98961   __I  uint32_t SWREG57;                           /**< Decoder fuse register, offset: 0xE4 */
98962   __IO uint32_t SWREG58;                           /**< Device configuration register decoder 2 + Multi core control register, offset: 0xE8 */
98963   __IO uint32_t SWREG59;                           /**< H264 Chrominance 8 pixel interleaved data base, offset: 0xEC */
98964   __IO uint32_t SWREG60;                           /**< Interrupt register post-processor, offset: 0xF0 */
98965   __IO uint32_t SWREG61;                           /**< Device configuration register post-processor, offset: 0xF4 */
98966   __IO uint32_t SWREG62;                           /**< Deinterlace control register, offset: 0xF8 */
98967   __IO uint32_t SWREG63;                           /**< Base address for reading post-processing input picture luminance (top field/frame), offset: 0xFC */
98968   __IO uint32_t SWREG64;                           /**< Base address for reading post-processing input picture Cb/Ch (top field/frame), offset: 0x100 */
98969   __IO uint32_t SWREG65;                           /**< Base address for reading post-processing input picture Cr, offset: 0x104 */
98970   __IO uint32_t SWREG66;                           /**< Base address for writing post-processed picture luminance/RGB, offset: 0x108 */
98971   __IO uint32_t SWREG67;                           /**< Base address for writing post-processed picture Ch, offset: 0x10C */
98972   __IO uint32_t SWREG68;                           /**< Register for contrast adjusting, offset: 0x110 */
98973   __IO uint32_t SWREG69;                           /**< Register for colour conversion and contrast adjusting/YUYV 422 channel orders, offset: 0x114 */
98974   __IO uint32_t SWREG70;                           /**< Register for colour conversion 0, offset: 0x118 */
98975   __IO uint32_t SWREG71;                           /**< Register for colour conversion 1 + rotation mode, offset: 0x11C */
98976   __IO uint32_t SWREG72;                           /**< PP input size and -cropping register, offset: 0x120 */
98977   __IO uint32_t SWREG73;                           /**< PP input picture base address for Y bottom field, offset: 0x124 */
98978   __IO uint32_t SWREG74;                           /**< PP input picture base for Ch bottom field, offset: 0x128 */
98979        uint8_t RESERVED_4[16];
98980   __IO uint32_t SWREG79;                           /**< Scaling register 0 ratio and padding for R and G, offset: 0x13C */
98981   __IO uint32_t SWREG80;                           /**< Scaling ratio register 1 and padding for B, offset: 0x140 */
98982   __IO uint32_t SWREG81;                           /**< Scaling ratio register 2, offset: 0x144 */
98983   __IO uint32_t SWREG82;                           /**< Rmask register, offset: 0x148 */
98984   __IO uint32_t SWREG83;                           /**< Gmask register, offset: 0x14C */
98985   __IO uint32_t SWREG84;                           /**< Bmask register, offset: 0x150 */
98986   __IO uint32_t SWREG85;                           /**< Post-processor control register, offset: 0x154 */
98987   __IO uint32_t SWREG86;                           /**< Mask 1 start coordinate register, offset: 0x158 */
98988   __IO uint32_t SWREG87;                           /**< Mask 2 start coordinate register + Mask extensions, offset: 0x15C */
98989   __IO uint32_t SWREG88;                           /**< Mask 1 size and PP original width register, offset: 0x160 */
98990   __IO uint32_t SWREG89;                           /**< Mask 2 size register + mask extensions, offset: 0x164 */
98991   __IO uint32_t SWREG90;                           /**< PiP register 0, offset: 0x168 */
98992   __IO uint32_t SWREG91;                           /**< PiP register 1 and dithering control, offset: 0x16C */
98993   __IO uint32_t SWREG92;                           /**< Display width and PP input size extension register, offset: 0x170 */
98994   __IO uint32_t SWREG93;                           /**< Base address for alpha blend 1 gui component, offset: 0x174 */
98995   __IO uint32_t SWREG94;                           /**< Base address for alpha blend 2 gui component, offset: 0x178 */
98996   __IO uint32_t SWREG95;                           /**< Alpha blend input cropping register (scanline for cropping), offset: 0x17C */
98997        uint8_t RESERVED_5[12];
98998   __I  uint32_t SWREG99;                           /**< PP fuse register, offset: 0x18C */
98999   __I  uint32_t SWREG100;                          /**< Synthesis configuration register post-processor, offset: 0x190 */
99000        uint8_t RESERVED_6[4];
99001   __IO uint32_t SWREG102;                          /**< Base address for H264 decoded chroma picture, offset: 0x198 */
99002   __IO uint32_t SWREG103;                          /**< Base address for reference chroma picture index 0, offset: 0x19C */
99003   __IO uint32_t SWREG104;                          /**< Base address for reference chroma picture index 1, offset: 0x1A0 */
99004   __IO uint32_t SWREG105;                          /**< Base address for reference chroma picture index 2, offset: 0x1A4 */
99005   __IO uint32_t SWREG106;                          /**< Base address for reference chroma picture index 3, offset: 0x1A8 */
99006   __IO uint32_t SWREG107;                          /**< Base address for reference chroma picture index 4, offset: 0x1AC */
99007   __IO uint32_t SWREG108;                          /**< Base address for reference chroma picture index 5, offset: 0x1B0 */
99008   __IO uint32_t SWREG109;                          /**< Base address for reference chroma picture index 6, offset: 0x1B4 */
99009   __IO uint32_t SWREG110;                          /**< Base address for reference chroma picture index 7, offset: 0x1B8 */
99010   __IO uint32_t SWREG111;                          /**< Base address for reference chroma picture index 8, offset: 0x1BC */
99011   __IO uint32_t SWREG112;                          /**< Base address for reference chroma picture index 9, offset: 0x1C0 */
99012   __IO uint32_t SWREG113;                          /**< Base address for reference chroma picture index 10, offset: 0x1C4 */
99013   __IO uint32_t SWREG114;                          /**< Base address for reference chroma picture index 11, offset: 0x1C8 */
99014   __IO uint32_t SWREG115;                          /**< Base address for reference chroma picture index 12, offset: 0x1CC */
99015   __IO uint32_t SWREG116;                          /**< Base address for reference chroma picture index 13, offset: 0x1D0 */
99016   __IO uint32_t SWREG117;                          /**< Base address for reference chroma picture index 14, offset: 0x1D4 */
99017   __IO uint32_t SWREG118;                          /**< Base address for reference chroma picture index 15, offset: 0x1D8 */
99018 } VPU_G1_Type;
99019 
99020 /* ----------------------------------------------------------------------------
99021    -- VPU_G1 Register Masks
99022    ---------------------------------------------------------------------------- */
99023 
99024 /*!
99025  * @addtogroup VPU_G1_Register_Masks VPU_G1 Register Masks
99026  * @{
99027  */
99028 
99029 /*! @name SWREG1 - Interrupt register decoder */
99030 /*! @{ */
99031 
99032 #define VPU_G1_SWREG1_SW_DEC_E_MASK              (0x1U)
99033 #define VPU_G1_SWREG1_SW_DEC_E_SHIFT             (0U)
99034 /*! SW_DEC_E - Decoder enable. Setting this bit high will start the decoding operation. HW will
99035  *    reset this when picture is processed or ASO or stream error is detected or bus error or timeout
99036  *    interrupt is given.
99037  */
99038 #define VPU_G1_SWREG1_SW_DEC_E(x)                (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_E_SHIFT)) & VPU_G1_SWREG1_SW_DEC_E_MASK)
99039 
99040 #define VPU_G1_SWREG1_SW_DEC_IRQ_DIS_MASK        (0x10U)
99041 #define VPU_G1_SWREG1_SW_DEC_IRQ_DIS_SHIFT       (4U)
99042 /*! SW_DEC_IRQ_DIS - Decoder IRQ disable. When high, there are no interrupts concerning decoder from
99043  *    HW. Polling must be used to see the interrupt statuses.
99044  */
99045 #define VPU_G1_SWREG1_SW_DEC_IRQ_DIS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_IRQ_DIS_SHIFT)) & VPU_G1_SWREG1_SW_DEC_IRQ_DIS_MASK)
99046 
99047 #define VPU_G1_SWREG1_SW_DEC_ABORT_E_MASK        (0x20U)
99048 #define VPU_G1_SWREG1_SW_DEC_ABORT_E_SHIFT       (5U)
99049 /*! SW_DEC_ABORT_E - Abort decoding enable. Setting this bit high will cause HW to abort decoding
99050  *    and safely to reset itself down. After abort is complete the corresponding interrupt status is
99051  *    set and this bit is set low as well as the decoder enable.
99052  */
99053 #define VPU_G1_SWREG1_SW_DEC_ABORT_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_ABORT_E_SHIFT)) & VPU_G1_SWREG1_SW_DEC_ABORT_E_MASK)
99054 
99055 #define VPU_G1_SWREG1_SW_DEC_IRQ_MASK            (0x100U)
99056 #define VPU_G1_SWREG1_SW_DEC_IRQ_SHIFT           (8U)
99057 /*! SW_DEC_IRQ - Decoder IRQ. When high, decoder requests an interrupt. SW will reset this after interrupt is handled. */
99058 #define VPU_G1_SWREG1_SW_DEC_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_IRQ_SHIFT)) & VPU_G1_SWREG1_SW_DEC_IRQ_MASK)
99059 
99060 #define VPU_G1_SWREG1_SW_DEC_RDY_INT_MASK        (0x1000U)
99061 #define VPU_G1_SWREG1_SW_DEC_RDY_INT_SHIFT       (12U)
99062 /*! SW_DEC_RDY_INT - Interrupt status bit decoder. When this bit is high decoder has decoded a picture. HW will self reset. */
99063 #define VPU_G1_SWREG1_SW_DEC_RDY_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_RDY_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_RDY_INT_MASK)
99064 
99065 #define VPU_G1_SWREG1_SW_DEC_BUS_INT_MASK        (0x2000U)
99066 #define VPU_G1_SWREG1_SW_DEC_BUS_INT_SHIFT       (13U)
99067 /*! SW_DEC_BUS_INT - Interrupt status bit bus. Error response from bus. */
99068 #define VPU_G1_SWREG1_SW_DEC_BUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_BUS_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_BUS_INT_MASK)
99069 
99070 #define VPU_G1_SWREG1_SW_DEC_BUFFER_INT_MASK     (0x4000U)
99071 #define VPU_G1_SWREG1_SW_DEC_BUFFER_INT_SHIFT    (14U)
99072 /*! SW_DEC_BUFFER_INT - Interrupt status bit input buffer empty. When high, input stream buffer is
99073  *    empty but picture is not ready. HW will not self reset.
99074  */
99075 #define VPU_G1_SWREG1_SW_DEC_BUFFER_INT(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_BUFFER_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_BUFFER_INT_MASK)
99076 
99077 #define VPU_G1_SWREG1_SW_DEC_ASO_INT_MASK        (0x8000U)
99078 #define VPU_G1_SWREG1_SW_DEC_ASO_INT_SHIFT       (15U)
99079 /*! SW_DEC_ASO_INT - H264: Interrupt status bit ASO (Arbitrary Slice Ordering) detected. When high,
99080  *    ASO detected in input data stream decoding. HW will self reset. VP8: Error detected in
99081  *    Residual data. HW returns MB number in error concealment register for MB it detected it
99082  */
99083 #define VPU_G1_SWREG1_SW_DEC_ASO_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_ASO_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_ASO_INT_MASK)
99084 
99085 #define VPU_G1_SWREG1_SW_DEC_ERROR_INT_MASK      (0x10000U)
99086 #define VPU_G1_SWREG1_SW_DEC_ERROR_INT_SHIFT     (16U)
99087 /*! SW_DEC_ERROR_INT - Interrupt status bit input stream error. When high, an error is found in input data stream decoding. HW will self reset. */
99088 #define VPU_G1_SWREG1_SW_DEC_ERROR_INT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_ERROR_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_ERROR_INT_MASK)
99089 
99090 #define VPU_G1_SWREG1_SW_DEC_SLICE_INT_MASK      (0x20000U)
99091 #define VPU_G1_SWREG1_SW_DEC_SLICE_INT_SHIFT     (17U)
99092 /*! SW_DEC_SLICE_INT - Interrupt status bit dec_slice_decoded. When high SW must set new base
99093  *    addresses for sw_dec_out_base and sw_jpg_ch_out_base before resetting this status bit. Used for VP8
99094  *    web-p modes
99095  */
99096 #define VPU_G1_SWREG1_SW_DEC_SLICE_INT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_SLICE_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_SLICE_INT_MASK)
99097 
99098 #define VPU_G1_SWREG1_SW_DEC_TIMEOUT_MASK        (0x40000U)
99099 #define VPU_G1_SWREG1_SW_DEC_TIMEOUT_SHIFT       (18U)
99100 /*! SW_DEC_TIMEOUT - Interrupt status bit decoder timeout. When high the decoder has been idling for
99101  *    too long. HW will self reset. Possible only if timeout interrupt is enabled
99102  */
99103 #define VPU_G1_SWREG1_SW_DEC_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_TIMEOUT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_TIMEOUT_MASK)
99104 
99105 #define VPU_G1_SWREG1_SW_DEC_PIC_INF_MASK        (0x1000000U)
99106 #define VPU_G1_SWREG1_SW_DEC_PIC_INF_SHIFT       (24U)
99107 /*! SW_DEC_PIC_INF - B slice detected. This signal is driven high during picture ready interrupt if
99108  *    B-type slice is found. This bit does not launch interrupt but is used to inform SW about h264
99109  *    tools.
99110  */
99111 #define VPU_G1_SWREG1_SW_DEC_PIC_INF(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_PIC_INF_SHIFT)) & VPU_G1_SWREG1_SW_DEC_PIC_INF_MASK)
99112 /*! @} */
99113 
99114 /*! @name SWREG2 - Device configuration register decoder */
99115 /*! @{ */
99116 
99117 #define VPU_G1_SWREG2_SW_DEC_MAX_BURST_MASK      (0x1FU)
99118 #define VPU_G1_SWREG2_SW_DEC_MAX_BURST_SHIFT     (0U)
99119 /*! SW_DEC_MAX_BURST - Maximum burst length for decoder bus transactions. */
99120 #define VPU_G1_SWREG2_SW_DEC_MAX_BURST(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_MAX_BURST_SHIFT)) & VPU_G1_SWREG2_SW_DEC_MAX_BURST_MASK)
99121 
99122 #define VPU_G1_SWREG2_SW_DEC_SCMD_DIS_MASK       (0x20U)
99123 #define VPU_G1_SWREG2_SW_DEC_SCMD_DIS_SHIFT      (5U)
99124 /*! SW_DEC_SCMD_DIS - 9170 decoder and later->: AXI Single Command Multiple Data disable. 9170 axi
99125  *    wrapper supports this mode by default (where only the first addresses of the burst are given
99126  *    from address generator). This bit is used to disable the feature (possible SW workaround if
99127  *    something is not working correctly)
99128  */
99129 #define VPU_G1_SWREG2_SW_DEC_SCMD_DIS(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_SCMD_DIS_SHIFT)) & VPU_G1_SWREG2_SW_DEC_SCMD_DIS_MASK)
99130 
99131 #define VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_MASK    (0x40U)
99132 #define VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_SHIFT   (6U)
99133 /*! SW_DEC_ADV_PRE_DIS - Advanced PREFETCH mode disable (advanced reference picture reading mode for video) */
99134 #define VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_SHIFT)) & VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_MASK)
99135 
99136 #define VPU_G1_SWREG2_SW_TILED_MODE_LSB_MASK     (0x80U)
99137 #define VPU_G1_SWREG2_SW_TILED_MODE_LSB_SHIFT    (7U)
99138 /*! SW_TILED_MODE_LSB - Tiled mode lsb. Concatenated to Tiled mode msb which form 2 bit tiled mode. Defined in tiled_mode_msb */
99139 #define VPU_G1_SWREG2_SW_TILED_MODE_LSB(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_TILED_MODE_LSB_SHIFT)) & VPU_G1_SWREG2_SW_TILED_MODE_LSB_MASK)
99140 
99141 #define VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_MASK     (0x100U)
99142 #define VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_SHIFT    (8U)
99143 /*! SW_DEC_OUT_ENDIAN - Decoder output endian mode:
99144  *  0b0..Big endian (0-1-2-3 order)
99145  *  0b1..Little endian (3-2-1-0 order)
99146  */
99147 #define VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_SHIFT)) & VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_MASK)
99148 
99149 #define VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_MASK      (0x200U)
99150 #define VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_SHIFT     (9U)
99151 /*! SW_DEC_IN_ENDIAN - Decoder input endian mode for other than stream data:
99152  *  0b0..Big endian (0-1-2-3 order)
99153  *  0b1..Little endian (3-2-1-0 order)
99154  */
99155 #define VPU_G1_SWREG2_SW_DEC_IN_ENDIAN(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_SHIFT)) & VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_MASK)
99156 
99157 #define VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_MASK     (0x400U)
99158 #define VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_SHIFT    (10U)
99159 /*! SW_DEC_CLK_GATE_E - Decoder dynamic clock gating enable:
99160  *  0b0..Clock is running for all structures
99161  *  0b1..Clock is gated for decoder structures that are not used. Note: Clock gating value can be changed only when decoder is disabled.
99162  */
99163 #define VPU_G1_SWREG2_SW_DEC_CLK_GATE_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_MASK)
99164 
99165 #define VPU_G1_SWREG2_SW_DEC_LATENCY_MASK        (0x1F800U)
99166 #define VPU_G1_SWREG2_SW_DEC_LATENCY_SHIFT       (11U)
99167 /*! SW_DEC_LATENCY - Decoder master interface additional latency. */
99168 #define VPU_G1_SWREG2_SW_DEC_LATENCY(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_LATENCY_SHIFT)) & VPU_G1_SWREG2_SW_DEC_LATENCY_MASK)
99169 
99170 #define VPU_G1_SWREG2_SW_TILED_MODE_MSB_MASK     (0x20000U)
99171 #define VPU_G1_SWREG2_SW_TILED_MODE_MSB_SHIFT    (17U)
99172 /*! SW_TILED_MODE_MSB - Tiled mode msb. Concatenated to Tiled mode lsb which form 2 bit tiled mode.
99173  *  0b0..Tiled mode not enabled
99174  *  0b1..Tiled mode enabled for 8x4 tile size
99175  */
99176 #define VPU_G1_SWREG2_SW_TILED_MODE_MSB(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_TILED_MODE_MSB_SHIFT)) & VPU_G1_SWREG2_SW_TILED_MODE_MSB_MASK)
99177 
99178 #define VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_MASK    (0x40000U)
99179 #define VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_SHIFT   (18U)
99180 /*! SW_DEC_DATA_DISC_E - Data discard enable. Precise burst lengths are used with reading services.
99181  *    Extra data is discarded internally. Note. If AHB maxburst 17 is used data discard cannot be
99182  *    enabled (causes conflict)
99183  */
99184 #define VPU_G1_SWREG2_SW_DEC_DATA_DISC_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_MASK)
99185 
99186 #define VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_MASK    (0x80000U)
99187 #define VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_SHIFT   (19U)
99188 /*! SW_DEC_OUTSWAP32_E - Decoder output 32bit data swap (may be used for 64 bit environment):
99189  *  0b0..no swapping of 32 bit words
99190  *  0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
99191  */
99192 #define VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_MASK)
99193 
99194 #define VPU_G1_SWREG2_SW_DEC_INSWAP32_E_MASK     (0x100000U)
99195 #define VPU_G1_SWREG2_SW_DEC_INSWAP32_E_SHIFT    (20U)
99196 /*! SW_DEC_INSWAP32_E - Decoder input 32bit data swap for other than stream data (may be used for 64 bit environment):
99197  *  0b0..no swapping of 32 bit words
99198  *  0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
99199  */
99200 #define VPU_G1_SWREG2_SW_DEC_INSWAP32_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_INSWAP32_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_INSWAP32_E_MASK)
99201 
99202 #define VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_MASK    (0x200000U)
99203 #define VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_SHIFT   (21U)
99204 /*! SW_DEC_STRENDIAN_E - Decoder input endian mode for stream data:
99205  *  0b0..Big endian (0-1-2-3 order)
99206  *  0b1..Little endian (3-2-1-0 order)
99207  */
99208 #define VPU_G1_SWREG2_SW_DEC_STRENDIAN_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_MASK)
99209 
99210 #define VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_MASK    (0x400000U)
99211 #define VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_SHIFT   (22U)
99212 /*! SW_DEC_STRSWAP32_E - Decoder input 32bit data swap for stream data (may be used for 64 bit environment):
99213  *  0b0..no swapping of 32 bit words
99214  *  0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
99215  */
99216 #define VPU_G1_SWREG2_SW_DEC_STRSWAP32_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_MASK)
99217 
99218 #define VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_MASK      (0x800000U)
99219 #define VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_SHIFT     (23U)
99220 /*! SW_DEC_TIMEOUT_E - Timeout interrupt enable. If enabled HW may return timeout interrupt in case HW gets stuck while decoding picture. */
99221 #define VPU_G1_SWREG2_SW_DEC_TIMEOUT_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_MASK)
99222 
99223 #define VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_MASK      (0xFF000000U)
99224 #define VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_SHIFT     (24U)
99225 /*! SW_DEC_AXI_RD_ID - Read ID used for decoder reading services in AXI bus (if connected to AXI). */
99226 #define VPU_G1_SWREG2_SW_DEC_AXI_RD_ID(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_SHIFT)) & VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_MASK)
99227 /*! @} */
99228 
99229 /*! @name SWREG3 - Decoder control register 0 (decmode,picture type etc) */
99230 /*! @{ */
99231 
99232 #define VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_MASK      (0xFFU)
99233 #define VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_SHIFT     (0U)
99234 /*! SW_DEC_AXI_WR_ID - Write ID used for decoder writing services in AXI bus (if connected to AXI) */
99235 #define VPU_G1_SWREG3_SW_DEC_AXI_WR_ID(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_SHIFT)) & VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_MASK)
99236 
99237 #define VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_MASK    (0x100U)
99238 #define VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_SHIFT   (8U)
99239 /*! SW_DEC_AHB_HLOCK_E - AHB master HLOCK enable. When high the service is locked to decoder as long
99240  *    as it needs the bus (whenever decoder requests the bus it will be granted)
99241  */
99242 #define VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_SHIFT)) & VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_MASK)
99243 
99244 #define VPU_G1_SWREG3_SW_PICORD_COUNT_E_MASK     (0x200U)
99245 #define VPU_G1_SWREG3_SW_PICORD_COUNT_E_SHIFT    (9U)
99246 /*! SW_PICORD_COUNT_E - h264_high config: Picture order count table read enable. If enabled HW will
99247  *    read picture order counts from memory in the beginning of picture
99248  */
99249 #define VPU_G1_SWREG3_SW_PICORD_COUNT_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PICORD_COUNT_E_SHIFT)) & VPU_G1_SWREG3_SW_PICORD_COUNT_E_MASK)
99250 
99251 #define VPU_G1_SWREG3_SW_SEQ_MBAFF_E_MASK        (0x400U)
99252 #define VPU_G1_SWREG3_SW_SEQ_MBAFF_E_SHIFT       (10U)
99253 /*! SW_SEQ_MBAFF_E - Sequence includes MBAFF coded pictures */
99254 #define VPU_G1_SWREG3_SW_SEQ_MBAFF_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_SEQ_MBAFF_E_SHIFT)) & VPU_G1_SWREG3_SW_SEQ_MBAFF_E_MASK)
99255 
99256 #define VPU_G1_SWREG3_SW_REFTOPFIRST_E_MASK      (0x800U)
99257 #define VPU_G1_SWREG3_SW_REFTOPFIRST_E_SHIFT     (11U)
99258 /*! SW_REFTOPFIRST_E - Indicates which FWD reference field has been decoded first.
99259  *  0b0..FWD reference bottom field
99260  *  0b1..FWD reference top field
99261  */
99262 #define VPU_G1_SWREG3_SW_REFTOPFIRST_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_REFTOPFIRST_E_SHIFT)) & VPU_G1_SWREG3_SW_REFTOPFIRST_E_MASK)
99263 
99264 #define VPU_G1_SWREG3_SW_WRITE_MVS_E_MASK        (0x1000U)
99265 #define VPU_G1_SWREG3_SW_WRITE_MVS_E_SHIFT       (12U)
99266 /*! SW_WRITE_MVS_E - Direct mode motion vector write enable for current picture / VPX motion vector
99267  *    write enable for error concealment purposes:
99268  *  0b0..Writing disabled for current picture
99269  *  0b1..The direct mode motion vectors are written to external memory. H264 direct mode motion vectors are
99270  *       written to DPB aside with the corresponding reference picture. Other decoding mode dir mode mvs are written to
99271  *       external memory starting from sw_dir_mv_base.
99272  */
99273 #define VPU_G1_SWREG3_SW_WRITE_MVS_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_WRITE_MVS_E_SHIFT)) & VPU_G1_SWREG3_SW_WRITE_MVS_E_MASK)
99274 
99275 #define VPU_G1_SWREG3_SW_WEBP_E_MASK             (0x2000U)
99276 #define VPU_G1_SWREG3_SW_WEBP_E_SHIFT            (13U)
99277 #define VPU_G1_SWREG3_SW_WEBP_E(x)               (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_WEBP_E_SHIFT)) & VPU_G1_SWREG3_SW_WEBP_E_MASK)
99278 
99279 #define VPU_G1_SWREG3_SW_FILTERING_DIS_MASK      (0x4000U)
99280 #define VPU_G1_SWREG3_SW_FILTERING_DIS_SHIFT     (14U)
99281 /*! SW_FILTERING_DIS - De-block filtering disable:
99282  *  0b1..filtering is disabled for current picture
99283  *  0b0..filtering is enabled for current picture
99284  */
99285 #define VPU_G1_SWREG3_SW_FILTERING_DIS(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_FILTERING_DIS_SHIFT)) & VPU_G1_SWREG3_SW_FILTERING_DIS_MASK)
99286 
99287 #define VPU_G1_SWREG3_SW_DEC_OUT_DIS_MASK        (0x8000U)
99288 #define VPU_G1_SWREG3_SW_DEC_OUT_DIS_SHIFT       (15U)
99289 /*! SW_DEC_OUT_DIS - Disable decoder output picture writing:
99290  *  0b0..Decoder output picture is written to external memory
99291  *  0b1..Decoder output picture is not written to external memory
99292  */
99293 #define VPU_G1_SWREG3_SW_DEC_OUT_DIS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_OUT_DIS_SHIFT)) & VPU_G1_SWREG3_SW_DEC_OUT_DIS_MASK)
99294 
99295 #define VPU_G1_SWREG3_SW_REF_TOPFIELD_E_MASK     (0x10000U)
99296 #define VPU_G1_SWREG3_SW_REF_TOPFIELD_E_SHIFT    (16U)
99297 /*! SW_REF_TOPFIELD_E - Indicates which field should be used as reference if sw_ref_frames = '0':
99298  *  0b0..bottom field
99299  *  0b1..top field
99300  */
99301 #define VPU_G1_SWREG3_SW_REF_TOPFIELD_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_REF_TOPFIELD_E_SHIFT)) & VPU_G1_SWREG3_SW_REF_TOPFIELD_E_MASK)
99302 
99303 #define VPU_G1_SWREG3_SW_FWD_INTERLACE_E_MASK    (0x40000U)
99304 #define VPU_G1_SWREG3_SW_FWD_INTERLACE_E_SHIFT   (18U)
99305 /*! SW_FWD_INTERLACE_E - Coding mode of forward reference picture
99306  *  0b0..progressive
99307  *  0b1..interlaced
99308  */
99309 #define VPU_G1_SWREG3_SW_FWD_INTERLACE_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_FWD_INTERLACE_E_SHIFT)) & VPU_G1_SWREG3_SW_FWD_INTERLACE_E_MASK)
99310 
99311 #define VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_MASK     (0x80000U)
99312 #define VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_SHIFT    (19U)
99313 /*! SW_PIC_TOPFIELD_E - If field structure is enabled, this bit informs which one of the fields is being decoded:
99314  *  0b0..bottom field
99315  *  0b1..top field
99316  */
99317 #define VPU_G1_SWREG3_SW_PIC_TOPFIELD_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_MASK)
99318 
99319 #define VPU_G1_SWREG3_SW_PIC_INTER_E_MASK        (0x100000U)
99320 #define VPU_G1_SWREG3_SW_PIC_INTER_E_SHIFT       (20U)
99321 /*! SW_PIC_INTER_E - Picture type. Please also see SW_PIC_B_E.
99322  *  0b1..Inter type (P)
99323  *  0b0..Intra type (I)
99324  */
99325 #define VPU_G1_SWREG3_SW_PIC_INTER_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_INTER_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_INTER_E_MASK)
99326 
99327 #define VPU_G1_SWREG3_SW_PIC_B_E_MASK            (0x200000U)
99328 #define VPU_G1_SWREG3_SW_PIC_B_E_SHIFT           (21U)
99329 /*! SW_PIC_B_E - B picture enable for current picture:
99330  *  0b0..picture type is I or P depending on sw_pic_inter_e
99331  *  0b1..picture type is B depending on sw_pic_inter_e (not valid for H264 since it is slice based information)
99332  */
99333 #define VPU_G1_SWREG3_SW_PIC_B_E(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_B_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_B_E_MASK)
99334 
99335 #define VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_MASK    (0x400000U)
99336 #define VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_SHIFT   (22U)
99337 /*! SW_PIC_FIELDMODE_E - Structure of the current picture (residual structure)
99338  *  0b0..Frame structure. For H264, this means MBAFF structured picture for interlaced sequence
99339  *  0b1..Field structure
99340  */
99341 #define VPU_G1_SWREG3_SW_PIC_FIELDMODE_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_MASK)
99342 
99343 #define VPU_G1_SWREG3_SW_PIC_INTERLACE_E_MASK    (0x800000U)
99344 #define VPU_G1_SWREG3_SW_PIC_INTERLACE_E_SHIFT   (23U)
99345 /*! SW_PIC_INTERLACE_E - Coding mode of the current picture:
99346  *  0b0..progressive
99347  *  0b1..interlaced
99348  */
99349 #define VPU_G1_SWREG3_SW_PIC_INTERLACE_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_INTERLACE_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_INTERLACE_E_MASK)
99350 
99351 #define VPU_G1_SWREG3_SW_SKIP_MODE_MASK          (0x4000000U)
99352 #define VPU_G1_SWREG3_SW_SKIP_MODE_SHIFT         (26U)
99353 #define VPU_G1_SWREG3_SW_SKIP_MODE(x)            (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_SKIP_MODE_SHIFT)) & VPU_G1_SWREG3_SW_SKIP_MODE_MASK)
99354 
99355 #define VPU_G1_SWREG3_SW_RLC_MODE_E_MASK         (0x8000000U)
99356 #define VPU_G1_SWREG3_SW_RLC_MODE_E_SHIFT        (27U)
99357 /*! SW_RLC_MODE_E - RLC mode enable:
99358  *  0b1..HW decodes video from RLC input data + side information (Differential MV's, separate DC coeffs, Intra 4x4
99359  *       modes, MB control). Valid only for H.264 Baseline.
99360  *  0b0..HW decodes video from bit stream (VLC mode) + side information
99361  */
99362 #define VPU_G1_SWREG3_SW_RLC_MODE_E(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_RLC_MODE_E_SHIFT)) & VPU_G1_SWREG3_SW_RLC_MODE_E_MASK)
99363 
99364 #define VPU_G1_SWREG3_SW_DEC_MODE_MASK           (0xF0000000U)
99365 #define VPU_G1_SWREG3_SW_DEC_MODE_SHIFT          (28U)
99366 /*! SW_DEC_MODE - Decoding mode:
99367  *  0b0000..H.264
99368  *  0b0001..Reserved
99369  *  0b0010..Reserved
99370  *  0b0011..Reserved
99371  *  0b0100..Reserved
99372  *  0b0101..Reserved
99373  *  0b0110..Reserved
99374  *  0b0111..Reserved
99375  *  0b1000..Reserved
99376  *  0b1001..Reserved
99377  *  0b1010..VP8
99378  *  0b1011..Reserved
99379  *  0b1100..Reserved
99380  *  0b1101..Reserved
99381  *  0b1110..Reserved
99382  *  0b1111..Reserved
99383  */
99384 #define VPU_G1_SWREG3_SW_DEC_MODE(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_MODE_SHIFT)) & VPU_G1_SWREG3_SW_DEC_MODE_MASK)
99385 /*! @} */
99386 
99387 /*! @name SWREG12 - Base address for RLC data (RLC) / stream start address/decoded end addr register (VLC) */
99388 /*! @{ */
99389 
99390 #define VPU_G1_SWREG12_SW_RLC_VLC_BASE_MASK      (0xFFFFFFFFU)
99391 #define VPU_G1_SWREG12_SW_RLC_VLC_BASE_SHIFT     (0U)
99392 #define VPU_G1_SWREG12_SW_RLC_VLC_BASE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG12_SW_RLC_VLC_BASE_SHIFT)) & VPU_G1_SWREG12_SW_RLC_VLC_BASE_MASK)
99393 /*! @} */
99394 
99395 /*! @name SWREG13 - Base address for decoded picture */
99396 /*! @{ */
99397 
99398 #define VPU_G1_SWREG13_SW_DPB_ILACE_MODE_MASK    (0x2U)
99399 #define VPU_G1_SWREG13_SW_DPB_ILACE_MODE_SHIFT   (1U)
99400 /*! SW_DPB_ILACE_MODE - DPB ilaced mode: '0' : DPB consist of ilaced/progressive frames '1' : DPB
99401  *    consist of progressive frames / separate fields. This mode requires config support from HW
99402  */
99403 #define VPU_G1_SWREG13_SW_DPB_ILACE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG13_SW_DPB_ILACE_MODE_SHIFT)) & VPU_G1_SWREG13_SW_DPB_ILACE_MODE_MASK)
99404 
99405 #define VPU_G1_SWREG13_SW_DEC_OUT_BASE_MASK      (0xFFFFFFFCU)
99406 #define VPU_G1_SWREG13_SW_DEC_OUT_BASE_SHIFT     (2U)
99407 /*! SW_DEC_OUT_BASE - Video: Base address for decoder output picture. Points directly to start of decoder output picture or field. */
99408 #define VPU_G1_SWREG13_SW_DEC_OUT_BASE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG13_SW_DEC_OUT_BASE_SHIFT)) & VPU_G1_SWREG13_SW_DEC_OUT_BASE_MASK)
99409 /*! @} */
99410 
99411 /*! @name SWREG40 - Base address for standard dependent tables */
99412 /*! @{ */
99413 
99414 #define VPU_G1_SWREG40_SW_QTABLE_BASE_MASK       (0xFFFFFFFCU)
99415 #define VPU_G1_SWREG40_SW_QTABLE_BASE_SHIFT      (2U)
99416 /*! SW_QTABLE_BASE - Base address for standard dependent tables: */
99417 #define VPU_G1_SWREG40_SW_QTABLE_BASE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG40_SW_QTABLE_BASE_SHIFT)) & VPU_G1_SWREG40_SW_QTABLE_BASE_MASK)
99418 /*! @} */
99419 
99420 /*! @name SWREG41 - Base address for direct mode motion vectors */
99421 /*! @{ */
99422 
99423 #define VPU_G1_SWREG41_SW_DIR_MV_BASE_MASK       (0xFFFFFFFCU)
99424 #define VPU_G1_SWREG41_SW_DIR_MV_BASE_SHIFT      (2U)
99425 /*! SW_DIR_MV_BASE - Direct mode motion vector write/read base address. For H264 this is used only
99426  *    for direct mode motion vector write base. VP8: Motion vectors are written for error concealment
99427  *    purposes if sw_write_mvs is high. In error concealment mode motion vectors are read from this
99428  *    base address
99429  */
99430 #define VPU_G1_SWREG41_SW_DIR_MV_BASE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG41_SW_DIR_MV_BASE_SHIFT)) & VPU_G1_SWREG41_SW_DIR_MV_BASE_MASK)
99431 /*! @} */
99432 
99433 /*! @name SWREG48 - Error concealment register */
99434 /*! @{ */
99435 
99436 #define VPU_G1_SWREG48_SW_ERROR_CONC_MODE_MASK   (0x3000U)
99437 #define VPU_G1_SWREG48_SW_ERROR_CONC_MODE_SHIFT  (12U)
99438 /*! SW_ERROR_CONC_MODE - Error concealment mode:
99439  *  0b00..disabled (normal decoding mode)
99440  *  0b01..enabled for direct mode MV usage starting from MB defined by sw_startmb_x, sw_startmb_y
99441  */
99442 #define VPU_G1_SWREG48_SW_ERROR_CONC_MODE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG48_SW_ERROR_CONC_MODE_SHIFT)) & VPU_G1_SWREG48_SW_ERROR_CONC_MODE_MASK)
99443 
99444 #define VPU_G1_SWREG48_SW_STARTMB_Y_MASK         (0x7FC000U)
99445 #define VPU_G1_SWREG48_SW_STARTMB_Y_SHIFT        (14U)
99446 /*! SW_STARTMB_Y - Start MB from SW for Y dimension. Used in error concealment case as HW return
99447  *    value if HW founds an error or in HW init mb for error concealment if SW enables error concealment
99448  */
99449 #define VPU_G1_SWREG48_SW_STARTMB_Y(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG48_SW_STARTMB_Y_SHIFT)) & VPU_G1_SWREG48_SW_STARTMB_Y_MASK)
99450 
99451 #define VPU_G1_SWREG48_SW_STARTMB_X_MASK         (0xFF800000U)
99452 #define VPU_G1_SWREG48_SW_STARTMB_X_SHIFT        (23U)
99453 /*! SW_STARTMB_X - Start MB from SW for X dimension. Used in error concealment case as HW return
99454  *    value if HW founds an error or in HW init mb for error concealment if SW enables error concealment
99455  */
99456 #define VPU_G1_SWREG48_SW_STARTMB_X(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG48_SW_STARTMB_X_SHIFT)) & VPU_G1_SWREG48_SW_STARTMB_X_MASK)
99457 /*! @} */
99458 
99459 /*! @name SWREG49 - Prediction filter tap register for H264 */
99460 /*! @{ */
99461 
99462 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_MASK   (0xFFCU)
99463 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_SHIFT  (2U)
99464 /*! SW_PRED_BC_TAP_0_2 - Prediction filter set 0, tap 2 */
99465 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_SHIFT)) & VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_MASK)
99466 
99467 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_MASK   (0x3FF000U)
99468 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_SHIFT  (12U)
99469 /*! SW_PRED_BC_TAP_0_1 - Prediction filter set 0, tap 1 */
99470 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_SHIFT)) & VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_MASK)
99471 
99472 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_MASK   (0xFFC00000U)
99473 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_SHIFT  (22U)
99474 /*! SW_PRED_BC_TAP_0_0 - Prediction filter set 0, tap 0 */
99475 #define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_SHIFT)) & VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_MASK)
99476 /*! @} */
99477 
99478 /*! @name SWREG50 - Synthesis configuration register decoder 0 */
99479 /*! @{ */
99480 
99481 #define VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_MASK    (0x7FFU)
99482 #define VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT   (0U)
99483 /*! SW_DEC_MAX_OWIDTH - Max configured decoder video resolution that can be decoded. Informed as width of the picture in pixels. */
99484 #define VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT)) & VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_MASK)
99485 
99486 #define VPU_G1_SWREG50_SW_DEC_SOREN_PROF_MASK    (0x800U)
99487 #define VPU_G1_SWREG50_SW_DEC_SOREN_PROF_SHIFT   (11U)
99488 /*! SW_DEC_SOREN_PROF - Decoding format support, Sorenson
99489  *  0b0..not supported
99490  *  0b1..supported
99491  */
99492 #define VPU_G1_SWREG50_SW_DEC_SOREN_PROF(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_SOREN_PROF_SHIFT)) & VPU_G1_SWREG50_SW_DEC_SOREN_PROF_MASK)
99493 
99494 #define VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_MASK     (0x3000U)
99495 #define VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_SHIFT    (12U)
99496 /*! SW_DEC_BUS_WIDTH
99497  *  0b00..error
99498  *  0b01..32 bit bus
99499  *  0b10..64 bit bus
99500  *  0b11..128 bit bus
99501  */
99502 #define VPU_G1_SWREG50_SW_DEC_BUS_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_SHIFT)) & VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_MASK)
99503 
99504 #define VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_MASK     (0xC000U)
99505 #define VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_SHIFT    (14U)
99506 /*! SW_DEC_SYNTH_LAN
99507  *  0b00..error
99508  *  0b01..vhdl
99509  *  0b10..verilog
99510  */
99511 #define VPU_G1_SWREG50_SW_DEC_SYNTH_LAN(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_SHIFT)) & VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_MASK)
99512 
99513 #define VPU_G1_SWREG50_SW_DEC_BUS_STRD_MASK      (0xF0000U)
99514 #define VPU_G1_SWREG50_SW_DEC_BUS_STRD_SHIFT     (16U)
99515 /*! SW_DEC_BUS_STRD - Connected to standard bus:
99516  *  0b0000..error
99517  *  0b0001..AHB master, AHB slave
99518  *  0b0010..OCP master, OCP slave
99519  *  0b0011..AXI master, AXI slave
99520  *  0b0100..AXI master, APB slave
99521  *  0b0101..AXI master, AHB slave
99522  */
99523 #define VPU_G1_SWREG50_SW_DEC_BUS_STRD(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_BUS_STRD_SHIFT)) & VPU_G1_SWREG50_SW_DEC_BUS_STRD_MASK)
99524 
99525 #define VPU_G1_SWREG50_SW_REF_BUFF_EXIST_MASK    (0x100000U)
99526 #define VPU_G1_SWREG50_SW_REF_BUFF_EXIST_SHIFT   (20U)
99527 /*! SW_REF_BUFF_EXIST - Reference picture buffer usage:
99528  *  0b0..not supported
99529  *  0b1..reference buffer is used
99530  */
99531 #define VPU_G1_SWREG50_SW_REF_BUFF_EXIST(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_REF_BUFF_EXIST_SHIFT)) & VPU_G1_SWREG50_SW_REF_BUFF_EXIST_MASK)
99532 
99533 #define VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_MASK   (0x200000U)
99534 #define VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_SHIFT  (21U)
99535 /*! SW_DEC_OBUFF_LEVEL - Decoder output buffer level:
99536  *  0b0..1 MB buffering is used
99537  *  0b1..4 MB buffering is used
99538  */
99539 #define VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_SHIFT)) & VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_MASK)
99540 
99541 #define VPU_G1_SWREG50_SW_DEC_H264_PROF_MASK     (0x3000000U)
99542 #define VPU_G1_SWREG50_SW_DEC_H264_PROF_SHIFT    (24U)
99543 /*! SW_DEC_H264_PROF - Decoding format support, H.264
99544  *  0b00..not supported
99545  *  0b01..supported up to baseline profile
99546  *  0b10..supported up to high profile labeled stream with restricted high profile tools (Tools that are used in Hantro 7280, 8270 encoder)
99547  *  0b11..supported up to high profile
99548  */
99549 #define VPU_G1_SWREG50_SW_DEC_H264_PROF(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_H264_PROF_SHIFT)) & VPU_G1_SWREG50_SW_DEC_H264_PROF_MASK)
99550 /*! @} */
99551 
99552 /*! @name SWREG51 - Reference picture buffer control register */
99553 /*! @{ */
99554 
99555 #define VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_MASK    (0x1FFU)
99556 #define VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_SHIFT   (0U)
99557 /*! SW_REFBU_Y_OFFSET - Y offset for refbufferd. This coordinate is used to compensate the global motion of the video for better buffer hit rate */
99558 #define VPU_G1_SWREG51_SW_REFBU_Y_OFFSET(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_MASK)
99559 
99560 #define VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_MASK   (0x1000U)
99561 #define VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_SHIFT  (12U)
99562 /*! SW_REFBU_FPARMOD_E - Field parity mode enable. Used in refbufferd evaluation mode.
99563  *  0b0..use the result field of the evaluation
99564  *  0b1..use the parity mode field
99565  */
99566 #define VPU_G1_SWREG51_SW_REFBU_FPARMOD_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_MASK)
99567 
99568 #define VPU_G1_SWREG51_SW_REFBU_EVAL_E_MASK      (0x2000U)
99569 #define VPU_G1_SWREG51_SW_REFBU_EVAL_E_SHIFT     (13U)
99570 /*! SW_REFBU_EVAL_E - Enable for HW internal reference ID calculation. If given threshold level is
99571  *    reached by any picture_id after first MB row, that picture_id is used for reference buffer fill
99572  *    for rest of the picture
99573  */
99574 #define VPU_G1_SWREG51_SW_REFBU_EVAL_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_EVAL_E_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_EVAL_E_MASK)
99575 
99576 #define VPU_G1_SWREG51_SW_REFBU_PICID_MASK       (0x7C000U)
99577 #define VPU_G1_SWREG51_SW_REFBU_PICID_SHIFT      (14U)
99578 /*! SW_REFBU_PICID - The used reference picture ID for reference buffer usage */
99579 #define VPU_G1_SWREG51_SW_REFBU_PICID(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_PICID_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_PICID_MASK)
99580 
99581 #define VPU_G1_SWREG51_SW_REFBU_THR_MASK         (0x7FF80000U)
99582 #define VPU_G1_SWREG51_SW_REFBU_THR_SHIFT        (19U)
99583 /*! SW_REFBU_THR - Reference buffer disable threshold value (cache miss amount). Used to buffer shut down (if more misses than allowed) */
99584 #define VPU_G1_SWREG51_SW_REFBU_THR(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_THR_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_THR_MASK)
99585 
99586 #define VPU_G1_SWREG51_SW_REFBU_E_MASK           (0x80000000U)
99587 #define VPU_G1_SWREG51_SW_REFBU_E_SHIFT          (31U)
99588 /*! SW_REFBU_E - Refer picture buffer enable:
99589  *  0b0..refer picture buffer disabled
99590  *  0b1..refer picture buffer enabled. Valid if picture size is QVGA or more.
99591  */
99592 #define VPU_G1_SWREG51_SW_REFBU_E(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_E_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_E_MASK)
99593 /*! @} */
99594 
99595 /*! @name SWREG52 - Reference picture buffer information register 1 */
99596 /*! @{ */
99597 
99598 #define VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_MASK   (0xFFFFU)
99599 #define VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_SHIFT  (0U)
99600 /*! SW_REFBU_INTRA_SUM - The sum of the luminance 8x8 intra partitions of the picture. The
99601  *    proceeding of the HW calculation can be read during HW decoding.
99602  */
99603 #define VPU_G1_SWREG52_SW_REFBU_INTRA_SUM(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_SHIFT)) & VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_MASK)
99604 
99605 #define VPU_G1_SWREG52_SW_REFBU_HIT_SUM_MASK     (0xFFFF0000U)
99606 #define VPU_G1_SWREG52_SW_REFBU_HIT_SUM_SHIFT    (16U)
99607 /*! SW_REFBU_HIT_SUM - The sum of the refbufferd hits of the picture. Determined for each 8x8
99608  *    luminance partition of the picture. The proceeding of the HW calculation can be read during HW
99609  *    decoding.
99610  */
99611 #define VPU_G1_SWREG52_SW_REFBU_HIT_SUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG52_SW_REFBU_HIT_SUM_SHIFT)) & VPU_G1_SWREG52_SW_REFBU_HIT_SUM_MASK)
99612 /*! @} */
99613 
99614 /*! @name SWREG53 - Reference picture buffer information register 2 */
99615 /*! @{ */
99616 
99617 #define VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_MASK    (0x3FFFFFU)
99618 #define VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_SHIFT   (0U)
99619 /*! SW_REFBU_Y_MV_SUM - The sum of the decoded motion vector y-components of the picture. The first
99620  *    luminance motion vector of each MB is used in calculation. Other motion vectors of the MB are
99621  *    discarded. Each motion vector is saturated between -256 - 255 before calculation. The
99622  *    proceeding of the HW calculation can be read during HW decoding.
99623  */
99624 #define VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_SHIFT)) & VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_MASK)
99625 /*! @} */
99626 
99627 /*! @name SWREG54 - Synthesis configuration register decoder 1 */
99628 /*! @{ */
99629 
99630 #define VPU_G1_SWREG54_SW_DEC_CORE_AM_MASK       (0x380U)
99631 #define VPU_G1_SWREG54_SW_DEC_CORE_AM_SHIFT      (7U)
99632 /*! SW_DEC_CORE_AM - Decoder core amount. If other than 0, the multicore can be used. Each
99633  *    individual cores can be identified from corresponding core ID register:
99634  *  0b000..single core decoder
99635  *  0b001..dual core decoder
99636  *  0b010..3 core decoder
99637  *  0b011..4 core decoder
99638  *  0b100..5 core decoder
99639  *  0b101..6 core decoder
99640  *  0b110..7 core decoder
99641  *  0b111..8 core decoder
99642  */
99643 #define VPU_G1_SWREG54_SW_DEC_CORE_AM(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_CORE_AM_SHIFT)) & VPU_G1_SWREG54_SW_DEC_CORE_AM_MASK)
99644 
99645 #define VPU_G1_SWREG54_SW_DPB_FIELD_E_MASK       (0x400U)
99646 #define VPU_G1_SWREG54_SW_DPB_FIELD_E_SHIFT      (10U)
99647 /*! SW_DPB_FIELD_E - DPB field separate mode support for ilaced content:
99648  *  0b0..Not supported. For ilaced content, DPB is ilaced frame order.
99649  *  0b1..Supported. For ilaced content, DPB can consist of ilaced frames or separate fields (TOP/BOT).
99650  */
99651 #define VPU_G1_SWREG54_SW_DPB_FIELD_E(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DPB_FIELD_E_SHIFT)) & VPU_G1_SWREG54_SW_DPB_FIELD_E_MASK)
99652 
99653 #define VPU_G1_SWREG54_SW_VP8_STRIDE_E_MASK      (0x800U)
99654 #define VPU_G1_SWREG54_SW_VP8_STRIDE_E_SHIFT     (11U)
99655 /*! SW_VP8_STRIDE_E - Decoder output stride support for VP8. Separate base addresses for Y/C data
99656  *    and possibility to set scanline bigger than picture width:
99657  *  0b0..not supported, Y and C tables attached.
99658  *  0b1..supported, Y and C tables can be set freely.
99659  */
99660 #define VPU_G1_SWREG54_SW_VP8_STRIDE_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_VP8_STRIDE_E_SHIFT)) & VPU_G1_SWREG54_SW_VP8_STRIDE_E_MASK)
99661 
99662 #define VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_MASK   (0x3000U)
99663 #define VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_SHIFT  (12U)
99664 /*! SW_DEC_ERRCO_LEVEL - Decoder error concealment support level:
99665  *  0b00..Error concealment not supported (only error detection)
99666  *  0b01..VP8 direct mode motion vector error concealment supported
99667  */
99668 #define VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_SHIFT)) & VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_MASK)
99669 
99670 #define VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_MASK    (0xC000U)
99671 #define VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT   (14U)
99672 /*! SW_DEC_MAX_OW_EXT - Max configured decoder video resolution that can be decoded. This is the MSB part of the configuration signal */
99673 #define VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT)) & VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_MASK)
99674 
99675 #define VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_MASK     (0x10000U)
99676 #define VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_SHIFT    (16U)
99677 /*! SW_DEC_VP8S_ARCH - VP8 Architecture type (for prediction)
99678  *  0b0..Same prediction architecture as for other decoding formats
99679  *  0b1..Dedicated small architecture for VP8 (refbuffer cannot be used either)
99680  */
99681 #define VPU_G1_SWREG54_SW_DEC_VP8S_ARCH(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_SHIFT)) & VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_MASK)
99682 
99683 #define VPU_G1_SWREG54_SW_DEC_TILED_L_MASK       (0x60000U)
99684 #define VPU_G1_SWREG54_SW_DEC_TILED_L_SHIFT      (17U)
99685 /*! SW_DEC_TILED_L - Tiled mode support level
99686  *  0b00..not supported
99687  *  0b01..supported with 8x4 tile size for progressive content
99688  *  0b10..supported with 8x4 tile size for progressive/ilaced content
99689  */
99690 #define VPU_G1_SWREG54_SW_DEC_TILED_L(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_TILED_L_SHIFT)) & VPU_G1_SWREG54_SW_DEC_TILED_L_MASK)
99691 
99692 #define VPU_G1_SWREG54_SW_DEC_WEBP_E_MASK        (0x80000U)
99693 #define VPU_G1_SWREG54_SW_DEC_WEBP_E_SHIFT       (19U)
99694 /*! SW_DEC_WEBP_E - Decoding format support, Web-p
99695  *  0b0..not supported bigger than 1080p resolution
99696  *  0b1..supported upto 16kx16k pixel resolution (defined max)
99697  */
99698 #define VPU_G1_SWREG54_SW_DEC_WEBP_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_WEBP_E_SHIFT)) & VPU_G1_SWREG54_SW_DEC_WEBP_E_MASK)
99699 
99700 #define VPU_G1_SWREG54_SW_DEC_MVC_PROF_MASK      (0x100000U)
99701 #define VPU_G1_SWREG54_SW_DEC_MVC_PROF_SHIFT     (20U)
99702 /*! SW_DEC_MVC_PROF - Decoding format support, MVC
99703  *  0b0..not supported
99704  *  0b1..supported
99705  */
99706 #define VPU_G1_SWREG54_SW_DEC_MVC_PROF(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_MVC_PROF_SHIFT)) & VPU_G1_SWREG54_SW_DEC_MVC_PROF_MASK)
99707 
99708 #define VPU_G1_SWREG54_SW_DEC_VP8_PROF_MASK      (0x800000U)
99709 #define VPU_G1_SWREG54_SW_DEC_VP8_PROF_SHIFT     (23U)
99710 /*! SW_DEC_VP8_PROF - Decoding format support, VP8
99711  *  0b0..not supported
99712  *  0b1..supported
99713  */
99714 #define VPU_G1_SWREG54_SW_DEC_VP8_PROF(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_VP8_PROF_SHIFT)) & VPU_G1_SWREG54_SW_DEC_VP8_PROF_MASK)
99715 
99716 #define VPU_G1_SWREG54_SW_DEC_RTL_ROM_MASK       (0x2000000U)
99717 #define VPU_G1_SWREG54_SW_DEC_RTL_ROM_SHIFT      (25U)
99718 /*! SW_DEC_RTL_ROM - ROM implementation type (If design includes ROMs)
99719  *  0b0..ROMs are implemented from actual ROM units
99720  *  0b1..ROMs are implemented from RTL
99721  */
99722 #define VPU_G1_SWREG54_SW_DEC_RTL_ROM(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_RTL_ROM_SHIFT)) & VPU_G1_SWREG54_SW_DEC_RTL_ROM_MASK)
99723 
99724 #define VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_MASK   (0x10000000U)
99725 #define VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_SHIFT  (28U)
99726 /*! SW_REF_BUFF2_EXIST - Reference picture buffer 2 usage:
99727  *  0b0..not supported
99728  *  0b1..reference buffer 2 is used
99729  */
99730 #define VPU_G1_SWREG54_SW_REF_BUFF2_EXIST(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_SHIFT)) & VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_MASK)
99731 
99732 #define VPU_G1_SWREG54_SW_DEC_DIVX_PROF_MASK     (0x20000000U)
99733 #define VPU_G1_SWREG54_SW_DEC_DIVX_PROF_SHIFT    (29U)
99734 /*! SW_DEC_DIVX_PROF - DIVX Support:
99735  *  0b0..not supported
99736  *  0b1..supported
99737  */
99738 #define VPU_G1_SWREG54_SW_DEC_DIVX_PROF(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_DIVX_PROF_SHIFT)) & VPU_G1_SWREG54_SW_DEC_DIVX_PROF_MASK)
99739 
99740 #define VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_MASK   (0x40000000U)
99741 #define VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_SHIFT  (30U)
99742 /*! SW_DEC_REFBU_ILACE - Refbufferd support for interlaced content:
99743  *  0b0..not supported
99744  *  0b1..supported
99745  */
99746 #define VPU_G1_SWREG54_SW_DEC_REFBU_ILACE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_SHIFT)) & VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_MASK)
99747 /*! @} */
99748 
99749 /*! @name SWREG55 - Reference picture buffer 2 / Advanced prefetch control register */
99750 /*! @{ */
99751 
99752 #define VPU_G1_SWREG55_SW_APF_THRESHOLD_MASK     (0x3FFFU)
99753 #define VPU_G1_SWREG55_SW_APF_THRESHOLD_SHIFT    (0U)
99754 /*! SW_APF_THRESHOLD - G1 decoder and later :Advanced prefetch threshold value. If current MB
99755  *    exceeds the threshold the advanced mode is not used. Value 0 disables threshold usage and advanced
99756  *    prefetch usage is restricted by internal memory limitation only
99757  */
99758 #define VPU_G1_SWREG55_SW_APF_THRESHOLD(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_APF_THRESHOLD_SHIFT)) & VPU_G1_SWREG55_SW_APF_THRESHOLD_MASK)
99759 
99760 #define VPU_G1_SWREG55_SW_REFBU2_PICID_MASK      (0x7C000U)
99761 #define VPU_G1_SWREG55_SW_REFBU2_PICID_SHIFT     (14U)
99762 /*! SW_REFBU2_PICID - The used reference picture ID for reference buffer usage */
99763 #define VPU_G1_SWREG55_SW_REFBU2_PICID(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_REFBU2_PICID_SHIFT)) & VPU_G1_SWREG55_SW_REFBU2_PICID_MASK)
99764 
99765 #define VPU_G1_SWREG55_SW_REFBU2_THR_MASK        (0x7FF80000U)
99766 #define VPU_G1_SWREG55_SW_REFBU2_THR_SHIFT       (19U)
99767 /*! SW_REFBU2_THR - Reference buffer disable threshold value (buffer miss amount). Used to buffer shut down (if more misses than allowed) */
99768 #define VPU_G1_SWREG55_SW_REFBU2_THR(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_REFBU2_THR_SHIFT)) & VPU_G1_SWREG55_SW_REFBU2_THR_MASK)
99769 
99770 #define VPU_G1_SWREG55_SW_REFBU2_BUF_E_MASK      (0x80000000U)
99771 #define VPU_G1_SWREG55_SW_REFBU2_BUF_E_SHIFT     (31U)
99772 /*! SW_REFBU2_BUF_E - Refer picture buffer 2 enable:
99773  *  0b0..refer picture buffer disabled
99774  *  0b1..refer picture buffer enabled. Valid if picture size is QVGA or more (can be turned of by HW if threshold value reached).
99775  */
99776 #define VPU_G1_SWREG55_SW_REFBU2_BUF_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_REFBU2_BUF_E_SHIFT)) & VPU_G1_SWREG55_SW_REFBU2_BUF_E_MASK)
99777 /*! @} */
99778 
99779 /*! @name SWREG56 - Reference buffer information register 3 */
99780 /*! @{ */
99781 
99782 #define VPU_G1_SWREG56_SW_REFBU_BOT_SUM_MASK     (0xFFFFU)
99783 #define VPU_G1_SWREG56_SW_REFBU_BOT_SUM_SHIFT    (0U)
99784 /*! SW_REFBU_BOT_SUM - The sum of the bottom partitions of the picture */
99785 #define VPU_G1_SWREG56_SW_REFBU_BOT_SUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG56_SW_REFBU_BOT_SUM_SHIFT)) & VPU_G1_SWREG56_SW_REFBU_BOT_SUM_MASK)
99786 
99787 #define VPU_G1_SWREG56_SW_REFBU_TOP_SUM_MASK     (0xFFFF0000U)
99788 #define VPU_G1_SWREG56_SW_REFBU_TOP_SUM_SHIFT    (16U)
99789 /*! SW_REFBU_TOP_SUM - The sum of the top partitions of the picture */
99790 #define VPU_G1_SWREG56_SW_REFBU_TOP_SUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG56_SW_REFBU_TOP_SUM_SHIFT)) & VPU_G1_SWREG56_SW_REFBU_TOP_SUM_MASK)
99791 /*! @} */
99792 
99793 /*! @name SWREG57 - Decoder fuse register */
99794 /*! @{ */
99795 
99796 #define VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_MASK   (0x80U)
99797 #define VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_SHIFT  (7U)
99798 /*! FUSE_DEC_REFBUFFER - 1 = reference buffer used */
99799 #define VPU_G1_SWREG57_FUSE_DEC_REFBUFFER(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_MASK)
99800 
99801 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_352_MASK    (0x1000U)
99802 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_352_SHIFT   (12U)
99803 /*! FUSE_DEC_MAXW_352 - 1 = Max video width up to 352 pixels enabled. Priority coded with priority 5. */
99804 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_352(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_352_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_352_MASK)
99805 
99806 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_720_MASK    (0x2000U)
99807 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_720_SHIFT   (13U)
99808 /*! FUSE_DEC_MAXW_720 - 1 = Max video width up to 720 pixels enabled. Priority coded with priority 4. */
99809 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_720(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_720_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_720_MASK)
99810 
99811 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_MASK   (0x4000U)
99812 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_SHIFT  (14U)
99813 /*! FUSE_DEC_MAXW_1280 - 1 = Max video width up to 1280 pixels enabled. Priority coded with priority 3. */
99814 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_1280(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_MASK)
99815 
99816 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_MASK   (0x8000U)
99817 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_SHIFT  (15U)
99818 /*! FUSE_DEC_MAXW_1920 - 1 = Max video width up to 1920 pixels enabled. Priority coded with priority 2. */
99819 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_1920(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_MASK)
99820 
99821 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_MASK     (0x10000U)
99822 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_SHIFT    (16U)
99823 /*! FUSE_DEC_MAXW_4K - 1 = Max video width up to 4096 pixels enabled. Priority coded with priority 1. */
99824 #define VPU_G1_SWREG57_FUSE_DEC_MAXW_4K(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_MASK)
99825 
99826 #define VPU_G1_SWREG57_FUSE_DEC_MVC_MASK         (0x40000U)
99827 #define VPU_G1_SWREG57_FUSE_DEC_MVC_SHIFT        (18U)
99828 /*! FUSE_DEC_MVC - 1 = MVC enabled (requires also H264 to be enabled) */
99829 #define VPU_G1_SWREG57_FUSE_DEC_MVC(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MVC_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MVC_MASK)
99830 
99831 #define VPU_G1_SWREG57_FUSE_DEC_VP8_MASK         (0x100000U)
99832 #define VPU_G1_SWREG57_FUSE_DEC_VP8_SHIFT        (20U)
99833 /*! FUSE_DEC_VP8 - 1 = VP8 enabled */
99834 #define VPU_G1_SWREG57_FUSE_DEC_VP8(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_VP8_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_VP8_MASK)
99835 
99836 #define VPU_G1_SWREG57_FUSE_DEC_H264_MASK        (0x80000000U)
99837 #define VPU_G1_SWREG57_FUSE_DEC_H264_SHIFT       (31U)
99838 /*! FUSE_DEC_H264 - 1 = H.264 enabled */
99839 #define VPU_G1_SWREG57_FUSE_DEC_H264(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_H264_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_H264_MASK)
99840 /*! @} */
99841 
99842 /*! @name SWREG58 - Device configuration register decoder 2 + Multi core control register */
99843 /*! @{ */
99844 
99845 #define VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_MASK   (0x7FE0000U)
99846 #define VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_SHIFT  (17U)
99847 /*! SW_DEC_MC_POLLTIME - sw_dec_mc_polltime definition depends on sw_dec_mc_mode. */
99848 #define VPU_G1_SWREG58_SW_DEC_MC_POLLTIME(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_SHIFT)) & VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_MASK)
99849 
99850 #define VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_MASK   (0x18000000U)
99851 #define VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_SHIFT  (27U)
99852 /*! SW_DEC_MC_POLLMODE - Decoder multicore status reading mode:
99853  *  0b00..HW internal status polling mechanism is used. Status of reference picture is read only when required
99854  *        coordinate for the reference picture is not big enough. If the status is still not big enough after reading
99855  *        it the HW waits N clock cycles per pixel from the coordinate difference. The N is defined by the
99856  *        sw_dec_mc_polltime (range 0...4).
99857  *  0b01..Dummy status polling mechanism is used for all reference pictures. HW reads status of all reference
99858  *        pictures at frequency defined by sw_dec_mc_polltime.
99859  */
99860 #define VPU_G1_SWREG58_SW_DEC_MC_POLLMODE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_SHIFT)) & VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_MASK)
99861 
99862 #define VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_MASK   (0x20000000U)
99863 #define VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_SHIFT  (29U)
99864 /*! SW_DEC_WRITESTAT_E - Decoder write statusword enable. Must be high if multi core decoding
99865  *    enabled. HW writes output picture data proceeding to external memory after picture data (and after
99866  *    H264 direct mode MVS if they exist)
99867  */
99868 #define VPU_G1_SWREG58_SW_DEC_WRITESTAT_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_SHIFT)) & VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_MASK)
99869 
99870 #define VPU_G1_SWREG58_SW_DEC_MULTICORE_E_MASK   (0x40000000U)
99871 #define VPU_G1_SWREG58_SW_DEC_MULTICORE_E_SHIFT  (30U)
99872 /*! SW_DEC_MULTICORE_E - Decoder multi core enable:
99873  *  0b0..Multi core disabled or only one core exists in design.
99874  *  0b1..Multi core enable. Each reference picture status must be verified from external memory status field
99875  *       before usage. 128 bits status word exists after each reference picture and include picture proceeding
99876  *       coordinates Y and X.
99877  */
99878 #define VPU_G1_SWREG58_SW_DEC_MULTICORE_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_MULTICORE_E_SHIFT)) & VPU_G1_SWREG58_SW_DEC_MULTICORE_E_MASK)
99879 
99880 #define VPU_G1_SWREG58_SW_SERV_MERGE_DIS_MASK    (0x80000000U)
99881 #define VPU_G1_SWREG58_SW_SERV_MERGE_DIS_SHIFT   (31U)
99882 /*! SW_SERV_MERGE_DIS - Decoder service merge disable:
99883  *  0b0..HW merges simultaneous sub-block requests internally if they are same type (read or write).
99884  *  0b1..decoder serves one sub-block per service and merging is disabled.
99885  */
99886 #define VPU_G1_SWREG58_SW_SERV_MERGE_DIS(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_SERV_MERGE_DIS_SHIFT)) & VPU_G1_SWREG58_SW_SERV_MERGE_DIS_MASK)
99887 /*! @} */
99888 
99889 /*! @name SWREG59 - H264 Chrominance 8 pixel interleaved data base */
99890 /*! @{ */
99891 
99892 #define VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_MASK   (0xFFFFFFFCU)
99893 #define VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_SHIFT  (2U)
99894 /*! SW_DEC_CH8PIX_BASE - Base address for additional chrominance data format where chrominance is
99895  *    interleaved in group of 8 pixels. The usage is enabled by sw_ch_8pix_ileav_e
99896  */
99897 #define VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_SHIFT)) & VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_MASK)
99898 /*! @} */
99899 
99900 /*! @name SWREG60 - Interrupt register post-processor */
99901 /*! @{ */
99902 
99903 #define VPU_G1_SWREG60_SW_PP_E_MASK              (0x1U)
99904 #define VPU_G1_SWREG60_SW_PP_E_SHIFT             (0U)
99905 /*! SW_PP_E - External mode post-processing enable. This bit will start the post-processing
99906  *    operation. Not to be used if PP is in pipeline with decoder (sw_pp_pipeline_e = 1). HW will reset this
99907  *    when picture is post-processed.
99908  */
99909 #define VPU_G1_SWREG60_SW_PP_E(x)                (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_E_SHIFT)) & VPU_G1_SWREG60_SW_PP_E_MASK)
99910 
99911 #define VPU_G1_SWREG60_SW_PP_PIPELINE_E_MASK     (0x2U)
99912 #define VPU_G1_SWREG60_SW_PP_PIPELINE_E_SHIFT    (1U)
99913 /*! SW_PP_PIPELINE_E - Decoder - post-processing pipeline enable:
99914  *  0b0..Post-processing is processing different picture than decoder or is disabled
99915  *  0b1..Post-processing is performed in pipeline with decoder
99916  */
99917 #define VPU_G1_SWREG60_SW_PP_PIPELINE_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_PIPELINE_E_SHIFT)) & VPU_G1_SWREG60_SW_PP_PIPELINE_E_MASK)
99918 
99919 #define VPU_G1_SWREG60_SW_PP_IRQ_DIS_MASK        (0x10U)
99920 #define VPU_G1_SWREG60_SW_PP_IRQ_DIS_SHIFT       (4U)
99921 /*! SW_PP_IRQ_DIS - Post-processor IRQ disable. When high, there are no interrupts from HW
99922  *    concerning post processing. Polling must be used to see the interrupt
99923  */
99924 #define VPU_G1_SWREG60_SW_PP_IRQ_DIS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_IRQ_DIS_SHIFT)) & VPU_G1_SWREG60_SW_PP_IRQ_DIS_MASK)
99925 
99926 #define VPU_G1_SWREG60_SW_PP_IRQ_MASK            (0x100U)
99927 #define VPU_G1_SWREG60_SW_PP_IRQ_SHIFT           (8U)
99928 /*! SW_PP_IRQ - Post-processor IRQ. SW will reset this after interrupt is handled. HINTpp is not
99929  *    used for pp if IRQ disable pp is high (sw_pp_irq_n_e = 1). In pipeline mode this bit is not used
99930  */
99931 #define VPU_G1_SWREG60_SW_PP_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_IRQ_SHIFT)) & VPU_G1_SWREG60_SW_PP_IRQ_MASK)
99932 
99933 #define VPU_G1_SWREG60_SW_PP_RDY_INT_MASK        (0x1000U)
99934 #define VPU_G1_SWREG60_SW_PP_RDY_INT_SHIFT       (12U)
99935 /*! SW_PP_RDY_INT - Interrupt status bit pp. When this bit is high post processor has processed a
99936  *    picture in external mode. In pipeline mode this bit is not used.
99937  */
99938 #define VPU_G1_SWREG60_SW_PP_RDY_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_RDY_INT_SHIFT)) & VPU_G1_SWREG60_SW_PP_RDY_INT_MASK)
99939 
99940 #define VPU_G1_SWREG60_SW_PP_BUS_INT_MASK        (0x2000U)
99941 #define VPU_G1_SWREG60_SW_PP_BUS_INT_SHIFT       (13U)
99942 /*! SW_PP_BUS_INT - Interrupt status bit bus. Error response from bus. In pipeline mode this bit is not used */
99943 #define VPU_G1_SWREG60_SW_PP_BUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_BUS_INT_SHIFT)) & VPU_G1_SWREG60_SW_PP_BUS_INT_MASK)
99944 /*! @} */
99945 
99946 /*! @name SWREG61 - Device configuration register post-processor */
99947 /*! @{ */
99948 
99949 #define VPU_G1_SWREG61_SW_PP_MAX_BURST_MASK      (0x1FU)
99950 #define VPU_G1_SWREG61_SW_PP_MAX_BURST_SHIFT     (0U)
99951 /*! SW_PP_MAX_BURST - Maximum burst length for PP bus transactions. */
99952 #define VPU_G1_SWREG61_SW_PP_MAX_BURST(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_MAX_BURST_SHIFT)) & VPU_G1_SWREG61_SW_PP_MAX_BURST_MASK)
99953 
99954 #define VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_MASK   (0x20U)
99955 #define VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_SHIFT  (5U)
99956 /*! SW_PP_OUT_SWAP32_E - PP output data word swap (may be used for 64 bit environment):
99957  *  0b0..no swapping of 32 bit words
99958  *  0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order (also little endian should be enabled))
99959  */
99960 #define VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_MASK)
99961 
99962 #define VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_MASK     (0x40U)
99963 #define VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_SHIFT    (6U)
99964 /*! SW_PP_OUT_ENDIAN - PP output picture endian mode for YCbCr data or for any data if config value SW_PP_OEN_VERSION = 1.
99965  *  0b0..Big endian (0-1-2-3 order)
99966  *  0b1..Little endian (3-2-1-0 order)
99967  */
99968 #define VPU_G1_SWREG61_SW_PP_OUT_ENDIAN(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_SHIFT)) & VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_MASK)
99969 
99970 #define VPU_G1_SWREG61_SW_PP_IN_ENDIAN_MASK      (0x80U)
99971 #define VPU_G1_SWREG61_SW_PP_IN_ENDIAN_SHIFT     (7U)
99972 /*! SW_PP_IN_ENDIAN - PP input picture byte endian mode. Used only if PP is in standalone mode. If
99973  *    PP is running pipelined with the decoder, this bit has no effect.
99974  *  0b0..Big endian (0-1-2-3 order)
99975  *  0b1..Little endian (3-2-1-0 order)
99976  */
99977 #define VPU_G1_SWREG61_SW_PP_IN_ENDIAN(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_ENDIAN_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_ENDIAN_MASK)
99978 
99979 #define VPU_G1_SWREG61_SW_PP_CLK_GATE_E_MASK     (0x100U)
99980 #define VPU_G1_SWREG61_SW_PP_CLK_GATE_E_SHIFT    (8U)
99981 /*! SW_PP_CLK_GATE_E - PP dynamic clock gating enable.
99982  *  0b1..Clock is gated from PP structures that are not used
99983  *  0b0..Clock is running for all PP structures
99984  */
99985 #define VPU_G1_SWREG61_SW_PP_CLK_GATE_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_CLK_GATE_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_CLK_GATE_E_MASK)
99986 
99987 #define VPU_G1_SWREG61_SW_PP_DATA_DISC_E_MASK    (0x200U)
99988 #define VPU_G1_SWREG61_SW_PP_DATA_DISC_E_SHIFT   (9U)
99989 /*! SW_PP_DATA_DISC_E - PP data discard enable. Precise burst lengths are used with reading
99990  *    services. Extra data is discarded internally. Note. If AHB maxburst 17 is used data discard cannot be
99991  *    enabled (causes conflict)
99992  */
99993 #define VPU_G1_SWREG61_SW_PP_DATA_DISC_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_DATA_DISC_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_DATA_DISC_E_MASK)
99994 
99995 #define VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_MASK    (0x400U)
99996 #define VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_SHIFT   (10U)
99997 /*! SW_PP_IN_SWAP32_E - PP input 32bit data swap (may be used for 64 bit environment):
99998  *  0b0..no swapping of 32 bit words
99999  *  0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
100000  */
100001 #define VPU_G1_SWREG61_SW_PP_IN_SWAP32_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_MASK)
100002 
100003 #define VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_MASK   (0x800U)
100004 #define VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_SHIFT  (11U)
100005 /*! SW_PP_IN_A1_ENDIAN - Alpha blend source 1 input data byte endian mode.
100006  *  0b0..Big endian (0-1-2-3 order)
100007  *  0b1..Little endian (3-2-1-0 order)
100008  */
100009 #define VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_MASK)
100010 
100011 #define VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_MASK   (0x1000U)
100012 #define VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_SHIFT  (12U)
100013 /*! SW_PP_IN_A1_SWAP32 - Alpha blend source 1 input 32bit data swap (may be used for 64 bit environment):
100014  *  0b0..no swapping of 32 bit words
100015  *  0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
100016  */
100017 #define VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_MASK)
100018 
100019 #define VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_MASK   (0x2000U)
100020 #define VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_SHIFT  (13U)
100021 /*! SW_PP_IN_A2_ENDSEL - Endian/swap select for Alpha blend input source 2:
100022  *  0b0..Use PP in endian/swap definitions (sw_pp_in_endian, sw_pp_in_swap)
100023  *  0b1..Use Ablend source 1 endian/swap definitions (sw_pp_in_a1_endian, sw_pp_in_a1_swap)
100024  */
100025 #define VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_MASK)
100026 
100027 #define VPU_G1_SWREG61_SW_PP_SCMD_DIS_MASK       (0x4000U)
100028 #define VPU_G1_SWREG61_SW_PP_SCMD_DIS_SHIFT      (14U)
100029 /*! SW_PP_SCMD_DIS - 9170 decoder: AXI Single Command Multiple Data disable. 9170 axi wrapper
100030  *    supports this mode by default (where only the first addresses of the burst are given from address
100031  *    generator). This bit is used to disable the feature (possible SW workaround if something is not
100032  *    working correctly)
100033  */
100034 #define VPU_G1_SWREG61_SW_PP_SCMD_DIS(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_SCMD_DIS_SHIFT)) & VPU_G1_SWREG61_SW_PP_SCMD_DIS_MASK)
100035 
100036 #define VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_MASK    (0x8000U)
100037 #define VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_SHIFT   (15U)
100038 /*! SW_PP_AHB_HLOCK_E - AHB master HLOCK enable. When high the service is locked to pp as long as it
100039  *    needs the bus (whenever pp requests the bus it will be granted)
100040  */
100041 #define VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_MASK)
100042 
100043 #define VPU_G1_SWREG61_SW_PP_AXI_WR_ID_MASK      (0xFF0000U)
100044 #define VPU_G1_SWREG61_SW_PP_AXI_WR_ID_SHIFT     (16U)
100045 /*! SW_PP_AXI_WR_ID - Write ID used for AXI PP write services (if connected to AXI) */
100046 #define VPU_G1_SWREG61_SW_PP_AXI_WR_ID(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_AXI_WR_ID_SHIFT)) & VPU_G1_SWREG61_SW_PP_AXI_WR_ID_MASK)
100047 
100048 #define VPU_G1_SWREG61_SW_PP_AXI_RD_ID_MASK      (0xFF000000U)
100049 #define VPU_G1_SWREG61_SW_PP_AXI_RD_ID_SHIFT     (24U)
100050 /*! SW_PP_AXI_RD_ID - Read ID used for AXI PP read services (if connected to AXI) */
100051 #define VPU_G1_SWREG61_SW_PP_AXI_RD_ID(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_AXI_RD_ID_SHIFT)) & VPU_G1_SWREG61_SW_PP_AXI_RD_ID_MASK)
100052 /*! @} */
100053 
100054 /*! @name SWREG62 - Deinterlace control register */
100055 /*! @{ */
100056 
100057 #define VPU_G1_SWREG62_SW_DEINT_EDGE_DET_MASK    (0x7FFFU)
100058 #define VPU_G1_SWREG62_SW_DEINT_EDGE_DET_SHIFT   (0U)
100059 /*! SW_DEINT_EDGE_DET - Edge detect value used for deinterlacing */
100060 #define VPU_G1_SWREG62_SW_DEINT_EDGE_DET(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_EDGE_DET_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_EDGE_DET_MASK)
100061 
100062 #define VPU_G1_SWREG62_SW_DEINT_BLEND_E_MASK     (0x8000U)
100063 #define VPU_G1_SWREG62_SW_DEINT_BLEND_E_SHIFT    (15U)
100064 /*! SW_DEINT_BLEND_E - Blend enable for de-interlacing */
100065 #define VPU_G1_SWREG62_SW_DEINT_BLEND_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_BLEND_E_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_BLEND_E_MASK)
100066 
100067 #define VPU_G1_SWREG62_SW_DEINT_THRESHOLD_MASK   (0x3FFF0000U)
100068 #define VPU_G1_SWREG62_SW_DEINT_THRESHOLD_SHIFT  (16U)
100069 /*! SW_DEINT_THRESHOLD - Threshold value used in deinterlacing */
100070 #define VPU_G1_SWREG62_SW_DEINT_THRESHOLD(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_THRESHOLD_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_THRESHOLD_MASK)
100071 
100072 #define VPU_G1_SWREG62_SW_DEINT_E_MASK           (0x80000000U)
100073 #define VPU_G1_SWREG62_SW_DEINT_E_SHIFT          (31U)
100074 /*! SW_DEINT_E - De-interlace enable. Input data is in interlaced format and deinterlacing needs to be performed */
100075 #define VPU_G1_SWREG62_SW_DEINT_E(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_E_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_E_MASK)
100076 /*! @} */
100077 
100078 /*! @name SWREG63 - Base address for reading post-processing input picture luminance (top field/frame) */
100079 /*! @{ */
100080 
100081 #define VPU_G1_SWREG63_SW_PP_IN_LU_BASE_MASK     (0xFFFFFFFCU)
100082 #define VPU_G1_SWREG63_SW_PP_IN_LU_BASE_SHIFT    (2U)
100083 /*! SW_PP_IN_LU_BASE - Base address for post-processing input luminance picture. If PP input picture
100084  *    is fetched from fields this base address is used to point to top field of the picture. Used
100085  *    in external mode only.
100086  */
100087 #define VPU_G1_SWREG63_SW_PP_IN_LU_BASE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG63_SW_PP_IN_LU_BASE_SHIFT)) & VPU_G1_SWREG63_SW_PP_IN_LU_BASE_MASK)
100088 /*! @} */
100089 
100090 /*! @name SWREG64 - Base address for reading post-processing input picture Cb/Ch (top field/frame) */
100091 /*! @{ */
100092 
100093 #define VPU_G1_SWREG64_SW_PP_IN_CB_BASE_MASK     (0xFFFFFFFCU)
100094 #define VPU_G1_SWREG64_SW_PP_IN_CB_BASE_SHIFT    (2U)
100095 /*! SW_PP_IN_CB_BASE - Base address for post-processing input Cb picture or for both chrominance
100096  *    pictures (if chrominances interleaved). If PP input picture is fetched from fields this base
100097  *    address is used to point to top field of the picture. Used in external mode only
100098  */
100099 #define VPU_G1_SWREG64_SW_PP_IN_CB_BASE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG64_SW_PP_IN_CB_BASE_SHIFT)) & VPU_G1_SWREG64_SW_PP_IN_CB_BASE_MASK)
100100 /*! @} */
100101 
100102 /*! @name SWREG65 - Base address for reading post-processing input picture Cr */
100103 /*! @{ */
100104 
100105 #define VPU_G1_SWREG65_SW_PP_IN_CR_BASE_MASK     (0xFFFFFFFCU)
100106 #define VPU_G1_SWREG65_SW_PP_IN_CR_BASE_SHIFT    (2U)
100107 /*! SW_PP_IN_CR_BASE - Base address for post-processing input cr picture. Used in external mode only */
100108 #define VPU_G1_SWREG65_SW_PP_IN_CR_BASE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG65_SW_PP_IN_CR_BASE_SHIFT)) & VPU_G1_SWREG65_SW_PP_IN_CR_BASE_MASK)
100109 /*! @} */
100110 
100111 /*! @name SWREG66 - Base address for writing post-processed picture luminance/RGB */
100112 /*! @{ */
100113 
100114 #define VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_MASK    (0xFFFFFFFFU)
100115 #define VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_SHIFT   (0U)
100116 /*! SW_PP_OUT_LU_BASE - Base address for post-processing output picture (luminance/YUYV/RGB). NOTE:
100117  *    Bits 2:0 are used to adjust the post-processor output to start from zertain byte (1:0 for 32
100118  *    bit bus). These bits can be other than zero only if Pixel Accurate PP output configuration is
100119  *    enabled
100120  */
100121 #define VPU_G1_SWREG66_SW_PP_OUT_LU_BASE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_SHIFT)) & VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_MASK)
100122 /*! @} */
100123 
100124 /*! @name SWREG67 - Base address for writing post-processed picture Ch */
100125 /*! @{ */
100126 
100127 #define VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_MASK    (0xFFFFFFFFU)
100128 #define VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_SHIFT   (0U)
100129 /*! SW_PP_OUT_CH_BASE - Base address for post-processing output chrominance picture (interleaved
100130  *    chrominance). NOTE: Bits 2:0 are used to adjust the post-processor output to start from zertain
100131  *    byte (1:0 for 32 bit bus). These bits can be other than zero only if Pixel Accurate PP output
100132  *    configuration is enabled
100133  */
100134 #define VPU_G1_SWREG67_SW_PP_OUT_CH_BASE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_SHIFT)) & VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_MASK)
100135 /*! @} */
100136 
100137 /*! @name SWREG68 - Register for contrast adjusting */
100138 /*! @{ */
100139 
100140 #define VPU_G1_SWREG68_SW_CONTRAST_OFF1_MASK     (0x3FFU)
100141 #define VPU_G1_SWREG68_SW_CONTRAST_OFF1_SHIFT    (0U)
100142 /*! SW_CONTRAST_OFF1 - Offset value 1, used with contrast adjusting */
100143 #define VPU_G1_SWREG68_SW_CONTRAST_OFF1(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG68_SW_CONTRAST_OFF1_SHIFT)) & VPU_G1_SWREG68_SW_CONTRAST_OFF1_MASK)
100144 
100145 #define VPU_G1_SWREG68_SW_CONTRAST_OFF2_MASK     (0xFFC00U)
100146 #define VPU_G1_SWREG68_SW_CONTRAST_OFF2_SHIFT    (10U)
100147 /*! SW_CONTRAST_OFF2 - Offset value 2, used with contrast adjusting */
100148 #define VPU_G1_SWREG68_SW_CONTRAST_OFF2(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG68_SW_CONTRAST_OFF2_SHIFT)) & VPU_G1_SWREG68_SW_CONTRAST_OFF2_MASK)
100149 
100150 #define VPU_G1_SWREG68_SW_CONTRAST_THR1_MASK     (0xFF000000U)
100151 #define VPU_G1_SWREG68_SW_CONTRAST_THR1_SHIFT    (24U)
100152 /*! SW_CONTRAST_THR1 - Threshold value 1, used with contrast adjusting */
100153 #define VPU_G1_SWREG68_SW_CONTRAST_THR1(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG68_SW_CONTRAST_THR1_SHIFT)) & VPU_G1_SWREG68_SW_CONTRAST_THR1_MASK)
100154 /*! @} */
100155 
100156 /*! @name SWREG69 - Register for colour conversion and contrast adjusting/YUYV 422 channel orders */
100157 /*! @{ */
100158 
100159 #define VPU_G1_SWREG69_SW_CONTRAST_THR2_MASK     (0xFFU)
100160 #define VPU_G1_SWREG69_SW_CONTRAST_THR2_SHIFT    (0U)
100161 /*! SW_CONTRAST_THR2 - Threshold value 2, used with contrast adjusting */
100162 #define VPU_G1_SWREG69_SW_CONTRAST_THR2(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_CONTRAST_THR2_SHIFT)) & VPU_G1_SWREG69_SW_CONTRAST_THR2_MASK)
100163 
100164 #define VPU_G1_SWREG69_SW_COLOR_COEFFA1_MASK     (0x3FF00U)
100165 #define VPU_G1_SWREG69_SW_COLOR_COEFFA1_SHIFT    (8U)
100166 /*! SW_COLOR_COEFFA1 - Coefficient a1, used with Y pixel to calculate all color components */
100167 #define VPU_G1_SWREG69_SW_COLOR_COEFFA1(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_COLOR_COEFFA1_SHIFT)) & VPU_G1_SWREG69_SW_COLOR_COEFFA1_MASK)
100168 
100169 #define VPU_G1_SWREG69_SW_COLOR_COEFFA2_MASK     (0xFFC0000U)
100170 #define VPU_G1_SWREG69_SW_COLOR_COEFFA2_SHIFT    (18U)
100171 /*! SW_COLOR_COEFFA2 - Coefficient a2, used with Y pixel to calculate all color components */
100172 #define VPU_G1_SWREG69_SW_COLOR_COEFFA2(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_COLOR_COEFFA2_SHIFT)) & VPU_G1_SWREG69_SW_COLOR_COEFFA2_MASK)
100173 
100174 #define VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_MASK   (0x10000000U)
100175 #define VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_SHIFT  (28U)
100176 /*! SW_PP_OUT_CR_FIRST - For YUYV 422 output format. Enable for Cr first (before Cb).
100177  *  0b0..the order is Y0CbY0Cr or CbY0CrY0
100178  *  0b1..the order is Y0CrY0Cb or CrY0CbY0
100179  */
100180 #define VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_SHIFT)) & VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_MASK)
100181 
100182 #define VPU_G1_SWREG69_SW_PP_OUT_START_CH_MASK   (0x20000000U)
100183 #define VPU_G1_SWREG69_SW_PP_OUT_START_CH_SHIFT  (29U)
100184 /*! SW_PP_OUT_START_CH - For YUYV 422 output format. Enable for start_with_chrominance.
100185  *  0b0..the order is Y0CbY0Cr or Y0CrY0Cb
100186  *  0b1..the order is CbY0CrY0 or CrY0CbY0
100187  */
100188 #define VPU_G1_SWREG69_SW_PP_OUT_START_CH(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_OUT_START_CH_SHIFT)) & VPU_G1_SWREG69_SW_PP_OUT_START_CH_MASK)
100189 
100190 #define VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_MASK    (0x40000000U)
100191 #define VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_SHIFT   (30U)
100192 /*! SW_PP_IN_CR_FIRST - For YUYV 422 input format. Enable for Cr first (before Cb).
100193  *  0b0..the order is Y0CbY0Cr or CbY0CrY0 (if 420 semiplanar chrominance: CbCrCbCr)
100194  *  0b1..the order is Y0CrY0Cb or CrY0CbY0 (if 420 semiplanar chrominance: CrCbCrCb)
100195  */
100196 #define VPU_G1_SWREG69_SW_PP_IN_CR_FIRST(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_SHIFT)) & VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_MASK)
100197 
100198 #define VPU_G1_SWREG69_SW_PP_IN_START_CH_MASK    (0x80000000U)
100199 #define VPU_G1_SWREG69_SW_PP_IN_START_CH_SHIFT   (31U)
100200 /*! SW_PP_IN_START_CH - For YUYV 422 input format. Enable for start_with_chrominance.
100201  *  0b0..the order is Y0CbY0Cr or Y0CrY0Cb
100202  *  0b1..the order is CbY0CrY0 or CrY0CbY0
100203  */
100204 #define VPU_G1_SWREG69_SW_PP_IN_START_CH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_IN_START_CH_SHIFT)) & VPU_G1_SWREG69_SW_PP_IN_START_CH_MASK)
100205 /*! @} */
100206 
100207 /*! @name SWREG70 - Register for colour conversion 0 */
100208 /*! @{ */
100209 
100210 #define VPU_G1_SWREG70_SW_COLOR_COEFFB_MASK      (0x3FFU)
100211 #define VPU_G1_SWREG70_SW_COLOR_COEFFB_SHIFT     (0U)
100212 /*! SW_COLOR_COEFFB - Coefficient b, used with Cr to calculate red component value */
100213 #define VPU_G1_SWREG70_SW_COLOR_COEFFB(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_COLOR_COEFFB_SHIFT)) & VPU_G1_SWREG70_SW_COLOR_COEFFB_MASK)
100214 
100215 #define VPU_G1_SWREG70_SW_COLOR_COEFFC_MASK      (0xFFC00U)
100216 #define VPU_G1_SWREG70_SW_COLOR_COEFFC_SHIFT     (10U)
100217 /*! SW_COLOR_COEFFC - Coefficient c, used with Cr to calculate green component value */
100218 #define VPU_G1_SWREG70_SW_COLOR_COEFFC(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_COLOR_COEFFC_SHIFT)) & VPU_G1_SWREG70_SW_COLOR_COEFFC_MASK)
100219 
100220 #define VPU_G1_SWREG70_SW_COLOR_COEFFD_MASK      (0x3FF00000U)
100221 #define VPU_G1_SWREG70_SW_COLOR_COEFFD_SHIFT     (20U)
100222 /*! SW_COLOR_COEFFD - Coefficient d, used with Cb to calculate green component value */
100223 #define VPU_G1_SWREG70_SW_COLOR_COEFFD(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_COLOR_COEFFD_SHIFT)) & VPU_G1_SWREG70_SW_COLOR_COEFFD_MASK)
100224 
100225 #define VPU_G1_SWREG70_SW_PP_OUT_H_EXT_MASK      (0xC0000000U)
100226 #define VPU_G1_SWREG70_SW_PP_OUT_H_EXT_SHIFT     (30U)
100227 /*! SW_PP_OUT_H_EXT - Extended output height for 4k resolution */
100228 #define VPU_G1_SWREG70_SW_PP_OUT_H_EXT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_PP_OUT_H_EXT_SHIFT)) & VPU_G1_SWREG70_SW_PP_OUT_H_EXT_MASK)
100229 /*! @} */
100230 
100231 /*! @name SWREG71 - Register for colour conversion 1 + rotation mode */
100232 /*! @{ */
100233 
100234 #define VPU_G1_SWREG71_SW_COLOR_COEFFE_MASK      (0x3FFU)
100235 #define VPU_G1_SWREG71_SW_COLOR_COEFFE_SHIFT     (0U)
100236 /*! SW_COLOR_COEFFE - Coefficient e, used with Cb to calculate blue component value */
100237 #define VPU_G1_SWREG71_SW_COLOR_COEFFE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_COLOR_COEFFE_SHIFT)) & VPU_G1_SWREG71_SW_COLOR_COEFFE_MASK)
100238 
100239 #define VPU_G1_SWREG71_SW_COLOR_COEFFF_MASK      (0x3FC00U)
100240 #define VPU_G1_SWREG71_SW_COLOR_COEFFF_SHIFT     (10U)
100241 /*! SW_COLOR_COEFFF - Coefficient f, used with Y to adjust brightness */
100242 #define VPU_G1_SWREG71_SW_COLOR_COEFFF(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_COLOR_COEFFF_SHIFT)) & VPU_G1_SWREG71_SW_COLOR_COEFFF_MASK)
100243 
100244 #define VPU_G1_SWREG71_SW_ROTATION_MODE_MASK     (0x1C0000U)
100245 #define VPU_G1_SWREG71_SW_ROTATION_MODE_SHIFT    (18U)
100246 /*! SW_ROTATION_MODE - Rotation mode:
100247  *  0b000..rotation disabled
100248  *  0b001..rotate + 90
100249  *  0b010..rotate - 90
100250  *  0b011..horizontal flip (mirror)
100251  *  0b100..vertical flip
100252  *  0b101..rotate 180
100253  */
100254 #define VPU_G1_SWREG71_SW_ROTATION_MODE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_ROTATION_MODE_SHIFT)) & VPU_G1_SWREG71_SW_ROTATION_MODE_MASK)
100255 
100256 #define VPU_G1_SWREG71_SW_CROP_STARTX_MASK       (0x3FE00000U)
100257 #define VPU_G1_SWREG71_SW_CROP_STARTX_SHIFT      (21U)
100258 /*! SW_CROP_STARTX - Start coordinate x for the cropped area in macroblocks. */
100259 #define VPU_G1_SWREG71_SW_CROP_STARTX(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_CROP_STARTX_SHIFT)) & VPU_G1_SWREG71_SW_CROP_STARTX_MASK)
100260 
100261 #define VPU_G1_SWREG71_SW_PP_OUT_W_EXT_MASK      (0xC0000000U)
100262 #define VPU_G1_SWREG71_SW_PP_OUT_W_EXT_SHIFT     (30U)
100263 /*! SW_PP_OUT_W_EXT - Extended output width for 4k resolution */
100264 #define VPU_G1_SWREG71_SW_PP_OUT_W_EXT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_PP_OUT_W_EXT_SHIFT)) & VPU_G1_SWREG71_SW_PP_OUT_W_EXT_MASK)
100265 /*! @} */
100266 
100267 /*! @name SWREG72 - PP input size and -cropping register */
100268 /*! @{ */
100269 
100270 #define VPU_G1_SWREG72_SW_PP_IN_WIDTH_MASK       (0x1FFU)
100271 #define VPU_G1_SWREG72_SW_PP_IN_WIDTH_SHIFT      (0U)
100272 /*! SW_PP_IN_WIDTH - PP input picture width in MBs. Can be cropped from a bigger input picture in external mode */
100273 #define VPU_G1_SWREG72_SW_PP_IN_WIDTH(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_PP_IN_WIDTH_SHIFT)) & VPU_G1_SWREG72_SW_PP_IN_WIDTH_MASK)
100274 
100275 #define VPU_G1_SWREG72_SW_PP_IN_HEIGHT_MASK      (0x1FE00U)
100276 #define VPU_G1_SWREG72_SW_PP_IN_HEIGHT_SHIFT     (9U)
100277 /*! SW_PP_IN_HEIGHT - PP input picture height in MBs. Can be cropped from a bigger input picture in external mode */
100278 #define VPU_G1_SWREG72_SW_PP_IN_HEIGHT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_PP_IN_HEIGHT_SHIFT)) & VPU_G1_SWREG72_SW_PP_IN_HEIGHT_MASK)
100279 
100280 #define VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_MASK   (0x7C0000U)
100281 #define VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_SHIFT  (18U)
100282 /*! SW_RANGEMAP_COEF_Y - Range map value for Y component */
100283 #define VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_SHIFT)) & VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_MASK)
100284 
100285 #define VPU_G1_SWREG72_SW_CROP_STARTY_MASK       (0xFF000000U)
100286 #define VPU_G1_SWREG72_SW_CROP_STARTY_SHIFT      (24U)
100287 /*! SW_CROP_STARTY - Start coordinate y for the cropped area in macroblocks. */
100288 #define VPU_G1_SWREG72_SW_CROP_STARTY(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_CROP_STARTY_SHIFT)) & VPU_G1_SWREG72_SW_CROP_STARTY_MASK)
100289 /*! @} */
100290 
100291 /*! @name SWREG73 - PP input picture base address for Y bottom field */
100292 /*! @{ */
100293 
100294 #define VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_MASK   (0xFFFFFFFCU)
100295 #define VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_SHIFT  (2U)
100296 /*! SW_PP_BOT_YIN_BASE - PP input Y base for bottom field */
100297 #define VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_SHIFT)) & VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_MASK)
100298 /*! @} */
100299 
100300 /*! @name SWREG74 - PP input picture base for Ch bottom field */
100301 /*! @{ */
100302 
100303 #define VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_MASK   (0xFFFFFFFCU)
100304 #define VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_SHIFT  (2U)
100305 /*! SW_PP_BOT_CIN_BASE - PP input C base for bottom field (mixed chrominance) */
100306 #define VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_SHIFT)) & VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_MASK)
100307 /*! @} */
100308 
100309 /*! @name SWREG79 - Scaling register 0 ratio and padding for R and G */
100310 /*! @{ */
100311 
100312 #define VPU_G1_SWREG79_SW_SCALE_WRATIO_MASK      (0x3FFFFU)
100313 #define VPU_G1_SWREG79_SW_SCALE_WRATIO_SHIFT     (0U)
100314 /*! SW_SCALE_WRATIO - Scaling ratio for width (outputw-1/inputw-1) */
100315 #define VPU_G1_SWREG79_SW_SCALE_WRATIO(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_SCALE_WRATIO_SHIFT)) & VPU_G1_SWREG79_SW_SCALE_WRATIO_MASK)
100316 
100317 #define VPU_G1_SWREG79_SW_RGB_G_PADD_MASK        (0x7C0000U)
100318 #define VPU_G1_SWREG79_SW_RGB_G_PADD_SHIFT       (18U)
100319 /*! SW_RGB_G_PADD - Amount of ones that will be padded in front of the G-component */
100320 #define VPU_G1_SWREG79_SW_RGB_G_PADD(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RGB_G_PADD_SHIFT)) & VPU_G1_SWREG79_SW_RGB_G_PADD_MASK)
100321 
100322 #define VPU_G1_SWREG79_SW_RGB_R_PADD_MASK        (0xF800000U)
100323 #define VPU_G1_SWREG79_SW_RGB_R_PADD_SHIFT       (23U)
100324 /*! SW_RGB_R_PADD - Amount of ones that will be padded in front of the R-component */
100325 #define VPU_G1_SWREG79_SW_RGB_R_PADD(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RGB_R_PADD_SHIFT)) & VPU_G1_SWREG79_SW_RGB_R_PADD_MASK)
100326 
100327 #define VPU_G1_SWREG79_SW_RGB_PIX_IN32_MASK      (0x10000000U)
100328 #define VPU_G1_SWREG79_SW_RGB_PIX_IN32_SHIFT     (28U)
100329 /*! SW_RGB_PIX_IN32 - RGB pixel amount/ 32 bit word
100330  *  0b0..1 RGB pixel/32 bit
100331  *  0b1..2 RGB pixels/32 bit
100332  */
100333 #define VPU_G1_SWREG79_SW_RGB_PIX_IN32(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RGB_PIX_IN32_SHIFT)) & VPU_G1_SWREG79_SW_RGB_PIX_IN32_MASK)
100334 
100335 #define VPU_G1_SWREG79_SW_YCBCR_RANGE_MASK       (0x20000000U)
100336 #define VPU_G1_SWREG79_SW_YCBCR_RANGE_SHIFT      (29U)
100337 /*! SW_YCBCR_RANGE - Defines the YCbCr range in RGB conversion:
100338  *  0b0..16...235 for Y, 16...240 for Chrominance.
100339  *  0b1..0...255 for all components
100340  */
100341 #define VPU_G1_SWREG79_SW_YCBCR_RANGE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_YCBCR_RANGE_SHIFT)) & VPU_G1_SWREG79_SW_YCBCR_RANGE_MASK)
100342 
100343 #define VPU_G1_SWREG79_SW_RANGEMAP_C_E_MASK      (0x40000000U)
100344 #define VPU_G1_SWREG79_SW_RANGEMAP_C_E_SHIFT     (30U)
100345 /*! SW_RANGEMAP_C_E - Range map enable for chrominance component */
100346 #define VPU_G1_SWREG79_SW_RANGEMAP_C_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RANGEMAP_C_E_SHIFT)) & VPU_G1_SWREG79_SW_RANGEMAP_C_E_MASK)
100347 
100348 #define VPU_G1_SWREG79_SW_RANGEMAP_Y_E_MASK      (0x80000000U)
100349 #define VPU_G1_SWREG79_SW_RANGEMAP_Y_E_SHIFT     (31U)
100350 /*! SW_RANGEMAP_Y_E - Range map enable for Y component */
100351 #define VPU_G1_SWREG79_SW_RANGEMAP_Y_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RANGEMAP_Y_E_SHIFT)) & VPU_G1_SWREG79_SW_RANGEMAP_Y_E_MASK)
100352 /*! @} */
100353 
100354 /*! @name SWREG80 - Scaling ratio register 1 and padding for B */
100355 /*! @{ */
100356 
100357 #define VPU_G1_SWREG80_SW_SCALE_HRATIO_MASK      (0x3FFFFU)
100358 #define VPU_G1_SWREG80_SW_SCALE_HRATIO_SHIFT     (0U)
100359 /*! SW_SCALE_HRATIO - Scaling ratio for height (outputh-1/inputh-1) */
100360 #define VPU_G1_SWREG80_SW_SCALE_HRATIO(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_SCALE_HRATIO_SHIFT)) & VPU_G1_SWREG80_SW_SCALE_HRATIO_MASK)
100361 
100362 #define VPU_G1_SWREG80_SW_RGB_B_PADD_MASK        (0x7C0000U)
100363 #define VPU_G1_SWREG80_SW_RGB_B_PADD_SHIFT       (18U)
100364 /*! SW_RGB_B_PADD - Amount of ones that will be padded in front of the B-component */
100365 #define VPU_G1_SWREG80_SW_RGB_B_PADD(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_RGB_B_PADD_SHIFT)) & VPU_G1_SWREG80_SW_RGB_B_PADD_MASK)
100366 
100367 #define VPU_G1_SWREG80_SW_VER_SCALE_MODE_MASK    (0x1800000U)
100368 #define VPU_G1_SWREG80_SW_VER_SCALE_MODE_SHIFT   (23U)
100369 /*! SW_VER_SCALE_MODE - Vertical scaling mode:
100370  *  0b00..Off
100371  *  0b01..Upscale
100372  *  0b10..Downscale
100373  */
100374 #define VPU_G1_SWREG80_SW_VER_SCALE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_VER_SCALE_MODE_SHIFT)) & VPU_G1_SWREG80_SW_VER_SCALE_MODE_MASK)
100375 
100376 #define VPU_G1_SWREG80_SW_HOR_SCALE_MODE_MASK    (0x6000000U)
100377 #define VPU_G1_SWREG80_SW_HOR_SCALE_MODE_SHIFT   (25U)
100378 /*! SW_HOR_SCALE_MODE - Horizontal scaling mode:
100379  *  0b00..Off
100380  *  0b01..Upscale
100381  *  0b10..Downscale
100382  */
100383 #define VPU_G1_SWREG80_SW_HOR_SCALE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_HOR_SCALE_MODE_SHIFT)) & VPU_G1_SWREG80_SW_HOR_SCALE_MODE_MASK)
100384 
100385 #define VPU_G1_SWREG80_SW_PP_IN_STRUCT_MASK      (0x38000000U)
100386 #define VPU_G1_SWREG80_SW_PP_IN_STRUCT_SHIFT     (27U)
100387 /*! SW_PP_IN_STRUCT - PP input data picture structure:
100388  *  0b000..Top field / progressive frame structure: Read input data from top field base address /frame base address and read every line.
100389  *  0b001..Bottom field structure: Read input data from bottom field base address and read every line.
100390  *  0b010..Interlaced field structure: Read input data from both top and bottom field base address and take every line from each field.
100391  *  0b011..Interlaced frame structure: Read input data from both top and bottom field base address and take every second line from each field.
100392  *  0b100..Ripped top field structure: Read input data from top field base address and read every second line.
100393  *  0b101..Ripped bottom field structure: Read input data from bottom field base address and read every second line.
100394  */
100395 #define VPU_G1_SWREG80_SW_PP_IN_STRUCT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_PP_IN_STRUCT_SHIFT)) & VPU_G1_SWREG80_SW_PP_IN_STRUCT_MASK)
100396 
100397 #define VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_MASK   (0x40000000U)
100398 #define VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_SHIFT  (30U)
100399 /*! SW_PP_FAST_SCALE_E
100400  *  0b0..fast downscaling is not enabled
100401  *  0b1..fast downscaling is enabled. The quality of the picture is decreased but performance is improved.
100402  */
100403 #define VPU_G1_SWREG80_SW_PP_FAST_SCALE_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_SHIFT)) & VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_MASK)
100404 /*! @} */
100405 
100406 /*! @name SWREG81 - Scaling ratio register 2 */
100407 /*! @{ */
100408 
100409 #define VPU_G1_SWREG81_SW_HSCALE_INVRA_MASK      (0xFFFFU)
100410 #define VPU_G1_SWREG81_SW_HSCALE_INVRA_SHIFT     (0U)
100411 /*! SW_HSCALE_INVRA - Inverse scaling ratio for height or cv (inputh-1 / outputh-1) */
100412 #define VPU_G1_SWREG81_SW_HSCALE_INVRA(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG81_SW_HSCALE_INVRA_SHIFT)) & VPU_G1_SWREG81_SW_HSCALE_INVRA_MASK)
100413 
100414 #define VPU_G1_SWREG81_SW_WSCALE_INVRA_MASK      (0xFFFF0000U)
100415 #define VPU_G1_SWREG81_SW_WSCALE_INVRA_SHIFT     (16U)
100416 /*! SW_WSCALE_INVRA - Inverse scaling ratio for width, or ch (inputw-1 / outputw-1) */
100417 #define VPU_G1_SWREG81_SW_WSCALE_INVRA(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG81_SW_WSCALE_INVRA_SHIFT)) & VPU_G1_SWREG81_SW_WSCALE_INVRA_MASK)
100418 /*! @} */
100419 
100420 /*! @name SWREG82 - Rmask register */
100421 /*! @{ */
100422 
100423 #define VPU_G1_SWREG82_SW_R_MASK_MASK            (0xFFFFFFFFU)
100424 #define VPU_G1_SWREG82_SW_R_MASK_SHIFT           (0U)
100425 /*! SW_R_MASK - Bit mask for R component (and alpha channel) */
100426 #define VPU_G1_SWREG82_SW_R_MASK(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG82_SW_R_MASK_SHIFT)) & VPU_G1_SWREG82_SW_R_MASK_MASK)
100427 /*! @} */
100428 
100429 /*! @name SWREG83 - Gmask register */
100430 /*! @{ */
100431 
100432 #define VPU_G1_SWREG83_SW_G_MASK_MASK            (0xFFFFFFFFU)
100433 #define VPU_G1_SWREG83_SW_G_MASK_SHIFT           (0U)
100434 /*! SW_G_MASK - Bit mask for G component (and alpha channel) */
100435 #define VPU_G1_SWREG83_SW_G_MASK(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG83_SW_G_MASK_SHIFT)) & VPU_G1_SWREG83_SW_G_MASK_MASK)
100436 /*! @} */
100437 
100438 /*! @name SWREG84 - Bmask register */
100439 /*! @{ */
100440 
100441 #define VPU_G1_SWREG84_SW_B_MASK_MASK            (0xFFFFFFFFU)
100442 #define VPU_G1_SWREG84_SW_B_MASK_SHIFT           (0U)
100443 /*! SW_B_MASK - Bit mask for B component (and alpha channel) */
100444 #define VPU_G1_SWREG84_SW_B_MASK(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG84_SW_B_MASK_SHIFT)) & VPU_G1_SWREG84_SW_B_MASK_MASK)
100445 /*! @} */
100446 
100447 /*! @name SWREG85 - Post-processor control register */
100448 /*! @{ */
100449 
100450 #define VPU_G1_SWREG85_SW_PP_CROP8_D_E_MASK      (0x1U)
100451 #define VPU_G1_SWREG85_SW_PP_CROP8_D_E_SHIFT     (0U)
100452 /*! SW_PP_CROP8_D_E - PP input picture height is not 16 pixels multiple. Only 8 pixel rows of the
100453  *    most down MB of the unrotated input picture is used for PP input.
100454  */
100455 #define VPU_G1_SWREG85_SW_PP_CROP8_D_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_CROP8_D_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_CROP8_D_E_MASK)
100456 
100457 #define VPU_G1_SWREG85_SW_PP_CROP8_R_E_MASK      (0x2U)
100458 #define VPU_G1_SWREG85_SW_PP_CROP8_R_E_SHIFT     (1U)
100459 /*! SW_PP_CROP8_R_E - PP input picture width is not 16 pixels multiple. Only 8 pixels of the most
100460  *    right MB of the unrotated input picture is used for PP input.
100461  */
100462 #define VPU_G1_SWREG85_SW_PP_CROP8_R_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_CROP8_R_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_CROP8_R_E_MASK)
100463 
100464 #define VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_MASK   (0x4U)
100465 #define VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_SHIFT  (2U)
100466 /*! SW_PP_OUT_SWAP16_E - PP output swap 16, swaps 16 bit half inside of 32 bit word. Can be used for
100467  *    16 bit RGB to change pixel orders but is valid also for any output format. NOTE: requires
100468  *    that configuration of SW_PPD_OEN_VERSION=1
100469  */
100470 #define VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_MASK)
100471 
100472 #define VPU_G1_SWREG85_SW_PP_OUT_TILED_E_MASK    (0x8U)
100473 #define VPU_G1_SWREG85_SW_PP_OUT_TILED_E_SHIFT   (3U)
100474 /*! SW_PP_OUT_TILED_E - Tiled mode enable for PP output. Can be used only for YCbYCr 422 output
100475  *    format. Can be used only if corresponding configuration supports this feature. Tile size is 4x4
100476  *    pixels.
100477  */
100478 #define VPU_G1_SWREG85_SW_PP_OUT_TILED_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_TILED_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_TILED_E_MASK)
100479 
100480 #define VPU_G1_SWREG85_SW_PP_OUT_WIDTH_MASK      (0x7FF0U)
100481 #define VPU_G1_SWREG85_SW_PP_OUT_WIDTH_SHIFT     (4U)
100482 /*! SW_PP_OUT_WIDTH - Scaled picture width in pixels. Must be dividable by 8 or by any if Pixel
100483  *    Accurate PP output configuration is enabled. Max scaled picture width is 1920 pixels or maximum
100484  *    three times the input source width minus 8 pixels
100485  */
100486 #define VPU_G1_SWREG85_SW_PP_OUT_WIDTH(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_WIDTH_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_WIDTH_MASK)
100487 
100488 #define VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_MASK     (0x3FF8000U)
100489 #define VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_SHIFT    (15U)
100490 /*! SW_PP_OUT_HEIGHT - Scaled picture height in pixels (Must be dividable by 2 or by any if Pixel
100491  *    Accurate PP output configuration is enabled) Max scaled picture height is 1920 pixels or maximum
100492  *    three times the input source height minus 8 pixels
100493  */
100494 #define VPU_G1_SWREG85_SW_PP_OUT_HEIGHT(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_MASK)
100495 
100496 #define VPU_G1_SWREG85_SW_PP_OUT_FORMAT_MASK     (0x1C000000U)
100497 #define VPU_G1_SWREG85_SW_PP_OUT_FORMAT_SHIFT    (26U)
100498 /*! SW_PP_OUT_FORMAT - PP output picture data format:
100499  *  0b000..RGB
100500  *  0b001..YCbCr 4:2:0 planar (Not supported)
100501  *  0b010..YCbCr 4:2:2 planar (Not supported)
100502  *  0b011..YUYV 4:2:2 interleaved
100503  *  0b100..YCbCr 4:4:4 planar (Not supported)
100504  *  0b101..YCh 4:2:0 chrominance interleaved
100505  *  0b110..YCh 4:2:2 (Not supported)
100506  *  0b111..YCh 4:4:4 (Not supported)
100507  */
100508 #define VPU_G1_SWREG85_SW_PP_OUT_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_FORMAT_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_FORMAT_MASK)
100509 
100510 #define VPU_G1_SWREG85_SW_PP_IN_FORMAT_MASK      (0xE0000000U)
100511 #define VPU_G1_SWREG85_SW_PP_IN_FORMAT_SHIFT     (29U)
100512 /*! SW_PP_IN_FORMAT - PP input picture data format
100513  *  0b000..YUYV 4:2:2 interleaved (supported only in external mode)
100514  *  0b001..YCbCr 4:2:0 Semi-planar in linear raster-scan format
100515  *  0b010..YCbCr 4:2:0 planar (supported only in external mode)
100516  *  0b011..YCbCr 4:0:0 (supported only in pipelined mode)
100517  *  0b100..YCbCr 4:2:2 Semi-planar (supported only in pipelined mode)
100518  *  0b101..YCbCr 4:2:0 Semi-planar in tiled format (supported only in external mode (8170 decoder only)
100519  *  0b110..Reserved
100520  *  0b111..Escape pp input data format. Defined in swreg86.
100521  */
100522 #define VPU_G1_SWREG85_SW_PP_IN_FORMAT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_IN_FORMAT_SHIFT)) & VPU_G1_SWREG85_SW_PP_IN_FORMAT_MASK)
100523 /*! @} */
100524 
100525 /*! @name SWREG86 - Mask 1 start coordinate register */
100526 /*! @{ */
100527 
100528 #define VPU_G1_SWREG86_SW_MASK1_STARTX_MASK      (0x7FFU)
100529 #define VPU_G1_SWREG86_SW_MASK1_STARTX_SHIFT     (0U)
100530 /*! SW_MASK1_STARTX - Horizontal start pixel for mask area 1. Defines the x coordinate. Coordinate
100531  *    0,0 means the up-left corner in PP output luminance picture. See Table 47 for restrictions
100532  */
100533 #define VPU_G1_SWREG86_SW_MASK1_STARTX(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_MASK1_STARTX_SHIFT)) & VPU_G1_SWREG86_SW_MASK1_STARTX_MASK)
100534 
100535 #define VPU_G1_SWREG86_SW_MASK1_STARTY_MASK      (0x3FF800U)
100536 #define VPU_G1_SWREG86_SW_MASK1_STARTY_SHIFT     (11U)
100537 /*! SW_MASK1_STARTY - Vertical start pixel for mask area 1. Defines the y coordinate. Coordinate 0,0
100538  *    means the up-left corner in PP output luminance picture. See Table 47 for restrictions
100539  */
100540 #define VPU_G1_SWREG86_SW_MASK1_STARTY(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_MASK1_STARTY_SHIFT)) & VPU_G1_SWREG86_SW_MASK1_STARTY_MASK)
100541 
100542 #define VPU_G1_SWREG86_SW_MASK1_ABLEND_E_MASK    (0x400000U)
100543 #define VPU_G1_SWREG86_SW_MASK1_ABLEND_E_SHIFT   (22U)
100544 /*! SW_MASK1_ABLEND_E - Mask 1 alpha blending enable. Instead of masking the output picture the
100545  *    alpha blending is performed. Alpha blending source can be found from alpha blend 1 base address.
100546  *    Alpha blending can be enabled only for RGB/ YUYV 422 data.
100547  */
100548 #define VPU_G1_SWREG86_SW_MASK1_ABLEND_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_MASK1_ABLEND_E_SHIFT)) & VPU_G1_SWREG86_SW_MASK1_ABLEND_E_MASK)
100549 
100550 #define VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_MASK   (0xF800000U)
100551 #define VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_SHIFT  (23U)
100552 /*! SW_RANGEMAP_COEF_C - Range map value for chrominance component */
100553 #define VPU_G1_SWREG86_SW_RANGEMAP_COEF_C(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_SHIFT)) & VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_MASK)
100554 
100555 #define VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_MASK   (0xE0000000U)
100556 #define VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_SHIFT  (29U)
100557 /*! SW_PP_IN_FORMAT_ES - Escape PP in format. Used if sw_pp_in_format is defined to 7.
100558  *  0b000..YCbCr 4:4:4
100559  *  0b001..YCbCr 4:1:1
100560  */
100561 #define VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_SHIFT)) & VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_MASK)
100562 /*! @} */
100563 
100564 /*! @name SWREG87 - Mask 2 start coordinate register + Mask extensions */
100565 /*! @{ */
100566 
100567 #define VPU_G1_SWREG87_SW_MASK2_STARTX_MASK      (0x7FFU)
100568 #define VPU_G1_SWREG87_SW_MASK2_STARTX_SHIFT     (0U)
100569 /*! SW_MASK2_STARTX - Horizontal start pixel for mask area 2. Defines the x coordinate. Coordinate
100570  *    0,0 means the up-left corner in PP output Y picture. See Table 47 for restrictions
100571  */
100572 #define VPU_G1_SWREG87_SW_MASK2_STARTX(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTX_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTX_MASK)
100573 
100574 #define VPU_G1_SWREG87_SW_MASK2_STARTY_MASK      (0x3FF800U)
100575 #define VPU_G1_SWREG87_SW_MASK2_STARTY_SHIFT     (11U)
100576 /*! SW_MASK2_STARTY - Vertical start pixel for mask area 2. Defines the y coordinate. Coordinate 0,0
100577  *    means the up-left corner in PP output Y picture. See Table 47 for restrictions
100578  */
100579 #define VPU_G1_SWREG87_SW_MASK2_STARTY(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTY_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTY_MASK)
100580 
100581 #define VPU_G1_SWREG87_SW_MASK2_ABLEND_E_MASK    (0x400000U)
100582 #define VPU_G1_SWREG87_SW_MASK2_ABLEND_E_SHIFT   (22U)
100583 /*! SW_MASK2_ABLEND_E - Mask 2 alpha blending enable. Instead of masking the output picture the
100584  *    alpha blending is performed. Alpha blending source can be found from alpha blend 2 base address.
100585  *    Alpha blending can be enabled only for RGB/YUYV 422 data.
100586  */
100587 #define VPU_G1_SWREG87_SW_MASK2_ABLEND_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_ABLEND_E_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_ABLEND_E_MASK)
100588 
100589 #define VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_MASK  (0x1800000U)
100590 #define VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_SHIFT (23U)
100591 /*! SW_MASK2_STARTY_EXT - Extended coordinate upto 4k resolution */
100592 #define VPU_G1_SWREG87_SW_MASK2_STARTY_EXT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_MASK)
100593 
100594 #define VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_MASK  (0x6000000U)
100595 #define VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_SHIFT (25U)
100596 /*! SW_MASK2_STARTX_EXT - Extended coordinate upto 4k resolution */
100597 #define VPU_G1_SWREG87_SW_MASK2_STARTX_EXT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_MASK)
100598 
100599 #define VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_MASK  (0x18000000U)
100600 #define VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_SHIFT (27U)
100601 /*! SW_MASK1_STARTY_EXT - Extended coordinate upto 4k resolution */
100602 #define VPU_G1_SWREG87_SW_MASK1_STARTY_EXT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_MASK)
100603 
100604 #define VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_MASK  (0x60000000U)
100605 #define VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_SHIFT (29U)
100606 /*! SW_MASK1_STARTX_EXT - Extended coordinate upto 4k resolution */
100607 #define VPU_G1_SWREG87_SW_MASK1_STARTX_EXT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_MASK)
100608 /*! @} */
100609 
100610 /*! @name SWREG88 - Mask 1 size and PP original width register */
100611 /*! @{ */
100612 
100613 #define VPU_G1_SWREG88_SW_MASK1_ENDX_MASK        (0x7FFU)
100614 #define VPU_G1_SWREG88_SW_MASK1_ENDX_SHIFT       (0U)
100615 /*! SW_MASK1_ENDX - Mask 1 end coordinate x in pixels (inside of PPD output picture). Range must be
100616  *    between [Mask1StartCoordinateX, ScaledWidth]
100617  */
100618 #define VPU_G1_SWREG88_SW_MASK1_ENDX(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_MASK1_ENDX_SHIFT)) & VPU_G1_SWREG88_SW_MASK1_ENDX_MASK)
100619 
100620 #define VPU_G1_SWREG88_SW_MASK1_ENDY_MASK        (0x3FF800U)
100621 #define VPU_G1_SWREG88_SW_MASK1_ENDY_SHIFT       (11U)
100622 /*! SW_MASK1_ENDY - Mask 1 end coordinate y in pixels (inside of PPD output picture). Range must be
100623  *    between [Mask1StartCoordinateY, ScaledHeight].
100624  */
100625 #define VPU_G1_SWREG88_SW_MASK1_ENDY(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_MASK1_ENDY_SHIFT)) & VPU_G1_SWREG88_SW_MASK1_ENDY_MASK)
100626 
100627 #define VPU_G1_SWREG88_SW_MASK1_E_MASK           (0x400000U)
100628 #define VPU_G1_SWREG88_SW_MASK1_E_SHIFT          (22U)
100629 /*! SW_MASK1_E - Mask 1 enable. If mask 1 is used this bit is high */
100630 #define VPU_G1_SWREG88_SW_MASK1_E(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_MASK1_E_SHIFT)) & VPU_G1_SWREG88_SW_MASK1_E_MASK)
100631 
100632 #define VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_MASK    (0xFF800000U)
100633 #define VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_SHIFT   (23U)
100634 /*! SW_EXT_ORIG_WIDTH - PP input picture original width in macro blocks. */
100635 #define VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_SHIFT)) & VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_MASK)
100636 /*! @} */
100637 
100638 /*! @name SWREG89 - Mask 2 size register + mask extensions */
100639 /*! @{ */
100640 
100641 #define VPU_G1_SWREG89_SW_MASK2_ENDX_MASK        (0x7FFU)
100642 #define VPU_G1_SWREG89_SW_MASK2_ENDX_SHIFT       (0U)
100643 /*! SW_MASK2_ENDX - Mask 2 end coordinate x in pixels (inside of PP output picture). Range must be
100644  *    between [Mask2StartCoordinateX, ScaledWidth].
100645  */
100646 #define VPU_G1_SWREG89_SW_MASK2_ENDX(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDX_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDX_MASK)
100647 
100648 #define VPU_G1_SWREG89_SW_MASK2_ENDY_MASK        (0x3FF800U)
100649 #define VPU_G1_SWREG89_SW_MASK2_ENDY_SHIFT       (11U)
100650 /*! SW_MASK2_ENDY - Mask 2 end coordinate y in pixels (inside of PP output picture). Range must be
100651  *    between [Mask2StartCoordinateY, ScaledHeight].
100652  */
100653 #define VPU_G1_SWREG89_SW_MASK2_ENDY(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDY_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDY_MASK)
100654 
100655 #define VPU_G1_SWREG89_SW_MASK2_E_MASK           (0x400000U)
100656 #define VPU_G1_SWREG89_SW_MASK2_E_SHIFT          (22U)
100657 /*! SW_MASK2_E - Mask 2 enable. If mask 1 is used this bit is high */
100658 #define VPU_G1_SWREG89_SW_MASK2_E(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_E_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_E_MASK)
100659 
100660 #define VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_MASK    (0x1800000U)
100661 #define VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_SHIFT   (23U)
100662 /*! SW_MASK2_ENDY_EXT - Extended coordinate upto 4k resolution */
100663 #define VPU_G1_SWREG89_SW_MASK2_ENDY_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_MASK)
100664 
100665 #define VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_MASK    (0x6000000U)
100666 #define VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_SHIFT   (25U)
100667 /*! SW_MASK2_ENDX_EXT - Extended coordinate upto 4k resolution */
100668 #define VPU_G1_SWREG89_SW_MASK2_ENDX_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_MASK)
100669 
100670 #define VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_MASK    (0x18000000U)
100671 #define VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_SHIFT   (27U)
100672 /*! SW_MASK1_ENDY_EXT - Extended coordinate upto 4k resolution */
100673 #define VPU_G1_SWREG89_SW_MASK1_ENDY_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_MASK)
100674 
100675 #define VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_MASK    (0x60000000U)
100676 #define VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_SHIFT   (29U)
100677 /*! SW_MASK1_ENDX_EXT - Extended coordinate upto 4k resolution */
100678 #define VPU_G1_SWREG89_SW_MASK1_ENDX_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_MASK)
100679 /*! @} */
100680 
100681 /*! @name SWREG90 - PiP register 0 */
100682 /*! @{ */
100683 
100684 #define VPU_G1_SWREG90_SW_DOWN_CROSS_MASK        (0x7FFU)
100685 #define VPU_G1_SWREG90_SW_DOWN_CROSS_SHIFT       (0U)
100686 /*! SW_DOWN_CROSS - Amount of downward overcross (vertical pixels outside of display from the down
100687  *    side). Range must be between [0, ScaledHeight].
100688  */
100689 #define VPU_G1_SWREG90_SW_DOWN_CROSS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_DOWN_CROSS_SHIFT)) & VPU_G1_SWREG90_SW_DOWN_CROSS_MASK)
100690 
100691 #define VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_MASK    (0x1800U)
100692 #define VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_SHIFT   (11U)
100693 /*! SW_DOWN_CROSS_EXT - Extended coordinate for 4k resolution */
100694 #define VPU_G1_SWREG90_SW_DOWN_CROSS_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_SHIFT)) & VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_MASK)
100695 
100696 #define VPU_G1_SWREG90_SW_UP_CROSS_MASK          (0x3FF8000U)
100697 #define VPU_G1_SWREG90_SW_UP_CROSS_SHIFT         (15U)
100698 /*! SW_UP_CROSS - Amount of upward overcross (vertical pixels outside of display from the upper
100699  *    side). Range must be between [0, ScaledHeight].
100700  */
100701 #define VPU_G1_SWREG90_SW_UP_CROSS(x)            (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_UP_CROSS_SHIFT)) & VPU_G1_SWREG90_SW_UP_CROSS_MASK)
100702 
100703 #define VPU_G1_SWREG90_SW_DOWN_CROSS_E_MASK      (0x4000000U)
100704 #define VPU_G1_SWREG90_SW_DOWN_CROSS_E_SHIFT     (26U)
100705 /*! SW_DOWN_CROSS_E - Downward overcross enable.
100706  *  0b0..No downward overcross
100707  *  0b1..Downward overcross
100708  */
100709 #define VPU_G1_SWREG90_SW_DOWN_CROSS_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_DOWN_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_DOWN_CROSS_E_MASK)
100710 
100711 #define VPU_G1_SWREG90_SW_UP_CROSS_E_MASK        (0x8000000U)
100712 #define VPU_G1_SWREG90_SW_UP_CROSS_E_SHIFT       (27U)
100713 /*! SW_UP_CROSS_E - Upward overcross enable.
100714  *  0b0..No upward overcross
100715  *  0b1..Upward overcross
100716  */
100717 #define VPU_G1_SWREG90_SW_UP_CROSS_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_UP_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_UP_CROSS_E_MASK)
100718 
100719 #define VPU_G1_SWREG90_SW_LEFT_CROSS_E_MASK      (0x10000000U)
100720 #define VPU_G1_SWREG90_SW_LEFT_CROSS_E_SHIFT     (28U)
100721 /*! SW_LEFT_CROSS_E - Left side overcross enable.
100722  *  0b0..No left side overcross
100723  *  0b1..Left side overcross
100724  */
100725 #define VPU_G1_SWREG90_SW_LEFT_CROSS_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_LEFT_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_LEFT_CROSS_E_MASK)
100726 
100727 #define VPU_G1_SWREG90_SW_RIGHT_CROSS_E_MASK     (0x20000000U)
100728 #define VPU_G1_SWREG90_SW_RIGHT_CROSS_E_SHIFT    (29U)
100729 /*! SW_RIGHT_CROSS_E - Right side overcross enable.
100730  *  0b0..No right side overcross
100731  *  0b1..Right side overcross
100732  */
100733 #define VPU_G1_SWREG90_SW_RIGHT_CROSS_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_RIGHT_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_RIGHT_CROSS_E_MASK)
100734 /*! @} */
100735 
100736 /*! @name SWREG91 - PiP register 1 and dithering control */
100737 /*! @{ */
100738 
100739 #define VPU_G1_SWREG91_SW_LEFT_CROSS_MASK        (0x7FFU)
100740 #define VPU_G1_SWREG91_SW_LEFT_CROSS_SHIFT       (0U)
100741 /*! SW_LEFT_CROSS - Amount of left side overcross (Horizontal pixels outside of display from the
100742  *    left side). Range must be between [0, ScaledWidth].
100743  */
100744 #define VPU_G1_SWREG91_SW_LEFT_CROSS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_LEFT_CROSS_SHIFT)) & VPU_G1_SWREG91_SW_LEFT_CROSS_MASK)
100745 
100746 #define VPU_G1_SWREG91_SW_RIGHT_CROSS_MASK       (0x3FF800U)
100747 #define VPU_G1_SWREG91_SW_RIGHT_CROSS_SHIFT      (11U)
100748 /*! SW_RIGHT_CROSS - Amount of right side overcross (Horizontal pixels outside of display from the
100749  *    right side). Range must be between [0, ScaledWidth].
100750  */
100751 #define VPU_G1_SWREG91_SW_RIGHT_CROSS(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_RIGHT_CROSS_SHIFT)) & VPU_G1_SWREG91_SW_RIGHT_CROSS_MASK)
100752 
100753 #define VPU_G1_SWREG91_SW_PP_TILED_MODE_MASK     (0xC00000U)
100754 #define VPU_G1_SWREG91_SW_PP_TILED_MODE_SHIFT    (22U)
100755 /*! SW_PP_TILED_MODE - Input data is in tiled mode (at the moment valid only for YCbCr 420 data, pipeline or external mode):
100756  *  0b00..Tiled mode not used
100757  *  0b01..Tiled mode enabled for 8x4 sized tiles
100758  */
100759 #define VPU_G1_SWREG91_SW_PP_TILED_MODE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_PP_TILED_MODE_SHIFT)) & VPU_G1_SWREG91_SW_PP_TILED_MODE_MASK)
100760 
100761 #define VPU_G1_SWREG91_SW_DITHER_SELECT_B_MASK   (0xC000000U)
100762 #define VPU_G1_SWREG91_SW_DITHER_SELECT_B_SHIFT  (26U)
100763 /*! SW_DITHER_SELECT_B - Dithering control for B channel:
100764  *  0b00..dithering disabled
100765  *  0b01..use four-bit dither matrix
100766  *  0b10..use five-bit dither matrix
100767  *  0b11..use six-bit dither matrix
100768  */
100769 #define VPU_G1_SWREG91_SW_DITHER_SELECT_B(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_DITHER_SELECT_B_SHIFT)) & VPU_G1_SWREG91_SW_DITHER_SELECT_B_MASK)
100770 
100771 #define VPU_G1_SWREG91_SW_DITHER_SELECT_G_MASK   (0x30000000U)
100772 #define VPU_G1_SWREG91_SW_DITHER_SELECT_G_SHIFT  (28U)
100773 /*! SW_DITHER_SELECT_G - Dithering control for G channel:
100774  *  0b00..dithering disabled
100775  *  0b01..use four-bit dither matrix
100776  *  0b10..use five-bit dither matrix
100777  *  0b11..use six-bit dither matrix
100778  */
100779 #define VPU_G1_SWREG91_SW_DITHER_SELECT_G(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_DITHER_SELECT_G_SHIFT)) & VPU_G1_SWREG91_SW_DITHER_SELECT_G_MASK)
100780 
100781 #define VPU_G1_SWREG91_SW_DITHER_SELECT_R_MASK   (0xC0000000U)
100782 #define VPU_G1_SWREG91_SW_DITHER_SELECT_R_SHIFT  (30U)
100783 /*! SW_DITHER_SELECT_R - Dithering control for R channel:
100784  *  0b00..dithering disabled
100785  *  0b01..use four-bit dither matrix
100786  *  0b10..use five-bit dither matrix
100787  *  0b11..use six-bit dither matrix
100788  */
100789 #define VPU_G1_SWREG91_SW_DITHER_SELECT_R(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_DITHER_SELECT_R_SHIFT)) & VPU_G1_SWREG91_SW_DITHER_SELECT_R_MASK)
100790 /*! @} */
100791 
100792 /*! @name SWREG92 - Display width and PP input size extension register */
100793 /*! @{ */
100794 
100795 #define VPU_G1_SWREG92_SW_DISPLAY_WIDTH_MASK     (0x1FFFU)
100796 #define VPU_G1_SWREG92_SW_DISPLAY_WIDTH_SHIFT    (0U)
100797 /*! SW_DISPLAY_WIDTH - Width of the display in pixels. Max 4k (depends on HW config support) */
100798 #define VPU_G1_SWREG92_SW_DISPLAY_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_DISPLAY_WIDTH_SHIFT)) & VPU_G1_SWREG92_SW_DISPLAY_WIDTH_MASK)
100799 
100800 #define VPU_G1_SWREG92_SW_UP_CROSS_EXT_MASK      (0xC000U)
100801 #define VPU_G1_SWREG92_SW_UP_CROSS_EXT_SHIFT     (14U)
100802 /*! SW_UP_CROSS_EXT - Extended coordinate for 4k resolution */
100803 #define VPU_G1_SWREG92_SW_UP_CROSS_EXT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_UP_CROSS_EXT_SHIFT)) & VPU_G1_SWREG92_SW_UP_CROSS_EXT_MASK)
100804 
100805 #define VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_MASK    (0x30000U)
100806 #define VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_SHIFT   (16U)
100807 /*! SW_LEFT_CROSS_EXT - Extended coordinate for 4k resolution */
100808 #define VPU_G1_SWREG92_SW_LEFT_CROSS_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_SHIFT)) & VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_MASK)
100809 
100810 #define VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_MASK   (0xC0000U)
100811 #define VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_SHIFT  (18U)
100812 /*! SW_RIGHT_CROSS_EXT - Extended coordinate for 4k resolution */
100813 #define VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_SHIFT)) & VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_MASK)
100814 
100815 #define VPU_G1_SWREG92_SW_CROP_STARTX_EXT_MASK   (0x700000U)
100816 #define VPU_G1_SWREG92_SW_CROP_STARTX_EXT_SHIFT  (20U)
100817 /*! SW_CROP_STARTX_EXT - Extended PP input crop start coordinate y. Used with WEBP */
100818 #define VPU_G1_SWREG92_SW_CROP_STARTX_EXT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_CROP_STARTX_EXT_SHIFT)) & VPU_G1_SWREG92_SW_CROP_STARTX_EXT_MASK)
100819 
100820 #define VPU_G1_SWREG92_SW_CROP_STARTY_EXT_MASK   (0x3800000U)
100821 #define VPU_G1_SWREG92_SW_CROP_STARTY_EXT_SHIFT  (23U)
100822 /*! SW_CROP_STARTY_EXT - Extended PP input crop start coordinate x. Used with WEBP */
100823 #define VPU_G1_SWREG92_SW_CROP_STARTY_EXT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_CROP_STARTY_EXT_SHIFT)) & VPU_G1_SWREG92_SW_CROP_STARTY_EXT_MASK)
100824 
100825 #define VPU_G1_SWREG92_SW_PP_IN_W_EXT_MASK       (0x1C000000U)
100826 #define VPU_G1_SWREG92_SW_PP_IN_W_EXT_SHIFT      (26U)
100827 /*! SW_PP_IN_W_EXT - Extended PP input width. Used with WEBP */
100828 #define VPU_G1_SWREG92_SW_PP_IN_W_EXT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_PP_IN_W_EXT_SHIFT)) & VPU_G1_SWREG92_SW_PP_IN_W_EXT_MASK)
100829 
100830 #define VPU_G1_SWREG92_SW_PP_IN_H_EXT_MASK       (0xE0000000U)
100831 #define VPU_G1_SWREG92_SW_PP_IN_H_EXT_SHIFT      (29U)
100832 /*! SW_PP_IN_H_EXT - Extended PP input height. Used with WEBP */
100833 #define VPU_G1_SWREG92_SW_PP_IN_H_EXT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_PP_IN_H_EXT_SHIFT)) & VPU_G1_SWREG92_SW_PP_IN_H_EXT_MASK)
100834 /*! @} */
100835 
100836 /*! @name SWREG93 - Base address for alpha blend 1 gui component */
100837 /*! @{ */
100838 
100839 #define VPU_G1_SWREG93_SW_ABLEND1_BASE_MASK      (0xFFFFFFFFU)
100840 #define VPU_G1_SWREG93_SW_ABLEND1_BASE_SHIFT     (0U)
100841 /*! SW_ABLEND1_BASE - Base address for alpha blending input 1 (if mask1 is used in alpha blending
100842  *    mode). Format of data is 24 bit RGB/ YCbCr and endian/swap -mode is as in PP input. Amount of
100843  *    data is informed with mask 1 size or with ablend1_scanline if ablend cropping is supported in
100844  *    configuration.
100845  */
100846 #define VPU_G1_SWREG93_SW_ABLEND1_BASE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG93_SW_ABLEND1_BASE_SHIFT)) & VPU_G1_SWREG93_SW_ABLEND1_BASE_MASK)
100847 /*! @} */
100848 
100849 /*! @name SWREG94 - Base address for alpha blend 2 gui component */
100850 /*! @{ */
100851 
100852 #define VPU_G1_SWREG94_SW_ABLEND2_BASE_MASK      (0xFFFFFFFFU)
100853 #define VPU_G1_SWREG94_SW_ABLEND2_BASE_SHIFT     (0U)
100854 /*! SW_ABLEND2_BASE - Base address for alpha blending input 2 (if mask2 is used in alpha blending
100855  *    mode). Format of data is 24 bit RGB/ YCbCr and endian/swap -mode is as in PP input. Amount of
100856  *    data is informed with mask 2 size or with ablend2_scanline if ablend cropping is supported in
100857  *    configuration.
100858  */
100859 #define VPU_G1_SWREG94_SW_ABLEND2_BASE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG94_SW_ABLEND2_BASE_SHIFT)) & VPU_G1_SWREG94_SW_ABLEND2_BASE_MASK)
100860 /*! @} */
100861 
100862 /*! @name SWREG95 - Alpha blend input cropping register (scanline for cropping) */
100863 /*! @{ */
100864 
100865 #define VPU_G1_SWREG95_SW_ABLEND1_SCANL_MASK     (0x1FFFU)
100866 #define VPU_G1_SWREG95_SW_ABLEND1_SCANL_SHIFT    (0U)
100867 /*! SW_ABLEND1_SCANL - Scanline width in pixels for Ablend 1. Usage enabled if corresponding configuration bit is enabled */
100868 #define VPU_G1_SWREG95_SW_ABLEND1_SCANL(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG95_SW_ABLEND1_SCANL_SHIFT)) & VPU_G1_SWREG95_SW_ABLEND1_SCANL_MASK)
100869 
100870 #define VPU_G1_SWREG95_SW_ABLEND2_SCANL_MASK     (0x3FFE000U)
100871 #define VPU_G1_SWREG95_SW_ABLEND2_SCANL_SHIFT    (13U)
100872 /*! SW_ABLEND2_SCANL - Scanline width in pixels for Ablend 2. Usage enabled if corresponding configuration bit is enabled */
100873 #define VPU_G1_SWREG95_SW_ABLEND2_SCANL(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG95_SW_ABLEND2_SCANL_SHIFT)) & VPU_G1_SWREG95_SW_ABLEND2_SCANL_MASK)
100874 /*! @} */
100875 
100876 /*! @name SWREG99 - PP fuse register */
100877 /*! @{ */
100878 
100879 #define VPU_G1_SWREG99_FUSE_PP_MAXW_352_MASK     (0x1000U)
100880 #define VPU_G1_SWREG99_FUSE_PP_MAXW_352_SHIFT    (12U)
100881 /*! FUSE_PP_MAXW_352 - 1 = Max PP output width up to 352 pixels enabled. Priority coded with priority 5 */
100882 #define VPU_G1_SWREG99_FUSE_PP_MAXW_352(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_352_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_352_MASK)
100883 
100884 #define VPU_G1_SWREG99_FUSE_PP_MAXW_720_MASK     (0x2000U)
100885 #define VPU_G1_SWREG99_FUSE_PP_MAXW_720_SHIFT    (13U)
100886 /*! FUSE_PP_MAXW_720 - 1 = Max PP output width up to 720 pixels enabled. Priority coded with priority 4 */
100887 #define VPU_G1_SWREG99_FUSE_PP_MAXW_720(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_720_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_720_MASK)
100888 
100889 #define VPU_G1_SWREG99_FUSE_PP_MAXW_1280_MASK    (0x4000U)
100890 #define VPU_G1_SWREG99_FUSE_PP_MAXW_1280_SHIFT   (14U)
100891 /*! FUSE_PP_MAXW_1280 - 1 = Max PP output width up to 1280 pixels enabled. Priority coded with priority 3 */
100892 #define VPU_G1_SWREG99_FUSE_PP_MAXW_1280(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_1280_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_1280_MASK)
100893 
100894 #define VPU_G1_SWREG99_FUSE_PP_MAXW_1920_MASK    (0x8000U)
100895 #define VPU_G1_SWREG99_FUSE_PP_MAXW_1920_SHIFT   (15U)
100896 /*! FUSE_PP_MAXW_1920 - 1 = Max PP output width up to 1920 pixels enabled. Priority coded with priority 2 */
100897 #define VPU_G1_SWREG99_FUSE_PP_MAXW_1920(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_1920_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_1920_MASK)
100898 
100899 #define VPU_G1_SWREG99_FUSE_PP_MAXW_4K_MASK      (0x10000U)
100900 #define VPU_G1_SWREG99_FUSE_PP_MAXW_4K_SHIFT     (16U)
100901 /*! FUSE_PP_MAXW_4K - 1 = Max PP output width up to 4096 pixels enabled. Priority coded with priority 1 */
100902 #define VPU_G1_SWREG99_FUSE_PP_MAXW_4K(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_4K_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_4K_MASK)
100903 
100904 #define VPU_G1_SWREG99_FUSE_PP_ABLEND_MASK       (0x20000000U)
100905 #define VPU_G1_SWREG99_FUSE_PP_ABLEND_SHIFT      (29U)
100906 /*! FUSE_PP_ABLEND - 1 = Alpha Blending enabled */
100907 #define VPU_G1_SWREG99_FUSE_PP_ABLEND(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_ABLEND_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_ABLEND_MASK)
100908 
100909 #define VPU_G1_SWREG99_FUSE_PP_DEINT_MASK        (0x40000000U)
100910 #define VPU_G1_SWREG99_FUSE_PP_DEINT_SHIFT       (30U)
100911 /*! FUSE_PP_DEINT - 1 = Deinterlacing enabled */
100912 #define VPU_G1_SWREG99_FUSE_PP_DEINT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_DEINT_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_DEINT_MASK)
100913 
100914 #define VPU_G1_SWREG99_FUSE_PP_PP_MASK           (0x80000000U)
100915 #define VPU_G1_SWREG99_FUSE_PP_PP_SHIFT          (31U)
100916 /*! FUSE_PP_PP - 1 = PP enabled */
100917 #define VPU_G1_SWREG99_FUSE_PP_PP(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_PP_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_PP_MASK)
100918 /*! @} */
100919 
100920 /*! @name SWREG100 - Synthesis configuration register post-processor */
100921 /*! @{ */
100922 
100923 #define VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_MASK   (0x1FFFU)
100924 #define VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_SHIFT  (0U)
100925 /*! SW_PPD_MAX_OWIDTH - Max supported PP output width in pixels */
100926 #define VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_SHIFT)) & VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_MASK)
100927 
100928 #define VPU_G1_SWREG100_SW_PPD_IN_TILED_L_MASK   (0xC000U)
100929 #define VPU_G1_SWREG100_SW_PPD_IN_TILED_L_SHIFT  (14U)
100930 /*! SW_PPD_IN_TILED_L - PPD input tiled mode support level
100931  *  0b00..not supported
100932  *  0b01..8x4 tile size supported
100933  */
100934 #define VPU_G1_SWREG100_SW_PPD_IN_TILED_L(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_IN_TILED_L_SHIFT)) & VPU_G1_SWREG100_SW_PPD_IN_TILED_L_MASK)
100935 
100936 #define VPU_G1_SWREG100_SW_PPD_PP_EXIST_MASK     (0x10000U)
100937 #define VPU_G1_SWREG100_SW_PPD_PP_EXIST_SHIFT    (16U)
100938 /*! SW_PPD_PP_EXIST - PPD exists:
100939  *  0b0..No
100940  *  0b1..Yes
100941  */
100942 #define VPU_G1_SWREG100_SW_PPD_PP_EXIST(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_PP_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_PP_EXIST_MASK)
100943 
100944 #define VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_MASK  (0x20000U)
100945 #define VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_SHIFT (17U)
100946 /*! SW_PPD_OBUFF_LEVEL - PP output buffering level:
100947  *  0b0..1 unit output buffering is used
100948  *  0b1..4 unit output buffering is used
100949  */
100950 #define VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_SHIFT)) & VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_MASK)
100951 
100952 #define VPU_G1_SWREG100_SW_PPD_OEN_VERSION_MASK  (0x40000U)
100953 #define VPU_G1_SWREG100_SW_PPD_OEN_VERSION_SHIFT (18U)
100954 /*! SW_PPD_OEN_VERSION - PP output endian version:
100955  *  0b0..Endian mode supported for other than RGB
100956  *  0b1..Endian mode supported for any output format
100957  */
100958 #define VPU_G1_SWREG100_SW_PPD_OEN_VERSION(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_OEN_VERSION_SHIFT)) & VPU_G1_SWREG100_SW_PPD_OEN_VERSION_MASK)
100959 
100960 #define VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_MASK  (0x800000U)
100961 #define VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_SHIFT (23U)
100962 /*! SW_PPD_IBUFF_LEVEL - PP input buffering level:
100963  *  0b0..1 MB input buffering is used
100964  *  0b1..4 MB input buffering is used
100965  */
100966 #define VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_SHIFT)) & VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_MASK)
100967 
100968 #define VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_MASK  (0x1000000U)
100969 #define VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_SHIFT (24U)
100970 /*! SW_PPD_BLEND_EXIST - Alpha blending exists:
100971  *  0b0..No
100972  *  0b1..Yes
100973  */
100974 #define VPU_G1_SWREG100_SW_PPD_BLEND_EXIST(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_MASK)
100975 
100976 #define VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_MASK  (0x2000000U)
100977 #define VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_SHIFT (25U)
100978 /*! SW_PPD_DEINT_EXIST - De-interlacing exits:
100979  *  0b0..No
100980  *  0b1..Yes
100981  */
100982 #define VPU_G1_SWREG100_SW_PPD_DEINT_EXIST(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_MASK)
100983 
100984 #define VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_MASK  (0xC000000U)
100985 #define VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_SHIFT (26U)
100986 /*! SW_PPD_SCALE_LEVEL - Scaling support:
100987  *  0b00..No scaling
100988  *  0b01..Scaling with lo performance architecture
100989  *  0b10..Scaling with high performance architecture
100990  *  0b11..Scaling with high performance architecture + fast downscaling enabled
100991  */
100992 #define VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_SHIFT)) & VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_MASK)
100993 
100994 #define VPU_G1_SWREG100_SW_PPD_DITH_EXIST_MASK   (0x10000000U)
100995 #define VPU_G1_SWREG100_SW_PPD_DITH_EXIST_SHIFT  (28U)
100996 /*! SW_PPD_DITH_EXIST - Dithering exists:
100997  *  0b0..No
100998  *  0b1..Yes
100999  */
101000 #define VPU_G1_SWREG100_SW_PPD_DITH_EXIST(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_DITH_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_DITH_EXIST_MASK)
101001 
101002 #define VPU_G1_SWREG100_SW_PPD_TILED_EXIST_MASK  (0x20000000U)
101003 #define VPU_G1_SWREG100_SW_PPD_TILED_EXIST_SHIFT (29U)
101004 /*! SW_PPD_TILED_EXIST - PP output YCbYCr 422 tiled support (4x4 pixel tiles)
101005  *  0b0..Not supported
101006  *  0b1..Supported
101007  */
101008 #define VPU_G1_SWREG100_SW_PPD_TILED_EXIST(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_TILED_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_TILED_EXIST_MASK)
101009 
101010 #define VPU_G1_SWREG100_SW_PPD_PIXAC_E_MASK      (0x40000000U)
101011 #define VPU_G1_SWREG100_SW_PPD_PIXAC_E_SHIFT     (30U)
101012 /*! SW_PPD_PIXAC_E - Pixel Accurate PP output mode exists:
101013  *  0b0..PIP, Scaling and masks can be adjusted by steps of 8 pixels (width) or 2 pixels (height)
101014  *  0b1..PIP, Scaling and masks can be adjusted by steps of 1 pixel for RGB and 2 pixels for subsampled chroma
101015  *       formats (by using bus specific write strobe functionality)
101016  */
101017 #define VPU_G1_SWREG100_SW_PPD_PIXAC_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_PIXAC_E_SHIFT)) & VPU_G1_SWREG100_SW_PPD_PIXAC_E_MASK)
101018 
101019 #define VPU_G1_SWREG100_SW_ABLEND_CROP_E_MASK    (0x80000000U)
101020 #define VPU_G1_SWREG100_SW_ABLEND_CROP_E_SHIFT   (31U)
101021 /*! SW_ABLEND_CROP_E - Alpha blending support for input cropping:
101022  *  0b0..Not supported. External memory must include the exact image of the area being alpha blended.
101023  *  0b1..Supported. External memory can include a picture from blended area can be cropped. Requires usage of swreg95.
101024  */
101025 #define VPU_G1_SWREG100_SW_ABLEND_CROP_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_ABLEND_CROP_E_SHIFT)) & VPU_G1_SWREG100_SW_ABLEND_CROP_E_MASK)
101026 /*! @} */
101027 
101028 /*! @name SWREG102 - Base address for H264 decoded chroma picture */
101029 /*! @{ */
101030 
101031 #define VPU_G1_SWREG102_SW_CH_BASE_E_MASK        (0x1U)
101032 #define VPU_G1_SWREG102_SW_CH_BASE_E_SHIFT       (0U)
101033 /*! SW_CH_BASE_E - chroma address separate mode enable:
101034  *  0b1..HW outputs decoded chroma picture to independent memory address
101035  *  0b0..HW outputs decoded chroma picture to the end of decoded luma picture. HW calculates the chroma picture
101036  *       address according to sw_dec_base and luma data length.
101037  */
101038 #define VPU_G1_SWREG102_SW_CH_BASE_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG102_SW_CH_BASE_E_SHIFT)) & VPU_G1_SWREG102_SW_CH_BASE_E_MASK)
101039 
101040 #define VPU_G1_SWREG102_SW_DEC_CH_BASE_MASK      (0xFFFFFFFCU)
101041 #define VPU_G1_SWREG102_SW_DEC_CH_BASE_SHIFT     (2U)
101042 /*! SW_DEC_CH_BASE - Valid only if chroma address separate mode is enabled. H264: Base address for
101043  *    decoder output chroma picture. Points directly to start of decoder output chroma picture or
101044  *    field.
101045  */
101046 #define VPU_G1_SWREG102_SW_DEC_CH_BASE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG102_SW_DEC_CH_BASE_SHIFT)) & VPU_G1_SWREG102_SW_DEC_CH_BASE_MASK)
101047 /*! @} */
101048 
101049 /*! @name SWREG103 - Base address for reference chroma picture index 0 */
101050 /*! @{ */
101051 
101052 #define VPU_G1_SWREG103_SW_REFER0_CH_BASE_MASK   (0xFFFFFFFCU)
101053 #define VPU_G1_SWREG103_SW_REFER0_CH_BASE_SHIFT  (2U)
101054 /*! SW_REFER0_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 0. */
101055 #define VPU_G1_SWREG103_SW_REFER0_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG103_SW_REFER0_CH_BASE_SHIFT)) & VPU_G1_SWREG103_SW_REFER0_CH_BASE_MASK)
101056 /*! @} */
101057 
101058 /*! @name SWREG104 - Base address for reference chroma picture index 1 */
101059 /*! @{ */
101060 
101061 #define VPU_G1_SWREG104_SW_REFER1_CH_BASE_MASK   (0xFFFFFFFCU)
101062 #define VPU_G1_SWREG104_SW_REFER1_CH_BASE_SHIFT  (2U)
101063 /*! SW_REFER1_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 1. */
101064 #define VPU_G1_SWREG104_SW_REFER1_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG104_SW_REFER1_CH_BASE_SHIFT)) & VPU_G1_SWREG104_SW_REFER1_CH_BASE_MASK)
101065 /*! @} */
101066 
101067 /*! @name SWREG105 - Base address for reference chroma picture index 2 */
101068 /*! @{ */
101069 
101070 #define VPU_G1_SWREG105_SW_REFER2_CH_BASE_MASK   (0xFFFFFFFCU)
101071 #define VPU_G1_SWREG105_SW_REFER2_CH_BASE_SHIFT  (2U)
101072 /*! SW_REFER2_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 2. */
101073 #define VPU_G1_SWREG105_SW_REFER2_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG105_SW_REFER2_CH_BASE_SHIFT)) & VPU_G1_SWREG105_SW_REFER2_CH_BASE_MASK)
101074 /*! @} */
101075 
101076 /*! @name SWREG106 - Base address for reference chroma picture index 3 */
101077 /*! @{ */
101078 
101079 #define VPU_G1_SWREG106_SW_REFER3_CH_BASE_MASK   (0xFFFFFFFCU)
101080 #define VPU_G1_SWREG106_SW_REFER3_CH_BASE_SHIFT  (2U)
101081 /*! SW_REFER3_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 3. */
101082 #define VPU_G1_SWREG106_SW_REFER3_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG106_SW_REFER3_CH_BASE_SHIFT)) & VPU_G1_SWREG106_SW_REFER3_CH_BASE_MASK)
101083 /*! @} */
101084 
101085 /*! @name SWREG107 - Base address for reference chroma picture index 4 */
101086 /*! @{ */
101087 
101088 #define VPU_G1_SWREG107_SW_REFER4_CH_BASE_MASK   (0xFFFFFFFCU)
101089 #define VPU_G1_SWREG107_SW_REFER4_CH_BASE_SHIFT  (2U)
101090 /*! SW_REFER4_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 4. */
101091 #define VPU_G1_SWREG107_SW_REFER4_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG107_SW_REFER4_CH_BASE_SHIFT)) & VPU_G1_SWREG107_SW_REFER4_CH_BASE_MASK)
101092 /*! @} */
101093 
101094 /*! @name SWREG108 - Base address for reference chroma picture index 5 */
101095 /*! @{ */
101096 
101097 #define VPU_G1_SWREG108_SW_REFER5_CH_BASE_MASK   (0xFFFFFFFCU)
101098 #define VPU_G1_SWREG108_SW_REFER5_CH_BASE_SHIFT  (2U)
101099 /*! SW_REFER5_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 5. */
101100 #define VPU_G1_SWREG108_SW_REFER5_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG108_SW_REFER5_CH_BASE_SHIFT)) & VPU_G1_SWREG108_SW_REFER5_CH_BASE_MASK)
101101 /*! @} */
101102 
101103 /*! @name SWREG109 - Base address for reference chroma picture index 6 */
101104 /*! @{ */
101105 
101106 #define VPU_G1_SWREG109_SW_REFER6_CH_BASE_MASK   (0xFFFFFFFCU)
101107 #define VPU_G1_SWREG109_SW_REFER6_CH_BASE_SHIFT  (2U)
101108 /*! SW_REFER6_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 6. */
101109 #define VPU_G1_SWREG109_SW_REFER6_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG109_SW_REFER6_CH_BASE_SHIFT)) & VPU_G1_SWREG109_SW_REFER6_CH_BASE_MASK)
101110 /*! @} */
101111 
101112 /*! @name SWREG110 - Base address for reference chroma picture index 7 */
101113 /*! @{ */
101114 
101115 #define VPU_G1_SWREG110_SW_REFER7_CH_BASE_MASK   (0xFFFFFFFCU)
101116 #define VPU_G1_SWREG110_SW_REFER7_CH_BASE_SHIFT  (2U)
101117 /*! SW_REFER7_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 7. */
101118 #define VPU_G1_SWREG110_SW_REFER7_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG110_SW_REFER7_CH_BASE_SHIFT)) & VPU_G1_SWREG110_SW_REFER7_CH_BASE_MASK)
101119 /*! @} */
101120 
101121 /*! @name SWREG111 - Base address for reference chroma picture index 8 */
101122 /*! @{ */
101123 
101124 #define VPU_G1_SWREG111_SW_REFER8_CH_BASE_MASK   (0xFFFFFFFCU)
101125 #define VPU_G1_SWREG111_SW_REFER8_CH_BASE_SHIFT  (2U)
101126 /*! SW_REFER8_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 8. */
101127 #define VPU_G1_SWREG111_SW_REFER8_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG111_SW_REFER8_CH_BASE_SHIFT)) & VPU_G1_SWREG111_SW_REFER8_CH_BASE_MASK)
101128 /*! @} */
101129 
101130 /*! @name SWREG112 - Base address for reference chroma picture index 9 */
101131 /*! @{ */
101132 
101133 #define VPU_G1_SWREG112_SW_REFER9_CH_BASE_MASK   (0xFFFFFFFCU)
101134 #define VPU_G1_SWREG112_SW_REFER9_CH_BASE_SHIFT  (2U)
101135 /*! SW_REFER9_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 9. */
101136 #define VPU_G1_SWREG112_SW_REFER9_CH_BASE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG112_SW_REFER9_CH_BASE_SHIFT)) & VPU_G1_SWREG112_SW_REFER9_CH_BASE_MASK)
101137 /*! @} */
101138 
101139 /*! @name SWREG113 - Base address for reference chroma picture index 10 */
101140 /*! @{ */
101141 
101142 #define VPU_G1_SWREG113_SW_REFER10_CH_BASE_MASK  (0xFFFFFFFCU)
101143 #define VPU_G1_SWREG113_SW_REFER10_CH_BASE_SHIFT (2U)
101144 /*! SW_REFER10_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 10. */
101145 #define VPU_G1_SWREG113_SW_REFER10_CH_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG113_SW_REFER10_CH_BASE_SHIFT)) & VPU_G1_SWREG113_SW_REFER10_CH_BASE_MASK)
101146 /*! @} */
101147 
101148 /*! @name SWREG114 - Base address for reference chroma picture index 11 */
101149 /*! @{ */
101150 
101151 #define VPU_G1_SWREG114_SW_REFER11_CH_BASE_MASK  (0xFFFFFFFCU)
101152 #define VPU_G1_SWREG114_SW_REFER11_CH_BASE_SHIFT (2U)
101153 /*! SW_REFER11_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 11. */
101154 #define VPU_G1_SWREG114_SW_REFER11_CH_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG114_SW_REFER11_CH_BASE_SHIFT)) & VPU_G1_SWREG114_SW_REFER11_CH_BASE_MASK)
101155 /*! @} */
101156 
101157 /*! @name SWREG115 - Base address for reference chroma picture index 12 */
101158 /*! @{ */
101159 
101160 #define VPU_G1_SWREG115_SW_REFER12_CH_BASE_MASK  (0xFFFFFFFCU)
101161 #define VPU_G1_SWREG115_SW_REFER12_CH_BASE_SHIFT (2U)
101162 /*! SW_REFER12_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 12. */
101163 #define VPU_G1_SWREG115_SW_REFER12_CH_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG115_SW_REFER12_CH_BASE_SHIFT)) & VPU_G1_SWREG115_SW_REFER12_CH_BASE_MASK)
101164 /*! @} */
101165 
101166 /*! @name SWREG116 - Base address for reference chroma picture index 13 */
101167 /*! @{ */
101168 
101169 #define VPU_G1_SWREG116_SW_REFER13_CH_BASE_MASK  (0xFFFFFFFCU)
101170 #define VPU_G1_SWREG116_SW_REFER13_CH_BASE_SHIFT (2U)
101171 /*! SW_REFER13_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 13. */
101172 #define VPU_G1_SWREG116_SW_REFER13_CH_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG116_SW_REFER13_CH_BASE_SHIFT)) & VPU_G1_SWREG116_SW_REFER13_CH_BASE_MASK)
101173 /*! @} */
101174 
101175 /*! @name SWREG117 - Base address for reference chroma picture index 14 */
101176 /*! @{ */
101177 
101178 #define VPU_G1_SWREG117_SW_REFER14_CH_BASE_MASK  (0xFFFFFFFCU)
101179 #define VPU_G1_SWREG117_SW_REFER14_CH_BASE_SHIFT (2U)
101180 /*! SW_REFER14_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 14. */
101181 #define VPU_G1_SWREG117_SW_REFER14_CH_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG117_SW_REFER14_CH_BASE_SHIFT)) & VPU_G1_SWREG117_SW_REFER14_CH_BASE_MASK)
101182 /*! @} */
101183 
101184 /*! @name SWREG118 - Base address for reference chroma picture index 15 */
101185 /*! @{ */
101186 
101187 #define VPU_G1_SWREG118_SW_REFER15_CH_BASE_MASK  (0xFFFFFFFCU)
101188 #define VPU_G1_SWREG118_SW_REFER15_CH_BASE_SHIFT (2U)
101189 /*! SW_REFER15_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 15. */
101190 #define VPU_G1_SWREG118_SW_REFER15_CH_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG118_SW_REFER15_CH_BASE_SHIFT)) & VPU_G1_SWREG118_SW_REFER15_CH_BASE_MASK)
101191 /*! @} */
101192 
101193 
101194 /*!
101195  * @}
101196  */ /* end of group VPU_G1_Register_Masks */
101197 
101198 
101199 /* VPU_G1 - Peripheral instance base addresses */
101200 /** Peripheral VPU_G1 base address */
101201 #define VPU_G1_BASE                              (0x38300000u)
101202 /** Peripheral VPU_G1 base pointer */
101203 #define VPU_G1                                   ((VPU_G1_Type *)VPU_G1_BASE)
101204 /** Array initializer of VPU_G1 peripheral base addresses */
101205 #define VPU_G1_BASE_ADDRS                        { VPU_G1_BASE }
101206 /** Array initializer of VPU_G1 peripheral base pointers */
101207 #define VPU_G1_BASE_PTRS                         { VPU_G1 }
101208 
101209 /*!
101210  * @}
101211  */ /* end of group VPU_G1_Peripheral_Access_Layer */
101212 
101213 
101214 /* ----------------------------------------------------------------------------
101215    -- VPU_G1_H264 Peripheral Access Layer
101216    ---------------------------------------------------------------------------- */
101217 
101218 /*!
101219  * @addtogroup VPU_G1_H264_Peripheral_Access_Layer VPU_G1_H264 Peripheral Access Layer
101220  * @{
101221  */
101222 
101223 /** VPU_G1_H264 - Register Layout Typedef */
101224 typedef struct {
101225        uint8_t RESERVED_0[16];
101226   __IO uint32_t SWREG4;                            /**< Decoder control register 1 (picture parameters), offset: 0x10 */
101227   __IO uint32_t SWREG5;                            /**< Decoder control register 2 (stream decoding table selects), offset: 0x14 */
101228   __IO uint32_t SWREG6;                            /**< Decoder control register 3 (stream buffer information), offset: 0x18 */
101229   __IO uint32_t SWREG7;                            /**< Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control), offset: 0x1C */
101230   __IO uint32_t SWREG8;                            /**< Decoder control register 5 (H264, VC-1, VP6, Progressive JPEG and RV control), offset: 0x20 */
101231   __IO uint32_t SWREG9;                            /**< Decoder control register 6 / base address for MB-control (RLC) / VC-1 intensity control 0/ VP6,VP7,VP8 ctrl-stream length/ RV pic slice amount, offset: 0x24 */
101232   __IO uint32_t SWREG10;                           /**< Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register, offset: 0x28 */
101233   __IO uint32_t SWREG11;                           /**< Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2, offset: 0x2C */
101234        uint8_t RESERVED_1[8];
101235   __IO uint32_t SWREG14;                           /**< Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture, offset: 0x38 */
101236   __IO uint32_t SWREG15;                           /**< Base address for reference picture index 1 / JPEG control, offset: 0x3C */
101237   __IO uint32_t SWREG16;                           /**< Base address for reference picture index 2 / List of VLC code lengths in first JPEG AC table, offset: 0x40 */
101238   __IO uint32_t SWREG17;                           /**< Base address for reference picture index 3 / List of VLC code lengths in first JPEG AC table, offset: 0x44 */
101239   __IO uint32_t SWREG18;                           /**< Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base, offset: 0x48 */
101240   __IO uint32_t SWREG19;                           /**< Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps, offset: 0x4C */
101241   __IO uint32_t SWREG20;                           /**< Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x50 */
101242   __IO uint32_t SWREG21;                           /**< Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x54 */
101243   __IO uint32_t SWREG22;                           /**< Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base, offset: 0x58 */
101244   __IO uint32_t SWREG23;                           /**< Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base, offset: 0x5C */
101245   __IO uint32_t SWREG24;                           /**< Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base, offset: 0x60 */
101246   __IO uint32_t SWREG25;                           /**< Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base, offset: 0x64 */
101247   __IO uint32_t SWREG26;                           /**< Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base, offset: 0x68 */
101248   __IO uint32_t SWREG27;                           /**< Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table, offset: 0x6C */
101249   __IO uint32_t SWREG28;                           /**< Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base, offset: 0x70 */
101250   __IO uint32_t SWREG29;                           /**< Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base, offset: 0x74 */
101251   __IO uint32_t SWREG30;                           /**< Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts, offset: 0x78 */
101252   __IO uint32_t SWREG31;                           /**< Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts, offset: 0x7C */
101253   __IO uint32_t SWREG32;                           /**< Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels, offset: 0x80 */
101254   __IO uint32_t SWREG33;                           /**< Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values, offset: 0x84 */
101255   __IO uint32_t SWREG34;                           /**< Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps, offset: 0x88 */
101256   __IO uint32_t SWREG35;                           /**< Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x8C */
101257   __IO uint32_t SWREG36;                           /**< Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x90 */
101258   __IO uint32_t SWREG37;                           /**< Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps, offset: 0x94 */
101259   __IO uint32_t SWREG38;                           /**< Reference picture long term flags (H264 VLC) / VPx prediction filter taps, offset: 0x98 */
101260   __IO uint32_t SWREG39;                           /**< Reference picture valid flags (H264 VLC) / VPx prediction filter taps, offset: 0x9C */
101261        uint8_t RESERVED_2[8];
101262   __IO uint32_t SWREG42_H264;                      /**< bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base, offset: 0xA8 */
101263   __IO uint32_t SWREG43_H264;                      /**< bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base, offset: 0xAC */
101264   __IO uint32_t SWREG44_H264;                      /**< bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps, offset: 0xB0 */
101265   __IO uint32_t SWREG45;                           /**< bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps, offset: 0xB4 */
101266   __IO uint32_t SWREG46;                           /**< bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values, offset: 0xB8 */
101267   __IO uint32_t SWREG47;                           /**< bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values, offset: 0xBC */
101268 } VPU_G1_H264_Type;
101269 
101270 /* ----------------------------------------------------------------------------
101271    -- VPU_G1_H264 Register Masks
101272    ---------------------------------------------------------------------------- */
101273 
101274 /*!
101275  * @addtogroup VPU_G1_H264_Register_Masks VPU_G1_H264 Register Masks
101276  * @{
101277  */
101278 
101279 /*! @name SWREG4 - Decoder control register 1 (picture parameters) */
101280 /*! @{ */
101281 
101282 #define VPU_G1_H264_SWREG4_SW_REF_FRAMES_MASK    (0x1FU)
101283 #define VPU_G1_H264_SWREG4_SW_REF_FRAMES_SHIFT   (0U)
101284 /*! SW_REF_FRAMES - H.264: num_ref_frames, maximum number of short and long term reference frames in
101285  *    decoded picture buffer VC-1: num_ref semantics
101286  */
101287 #define VPU_G1_H264_SWREG4_SW_REF_FRAMES(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_REF_FRAMES_SHIFT)) & VPU_G1_H264_SWREG4_SW_REF_FRAMES_MASK)
101288 
101289 #define VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_MASK    (0x40U)
101290 #define VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_SHIFT   (6U)
101291 /*! SW_ALT_SCAN_E - indicates alternative vertical scan method used for interlaced frames */
101292 #define VPU_G1_H264_SWREG4_SW_ALT_SCAN_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_SHIFT)) & VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_MASK)
101293 
101294 #define VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_MASK (0x780U)
101295 #define VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_SHIFT (7U)
101296 /*! SW_MB_HEIGHT_OFF - The amount of meaningful vertical pixels in last MB (height offset 0 if
101297  *    exactly 16 pixels multiple picture and all the vertical pixels in last MB are meaningfull
101298  */
101299 #define VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_SHIFT)) & VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_MASK)
101300 
101301 #define VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_MASK (0x7F800U)
101302 #define VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_SHIFT (11U)
101303 /*! SW_PIC_MB_HEIGHT_P - Picture height in macroblocks =((height in pixels+15)/16). Picture height
101304  *    is informed as size of the (progressive) frame also for single field (of interlaced content) is
101305  *    being decoded
101306  */
101307 #define VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_SHIFT)) & VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_MASK)
101308 
101309 #define VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_MASK  (0x780000U)
101310 #define VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_SHIFT (19U)
101311 /*! SW_MB_WIDTH_OFF - The amount of meaningfull horizontal pixels in last MB (width offset) 0 if
101312  *    exactly 16 pixels multiple picture and all the horizontal pixels in last MB are meaningfull
101313  */
101314 #define VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_SHIFT)) & VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_MASK)
101315 
101316 #define VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_MASK  (0xFF800000U)
101317 #define VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_SHIFT (23U)
101318 /*! SW_PIC_MB_WIDTH - Picture width in macroblocks = ((width in pixels + 15) /16) */
101319 #define VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_SHIFT)) & VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_MASK)
101320 /*! @} */
101321 
101322 /*! @name SWREG5 - Decoder control register 2 (stream decoding table selects) */
101323 /*! @{ */
101324 
101325 #define VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_MASK (0x1U)
101326 #define VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_SHIFT (0U)
101327 /*! SW_FIELDPIC_FLAG_E - Flag for streamd that field_pic_flag exists in stream */
101328 #define VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_SHIFT)) & VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_MASK)
101329 
101330 #define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_MASK (0x7C000U)
101331 #define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_SHIFT (14U)
101332 /*! SW_CH_QP_OFFSET2 - Chroma Qp filter offset for cr type */
101333 #define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_SHIFT)) & VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_MASK)
101334 
101335 #define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_MASK  (0xF80000U)
101336 #define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_SHIFT (19U)
101337 /*! SW_CH_QP_OFFSET - Chroma Qp filter offset. (For H.264 this offset concerns Cb only) */
101338 #define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_SHIFT)) & VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_MASK)
101339 
101340 #define VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_MASK (0x1000000U)
101341 #define VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_SHIFT (24U)
101342 #define VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_SHIFT)) & VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_MASK)
101343 
101344 #define VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_MASK (0x2000000U)
101345 #define VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_SHIFT (25U)
101346 /*! SW_SYNC_MARKER_E - Sync markers enable
101347  *  0b0..synch markers are not used
101348  *  0b1..synch markers are used.
101349  */
101350 #define VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_SHIFT)) & VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_MASK)
101351 
101352 #define VPU_G1_H264_SWREG5_SW_STRM_START_BIT_MASK (0xFC000000U)
101353 #define VPU_G1_H264_SWREG5_SW_STRM_START_BIT_SHIFT (26U)
101354 /*! SW_STRM_START_BIT - Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base) */
101355 #define VPU_G1_H264_SWREG5_SW_STRM_START_BIT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_STRM_START_BIT_SHIFT)) & VPU_G1_H264_SWREG5_SW_STRM_START_BIT_MASK)
101356 /*! @} */
101357 
101358 /*! @name SWREG6 - Decoder control register 3 (stream buffer information) */
101359 /*! @{ */
101360 
101361 #define VPU_G1_H264_SWREG6_SW_STREAM_LEN_MASK    (0xFFFFFFU)
101362 #define VPU_G1_H264_SWREG6_SW_STREAM_LEN_SHIFT   (0U)
101363 /*! SW_STREAM_LEN - Amount of stream data bytes in input buffer. If the given buffer size is not
101364  *    enough for finishing the picture the corresponding interrupt is given and new stream buffer base
101365  *    address and stream buffer size information should be given (assosiates with sw_rlc_vlc_base).
101366  *    For VC-1/VP6 the buffer must include data for one picture/slice of the picture For
101367  *    H264/MPEG4/H263/MPEG2/MPEG1 the buffer must include at least data for one slice/VP of the picture For
101368  *    JPEG the buffer size must be a multiple of 256 bytes or the amount of data for one picture.
101369  */
101370 #define VPU_G1_H264_SWREG6_SW_STREAM_LEN(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_STREAM_LEN_SHIFT)) & VPU_G1_H264_SWREG6_SW_STREAM_LEN_MASK)
101371 
101372 #define VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_MASK (0x1000000U)
101373 #define VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_SHIFT (24U)
101374 /*! SW_CH_8PIX_ILEAV_E - Enable for additional chrominance data format writing where decoder writes
101375  *    chrominance in group of 8 pixels of Cb and then corresponding 8 pixels of Cr. Data is written
101376  *    to sw_dec_ch8pix_base. Cannot be used if tiled mode is enabled
101377  */
101378 #define VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_SHIFT)) & VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_MASK)
101379 
101380 #define VPU_G1_H264_SWREG6_SW_INIT_QP_MASK       (0x7E000000U)
101381 #define VPU_G1_H264_SWREG6_SW_INIT_QP_SHIFT      (25U)
101382 /*! SW_INIT_QP - Initial value for quantization parameter (picture quantizer). */
101383 #define VPU_G1_H264_SWREG6_SW_INIT_QP(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_INIT_QP_SHIFT)) & VPU_G1_H264_SWREG6_SW_INIT_QP_MASK)
101384 
101385 #define VPU_G1_H264_SWREG6_SW_START_CODE_E_MASK  (0x80000000U)
101386 #define VPU_G1_H264_SWREG6_SW_START_CODE_E_SHIFT (31U)
101387 /*! SW_START_CODE_E - Bit for indicating stream start code existence:
101388  *  0b0..stream doesn't contain start codes
101389  *  0b1..stream contains start codes
101390  */
101391 #define VPU_G1_H264_SWREG6_SW_START_CODE_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_START_CODE_E_SHIFT)) & VPU_G1_H264_SWREG6_SW_START_CODE_E_MASK)
101392 /*! @} */
101393 
101394 /*! @name SWREG7 - Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control) */
101395 /*! @{ */
101396 
101397 #define VPU_G1_H264_SWREG7_SW_FRAMENUM_MASK      (0xFFFFU)
101398 #define VPU_G1_H264_SWREG7_SW_FRAMENUM_SHIFT     (0U)
101399 /*! SW_FRAMENUM - current frame_num, used to identify short-term reference frames. Used in reference picture reordering */
101400 #define VPU_G1_H264_SWREG7_SW_FRAMENUM(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_FRAMENUM_SHIFT)) & VPU_G1_H264_SWREG7_SW_FRAMENUM_MASK)
101401 
101402 #define VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_MASK  (0x1F0000U)
101403 #define VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_SHIFT (16U)
101404 /*! SW_FRAMENUM_LEN - H.264: Bit length of frame_num in data stream RV: frame size length. Informs
101405  *    how many bits in stream are used for frame size (HW discards these bits)
101406  */
101407 #define VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_SHIFT)) & VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_MASK)
101408 
101409 #define VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_MASK (0x2000000U)
101410 #define VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_SHIFT (25U)
101411 /*! SW_AVS_H264_H_EXT - Resolution extension to support 4k resolution for AVS/H264. Used as MSB of sw_pic_mb_height */
101412 #define VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_SHIFT)) & VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_MASK)
101413 
101414 #define VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_MASK (0xC000000U)
101415 #define VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT (26U)
101416 /*! SW_WEIGHT_BIPR_IDC - weighted prediction specification for B slices:
101417  *  0b00..default weighted prediction is applied to B slices
101418  *  0b01..explicit weighted prediction shall be applied to B slices
101419  *  0b10..implicit weighted prediction shall be applied to B slices
101420  */
101421 #define VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT)) & VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_MASK)
101422 
101423 #define VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_MASK (0x10000000U)
101424 #define VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_SHIFT (28U)
101425 /*! SW_WEIGHT_PRED_E - Weighted prediction enable for P slices */
101426 #define VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_MASK)
101427 
101428 #define VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_MASK (0x20000000U)
101429 #define VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_SHIFT (29U)
101430 /*! SW_DIR_8X8_INFER_E - Specifies the method to use to derive luma motion vectors in B_skip,
101431  *    B_Direct_16x16 and B_direct_8x8_inference_flag (see direct_8x8_inference flag)
101432  */
101433 #define VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_MASK)
101434 
101435 #define VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_MASK  (0x40000000U)
101436 #define VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_SHIFT (30U)
101437 /*! SW_BLACKWHITE_E
101438  *  0b0..4:2:0 sampling format
101439  *  0b1..4:0:0 sampling format (H264 monochroma)
101440  */
101441 #define VPU_G1_H264_SWREG7_SW_BLACKWHITE_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_MASK)
101442 
101443 #define VPU_G1_H264_SWREG7_SW_CABAC_E_MASK       (0x80000000U)
101444 #define VPU_G1_H264_SWREG7_SW_CABAC_E_SHIFT      (31U)
101445 /*! SW_CABAC_E - CABAC enable */
101446 #define VPU_G1_H264_SWREG7_SW_CABAC_E(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_CABAC_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_CABAC_E_MASK)
101447 /*! @} */
101448 
101449 /*! @name SWREG8 - Decoder control register 5 (H264, VC-1, VP6, Progressive JPEG and RV control) */
101450 /*! @{ */
101451 
101452 #define VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_MASK    (0xFFFFU)
101453 #define VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_SHIFT   (0U)
101454 /*! SW_IDR_PIC_ID - idr_pic_id, identifies IDR (instantaneous decoding refresh) picture */
101455 #define VPU_G1_H264_SWREG8_SW_IDR_PIC_ID(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_SHIFT)) & VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_MASK)
101456 
101457 #define VPU_G1_H264_SWREG8_SW_IDR_PIC_E_MASK     (0x10000U)
101458 #define VPU_G1_H264_SWREG8_SW_IDR_PIC_E_SHIFT    (16U)
101459 /*! SW_IDR_PIC_E - IDR (instantaneous decoding refresh) picture flag. */
101460 #define VPU_G1_H264_SWREG8_SW_IDR_PIC_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_IDR_PIC_E_SHIFT)) & VPU_G1_H264_SWREG8_SW_IDR_PIC_E_MASK)
101461 
101462 #define VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_MASK (0xFFE0000U)
101463 #define VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_SHIFT (17U)
101464 /*! SW_REFPIC_MK_LEN - Length of decoded reference picture marking bits */
101465 #define VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_SHIFT)) & VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_MASK)
101466 
101467 #define VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_MASK (0x10000000U)
101468 #define VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_SHIFT (28U)
101469 /*! SW_8X8TRANS_FLAG_E - 8x8 transform flag enable for stream decoding */
101470 #define VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_SHIFT)) & VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_MASK)
101471 
101472 #define VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_MASK (0x20000000U)
101473 #define VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_SHIFT (29U)
101474 /*! SW_RDPIC_CNT_PRES - redundant_pic_cnt_present_flag specifies whether redundant_pic_cnt syntax elements are present in the slice header. */
101475 #define VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_SHIFT)) & VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_MASK)
101476 
101477 #define VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_MASK (0x40000000U)
101478 #define VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_SHIFT (30U)
101479 /*! SW_FILT_CTRL_PRES - deblocking_filter_control_present_flag indicates whether extra variables
101480  *    controlling characteristics of the deblocking filter are present in the slice header.
101481  */
101482 #define VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_SHIFT)) & VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_MASK)
101483 
101484 #define VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_MASK (0x80000000U)
101485 #define VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_SHIFT (31U)
101486 /*! SW_CONST_INTRA_E - constrained_intra_pred_flag equal to 1 specifies that intra prediction uses
101487  *    only neighbouring intra macroblocks in prediction. When equal to 0 also neighbouring inter
101488  *    macroblocks are used in intra prediction process.
101489  */
101490 #define VPU_G1_H264_SWREG8_SW_CONST_INTRA_E(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_SHIFT)) & VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_MASK)
101491 /*! @} */
101492 
101493 /*! @name SWREG9 - Decoder control register 6 / base address for MB-control (RLC) / VC-1 intensity control 0/ VP6,VP7,VP8 ctrl-stream length/ RV pic slice amount */
101494 /*! @{ */
101495 
101496 #define VPU_G1_H264_SWREG9_SW_POC_LENGTH_MASK    (0xFFU)
101497 #define VPU_G1_H264_SWREG9_SW_POC_LENGTH_SHIFT   (0U)
101498 /*! SW_POC_LENGTH - Length of picture order count field in stream */
101499 #define VPU_G1_H264_SWREG9_SW_POC_LENGTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_POC_LENGTH_SHIFT)) & VPU_G1_H264_SWREG9_SW_POC_LENGTH_MASK)
101500 
101501 #define VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_MASK (0x7C000U)
101502 #define VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_SHIFT (14U)
101503 /*! SW_REFIDX0_ACTIVE - Specifies the maximum reference index that can be used while decoding inter
101504  *    predicted macro blocks. This is same as in previous decoders (width increased with q bit)
101505  */
101506 #define VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_SHIFT)) & VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_MASK)
101507 
101508 #define VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_MASK (0xF80000U)
101509 #define VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_SHIFT (19U)
101510 /*! SW_REFIDX1_ACTIVE - Specifies the maximum reference index that can be used while decoding inter predicted macro blocks. */
101511 #define VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_SHIFT)) & VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_MASK)
101512 
101513 #define VPU_G1_H264_SWREG9_SW_PPS_ID_MASK        (0xFF000000U)
101514 #define VPU_G1_H264_SWREG9_SW_PPS_ID_SHIFT       (24U)
101515 /*! SW_PPS_ID - pic_parameter_set_id, identifies the picture parameter set that is referred to in the slice header. */
101516 #define VPU_G1_H264_SWREG9_SW_PPS_ID(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_PPS_ID_SHIFT)) & VPU_G1_H264_SWREG9_SW_PPS_ID_MASK)
101517 /*! @} */
101518 
101519 /*! @name SWREG10 - Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register */
101520 /*! @{ */
101521 
101522 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_MASK (0x1FU)
101523 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_SHIFT (0U)
101524 /*! SW_PINIT_RLIST_F4 - Initial reference picture list for P forward picid 4 */
101525 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_MASK)
101526 
101527 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_MASK (0x3E0U)
101528 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_SHIFT (5U)
101529 /*! SW_PINIT_RLIST_F5 - Initial reference picture list for P forward picid 5 */
101530 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_MASK)
101531 
101532 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_MASK (0x7C00U)
101533 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_SHIFT (10U)
101534 /*! SW_PINIT_RLIST_F6 - Initial reference picture list for P forward picid 6 */
101535 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_MASK)
101536 
101537 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_MASK (0xF8000U)
101538 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_SHIFT (15U)
101539 /*! SW_PINIT_RLIST_F7 - Initial reference picture list for P forward picid 7 */
101540 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_MASK)
101541 
101542 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_MASK (0x1F00000U)
101543 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_SHIFT (20U)
101544 /*! SW_PINIT_RLIST_F8 - Initial reference picture list for P forward picid 8 */
101545 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_MASK)
101546 
101547 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_MASK (0x3E000000U)
101548 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_SHIFT (25U)
101549 /*! SW_PINIT_RLIST_F9 - Initial reference picture list for P forward picid 9 */
101550 #define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_MASK)
101551 /*! @} */
101552 
101553 /*! @name SWREG11 - Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2 */
101554 /*! @{ */
101555 
101556 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_MASK (0x1FU)
101557 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_SHIFT (0U)
101558 /*! SW_PINIT_RLIST_F10 - Initial reference picture list for P forward picid 10 */
101559 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_MASK)
101560 
101561 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_MASK (0x3E0U)
101562 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_SHIFT (5U)
101563 /*! SW_PINIT_RLIST_F11 - Initial reference picture list for P forward picid 11 */
101564 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_MASK)
101565 
101566 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_MASK (0x7C00U)
101567 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_SHIFT (10U)
101568 /*! SW_PINIT_RLIST_F12 - Initial reference picture list for P forward picid 12 */
101569 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_MASK)
101570 
101571 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_MASK (0xF8000U)
101572 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_SHIFT (15U)
101573 /*! SW_PINIT_RLIST_F13 - Initial reference picture list for P forward picid 13 */
101574 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_MASK)
101575 
101576 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_MASK (0x1F00000U)
101577 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_SHIFT (20U)
101578 /*! SW_PINIT_RLIST_F14 - Initial reference picture list for P forward picid 14 */
101579 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_MASK)
101580 
101581 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_MASK (0x3E000000U)
101582 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_SHIFT (25U)
101583 /*! SW_PINIT_RLIST_F15 - Initial reference picture list for P forward picid 15 */
101584 #define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_MASK)
101585 /*! @} */
101586 
101587 /*! @name SWREG14 - Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture */
101588 /*! @{ */
101589 
101590 #define VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_MASK (0x1U)
101591 #define VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_SHIFT (0U)
101592 /*! SW_REFER0_TOPC_E - Which field of reference picture is closer to current picture:
101593  *  0b0..Bottom field is closer to current picture
101594  *  0b1..Top field is closer to current picture
101595  */
101596 #define VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_MASK)
101597 
101598 #define VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_MASK (0x2U)
101599 #define VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_SHIFT (1U)
101600 /*! SW_REFER0_FIELD_E - Refer picture consist of single fields or frame:
101601  *  0b0..reference picture consists of frame
101602  *  0b1..reference picture consists of fields
101603  */
101604 #define VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_MASK)
101605 
101606 #define VPU_G1_H264_SWREG14_SW_REFER0_BASE_MASK  (0xFFFFFFFCU)
101607 #define VPU_G1_H264_SWREG14_SW_REFER0_BASE_SHIFT (2U)
101608 /*! SW_REFER0_BASE - Base address for reference picture index 0. See picture index definition from toplevel_sp */
101609 #define VPU_G1_H264_SWREG14_SW_REFER0_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG14_SW_REFER0_BASE_SHIFT)) & VPU_G1_H264_SWREG14_SW_REFER0_BASE_MASK)
101610 /*! @} */
101611 
101612 /*! @name SWREG15 - Base address for reference picture index 1 / JPEG control */
101613 /*! @{ */
101614 
101615 #define VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_MASK (0x1U)
101616 #define VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_SHIFT (0U)
101617 /*! SW_REFER1_TOPC_E - Which field of reference picture is closer to current picture:
101618  *  0b0..bottom field is closer to current picture
101619  *  0b1..top field is closer to current picture
101620  */
101621 #define VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_MASK)
101622 
101623 #define VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_MASK (0x2U)
101624 #define VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_SHIFT (1U)
101625 /*! SW_REFER1_FIELD_E - Refer picture consist of single fields or frame:
101626  *  0b0..reference picture consists of frame
101627  *  0b1..reference picture consists of fields
101628  */
101629 #define VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_MASK)
101630 
101631 #define VPU_G1_H264_SWREG15_SW_REFER1_BASE_MASK  (0xFFFFFFFCU)
101632 #define VPU_G1_H264_SWREG15_SW_REFER1_BASE_SHIFT (2U)
101633 /*! SW_REFER1_BASE - Base address for reference picture index 1. See picture index definition from
101634  *    toplevel_sp. For VP8 this base address is used as Chrominance base address for reference
101635  *    picture 0 (if vp8 stride configuration is enabled)
101636  */
101637 #define VPU_G1_H264_SWREG15_SW_REFER1_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG15_SW_REFER1_BASE_SHIFT)) & VPU_G1_H264_SWREG15_SW_REFER1_BASE_MASK)
101638 /*! @} */
101639 
101640 /*! @name SWREG16 - Base address for reference picture index 2 / List of VLC code lengths in first JPEG AC table */
101641 /*! @{ */
101642 
101643 #define VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_MASK (0x1U)
101644 #define VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_SHIFT (0U)
101645 /*! SW_REFER2_TOPC_E - Which field of reference picture is closer to current picture:
101646  *  0b0..bottom field is closer to current picture
101647  *  0b1..top field is closer to current picture
101648  */
101649 #define VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_MASK)
101650 
101651 #define VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_MASK (0x2U)
101652 #define VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_SHIFT (1U)
101653 /*! SW_REFER2_FIELD_E - Refer picture consist of single fields or frame:
101654  *  0b0..reference picture consists of frame
101655  *  0b1..reference picture consists of fields
101656  */
101657 #define VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_MASK)
101658 
101659 #define VPU_G1_H264_SWREG16_SW_REFER2_BASE_MASK  (0xFFFFFFFCU)
101660 #define VPU_G1_H264_SWREG16_SW_REFER2_BASE_SHIFT (2U)
101661 /*! SW_REFER2_BASE - Base address for reference picture index 2. See picture index definition from
101662  *    toplevel_sp. For VP8 video this base address is used as Golden reference chrominance base
101663  *    address (if vp8 stride configuration is enabled)
101664  */
101665 #define VPU_G1_H264_SWREG16_SW_REFER2_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG16_SW_REFER2_BASE_SHIFT)) & VPU_G1_H264_SWREG16_SW_REFER2_BASE_MASK)
101666 /*! @} */
101667 
101668 /*! @name SWREG17 - Base address for reference picture index 3 / List of VLC code lengths in first JPEG AC table */
101669 /*! @{ */
101670 
101671 #define VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_MASK (0x1U)
101672 #define VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_SHIFT (0U)
101673 /*! SW_REFER3_TOPC_E - Which field of reference picture is closer to current picture:
101674  *  0b0..bottom field is closer to current picture
101675  *  0b1..top field is closer to current picture
101676  */
101677 #define VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_MASK)
101678 
101679 #define VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_MASK (0x2U)
101680 #define VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_SHIFT (1U)
101681 /*! SW_REFER3_FIELD_E - Refer picture consist of single fields or frame:
101682  *  0b0..reference picture consists of frame
101683  *  0b1..reference picture consists of fields
101684  */
101685 #define VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_MASK)
101686 
101687 #define VPU_G1_H264_SWREG17_SW_REFER3_BASE_MASK  (0xFFFFFFFCU)
101688 #define VPU_G1_H264_SWREG17_SW_REFER3_BASE_SHIFT (2U)
101689 /*! SW_REFER3_BASE - Base address for reference picture index 3. See picture index definition from
101690  *    toplevel_sp. For VP8 video this base address is used as Alternate reference chrominance base
101691  *    address (if vp8 stride configuration is enabled)
101692  */
101693 #define VPU_G1_H264_SWREG17_SW_REFER3_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG17_SW_REFER3_BASE_SHIFT)) & VPU_G1_H264_SWREG17_SW_REFER3_BASE_MASK)
101694 /*! @} */
101695 
101696 /*! @name SWREG18 - Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base */
101697 /*! @{ */
101698 
101699 #define VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_MASK (0x1U)
101700 #define VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_SHIFT (0U)
101701 /*! SW_REFER4_TOPC_E - Which field of reference picture is closer to current picture:
101702  *  0b0..bottom field is closer to current picture
101703  *  0b1..top field is closer to current picture
101704  */
101705 #define VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_MASK)
101706 
101707 #define VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_MASK (0x2U)
101708 #define VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_SHIFT (1U)
101709 /*! SW_REFER4_FIELD_E - Refer picture consist of single fields or frame:
101710  *  0b0..reference picture consists of frame
101711  *  0b1..reference picture consists of fields
101712  */
101713 #define VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_MASK)
101714 
101715 #define VPU_G1_H264_SWREG18_SW_REFER4_BASE_MASK  (0xFFFFFFFCU)
101716 #define VPU_G1_H264_SWREG18_SW_REFER4_BASE_SHIFT (2U)
101717 /*! SW_REFER4_BASE - H264: Base address for reference picture index 4 VP6/VP7/VP8: Base address for
101718  *    Golden reference picture (corresponds picid 4)
101719  */
101720 #define VPU_G1_H264_SWREG18_SW_REFER4_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG18_SW_REFER4_BASE_SHIFT)) & VPU_G1_H264_SWREG18_SW_REFER4_BASE_MASK)
101721 /*! @} */
101722 
101723 /*! @name SWREG19 - Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps */
101724 /*! @{ */
101725 
101726 #define VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_MASK (0x1U)
101727 #define VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_SHIFT (0U)
101728 /*! SW_REFER5_TOPC_E - Which field of reference picture is closer to current picture:
101729  *  0b0..bottom field is closer to current picture
101730  *  0b1..top field is closer to current picture
101731  */
101732 #define VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_MASK)
101733 
101734 #define VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_MASK (0x2U)
101735 #define VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_SHIFT (1U)
101736 /*! SW_REFER5_FIELD_E - Refer picture consist of single fields or frame:
101737  *  0b0..reference picture consists of frame
101738  *  0b1..reference picture consists of fields
101739  */
101740 #define VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_MASK)
101741 
101742 #define VPU_G1_H264_SWREG19_SW_REFER5_BASE_MASK  (0xFFFFFFFCU)
101743 #define VPU_G1_H264_SWREG19_SW_REFER5_BASE_SHIFT (2U)
101744 /*! SW_REFER5_BASE - H.264: Base address for reference picture index 5 VP8: Base address for
101745  *    alternate reference picture (corresponds picid 5)
101746  */
101747 #define VPU_G1_H264_SWREG19_SW_REFER5_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG19_SW_REFER5_BASE_SHIFT)) & VPU_G1_H264_SWREG19_SW_REFER5_BASE_MASK)
101748 /*! @} */
101749 
101750 /*! @name SWREG20 - Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
101751 /*! @{ */
101752 
101753 #define VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_MASK (0x1U)
101754 #define VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_SHIFT (0U)
101755 /*! SW_REFER6_TOPC_E - Which field of reference picture is closer to current picture:
101756  *  0b0..bottom field is closer to current picture
101757  *  0b1..top field is closer to current picture
101758  */
101759 #define VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_MASK)
101760 
101761 #define VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_MASK (0x2U)
101762 #define VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_SHIFT (1U)
101763 /*! SW_REFER6_FIELD_E - Refer picture consist of single fields or frame:
101764  *  0b0..reference picture consists of frame
101765  *  0b1..reference picture consists of fields
101766  */
101767 #define VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_MASK)
101768 
101769 #define VPU_G1_H264_SWREG20_SW_REFER6_BASE_MASK  (0xFFFFFFFCU)
101770 #define VPU_G1_H264_SWREG20_SW_REFER6_BASE_SHIFT (2U)
101771 /*! SW_REFER6_BASE - Base address for reference picture index 6. For VP8 video this base address is
101772  *    used as decoder output chrominance base address (if vp8 stride configuration is enabled)
101773  */
101774 #define VPU_G1_H264_SWREG20_SW_REFER6_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG20_SW_REFER6_BASE_SHIFT)) & VPU_G1_H264_SWREG20_SW_REFER6_BASE_MASK)
101775 /*! @} */
101776 
101777 /*! @name SWREG21 - Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
101778 /*! @{ */
101779 
101780 #define VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_MASK (0x1U)
101781 #define VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_SHIFT (0U)
101782 /*! SW_REFER7_TOPC_E - Which field of reference picture is closer to current picture:
101783  *  0b0..bottom field is closer to current picture
101784  *  0b1..top field is closer to current picture
101785  */
101786 #define VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_MASK)
101787 
101788 #define VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_MASK (0x2U)
101789 #define VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_SHIFT (1U)
101790 /*! SW_REFER7_FIELD_E - Refer picture consist of single fields or frame:
101791  *  0b0..reference picture consists of frame
101792  *  0b1..reference picture consists of fields
101793  */
101794 #define VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_MASK)
101795 
101796 #define VPU_G1_H264_SWREG21_SW_REFER7_BASE_MASK  (0xFFFFFFFCU)
101797 #define VPU_G1_H264_SWREG21_SW_REFER7_BASE_SHIFT (2U)
101798 /*! SW_REFER7_BASE - Base address for reference picture index 7 */
101799 #define VPU_G1_H264_SWREG21_SW_REFER7_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG21_SW_REFER7_BASE_SHIFT)) & VPU_G1_H264_SWREG21_SW_REFER7_BASE_MASK)
101800 /*! @} */
101801 
101802 /*! @name SWREG22 - Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base */
101803 /*! @{ */
101804 
101805 #define VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_MASK (0x1U)
101806 #define VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_SHIFT (0U)
101807 /*! SW_REFER8_TOPC_E - Which field of reference picture is closer to current picture:
101808  *  0b0..bottom field is closer to current picture
101809  *  0b1..top field is closer to current picture
101810  */
101811 #define VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_MASK)
101812 
101813 #define VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_MASK (0x2U)
101814 #define VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_SHIFT (1U)
101815 /*! SW_REFER8_FIELD_E - Refer picture consist of single fields or frame:
101816  *  0b0..reference picture consists of frame
101817  *  0b1..reference picture consists of fields
101818  */
101819 #define VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_MASK)
101820 
101821 #define VPU_G1_H264_SWREG22_SW_REFER8_BASE_MASK  (0xFFFFFFFCU)
101822 #define VPU_G1_H264_SWREG22_SW_REFER8_BASE_SHIFT (2U)
101823 /*! SW_REFER8_BASE - Base address for reference picture index 8 */
101824 #define VPU_G1_H264_SWREG22_SW_REFER8_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG22_SW_REFER8_BASE_SHIFT)) & VPU_G1_H264_SWREG22_SW_REFER8_BASE_MASK)
101825 /*! @} */
101826 
101827 /*! @name SWREG23 - Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base */
101828 /*! @{ */
101829 
101830 #define VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_MASK (0x1U)
101831 #define VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_SHIFT (0U)
101832 /*! SW_REFER9_TOPC_E - Which field of reference picture is closer to current picture:
101833  *  0b0..bottom field is closer to current picture
101834  *  0b1..top field is closer to current picture
101835  */
101836 #define VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_MASK)
101837 
101838 #define VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_MASK (0x2U)
101839 #define VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_SHIFT (1U)
101840 /*! SW_REFER9_FIELD_E - Refer picture consist of single fields or frame:
101841  *  0b0..reference picture consists of frame
101842  *  0b1..reference picture consists of fields
101843  */
101844 #define VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_MASK)
101845 
101846 #define VPU_G1_H264_SWREG23_SW_REFER9_BASE_MASK  (0xFFFFFFFCU)
101847 #define VPU_G1_H264_SWREG23_SW_REFER9_BASE_SHIFT (2U)
101848 /*! SW_REFER9_BASE - Base address for reference picture index 9 */
101849 #define VPU_G1_H264_SWREG23_SW_REFER9_BASE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG23_SW_REFER9_BASE_SHIFT)) & VPU_G1_H264_SWREG23_SW_REFER9_BASE_MASK)
101850 /*! @} */
101851 
101852 /*! @name SWREG24 - Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base */
101853 /*! @{ */
101854 
101855 #define VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_MASK (0x1U)
101856 #define VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_SHIFT (0U)
101857 /*! SW_REFER10_TOPC_E - Which field of reference picture is closer to current picture:
101858  *  0b0..bottom field is closer to current picture
101859  *  0b1..top field is closer to current picture
101860  */
101861 #define VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_MASK)
101862 
101863 #define VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_MASK (0x2U)
101864 #define VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_SHIFT (1U)
101865 /*! SW_REFER10_FIELD_E - Refer picture consist of single fields or frame:
101866  *  0b0..reference picture consists of frame
101867  *  0b1..reference picture consists of fields
101868  */
101869 #define VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_MASK)
101870 
101871 #define VPU_G1_H264_SWREG24_SW_REFER10_BASE_MASK (0xFFFFFFFCU)
101872 #define VPU_G1_H264_SWREG24_SW_REFER10_BASE_SHIFT (2U)
101873 /*! SW_REFER10_BASE - Base address for reference picture index 10 */
101874 #define VPU_G1_H264_SWREG24_SW_REFER10_BASE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG24_SW_REFER10_BASE_SHIFT)) & VPU_G1_H264_SWREG24_SW_REFER10_BASE_MASK)
101875 /*! @} */
101876 
101877 /*! @name SWREG25 - Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base */
101878 /*! @{ */
101879 
101880 #define VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_MASK (0x1U)
101881 #define VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_SHIFT (0U)
101882 /*! SW_REFER11_TOPC_E - Which field of reference picture is closer to current picture:
101883  *  0b0..bottom field is closer to current picture
101884  *  0b1..top field is closer to current picture
101885  */
101886 #define VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_MASK)
101887 
101888 #define VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_MASK (0x2U)
101889 #define VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_SHIFT (1U)
101890 /*! SW_REFER11_FIELD_E - Refer picture consist of single fields or frame:
101891  *  0b0..reference picture consists of frame
101892  *  0b1..reference picture consists of fields
101893  */
101894 #define VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_MASK)
101895 
101896 #define VPU_G1_H264_SWREG25_SW_REFER11_BASE_MASK (0xFFFFFFFCU)
101897 #define VPU_G1_H264_SWREG25_SW_REFER11_BASE_SHIFT (2U)
101898 /*! SW_REFER11_BASE - Base address for reference picture index 11 */
101899 #define VPU_G1_H264_SWREG25_SW_REFER11_BASE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG25_SW_REFER11_BASE_SHIFT)) & VPU_G1_H264_SWREG25_SW_REFER11_BASE_MASK)
101900 /*! @} */
101901 
101902 /*! @name SWREG26 - Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base */
101903 /*! @{ */
101904 
101905 #define VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_MASK (0x1U)
101906 #define VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_SHIFT (0U)
101907 /*! SW_REFER12_TOPC_E - Which field of reference picture is closer to current picture:
101908  *  0b0..bottom field is closer to current picture
101909  *  0b1..top field is closer to current picture
101910  */
101911 #define VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_MASK)
101912 
101913 #define VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_MASK (0x2U)
101914 #define VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_SHIFT (1U)
101915 /*! SW_REFER12_FIELD_E - Refer picture consist of single fields or frame:
101916  *  0b0..reference picture consists of frame
101917  *  0b1..reference picture consists of fields
101918  */
101919 #define VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_MASK)
101920 
101921 #define VPU_G1_H264_SWREG26_SW_REFER12_BASE_MASK (0xFFFFFFFCU)
101922 #define VPU_G1_H264_SWREG26_SW_REFER12_BASE_SHIFT (2U)
101923 /*! SW_REFER12_BASE - Base address for reference picture index 12 */
101924 #define VPU_G1_H264_SWREG26_SW_REFER12_BASE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG26_SW_REFER12_BASE_SHIFT)) & VPU_G1_H264_SWREG26_SW_REFER12_BASE_MASK)
101925 /*! @} */
101926 
101927 /*! @name SWREG27 - Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table */
101928 /*! @{ */
101929 
101930 #define VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_MASK (0x1U)
101931 #define VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_SHIFT (0U)
101932 /*! SW_REFER13_TOPC_E - Which field of reference picture is closer to current picture:
101933  *  0b0..bottom field is closer to current picture
101934  *  0b1..top field is closer to current picture
101935  */
101936 #define VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_MASK)
101937 
101938 #define VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_MASK (0x2U)
101939 #define VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_SHIFT (1U)
101940 /*! SW_REFER13_FIELD_E - Refer picture consist of single fields or frame:
101941  *  0b0..reference picture consists of frame
101942  *  0b1..reference picture consists of fields
101943  */
101944 #define VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_MASK)
101945 
101946 #define VPU_G1_H264_SWREG27_SW_REFER13_BASE_MASK (0xFFFFFFFCU)
101947 #define VPU_G1_H264_SWREG27_SW_REFER13_BASE_SHIFT (2U)
101948 /*! SW_REFER13_BASE - Base address for reference picture index 13 */
101949 #define VPU_G1_H264_SWREG27_SW_REFER13_BASE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG27_SW_REFER13_BASE_SHIFT)) & VPU_G1_H264_SWREG27_SW_REFER13_BASE_MASK)
101950 /*! @} */
101951 
101952 /*! @name SWREG28 - Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base */
101953 /*! @{ */
101954 
101955 #define VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_MASK (0x1U)
101956 #define VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_SHIFT (0U)
101957 /*! SW_REFER14_TOPC_E - Which field of reference picture is closer to current picture:
101958  *  0b0..bottom field is closer to current picture
101959  *  0b1..top field is closer to current picture
101960  */
101961 #define VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_MASK)
101962 
101963 #define VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_MASK (0x2U)
101964 #define VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_SHIFT (1U)
101965 /*! SW_REFER14_FIELD_E - Refer picture consist of single fields or frame:
101966  *  0b0..reference picture consists of frame
101967  *  0b1..reference picture consists of fields
101968  */
101969 #define VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_MASK)
101970 
101971 #define VPU_G1_H264_SWREG28_SW_REFER14_BASE_MASK (0xFFFFFFFCU)
101972 #define VPU_G1_H264_SWREG28_SW_REFER14_BASE_SHIFT (2U)
101973 /*! SW_REFER14_BASE - Base address for reference picture index 14 */
101974 #define VPU_G1_H264_SWREG28_SW_REFER14_BASE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG28_SW_REFER14_BASE_SHIFT)) & VPU_G1_H264_SWREG28_SW_REFER14_BASE_MASK)
101975 /*! @} */
101976 
101977 /*! @name SWREG29 - Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base */
101978 /*! @{ */
101979 
101980 #define VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_MASK (0x1U)
101981 #define VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_SHIFT (0U)
101982 /*! SW_REFER15_TOPC_E - Which field of reference picture is closer to current picture:
101983  *  0b0..bottom field is closer to current picture
101984  *  0b1..top field is closer to current picture
101985  */
101986 #define VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_MASK)
101987 
101988 #define VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_MASK (0x2U)
101989 #define VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_SHIFT (1U)
101990 /*! SW_REFER15_FIELD_E - Refer picture consist of single fields or frame:
101991  *  0b0..reference picture consists of frame
101992  *  0b1..reference picture consists of fields
101993  */
101994 #define VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_MASK)
101995 
101996 #define VPU_G1_H264_SWREG29_SW_REFER15_BASE_MASK (0xFFFFFFFCU)
101997 #define VPU_G1_H264_SWREG29_SW_REFER15_BASE_SHIFT (2U)
101998 /*! SW_REFER15_BASE - Base address for reference picture index 15. For Multi View Coding this base address refers to inter view base address */
101999 #define VPU_G1_H264_SWREG29_SW_REFER15_BASE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG29_SW_REFER15_BASE_SHIFT)) & VPU_G1_H264_SWREG29_SW_REFER15_BASE_MASK)
102000 /*! @} */
102001 
102002 /*! @name SWREG30 - Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts */
102003 /*! @{ */
102004 
102005 #define VPU_G1_H264_SWREG30_SW_REFER0_NBR_MASK   (0xFFFFU)
102006 #define VPU_G1_H264_SWREG30_SW_REFER0_NBR_SHIFT  (0U)
102007 /*! SW_REFER0_NBR - Number for reference picture index 0 */
102008 #define VPU_G1_H264_SWREG30_SW_REFER0_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG30_SW_REFER0_NBR_SHIFT)) & VPU_G1_H264_SWREG30_SW_REFER0_NBR_MASK)
102009 
102010 #define VPU_G1_H264_SWREG30_SW_REFER1_NBR_MASK   (0xFFFF0000U)
102011 #define VPU_G1_H264_SWREG30_SW_REFER1_NBR_SHIFT  (16U)
102012 /*! SW_REFER1_NBR - Number for reference picture index 1 */
102013 #define VPU_G1_H264_SWREG30_SW_REFER1_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG30_SW_REFER1_NBR_SHIFT)) & VPU_G1_H264_SWREG30_SW_REFER1_NBR_MASK)
102014 /*! @} */
102015 
102016 /*! @name SWREG31 - Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts */
102017 /*! @{ */
102018 
102019 #define VPU_G1_H264_SWREG31_SW_REFER2_NBR_MASK   (0xFFFFU)
102020 #define VPU_G1_H264_SWREG31_SW_REFER2_NBR_SHIFT  (0U)
102021 /*! SW_REFER2_NBR - Number for reference picture index 2 */
102022 #define VPU_G1_H264_SWREG31_SW_REFER2_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG31_SW_REFER2_NBR_SHIFT)) & VPU_G1_H264_SWREG31_SW_REFER2_NBR_MASK)
102023 
102024 #define VPU_G1_H264_SWREG31_SW_REFER3_NBR_MASK   (0xFFFF0000U)
102025 #define VPU_G1_H264_SWREG31_SW_REFER3_NBR_SHIFT  (16U)
102026 /*! SW_REFER3_NBR - Number for reference picture index 3 */
102027 #define VPU_G1_H264_SWREG31_SW_REFER3_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG31_SW_REFER3_NBR_SHIFT)) & VPU_G1_H264_SWREG31_SW_REFER3_NBR_MASK)
102028 /*! @} */
102029 
102030 /*! @name SWREG32 - Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels */
102031 /*! @{ */
102032 
102033 #define VPU_G1_H264_SWREG32_SW_REFER4_NBR_MASK   (0xFFFFU)
102034 #define VPU_G1_H264_SWREG32_SW_REFER4_NBR_SHIFT  (0U)
102035 /*! SW_REFER4_NBR - Number for reference picture index 4 */
102036 #define VPU_G1_H264_SWREG32_SW_REFER4_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG32_SW_REFER4_NBR_SHIFT)) & VPU_G1_H264_SWREG32_SW_REFER4_NBR_MASK)
102037 
102038 #define VPU_G1_H264_SWREG32_SW_REFER5_NBR_MASK   (0xFFFF0000U)
102039 #define VPU_G1_H264_SWREG32_SW_REFER5_NBR_SHIFT  (16U)
102040 /*! SW_REFER5_NBR - Number for reference picture index 5 */
102041 #define VPU_G1_H264_SWREG32_SW_REFER5_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG32_SW_REFER5_NBR_SHIFT)) & VPU_G1_H264_SWREG32_SW_REFER5_NBR_MASK)
102042 /*! @} */
102043 
102044 /*! @name SWREG33 - Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values */
102045 /*! @{ */
102046 
102047 #define VPU_G1_H264_SWREG33_SW_REFER6_NBR_MASK   (0xFFFFU)
102048 #define VPU_G1_H264_SWREG33_SW_REFER6_NBR_SHIFT  (0U)
102049 /*! SW_REFER6_NBR - Number for reference picture index 6 */
102050 #define VPU_G1_H264_SWREG33_SW_REFER6_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG33_SW_REFER6_NBR_SHIFT)) & VPU_G1_H264_SWREG33_SW_REFER6_NBR_MASK)
102051 
102052 #define VPU_G1_H264_SWREG33_SW_REFER7_NBR_MASK   (0xFFFF0000U)
102053 #define VPU_G1_H264_SWREG33_SW_REFER7_NBR_SHIFT  (16U)
102054 /*! SW_REFER7_NBR - Number for reference picture index 7 */
102055 #define VPU_G1_H264_SWREG33_SW_REFER7_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG33_SW_REFER7_NBR_SHIFT)) & VPU_G1_H264_SWREG33_SW_REFER7_NBR_MASK)
102056 /*! @} */
102057 
102058 /*! @name SWREG34 - Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps */
102059 /*! @{ */
102060 
102061 #define VPU_G1_H264_SWREG34_SW_REFER8_NBR_MASK   (0xFFFFU)
102062 #define VPU_G1_H264_SWREG34_SW_REFER8_NBR_SHIFT  (0U)
102063 /*! SW_REFER8_NBR - Number for reference picture index 8 */
102064 #define VPU_G1_H264_SWREG34_SW_REFER8_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG34_SW_REFER8_NBR_SHIFT)) & VPU_G1_H264_SWREG34_SW_REFER8_NBR_MASK)
102065 
102066 #define VPU_G1_H264_SWREG34_SW_REFER9_NBR_MASK   (0xFFFF0000U)
102067 #define VPU_G1_H264_SWREG34_SW_REFER9_NBR_SHIFT  (16U)
102068 /*! SW_REFER9_NBR - Number for reference picture index 9 */
102069 #define VPU_G1_H264_SWREG34_SW_REFER9_NBR(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG34_SW_REFER9_NBR_SHIFT)) & VPU_G1_H264_SWREG34_SW_REFER9_NBR_MASK)
102070 /*! @} */
102071 
102072 /*! @name SWREG35 - Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps */
102073 /*! @{ */
102074 
102075 #define VPU_G1_H264_SWREG35_SW_REFER10_NBR_MASK  (0xFFFFU)
102076 #define VPU_G1_H264_SWREG35_SW_REFER10_NBR_SHIFT (0U)
102077 /*! SW_REFER10_NBR - Number for reference picture index 10 */
102078 #define VPU_G1_H264_SWREG35_SW_REFER10_NBR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG35_SW_REFER10_NBR_SHIFT)) & VPU_G1_H264_SWREG35_SW_REFER10_NBR_MASK)
102079 
102080 #define VPU_G1_H264_SWREG35_SW_REFER11_NBR_MASK  (0xFFFF0000U)
102081 #define VPU_G1_H264_SWREG35_SW_REFER11_NBR_SHIFT (16U)
102082 /*! SW_REFER11_NBR - Number for reference picture index 11 */
102083 #define VPU_G1_H264_SWREG35_SW_REFER11_NBR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG35_SW_REFER11_NBR_SHIFT)) & VPU_G1_H264_SWREG35_SW_REFER11_NBR_MASK)
102084 /*! @} */
102085 
102086 /*! @name SWREG36 - Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps */
102087 /*! @{ */
102088 
102089 #define VPU_G1_H264_SWREG36_SW_REFER12_NBR_MASK  (0xFFFFU)
102090 #define VPU_G1_H264_SWREG36_SW_REFER12_NBR_SHIFT (0U)
102091 /*! SW_REFER12_NBR - Number for reference picture index 12 */
102092 #define VPU_G1_H264_SWREG36_SW_REFER12_NBR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG36_SW_REFER12_NBR_SHIFT)) & VPU_G1_H264_SWREG36_SW_REFER12_NBR_MASK)
102093 
102094 #define VPU_G1_H264_SWREG36_SW_REFER13_NBR_MASK  (0xFFFF0000U)
102095 #define VPU_G1_H264_SWREG36_SW_REFER13_NBR_SHIFT (16U)
102096 /*! SW_REFER13_NBR - Number for reference picture index 13 */
102097 #define VPU_G1_H264_SWREG36_SW_REFER13_NBR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG36_SW_REFER13_NBR_SHIFT)) & VPU_G1_H264_SWREG36_SW_REFER13_NBR_MASK)
102098 /*! @} */
102099 
102100 /*! @name SWREG37 - Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps */
102101 /*! @{ */
102102 
102103 #define VPU_G1_H264_SWREG37_SW_REFER14_NBR_MASK  (0xFFFFU)
102104 #define VPU_G1_H264_SWREG37_SW_REFER14_NBR_SHIFT (0U)
102105 /*! SW_REFER14_NBR - Number for reference picture index 14 */
102106 #define VPU_G1_H264_SWREG37_SW_REFER14_NBR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG37_SW_REFER14_NBR_SHIFT)) & VPU_G1_H264_SWREG37_SW_REFER14_NBR_MASK)
102107 
102108 #define VPU_G1_H264_SWREG37_SW_REFER15_NBR_MASK  (0xFFFF0000U)
102109 #define VPU_G1_H264_SWREG37_SW_REFER15_NBR_SHIFT (16U)
102110 /*! SW_REFER15_NBR - Number for reference picture index 15 */
102111 #define VPU_G1_H264_SWREG37_SW_REFER15_NBR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG37_SW_REFER15_NBR_SHIFT)) & VPU_G1_H264_SWREG37_SW_REFER15_NBR_MASK)
102112 /*! @} */
102113 
102114 /*! @name SWREG38 - Reference picture long term flags (H264 VLC) / VPx prediction filter taps */
102115 /*! @{ */
102116 
102117 #define VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_MASK (0xFFFFFFFFU)
102118 #define VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_SHIFT (0U)
102119 /*! SW_REFER_LTERM_E - Long term flag for reference picture index [31:0]. Definition: If frame is
102120  *    being decoded the bits 31:15 are used, Bit 31 for picture index 0, Bit 30 for picture index 1
102121  *    etc... IF field is being decoded the bits 31:0 are used, Bit 31 for reference picture 0 top
102122  *    field, bit 30 for reference picture 0 bottom field etc...
102123  */
102124 #define VPU_G1_H264_SWREG38_SW_REFER_LTERM_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_SHIFT)) & VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_MASK)
102125 /*! @} */
102126 
102127 /*! @name SWREG39 - Reference picture valid flags (H264 VLC) / VPx prediction filter taps */
102128 /*! @{ */
102129 
102130 #define VPU_G1_H264_SWREG39_SW_REFER_VALID_E_MASK (0xFFFFFFFFU)
102131 #define VPU_G1_H264_SWREG39_SW_REFER_VALID_E_SHIFT (0U)
102132 /*! SW_REFER_VALID_E - Valid flag for reference picture index [31:0].Definition: If frame is being
102133  *    decoded the bits 31:15 are used, Bit 31 for picture index 0, Bit 30 for picture index 1 etc...
102134  *    IF field is being decoded the bits 31:0 are used, Bit 31 for reference picture 0 top field,
102135  *    bit 30 for reference picture 0 bottom field etc...
102136  */
102137 #define VPU_G1_H264_SWREG39_SW_REFER_VALID_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG39_SW_REFER_VALID_E_SHIFT)) & VPU_G1_H264_SWREG39_SW_REFER_VALID_E_MASK)
102138 /*! @} */
102139 
102140 /*! @name SWREG42_H264 - bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base */
102141 /*! @{ */
102142 
102143 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_MASK (0x1FU)
102144 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_SHIFT (0U)
102145 /*! SW_BINIT_RLIST_F0_H264 - Initial reference picture list for bi-direct forward picid 0 */
102146 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_MASK)
102147 
102148 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_MASK (0x3E0U)
102149 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_SHIFT (5U)
102150 /*! SW_BINIT_RLIST_B0_H264 - Initial reference picture list for bi-direct backward picid 0 */
102151 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_MASK)
102152 
102153 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_MASK (0x7C00U)
102154 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_SHIFT (10U)
102155 /*! SW_BINIT_RLIST_F1_H264 - Initial reference picture list for bi-direct forward picid 1 */
102156 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_MASK)
102157 
102158 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_MASK (0xF8000U)
102159 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_SHIFT (15U)
102160 /*! SW_BINIT_RLIST_B1_H264 - Initial reference picture list for bi-direct backward picid 1 */
102161 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_MASK)
102162 
102163 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_MASK (0x1F00000U)
102164 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_SHIFT (20U)
102165 /*! SW_BINIT_RLIST_F2_H264 - Initial reference picture list for bi-direct forward picid 2 */
102166 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_MASK)
102167 
102168 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_MASK (0x3E000000U)
102169 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_SHIFT (25U)
102170 /*! SW_BINIT_RLIST_B2_H264 - Initial reference picture list for bi-direct backward picid 2 */
102171 #define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_MASK)
102172 /*! @} */
102173 
102174 /*! @name SWREG43_H264 - bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base */
102175 /*! @{ */
102176 
102177 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_MASK (0x1FU)
102178 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_SHIFT (0U)
102179 /*! SW_BINIT_RLIST_F3_H264 - Initial reference picture list for bi-direct forward picid 3 */
102180 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_MASK)
102181 
102182 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_MASK (0x3E0U)
102183 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_SHIFT (5U)
102184 /*! SW_BINIT_RLIST_B3_H264 - Initial reference picture list for bi-direct backward picid 3 */
102185 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_MASK)
102186 
102187 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_MASK (0x7C00U)
102188 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_SHIFT (10U)
102189 /*! SW_BINIT_RLIST_F4_H264 - Initial reference picture list for bi-direct forward picid 4 */
102190 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_MASK)
102191 
102192 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_MASK (0xF8000U)
102193 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_SHIFT (15U)
102194 /*! SW_BINIT_RLIST_B4_H264 - Initial reference picture list for bi-direct backward picid 4 */
102195 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_MASK)
102196 
102197 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_MASK (0x1F00000U)
102198 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_SHIFT (20U)
102199 /*! SW_BINIT_RLIST_F5_H264 - Initial reference picture list for bi-direct forward picid 5 */
102200 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_MASK)
102201 
102202 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_MASK (0x3E000000U)
102203 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_SHIFT (25U)
102204 /*! SW_BINIT_RLIST_B5_H264 - Initial reference picture list for bi-direct backward picid 5 */
102205 #define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_MASK)
102206 /*! @} */
102207 
102208 /*! @name SWREG44_H264 - bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps */
102209 /*! @{ */
102210 
102211 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_MASK (0x1FU)
102212 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_SHIFT (0U)
102213 /*! SW_BINIT_RLIST_F6_H264 - Initial reference picture list for bi-direct forward picid 6 */
102214 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_MASK)
102215 
102216 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_MASK (0x3E0U)
102217 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_SHIFT (5U)
102218 /*! SW_BINIT_RLIST_B6_H264 - Initial reference picture list for bi-direct backward picid 6 */
102219 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_MASK)
102220 
102221 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_MASK (0x7C00U)
102222 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_SHIFT (10U)
102223 /*! SW_BINIT_RLIST_F7_H264 - Initial reference picture list for bi-direct forward picid 7 */
102224 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_MASK)
102225 
102226 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_MASK (0xF8000U)
102227 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_SHIFT (15U)
102228 /*! SW_BINIT_RLIST_B7_H264 - Initial reference picture list for bi-direct backward picid 7 */
102229 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_MASK)
102230 
102231 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_MASK (0x1F00000U)
102232 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_SHIFT (20U)
102233 /*! SW_BINIT_RLIST_F8_H264 - Initial reference picture list for bi-direct forward picid 8 */
102234 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_MASK)
102235 
102236 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_MASK (0x3E000000U)
102237 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_SHIFT (25U)
102238 /*! SW_BINIT_RLIST_B8_H264 - Initial reference picture list for bi-direct backward picid 8 */
102239 #define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_MASK)
102240 /*! @} */
102241 
102242 /*! @name SWREG45 - bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps */
102243 /*! @{ */
102244 
102245 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_MASK (0x1FU)
102246 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_SHIFT (0U)
102247 /*! SW_BINIT_RLIST_F9 - Initial reference picture list for bi-direct forward picid 9 */
102248 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_MASK)
102249 
102250 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_MASK (0x3E0U)
102251 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_SHIFT (5U)
102252 /*! SW_BINIT_RLIST_B9 - Initial reference picture list for bi-direct backward picid 9 */
102253 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_MASK)
102254 
102255 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_MASK (0x7C00U)
102256 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_SHIFT (10U)
102257 /*! SW_BINIT_RLIST_F10 - Initial reference picture list for bi-direct forward picid 10 */
102258 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_MASK)
102259 
102260 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_MASK (0xF8000U)
102261 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_SHIFT (15U)
102262 /*! SW_BINIT_RLIST_B10 - Initial reference picture list for bi-direct backward picid 10 */
102263 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_MASK)
102264 
102265 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_MASK (0x1F00000U)
102266 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_SHIFT (20U)
102267 /*! SW_BINIT_RLIST_F11 - Initial reference picture list for bi-direct forward picid 11 */
102268 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_MASK)
102269 
102270 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_MASK (0x3E000000U)
102271 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_SHIFT (25U)
102272 /*! SW_BINIT_RLIST_B11 - Initial reference picture list for bi-direct backward picid 11 */
102273 #define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_MASK)
102274 /*! @} */
102275 
102276 /*! @name SWREG46 - bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values */
102277 /*! @{ */
102278 
102279 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_MASK (0x1FU)
102280 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_SHIFT (0U)
102281 /*! SW_BINIT_RLIST_F12 - Initial reference picture list for bi-direct forward picid 12 */
102282 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_MASK)
102283 
102284 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_MASK (0x3E0U)
102285 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_SHIFT (5U)
102286 /*! SW_BINIT_RLIST_B12 - Initial reference picture list for bi-direct backward picid 12 */
102287 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_MASK)
102288 
102289 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_MASK (0x7C00U)
102290 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_SHIFT (10U)
102291 /*! SW_BINIT_RLIST_F13 - Initial reference picture list for bi-direct forward picid 13 */
102292 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_MASK)
102293 
102294 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_MASK (0xF8000U)
102295 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_SHIFT (15U)
102296 /*! SW_BINIT_RLIST_B13 - Initial reference picture list for bi-direct backward picid 13 */
102297 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_MASK)
102298 
102299 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_MASK (0x1F00000U)
102300 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_SHIFT (20U)
102301 /*! SW_BINIT_RLIST_F14 - Initial reference picture list for bi-direct forward picid 14 */
102302 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_MASK)
102303 
102304 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_MASK (0x3E000000U)
102305 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_SHIFT (25U)
102306 /*! SW_BINIT_RLIST_B14 - Initial reference picture list for bi-direct backward picid 14 */
102307 #define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_MASK)
102308 /*! @} */
102309 
102310 /*! @name SWREG47 - bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values */
102311 /*! @{ */
102312 
102313 #define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_MASK (0x1FU)
102314 #define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_SHIFT (0U)
102315 /*! SW_BINIT_RLIST_F15 - Initial reference picture list for bi-direct forward picid 15 */
102316 #define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_SHIFT)) & VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_MASK)
102317 
102318 #define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_MASK (0x3E0U)
102319 #define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_SHIFT (5U)
102320 /*! SW_BINIT_RLIST_B15 - Initial reference picture list for bi-direct backward picid 15 */
102321 #define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_SHIFT)) & VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_MASK)
102322 
102323 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_MASK (0x7C00U)
102324 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_SHIFT (10U)
102325 /*! SW_PINIT_RLIST_F0 - Initial reference picture list for P forward picid 0 */
102326 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_MASK)
102327 
102328 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_MASK (0xF8000U)
102329 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_SHIFT (15U)
102330 /*! SW_PINIT_RLIST_F1 - Initial reference picture list for P forward picid 1 */
102331 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_MASK)
102332 
102333 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_MASK (0x1F00000U)
102334 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_SHIFT (20U)
102335 /*! SW_PINIT_RLIST_F2 - Initial reference picture list for P forward picid 2 */
102336 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_MASK)
102337 
102338 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_MASK (0x3E000000U)
102339 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_SHIFT (25U)
102340 /*! SW_PINIT_RLIST_F3 - Initial reference picture list for P forward picid 3 */
102341 #define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_MASK)
102342 /*! @} */
102343 
102344 
102345 /*!
102346  * @}
102347  */ /* end of group VPU_G1_H264_Register_Masks */
102348 
102349 
102350 /* VPU_G1_H264 - Peripheral instance base addresses */
102351 /** Peripheral VPU_G1_H264 base address */
102352 #define VPU_G1_H264_BASE                         (0x38300000u)
102353 /** Peripheral VPU_G1_H264 base pointer */
102354 #define VPU_G1_H264                              ((VPU_G1_H264_Type *)VPU_G1_H264_BASE)
102355 /** Array initializer of VPU_G1_H264 peripheral base addresses */
102356 #define VPU_G1_H264_BASE_ADDRS                   { VPU_G1_H264_BASE }
102357 /** Array initializer of VPU_G1_H264 peripheral base pointers */
102358 #define VPU_G1_H264_BASE_PTRS                    { VPU_G1_H264 }
102359 
102360 /*!
102361  * @}
102362  */ /* end of group VPU_G1_H264_Peripheral_Access_Layer */
102363 
102364 
102365 /* ----------------------------------------------------------------------------
102366    -- VPU_G1_VP7_VP8 Peripheral Access Layer
102367    ---------------------------------------------------------------------------- */
102368 
102369 /*!
102370  * @addtogroup VPU_G1_VP7_VP8_Peripheral_Access_Layer VPU_G1_VP7_VP8 Peripheral Access Layer
102371  * @{
102372  */
102373 
102374 /** VPU_G1_VP7_VP8 - Register Layout Typedef */
102375 typedef struct {
102376        uint8_t RESERVED_0[16];
102377   __IO uint32_t SWREG4_JPEG_VP7_VP8;               /**< Decoder control register 1 (picture parameters), offset: 0x10 */
102378   __IO uint32_t SWREG5_VP7_VP8;                    /**< Decoder control register 2 (stream decoding table selects), offset: 0x14 */
102379   __IO uint32_t SWREG6_VP7_VP8;                    /**< Decoder control register 3 (stream buffer information), offset: 0x18 */
102380   __IO uint32_t SWREG7_VP7_VP8;                    /**< Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control), offset: 0x1C */
102381        uint8_t RESERVED_1[8];
102382   __IO uint32_t SWREG10_VP7_VP8;                   /**< Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register, offset: 0x28 */
102383   __IO uint32_t SWREG11_VP7_VP8;                   /**< Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2, offset: 0x2C */
102384        uint8_t RESERVED_2[8];
102385   __IO uint32_t SWREG14_VP7_VP8;                   /**< Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture, offset: 0x38 */
102386   __IO uint32_t SWREG15_VP7_VP8;                   /**< Base address for reference picture index 1 / JPEG control, offset: 0x3C */
102387        uint8_t RESERVED_3[8];
102388   __IO uint32_t SWREG18_VP7_VP8;                   /**< Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base, offset: 0x48 */
102389        uint8_t RESERVED_4[12];
102390   __IO uint32_t SWREG22_VP7_VP8;                   /**< Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base, offset: 0x58 */
102391   __IO uint32_t SWREG23_VP7_VP8;                   /**< Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base, offset: 0x5C */
102392   __IO uint32_t SWREG24_VP7_VP8;                   /**< Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base, offset: 0x60 */
102393   __IO uint32_t SWREG25_VP7_VP8;                   /**< Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base, offset: 0x64 */
102394   __IO uint32_t SWREG26_VP7_VP8;                   /**< Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base, offset: 0x68 */
102395   __IO uint32_t SWREG27_VC1;                       /**< Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table, offset: 0x6C */
102396   __IO uint32_t SWREG28_VP7_VP8;                   /**< Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base, offset: 0x70 */
102397   __IO uint32_t SWREG29_VP7_VP8;                   /**< Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base, offset: 0x74 */
102398   __IO uint32_t SWREG30_VP7_VP8;                   /**< Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts, offset: 0x78 */
102399   __IO uint32_t SWREG31_VP7_VP8;                   /**< Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts, offset: 0x7C */
102400   __IO uint32_t SWREG32_VP7_VP8;                   /**< Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels, offset: 0x80 */
102401   __IO uint32_t SWREG33_VP7_VP8;                   /**< Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values, offset: 0x84 */
102402   __IO uint32_t SWREG34_H263;                      /**< Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps, offset: 0x88 */
102403   __IO uint32_t SWREG35_VC1;                       /**< Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x8C */
102404   __IO uint32_t SWREG36_VC1;                       /**< Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x90 */
102405   __IO uint32_t SWREG37_VP6_VP7_VP8;               /**< Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps, offset: 0x94 */
102406   __IO uint32_t SWREG38_VP6_VP7_VP8;               /**< Reference picture long term flags (H264 VLC) / VPx prediction filter taps, offset: 0x98 */
102407   __IO uint32_t SWREG39_VP6_VP7_VP8;               /**< Reference picture valid flags (H264 VLC) / VPx prediction filter taps, offset: 0x9C */
102408        uint8_t RESERVED_5[8];
102409   __IO uint32_t SWREG42_VP6;                       /**< bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base, offset: 0xA8 */
102410   __IO uint32_t SWREG43_VP7_VP8;                   /**< bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base, offset: 0xAC */
102411   __IO uint32_t SWREG44_VP7_VP8;                   /**< bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps, offset: 0xB0 */
102412   __IO uint32_t SWREG45_VP7_VP8;                   /**< bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps, offset: 0xB4 */
102413   __IO uint32_t SWREG46_VP7_VP8;                   /**< bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values, offset: 0xB8 */
102414   __IO uint32_t SWREG47_VP7_VP8;                   /**< bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values, offset: 0xBC */
102415 } VPU_G1_VP7_VP8_Type;
102416 
102417 /* ----------------------------------------------------------------------------
102418    -- VPU_G1_VP7_VP8 Register Masks
102419    ---------------------------------------------------------------------------- */
102420 
102421 /*!
102422  * @addtogroup VPU_G1_VP7_VP8_Register_Masks VPU_G1_VP7_VP8 Register Masks
102423  * @{
102424  */
102425 
102426 /*! @name SWREG4_JPEG_VP7_VP8 - Decoder control register 1 (picture parameters) */
102427 /*! @{ */
102428 
102429 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_MASK (0x7U)
102430 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_SHIFT (0U)
102431 /*! SW_PIC_MB_H_EXT_JPEG_VP7_VP6 - Picture mb height extension. If sw_pic_mb_height_p does not fit
102432  *    to 9 bits then these bits are used to increase the range upto 11 bits (used as 3 msb). For 4k
102433  *    video one bit is used for extension (bit 0)
102434  */
102435 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_MASK)
102436 
102437 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_MASK (0x38U)
102438 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_SHIFT (3U)
102439 /*! SW_PIC_MB_W_EXT_JPEG_VP7_VP6 - Picture mb width extension. If sw_pic_mb_width does not fit to 9
102440  *    bits then these bits are used to increase the range upto 11 bits (used as 3 msb)
102441  */
102442 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_MASK)
102443 
102444 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_MASK (0x40U)
102445 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_SHIFT (6U)
102446 /*! SW_ALT_SCAN_E_JPEG_VP7_VP6 - indicates alternative vertical scan method used for interlaced frames */
102447 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_MASK)
102448 
102449 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_MASK (0x780U)
102450 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_SHIFT (7U)
102451 /*! SW_MB_HEIGHT_OFF_JPEG_VP7_VP6 - The amount of meaningful vertical pixels in last MB (height
102452  *    offset 0 if exactly 16 pixels multiple picture and all the vertical pixels in last MB are
102453  *    meaningfull
102454  */
102455 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_MASK)
102456 
102457 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_MASK (0x7F800U)
102458 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_SHIFT (11U)
102459 /*! SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6 - Picture height in macroblocks =((height in pixels+15)/16).
102460  *    Picture height is informed as size of the (progressive) frame also for single field (of
102461  *    interlaced content) is being decoded
102462  */
102463 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_MASK)
102464 
102465 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_MASK (0x780000U)
102466 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_SHIFT (19U)
102467 /*! SW_MB_WIDTH_OFF_JPEG_VP7_VP6 - The amount of meaningfull horizontal pixels in last MB (width
102468  *    offset) 0 if exactly 16 pixels multiple picture and all the horizontal pixels in last MB are
102469  *    meaningfull
102470  */
102471 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_MASK)
102472 
102473 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_MASK (0xFF800000U)
102474 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_SHIFT (23U)
102475 /*! SW_PIC_MB_WIDTH_JPEG_VP7_VP6 - Picture width in macroblocks = ((width in pixels + 15) /16) */
102476 #define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_MASK)
102477 /*! @} */
102478 
102479 /*! @name SWREG5_VP7_VP8 - Decoder control register 2 (stream decoding table selects) */
102480 /*! @{ */
102481 
102482 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_MASK (0xFFU)
102483 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_SHIFT (0U)
102484 /*! SW_BOOLEAN_RANGE_VP7_VP8 - Initial range for boolean dec */
102485 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_MASK)
102486 
102487 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_MASK (0xFF00U)
102488 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_SHIFT (8U)
102489 /*! SW_BOOLEAN_VALUE_VP7_VP8 - Initial value for boolean dec */
102490 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_MASK)
102491 
102492 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_MASK (0xFC0000U)
102493 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_SHIFT (18U)
102494 /*! SW_STRM1_START_BIT_VP7_VP8 - Start bit for ctrl-stream (needed if multistream is enabled, assosiates with sw_bitpl_ctrl_base) */
102495 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_MASK)
102496 
102497 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_MASK (0xFC000000U)
102498 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_SHIFT (26U)
102499 /*! SW_STRM_START_BIT_VP7_VP8 - Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base) */
102500 #define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_MASK)
102501 /*! @} */
102502 
102503 /*! @name SWREG6_VP7_VP8 - Decoder control register 3 (stream buffer information) */
102504 /*! @{ */
102505 
102506 #define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_MASK (0xFFFFFFU)
102507 #define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_SHIFT (0U)
102508 /*! SW_STREAM_LEN_VP7_VP8 - Amount of stream data bytes in input buffer. If the given buffer size is
102509  *    not enough for finishing the picture the corresponding interrupt is given and new stream
102510  *    buffer base address and stream buffer size information should be given (assosiates with
102511  *    sw_rlc_vlc_base). For VC-1/VP6 the buffer must include data for one picture/slice of the picture For
102512  *    H264/MPEG4/H263/MPEG2/MPEG1 the buffer must include at least data for one slice/VP of the picture
102513  *    For JPEG the buffer size must be a multiple of 256 bytes or the amount of data for one
102514  *    picture.
102515  */
102516 #define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_MASK)
102517 
102518 #define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_MASK (0xFF000000U)
102519 #define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_SHIFT (24U)
102520 /*! SW_STREAM_LEN_EXT_VP7_VP8 - Extended stream length for WEBP/VP8 */
102521 #define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_MASK)
102522 /*! @} */
102523 
102524 /*! @name SWREG7_VP7_VP8 - Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control) */
102525 /*! @{ */
102526 
102527 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_MASK (0x20U)
102528 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_SHIFT (5U)
102529 /*! SW_VP7_VERSION_VP7_VP8 - VP7 version information to streamd:
102530  *  0b0..VP7 version 7.0
102531  *  0b1..VP7 version 7.1 or better
102532  */
102533 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_MASK)
102534 
102535 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_MASK (0x1C0U)
102536 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_SHIFT (6U)
102537 /*! SW_INIT_DC_MATCH1_VP7_VP8 - Initial DC prediction mach count 1. After HW has decoded a picture
102538  *    HW returns the final match count1 information which is read by SW
102539  */
102540 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_MASK)
102541 
102542 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_MASK (0xE00U)
102543 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_SHIFT (9U)
102544 /*! SW_INIT_DC_MATCH0_VP7_VP8 - Initial DC prediction mach count 0. After HW has decoded a picture
102545  *    HW returns the final match count0 information which is read by SW
102546  */
102547 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_MASK)
102548 
102549 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_MASK (0x1000U)
102550 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_SHIFT (12U)
102551 /*! SW_BILIN_MC_E_VP7_VP8 - Bilinear motion compensation enable:
102552  *  0b0..Bicubic interpolation used
102553  *  0b1..Bilinear interpolation used
102554  */
102555 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_MASK)
102556 
102557 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_MASK (0x2000U)
102558 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_SHIFT (13U)
102559 /*! SW_CH_MV_RES_VP7_VP8 - VP7/VP8 Chrominance motion vector resolution:
102560  *  0b0..Full pixel
102561  *  0b1..1/8 pixel
102562  */
102563 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_MASK)
102564 
102565 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_MASK (0x3F00000U)
102566 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_SHIFT (20U)
102567 /*! SW_DCT2_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 2 */
102568 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_MASK)
102569 
102570 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_MASK (0xFC000000U)
102571 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_SHIFT (26U)
102572 /*! SW_DCT1_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 1 */
102573 #define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_MASK)
102574 /*! @} */
102575 
102576 /*! @name SWREG10_VP7_VP8 - Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register */
102577 /*! @{ */
102578 
102579 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_MASK (0x1U)
102580 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_SHIFT (0U)
102581 /*! SW_SEGMENT_E_VP7_VP8 - Segmentation enable: '0': segmentation is not enabled '1': segmentation is enabled (sw_segment_upd_e value is used) */
102582 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_MASK)
102583 
102584 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_MASK (0x2U)
102585 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_SHIFT (1U)
102586 /*! SW_SEGMENT_UPD_E_VP7_VP8 - VP7/VP8 Segmentation map update enable: '0': segmentation values are
102587  *    read from external memory (from segment_base) '1': segmentation update is included in stream
102588  */
102589 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_MASK)
102590 
102591 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_MASK (0xFFFFFFFCU)
102592 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_SHIFT (2U)
102593 /*! SW_SEGMENT_BASE_VP7_VP8 - VP7/VP8: base address for segmentation map values */
102594 #define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_MASK)
102595 /*! @} */
102596 
102597 /*! @name SWREG11_VP7_VP8 - Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2 */
102598 /*! @{ */
102599 
102600 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_MASK (0x3FU)
102601 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_SHIFT (0U)
102602 /*! SW_DCT7_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 7 */
102603 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_MASK)
102604 
102605 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_MASK (0xFC0U)
102606 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_SHIFT (6U)
102607 /*! SW_DCT6_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 6 */
102608 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_MASK)
102609 
102610 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_MASK (0x3F000U)
102611 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_SHIFT (12U)
102612 /*! SW_DCT5_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 5 */
102613 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_MASK)
102614 
102615 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_MASK (0xFC0000U)
102616 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_SHIFT (18U)
102617 /*! SW_DCT4_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 4 */
102618 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_MASK)
102619 
102620 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_MASK (0x3F000000U)
102621 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_SHIFT (24U)
102622 /*! SW_DCT3_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 3 */
102623 #define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_MASK)
102624 /*! @} */
102625 
102626 /*! @name SWREG14_VP7_VP8 - Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture */
102627 /*! @{ */
102628 
102629 #define VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_MASK (0xFFFFFFFCU)
102630 #define VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_SHIFT (2U)
102631 /*! SW_JPG_CH_OUT_BASE_VP7_VP8 - Base address for decoder output chrominance picture. Used in JPEG
102632  *    and web-p picture mode (not needed if decoder output is not written)
102633  */
102634 #define VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_MASK)
102635 /*! @} */
102636 
102637 /*! @name SWREG15_VP7_VP8 - Base address for reference picture index 1 / JPEG control */
102638 /*! @{ */
102639 
102640 #define VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_MASK (0xFFU)
102641 #define VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_SHIFT (0U)
102642 /*! SW_JPEG_SLICE_H_VP7_VP8 - JPEG/Web-p. Height of the slice (multiple of 16 pixels) that HW
102643  *    decodes before interrupt. When slice is decoded HW will rise an interrupt and reset external
102644  *    addresses back to base address. Note, value 0 disables slice mode. Slice mode must be used if picture
102645  *    size is more than 16 Mpixels. However for bigger than 4096 MBs the slice mode usage is
102646  *    recommended.
102647  */
102648 #define VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_MASK)
102649 /*! @} */
102650 
102651 /*! @name SWREG18_VP7_VP8 - Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base */
102652 /*! @{ */
102653 
102654 #define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_MASK (0x1U)
102655 #define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_SHIFT (0U)
102656 /*! SW_GREF_SIGN_BIAS_VP7_VP8 - Reference picture sign bias for Golden reference frame */
102657 #define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_MASK)
102658 
102659 #define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_MASK (0xFFFFFFFCU)
102660 #define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_SHIFT (2U)
102661 /*! SW_REFER4_BASE_VP7_VP8 - H264: Base address for reference picture index 4 VP6/VP7/VP8: Base
102662  *    address for Golden reference picture (corresponds picid 4)
102663  */
102664 #define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_MASK)
102665 /*! @} */
102666 
102667 /*! @name SWREG22_VP7_VP8 - Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base */
102668 /*! @{ */
102669 
102670 #define VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_MASK (0xFFFFFFFCU)
102671 #define VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_SHIFT (2U)
102672 /*! SW_DCT_STRM1_BASE - Base address for VP7/VP8 DCT stream MB row 1,2n+1 */
102673 #define VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_MASK)
102674 /*! @} */
102675 
102676 /*! @name SWREG23_VP7_VP8 - Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base */
102677 /*! @{ */
102678 
102679 #define VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_MASK (0xFFFFFFFCU)
102680 #define VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_SHIFT (2U)
102681 /*! SW_DCT_STRM2_BASE - Base address for VP7/VP8 DCT stream MB row 2,2n+2 */
102682 #define VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_MASK)
102683 /*! @} */
102684 
102685 /*! @name SWREG24_VP7_VP8 - Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base */
102686 /*! @{ */
102687 
102688 #define VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_MASK (0xFFFFFFFCU)
102689 #define VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_SHIFT (2U)
102690 /*! SW_DCT_STRM3_BASE - Base address for VP7/VP8 DCT stream MB row 3,2n+3 */
102691 #define VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_MASK)
102692 /*! @} */
102693 
102694 /*! @name SWREG25_VP7_VP8 - Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base */
102695 /*! @{ */
102696 
102697 #define VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_MASK (0xFFFFFFFCU)
102698 #define VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_SHIFT (2U)
102699 /*! SW_DCT_STRM4_BASE - Base address for VP7/VP8 DCT stream MB row 4,2n+4 */
102700 #define VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_MASK)
102701 /*! @} */
102702 
102703 /*! @name SWREG26_VP7_VP8 - Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base */
102704 /*! @{ */
102705 
102706 #define VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_MASK (0xFFFFFFFCU)
102707 #define VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_SHIFT (2U)
102708 /*! SW_DCT_STRM5_BASE - Base address for VP7/VP8 DCT stream MB row 5,2n+5 */
102709 #define VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_MASK)
102710 /*! @} */
102711 
102712 /*! @name SWREG27_VC1 - Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table */
102713 /*! @{ */
102714 
102715 #define VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_MASK (0xFFFFFFFCU)
102716 #define VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_SHIFT (2U)
102717 /*! SW_BITPL_CTRL_BASE - VC-1: Base address for bitplane mb control VP6/VP7/VP8 : Base address for
102718  *    ctrl data stream. Used if multistream is enabled
102719  */
102720 #define VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_MASK)
102721 /*! @} */
102722 
102723 /*! @name SWREG28_VP7_VP8 - Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base */
102724 /*! @{ */
102725 
102726 #define VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_MASK (0xFFFFFFFCU)
102727 #define VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_SHIFT (2U)
102728 /*! SW_DCT_STRM6_BASE - Base address for VP7/VP8 DCT stream MB row 6,2n+6 */
102729 #define VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_MASK)
102730 /*! @} */
102731 
102732 /*! @name SWREG29_VP7_VP8 - Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base */
102733 /*! @{ */
102734 
102735 #define VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_MASK (0xFFFFFFFCU)
102736 #define VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_SHIFT (2U)
102737 /*! SW_DCT_STRM7_BASE - Base address for VP7/VP8 DCT stream MB row 7,2n+7 */
102738 #define VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_MASK)
102739 /*! @} */
102740 
102741 /*! @name SWREG30_VP7_VP8 - Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts */
102742 /*! @{ */
102743 
102744 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_MASK (0x7FU)
102745 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_SHIFT (0U)
102746 /*! SW_FILT_MB_ADJ_3 - VP7/VP8 filter level adjustment for MB type 3 */
102747 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_MASK)
102748 
102749 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_MASK (0x3F80U)
102750 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_SHIFT (7U)
102751 /*! SW_FILT_MB_ADJ_2 - VP7/VP8 filter level adjustment for MB type 2 */
102752 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_MASK)
102753 
102754 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_MASK (0x1FC000U)
102755 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_SHIFT (14U)
102756 /*! SW_FILT_MB_ADJ_1 - VP7/VP8 filter level adjustment for MB type 1 */
102757 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_MASK)
102758 
102759 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_MASK (0xFE00000U)
102760 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_SHIFT (21U)
102761 /*! SW_FILT_MB_ADJ_0 - VP7/VP8 filter level adjustment for MB type 0 */
102762 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_MASK)
102763 
102764 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_MASK (0x70000000U)
102765 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_SHIFT (28U)
102766 /*! SW_FILT_SHARPNESS - VP7/VP8 loop filter sharpness */
102767 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_MASK)
102768 
102769 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_MASK (0x80000000U)
102770 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_SHIFT (31U)
102771 /*! SW_FILT_TYPE - VP7/VP8 loop filter type */
102772 #define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_MASK)
102773 /*! @} */
102774 
102775 /*! @name SWREG31_VP7_VP8 - Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts */
102776 /*! @{ */
102777 
102778 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_MASK (0x7FU)
102779 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_SHIFT (0U)
102780 /*! SW_FILT_REF_ADJ_3 - VP7/VP8 filter level adjustment for reference frame type 3 */
102781 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_MASK)
102782 
102783 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_MASK (0x3F80U)
102784 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_SHIFT (7U)
102785 /*! SW_FILT_REF_ADJ_2 - VP7/VP8 filter level adjustment for reference frame type 2 */
102786 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_MASK)
102787 
102788 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_MASK (0x1FC000U)
102789 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_SHIFT (14U)
102790 /*! SW_FILT_REF_ADJ_1 - VP7/VP8 filter level adjustment for reference frame type 1 */
102791 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_MASK)
102792 
102793 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_MASK (0xFE00000U)
102794 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_SHIFT (21U)
102795 /*! SW_FILT_REF_ADJ_0 - VP7/VP8 filter level adjustment for reference frame type 0 */
102796 #define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_MASK)
102797 /*! @} */
102798 
102799 /*! @name SWREG32_VP7_VP8 - Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels */
102800 /*! @{ */
102801 
102802 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_MASK (0x3FU)
102803 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_SHIFT (0U)
102804 /*! SW_FILT_LEVEL_3 - VP7/VP8 filter level value for reference frame type 3 */
102805 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_MASK)
102806 
102807 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_MASK (0xFC0U)
102808 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_SHIFT (6U)
102809 /*! SW_FILT_LEVEL_2 - VP7/VP8 filter level value for reference frame type 2 */
102810 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_MASK)
102811 
102812 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_MASK (0x3F000U)
102813 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_SHIFT (12U)
102814 /*! SW_FILT_LEVEL_1 - VP7/VP8 filter level value for reference frame type 1 */
102815 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_MASK)
102816 
102817 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_MASK (0xFC0000U)
102818 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_SHIFT (18U)
102819 /*! SW_FILT_LEVEL_0 - VP7/VP8 filter level value for reference frame type 0 */
102820 #define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_MASK)
102821 /*! @} */
102822 
102823 /*! @name SWREG33_VP7_VP8 - Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values */
102824 /*! @{ */
102825 
102826 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_MASK (0x7FFU)
102827 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_SHIFT (0U)
102828 /*! SW_QUANT_1 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit) */
102829 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_MASK)
102830 
102831 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_MASK (0x3FF800U)
102832 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_SHIFT (11U)
102833 /*! SW_QUANT_0 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit) */
102834 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_MASK)
102835 
102836 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_MASK (0x7C00000U)
102837 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_SHIFT (22U)
102838 /*! SW_QUANT_DELTA_1 - VP8 quantisizer delta 1 */
102839 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_MASK)
102840 
102841 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_MASK (0xF8000000U)
102842 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_SHIFT (27U)
102843 /*! SW_QUANT_DELTA_0 - VP8 quantisizer delta 0 */
102844 #define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_MASK)
102845 /*! @} */
102846 
102847 /*! @name SWREG34_H263 - Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps */
102848 /*! @{ */
102849 
102850 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_MASK (0xFFCU)
102851 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_SHIFT (2U)
102852 /*! SW_PRED_BC_TAP_1_1 - Prediction filter set 1, tap 1 */
102853 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_MASK)
102854 
102855 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_MASK (0x3FF000U)
102856 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_SHIFT (12U)
102857 /*! SW_PRED_BC_TAP_1_0 - Prediction filter set 1, tap 0 */
102858 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_MASK)
102859 
102860 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_MASK (0xFFC00000U)
102861 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_SHIFT (22U)
102862 /*! SW_PRED_BC_TAP_0_3 - Prediction filter set 0, tap 3 */
102863 #define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_MASK)
102864 /*! @} */
102865 
102866 /*! @name SWREG35_VC1 - Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps */
102867 /*! @{ */
102868 
102869 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_MASK (0xFFCU)
102870 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_SHIFT (2U)
102871 /*! SW_PRED_BC_TAP_2_0 - Prediction filter set 2, tap 0 */
102872 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_MASK)
102873 
102874 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_MASK (0x3FF000U)
102875 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_SHIFT (12U)
102876 /*! SW_PRED_BC_TAP_1_3 - Prediction filter set 1, tap 3 */
102877 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_MASK)
102878 
102879 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_MASK (0xFFC00000U)
102880 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_SHIFT (22U)
102881 /*! SW_PRED_BC_TAP_1_2 - Prediction filter set 1, tap 2 */
102882 #define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_MASK)
102883 /*! @} */
102884 
102885 /*! @name SWREG36_VC1 - Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps */
102886 /*! @{ */
102887 
102888 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_MASK (0xFFCU)
102889 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_SHIFT (2U)
102890 /*! SW_PRED_BC_TAP_2_3 - Prediction filter set 2, tap 3 */
102891 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_MASK)
102892 
102893 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_MASK (0x3FF000U)
102894 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_SHIFT (12U)
102895 /*! SW_PRED_BC_TAP_2_2 - Prediction filter set 2, tap 2 */
102896 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_MASK)
102897 
102898 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_MASK (0xFFC00000U)
102899 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_SHIFT (22U)
102900 /*! SW_PRED_BC_TAP_2_1 - Prediction filter set 2, tap 1 */
102901 #define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_MASK)
102902 /*! @} */
102903 
102904 /*! @name SWREG37_VP6_VP7_VP8 - Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps */
102905 /*! @{ */
102906 
102907 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_MASK (0xFFCU)
102908 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_SHIFT (2U)
102909 /*! SW_PRED_BC_TAP_3_2 - Prediction filter set 3, tap 2 */
102910 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_MASK)
102911 
102912 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_MASK (0x3FF000U)
102913 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_SHIFT (12U)
102914 /*! SW_PRED_BC_TAP_3_1 - Prediction filter set 3, tap 1 */
102915 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_MASK)
102916 
102917 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_MASK (0xFFC00000U)
102918 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_SHIFT (22U)
102919 /*! SW_PRED_BC_TAP_3_0 - Prediction filter set 3, tap 0 */
102920 #define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_MASK)
102921 /*! @} */
102922 
102923 /*! @name SWREG38_VP6_VP7_VP8 - Reference picture long term flags (H264 VLC) / VPx prediction filter taps */
102924 /*! @{ */
102925 
102926 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_MASK (0xFFCU)
102927 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_SHIFT (2U)
102928 /*! SW_PRED_BC_TAP_4_1 - Prediction filter set 4, tap 1 */
102929 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_MASK)
102930 
102931 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_MASK (0x3FF000U)
102932 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_SHIFT (12U)
102933 /*! SW_PRED_BC_TAP_4_0 - Prediction filter set 4, tap 0 */
102934 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_MASK)
102935 
102936 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_MASK (0xFFC00000U)
102937 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_SHIFT (22U)
102938 /*! SW_PRED_BC_TAP_3_3 - Prediction filter set 3, tap 3 */
102939 #define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_MASK)
102940 /*! @} */
102941 
102942 /*! @name SWREG39_VP6_VP7_VP8 - Reference picture valid flags (H264 VLC) / VPx prediction filter taps */
102943 /*! @{ */
102944 
102945 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_MASK (0xFFCU)
102946 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_SHIFT (2U)
102947 /*! SW_PRED_BC_TAP_5_0 - Prediction filter set 5, tap 0 */
102948 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_MASK)
102949 
102950 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_MASK (0x3FF000U)
102951 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_SHIFT (12U)
102952 /*! SW_PRED_BC_TAP_4_3 - Prediction filter set 4, tap 3 */
102953 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_MASK)
102954 
102955 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_MASK (0xFFC00000U)
102956 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_SHIFT (22U)
102957 /*! SW_PRED_BC_TAP_4_2 - Prediction filter set 4, tap 2 */
102958 #define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_MASK)
102959 /*! @} */
102960 
102961 /*! @name SWREG42_VP6 - bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base */
102962 /*! @{ */
102963 
102964 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_MASK (0xFFCU)
102965 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_SHIFT (2U)
102966 /*! SW_PRED_BC_TAP_5_3_VP6 - Prediction filter set 5, tap 3 */
102967 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_MASK)
102968 
102969 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_MASK (0x3FF000U)
102970 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_SHIFT (12U)
102971 /*! SW_PRED_BC_TAP_5_2_VP6 - Prediction filter set 5, tap 2 */
102972 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_MASK)
102973 
102974 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_MASK (0xFFC00000U)
102975 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_SHIFT (22U)
102976 /*! SW_PRED_BC_TAP_5_1_VP6 - Prediction filter set 5, tap 1 */
102977 #define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_MASK)
102978 /*! @} */
102979 
102980 /*! @name SWREG43_VP7_VP8 - bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base */
102981 /*! @{ */
102982 
102983 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_MASK (0xFFCU)
102984 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_SHIFT (2U)
102985 /*! SW_PRED_BC_TAP_6_2_VP7_VP8 - Prediction filter set 6, tap 2 */
102986 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_MASK)
102987 
102988 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_MASK (0x3FF000U)
102989 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_SHIFT (12U)
102990 /*! SW_PRED_BC_TAP_6_1_VP7_VP8 - Prediction filter set 6, tap 1 */
102991 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_MASK)
102992 
102993 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_MASK (0xFFC00000U)
102994 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_SHIFT (22U)
102995 /*! SW_PRED_BC_TAP_6_0_VP7_VP8 - Prediction filter set 6, tap 0 */
102996 #define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_MASK)
102997 /*! @} */
102998 
102999 /*! @name SWREG44_VP7_VP8 - bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps */
103000 /*! @{ */
103001 
103002 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_MASK (0xFFCU)
103003 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_SHIFT (2U)
103004 /*! SW_PRED_BC_TAP_7_1_VP7_VP8 - Prediction filter set 7, tap 1 */
103005 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_MASK)
103006 
103007 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_MASK (0x3FF000U)
103008 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_SHIFT (12U)
103009 /*! SW_PRED_BC_TAP_7_0_VP7_VP8 - Prediction filter set 7, tap 0 */
103010 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_MASK)
103011 
103012 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_MASK (0xFFC00000U)
103013 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_SHIFT (22U)
103014 /*! SW_PRED_BC_TAP_6_3_VP7_VP8 - Prediction filter set 6, tap 3 */
103015 #define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_MASK)
103016 /*! @} */
103017 
103018 /*! @name SWREG45_VP7_VP8 - bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps */
103019 /*! @{ */
103020 
103021 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_MASK (0x3U)
103022 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_SHIFT (0U)
103023 /*! SW_PRED_TAP_6_4_VP7_VP8 - Additional Prediction filter tap 4 for set 6 */
103024 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_MASK)
103025 
103026 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_MASK (0xCU)
103027 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_SHIFT (2U)
103028 /*! SW_PRED_TAP_6_M1_VP7_VP8 - Additional Prediction filter tap -1 for set 6 */
103029 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_MASK)
103030 
103031 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_MASK (0x30U)
103032 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_SHIFT (4U)
103033 /*! SW_PRED_TAP_4_4_VP7_VP8 - Additional Prediction filter tap 4 for set 4 */
103034 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_MASK)
103035 
103036 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_MASK (0xC0U)
103037 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_SHIFT (6U)
103038 /*! SW_PRED_TAP_4_M1_VP7_VP8 - Additional Prediction filter tap -1 for set 4 */
103039 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_MASK)
103040 
103041 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_MASK (0x300U)
103042 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_SHIFT (8U)
103043 /*! SW_PRED_TAP_2_4_VP7_VP8 - Additional Prediction filter tap 4 for set 2 */
103044 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_MASK)
103045 
103046 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_MASK (0xC00U)
103047 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_SHIFT (10U)
103048 /*! SW_PRED_TAP_2_M1_VP7_VP8 - Additional Prediction filter tap -1 for set 2 */
103049 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_MASK)
103050 
103051 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_MASK (0x3FF000U)
103052 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_SHIFT (12U)
103053 /*! SW_PRED_BC_TAP_7_3_VP7_VP8 - Prediction filter set 7, tap 3 */
103054 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_MASK)
103055 
103056 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_MASK (0xFFC00000U)
103057 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_SHIFT (22U)
103058 /*! SW_PRED_BC_TAP_7_2_VP7_VP8 - Prediction filter set 7, tap 2 */
103059 #define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_MASK)
103060 /*! @} */
103061 
103062 /*! @name SWREG46_VP7_VP8 - bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values */
103063 /*! @{ */
103064 
103065 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_MASK (0x7FFU)
103066 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_SHIFT (0U)
103067 /*! SW_QUANT_3_VP7_VP8 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit) */
103068 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_MASK)
103069 
103070 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_MASK (0x3FF800U)
103071 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_SHIFT (11U)
103072 /*! SW_QUANT_2_VP7_VP8 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit) */
103073 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_MASK)
103074 
103075 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_MASK (0x7C00000U)
103076 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_SHIFT (22U)
103077 /*! SW_QUANT_DELTA_3_VP7_VP8 - VP8 quantisizer delta 3 */
103078 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_MASK)
103079 
103080 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_MASK (0xF8000000U)
103081 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_SHIFT (27U)
103082 /*! SW_QUANT_DELTA_2_VP7_VP8 - VP8 quantisizer delta 2 */
103083 #define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_MASK)
103084 /*! @} */
103085 
103086 /*! @name SWREG47_VP7_VP8 - bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values */
103087 /*! @{ */
103088 
103089 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_MASK (0x7FFU)
103090 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_SHIFT (0U)
103091 /*! SW_QUANT_5_VP7_VP8 - VP7 QP (11 bit) */
103092 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_MASK)
103093 
103094 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_MASK (0x3FF800U)
103095 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_SHIFT (11U)
103096 /*! SW_QUANT_4_VP7_VP8 - VP7 QP (11 bit) */
103097 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_MASK)
103098 
103099 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_MASK (0xF8000000U)
103100 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_SHIFT (27U)
103101 /*! SW_QUANT_DELTA_4_VP7_VP8 - VP8 quantisizer delta 4 */
103102 #define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_MASK)
103103 /*! @} */
103104 
103105 
103106 /*!
103107  * @}
103108  */ /* end of group VPU_G1_VP7_VP8_Register_Masks */
103109 
103110 
103111 /* VPU_G1_VP7_VP8 - Peripheral instance base addresses */
103112 /** Peripheral VPU_G1_VP7_VP8 base address */
103113 #define VPU_G1_VP7_VP8_BASE                      (0x38300000u)
103114 /** Peripheral VPU_G1_VP7_VP8 base pointer */
103115 #define VPU_G1_VP7_VP8                           ((VPU_G1_VP7_VP8_Type *)VPU_G1_VP7_VP8_BASE)
103116 /** Array initializer of VPU_G1_VP7_VP8 peripheral base addresses */
103117 #define VPU_G1_VP7_VP8_BASE_ADDRS                { VPU_G1_VP7_VP8_BASE }
103118 /** Array initializer of VPU_G1_VP7_VP8 peripheral base pointers */
103119 #define VPU_G1_VP7_VP8_BASE_PTRS                 { VPU_G1_VP7_VP8 }
103120 
103121 /*!
103122  * @}
103123  */ /* end of group VPU_G1_VP7_VP8_Peripheral_Access_Layer */
103124 
103125 
103126 /* ----------------------------------------------------------------------------
103127    -- VPU_G1_VP8 Peripheral Access Layer
103128    ---------------------------------------------------------------------------- */
103129 
103130 /*!
103131  * @addtogroup VPU_G1_VP8_Peripheral_Access_Layer VPU_G1_VP8 Peripheral Access Layer
103132  * @{
103133  */
103134 
103135 /** VPU_G1_VP8 - Register Layout Typedef */
103136 typedef struct {
103137        uint8_t RESERVED_0[76];
103138   __IO uint32_t SWREG19_VP8;                       /**< Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps, offset: 0x4C */
103139   __IO uint32_t SWREG20_VP8;                       /**< Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x50 */
103140   __IO uint32_t SWREG21_VP8;                       /**< Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x54 */
103141 } VPU_G1_VP8_Type;
103142 
103143 /* ----------------------------------------------------------------------------
103144    -- VPU_G1_VP8 Register Masks
103145    ---------------------------------------------------------------------------- */
103146 
103147 /*!
103148  * @addtogroup VPU_G1_VP8_Register_Masks VPU_G1_VP8 Register Masks
103149  * @{
103150  */
103151 
103152 /*! @name SWREG19_VP8 - Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps */
103153 /*! @{ */
103154 
103155 #define VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_MASK (0x1U)
103156 #define VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_SHIFT (0U)
103157 /*! SW_AREF_SIGN_BIAS - VP8 only: Reference picture sign bias for Alternate reference frame */
103158 #define VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_SHIFT)) & VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_MASK)
103159 
103160 #define VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_MASK (0xFFFFFFFCU)
103161 #define VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_SHIFT (2U)
103162 /*! SW_REFER5_BASE_VP8 - H.264: Base address for reference picture index 5 VP8: Base address for
103163  *    alternate reference picture (corresponds picid 5)
103164  */
103165 #define VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_SHIFT)) & VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_MASK)
103166 /*! @} */
103167 
103168 /*! @name SWREG20_VP8 - Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
103169 /*! @{ */
103170 
103171 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_MASK (0x1U)
103172 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_SHIFT (0U)
103173 /*! SW_VP8_CH_BASE_E - VP8 separate chrominance enable:
103174  *  0b0..Write/Read chrominance data from internal offset after the luminance data
103175  *  0b1..Write/Read chrominance data from separate base addresses given by SW
103176  */
103177 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_SHIFT)) & VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_MASK)
103178 
103179 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_MASK (0x2U)
103180 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_SHIFT (1U)
103181 /*! SW_VP8_STRIDE_E - VP8 stride enable. Can be set high only if HW configuration supports strides.
103182  *    Y and C strides are used instead of picture width. Separate chrominance base addresses are
103183  *    used instead of internal chrominance offsets.
103184  *  0b0..Not enabled
103185  *  0b1..Enabled
103186  */
103187 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_SHIFT)) & VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_MASK)
103188 
103189 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_MASK (0xFFFFFFFCU)
103190 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_SHIFT (2U)
103191 /*! SW_VP8_DEC_CH_BASE - VP8 video base address for decoder output chrominance data (if vp8 stride configuration is enabled) */
103192 #define VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_SHIFT)) & VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_MASK)
103193 /*! @} */
103194 
103195 /*! @name SWREG21_VP8 - Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
103196 /*! @{ */
103197 
103198 #define VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_MASK (0x7C00000U)
103199 #define VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_SHIFT (22U)
103200 /*! SW_C_STRIDE_POW2 - VP8 C stride length informed by 2^n (n=sw_c_stride_pow2). Valid range 10-17 for 32 bit bus and 10-18 for 64 bit bus */
103201 #define VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_SHIFT)) & VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_MASK)
103202 
103203 #define VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_MASK (0xF8000000U)
103204 #define VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_SHIFT (27U)
103205 /*! SW_Y_STRIDE_POW2 - VP8 Y stride length informed by 2^n (n=sw_y_stride_pow2). Valid range 10-17 for 32 bit bus and 10-18 for 64 bit bus */
103206 #define VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_SHIFT)) & VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_MASK)
103207 /*! @} */
103208 
103209 
103210 /*!
103211  * @}
103212  */ /* end of group VPU_G1_VP8_Register_Masks */
103213 
103214 
103215 /* VPU_G1_VP8 - Peripheral instance base addresses */
103216 /** Peripheral VPU_G1_VP8 base address */
103217 #define VPU_G1_VP8_BASE                          (0x38300000u)
103218 /** Peripheral VPU_G1_VP8 base pointer */
103219 #define VPU_G1_VP8                               ((VPU_G1_VP8_Type *)VPU_G1_VP8_BASE)
103220 /** Array initializer of VPU_G1_VP8 peripheral base addresses */
103221 #define VPU_G1_VP8_BASE_ADDRS                    { VPU_G1_VP8_BASE }
103222 /** Array initializer of VPU_G1_VP8 peripheral base pointers */
103223 #define VPU_G1_VP8_BASE_PTRS                     { VPU_G1_VP8 }
103224 
103225 /*!
103226  * @}
103227  */ /* end of group VPU_G1_VP8_Peripheral_Access_Layer */
103228 
103229 
103230 /* ----------------------------------------------------------------------------
103231    -- VPU_G2 Peripheral Access Layer
103232    ---------------------------------------------------------------------------- */
103233 
103234 /*!
103235  * @addtogroup VPU_G2_Peripheral_Access_Layer VPU_G2 Peripheral Access Layer
103236  * @{
103237  */
103238 
103239 /** VPU_G2 - Register Layout Typedef */
103240 typedef struct {
103241   __I  uint32_t SWREG0;                            /**< ID register (read only), offset: 0x0 */
103242   __IO uint32_t SWREG1;                            /**< Interrupt register decoder, offset: 0x4 */
103243   __IO uint32_t SWREG2;                            /**< Data configuration register decoder, offset: 0x8 */
103244   __IO uint32_t SWREG3;                            /**< Decoder control register 0, offset: 0xC */
103245   __IO uint32_t SWREG4;                            /**< Decoder control register 1, offset: 0x10 */
103246   __IO uint32_t SWREG5;                            /**< Decoder control register 2, offset: 0x14 */
103247   __IO uint32_t SWREG6;                            /**< Decoder control register 3, offset: 0x18 */
103248   __IO uint32_t SWREG7;                            /**< Decoder control register 4, offset: 0x1C */
103249   __IO uint32_t SWREG8;                            /**< Decoder control register 5, offset: 0x20 */
103250   __IO uint32_t SWREG9;                            /**< Decoder control register 6, offset: 0x24 */
103251   __IO uint32_t SWREG10;                           /**< Decoder control register 7, offset: 0x28 */
103252   __IO uint32_t SWREG11;                           /**< Decoder control register 8, offset: 0x2C */
103253   __IO uint32_t SWREG12;                           /**< Decoder control register 9, offset: 0x30 */
103254   __IO uint32_t SWREG13;                           /**< Decoder control register 10, offset: 0x34 */
103255   __IO uint32_t SWREG14;                           /**< Initial ref pic list register (0-2), offset: 0x38 */
103256   __IO uint32_t SWREG15;                           /**< Initial ref pic list register (3-5), offset: 0x3C */
103257   __IO uint32_t SWREG16;                           /**< Initial ref pic list register (6-8), offset: 0x40 */
103258   __IO uint32_t SWREG17;                           /**< Initial ref pic list register (9-11), offset: 0x44 */
103259   __IO uint32_t SWREG18;                           /**< Initial ref pic list register (12-14), offset: 0x48 */
103260   __IO uint32_t SWREG19;                           /**< Initial ref pic list register (15 and P 0-3), offset: 0x4C */
103261   __IO uint32_t SWREG20;                           /**< Decoder control register 11, offset: 0x50 */
103262        uint32_t SWREG21;                           /**< Not used, offset: 0x54 */
103263        uint32_t SWREG22;                           /**< Not used, offset: 0x58 */
103264   __I  uint32_t SWREG23;                           /**< Decoder configure status register, offset: 0x5C */
103265        uint32_t SWREG24;                           /**< Not used, offset: 0x60 */
103266        uint32_t SWREG25;                           /**< Not used, offset: 0x64 */
103267        uint32_t SWREG26;                           /**< Not used, offset: 0x68 */
103268        uint32_t SWREG27;                           /**< Not used, offset: 0x6C */
103269        uint32_t SWREG28;                           /**< Not used, offset: 0x70 */
103270        uint32_t SWREG29;                           /**< Not used, offset: 0x74 */
103271        uint32_t SWREG30;                           /**< Not used, offset: 0x78 */
103272   __IO uint32_t SWREG31;                           /**< VP9 segmentation values, offset: 0x7C */
103273   __IO uint32_t SWREG32;                           /**< VP9 segmentation values, offset: 0x80 */
103274   __IO uint32_t SWREG33;                           /**< VP9 reference picture scaling register 0, offset: 0x84 */
103275   __IO uint32_t SWREG34;                           /**< VP9 reference picture scaling register 1, offset: 0x88 */
103276   __IO uint32_t SWREG35;                           /**< VP9 reference picture scaling register 2, offset: 0x8C */
103277   __IO uint32_t SWREG36;                           /**< VP9 reference picture scaling register 3, offset: 0x90 */
103278   __IO uint32_t SWREG37;                           /**< VP9 reference picture scaling register 4, offset: 0x94 */
103279   __IO uint32_t SWREG38;                           /**< VP9 reference picture scaling register 5, offset: 0x98 */
103280        uint32_t SWREG39;                           /**< Not used, offset: 0x9C */
103281        uint32_t SWREG40;                           /**< Not used, offset: 0xA0 */
103282        uint32_t SWREG41;                           /**< Not used, offset: 0xA4 */
103283        uint32_t SWREG42;                           /**< Not used, offset: 0xA8 */
103284        uint32_t SWREG43;                           /**< Not used, offset: 0xAC */
103285        uint32_t SWREG44;                           /**< Not used, offset: 0xB0 */
103286   __IO uint32_t SWREG45;                           /**< Timeout control register, offset: 0xB4 */
103287   __IO uint32_t SWREG46;                           /**< Picture order count from current pictures for index 0-3, offset: 0xB8 */
103288   __IO uint32_t SWREG47;                           /**< Picture order count from current pictures for index 4-7, offset: 0xBC */
103289   __IO uint32_t SWREG48;                           /**< Picture order count from current pictures for index 8-11, offset: 0xC0 */
103290   __IO uint32_t SWREG49;                           /**< Picture order count from current pictures for index 12-15, offset: 0xC4 */
103291   __I  uint32_t SWREG50;                           /**< Synthesis configuration register decoder 0 (read only), offset: 0xC8 */
103292        uint32_t SWREG51;                           /**< Reference picture buffer control register, offset: 0xCC */
103293        uint32_t SWREG52;                           /**< Reference picture buffer information register 1 (read only), offset: 0xD0 */
103294        uint32_t SWREG53;                           /**< Reference picture buffer information register 2 (read only), offset: 0xD4 */
103295   __I  uint32_t SWREG54;                           /**< Synthesis configuration register decoder 1 (read only), offset: 0xD8 */
103296   __IO uint32_t SWREG55;                           /**< Advanced prefetch control register, offset: 0xDC */
103297   __I  uint32_t SWREG56;                           /**< Synthesis configuration register decoder 2 (read only), offset: 0xE0 */
103298        uint32_t SWREG57;                           /**< Decoder fuse register (read only), offset: 0xE4 */
103299   __IO uint32_t SWREG58;                           /**< Device configuration register decoder 2 + Multi core control register, offset: 0xE8 */
103300   __IO uint32_t SWREG59;                           /**< Device configuration register AXI ID, offset: 0xEC */
103301   __I  uint32_t SWREG60;                           /**< Synthesis configuration register decoder 3 for PP (read only), offset: 0xF0 */
103302        uint32_t SWREG61;                           /**< Not used, offset: 0xF4 */
103303   __IO uint32_t SWREG62;                           /**< HW proceed register (CU location), offset: 0xF8 */
103304   __I  uint32_t SWREG63;                           /**< HW performance register (cycles running), offset: 0xFC */
103305   __IO uint32_t SWREG64;                           /**< Base address MSB (bits 63:32) for decoded luminance picture, offset: 0x100 */
103306   __IO uint32_t SWREG65;                           /**< Base address LSB (bits 31:0) for decoded luminance picture, offset: 0x104 */
103307   __IO uint32_t SWREG66;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 0, offset: 0x108 */
103308   __IO uint32_t SWREG67;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 0, offset: 0x10C */
103309   __IO uint32_t SWREG68;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 1, offset: 0x110 */
103310   __IO uint32_t SWREG69;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 1, offset: 0x114 */
103311   __IO uint32_t SWREG70;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 2, offset: 0x118 */
103312   __IO uint32_t SWREG71;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 2, offset: 0x11C */
103313   __IO uint32_t SWREG72;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 3, offset: 0x120 */
103314   __IO uint32_t SWREG73;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 3, offset: 0x124 */
103315   __IO uint32_t SWREG74;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 4, offset: 0x128 */
103316   __IO uint32_t SWREG75;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 4, offset: 0x12C */
103317   __IO uint32_t SWREG76;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 5, offset: 0x130 */
103318   __IO uint32_t SWREG77;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 5, offset: 0x134 */
103319   __IO uint32_t SWREG78;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 6 /VP9 segment write base MSB, offset: 0x138 */
103320   __IO uint32_t SWREG79;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 6 /VP9 segment write base LSB, offset: 0x13C */
103321   __IO uint32_t SWREG80;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 7 /VP9 segment read base MSB, offset: 0x140 */
103322   __IO uint32_t SWREG81;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 7 /VP9 segment read base LSB, offset: 0x144 */
103323   __IO uint32_t SWREG82;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 8, offset: 0x148 */
103324   __IO uint32_t SWREG83;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 8, offset: 0x14C */
103325   __IO uint32_t SWREG84;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 9, offset: 0x150 */
103326   __IO uint32_t SWREG85;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 9, offset: 0x154 */
103327   __IO uint32_t SWREG86;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 10, offset: 0x158 */
103328   __IO uint32_t SWREG87;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 10, offset: 0x15C */
103329   __IO uint32_t SWREG88;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 11, offset: 0x160 */
103330   __IO uint32_t SWREG89;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 11, offset: 0x164 */
103331   __IO uint32_t SWREG90;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 12, offset: 0x168 */
103332   __IO uint32_t SWREG91;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 12, offset: 0x16C */
103333   __IO uint32_t SWREG92;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 13, offset: 0x170 */
103334   __IO uint32_t SWREG93;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 13, offset: 0x174 */
103335   __IO uint32_t SWREG94;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 14, offset: 0x178 */
103336   __IO uint32_t SWREG95;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 14, offset: 0x17C */
103337   __IO uint32_t SWREG96;                           /**< Base address MSB (bits 63:32) for reference luminance picture index 15, offset: 0x180 */
103338   __IO uint32_t SWREG97;                           /**< Base address LSB (bits 31:0) for reference luminance picture index 15, offset: 0x184 */
103339   __IO uint32_t SWREG98;                           /**< Base address MSB (bits 63:32) for decoded chrominance picture, offset: 0x188 */
103340   __IO uint32_t SWREG99;                           /**< Base address LSB (bits 31:0) for decoded chrominance picture, offset: 0x18C */
103341   __IO uint32_t SWREG100;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 0, offset: 0x190 */
103342   __IO uint32_t SWREG101;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 0, offset: 0x194 */
103343   __IO uint32_t SWREG102;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 1, offset: 0x198 */
103344   __IO uint32_t SWREG103;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 1, offset: 0x19C */
103345   __IO uint32_t SWREG104;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 2, offset: 0x1A0 */
103346   __IO uint32_t SWREG105;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 2, offset: 0x1A4 */
103347   __IO uint32_t SWREG106;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 3, offset: 0x1A8 */
103348   __IO uint32_t SWREG107;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 3, offset: 0x1AC */
103349   __IO uint32_t SWREG108;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 4, offset: 0x1B0 */
103350   __IO uint32_t SWREG109;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 4, offset: 0x1B4 */
103351   __IO uint32_t SWREG110;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 5, offset: 0x1B8 */
103352   __IO uint32_t SWREG111;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 5, offset: 0x1BC */
103353   __IO uint32_t SWREG112;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 6, offset: 0x1C0 */
103354   __IO uint32_t SWREG113;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 6, offset: 0x1C4 */
103355   __IO uint32_t SWREG114;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 7, offset: 0x1C8 */
103356   __IO uint32_t SWREG115;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 7, offset: 0x1CC */
103357   __IO uint32_t SWREG116;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 8, offset: 0x1D0 */
103358   __IO uint32_t SWREG117;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 8, offset: 0x1D4 */
103359   __IO uint32_t SWREG118;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 9, offset: 0x1D8 */
103360   __IO uint32_t SWREG119;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 9, offset: 0x1DC */
103361   __IO uint32_t SWREG120;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 10, offset: 0x1E0 */
103362   __IO uint32_t SWREG121;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 10, offset: 0x1E4 */
103363   __IO uint32_t SWREG122;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 11, offset: 0x1E8 */
103364   __IO uint32_t SWREG123;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 11, offset: 0x1EC */
103365   __IO uint32_t SWREG124;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 12, offset: 0x1F0 */
103366   __IO uint32_t SWREG125;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 12, offset: 0x1F4 */
103367   __IO uint32_t SWREG126;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 13, offset: 0x1F8 */
103368   __IO uint32_t SWREG127;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 13, offset: 0x1FC */
103369   __IO uint32_t SWREG128;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 14, offset: 0x200 */
103370   __IO uint32_t SWREG129;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 14, offset: 0x204 */
103371   __IO uint32_t SWREG130;                          /**< Base address MSB (bits 63:32) for reference chrominance picture index 15, offset: 0x208 */
103372   __IO uint32_t SWREG131;                          /**< Base address LSB (bits 31:0) for reference chrominance picture index 15, offset: 0x20C */
103373   __IO uint32_t SWREG132;                          /**< Base address MSB (bits 63:32) for decoded direct mode MVS, offset: 0x210 */
103374   __IO uint32_t SWREG133;                          /**< Base address LSB (bits 31:0) for decoded direct mode MVS, offset: 0x214 */
103375   __IO uint32_t SWREG134;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 0, offset: 0x218 */
103376   __IO uint32_t SWREG135;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 0, offset: 0x21C */
103377   __IO uint32_t SWREG136;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 1, offset: 0x220 */
103378   __IO uint32_t SWREG137;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 1, offset: 0x224 */
103379   __IO uint32_t SWREG138;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 2, offset: 0x228 */
103380   __IO uint32_t SWREG139;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 2, offset: 0x22C */
103381   __IO uint32_t SWREG140;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 3, offset: 0x230 */
103382   __IO uint32_t SWREG141;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 3, offset: 0x234 */
103383   __IO uint32_t SWREG142;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 4, offset: 0x238 */
103384   __IO uint32_t SWREG143;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 4, offset: 0x23C */
103385   __IO uint32_t SWREG144;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 5, offset: 0x240 */
103386   __IO uint32_t SWREG145;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 5, offset: 0x244 */
103387   __IO uint32_t SWREG146;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 6, offset: 0x248 */
103388   __IO uint32_t SWREG147;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 6, offset: 0x24C */
103389   __IO uint32_t SWREG148;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 7, offset: 0x250 */
103390   __IO uint32_t SWREG149;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 7, offset: 0x254 */
103391   __IO uint32_t SWREG150;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 8, offset: 0x258 */
103392   __IO uint32_t SWREG151;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 8, offset: 0x25C */
103393   __IO uint32_t SWREG152;                          /**< Base address MSB (bits 63:32) for reference direct mode mode MVS index 9, offset: 0x260 */
103394   __IO uint32_t SWREG153;                          /**< Base address LSB (bits 31:0) for reference direct mode mode MVS index 9, offset: 0x264 */
103395   __IO uint32_t SWREG154;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 10, offset: 0x268 */
103396   __IO uint32_t SWREG155;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 10, offset: 0x26C */
103397   __IO uint32_t SWREG156;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 11, offset: 0x270 */
103398   __IO uint32_t SWREG157;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 11, offset: 0x274 */
103399   __IO uint32_t SWREG158;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 12, offset: 0x278 */
103400   __IO uint32_t SWREG159;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 12, offset: 0x27C */
103401   __IO uint32_t SWREG160;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 13, offset: 0x280 */
103402   __IO uint32_t SWREG161;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 13, offset: 0x284 */
103403   __IO uint32_t SWREG162;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 14, offset: 0x288 */
103404   __IO uint32_t SWREG163;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 14, offset: 0x28C */
103405   __IO uint32_t SWREG164;                          /**< Base address MSB (bits 63:32) for reference direct mode MVS index 15, offset: 0x290 */
103406   __IO uint32_t SWREG165;                          /**< Base address LSB (bits 31:0) for reference direct mode MVS index 15, offset: 0x294 */
103407   __IO uint32_t SWREG166;                          /**< Base address MSB (bits 63:32) for tile sizes, offset: 0x298 */
103408   __IO uint32_t SWREG167;                          /**< Base address LSB (bits 31:0) for tile sizes, offset: 0x29C */
103409   __IO uint32_t SWREG168;                          /**< Base address MSB (bits 63:32) for / stream start address/decoded end addr register, offset: 0x2A0 */
103410   __IO uint32_t SWREG169;                          /**< Base address LSB (bits 31:0) for / stream start address/decoded end addr register, offset: 0x2A4 */
103411   __IO uint32_t SWREG170;                          /**< Base address MSB (bits 63:32) for scaling lists / VP9 CTX counter values, offset: 0x2A8 */
103412   __IO uint32_t SWREG171;                          /**< Base address LSB (bits 31:0) for scaling lists / VP9 CTX counter values, offset: 0x2AC */
103413   __IO uint32_t SWREG172;                          /**< Base address MSB (bits 63:32) for stream propability tables, offset: 0x2B0 */
103414   __IO uint32_t SWREG173;                          /**< Base address LSB (bits 31:0) for stream propability tables, offset: 0x2B4 */
103415   __IO uint32_t SWREG174;                          /**< Base address MSB (bits 63:32) for decoder output raster scan Y picture, offset: 0x2B8 */
103416   __IO uint32_t SWREG175;                          /**< Base address LSB (bits 31:0) for decoder output raster scan Y picture, offset: 0x2BC */
103417   __IO uint32_t SWREG176;                          /**< Base address MSB (bits 63:32) for decoder output raster scan C picture, offset: 0x2C0 */
103418   __IO uint32_t SWREG177;                          /**< Base address LSB (bits 31:0) for decoder output raster scan C picture, offset: 0x2C4 */
103419   __IO uint32_t SWREG178;                          /**< Base address MSB (bits 63:32) for tile border coeffients of filter, offset: 0x2C8 */
103420   __IO uint32_t SWREG179;                          /**< Base address LSB (bits 31:0) for tile border coeffients of filter, offset: 0x2CC */
103421   __IO uint32_t SWREG180;                          /**< Base address MSB (bits 63:32) for tile border coeffients of sao, offset: 0x2D0 */
103422   __IO uint32_t SWREG181;                          /**< Base address LSB (bits 31:0) for tile border coeffients of sao, offset: 0x2D4 */
103423   __IO uint32_t SWREG182;                          /**< Base address MSB (bits 63:32) for tile border bsd control data, offset: 0x2D8 */
103424   __IO uint32_t SWREG183;                          /**< Base address LSB (bits 31:0) for tile border bsd control data, offset: 0x2DC */
103425   __IO uint32_t SWREG184;                          /**< Raster scan down scale control register MSM, offset: 0x2E0 */
103426   __IO uint32_t SWREG185;                          /**< Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture, offset: 0x2E4 */
103427   __IO uint32_t SWREG186;                          /**< Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture, offset: 0x2E8 */
103428   __IO uint32_t SWREG187;                          /**< Base address MSB (bits 63:32) for decoder output raster scan down scale C picture, offset: 0x2EC */
103429   __IO uint32_t SWREG188;                          /**< Base address LSB (bits 31:0) for decoder output raster scan down scale C picture, offset: 0x2F0 */
103430   __IO uint32_t SWREG189;                          /**< Base address MSB (bits 63:32) for decoder output compress luminance table, offset: 0x2F4 */
103431   __IO uint32_t SWREG190;                          /**< Base address LSB (bits 31:0) for decoder output compress luminance table, offset: 0x2F8 */
103432   __IO uint32_t SWREG191;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 0, offset: 0x2FC */
103433   __IO uint32_t SWREG192;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 0, offset: 0x300 */
103434   __IO uint32_t SWREG193;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 1, offset: 0x304 */
103435   __IO uint32_t SWREG194;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 1, offset: 0x308 */
103436   __IO uint32_t SWREG195;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 2, offset: 0x30C */
103437   __IO uint32_t SWREG196;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 2, offset: 0x310 */
103438   __IO uint32_t SWREG197;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 3, offset: 0x314 */
103439   __IO uint32_t SWREG198;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 3, offset: 0x318 */
103440   __IO uint32_t SWREG199;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 4, offset: 0x31C */
103441   __IO uint32_t SWREG200;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 4, offset: 0x320 */
103442   __IO uint32_t SWREG201;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 5, offset: 0x324 */
103443   __IO uint32_t SWREG202;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 5, offset: 0x328 */
103444   __IO uint32_t SWREG203;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 6, offset: 0x32C */
103445   __IO uint32_t SWREG204;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 6, offset: 0x330 */
103446   __IO uint32_t SWREG205;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 7, offset: 0x334 */
103447   __IO uint32_t SWREG206;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 7, offset: 0x338 */
103448   __IO uint32_t SWREG207;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 8, offset: 0x33C */
103449   __IO uint32_t SWREG208;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 8, offset: 0x340 */
103450   __IO uint32_t SWREG209;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 9, offset: 0x344 */
103451   __IO uint32_t SWREG210;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 9, offset: 0x348 */
103452   __IO uint32_t SWREG211;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 10, offset: 0x34C */
103453   __IO uint32_t SWREG212;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 10, offset: 0x350 */
103454   __IO uint32_t SWREG213;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 11, offset: 0x354 */
103455   __IO uint32_t SWREG214;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 11, offset: 0x358 */
103456   __IO uint32_t SWREG215;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 12, offset: 0x35C */
103457   __IO uint32_t SWREG216;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 12, offset: 0x360 */
103458   __IO uint32_t SWREG217;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 13, offset: 0x364 */
103459   __IO uint32_t SWREG218;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 13, offset: 0x368 */
103460   __IO uint32_t SWREG219;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 14, offset: 0x36C */
103461   __IO uint32_t SWREG220;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 14, offset: 0x370 */
103462   __IO uint32_t SWREG221;                          /**< Base address MSB (bits 63:32) for reference compress luminance table index 15, offset: 0x374 */
103463   __IO uint32_t SWREG222;                          /**< Base address LSB (bits 31:0) for reference compress luminance table index 15, offset: 0x378 */
103464   __IO uint32_t SWREG223;                          /**< Base address MSB (bits 63:32) for decoder output compress chrominance table, offset: 0x37C */
103465   __IO uint32_t SWREG224;                          /**< Base address LSB (bits 31:0) for decoder output compress chrominance table, offset: 0x380 */
103466   __IO uint32_t SWREG225;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 0, offset: 0x384 */
103467   __IO uint32_t SWREG226;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 0, offset: 0x388 */
103468   __IO uint32_t SWREG227;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 1, offset: 0x38C */
103469   __IO uint32_t SWREG228;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 1, offset: 0x390 */
103470   __IO uint32_t SWREG229;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 2, offset: 0x394 */
103471   __IO uint32_t SWREG230;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 2, offset: 0x398 */
103472   __IO uint32_t SWREG231;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 3, offset: 0x39C */
103473   __IO uint32_t SWREG232;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 3, offset: 0x3A0 */
103474   __IO uint32_t SWREG233;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 4, offset: 0x3A4 */
103475   __IO uint32_t SWREG234;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 4, offset: 0x3A8 */
103476   __IO uint32_t SWREG235;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 5, offset: 0x3AC */
103477   __IO uint32_t SWREG236;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 5, offset: 0x3B0 */
103478   __IO uint32_t SWREG237;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 6, offset: 0x3B4 */
103479   __IO uint32_t SWREG238;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 6, offset: 0x3B8 */
103480   __IO uint32_t SWREG239;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 7, offset: 0x3BC */
103481   __IO uint32_t SWREG240;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 7, offset: 0x3C0 */
103482   __IO uint32_t SWREG241;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 8, offset: 0x3C4 */
103483   __IO uint32_t SWREG242;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 8, offset: 0x3C8 */
103484   __IO uint32_t SWREG243;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 9, offset: 0x3CC */
103485   __IO uint32_t SWREG244;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 9, offset: 0x3D0 */
103486   __IO uint32_t SWREG245;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 10, offset: 0x3D4 */
103487   __IO uint32_t SWREG246;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 10, offset: 0x3D8 */
103488   __IO uint32_t SWREG247;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 11, offset: 0x3DC */
103489   __IO uint32_t SWREG248;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 11, offset: 0x3E0 */
103490   __IO uint32_t SWREG249;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 12, offset: 0x3E4 */
103491   __IO uint32_t SWREG250;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 12, offset: 0x3E8 */
103492   __IO uint32_t SWREG251;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 13, offset: 0x3EC */
103493   __IO uint32_t SWREG252;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 13, offset: 0x3F0 */
103494   __IO uint32_t SWREG253;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 14, offset: 0x3F4 */
103495   __IO uint32_t SWREG254;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 14, offset: 0x3F8 */
103496   __IO uint32_t SWREG255;                          /**< Base address MSB (bits 63:32) for reference compress chrominance table index 15, offset: 0x3FC */
103497   __IO uint32_t SWREG256;                          /**< Base address LSB (bits 31:0) for reference compress chrominance table index 15, offset: 0x400 */
103498        uint32_t SWREG257;                          /**< Not used, offset: 0x404 */
103499   __IO uint32_t SWREG258;                          /**< input stream buffer length, offset: 0x408 */
103500   __IO uint32_t SWREG259;                          /**< input stream buffer start offset, offset: 0x40C */
103501 } VPU_G2_Type;
103502 
103503 /* ----------------------------------------------------------------------------
103504    -- VPU_G2 Register Masks
103505    ---------------------------------------------------------------------------- */
103506 
103507 /*!
103508  * @addtogroup VPU_G2_Register_Masks VPU_G2 Register Masks
103509  * @{
103510  */
103511 
103512 /*! @name SWREG0 - ID register (read only) */
103513 /*! @{ */
103514 
103515 #define VPU_G2_SWREG0_SW_BUILD_VERSION_MASK      (0x7U)
103516 #define VPU_G2_SWREG0_SW_BUILD_VERSION_SHIFT     (0U)
103517 /*! SW_BUILD_VERSION - Build version (core number) */
103518 #define VPU_G2_SWREG0_SW_BUILD_VERSION(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_BUILD_VERSION_SHIFT)) & VPU_G2_SWREG0_SW_BUILD_VERSION_MASK)
103519 
103520 #define VPU_G2_SWREG0_SW_PRODUCT_ID_EN_MASK      (0x8U)
103521 #define VPU_G2_SWREG0_SW_PRODUCT_ID_EN_SHIFT     (3U)
103522 /*! SW_PRODUCT_ID_EN - ASCII type product ID enable */
103523 #define VPU_G2_SWREG0_SW_PRODUCT_ID_EN(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_PRODUCT_ID_EN_SHIFT)) & VPU_G2_SWREG0_SW_PRODUCT_ID_EN_MASK)
103524 
103525 #define VPU_G2_SWREG0_SW_MINOR_VERSION_MASK      (0xFF0U)
103526 #define VPU_G2_SWREG0_SW_MINOR_VERSION_SHIFT     (4U)
103527 /*! SW_MINOR_VERSION - Minor version */
103528 #define VPU_G2_SWREG0_SW_MINOR_VERSION(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_MINOR_VERSION_SHIFT)) & VPU_G2_SWREG0_SW_MINOR_VERSION_MASK)
103529 
103530 #define VPU_G2_SWREG0_SW_MAJOR_VERSION_MASK      (0xF000U)
103531 #define VPU_G2_SWREG0_SW_MAJOR_VERSION_SHIFT     (12U)
103532 /*! SW_MAJOR_VERSION - Major version */
103533 #define VPU_G2_SWREG0_SW_MAJOR_VERSION(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_MAJOR_VERSION_SHIFT)) & VPU_G2_SWREG0_SW_MAJOR_VERSION_MASK)
103534 
103535 #define VPU_G2_SWREG0_SW_PRODUCT_NUMBER_MASK     (0xFFFF0000U)
103536 #define VPU_G2_SWREG0_SW_PRODUCT_NUMBER_SHIFT    (16U)
103537 /*! SW_PRODUCT_NUMBER - Product number (g2) */
103538 #define VPU_G2_SWREG0_SW_PRODUCT_NUMBER(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_PRODUCT_NUMBER_SHIFT)) & VPU_G2_SWREG0_SW_PRODUCT_NUMBER_MASK)
103539 /*! @} */
103540 
103541 /*! @name SWREG1 - Interrupt register decoder */
103542 /*! @{ */
103543 
103544 #define VPU_G2_SWREG1_SW_DEC_E_MASK              (0x1U)
103545 #define VPU_G2_SWREG1_SW_DEC_E_SHIFT             (0U)
103546 /*! SW_DEC_E - Decoder enable. Setting this bit high will start the decoding operation. HW will
103547  *    reset this when picture is processed or ASO or stream error is detected or bus error or timeout
103548  *    interrupt is given.
103549  */
103550 #define VPU_G2_SWREG1_SW_DEC_E(x)                (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_E_SHIFT)) & VPU_G2_SWREG1_SW_DEC_E_MASK)
103551 
103552 #define VPU_G2_SWREG1_SW_DEC_IRQ_DIS_MASK        (0x10U)
103553 #define VPU_G2_SWREG1_SW_DEC_IRQ_DIS_SHIFT       (4U)
103554 /*! SW_DEC_IRQ_DIS - Decoder IRQ disable. When high there are no interrupts concerning decoder from
103555  *    HW. Polling must be used to see the interrupt statuses.
103556  */
103557 #define VPU_G2_SWREG1_SW_DEC_IRQ_DIS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_IRQ_DIS_SHIFT)) & VPU_G2_SWREG1_SW_DEC_IRQ_DIS_MASK)
103558 
103559 #define VPU_G2_SWREG1_SW_DEC_ABORT_E_MASK        (0x20U)
103560 #define VPU_G2_SWREG1_SW_DEC_ABORT_E_SHIFT       (5U)
103561 /*! SW_DEC_ABORT_E - Abort decoding enable. Setting this bit high will cause HW to abort decoding
103562  *    and safely to reset itself down. After abort is complete the corresponding interrupt status is
103563  *    set and this bit is set low as well as the decoder enable.
103564  */
103565 #define VPU_G2_SWREG1_SW_DEC_ABORT_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_ABORT_E_SHIFT)) & VPU_G2_SWREG1_SW_DEC_ABORT_E_MASK)
103566 
103567 #define VPU_G2_SWREG1_SW_DEC_IRQ_MASK            (0x100U)
103568 #define VPU_G2_SWREG1_SW_DEC_IRQ_SHIFT           (8U)
103569 /*! SW_DEC_IRQ - Decoder IRQ. When high decoder requests an interrupt. SW will reset this after interrupt is handled. */
103570 #define VPU_G2_SWREG1_SW_DEC_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_IRQ_SHIFT)) & VPU_G2_SWREG1_SW_DEC_IRQ_MASK)
103571 
103572 #define VPU_G2_SWREG1_SW_DEC_ABORT_INT_MASK      (0x800U)
103573 #define VPU_G2_SWREG1_SW_DEC_ABORT_INT_SHIFT     (11U)
103574 /*! SW_DEC_ABORT_INT - Interrupt status bit decoding aborted. When this bit is high decoder has
103575  *    aborted the current picture decoding as SW requested (sw_dec_abort_e). Decoder self reset and
103576  *    sw_dec_abort_e written low
103577  */
103578 #define VPU_G2_SWREG1_SW_DEC_ABORT_INT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_ABORT_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_ABORT_INT_MASK)
103579 
103580 #define VPU_G2_SWREG1_SW_DEC_RDY_INT_MASK        (0x1000U)
103581 #define VPU_G2_SWREG1_SW_DEC_RDY_INT_SHIFT       (12U)
103582 /*! SW_DEC_RDY_INT - Interrupt status bit decoder. When this bit is high decoder has decoded a picture. HW will self reset. */
103583 #define VPU_G2_SWREG1_SW_DEC_RDY_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_RDY_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_RDY_INT_MASK)
103584 
103585 #define VPU_G2_SWREG1_SW_DEC_BUS_INT_MASK        (0x2000U)
103586 #define VPU_G2_SWREG1_SW_DEC_BUS_INT_SHIFT       (13U)
103587 /*! SW_DEC_BUS_INT - Interrupt status bit bus. Error response from bus. HW will self reset. */
103588 #define VPU_G2_SWREG1_SW_DEC_BUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_BUS_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_BUS_INT_MASK)
103589 
103590 #define VPU_G2_SWREG1_SW_DEC_BUFFER_INT_MASK     (0x4000U)
103591 #define VPU_G2_SWREG1_SW_DEC_BUFFER_INT_SHIFT    (14U)
103592 /*! SW_DEC_BUFFER_INT - Interrupt status bit input buffer empty. When high input stream buffer is
103593  *    empty but picture is not ready. HW will not self reset.
103594  */
103595 #define VPU_G2_SWREG1_SW_DEC_BUFFER_INT(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_BUFFER_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_BUFFER_INT_MASK)
103596 
103597 #define VPU_G2_SWREG1_SW_DEC_ERROR_INT_MASK      (0x10000U)
103598 #define VPU_G2_SWREG1_SW_DEC_ERROR_INT_SHIFT     (16U)
103599 /*! SW_DEC_ERROR_INT - Interrupt status bit input stream error. When high an error is found in input data stream decoding. HW will self reset. */
103600 #define VPU_G2_SWREG1_SW_DEC_ERROR_INT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_ERROR_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_ERROR_INT_MASK)
103601 
103602 #define VPU_G2_SWREG1_SW_DEC_TIMEOUT_MASK        (0x40000U)
103603 #define VPU_G2_SWREG1_SW_DEC_TIMEOUT_SHIFT       (18U)
103604 /*! SW_DEC_TIMEOUT - Interrupt status bit decoder timeout. When high the decoder has been idling for
103605  *    too long. HW will self reset. Possible only if timeout interrupt is enabled
103606  */
103607 #define VPU_G2_SWREG1_SW_DEC_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_TIMEOUT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_TIMEOUT_MASK)
103608 /*! @} */
103609 
103610 /*! @name SWREG2 - Data configuration register decoder */
103611 /*! @{ */
103612 
103613 #define VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_MASK     (0xFU)
103614 #define VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_SHIFT    (0U)
103615 /*! SW_DEC_RSCAN_SWAP - Byte swap for raster scan output picture data */
103616 #define VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_MASK)
103617 
103618 #define VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_MASK      (0xF0U)
103619 #define VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_SHIFT     (4U)
103620 /*! SW_DEC_TAB3_SWAP - Byte swap configuration for tile sizes */
103621 #define VPU_G2_SWREG2_SW_DEC_TAB3_SWAP(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_MASK)
103622 
103623 #define VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_MASK      (0xF00U)
103624 #define VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_SHIFT     (8U)
103625 /*! SW_DEC_TAB2_SWAP - Byte swap configuration for VP9 CTX counter values */
103626 #define VPU_G2_SWREG2_SW_DEC_TAB2_SWAP(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_MASK)
103627 
103628 #define VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_MASK      (0xF000U)
103629 #define VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_SHIFT     (12U)
103630 /*! SW_DEC_TAB1_SWAP - Byte swap configuration for HEVC scaling lists / VP9 segmentation map read/write */
103631 #define VPU_G2_SWREG2_SW_DEC_TAB1_SWAP(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_MASK)
103632 
103633 #define VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_MASK      (0xF0000U)
103634 #define VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_SHIFT     (16U)
103635 /*! SW_DEC_TAB0_SWAP - Byte swap configuration for VP9 stream propability tables */
103636 #define VPU_G2_SWREG2_SW_DEC_TAB0_SWAP(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_MASK)
103637 
103638 #define VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_MASK     (0xF00000U)
103639 #define VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_SHIFT    (20U)
103640 /*! SW_DEC_DIRMV_SWAP - Byte swap configuration for direct mode MV data (read/write) */
103641 #define VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_MASK)
103642 
103643 #define VPU_G2_SWREG2_SW_DEC_PIC_SWAP_MASK       (0xF000000U)
103644 #define VPU_G2_SWREG2_SW_DEC_PIC_SWAP_SHIFT      (24U)
103645 /*! SW_DEC_PIC_SWAP - Byte swap configuration for decoder reference output picture data */
103646 #define VPU_G2_SWREG2_SW_DEC_PIC_SWAP(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_PIC_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_PIC_SWAP_MASK)
103647 
103648 #define VPU_G2_SWREG2_SW_DEC_STRM_SWAP_MASK      (0xF0000000U)
103649 #define VPU_G2_SWREG2_SW_DEC_STRM_SWAP_SHIFT     (28U)
103650 /*! SW_DEC_STRM_SWAP - Byte swap configuration for stream data 4 Bit byte order vector to control
103651  *    byte locations inside HW internal 128 bit data vector. For 64 and 32 bit external bus widths,
103652  *    the data is first gathered to 128 bit width and then bytes swapped accordingly:
103653  */
103654 #define VPU_G2_SWREG2_SW_DEC_STRM_SWAP(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_STRM_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_STRM_SWAP_MASK)
103655 /*! @} */
103656 
103657 /*! @name SWREG3 - Decoder control register 0 */
103658 /*! @{ */
103659 
103660 #define VPU_G2_SWREG3_SW_APF_ONE_PID_MASK        (0x800U)
103661 #define VPU_G2_SWREG3_SW_APF_ONE_PID_SHIFT       (11U)
103662 /*! SW_APF_ONE_PID - Prefetch partitions that have the same pic_id together */
103663 #define VPU_G2_SWREG3_SW_APF_ONE_PID(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_APF_ONE_PID_SHIFT)) & VPU_G2_SWREG3_SW_APF_ONE_PID_MASK)
103664 
103665 #define VPU_G2_SWREG3_SW_WRITE_MVS_E_MASK        (0x1000U)
103666 #define VPU_G2_SWREG3_SW_WRITE_MVS_E_SHIFT       (12U)
103667 /*! SW_WRITE_MVS_E - Direct mode motion vector write enable for current picture
103668  *  0b0..Writing disabled for current picture.
103669  *  0b1..The direct mode motion vectors are written to external memory. HEVC/VP9 direct mode motion vectors are
103670  *       written to DPB aside with the corresponding reference picture. Other decoding mode dir mode mvs are written
103671  *       to external memory starting from sw_dir_mv_base.
103672  */
103673 #define VPU_G2_SWREG3_SW_WRITE_MVS_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_WRITE_MVS_E_SHIFT)) & VPU_G2_SWREG3_SW_WRITE_MVS_E_MASK)
103674 
103675 #define VPU_G2_SWREG3_SW_FILTERING_DIS_MASK      (0x4000U)
103676 #define VPU_G2_SWREG3_SW_FILTERING_DIS_SHIFT     (14U)
103677 /*! SW_FILTERING_DIS - De-block filtering disable
103678  *  0b1..Filtering is disabled for current picture
103679  *  0b0..Filtering is enabled for current picture
103680  */
103681 #define VPU_G2_SWREG3_SW_FILTERING_DIS(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_FILTERING_DIS_SHIFT)) & VPU_G2_SWREG3_SW_FILTERING_DIS_MASK)
103682 
103683 #define VPU_G2_SWREG3_SW_DEC_OUT_DIS_MASK        (0x8000U)
103684 #define VPU_G2_SWREG3_SW_DEC_OUT_DIS_SHIFT       (15U)
103685 /*! SW_DEC_OUT_DIS - Disable decoder output picture writing
103686  *  0b0..Decoder output picture is written to external memory
103687  *  0b1..Decoder output picture is not written to external memory
103688  */
103689 #define VPU_G2_SWREG3_SW_DEC_OUT_DIS(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_OUT_DIS_SHIFT)) & VPU_G2_SWREG3_SW_DEC_OUT_DIS_MASK)
103690 
103691 #define VPU_G2_SWREG3_SW_DEC_OUT_RS_E_MASK       (0x10000U)
103692 #define VPU_G2_SWREG3_SW_DEC_OUT_RS_E_SHIFT      (16U)
103693 /*! SW_DEC_OUT_RS_E - Raster scan output enable. If high decoder writes the raster scan output if
103694  *    the configuration of Decoder includes PP raster scan output
103695  */
103696 #define VPU_G2_SWREG3_SW_DEC_OUT_RS_E(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_OUT_RS_E_SHIFT)) & VPU_G2_SWREG3_SW_DEC_OUT_RS_E_MASK)
103697 
103698 #define VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_MASK  (0x20000U)
103699 #define VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_SHIFT (17U)
103700 /*! SW_DEC_OUT_EC_BYPASS - Compress bypass */
103701 #define VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_SHIFT)) & VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_MASK)
103702 
103703 #define VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_MASK (0xF00000U)
103704 #define VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_SHIFT (20U)
103705 /*! SW_DEC_COMP_TABLE_SWAP - Byte swap configuration for compress table data */
103706 #define VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_SHIFT)) & VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_MASK)
103707 
103708 #define VPU_G2_SWREG3_SW_DEC_MODE_MASK           (0xF8000000U)
103709 #define VPU_G2_SWREG3_SW_DEC_MODE_SHIFT          (27U)
103710 /*! SW_DEC_MODE - Decoding mode:
103711  *  0b00000-0b01011..Reserved
103712  *  0b01100..HEVC
103713  *  0b01101..VP9
103714  *  0b01110-0b11111..Reserved
103715  */
103716 #define VPU_G2_SWREG3_SW_DEC_MODE(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_MODE_SHIFT)) & VPU_G2_SWREG3_SW_DEC_MODE_MASK)
103717 /*! @} */
103718 
103719 /*! @name SWREG4 - Decoder control register 1 */
103720 /*! @{ */
103721 
103722 #define VPU_G2_SWREG4_SW_REF_FRAMES_MASK         (0x1FU)
103723 #define VPU_G2_SWREG4_SW_REF_FRAMES_SHIFT        (0U)
103724 /*! SW_REF_FRAMES - HEVC: num_ref_frames maximum number of short and long term reference frames in decoded picture buffer */
103725 #define VPU_G2_SWREG4_SW_REF_FRAMES(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG4_SW_REF_FRAMES_SHIFT)) & VPU_G2_SWREG4_SW_REF_FRAMES_MASK)
103726 
103727 #define VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_MASK  (0x7FFC0U)
103728 #define VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_SHIFT (6U)
103729 /*! SW_PIC_HEIGHT_IN_CBS - Picture height in min coded blocks (min = 8pix) */
103730 #define VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_SHIFT)) & VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_MASK)
103731 
103732 #define VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_MASK   (0xFFF80000U)
103733 #define VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_SHIFT  (19U)
103734 /*! SW_PIC_WIDTH_IN_CBS - Picture width in min coded blocks (min = 8pix) */
103735 #define VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_SHIFT)) & VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_MASK)
103736 /*! @} */
103737 
103738 /*! @name SWREG5 - Decoder control register 2 */
103739 /*! @{ */
103740 
103741 #define VPU_G2_SWREG5_SW_CU_QPD_E_MASK           (0x10U)
103742 #define VPU_G2_SWREG5_SW_CU_QPD_E_SHIFT          (4U)
103743 /*! SW_CU_QPD_E - CU qp delta enable */
103744 #define VPU_G2_SWREG5_SW_CU_QPD_E(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_CU_QPD_E_SHIFT)) & VPU_G2_SWREG5_SW_CU_QPD_E_MASK)
103745 
103746 #define VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_MASK   (0x7E0U)
103747 #define VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_SHIFT  (5U)
103748 /*! SW_MAX_CU_QPD_DEPTH - Max CU qp delta depth */
103749 #define VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_SHIFT)) & VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_MASK)
103750 
103751 #define VPU_G2_SWREG5_SW_TEMPOR_MVP_E_MASK       (0x800U)
103752 #define VPU_G2_SWREG5_SW_TEMPOR_MVP_E_SHIFT      (11U)
103753 /*! SW_TEMPOR_MVP_E - Temporal mvp enable */
103754 #define VPU_G2_SWREG5_SW_TEMPOR_MVP_E(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_TEMPOR_MVP_E_SHIFT)) & VPU_G2_SWREG5_SW_TEMPOR_MVP_E_MASK)
103755 
103756 #define VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_MASK     (0x1000U)
103757 #define VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_SHIFT    (12U)
103758 /*! SW_SIGN_DATA_HIDE - Flag for stream decoding */
103759 #define VPU_G2_SWREG5_SW_SIGN_DATA_HIDE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_SHIFT)) & VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_MASK)
103760 
103761 #define VPU_G2_SWREG5_SW_CH_QP_OFFSET2_MASK      (0x7C000U)
103762 #define VPU_G2_SWREG5_SW_CH_QP_OFFSET2_SHIFT     (14U)
103763 /*! SW_CH_QP_OFFSET2 - Chroma Qp filter offset for cr type */
103764 #define VPU_G2_SWREG5_SW_CH_QP_OFFSET2(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_CH_QP_OFFSET2_SHIFT)) & VPU_G2_SWREG5_SW_CH_QP_OFFSET2_MASK)
103765 
103766 #define VPU_G2_SWREG5_SW_CH_QP_OFFSET_MASK       (0xF80000U)
103767 #define VPU_G2_SWREG5_SW_CH_QP_OFFSET_SHIFT      (19U)
103768 /*! SW_CH_QP_OFFSET - Chroma Qp filter offset. (For HEVC this offset concerns Cb only) */
103769 #define VPU_G2_SWREG5_SW_CH_QP_OFFSET(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_CH_QP_OFFSET_SHIFT)) & VPU_G2_SWREG5_SW_CH_QP_OFFSET_MASK)
103770 
103771 #define VPU_G2_SWREG5_SW_SCALING_LIST_E_MASK     (0x1000000U)
103772 #define VPU_G2_SWREG5_SW_SCALING_LIST_E_SHIFT    (24U)
103773 /*! SW_SCALING_LIST_E - Scaling matrix enable
103774  *  0b0..Normal transform
103775  *  0b1..Use scaling matrix for transform (read from external memory)
103776  */
103777 #define VPU_G2_SWREG5_SW_SCALING_LIST_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_SCALING_LIST_E_SHIFT)) & VPU_G2_SWREG5_SW_SCALING_LIST_E_MASK)
103778 
103779 #define VPU_G2_SWREG5_SW_STRM_START_BIT_MASK     (0xFE000000U)
103780 #define VPU_G2_SWREG5_SW_STRM_START_BIT_SHIFT    (25U)
103781 /*! SW_STRM_START_BIT - Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base) */
103782 #define VPU_G2_SWREG5_SW_STRM_START_BIT(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_STRM_START_BIT_SHIFT)) & VPU_G2_SWREG5_SW_STRM_START_BIT_MASK)
103783 /*! @} */
103784 
103785 /*! @name SWREG6 - Decoder control register 3 */
103786 /*! @{ */
103787 
103788 #define VPU_G2_SWREG6_SW_STREAM_LEN_MASK         (0xFFFFFFFFU)
103789 #define VPU_G2_SWREG6_SW_STREAM_LEN_SHIFT        (0U)
103790 /*! SW_STREAM_LEN - Amount of stream data bytes in input buffer. If the given buffer size is not
103791  *    enough for finishing the picture the corresponding interrupt is given and new stream buffer base
103792  *    address and stream buffer size information should be given (assosiates with sw_rlc_vlc_base).
103793  *    For HEVC the buffer must include at least data for one slice/VP of the picture
103794  */
103795 #define VPU_G2_SWREG6_SW_STREAM_LEN(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG6_SW_STREAM_LEN_SHIFT)) & VPU_G2_SWREG6_SW_STREAM_LEN_MASK)
103796 /*! @} */
103797 
103798 /*! @name SWREG7 - Decoder control register 4 */
103799 /*! @{ */
103800 
103801 #define VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_MASK    (0x38U)
103802 #define VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_SHIFT   (3U)
103803 /*! SW_SLICE_HDR_EBITS - Number of extra slice header bits (if enabled slice header extension) */
103804 #define VPU_G2_SWREG7_SW_SLICE_HDR_EBITS(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_SHIFT)) & VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_MASK)
103805 
103806 #define VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_MASK    (0x40U)
103807 #define VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_SHIFT   (6U)
103808 /*! SW_SLICE_HDR_EXT_E - Slice header extension enable. Reserved for future use */
103809 #define VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_SHIFT)) & VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_MASK)
103810 
103811 #define VPU_G2_SWREG7_SW_FILT_OFFSET_TC_MASK     (0xF80U)
103812 #define VPU_G2_SWREG7_SW_FILT_OFFSET_TC_SHIFT    (7U)
103813 /*! SW_FILT_OFFSET_TC - Filter tc offset (declared as div2) */
103814 #define VPU_G2_SWREG7_SW_FILT_OFFSET_TC(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_OFFSET_TC_SHIFT)) & VPU_G2_SWREG7_SW_FILT_OFFSET_TC_MASK)
103815 
103816 #define VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_MASK   (0x1F000U)
103817 #define VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_SHIFT  (12U)
103818 /*! SW_FILT_OFFSET_BETA - Filter beta offset (declared as div2) */
103819 #define VPU_G2_SWREG7_SW_FILT_OFFSET_BETA(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_SHIFT)) & VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_MASK)
103820 
103821 #define VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_MASK    (0x20000U)
103822 #define VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_SHIFT   (17U)
103823 /*! SW_STRONG_SMOOTH_E - Strong smoothing enable */
103824 #define VPU_G2_SWREG7_SW_STRONG_SMOOTH_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_SHIFT)) & VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_MASK)
103825 
103826 #define VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_MASK    (0x40000U)
103827 #define VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_SHIFT   (18U)
103828 /*! SW_FILT_OVERRIDE_E - Filter override enable */
103829 #define VPU_G2_SWREG7_SW_FILT_OVERRIDE_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_SHIFT)) & VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_MASK)
103830 
103831 #define VPU_G2_SWREG7_SW_DEPEND_SLICE_E_MASK     (0x80000U)
103832 #define VPU_G2_SWREG7_SW_DEPEND_SLICE_E_SHIFT    (19U)
103833 /*! SW_DEPEND_SLICE_E - Dependent slice enable */
103834 #define VPU_G2_SWREG7_SW_DEPEND_SLICE_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_DEPEND_SLICE_E_SHIFT)) & VPU_G2_SWREG7_SW_DEPEND_SLICE_E_MASK)
103835 
103836 #define VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_MASK    (0x100000U)
103837 #define VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_SHIFT   (20U)
103838 /*! SW_SLICE_CHQP_FLAG - Slice header flag for chroma QP present (if it is included in slice header) */
103839 #define VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_SHIFT)) & VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_MASK)
103840 
103841 #define VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_MASK   (0x200000U)
103842 #define VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_SHIFT  (21U)
103843 /*! SW_PCM_FILT_DISABLE - Disable for PCM loop filtering */
103844 #define VPU_G2_SWREG7_SW_PCM_FILT_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_SHIFT)) & VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_MASK)
103845 
103846 #define VPU_G2_SWREG7_SW_SAO_E_MASK              (0x400000U)
103847 #define VPU_G2_SWREG7_SW_SAO_E_SHIFT             (22U)
103848 /*! SW_SAO_E - Sample Adaptive Offset enable for stream decoding */
103849 #define VPU_G2_SWREG7_SW_SAO_E(x)                (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SAO_E_SHIFT)) & VPU_G2_SWREG7_SW_SAO_E_MASK)
103850 
103851 #define VPU_G2_SWREG7_SW_ASYM_PRED_E_MASK        (0x800000U)
103852 #define VPU_G2_SWREG7_SW_ASYM_PRED_E_SHIFT       (23U)
103853 /*! SW_ASYM_PRED_E - Asymmetric prediction flag for stream decoding */
103854 #define VPU_G2_SWREG7_SW_ASYM_PRED_E(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_ASYM_PRED_E_SHIFT)) & VPU_G2_SWREG7_SW_ASYM_PRED_E_MASK)
103855 
103856 #define VPU_G2_SWREG7_SW_FILT_TILE_BORDER_MASK   (0x1000000U)
103857 #define VPU_G2_SWREG7_SW_FILT_TILE_BORDER_SHIFT  (24U)
103858 /*! SW_FILT_TILE_BORDER - Filter enable over tile border */
103859 #define VPU_G2_SWREG7_SW_FILT_TILE_BORDER(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_TILE_BORDER_SHIFT)) & VPU_G2_SWREG7_SW_FILT_TILE_BORDER_MASK)
103860 
103861 #define VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_MASK  (0x2000000U)
103862 #define VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_SHIFT (25U)
103863 /*! SW_FILT_SLICE_BORDER - Filter enable over slice border */
103864 #define VPU_G2_SWREG7_SW_FILT_SLICE_BORDER(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_SHIFT)) & VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_MASK)
103865 
103866 #define VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_MASK    (0xC000000U)
103867 #define VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT   (26U)
103868 /*! SW_WEIGHT_BIPR_IDC - Weighted prediction specification
103869  *  0b00..Default weighted prediction is applied to B slices
103870  *  0b01..Explicit weighted prediction shall be applied to B slices
103871  *  0b10..NA
103872  *  0b11..NA
103873  */
103874 #define VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT)) & VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_MASK)
103875 
103876 #define VPU_G2_SWREG7_SW_WEIGHT_PRED_E_MASK      (0x10000000U)
103877 #define VPU_G2_SWREG7_SW_WEIGHT_PRED_E_SHIFT     (28U)
103878 /*! SW_WEIGHT_PRED_E - Weighted prediction enable for P slices */
103879 #define VPU_G2_SWREG7_SW_WEIGHT_PRED_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_WEIGHT_PRED_E_SHIFT)) & VPU_G2_SWREG7_SW_WEIGHT_PRED_E_MASK)
103880 
103881 #define VPU_G2_SWREG7_SW_BLACKWHITE_E_MASK       (0x40000000U)
103882 #define VPU_G2_SWREG7_SW_BLACKWHITE_E_SHIFT      (30U)
103883 /*! SW_BLACKWHITE_E - Sampling
103884  *  0b0..4:2:0 sampling format
103885  *  0b1..4:0:0 sampling format (H264 monochroma)
103886  */
103887 #define VPU_G2_SWREG7_SW_BLACKWHITE_E(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_BLACKWHITE_E_SHIFT)) & VPU_G2_SWREG7_SW_BLACKWHITE_E_MASK)
103888 
103889 #define VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_MASK (0x80000000U)
103890 #define VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_SHIFT (31U)
103891 /*! SW_CABAC_INIT_PRESENT - CABAC init present enable for stream decoding */
103892 #define VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_SHIFT)) & VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_MASK)
103893 /*! @} */
103894 
103895 /*! @name SWREG8 - Decoder control register 5 */
103896 /*! @{ */
103897 
103898 #define VPU_G2_SWREG8_SW_OUTPUT_FORMAT_MASK      (0x7U)
103899 #define VPU_G2_SWREG8_SW_OUTPUT_FORMAT_SHIFT     (0U)
103900 /*! SW_OUTPUT_FORMAT - Raster scan and down scale output data format
103901  *  0b000..Each pixel in 10 bits when luma or chroma pixel bit depth is larger than 8; or 8 bits when both luma
103902  *         and chroma pixel bit depth are 8 bits. (default)
103903  *  0b001..Store in P010 format when luma or chroma pixel bit depth is larger than 8.
103904  *  0b010..A customized format: please refer to register SWREG23[6].
103905  */
103906 #define VPU_G2_SWREG8_SW_OUTPUT_FORMAT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_OUTPUT_FORMAT_SHIFT)) & VPU_G2_SWREG8_SW_OUTPUT_FORMAT_MASK)
103907 
103908 #define VPU_G2_SWREG8_SW_OUTPUT_8_BITS_MASK      (0x8U)
103909 #define VPU_G2_SWREG8_SW_OUTPUT_8_BITS_SHIFT     (3U)
103910 /*! SW_OUTPUT_8_BITS - enable rasterscan output force to 8 bit(only for hevc main10 and vp9 10bit) */
103911 #define VPU_G2_SWREG8_SW_OUTPUT_8_BITS(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_OUTPUT_8_BITS_SHIFT)) & VPU_G2_SWREG8_SW_OUTPUT_8_BITS_MASK)
103912 
103913 #define VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_MASK (0x30U)
103914 #define VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_SHIFT (4U)
103915 /*! SW_BIT_DEPTH_C_MINUS8 - Bit depth of chroma samples minus 8 */
103916 #define VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_SHIFT)) & VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_MASK)
103917 
103918 #define VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_MASK (0xC0U)
103919 #define VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_SHIFT (6U)
103920 /*! SW_BIT_DEPTH_Y_MINUS8 - Bit depth of luma samples minus 8 */
103921 #define VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_SHIFT)) & VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_MASK)
103922 
103923 #define VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_MASK     (0xF00U)
103924 #define VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_SHIFT    (8U)
103925 /*! SW_PCM_BITDEPTH_C - Bit depth for PCM C data */
103926 #define VPU_G2_SWREG8_SW_PCM_BITDEPTH_C(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_SHIFT)) & VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_MASK)
103927 
103928 #define VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_MASK     (0xF000U)
103929 #define VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_SHIFT    (12U)
103930 /*! SW_PCM_BITDEPTH_Y - Bit depth for PCM Y data */
103931 #define VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_SHIFT)) & VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_MASK)
103932 
103933 #define VPU_G2_SWREG8_SW_IDR_PIC_E_MASK          (0x10000U)
103934 #define VPU_G2_SWREG8_SW_IDR_PIC_E_SHIFT         (16U)
103935 /*! SW_IDR_PIC_E - IDR (instantaneous decoding refresh) picture flag. */
103936 #define VPU_G2_SWREG8_SW_IDR_PIC_E(x)            (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_IDR_PIC_E_SHIFT)) & VPU_G2_SWREG8_SW_IDR_PIC_E_MASK)
103937 
103938 #define VPU_G2_SWREG8_SW_FILT_CTRL_PRES_MASK     (0x40000000U)
103939 #define VPU_G2_SWREG8_SW_FILT_CTRL_PRES_SHIFT    (30U)
103940 /*! SW_FILT_CTRL_PRES - deblocking_filter_control_present_flag indicates whether extra variables
103941  *    controlling characteristics of the deblocking filter are present in the slice header.
103942  */
103943 #define VPU_G2_SWREG8_SW_FILT_CTRL_PRES(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_FILT_CTRL_PRES_SHIFT)) & VPU_G2_SWREG8_SW_FILT_CTRL_PRES_MASK)
103944 
103945 #define VPU_G2_SWREG8_SW_CONST_INTRA_E_MASK      (0x80000000U)
103946 #define VPU_G2_SWREG8_SW_CONST_INTRA_E_SHIFT     (31U)
103947 /*! SW_CONST_INTRA_E - constrained_intra_pred_flag equal to 1 specifies that intra prediction uses
103948  *    only neighbouring intra macroblocks in prediction. When equal to 0 also neighbouring inter
103949  *    macroblocks are used in intra prediction process.
103950  */
103951 #define VPU_G2_SWREG8_SW_CONST_INTRA_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_CONST_INTRA_E_SHIFT)) & VPU_G2_SWREG8_SW_CONST_INTRA_E_MASK)
103952 /*! @} */
103953 
103954 /*! @name SWREG9 - Decoder control register 6 */
103955 /*! @{ */
103956 
103957 #define VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_MASK    (0x3FFFU)
103958 #define VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_SHIFT   (0U)
103959 /*! SW_HDR_SKIP_LENGTH - Length of slice header skip length (bytes used by sw) */
103960 #define VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_SHIFT)) & VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_MASK)
103961 
103962 #define VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_MASK     (0x7C000U)
103963 #define VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_SHIFT    (14U)
103964 /*! SW_REFIDX0_ACTIVE - Specifies the maximum reference index that can be used while decoding inter
103965  *    predicted macro blocks. This is same as in previous decoders (width increased with q bit)
103966  */
103967 #define VPU_G2_SWREG9_SW_REFIDX0_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_SHIFT)) & VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_MASK)
103968 
103969 #define VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_MASK     (0xF80000U)
103970 #define VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_SHIFT    (19U)
103971 /*! SW_REFIDX1_ACTIVE - Specifies the maximum reference index that can be used while decoding inter predicted macro blocks. */
103972 #define VPU_G2_SWREG9_SW_REFIDX1_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_SHIFT)) & VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_MASK)
103973 /*! @} */
103974 
103975 /*! @name SWREG10 - Decoder control register 7 */
103976 /*! @{ */
103977 
103978 #define VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_MASK (0x1U)
103979 #define VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_SHIFT (0U)
103980 /*! SW_ENTR_CODE_SYNCH_E - Entropy coding synchronization enable (Possible parallel cabac decoding) */
103981 #define VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_SHIFT)) & VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_MASK)
103982 
103983 #define VPU_G2_SWREG10_SW_TILE_ENABLE_MASK       (0x2U)
103984 #define VPU_G2_SWREG10_SW_TILE_ENABLE_SHIFT      (1U)
103985 /*! SW_TILE_ENABLE - Tile enable */
103986 #define VPU_G2_SWREG10_SW_TILE_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_TILE_ENABLE_SHIFT)) & VPU_G2_SWREG10_SW_TILE_ENABLE_MASK)
103987 
103988 #define VPU_G2_SWREG10_SW_NUM_TILE_ROWS_MASK     (0x7C000U)
103989 #define VPU_G2_SWREG10_SW_NUM_TILE_ROWS_SHIFT    (14U)
103990 /*! SW_NUM_TILE_ROWS - Number of tile rows in picture */
103991 #define VPU_G2_SWREG10_SW_NUM_TILE_ROWS(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_NUM_TILE_ROWS_SHIFT)) & VPU_G2_SWREG10_SW_NUM_TILE_ROWS_MASK)
103992 
103993 #define VPU_G2_SWREG10_SW_NUM_TILE_COLS_MASK     (0xF80000U)
103994 #define VPU_G2_SWREG10_SW_NUM_TILE_COLS_SHIFT    (19U)
103995 /*! SW_NUM_TILE_COLS - Number of tile columns in picture */
103996 #define VPU_G2_SWREG10_SW_NUM_TILE_COLS(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_NUM_TILE_COLS_SHIFT)) & VPU_G2_SWREG10_SW_NUM_TILE_COLS_MASK)
103997 
103998 #define VPU_G2_SWREG10_SW_INIT_QP_MASK           (0x7F000000U)
103999 #define VPU_G2_SWREG10_SW_INIT_QP_SHIFT          (24U)
104000 /*! SW_INIT_QP - Initial value for quantization parameter (picture quantizer). */
104001 #define VPU_G2_SWREG10_SW_INIT_QP(x)             (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_INIT_QP_SHIFT)) & VPU_G2_SWREG10_SW_INIT_QP_MASK)
104002 
104003 #define VPU_G2_SWREG10_SW_START_CODE_E_MASK      (0x80000000U)
104004 #define VPU_G2_SWREG10_SW_START_CODE_E_SHIFT     (31U)
104005 /*! SW_START_CODE_E - Bit for indicating stream start code existence
104006  *  0b0..Stream does not contain start codes
104007  *  0b1..Stream contains start codes
104008  */
104009 #define VPU_G2_SWREG10_SW_START_CODE_E(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_START_CODE_E_SHIFT)) & VPU_G2_SWREG10_SW_START_CODE_E_MASK)
104010 /*! @} */
104011 
104012 /*! @name SWREG11 - Decoder control register 8 */
104013 /*! @{ */
104014 
104015 #define VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_MASK    (0x1U)
104016 #define VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_SHIFT   (0U)
104017 /*! SW_AREF_SIGN_BIAS - Alternate reference picture sign bias used for motion vector decoding */
104018 #define VPU_G2_SWREG11_SW_AREF_SIGN_BIAS(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_SHIFT)) & VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_MASK)
104019 
104020 #define VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_MASK    (0x4U)
104021 #define VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_SHIFT   (2U)
104022 /*! SW_GREF_SIGN_BIAS - Golden reference picture sign bias used for motion vector decoding */
104023 #define VPU_G2_SWREG11_SW_GREF_SIGN_BIAS(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_SHIFT)) & VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_MASK)
104024 
104025 #define VPU_G2_SWREG11_SW_COMP_PRED_MODE_MASK    (0x30U)
104026 #define VPU_G2_SWREG11_SW_COMP_PRED_MODE_SHIFT   (4U)
104027 /*! SW_COMP_PRED_MODE - Prediction Comp Type
104028  *  0b00..Single prediction only
104029  *  0b01..COMP prediction only
104030  *  0b10..Hybrid prediction
104031  */
104032 #define VPU_G2_SWREG11_SW_COMP_PRED_MODE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_COMP_PRED_MODE_SHIFT)) & VPU_G2_SWREG11_SW_COMP_PRED_MODE_MASK)
104033 
104034 #define VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_MASK    (0x80U)
104035 #define VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_SHIFT   (7U)
104036 /*! SW_HIGH_PREC_MV_E - High precision MV prediction enable */
104037 #define VPU_G2_SWREG11_SW_HIGH_PREC_MV_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_SHIFT)) & VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_MASK)
104038 
104039 #define VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_MASK   (0x700U)
104040 #define VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_SHIFT  (8U)
104041 /*! SW_MCOMP_FILT_TYPE - Inter prediction filter type to stream decoder
104042  *  0b000..Eight tap smooth
104043  *  0b001..Eight tap
104044  *  0b010..Eight tap sharp
104045  *  0b011..Bilinear
104046  *  0b100..Switchable
104047  */
104048 #define VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_SHIFT)) & VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_MASK)
104049 
104050 #define VPU_G2_SWREG11_SW_FILT_TYPE_MASK         (0x80000U)
104051 #define VPU_G2_SWREG11_SW_FILT_TYPE_SHIFT        (19U)
104052 /*! SW_FILT_TYPE - Filter Type */
104053 #define VPU_G2_SWREG11_SW_FILT_TYPE(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_FILT_TYPE_SHIFT)) & VPU_G2_SWREG11_SW_FILT_TYPE_MASK)
104054 
104055 #define VPU_G2_SWREG11_SW_FILT_SHARPNESS_MASK    (0xE00000U)
104056 #define VPU_G2_SWREG11_SW_FILT_SHARPNESS_SHIFT   (21U)
104057 /*! SW_FILT_SHARPNESS - Filter sharpness value */
104058 #define VPU_G2_SWREG11_SW_FILT_SHARPNESS(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_FILT_SHARPNESS_SHIFT)) & VPU_G2_SWREG11_SW_FILT_SHARPNESS_MASK)
104059 
104060 #define VPU_G2_SWREG11_SW_TRANSFORM_MODE_MASK    (0x38000000U)
104061 #define VPU_G2_SWREG11_SW_TRANSFORM_MODE_SHIFT   (27U)
104062 /*! SW_TRANSFORM_MODE - Transform modes
104063  *  0b000..4x4 only
104064  *  0b001..Allow 8x8
104065  *  0b010..Allow 16x16
104066  *  0b011..Allow 32x32
104067  *  0b100..TX mode select
104068  */
104069 #define VPU_G2_SWREG11_SW_TRANSFORM_MODE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_TRANSFORM_MODE_SHIFT)) & VPU_G2_SWREG11_SW_TRANSFORM_MODE_MASK)
104070 /*! @} */
104071 
104072 /*! @name SWREG12 - Decoder control register 9 */
104073 /*! @{ */
104074 
104075 #define VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_MASK  (0x1U)
104076 #define VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_SHIFT (0U)
104077 /*! SW_REFPICLIST_MOD_E - Refpic list reordering flag */
104078 #define VPU_G2_SWREG12_SW_REFPICLIST_MOD_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_SHIFT)) & VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_MASK)
104079 
104080 #define VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_MASK   (0x2U)
104081 #define VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_SHIFT  (1U)
104082 /*! SW_TRANSQ_BYPASS_E - Transform bypass flag (lossless mode) */
104083 #define VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_SHIFT)) & VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_MASK)
104084 
104085 #define VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_MASK  (0x4U)
104086 #define VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_SHIFT (2U)
104087 /*! SW_TRANSFORM_SKIP_E - Transform skipping flag */
104088 #define VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_SHIFT)) & VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_MASK)
104089 
104090 #define VPU_G2_SWREG12_SW_PCM_E_MASK             (0x8U)
104091 #define VPU_G2_SWREG12_SW_PCM_E_SHIFT            (3U)
104092 /*! SW_PCM_E - IPCM MBs flag */
104093 #define VPU_G2_SWREG12_SW_PCM_E(x)               (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_PCM_E_SHIFT)) & VPU_G2_SWREG12_SW_PCM_E_MASK)
104094 
104095 #define VPU_G2_SWREG12_SW_MAX_PCM_SIZE_MASK      (0x70U)
104096 #define VPU_G2_SWREG12_SW_MAX_PCM_SIZE_SHIFT     (4U)
104097 /*! SW_MAX_PCM_SIZE - PCM max size (2^N):
104098  *  0b011..8 pix
104099  *  0b100..16 pix
104100  *  0b101..32 pix
104101  *  0b110..64 pix
104102  */
104103 #define VPU_G2_SWREG12_SW_MAX_PCM_SIZE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MAX_PCM_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MAX_PCM_SIZE_MASK)
104104 
104105 #define VPU_G2_SWREG12_SW_MIN_PCM_SIZE_MASK      (0x380U)
104106 #define VPU_G2_SWREG12_SW_MIN_PCM_SIZE_SHIFT     (7U)
104107 /*! SW_MIN_PCM_SIZE - PCM min size (2^N):
104108  *  0b011..8 pix
104109  *  0b100..16 pix
104110  *  0b101..32 pix
104111  *  0b110..64 pix
104112  */
104113 #define VPU_G2_SWREG12_SW_MIN_PCM_SIZE(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MIN_PCM_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MIN_PCM_SIZE_MASK)
104114 
104115 #define VPU_G2_SWREG12_SW_MAX_CB_SIZE_MASK       (0x1C00U)
104116 #define VPU_G2_SWREG12_SW_MAX_CB_SIZE_SHIFT      (10U)
104117 /*! SW_MAX_CB_SIZE - CodedBlock max size (2^N):
104118  *  0b011..8 pix
104119  *  0b100..16 pix
104120  *  0b101..32 pix
104121  *  0b110..64 pix
104122  */
104123 #define VPU_G2_SWREG12_SW_MAX_CB_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MAX_CB_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MAX_CB_SIZE_MASK)
104124 
104125 #define VPU_G2_SWREG12_SW_MIN_CB_SIZE_MASK       (0xE000U)
104126 #define VPU_G2_SWREG12_SW_MIN_CB_SIZE_SHIFT      (13U)
104127 /*! SW_MIN_CB_SIZE - CodedBlock min size (2^N):
104128  *  0b011..8 pix
104129  *  0b100..16 pix
104130  *  0b101..32 pix
104131  *  0b110..64 pix
104132  */
104133 #define VPU_G2_SWREG12_SW_MIN_CB_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MIN_CB_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MIN_CB_SIZE_MASK)
104134 
104135 #define VPU_G2_SWREG12_SW_REFER_LTERM_E_MASK     (0xFFFF0000U)
104136 #define VPU_G2_SWREG12_SW_REFER_LTERM_E_SHIFT    (16U)
104137 /*! SW_REFER_LTERM_E - Long term flag for reference picture index Definition: Bit 31 for picture index 0 Bit 30 for picture index 1 etc. */
104138 #define VPU_G2_SWREG12_SW_REFER_LTERM_E(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_REFER_LTERM_E_SHIFT)) & VPU_G2_SWREG12_SW_REFER_LTERM_E_MASK)
104139 /*! @} */
104140 
104141 /*! @name SWREG13 - Decoder control register 10 */
104142 /*! @{ */
104143 
104144 #define VPU_G2_SWREG13_DEC_CTRL_REG10_BF_MASK    (0x1FFFFFFFU)
104145 #define VPU_G2_SWREG13_DEC_CTRL_REG10_BF_SHIFT   (0U)
104146 #define VPU_G2_SWREG13_DEC_CTRL_REG10_BF(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG13_DEC_CTRL_REG10_BF_SHIFT)) & VPU_G2_SWREG13_DEC_CTRL_REG10_BF_MASK)
104147 /*! @} */
104148 
104149 /*! @name SWREG14 - Initial ref pic list register (0-2) */
104150 /*! @{ */
104151 
104152 #define VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_MASK  (0xFFFFFFFFU)
104153 #define VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_SHIFT (0U)
104154 #define VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_SHIFT)) & VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_MASK)
104155 /*! @} */
104156 
104157 /*! @name SWREG15 - Initial ref pic list register (3-5) */
104158 /*! @{ */
104159 
104160 #define VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_MASK  (0xFFFFFFFFU)
104161 #define VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_SHIFT (0U)
104162 #define VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_SHIFT)) & VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_MASK)
104163 /*! @} */
104164 
104165 /*! @name SWREG16 - Initial ref pic list register (6-8) */
104166 /*! @{ */
104167 
104168 #define VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_MASK  (0xFFFFFFFFU)
104169 #define VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_SHIFT (0U)
104170 #define VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_SHIFT)) & VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_MASK)
104171 /*! @} */
104172 
104173 /*! @name SWREG17 - Initial ref pic list register (9-11) */
104174 /*! @{ */
104175 
104176 #define VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_MASK (0xFFFFFFFFU)
104177 #define VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_SHIFT (0U)
104178 #define VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_SHIFT)) & VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_MASK)
104179 /*! @} */
104180 
104181 /*! @name SWREG18 - Initial ref pic list register (12-14) */
104182 /*! @{ */
104183 
104184 #define VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_MASK (0xFFFFFFFFU)
104185 #define VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_SHIFT (0U)
104186 #define VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_SHIFT)) & VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_MASK)
104187 /*! @} */
104188 
104189 /*! @name SWREG19 - Initial ref pic list register (15 and P 0-3) */
104190 /*! @{ */
104191 
104192 #define VPU_G2_SWREG19_INIT_REF_PIC_15_BF_MASK   (0xFFFFFFFFU)
104193 #define VPU_G2_SWREG19_INIT_REF_PIC_15_BF_SHIFT  (0U)
104194 #define VPU_G2_SWREG19_INIT_REF_PIC_15_BF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG19_INIT_REF_PIC_15_BF_SHIFT)) & VPU_G2_SWREG19_INIT_REF_PIC_15_BF_MASK)
104195 /*! @} */
104196 
104197 /*! @name SWREG20 - Decoder control register 11 */
104198 /*! @{ */
104199 
104200 #define VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_MASK    (0xFFFU)
104201 #define VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_SHIFT   (0U)
104202 /*! SW_PIC_HEIGHT_4X4 - Current picture height in 4x4 blocks (Needed to reduce overlapping HW conditions in various blocks) */
104203 #define VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_SHIFT)) & VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_MASK)
104204 
104205 #define VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_MASK     (0xFFF0000U)
104206 #define VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_SHIFT    (16U)
104207 /*! SW_PIC_WIDTH_4X4 - Current picture width in 4x4 blocks (Needed to reduce overlapping HW conditions in various blocks) */
104208 #define VPU_G2_SWREG20_SW_PIC_WIDTH_4X4(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_SHIFT)) & VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_MASK)
104209 
104210 #define VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_MASK     (0x40000000U)
104211 #define VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_SHIFT    (30U)
104212 /*! SW_PARTIAL_CTB_Y - Picture height not multiple of CTB size */
104213 #define VPU_G2_SWREG20_SW_PARTIAL_CTB_Y(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_SHIFT)) & VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_MASK)
104214 
104215 #define VPU_G2_SWREG20_SW_PARTIAL_CTB_X_MASK     (0x80000000U)
104216 #define VPU_G2_SWREG20_SW_PARTIAL_CTB_X_SHIFT    (31U)
104217 /*! SW_PARTIAL_CTB_X - Picture width not multiple of CTB size */
104218 #define VPU_G2_SWREG20_SW_PARTIAL_CTB_X(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PARTIAL_CTB_X_SHIFT)) & VPU_G2_SWREG20_SW_PARTIAL_CTB_X_MASK)
104219 /*! @} */
104220 
104221 /*! @name SWREG23 - Decoder configure status register */
104222 /*! @{ */
104223 
104224 #define VPU_G2_SWREG23_SW_HEVC_SUPPORT_MASK      (0x1U)
104225 #define VPU_G2_SWREG23_SW_HEVC_SUPPORT_SHIFT     (0U)
104226 /*! SW_HEVC_SUPPORT - HEVC support
104227  *  0b0..Do not support HEVC
104228  *  0b1..Support HEVC
104229  */
104230 #define VPU_G2_SWREG23_SW_HEVC_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_HEVC_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_HEVC_SUPPORT_MASK)
104231 
104232 #define VPU_G2_SWREG23_SW_VP9_SUPPORT_MASK       (0x2U)
104233 #define VPU_G2_SWREG23_SW_VP9_SUPPORT_SHIFT      (1U)
104234 /*! SW_VP9_SUPPORT - VP9 support
104235  *  0b0..Do not support VP9
104236  *  0b1..Support VP9
104237  */
104238 #define VPU_G2_SWREG23_SW_VP9_SUPPORT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_VP9_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_VP9_SUPPORT_MASK)
104239 
104240 #define VPU_G2_SWREG23_SW_RFC_SUPPORT_MASK       (0x4U)
104241 #define VPU_G2_SWREG23_SW_RFC_SUPPORT_SHIFT      (2U)
104242 /*! SW_RFC_SUPPORT - RFC support
104243  *  0b0..Do not support RFC
104244  *  0b1..Support RFC
104245  */
104246 #define VPU_G2_SWREG23_SW_RFC_SUPPORT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_RFC_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_RFC_SUPPORT_MASK)
104247 
104248 #define VPU_G2_SWREG23_SW_DOWN_SUPPORT_MASK      (0x8U)
104249 #define VPU_G2_SWREG23_SW_DOWN_SUPPORT_SHIFT     (3U)
104250 /*! SW_DOWN_SUPPORT - Downscale support
104251  *  0b0..Do not support downscale
104252  *  0b1..Support downscale
104253  */
104254 #define VPU_G2_SWREG23_SW_DOWN_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DOWN_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_DOWN_SUPPORT_MASK)
104255 
104256 #define VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_MASK    (0x10U)
104257 #define VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_SHIFT   (4U)
104258 /*! SW_DEC_64BIT_AD_E - 64 bit addressing of master interface support
104259  *  0b0..Not supported (32 bit addressing)
104260  *  0b1..Supported
104261  */
104262 #define VPU_G2_SWREG23_SW_DEC_64BIT_AD_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_SHIFT)) & VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_MASK)
104263 
104264 #define VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_MASK (0x20U)
104265 #define VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_SHIFT (5U)
104266 /*! SW_DEC_FORMAT_P010_E - P010 output format support
104267  *  0b0..Not supported
104268  *  0b1..Supported
104269  */
104270 #define VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_SHIFT)) & VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_MASK)
104271 
104272 #define VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_MASK (0x40U)
104273 #define VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_SHIFT (6U)
104274 /*! SW_DEC_FORMAT_CUSTOMER1_E - Customized output format support
104275  *  0b0..Not supported
104276  *  0b1..Supported
104277  */
104278 #define VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_SHIFT)) & VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_MASK)
104279 
104280 #define VPU_G2_SWREG23_SW_MULTI_PREFETCH_MASK    (0x80U)
104281 #define VPU_G2_SWREG23_SW_MULTI_PREFETCH_SHIFT   (7U)
104282 /*! SW_MULTI_PREFETCH - Multi-Reference Blocks Prefetch
104283  *  0b0..Not supported
104284  *  0b1..Supported
104285  */
104286 #define VPU_G2_SWREG23_SW_MULTI_PREFETCH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_MULTI_PREFETCH_SHIFT)) & VPU_G2_SWREG23_SW_MULTI_PREFETCH_MASK)
104287 
104288 #define VPU_G2_SWREG23_SW_HEVC_VERSION_MASK      (0xF00U)
104289 #define VPU_G2_SWREG23_SW_HEVC_VERSION_SHIFT     (8U)
104290 /*! SW_HEVC_VERSION - HEVC version
104291  *  0b0000..main8
104292  *  0b0001..main10
104293  */
104294 #define VPU_G2_SWREG23_SW_HEVC_VERSION(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_HEVC_VERSION_SHIFT)) & VPU_G2_SWREG23_SW_HEVC_VERSION_MASK)
104295 
104296 #define VPU_G2_SWREG23_SW_VP9_PROFILE_MASK       (0xF000U)
104297 #define VPU_G2_SWREG23_SW_VP9_PROFILE_SHIFT      (12U)
104298 /*! SW_VP9_PROFILE - VP9 version
104299  *  0b0000..vp9 profile 0
104300  *  0b0001..vp9 profile 2 - 10bits
104301  */
104302 #define VPU_G2_SWREG23_SW_VP9_PROFILE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_VP9_PROFILE_SHIFT)) & VPU_G2_SWREG23_SW_VP9_PROFILE_MASK)
104303 /*! @} */
104304 
104305 /*! @name SWREG31 - VP9 segmentation values */
104306 /*! @{ */
104307 
104308 #define VPU_G2_SWREG31_SW_QUANT_SEG6_MASK        (0xFFU)
104309 #define VPU_G2_SWREG31_SW_QUANT_SEG6_SHIFT       (0U)
104310 /*! SW_QUANT_SEG6 - Segment quantization parameter */
104311 #define VPU_G2_SWREG31_SW_QUANT_SEG6(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_QUANT_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_QUANT_SEG6_MASK)
104312 
104313 #define VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_MASK   (0x3F00U)
104314 #define VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_SHIFT  (8U)
104315 /*! SW_FILT_LEVEL_SEG6 - Segment filter level */
104316 #define VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_MASK)
104317 
104318 #define VPU_G2_SWREG31_SW_SKIP_SEG6_MASK         (0x4000U)
104319 #define VPU_G2_SWREG31_SW_SKIP_SEG6_SHIFT        (14U)
104320 /*! SW_SKIP_SEG6 - Segment skip enable */
104321 #define VPU_G2_SWREG31_SW_SKIP_SEG6(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_SKIP_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_SKIP_SEG6_MASK)
104322 
104323 #define VPU_G2_SWREG31_SW_REFPIC_SEG6_MASK       (0x38000U)
104324 #define VPU_G2_SWREG31_SW_REFPIC_SEG6_SHIFT      (15U)
104325 /*! SW_REFPIC_SEG6 - Segment refer picture */
104326 #define VPU_G2_SWREG31_SW_REFPIC_SEG6(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_REFPIC_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_REFPIC_SEG6_MASK)
104327 /*! @} */
104328 
104329 /*! @name SWREG32 - VP9 segmentation values */
104330 /*! @{ */
104331 
104332 #define VPU_G2_SWREG32_SW_QUANT_SEG7_MASK        (0xFFU)
104333 #define VPU_G2_SWREG32_SW_QUANT_SEG7_SHIFT       (0U)
104334 /*! SW_QUANT_SEG7 - Segment quantization parameter */
104335 #define VPU_G2_SWREG32_SW_QUANT_SEG7(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_QUANT_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_QUANT_SEG7_MASK)
104336 
104337 #define VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_MASK   (0x3F00U)
104338 #define VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_SHIFT  (8U)
104339 /*! SW_FILT_LEVEL_SEG7 - Segment filter level */
104340 #define VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_MASK)
104341 
104342 #define VPU_G2_SWREG32_SW_SKIP_SEG7_MASK         (0x4000U)
104343 #define VPU_G2_SWREG32_SW_SKIP_SEG7_SHIFT        (14U)
104344 /*! SW_SKIP_SEG7 - Segment skip enable */
104345 #define VPU_G2_SWREG32_SW_SKIP_SEG7(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_SKIP_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_SKIP_SEG7_MASK)
104346 
104347 #define VPU_G2_SWREG32_SW_REFPIC_SEG7_MASK       (0x38000U)
104348 #define VPU_G2_SWREG32_SW_REFPIC_SEG7_SHIFT      (15U)
104349 /*! SW_REFPIC_SEG7 - Segment refer picture */
104350 #define VPU_G2_SWREG32_SW_REFPIC_SEG7(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_REFPIC_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_REFPIC_SEG7_MASK)
104351 /*! @} */
104352 
104353 /*! @name SWREG33 - VP9 reference picture scaling register 0 */
104354 /*! @{ */
104355 
104356 #define VPU_G2_SWREG33_SW_LREF_HEIGHT_MASK       (0xFFFFU)
104357 #define VPU_G2_SWREG33_SW_LREF_HEIGHT_SHIFT      (0U)
104358 /*! SW_LREF_HEIGHT - Accurate height of last (previous) reference picture in pixels */
104359 #define VPU_G2_SWREG33_SW_LREF_HEIGHT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG33_SW_LREF_HEIGHT_SHIFT)) & VPU_G2_SWREG33_SW_LREF_HEIGHT_MASK)
104360 
104361 #define VPU_G2_SWREG33_SW_LREF_WIDTH_MASK        (0xFFFF0000U)
104362 #define VPU_G2_SWREG33_SW_LREF_WIDTH_SHIFT       (16U)
104363 /*! SW_LREF_WIDTH - Accurate width of last (previous) reference picture in pixels */
104364 #define VPU_G2_SWREG33_SW_LREF_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG33_SW_LREF_WIDTH_SHIFT)) & VPU_G2_SWREG33_SW_LREF_WIDTH_MASK)
104365 /*! @} */
104366 
104367 /*! @name SWREG34 - VP9 reference picture scaling register 1 */
104368 /*! @{ */
104369 
104370 #define VPU_G2_SWREG34_SW_GREF_HEIGHT_MASK       (0xFFFFU)
104371 #define VPU_G2_SWREG34_SW_GREF_HEIGHT_SHIFT      (0U)
104372 /*! SW_GREF_HEIGHT - Accurate height of golden reference picture in pixels */
104373 #define VPU_G2_SWREG34_SW_GREF_HEIGHT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG34_SW_GREF_HEIGHT_SHIFT)) & VPU_G2_SWREG34_SW_GREF_HEIGHT_MASK)
104374 
104375 #define VPU_G2_SWREG34_SW_GREF_WIDTH_MASK        (0xFFFF0000U)
104376 #define VPU_G2_SWREG34_SW_GREF_WIDTH_SHIFT       (16U)
104377 /*! SW_GREF_WIDTH - Accurate width of golden reference picture in pixels */
104378 #define VPU_G2_SWREG34_SW_GREF_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG34_SW_GREF_WIDTH_SHIFT)) & VPU_G2_SWREG34_SW_GREF_WIDTH_MASK)
104379 /*! @} */
104380 
104381 /*! @name SWREG35 - VP9 reference picture scaling register 2 */
104382 /*! @{ */
104383 
104384 #define VPU_G2_SWREG35_SW_AREF_HEIGHT_MASK       (0xFFFFU)
104385 #define VPU_G2_SWREG35_SW_AREF_HEIGHT_SHIFT      (0U)
104386 /*! SW_AREF_HEIGHT - Accurate height of alternate reference picture in pixels */
104387 #define VPU_G2_SWREG35_SW_AREF_HEIGHT(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG35_SW_AREF_HEIGHT_SHIFT)) & VPU_G2_SWREG35_SW_AREF_HEIGHT_MASK)
104388 
104389 #define VPU_G2_SWREG35_SW_AREF_WIDTH_MASK        (0xFFFF0000U)
104390 #define VPU_G2_SWREG35_SW_AREF_WIDTH_SHIFT       (16U)
104391 /*! SW_AREF_WIDTH - Accurate width of alternate reference picture in pixels */
104392 #define VPU_G2_SWREG35_SW_AREF_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG35_SW_AREF_WIDTH_SHIFT)) & VPU_G2_SWREG35_SW_AREF_WIDTH_MASK)
104393 /*! @} */
104394 
104395 /*! @name SWREG36 - VP9 reference picture scaling register 3 */
104396 /*! @{ */
104397 
104398 #define VPU_G2_SWREG36_SW_LREF_VER_SCALE_MASK    (0xFFFFU)
104399 #define VPU_G2_SWREG36_SW_LREF_VER_SCALE_SHIFT   (0U)
104400 /*! SW_LREF_VER_SCALE - Vertical scaling factor for last (previous) reference picture */
104401 #define VPU_G2_SWREG36_SW_LREF_VER_SCALE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG36_SW_LREF_VER_SCALE_SHIFT)) & VPU_G2_SWREG36_SW_LREF_VER_SCALE_MASK)
104402 
104403 #define VPU_G2_SWREG36_SW_LREF_HOR_SCALE_MASK    (0xFFFF0000U)
104404 #define VPU_G2_SWREG36_SW_LREF_HOR_SCALE_SHIFT   (16U)
104405 /*! SW_LREF_HOR_SCALE - Horizontal scaling factor for last (previous) reference picture */
104406 #define VPU_G2_SWREG36_SW_LREF_HOR_SCALE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG36_SW_LREF_HOR_SCALE_SHIFT)) & VPU_G2_SWREG36_SW_LREF_HOR_SCALE_MASK)
104407 /*! @} */
104408 
104409 /*! @name SWREG37 - VP9 reference picture scaling register 4 */
104410 /*! @{ */
104411 
104412 #define VPU_G2_SWREG37_SW_GREF_VER_SCALE_MASK    (0xFFFFU)
104413 #define VPU_G2_SWREG37_SW_GREF_VER_SCALE_SHIFT   (0U)
104414 /*! SW_GREF_VER_SCALE - Vertical scaling factor for golden reference picture */
104415 #define VPU_G2_SWREG37_SW_GREF_VER_SCALE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG37_SW_GREF_VER_SCALE_SHIFT)) & VPU_G2_SWREG37_SW_GREF_VER_SCALE_MASK)
104416 
104417 #define VPU_G2_SWREG37_SW_GREF_HOR_SCALE_MASK    (0xFFFF0000U)
104418 #define VPU_G2_SWREG37_SW_GREF_HOR_SCALE_SHIFT   (16U)
104419 /*! SW_GREF_HOR_SCALE - Horizontal scaling factor for golden reference picture */
104420 #define VPU_G2_SWREG37_SW_GREF_HOR_SCALE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG37_SW_GREF_HOR_SCALE_SHIFT)) & VPU_G2_SWREG37_SW_GREF_HOR_SCALE_MASK)
104421 /*! @} */
104422 
104423 /*! @name SWREG38 - VP9 reference picture scaling register 5 */
104424 /*! @{ */
104425 
104426 #define VPU_G2_SWREG38_SW_AREF_VER_SCALE_MASK    (0xFFFFU)
104427 #define VPU_G2_SWREG38_SW_AREF_VER_SCALE_SHIFT   (0U)
104428 /*! SW_AREF_VER_SCALE - Vertical scaling factor for alternate reference picture */
104429 #define VPU_G2_SWREG38_SW_AREF_VER_SCALE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG38_SW_AREF_VER_SCALE_SHIFT)) & VPU_G2_SWREG38_SW_AREF_VER_SCALE_MASK)
104430 
104431 #define VPU_G2_SWREG38_SW_AREF_HOR_SCALE_MASK    (0xFFFF0000U)
104432 #define VPU_G2_SWREG38_SW_AREF_HOR_SCALE_SHIFT   (16U)
104433 /*! SW_AREF_HOR_SCALE - Horizontal scaling factor for alternate reference picture */
104434 #define VPU_G2_SWREG38_SW_AREF_HOR_SCALE(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG38_SW_AREF_HOR_SCALE_SHIFT)) & VPU_G2_SWREG38_SW_AREF_HOR_SCALE_MASK)
104435 /*! @} */
104436 
104437 /*! @name SWREG45 - Timeout control register */
104438 /*! @{ */
104439 
104440 #define VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_MASK    (0x7FFFFFFFU)
104441 #define VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_SHIFT   (0U)
104442 /*! SW_TIMEOUT_CYCLES - Amount of clock cycles to trigger timeout interrupt if no external master
104443  *    activity acknowledged. Used if sw_timeout_override_e is set
104444  */
104445 #define VPU_G2_SWREG45_SW_TIMEOUT_CYCLES(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_SHIFT)) & VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_MASK)
104446 
104447 #define VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_MASK (0x80000000U)
104448 #define VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_SHIFT (31U)
104449 /*! SW_TIMEOUT_OVERRIDE_E - Enable for SW controlled timeout. If enabled the sw_timeout_cycles is
104450  *    used to detect HW timeout instead of hard coded HW value
104451  */
104452 #define VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_SHIFT)) & VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_MASK)
104453 /*! @} */
104454 
104455 /*! @name SWREG46 - Picture order count from current pictures for index 0-3 */
104456 /*! @{ */
104457 
104458 #define VPU_G2_SWREG46_PIC_ORD_0_3_BF_MASK       (0xFFFFFFFFU)
104459 #define VPU_G2_SWREG46_PIC_ORD_0_3_BF_SHIFT      (0U)
104460 #define VPU_G2_SWREG46_PIC_ORD_0_3_BF(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG46_PIC_ORD_0_3_BF_SHIFT)) & VPU_G2_SWREG46_PIC_ORD_0_3_BF_MASK)
104461 /*! @} */
104462 
104463 /*! @name SWREG47 - Picture order count from current pictures for index 4-7 */
104464 /*! @{ */
104465 
104466 #define VPU_G2_SWREG47_PIC_ORD_4_7_BF_MASK       (0xFFFFFFFFU)
104467 #define VPU_G2_SWREG47_PIC_ORD_4_7_BF_SHIFT      (0U)
104468 #define VPU_G2_SWREG47_PIC_ORD_4_7_BF(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG47_PIC_ORD_4_7_BF_SHIFT)) & VPU_G2_SWREG47_PIC_ORD_4_7_BF_MASK)
104469 /*! @} */
104470 
104471 /*! @name SWREG48 - Picture order count from current pictures for index 8-11 */
104472 /*! @{ */
104473 
104474 #define VPU_G2_SWREG48_SW_CUR_POC_11_MASK        (0xFFU)
104475 #define VPU_G2_SWREG48_SW_CUR_POC_11_SHIFT       (0U)
104476 /*! SW_CUR_POC_11 - Picture order count from current picture 11 */
104477 #define VPU_G2_SWREG48_SW_CUR_POC_11(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_11_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_11_MASK)
104478 
104479 #define VPU_G2_SWREG48_SW_CUR_POC_10_MASK        (0xFF00U)
104480 #define VPU_G2_SWREG48_SW_CUR_POC_10_SHIFT       (8U)
104481 /*! SW_CUR_POC_10 - Picture order count from current picture 10 */
104482 #define VPU_G2_SWREG48_SW_CUR_POC_10(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_10_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_10_MASK)
104483 
104484 #define VPU_G2_SWREG48_SW_CUR_POC_09_MASK        (0xFF0000U)
104485 #define VPU_G2_SWREG48_SW_CUR_POC_09_SHIFT       (16U)
104486 /*! SW_CUR_POC_09 - Picture order count from current picture 9 */
104487 #define VPU_G2_SWREG48_SW_CUR_POC_09(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_09_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_09_MASK)
104488 
104489 #define VPU_G2_SWREG48_SW_CUR_POC_08_MASK        (0xFF000000U)
104490 #define VPU_G2_SWREG48_SW_CUR_POC_08_SHIFT       (24U)
104491 /*! SW_CUR_POC_08 - Picture order count from current picture 8 */
104492 #define VPU_G2_SWREG48_SW_CUR_POC_08(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_08_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_08_MASK)
104493 /*! @} */
104494 
104495 /*! @name SWREG49 - Picture order count from current pictures for index 12-15 */
104496 /*! @{ */
104497 
104498 #define VPU_G2_SWREG49_SW_CUR_POC_15_MASK        (0xFFU)
104499 #define VPU_G2_SWREG49_SW_CUR_POC_15_SHIFT       (0U)
104500 /*! SW_CUR_POC_15 - Picture order count from current picture 15 */
104501 #define VPU_G2_SWREG49_SW_CUR_POC_15(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_15_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_15_MASK)
104502 
104503 #define VPU_G2_SWREG49_SW_CUR_POC_14_MASK        (0xFF00U)
104504 #define VPU_G2_SWREG49_SW_CUR_POC_14_SHIFT       (8U)
104505 /*! SW_CUR_POC_14 - Picture order count from current picture 14 */
104506 #define VPU_G2_SWREG49_SW_CUR_POC_14(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_14_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_14_MASK)
104507 
104508 #define VPU_G2_SWREG49_SW_CUR_POC_13_MASK        (0xFF0000U)
104509 #define VPU_G2_SWREG49_SW_CUR_POC_13_SHIFT       (16U)
104510 /*! SW_CUR_POC_13 - Picture order count from current picture 13 */
104511 #define VPU_G2_SWREG49_SW_CUR_POC_13(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_13_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_13_MASK)
104512 
104513 #define VPU_G2_SWREG49_SW_CUR_POC_12_MASK        (0xFF000000U)
104514 #define VPU_G2_SWREG49_SW_CUR_POC_12_SHIFT       (24U)
104515 /*! SW_CUR_POC_12 - Picture order count from current picture 12 */
104516 #define VPU_G2_SWREG49_SW_CUR_POC_12(x)          (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_12_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_12_MASK)
104517 /*! @} */
104518 
104519 /*! @name SWREG50 - Synthesis configuration register decoder 0 (read only) */
104520 /*! @{ */
104521 
104522 #define VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_MASK    (0x7FFU)
104523 #define VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT   (0U)
104524 /*! SW_DEC_MAX_OWIDTH - Max configured decoder video resolution that can be decoded. Informed as width of the picture in pixels */
104525 #define VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT)) & VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_MASK)
104526 /*! @} */
104527 
104528 /*! @name SWREG54 - Synthesis configuration register decoder 1 (read only) */
104529 /*! @{ */
104530 
104531 #define VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_MASK    (0xC000U)
104532 #define VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT   (14U)
104533 /*! SW_DEC_MAX_OW_EXT - Max configured decoder video resolution that can be decoded. This is the MSB part of the configuration signal */
104534 #define VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT)) & VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_MASK)
104535 /*! @} */
104536 
104537 /*! @name SWREG55 - Advanced prefetch control register */
104538 /*! @{ */
104539 
104540 #define VPU_G2_SWREG55_SW_APF_THRESHOLD_MASK     (0xFFFFU)
104541 #define VPU_G2_SWREG55_SW_APF_THRESHOLD_SHIFT    (0U)
104542 /*! SW_APF_THRESHOLD - Advanced prefetch threshold. If current buffered unit exceeds the threshold
104543  *    the advanced mode is not used. Value 0 disables threshold usage and advanced prefetch usage is
104544  *    restricted by internal memory limitation only
104545  */
104546 #define VPU_G2_SWREG55_SW_APF_THRESHOLD(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG55_SW_APF_THRESHOLD_SHIFT)) & VPU_G2_SWREG55_SW_APF_THRESHOLD_MASK)
104547 
104548 #define VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_MASK (0x40000000U)
104549 #define VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_SHIFT (30U)
104550 /*! SW_APF_SINGLE_PU_MODE - APF amount of buffered Pus: can be restricted to buffer one PU at a time */
104551 #define VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_SHIFT)) & VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_MASK)
104552 
104553 #define VPU_G2_SWREG55_SW_APF_DISABLE_MASK       (0x80000000U)
104554 #define VPU_G2_SWREG55_SW_APF_DISABLE_SHIFT      (31U)
104555 /*! SW_APF_DISABLE - Advanced prefetch disable. If hight each partition is read separately */
104556 #define VPU_G2_SWREG55_SW_APF_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG55_SW_APF_DISABLE_SHIFT)) & VPU_G2_SWREG55_SW_APF_DISABLE_MASK)
104557 /*! @} */
104558 
104559 /*! @name SWREG56 - Synthesis configuration register decoder 2 (read only) */
104560 /*! @{ */
104561 
104562 #define VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_MASK   (0x1FFFU)
104563 #define VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_SHIFT  (0U)
104564 /*! SW_DEC_MAX_OHEIGHT - Max supported picture height in pixels */
104565 #define VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_SHIFT)) & VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_MASK)
104566 /*! @} */
104567 
104568 /*! @name SWREG58 - Device configuration register decoder 2 + Multi core control register */
104569 /*! @{ */
104570 
104571 #define VPU_G2_SWREG58_SW_DEC_MAX_BURST_MASK     (0xFFU)
104572 #define VPU_G2_SWREG58_SW_DEC_MAX_BURST_SHIFT    (0U)
104573 /*! SW_DEC_MAX_BURST - Maximum burst length for decoder bus transactions. Valid values: AXI: 1-256 */
104574 #define VPU_G2_SWREG58_SW_DEC_MAX_BURST(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_MAX_BURST_SHIFT)) & VPU_G2_SWREG58_SW_DEC_MAX_BURST_MASK)
104575 
104576 #define VPU_G2_SWREG58_SW_DEC_BUSWIDTH_MASK      (0x700U)
104577 #define VPU_G2_SWREG58_SW_DEC_BUSWIDTH_SHIFT     (8U)
104578 /*! SW_DEC_BUSWIDTH - Decoder master interface buswidth
104579  *  0b000..32 bit bus
104580  *  0b001..64 bit bus
104581  *  0b010..128 bit bus
104582  */
104583 #define VPU_G2_SWREG58_SW_DEC_BUSWIDTH(x)        (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_BUSWIDTH_SHIFT)) & VPU_G2_SWREG58_SW_DEC_BUSWIDTH_MASK)
104584 
104585 #define VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_MASK   (0x2000U)
104586 #define VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_SHIFT  (13U)
104587 /*! SW_DEC_AXI_WD_ID_E - SW axi ID enable. When enabled the given sw_dec_axi_wd_id is used as ID base and each sub-block will use offsets 0...max */
104588 #define VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_MASK)
104589 
104590 #define VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_MASK   (0x4000U)
104591 #define VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_SHIFT  (14U)
104592 /*! SW_DEC_AXI_RD_ID_E - SW axi ID enable. When enabled the given sw_dec_axi_rd_id is used as ID base and each sub-block will use offsets 0...max */
104593 #define VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_MASK)
104594 
104595 #define VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_MASK (0x8000U)
104596 #define VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_SHIFT (15U)
104597 /*! SW_DEC_REFER_DOUBLEBUFFER_E - HW internal double buffering enable for reference data. This
104598  *    enable requires that there are two buffers available at the configured decoder (see configuration
104599  *    register values)
104600  */
104601 #define VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_MASK)
104602 
104603 #define VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_MASK    (0x10000U)
104604 #define VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_SHIFT   (16U)
104605 /*! SW_DEC_CLK_GATE_E - Clock gating enable for picture-wise/decoding format clock gating. Between
104606  *    each picture the clock is gated from HW if this bit is high
104607  */
104608 #define VPU_G2_SWREG58_SW_DEC_CLK_GATE_E(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_MASK)
104609 
104610 #define VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_MASK (0x20000U)
104611 #define VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_SHIFT (17U)
104612 /*! SW_DEC_CLK_GATE_IDLE_E - Clock gating enable for decoder run-time. Generated separate clocks for each block by its own IDLE signal. */
104613 #define VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_MASK)
104614 /*! @} */
104615 
104616 /*! @name SWREG59 - Device configuration register AXI ID */
104617 /*! @{ */
104618 
104619 #define VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_MASK     (0xFFFFU)
104620 #define VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_SHIFT    (0U)
104621 /*! SW_DEC_AXI_RD_ID - Write ID base for HW write accesses. Each writing device use AXI ID of
104622  *    base+deviceoffset (where device offset is 0 1 2 3...Number of writing sub-blocks)
104623  */
104624 #define VPU_G2_SWREG59_SW_DEC_AXI_RD_ID(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_SHIFT)) & VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_MASK)
104625 
104626 #define VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_MASK     (0xFFFF0000U)
104627 #define VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_SHIFT    (16U)
104628 /*! SW_DEC_AXI_WR_ID - Read ID base for HW write accesses. Each writing device use AXI ID of
104629  *    base+deviceoffset (where device offset is 0 1 2 3...Number of reading sub-blocks)
104630  */
104631 #define VPU_G2_SWREG59_SW_DEC_AXI_WR_ID(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_SHIFT)) & VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_MASK)
104632 /*! @} */
104633 
104634 /*! @name SWREG60 - Synthesis configuration register decoder 3 for PP (read only) */
104635 /*! @{ */
104636 
104637 #define VPU_G2_SWREG60_SW_DEC_PP_RS_E_MASK       (0x40000000U)
104638 #define VPU_G2_SWREG60_SW_DEC_PP_RS_E_SHIFT      (30U)
104639 /*! SW_DEC_PP_RS_E - Decoder PP raster scan output support
104640  *  0b0..Raster scan output not supported
104641  *  0b1..Raster scan output supported
104642  */
104643 #define VPU_G2_SWREG60_SW_DEC_PP_RS_E(x)         (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG60_SW_DEC_PP_RS_E_SHIFT)) & VPU_G2_SWREG60_SW_DEC_PP_RS_E_MASK)
104644 
104645 #define VPU_G2_SWREG60_SW_DEC_PP_E_MASK          (0x80000000U)
104646 #define VPU_G2_SWREG60_SW_DEC_PP_E_SHIFT         (31U)
104647 /*! SW_DEC_PP_E - Decoder include PP
104648  *  0b0..PP does not exist. None of the PP features can be enabled.
104649  *  0b1..PP exists
104650  */
104651 #define VPU_G2_SWREG60_SW_DEC_PP_E(x)            (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG60_SW_DEC_PP_E_SHIFT)) & VPU_G2_SWREG60_SW_DEC_PP_E_MASK)
104652 /*! @} */
104653 
104654 /*! @name SWREG62 - HW proceed register (CU location) */
104655 /*! @{ */
104656 
104657 #define VPU_G2_SWREG62_SW_CU_LOCATION_Y_MASK     (0xFFFFU)
104658 #define VPU_G2_SWREG62_SW_CU_LOCATION_Y_SHIFT    (0U)
104659 /*! SW_CU_LOCATION_Y - Cu vertical start location Y in pixels (returned HW internal position during interrupt) */
104660 #define VPU_G2_SWREG62_SW_CU_LOCATION_Y(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG62_SW_CU_LOCATION_Y_SHIFT)) & VPU_G2_SWREG62_SW_CU_LOCATION_Y_MASK)
104661 
104662 #define VPU_G2_SWREG62_SW_CU_LOCATION_X_MASK     (0xFFFF0000U)
104663 #define VPU_G2_SWREG62_SW_CU_LOCATION_X_SHIFT    (16U)
104664 /*! SW_CU_LOCATION_X - Cu horizontal start location X in pixels (returned HW internal position during interrupt) */
104665 #define VPU_G2_SWREG62_SW_CU_LOCATION_X(x)       (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG62_SW_CU_LOCATION_X_SHIFT)) & VPU_G2_SWREG62_SW_CU_LOCATION_X_MASK)
104666 /*! @} */
104667 
104668 /*! @name SWREG63 - HW performance register (cycles running) */
104669 /*! @{ */
104670 
104671 #define VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_MASK  (0xFFFFFFFFU)
104672 #define VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_SHIFT (0U)
104673 /*! SW_PERF_CYCLE_COUNT - HW clock cycle counter return value. Amount of consumed clock cycles
104674  *    returned to this register when interrupt is being made (any kind of interrupt)
104675  */
104676 #define VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_SHIFT)) & VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_MASK)
104677 /*! @} */
104678 
104679 /*! @name SWREG64 - Base address MSB (bits 63:32) for decoded luminance picture */
104680 /*! @{ */
104681 
104682 #define VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_MASK (0xFFFFFFFFU)
104683 #define VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_SHIFT (0U)
104684 /*! SW_DEC_OUT_YBASE_MSB - Base address MSB (bits 63:32) for decoded luminance picture */
104685 #define VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_SHIFT)) & VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_MASK)
104686 /*! @} */
104687 
104688 /*! @name SWREG65 - Base address LSB (bits 31:0) for decoded luminance picture */
104689 /*! @{ */
104690 
104691 #define VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_MASK (0xFFFFFFFFU)
104692 #define VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_SHIFT (0U)
104693 /*! SW_DEC_OUT_YBASE_LSB - Base address LSB (bits 31:0) for decoded luminance picture */
104694 #define VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_SHIFT)) & VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_MASK)
104695 /*! @} */
104696 
104697 /*! @name SWREG66 - Base address MSB (bits 63:32) for reference luminance picture index 0 */
104698 /*! @{ */
104699 
104700 #define VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_MASK  (0xFFFFFFFFU)
104701 #define VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_SHIFT (0U)
104702 /*! SW_REFER0_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 0 */
104703 #define VPU_G2_SWREG66_SW_REFER0_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_SHIFT)) & VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_MASK)
104704 /*! @} */
104705 
104706 /*! @name SWREG67 - Base address LSB (bits 31:0) for reference luminance picture index 0 */
104707 /*! @{ */
104708 
104709 #define VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_MASK  (0xFFFFFFFFU)
104710 #define VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_SHIFT (0U)
104711 /*! SW_REFER0_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 0 */
104712 #define VPU_G2_SWREG67_SW_REFER0_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_SHIFT)) & VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_MASK)
104713 /*! @} */
104714 
104715 /*! @name SWREG68 - Base address MSB (bits 63:32) for reference luminance picture index 1 */
104716 /*! @{ */
104717 
104718 #define VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_MASK  (0xFFFFFFFFU)
104719 #define VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_SHIFT (0U)
104720 /*! SW_REFER1_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 1 */
104721 #define VPU_G2_SWREG68_SW_REFER1_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_SHIFT)) & VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_MASK)
104722 /*! @} */
104723 
104724 /*! @name SWREG69 - Base address LSB (bits 31:0) for reference luminance picture index 1 */
104725 /*! @{ */
104726 
104727 #define VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_MASK  (0xFFFFFFFFU)
104728 #define VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_SHIFT (0U)
104729 /*! SW_REFER1_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 1 */
104730 #define VPU_G2_SWREG69_SW_REFER1_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_SHIFT)) & VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_MASK)
104731 /*! @} */
104732 
104733 /*! @name SWREG70 - Base address MSB (bits 63:32) for reference luminance picture index 2 */
104734 /*! @{ */
104735 
104736 #define VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_MASK  (0xFFFFFFFFU)
104737 #define VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_SHIFT (0U)
104738 /*! SW_REFER2_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 2 */
104739 #define VPU_G2_SWREG70_SW_REFER2_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_SHIFT)) & VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_MASK)
104740 /*! @} */
104741 
104742 /*! @name SWREG71 - Base address LSB (bits 31:0) for reference luminance picture index 2 */
104743 /*! @{ */
104744 
104745 #define VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_MASK  (0xFFFFFFFFU)
104746 #define VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_SHIFT (0U)
104747 /*! SW_REFER2_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 2 */
104748 #define VPU_G2_SWREG71_SW_REFER2_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_SHIFT)) & VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_MASK)
104749 /*! @} */
104750 
104751 /*! @name SWREG72 - Base address MSB (bits 63:32) for reference luminance picture index 3 */
104752 /*! @{ */
104753 
104754 #define VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_MASK  (0xFFFFFFFFU)
104755 #define VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_SHIFT (0U)
104756 /*! SW_REFER3_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 3 */
104757 #define VPU_G2_SWREG72_SW_REFER3_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_SHIFT)) & VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_MASK)
104758 /*! @} */
104759 
104760 /*! @name SWREG73 - Base address LSB (bits 31:0) for reference luminance picture index 3 */
104761 /*! @{ */
104762 
104763 #define VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_MASK  (0xFFFFFFFFU)
104764 #define VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_SHIFT (0U)
104765 /*! SW_REFER3_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 3 */
104766 #define VPU_G2_SWREG73_SW_REFER3_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_SHIFT)) & VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_MASK)
104767 /*! @} */
104768 
104769 /*! @name SWREG74 - Base address MSB (bits 63:32) for reference luminance picture index 4 */
104770 /*! @{ */
104771 
104772 #define VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_MASK  (0xFFFFFFFFU)
104773 #define VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_SHIFT (0U)
104774 /*! SW_REFER4_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 4 */
104775 #define VPU_G2_SWREG74_SW_REFER4_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_SHIFT)) & VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_MASK)
104776 /*! @} */
104777 
104778 /*! @name SWREG75 - Base address LSB (bits 31:0) for reference luminance picture index 4 */
104779 /*! @{ */
104780 
104781 #define VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_MASK  (0xFFFFFFFFU)
104782 #define VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_SHIFT (0U)
104783 /*! SW_REFER4_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 4 */
104784 #define VPU_G2_SWREG75_SW_REFER4_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_SHIFT)) & VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_MASK)
104785 /*! @} */
104786 
104787 /*! @name SWREG76 - Base address MSB (bits 63:32) for reference luminance picture index 5 */
104788 /*! @{ */
104789 
104790 #define VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_MASK  (0xFFFFFFFFU)
104791 #define VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_SHIFT (0U)
104792 /*! SW_REFER5_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 5 */
104793 #define VPU_G2_SWREG76_SW_REFER5_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_SHIFT)) & VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_MASK)
104794 /*! @} */
104795 
104796 /*! @name SWREG77 - Base address LSB (bits 31:0) for reference luminance picture index 5 */
104797 /*! @{ */
104798 
104799 #define VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_MASK  (0xFFFFFFFFU)
104800 #define VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_SHIFT (0U)
104801 /*! SW_REFER5_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 5 */
104802 #define VPU_G2_SWREG77_SW_REFER5_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_SHIFT)) & VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_MASK)
104803 /*! @} */
104804 
104805 /*! @name SWREG78 - Base address MSB (bits 63:32) for reference luminance picture index 6 /VP9 segment write base MSB */
104806 /*! @{ */
104807 
104808 #define VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_MASK   (0xFFFFFFFFU)
104809 #define VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_SHIFT  (0U)
104810 #define VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_SHIFT)) & VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_MASK)
104811 /*! @} */
104812 
104813 /*! @name SWREG79 - Base address LSB (bits 31:0) for reference luminance picture index 6 /VP9 segment write base LSB */
104814 /*! @{ */
104815 
104816 #define VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_MASK   (0xFFFFFFFFU)
104817 #define VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_SHIFT  (0U)
104818 #define VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_SHIFT)) & VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_MASK)
104819 /*! @} */
104820 
104821 /*! @name SWREG80 - Base address MSB (bits 63:32) for reference luminance picture index 7 /VP9 segment read base MSB */
104822 /*! @{ */
104823 
104824 #define VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_MASK   (0xFFFFFFFFU)
104825 #define VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_SHIFT  (0U)
104826 #define VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_SHIFT)) & VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_MASK)
104827 /*! @} */
104828 
104829 /*! @name SWREG81 - Base address LSB (bits 31:0) for reference luminance picture index 7 /VP9 segment read base LSB */
104830 /*! @{ */
104831 
104832 #define VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_MASK   (0xFFFFFFFFU)
104833 #define VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_SHIFT  (0U)
104834 #define VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_SHIFT)) & VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_MASK)
104835 /*! @} */
104836 
104837 /*! @name SWREG82 - Base address MSB (bits 63:32) for reference luminance picture index 8 */
104838 /*! @{ */
104839 
104840 #define VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_MASK  (0xFFFFFFFFU)
104841 #define VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_SHIFT (0U)
104842 /*! SW_REFER8_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 8 */
104843 #define VPU_G2_SWREG82_SW_REFER8_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_SHIFT)) & VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_MASK)
104844 /*! @} */
104845 
104846 /*! @name SWREG83 - Base address LSB (bits 31:0) for reference luminance picture index 8 */
104847 /*! @{ */
104848 
104849 #define VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_MASK  (0xFFFFFFFFU)
104850 #define VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_SHIFT (0U)
104851 /*! SW_REFER8_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 8 */
104852 #define VPU_G2_SWREG83_SW_REFER8_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_SHIFT)) & VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_MASK)
104853 /*! @} */
104854 
104855 /*! @name SWREG84 - Base address MSB (bits 63:32) for reference luminance picture index 9 */
104856 /*! @{ */
104857 
104858 #define VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_MASK  (0xFFFFFFFFU)
104859 #define VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_SHIFT (0U)
104860 /*! SW_REFER9_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 9 */
104861 #define VPU_G2_SWREG84_SW_REFER9_YBASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_SHIFT)) & VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_MASK)
104862 /*! @} */
104863 
104864 /*! @name SWREG85 - Base address LSB (bits 31:0) for reference luminance picture index 9 */
104865 /*! @{ */
104866 
104867 #define VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_MASK  (0xFFFFFFFFU)
104868 #define VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_SHIFT (0U)
104869 /*! SW_REFER9_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 9 */
104870 #define VPU_G2_SWREG85_SW_REFER9_YBASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_SHIFT)) & VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_MASK)
104871 /*! @} */
104872 
104873 /*! @name SWREG86 - Base address MSB (bits 63:32) for reference luminance picture index 10 */
104874 /*! @{ */
104875 
104876 #define VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_MASK (0xFFFFFFFFU)
104877 #define VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_SHIFT (0U)
104878 /*! SW_REFER10_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 10 */
104879 #define VPU_G2_SWREG86_SW_REFER10_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_SHIFT)) & VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_MASK)
104880 /*! @} */
104881 
104882 /*! @name SWREG87 - Base address LSB (bits 31:0) for reference luminance picture index 10 */
104883 /*! @{ */
104884 
104885 #define VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_MASK (0xFFFFFFFFU)
104886 #define VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_SHIFT (0U)
104887 /*! SW_REFER10_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 10 */
104888 #define VPU_G2_SWREG87_SW_REFER10_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_SHIFT)) & VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_MASK)
104889 /*! @} */
104890 
104891 /*! @name SWREG88 - Base address MSB (bits 63:32) for reference luminance picture index 11 */
104892 /*! @{ */
104893 
104894 #define VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_MASK (0xFFFFFFFFU)
104895 #define VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_SHIFT (0U)
104896 /*! SW_REFER11_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 11 */
104897 #define VPU_G2_SWREG88_SW_REFER11_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_SHIFT)) & VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_MASK)
104898 /*! @} */
104899 
104900 /*! @name SWREG89 - Base address LSB (bits 31:0) for reference luminance picture index 11 */
104901 /*! @{ */
104902 
104903 #define VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_MASK (0xFFFFFFFFU)
104904 #define VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_SHIFT (0U)
104905 /*! SW_REFER11_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 11 */
104906 #define VPU_G2_SWREG89_SW_REFER11_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_SHIFT)) & VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_MASK)
104907 /*! @} */
104908 
104909 /*! @name SWREG90 - Base address MSB (bits 63:32) for reference luminance picture index 12 */
104910 /*! @{ */
104911 
104912 #define VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_MASK (0xFFFFFFFFU)
104913 #define VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_SHIFT (0U)
104914 /*! SW_REFER12_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 12 */
104915 #define VPU_G2_SWREG90_SW_REFER12_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_SHIFT)) & VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_MASK)
104916 /*! @} */
104917 
104918 /*! @name SWREG91 - Base address LSB (bits 31:0) for reference luminance picture index 12 */
104919 /*! @{ */
104920 
104921 #define VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_MASK (0xFFFFFFFFU)
104922 #define VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_SHIFT (0U)
104923 /*! SW_REFER12_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 12 */
104924 #define VPU_G2_SWREG91_SW_REFER12_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_SHIFT)) & VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_MASK)
104925 /*! @} */
104926 
104927 /*! @name SWREG92 - Base address MSB (bits 63:32) for reference luminance picture index 13 */
104928 /*! @{ */
104929 
104930 #define VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_MASK (0xFFFFFFFFU)
104931 #define VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_SHIFT (0U)
104932 /*! SW_REFER13_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 13 */
104933 #define VPU_G2_SWREG92_SW_REFER13_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_SHIFT)) & VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_MASK)
104934 /*! @} */
104935 
104936 /*! @name SWREG93 - Base address LSB (bits 31:0) for reference luminance picture index 13 */
104937 /*! @{ */
104938 
104939 #define VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_MASK (0xFFFFFFFFU)
104940 #define VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_SHIFT (0U)
104941 /*! SW_REFER13_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 13 */
104942 #define VPU_G2_SWREG93_SW_REFER13_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_SHIFT)) & VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_MASK)
104943 /*! @} */
104944 
104945 /*! @name SWREG94 - Base address MSB (bits 63:32) for reference luminance picture index 14 */
104946 /*! @{ */
104947 
104948 #define VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_MASK (0xFFFFFFFFU)
104949 #define VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_SHIFT (0U)
104950 /*! SW_REFER14_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 14 */
104951 #define VPU_G2_SWREG94_SW_REFER14_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_SHIFT)) & VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_MASK)
104952 /*! @} */
104953 
104954 /*! @name SWREG95 - Base address LSB (bits 31:0) for reference luminance picture index 14 */
104955 /*! @{ */
104956 
104957 #define VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_MASK (0xFFFFFFFFU)
104958 #define VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_SHIFT (0U)
104959 /*! SW_REFER14_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 14 */
104960 #define VPU_G2_SWREG95_SW_REFER14_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_SHIFT)) & VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_MASK)
104961 /*! @} */
104962 
104963 /*! @name SWREG96 - Base address MSB (bits 63:32) for reference luminance picture index 15 */
104964 /*! @{ */
104965 
104966 #define VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_MASK (0xFFFFFFFFU)
104967 #define VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_SHIFT (0U)
104968 /*! SW_REFER15_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 15 */
104969 #define VPU_G2_SWREG96_SW_REFER15_YBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_SHIFT)) & VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_MASK)
104970 /*! @} */
104971 
104972 /*! @name SWREG97 - Base address LSB (bits 31:0) for reference luminance picture index 15 */
104973 /*! @{ */
104974 
104975 #define VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_MASK (0xFFFFFFFFU)
104976 #define VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_SHIFT (0U)
104977 /*! SW_REFER15_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 15 */
104978 #define VPU_G2_SWREG97_SW_REFER15_YBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_SHIFT)) & VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_MASK)
104979 /*! @} */
104980 
104981 /*! @name SWREG98 - Base address MSB (bits 63:32) for decoded chrominance picture */
104982 /*! @{ */
104983 
104984 #define VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_MASK (0xFFFFFFFFU)
104985 #define VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_SHIFT (0U)
104986 /*! SW_DEC_OUT_CBASE_MSB - Base address MSB (bits 64:32) for decoded chrominance picture */
104987 #define VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_SHIFT)) & VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_MASK)
104988 /*! @} */
104989 
104990 /*! @name SWREG99 - Base address LSB (bits 31:0) for decoded chrominance picture */
104991 /*! @{ */
104992 
104993 #define VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_MASK (0xFFFFFFFFU)
104994 #define VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_SHIFT (0U)
104995 /*! SW_DEC_OUT_CBASE_LSB - Base address LSB (bits 31:0) for decoded chrominance picture */
104996 #define VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_SHIFT)) & VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_MASK)
104997 /*! @} */
104998 
104999 /*! @name SWREG100 - Base address MSB (bits 63:32) for reference chrominance picture index 0 */
105000 /*! @{ */
105001 
105002 #define VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_MASK (0xFFFFFFFFU)
105003 #define VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_SHIFT (0U)
105004 /*! SW_REFER0_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 0 */
105005 #define VPU_G2_SWREG100_SW_REFER0_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_SHIFT)) & VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_MASK)
105006 /*! @} */
105007 
105008 /*! @name SWREG101 - Base address LSB (bits 31:0) for reference chrominance picture index 0 */
105009 /*! @{ */
105010 
105011 #define VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_MASK (0xFFFFFFFFU)
105012 #define VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_SHIFT (0U)
105013 /*! SW_REFER0_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 0 */
105014 #define VPU_G2_SWREG101_SW_REFER0_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_SHIFT)) & VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_MASK)
105015 /*! @} */
105016 
105017 /*! @name SWREG102 - Base address MSB (bits 63:32) for reference chrominance picture index 1 */
105018 /*! @{ */
105019 
105020 #define VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_MASK (0xFFFFFFFFU)
105021 #define VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_SHIFT (0U)
105022 /*! SW_REFER1_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 1 */
105023 #define VPU_G2_SWREG102_SW_REFER1_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_SHIFT)) & VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_MASK)
105024 /*! @} */
105025 
105026 /*! @name SWREG103 - Base address LSB (bits 31:0) for reference chrominance picture index 1 */
105027 /*! @{ */
105028 
105029 #define VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_MASK (0xFFFFFFFFU)
105030 #define VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_SHIFT (0U)
105031 /*! SW_REFER1_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 1 */
105032 #define VPU_G2_SWREG103_SW_REFER1_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_SHIFT)) & VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_MASK)
105033 /*! @} */
105034 
105035 /*! @name SWREG104 - Base address MSB (bits 63:32) for reference chrominance picture index 2 */
105036 /*! @{ */
105037 
105038 #define VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_MASK (0xFFFFFFFFU)
105039 #define VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_SHIFT (0U)
105040 /*! SW_REFER2_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 2 */
105041 #define VPU_G2_SWREG104_SW_REFER2_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_SHIFT)) & VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_MASK)
105042 /*! @} */
105043 
105044 /*! @name SWREG105 - Base address LSB (bits 31:0) for reference chrominance picture index 2 */
105045 /*! @{ */
105046 
105047 #define VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_MASK (0xFFFFFFFFU)
105048 #define VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_SHIFT (0U)
105049 /*! SW_REFER2_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 2 */
105050 #define VPU_G2_SWREG105_SW_REFER2_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_SHIFT)) & VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_MASK)
105051 /*! @} */
105052 
105053 /*! @name SWREG106 - Base address MSB (bits 63:32) for reference chrominance picture index 3 */
105054 /*! @{ */
105055 
105056 #define VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_MASK (0xFFFFFFFFU)
105057 #define VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_SHIFT (0U)
105058 /*! SW_REFER3_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 3 */
105059 #define VPU_G2_SWREG106_SW_REFER3_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_SHIFT)) & VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_MASK)
105060 /*! @} */
105061 
105062 /*! @name SWREG107 - Base address LSB (bits 31:0) for reference chrominance picture index 3 */
105063 /*! @{ */
105064 
105065 #define VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_MASK (0xFFFFFFFFU)
105066 #define VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_SHIFT (0U)
105067 /*! SW_REFER3_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 3 */
105068 #define VPU_G2_SWREG107_SW_REFER3_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_SHIFT)) & VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_MASK)
105069 /*! @} */
105070 
105071 /*! @name SWREG108 - Base address MSB (bits 63:32) for reference chrominance picture index 4 */
105072 /*! @{ */
105073 
105074 #define VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_MASK (0xFFFFFFFFU)
105075 #define VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_SHIFT (0U)
105076 /*! SW_REFER4_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 4 */
105077 #define VPU_G2_SWREG108_SW_REFER4_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_SHIFT)) & VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_MASK)
105078 /*! @} */
105079 
105080 /*! @name SWREG109 - Base address LSB (bits 31:0) for reference chrominance picture index 4 */
105081 /*! @{ */
105082 
105083 #define VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_MASK (0xFFFFFFFFU)
105084 #define VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_SHIFT (0U)
105085 /*! SW_REFER4_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 4 */
105086 #define VPU_G2_SWREG109_SW_REFER4_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_SHIFT)) & VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_MASK)
105087 /*! @} */
105088 
105089 /*! @name SWREG110 - Base address MSB (bits 63:32) for reference chrominance picture index 5 */
105090 /*! @{ */
105091 
105092 #define VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_MASK (0xFFFFFFFFU)
105093 #define VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_SHIFT (0U)
105094 /*! SW_REFER5_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 5 */
105095 #define VPU_G2_SWREG110_SW_REFER5_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_SHIFT)) & VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_MASK)
105096 /*! @} */
105097 
105098 /*! @name SWREG111 - Base address LSB (bits 31:0) for reference chrominance picture index 5 */
105099 /*! @{ */
105100 
105101 #define VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_MASK (0xFFFFFFFFU)
105102 #define VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_SHIFT (0U)
105103 /*! SW_REFER5_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 5 */
105104 #define VPU_G2_SWREG111_SW_REFER5_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_SHIFT)) & VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_MASK)
105105 /*! @} */
105106 
105107 /*! @name SWREG112 - Base address MSB (bits 63:32) for reference chrominance picture index 6 */
105108 /*! @{ */
105109 
105110 #define VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_MASK (0xFFFFFFFFU)
105111 #define VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_SHIFT (0U)
105112 /*! SW_REFER6_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 6 */
105113 #define VPU_G2_SWREG112_SW_REFER6_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_SHIFT)) & VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_MASK)
105114 /*! @} */
105115 
105116 /*! @name SWREG113 - Base address LSB (bits 31:0) for reference chrominance picture index 6 */
105117 /*! @{ */
105118 
105119 #define VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_MASK (0xFFFFFFFFU)
105120 #define VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_SHIFT (0U)
105121 /*! SW_REFER6_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 6 */
105122 #define VPU_G2_SWREG113_SW_REFER6_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_SHIFT)) & VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_MASK)
105123 /*! @} */
105124 
105125 /*! @name SWREG114 - Base address MSB (bits 63:32) for reference chrominance picture index 7 */
105126 /*! @{ */
105127 
105128 #define VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_MASK (0xFFFFFFFFU)
105129 #define VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_SHIFT (0U)
105130 /*! SW_REFER7_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 7 */
105131 #define VPU_G2_SWREG114_SW_REFER7_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_SHIFT)) & VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_MASK)
105132 /*! @} */
105133 
105134 /*! @name SWREG115 - Base address LSB (bits 31:0) for reference chrominance picture index 7 */
105135 /*! @{ */
105136 
105137 #define VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_MASK (0xFFFFFFFFU)
105138 #define VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_SHIFT (0U)
105139 /*! SW_REFER7_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 7 */
105140 #define VPU_G2_SWREG115_SW_REFER7_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_SHIFT)) & VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_MASK)
105141 /*! @} */
105142 
105143 /*! @name SWREG116 - Base address MSB (bits 63:32) for reference chrominance picture index 8 */
105144 /*! @{ */
105145 
105146 #define VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_MASK (0xFFFFFFFFU)
105147 #define VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_SHIFT (0U)
105148 /*! SW_REFER8_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 8 */
105149 #define VPU_G2_SWREG116_SW_REFER8_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_SHIFT)) & VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_MASK)
105150 /*! @} */
105151 
105152 /*! @name SWREG117 - Base address LSB (bits 31:0) for reference chrominance picture index 8 */
105153 /*! @{ */
105154 
105155 #define VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_MASK (0xFFFFFFFFU)
105156 #define VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_SHIFT (0U)
105157 /*! SW_REFER8_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 8 */
105158 #define VPU_G2_SWREG117_SW_REFER8_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_SHIFT)) & VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_MASK)
105159 /*! @} */
105160 
105161 /*! @name SWREG118 - Base address MSB (bits 63:32) for reference chrominance picture index 9 */
105162 /*! @{ */
105163 
105164 #define VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_MASK (0xFFFFFFFFU)
105165 #define VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_SHIFT (0U)
105166 /*! SW_REFER9_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 9 */
105167 #define VPU_G2_SWREG118_SW_REFER9_CBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_SHIFT)) & VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_MASK)
105168 /*! @} */
105169 
105170 /*! @name SWREG119 - Base address LSB (bits 31:0) for reference chrominance picture index 9 */
105171 /*! @{ */
105172 
105173 #define VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_MASK (0xFFFFFFFFU)
105174 #define VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_SHIFT (0U)
105175 /*! SW_REFER9_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 9 */
105176 #define VPU_G2_SWREG119_SW_REFER9_CBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_SHIFT)) & VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_MASK)
105177 /*! @} */
105178 
105179 /*! @name SWREG120 - Base address MSB (bits 63:32) for reference chrominance picture index 10 */
105180 /*! @{ */
105181 
105182 #define VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_MASK (0xFFFFFFFFU)
105183 #define VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_SHIFT (0U)
105184 /*! SW_REFER10_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 10 */
105185 #define VPU_G2_SWREG120_SW_REFER10_CBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_SHIFT)) & VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_MASK)
105186 /*! @} */
105187 
105188 /*! @name SWREG121 - Base address LSB (bits 31:0) for reference chrominance picture index 10 */
105189 /*! @{ */
105190 
105191 #define VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_MASK (0xFFFFFFFFU)
105192 #define VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_SHIFT (0U)
105193 /*! SW_REFER10_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 10 */
105194 #define VPU_G2_SWREG121_SW_REFER10_CBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_SHIFT)) & VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_MASK)
105195 /*! @} */
105196 
105197 /*! @name SWREG122 - Base address MSB (bits 63:32) for reference chrominance picture index 11 */
105198 /*! @{ */
105199 
105200 #define VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_MASK (0xFFFFFFFFU)
105201 #define VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_SHIFT (0U)
105202 /*! SW_REFER11_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 11 */
105203 #define VPU_G2_SWREG122_SW_REFER11_CBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_SHIFT)) & VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_MASK)
105204 /*! @} */
105205 
105206 /*! @name SWREG123 - Base address LSB (bits 31:0) for reference chrominance picture index 11 */
105207 /*! @{ */
105208 
105209 #define VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_MASK (0xFFFFFFFFU)
105210 #define VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_SHIFT (0U)
105211 /*! SW_REFER11_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 11 */
105212 #define VPU_G2_SWREG123_SW_REFER11_CBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_SHIFT)) & VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_MASK)
105213 /*! @} */
105214 
105215 /*! @name SWREG124 - Base address MSB (bits 63:32) for reference chrominance picture index 12 */
105216 /*! @{ */
105217 
105218 #define VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_MASK (0xFFFFFFFFU)
105219 #define VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_SHIFT (0U)
105220 /*! SW_REFER12_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 12 */
105221 #define VPU_G2_SWREG124_SW_REFER12_CBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_SHIFT)) & VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_MASK)
105222 /*! @} */
105223 
105224 /*! @name SWREG125 - Base address LSB (bits 31:0) for reference chrominance picture index 12 */
105225 /*! @{ */
105226 
105227 #define VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_MASK (0xFFFFFFFFU)
105228 #define VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_SHIFT (0U)
105229 /*! SW_REFER12_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 12 */
105230 #define VPU_G2_SWREG125_SW_REFER12_CBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_SHIFT)) & VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_MASK)
105231 /*! @} */
105232 
105233 /*! @name SWREG126 - Base address MSB (bits 63:32) for reference chrominance picture index 13 */
105234 /*! @{ */
105235 
105236 #define VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_MASK (0xFFFFFFFFU)
105237 #define VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_SHIFT (0U)
105238 /*! SW_REFER13_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 13 */
105239 #define VPU_G2_SWREG126_SW_REFER13_CBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_SHIFT)) & VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_MASK)
105240 /*! @} */
105241 
105242 /*! @name SWREG127 - Base address LSB (bits 31:0) for reference chrominance picture index 13 */
105243 /*! @{ */
105244 
105245 #define VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_MASK (0xFFFFFFFFU)
105246 #define VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_SHIFT (0U)
105247 /*! SW_REFER13_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 13 */
105248 #define VPU_G2_SWREG127_SW_REFER13_CBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_SHIFT)) & VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_MASK)
105249 /*! @} */
105250 
105251 /*! @name SWREG128 - Base address MSB (bits 63:32) for reference chrominance picture index 14 */
105252 /*! @{ */
105253 
105254 #define VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_MASK (0xFFFFFFFFU)
105255 #define VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_SHIFT (0U)
105256 /*! SW_REFER14_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 14 */
105257 #define VPU_G2_SWREG128_SW_REFER14_CBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_SHIFT)) & VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_MASK)
105258 /*! @} */
105259 
105260 /*! @name SWREG129 - Base address LSB (bits 31:0) for reference chrominance picture index 14 */
105261 /*! @{ */
105262 
105263 #define VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_MASK (0xFFFFFFFFU)
105264 #define VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_SHIFT (0U)
105265 /*! SW_REFER14_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 14 */
105266 #define VPU_G2_SWREG129_SW_REFER14_CBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_SHIFT)) & VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_MASK)
105267 /*! @} */
105268 
105269 /*! @name SWREG130 - Base address MSB (bits 63:32) for reference chrominance picture index 15 */
105270 /*! @{ */
105271 
105272 #define VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_MASK (0xFFFFFFFFU)
105273 #define VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_SHIFT (0U)
105274 /*! SW_REFER15_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 15 */
105275 #define VPU_G2_SWREG130_SW_REFER15_CBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_SHIFT)) & VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_MASK)
105276 /*! @} */
105277 
105278 /*! @name SWREG131 - Base address LSB (bits 31:0) for reference chrominance picture index 15 */
105279 /*! @{ */
105280 
105281 #define VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_MASK (0xFFFFFFFFU)
105282 #define VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_SHIFT (0U)
105283 /*! SW_REFER15_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 15 */
105284 #define VPU_G2_SWREG131_SW_REFER15_CBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_SHIFT)) & VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_MASK)
105285 /*! @} */
105286 
105287 /*! @name SWREG132 - Base address MSB (bits 63:32) for decoded direct mode MVS */
105288 /*! @{ */
105289 
105290 #define VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_MASK (0xFFFFFFFFU)
105291 #define VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_SHIFT (0U)
105292 /*! SW_DEC_OUT_DBASE_MSB - Base address MSB (bits 63:32) for decoded direct mode MVS */
105293 #define VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_SHIFT)) & VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_MASK)
105294 /*! @} */
105295 
105296 /*! @name SWREG133 - Base address LSB (bits 31:0) for decoded direct mode MVS */
105297 /*! @{ */
105298 
105299 #define VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_MASK (0xFFFFFFFFU)
105300 #define VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_SHIFT (0U)
105301 /*! SW_DEC_OUT_DBASE_LSB - Base address LSB (bits 31:0) for decoded direct mode MVS */
105302 #define VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_SHIFT)) & VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_MASK)
105303 /*! @} */
105304 
105305 /*! @name SWREG134 - Base address MSB (bits 63:32) for reference direct mode MVS index 0 */
105306 /*! @{ */
105307 
105308 #define VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_MASK (0xFFFFFFFFU)
105309 #define VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_SHIFT (0U)
105310 /*! SW_REFER0_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 0 */
105311 #define VPU_G2_SWREG134_SW_REFER0_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_SHIFT)) & VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_MASK)
105312 /*! @} */
105313 
105314 /*! @name SWREG135 - Base address LSB (bits 31:0) for reference direct mode MVS index 0 */
105315 /*! @{ */
105316 
105317 #define VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_MASK (0xFFFFFFFFU)
105318 #define VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_SHIFT (0U)
105319 /*! SW_REFER0_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 0 */
105320 #define VPU_G2_SWREG135_SW_REFER0_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_SHIFT)) & VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_MASK)
105321 /*! @} */
105322 
105323 /*! @name SWREG136 - Base address MSB (bits 63:32) for reference direct mode MVS index 1 */
105324 /*! @{ */
105325 
105326 #define VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_MASK (0xFFFFFFFFU)
105327 #define VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_SHIFT (0U)
105328 /*! SW_REFER1_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 1 */
105329 #define VPU_G2_SWREG136_SW_REFER1_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_SHIFT)) & VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_MASK)
105330 /*! @} */
105331 
105332 /*! @name SWREG137 - Base address LSB (bits 31:0) for reference direct mode MVS index 1 */
105333 /*! @{ */
105334 
105335 #define VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_MASK (0xFFFFFFFFU)
105336 #define VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_SHIFT (0U)
105337 /*! SW_REFER1_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 1 */
105338 #define VPU_G2_SWREG137_SW_REFER1_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_SHIFT)) & VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_MASK)
105339 /*! @} */
105340 
105341 /*! @name SWREG138 - Base address MSB (bits 63:32) for reference direct mode MVS index 2 */
105342 /*! @{ */
105343 
105344 #define VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_MASK (0xFFFFFFFFU)
105345 #define VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_SHIFT (0U)
105346 /*! SW_REFER2_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 2 */
105347 #define VPU_G2_SWREG138_SW_REFER2_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_SHIFT)) & VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_MASK)
105348 /*! @} */
105349 
105350 /*! @name SWREG139 - Base address LSB (bits 31:0) for reference direct mode MVS index 2 */
105351 /*! @{ */
105352 
105353 #define VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_MASK (0xFFFFFFFFU)
105354 #define VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_SHIFT (0U)
105355 /*! SW_REFER2_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 2 */
105356 #define VPU_G2_SWREG139_SW_REFER2_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_SHIFT)) & VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_MASK)
105357 /*! @} */
105358 
105359 /*! @name SWREG140 - Base address MSB (bits 63:32) for reference direct mode MVS index 3 */
105360 /*! @{ */
105361 
105362 #define VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_MASK (0xFFFFFFFFU)
105363 #define VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_SHIFT (0U)
105364 /*! SW_REFER3_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 3 */
105365 #define VPU_G2_SWREG140_SW_REFER3_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_SHIFT)) & VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_MASK)
105366 /*! @} */
105367 
105368 /*! @name SWREG141 - Base address LSB (bits 31:0) for reference direct mode MVS index 3 */
105369 /*! @{ */
105370 
105371 #define VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_MASK (0xFFFFFFFFU)
105372 #define VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_SHIFT (0U)
105373 /*! SW_REFER3_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 3 */
105374 #define VPU_G2_SWREG141_SW_REFER3_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_SHIFT)) & VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_MASK)
105375 /*! @} */
105376 
105377 /*! @name SWREG142 - Base address MSB (bits 63:32) for reference direct mode MVS index 4 */
105378 /*! @{ */
105379 
105380 #define VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_MASK (0xFFFFFFFFU)
105381 #define VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_SHIFT (0U)
105382 /*! SW_REFER4_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 4 */
105383 #define VPU_G2_SWREG142_SW_REFER4_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_SHIFT)) & VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_MASK)
105384 /*! @} */
105385 
105386 /*! @name SWREG143 - Base address LSB (bits 31:0) for reference direct mode MVS index 4 */
105387 /*! @{ */
105388 
105389 #define VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_MASK (0xFFFFFFFFU)
105390 #define VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_SHIFT (0U)
105391 /*! SW_REFER4_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 4 */
105392 #define VPU_G2_SWREG143_SW_REFER4_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_SHIFT)) & VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_MASK)
105393 /*! @} */
105394 
105395 /*! @name SWREG144 - Base address MSB (bits 63:32) for reference direct mode MVS index 5 */
105396 /*! @{ */
105397 
105398 #define VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_MASK (0xFFFFFFFFU)
105399 #define VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_SHIFT (0U)
105400 /*! SW_REFER5_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 5 */
105401 #define VPU_G2_SWREG144_SW_REFER5_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_SHIFT)) & VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_MASK)
105402 /*! @} */
105403 
105404 /*! @name SWREG145 - Base address LSB (bits 31:0) for reference direct mode MVS index 5 */
105405 /*! @{ */
105406 
105407 #define VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_MASK (0xFFFFFFFFU)
105408 #define VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_SHIFT (0U)
105409 /*! SW_REFER5_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 5 */
105410 #define VPU_G2_SWREG145_SW_REFER5_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_SHIFT)) & VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_MASK)
105411 /*! @} */
105412 
105413 /*! @name SWREG146 - Base address MSB (bits 63:32) for reference direct mode MVS index 6 */
105414 /*! @{ */
105415 
105416 #define VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_MASK (0xFFFFFFFFU)
105417 #define VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_SHIFT (0U)
105418 /*! SW_REFER6_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 6 */
105419 #define VPU_G2_SWREG146_SW_REFER6_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_SHIFT)) & VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_MASK)
105420 /*! @} */
105421 
105422 /*! @name SWREG147 - Base address LSB (bits 31:0) for reference direct mode MVS index 6 */
105423 /*! @{ */
105424 
105425 #define VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_MASK (0xFFFFFFFFU)
105426 #define VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_SHIFT (0U)
105427 /*! SW_REFER6_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 6 */
105428 #define VPU_G2_SWREG147_SW_REFER6_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_SHIFT)) & VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_MASK)
105429 /*! @} */
105430 
105431 /*! @name SWREG148 - Base address MSB (bits 63:32) for reference direct mode MVS index 7 */
105432 /*! @{ */
105433 
105434 #define VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_MASK (0xFFFFFFFFU)
105435 #define VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_SHIFT (0U)
105436 /*! SW_REFER7_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 7 */
105437 #define VPU_G2_SWREG148_SW_REFER7_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_SHIFT)) & VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_MASK)
105438 /*! @} */
105439 
105440 /*! @name SWREG149 - Base address LSB (bits 31:0) for reference direct mode MVS index 7 */
105441 /*! @{ */
105442 
105443 #define VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_MASK (0xFFFFFFFFU)
105444 #define VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_SHIFT (0U)
105445 /*! SW_REFER7_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 7 */
105446 #define VPU_G2_SWREG149_SW_REFER7_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_SHIFT)) & VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_MASK)
105447 /*! @} */
105448 
105449 /*! @name SWREG150 - Base address MSB (bits 63:32) for reference direct mode MVS index 8 */
105450 /*! @{ */
105451 
105452 #define VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_MASK (0xFFFFFFFFU)
105453 #define VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_SHIFT (0U)
105454 /*! SW_REFER8_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 8 */
105455 #define VPU_G2_SWREG150_SW_REFER8_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_SHIFT)) & VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_MASK)
105456 /*! @} */
105457 
105458 /*! @name SWREG151 - Base address LSB (bits 31:0) for reference direct mode MVS index 8 */
105459 /*! @{ */
105460 
105461 #define VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_MASK (0xFFFFFFFFU)
105462 #define VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_SHIFT (0U)
105463 /*! SW_REFER8_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode mode MVS index 8 */
105464 #define VPU_G2_SWREG151_SW_REFER8_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_SHIFT)) & VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_MASK)
105465 /*! @} */
105466 
105467 /*! @name SWREG152 - Base address MSB (bits 63:32) for reference direct mode mode MVS index 9 */
105468 /*! @{ */
105469 
105470 #define VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_MASK (0xFFFFFFFFU)
105471 #define VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_SHIFT (0U)
105472 /*! SW_REFER9_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 9 */
105473 #define VPU_G2_SWREG152_SW_REFER9_DBASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_SHIFT)) & VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_MASK)
105474 /*! @} */
105475 
105476 /*! @name SWREG153 - Base address LSB (bits 31:0) for reference direct mode mode MVS index 9 */
105477 /*! @{ */
105478 
105479 #define VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_MASK (0xFFFFFFFFU)
105480 #define VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_SHIFT (0U)
105481 /*! SW_REFER9_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode mode MVS index 9 */
105482 #define VPU_G2_SWREG153_SW_REFER9_DBASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_SHIFT)) & VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_MASK)
105483 /*! @} */
105484 
105485 /*! @name SWREG154 - Base address MSB (bits 63:32) for reference direct mode MVS index 10 */
105486 /*! @{ */
105487 
105488 #define VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_MASK (0xFFFFFFFFU)
105489 #define VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_SHIFT (0U)
105490 /*! SW_REFER10_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 10 */
105491 #define VPU_G2_SWREG154_SW_REFER10_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_SHIFT)) & VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_MASK)
105492 /*! @} */
105493 
105494 /*! @name SWREG155 - Base address LSB (bits 31:0) for reference direct mode MVS index 10 */
105495 /*! @{ */
105496 
105497 #define VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_MASK (0xFFFFFFFFU)
105498 #define VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_SHIFT (0U)
105499 /*! SW_REFER10_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 10 */
105500 #define VPU_G2_SWREG155_SW_REFER10_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_SHIFT)) & VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_MASK)
105501 /*! @} */
105502 
105503 /*! @name SWREG156 - Base address MSB (bits 63:32) for reference direct mode MVS index 11 */
105504 /*! @{ */
105505 
105506 #define VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_MASK (0xFFFFFFFFU)
105507 #define VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_SHIFT (0U)
105508 /*! SW_REFER11_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 11 */
105509 #define VPU_G2_SWREG156_SW_REFER11_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_SHIFT)) & VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_MASK)
105510 /*! @} */
105511 
105512 /*! @name SWREG157 - Base address LSB (bits 31:0) for reference direct mode MVS index 11 */
105513 /*! @{ */
105514 
105515 #define VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_MASK (0xFFFFFFFFU)
105516 #define VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_SHIFT (0U)
105517 /*! SW_REFER11_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 11 */
105518 #define VPU_G2_SWREG157_SW_REFER11_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_SHIFT)) & VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_MASK)
105519 /*! @} */
105520 
105521 /*! @name SWREG158 - Base address MSB (bits 63:32) for reference direct mode MVS index 12 */
105522 /*! @{ */
105523 
105524 #define VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_MASK (0xFFFFFFFFU)
105525 #define VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_SHIFT (0U)
105526 /*! SW_REFER12_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 12 */
105527 #define VPU_G2_SWREG158_SW_REFER12_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_SHIFT)) & VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_MASK)
105528 /*! @} */
105529 
105530 /*! @name SWREG159 - Base address LSB (bits 31:0) for reference direct mode MVS index 12 */
105531 /*! @{ */
105532 
105533 #define VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_MASK (0xFFFFFFFFU)
105534 #define VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_SHIFT (0U)
105535 /*! SW_REFER12_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 12 */
105536 #define VPU_G2_SWREG159_SW_REFER12_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_SHIFT)) & VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_MASK)
105537 /*! @} */
105538 
105539 /*! @name SWREG160 - Base address MSB (bits 63:32) for reference direct mode MVS index 13 */
105540 /*! @{ */
105541 
105542 #define VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_MASK (0xFFFFFFFFU)
105543 #define VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_SHIFT (0U)
105544 /*! SW_REFER13_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 13 */
105545 #define VPU_G2_SWREG160_SW_REFER13_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_SHIFT)) & VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_MASK)
105546 /*! @} */
105547 
105548 /*! @name SWREG161 - Base address LSB (bits 31:0) for reference direct mode MVS index 13 */
105549 /*! @{ */
105550 
105551 #define VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_MASK (0xFFFFFFFFU)
105552 #define VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_SHIFT (0U)
105553 /*! SW_REFER13_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 13 */
105554 #define VPU_G2_SWREG161_SW_REFER13_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_SHIFT)) & VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_MASK)
105555 /*! @} */
105556 
105557 /*! @name SWREG162 - Base address MSB (bits 63:32) for reference direct mode MVS index 14 */
105558 /*! @{ */
105559 
105560 #define VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_MASK (0xFFFFFFFFU)
105561 #define VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_SHIFT (0U)
105562 /*! SW_REFER14_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 14 */
105563 #define VPU_G2_SWREG162_SW_REFER14_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_SHIFT)) & VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_MASK)
105564 /*! @} */
105565 
105566 /*! @name SWREG163 - Base address LSB (bits 31:0) for reference direct mode MVS index 14 */
105567 /*! @{ */
105568 
105569 #define VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_MASK (0xFFFFFFFFU)
105570 #define VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_SHIFT (0U)
105571 /*! SW_REFER14_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 14 */
105572 #define VPU_G2_SWREG163_SW_REFER14_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_SHIFT)) & VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_MASK)
105573 /*! @} */
105574 
105575 /*! @name SWREG164 - Base address MSB (bits 63:32) for reference direct mode MVS index 15 */
105576 /*! @{ */
105577 
105578 #define VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_MASK (0xFFFFFFFFU)
105579 #define VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_SHIFT (0U)
105580 /*! SW_REFER15_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 15 */
105581 #define VPU_G2_SWREG164_SW_REFER15_DBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_SHIFT)) & VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_MASK)
105582 /*! @} */
105583 
105584 /*! @name SWREG165 - Base address LSB (bits 31:0) for reference direct mode MVS index 15 */
105585 /*! @{ */
105586 
105587 #define VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_MASK (0xFFFFFFFFU)
105588 #define VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_SHIFT (0U)
105589 /*! SW_REFER15_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 15 */
105590 #define VPU_G2_SWREG165_SW_REFER15_DBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_SHIFT)) & VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_MASK)
105591 /*! @} */
105592 
105593 /*! @name SWREG166 - Base address MSB (bits 63:32) for tile sizes */
105594 /*! @{ */
105595 
105596 #define VPU_G2_SWREG166_SW_TILE_BASE_MSB_MASK    (0xFFFFFFFFU)
105597 #define VPU_G2_SWREG166_SW_TILE_BASE_MSB_SHIFT   (0U)
105598 /*! SW_TILE_BASE_MSB - Base address MSB (bits 63:32) for tile sizes */
105599 #define VPU_G2_SWREG166_SW_TILE_BASE_MSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG166_SW_TILE_BASE_MSB_SHIFT)) & VPU_G2_SWREG166_SW_TILE_BASE_MSB_MASK)
105600 /*! @} */
105601 
105602 /*! @name SWREG167 - Base address LSB (bits 31:0) for tile sizes */
105603 /*! @{ */
105604 
105605 #define VPU_G2_SWREG167_SW_TILE_BASE_LSB_MASK    (0xFFFFFFFFU)
105606 #define VPU_G2_SWREG167_SW_TILE_BASE_LSB_SHIFT   (0U)
105607 /*! SW_TILE_BASE_LSB - Base address LSB (bits 31:0) for tile sizes */
105608 #define VPU_G2_SWREG167_SW_TILE_BASE_LSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG167_SW_TILE_BASE_LSB_SHIFT)) & VPU_G2_SWREG167_SW_TILE_BASE_LSB_MASK)
105609 /*! @} */
105610 
105611 /*! @name SWREG168 - Base address MSB (bits 63:32) for / stream start address/decoded end addr register */
105612 /*! @{ */
105613 
105614 #define VPU_G2_SWREG168_SW_STREAM_BASE_MSB_MASK  (0xFFFFFFFFU)
105615 #define VPU_G2_SWREG168_SW_STREAM_BASE_MSB_SHIFT (0U)
105616 /*! SW_STREAM_BASE_MSB - Base address MSB (bits 63:32) for / stream start address/decoded end addr register */
105617 #define VPU_G2_SWREG168_SW_STREAM_BASE_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG168_SW_STREAM_BASE_MSB_SHIFT)) & VPU_G2_SWREG168_SW_STREAM_BASE_MSB_MASK)
105618 /*! @} */
105619 
105620 /*! @name SWREG169 - Base address LSB (bits 31:0) for / stream start address/decoded end addr register */
105621 /*! @{ */
105622 
105623 #define VPU_G2_SWREG169_SW_STREAM_BASE_LSB_MASK  (0xFFFFFFFFU)
105624 #define VPU_G2_SWREG169_SW_STREAM_BASE_LSB_SHIFT (0U)
105625 /*! SW_STREAM_BASE_LSB - Base address LSB (bits 31:0) for / stream start address/decoded end addr register */
105626 #define VPU_G2_SWREG169_SW_STREAM_BASE_LSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG169_SW_STREAM_BASE_LSB_SHIFT)) & VPU_G2_SWREG169_SW_STREAM_BASE_LSB_MASK)
105627 /*! @} */
105628 
105629 /*! @name SWREG170 - Base address MSB (bits 63:32) for scaling lists / VP9 CTX counter values */
105630 /*! @{ */
105631 
105632 #define VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_MASK (0xFFFFFFFFU)
105633 #define VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_SHIFT (0U)
105634 /*! SW_SCALE_LIST_CTX_COUNTER_BASE_MSB - HEVC: Base address MSB (bits 63:32) for scaling lists VP9: CTX counter values */
105635 #define VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_SHIFT)) & VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_MASK)
105636 /*! @} */
105637 
105638 /*! @name SWREG171 - Base address LSB (bits 31:0) for scaling lists / VP9 CTX counter values */
105639 /*! @{ */
105640 
105641 #define VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_MASK (0xFFFFFFFFU)
105642 #define VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_SHIFT (0U)
105643 /*! SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB - HEVC: Base address LSB (bits 31:0) for scaling lists VP9: CTX counter values */
105644 #define VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_SHIFT)) & VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_MASK)
105645 /*! @} */
105646 
105647 /*! @name SWREG172 - Base address MSB (bits 63:32) for stream propability tables */
105648 /*! @{ */
105649 
105650 #define VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_MASK (0xFFFFFFFFU)
105651 #define VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_SHIFT (0U)
105652 /*! SW_PROB_TAB_BASE_MSB - Base address MSB (bits 63:32) for stream propability tables */
105653 #define VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_SHIFT)) & VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_MASK)
105654 /*! @} */
105655 
105656 /*! @name SWREG173 - Base address LSB (bits 31:0) for stream propability tables */
105657 /*! @{ */
105658 
105659 #define VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_MASK (0xFFFFFFFFU)
105660 #define VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_SHIFT (0U)
105661 /*! SW_PROB_TAB_BASE_LSB - Base address LSB (bits 31:0) for stream propability tables */
105662 #define VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_SHIFT)) & VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_MASK)
105663 /*! @} */
105664 
105665 /*! @name SWREG174 - Base address MSB (bits 63:32) for decoder output raster scan Y picture */
105666 /*! @{ */
105667 
105668 #define VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_MASK (0xFFFFFFFFU)
105669 #define VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_SHIFT (0U)
105670 /*! SW_DEC_RSY_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan Y picture */
105671 #define VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_SHIFT)) & VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_MASK)
105672 /*! @} */
105673 
105674 /*! @name SWREG175 - Base address LSB (bits 31:0) for decoder output raster scan Y picture */
105675 /*! @{ */
105676 
105677 #define VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_MASK (0xFFFFFFFFU)
105678 #define VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_SHIFT (0U)
105679 /*! SW_DEC_RSY_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan Y picture */
105680 #define VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_SHIFT)) & VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_MASK)
105681 /*! @} */
105682 
105683 /*! @name SWREG176 - Base address MSB (bits 63:32) for decoder output raster scan C picture */
105684 /*! @{ */
105685 
105686 #define VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_MASK (0xFFFFFFFFU)
105687 #define VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_SHIFT (0U)
105688 /*! SW_DEC_RSC_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan C picture */
105689 #define VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_SHIFT)) & VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_MASK)
105690 /*! @} */
105691 
105692 /*! @name SWREG177 - Base address LSB (bits 31:0) for decoder output raster scan C picture */
105693 /*! @{ */
105694 
105695 #define VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_MASK (0xFFFFFFFFU)
105696 #define VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_SHIFT (0U)
105697 /*! SW_DEC_RSC_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan C picture */
105698 #define VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_SHIFT)) & VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_MASK)
105699 /*! @} */
105700 
105701 /*! @name SWREG178 - Base address MSB (bits 63:32) for tile border coeffients of filter */
105702 /*! @{ */
105703 
105704 #define VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_MASK (0xFFFFFFFFU)
105705 #define VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_SHIFT (0U)
105706 /*! SW_DEC_VERT_FILT_BASE_MSB - Base address MSB to store/read filtering coeffients of current picture at tile border. */
105707 #define VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_SHIFT)) & VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_MASK)
105708 /*! @} */
105709 
105710 /*! @name SWREG179 - Base address LSB (bits 31:0) for tile border coeffients of filter */
105711 /*! @{ */
105712 
105713 #define VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_MASK (0xFFFFFFFFU)
105714 #define VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_SHIFT (0U)
105715 /*! SW_DEC_VERT_FILT_BASE_LSB - Base address LSB to store/read filtering coeffients of current picture at tile border. */
105716 #define VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_SHIFT)) & VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_MASK)
105717 /*! @} */
105718 
105719 /*! @name SWREG180 - Base address MSB (bits 63:32) for tile border coeffients of sao */
105720 /*! @{ */
105721 
105722 #define VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_MASK (0xFFFFFFFFU)
105723 #define VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_SHIFT (0U)
105724 /*! SW_DEC_VERT_SAO_BASE_MSB - Base address MSB to store/read sao coeffients of current picture at tile border. */
105725 #define VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_SHIFT)) & VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_MASK)
105726 /*! @} */
105727 
105728 /*! @name SWREG181 - Base address LSB (bits 31:0) for tile border coeffients of sao */
105729 /*! @{ */
105730 
105731 #define VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_MASK (0xFFFFFFFFU)
105732 #define VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_SHIFT (0U)
105733 /*! SW_DEC_VERT_SAO_BASE_LSB - Base address LSB to store/read sao coeffients of current picture at tile border. */
105734 #define VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_SHIFT)) & VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_MASK)
105735 /*! @} */
105736 
105737 /*! @name SWREG182 - Base address MSB (bits 63:32) for tile border bsd control data */
105738 /*! @{ */
105739 
105740 #define VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_MASK (0xFFFFFFFFU)
105741 #define VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_SHIFT (0U)
105742 /*! SW_DEC_BSD_CTRL_BASE_MSB - Base address MSB to store/read BSD control data of current picture at tile border. */
105743 #define VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_SHIFT)) & VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_MASK)
105744 /*! @} */
105745 
105746 /*! @name SWREG183 - Base address LSB (bits 31:0) for tile border bsd control data */
105747 /*! @{ */
105748 
105749 #define VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_MASK (0xFFFFFFFFU)
105750 #define VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_SHIFT (0U)
105751 /*! SW_DEC_BSD_CTRL_BASE_LSB - Base address LSB to store/read BSD control data of current picture at tile border. */
105752 #define VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_SHIFT)) & VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_MASK)
105753 /*! @} */
105754 
105755 /*! @name SWREG184 - Raster scan down scale control register MSM */
105756 /*! @{ */
105757 
105758 #define VPU_G2_SWREG184_SW_DEC_DS_X_MASK         (0x3U)
105759 #define VPU_G2_SWREG184_SW_DEC_DS_X_SHIFT        (0U)
105760 /*! SW_DEC_DS_X - X coordinate down scale times for raster scan output picture data
105761  *  0b00..1/2
105762  *  0b01..1/4
105763  *  0b10..1/8
105764  */
105765 #define VPU_G2_SWREG184_SW_DEC_DS_X(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG184_SW_DEC_DS_X_SHIFT)) & VPU_G2_SWREG184_SW_DEC_DS_X_MASK)
105766 
105767 #define VPU_G2_SWREG184_SW_DEC_DS_Y_MASK         (0xCU)
105768 #define VPU_G2_SWREG184_SW_DEC_DS_Y_SHIFT        (2U)
105769 /*! SW_DEC_DS_Y - Y coordinate down scale times for raster scan output picture data
105770  *  0b00..1/2
105771  *  0b01..1/4
105772  *  0b10..1/8
105773  */
105774 #define VPU_G2_SWREG184_SW_DEC_DS_Y(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG184_SW_DEC_DS_Y_SHIFT)) & VPU_G2_SWREG184_SW_DEC_DS_Y_MASK)
105775 
105776 #define VPU_G2_SWREG184_SW_DEC_DS_E_MASK         (0x80U)
105777 #define VPU_G2_SWREG184_SW_DEC_DS_E_SHIFT        (7U)
105778 /*! SW_DEC_DS_E - Raster scan down scale enable
105779  *  0b1..Enable
105780  *  0b0..Disable
105781  */
105782 #define VPU_G2_SWREG184_SW_DEC_DS_E(x)           (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG184_SW_DEC_DS_E_SHIFT)) & VPU_G2_SWREG184_SW_DEC_DS_E_MASK)
105783 /*! @} */
105784 
105785 /*! @name SWREG185 - Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture */
105786 /*! @{ */
105787 
105788 #define VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_MASK (0xFFFFFFFFU)
105789 #define VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_SHIFT (0U)
105790 /*! SW_DEC_DSY_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture */
105791 #define VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_SHIFT)) & VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_MASK)
105792 /*! @} */
105793 
105794 /*! @name SWREG186 - Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture */
105795 /*! @{ */
105796 
105797 #define VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_MASK (0xFFFFFFFFU)
105798 #define VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_SHIFT (0U)
105799 /*! SW_DEC_DSY_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture */
105800 #define VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_SHIFT)) & VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_MASK)
105801 /*! @} */
105802 
105803 /*! @name SWREG187 - Base address MSB (bits 63:32) for decoder output raster scan down scale C picture */
105804 /*! @{ */
105805 
105806 #define VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_MASK (0xFFFFFFFFU)
105807 #define VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_SHIFT (0U)
105808 /*! SW_DEC_DSC_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan down scale C picture */
105809 #define VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_SHIFT)) & VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_MASK)
105810 /*! @} */
105811 
105812 /*! @name SWREG188 - Base address LSB (bits 31:0) for decoder output raster scan down scale C picture */
105813 /*! @{ */
105814 
105815 #define VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_MASK (0xFFFFFFFFU)
105816 #define VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_SHIFT (0U)
105817 /*! SW_DEC_DSC_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan down scale C picture */
105818 #define VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB(x)   (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_SHIFT)) & VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_MASK)
105819 /*! @} */
105820 
105821 /*! @name SWREG189 - Base address MSB (bits 63:32) for decoder output compress luminance table */
105822 /*! @{ */
105823 
105824 #define VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_MASK (0xFFFFFFFFU)
105825 #define VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_SHIFT (0U)
105826 /*! SW_DEC_OUT_TYBASE_MSB - Base address MSB (bits 63:32) for decoder output compress luminance table */
105827 #define VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_MASK)
105828 /*! @} */
105829 
105830 /*! @name SWREG190 - Base address LSB (bits 31:0) for decoder output compress luminance table */
105831 /*! @{ */
105832 
105833 #define VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_MASK (0xFFFFFFFFU)
105834 #define VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_SHIFT (0U)
105835 /*! SW_DEC_OUT_TYBASE_LSB - Base address LSB (bits 31:0) for decoder output compress luminance table */
105836 #define VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_MASK)
105837 /*! @} */
105838 
105839 /*! @name SWREG191 - Base address MSB (bits 63:32) for reference compress luminance table index 0 */
105840 /*! @{ */
105841 
105842 #define VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_MASK (0xFFFFFFFFU)
105843 #define VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_SHIFT (0U)
105844 /*! SW_REFER0_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 0 */
105845 #define VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_MASK)
105846 /*! @} */
105847 
105848 /*! @name SWREG192 - Base address LSB (bits 31:0) for reference compress luminance table index 0 */
105849 /*! @{ */
105850 
105851 #define VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_MASK (0xFFFFFFFFU)
105852 #define VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_SHIFT (0U)
105853 /*! SW_REFER0_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 0 */
105854 #define VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_MASK)
105855 /*! @} */
105856 
105857 /*! @name SWREG193 - Base address MSB (bits 63:32) for reference compress luminance table index 1 */
105858 /*! @{ */
105859 
105860 #define VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_MASK (0xFFFFFFFFU)
105861 #define VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_SHIFT (0U)
105862 /*! SW_REFER1_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 1 */
105863 #define VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_MASK)
105864 /*! @} */
105865 
105866 /*! @name SWREG194 - Base address LSB (bits 31:0) for reference compress luminance table index 1 */
105867 /*! @{ */
105868 
105869 #define VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_MASK (0xFFFFFFFFU)
105870 #define VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_SHIFT (0U)
105871 /*! SW_REFER1_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 1 */
105872 #define VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_MASK)
105873 /*! @} */
105874 
105875 /*! @name SWREG195 - Base address MSB (bits 63:32) for reference compress luminance table index 2 */
105876 /*! @{ */
105877 
105878 #define VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_MASK (0xFFFFFFFFU)
105879 #define VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_SHIFT (0U)
105880 /*! SW_REFER2_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 2 */
105881 #define VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_MASK)
105882 /*! @} */
105883 
105884 /*! @name SWREG196 - Base address LSB (bits 31:0) for reference compress luminance table index 2 */
105885 /*! @{ */
105886 
105887 #define VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_MASK (0xFFFFFFFFU)
105888 #define VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_SHIFT (0U)
105889 /*! SW_REFER2_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 2 */
105890 #define VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_MASK)
105891 /*! @} */
105892 
105893 /*! @name SWREG197 - Base address MSB (bits 63:32) for reference compress luminance table index 3 */
105894 /*! @{ */
105895 
105896 #define VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_MASK (0xFFFFFFFFU)
105897 #define VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_SHIFT (0U)
105898 /*! SW_REFER3_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 3 */
105899 #define VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_MASK)
105900 /*! @} */
105901 
105902 /*! @name SWREG198 - Base address LSB (bits 31:0) for reference compress luminance table index 3 */
105903 /*! @{ */
105904 
105905 #define VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_MASK (0xFFFFFFFFU)
105906 #define VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_SHIFT (0U)
105907 /*! SW_REFER3_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 3 */
105908 #define VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_MASK)
105909 /*! @} */
105910 
105911 /*! @name SWREG199 - Base address MSB (bits 63:32) for reference compress luminance table index 4 */
105912 /*! @{ */
105913 
105914 #define VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_MASK (0xFFFFFFFFU)
105915 #define VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_SHIFT (0U)
105916 /*! SW_REFER4_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 4 */
105917 #define VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_MASK)
105918 /*! @} */
105919 
105920 /*! @name SWREG200 - Base address LSB (bits 31:0) for reference compress luminance table index 4 */
105921 /*! @{ */
105922 
105923 #define VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_MASK (0xFFFFFFFFU)
105924 #define VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_SHIFT (0U)
105925 /*! SW_REFER4_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 4 */
105926 #define VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_MASK)
105927 /*! @} */
105928 
105929 /*! @name SWREG201 - Base address MSB (bits 63:32) for reference compress luminance table index 5 */
105930 /*! @{ */
105931 
105932 #define VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_MASK (0xFFFFFFFFU)
105933 #define VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_SHIFT (0U)
105934 /*! SW_REFER5_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 5 */
105935 #define VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_MASK)
105936 /*! @} */
105937 
105938 /*! @name SWREG202 - Base address LSB (bits 31:0) for reference compress luminance table index 5 */
105939 /*! @{ */
105940 
105941 #define VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_MASK (0xFFFFFFFFU)
105942 #define VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_SHIFT (0U)
105943 /*! SW_REFER5_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 5 */
105944 #define VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_MASK)
105945 /*! @} */
105946 
105947 /*! @name SWREG203 - Base address MSB (bits 63:32) for reference compress luminance table index 6 */
105948 /*! @{ */
105949 
105950 #define VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_MASK (0xFFFFFFFFU)
105951 #define VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_SHIFT (0U)
105952 /*! SW_REFER6_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 6 */
105953 #define VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_MASK)
105954 /*! @} */
105955 
105956 /*! @name SWREG204 - Base address LSB (bits 31:0) for reference compress luminance table index 6 */
105957 /*! @{ */
105958 
105959 #define VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_MASK (0xFFFFFFFFU)
105960 #define VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_SHIFT (0U)
105961 /*! SW_REFER6_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 6 */
105962 #define VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_MASK)
105963 /*! @} */
105964 
105965 /*! @name SWREG205 - Base address MSB (bits 63:32) for reference compress luminance table index 7 */
105966 /*! @{ */
105967 
105968 #define VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_MASK (0xFFFFFFFFU)
105969 #define VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_SHIFT (0U)
105970 /*! SW_REFER7_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 7 */
105971 #define VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_MASK)
105972 /*! @} */
105973 
105974 /*! @name SWREG206 - Base address LSB (bits 31:0) for reference compress luminance table index 7 */
105975 /*! @{ */
105976 
105977 #define VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_MASK (0xFFFFFFFFU)
105978 #define VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_SHIFT (0U)
105979 /*! SW_REFER7_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 7 */
105980 #define VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_MASK)
105981 /*! @} */
105982 
105983 /*! @name SWREG207 - Base address MSB (bits 63:32) for reference compress luminance table index 8 */
105984 /*! @{ */
105985 
105986 #define VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_MASK (0xFFFFFFFFU)
105987 #define VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_SHIFT (0U)
105988 /*! SW_REFER8_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 8 */
105989 #define VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_MASK)
105990 /*! @} */
105991 
105992 /*! @name SWREG208 - Base address LSB (bits 31:0) for reference compress luminance table index 8 */
105993 /*! @{ */
105994 
105995 #define VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_MASK (0xFFFFFFFFU)
105996 #define VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_SHIFT (0U)
105997 /*! SW_REFER8_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 8 */
105998 #define VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_MASK)
105999 /*! @} */
106000 
106001 /*! @name SWREG209 - Base address MSB (bits 63:32) for reference compress luminance table index 9 */
106002 /*! @{ */
106003 
106004 #define VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_MASK (0xFFFFFFFFU)
106005 #define VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_SHIFT (0U)
106006 /*! SW_REFER9_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 9 */
106007 #define VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_MASK)
106008 /*! @} */
106009 
106010 /*! @name SWREG210 - Base address LSB (bits 31:0) for reference compress luminance table index 9 */
106011 /*! @{ */
106012 
106013 #define VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_MASK (0xFFFFFFFFU)
106014 #define VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_SHIFT (0U)
106015 /*! SW_REFER9_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 9 */
106016 #define VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_MASK)
106017 /*! @} */
106018 
106019 /*! @name SWREG211 - Base address MSB (bits 63:32) for reference compress luminance table index 10 */
106020 /*! @{ */
106021 
106022 #define VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_MASK (0xFFFFFFFFU)
106023 #define VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_SHIFT (0U)
106024 /*! SW_REFER10_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 10 */
106025 #define VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_MASK)
106026 /*! @} */
106027 
106028 /*! @name SWREG212 - Base address LSB (bits 31:0) for reference compress luminance table index 10 */
106029 /*! @{ */
106030 
106031 #define VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_MASK (0xFFFFFFFFU)
106032 #define VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_SHIFT (0U)
106033 /*! SW_REFER10_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 10 */
106034 #define VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_MASK)
106035 /*! @} */
106036 
106037 /*! @name SWREG213 - Base address MSB (bits 63:32) for reference compress luminance table index 11 */
106038 /*! @{ */
106039 
106040 #define VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_MASK (0xFFFFFFFFU)
106041 #define VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_SHIFT (0U)
106042 /*! SW_REFER11_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 11 */
106043 #define VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_MASK)
106044 /*! @} */
106045 
106046 /*! @name SWREG214 - Base address LSB (bits 31:0) for reference compress luminance table index 11 */
106047 /*! @{ */
106048 
106049 #define VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_MASK (0xFFFFFFFFU)
106050 #define VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_SHIFT (0U)
106051 /*! SW_REFER11_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 11 */
106052 #define VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_MASK)
106053 /*! @} */
106054 
106055 /*! @name SWREG215 - Base address MSB (bits 63:32) for reference compress luminance table index 12 */
106056 /*! @{ */
106057 
106058 #define VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_MASK (0xFFFFFFFFU)
106059 #define VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_SHIFT (0U)
106060 /*! SW_REFER12_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 12 */
106061 #define VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_MASK)
106062 /*! @} */
106063 
106064 /*! @name SWREG216 - Base address LSB (bits 31:0) for reference compress luminance table index 12 */
106065 /*! @{ */
106066 
106067 #define VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_MASK (0xFFFFFFFFU)
106068 #define VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_SHIFT (0U)
106069 /*! SW_REFER12_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 12 */
106070 #define VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_MASK)
106071 /*! @} */
106072 
106073 /*! @name SWREG217 - Base address MSB (bits 63:32) for reference compress luminance table index 13 */
106074 /*! @{ */
106075 
106076 #define VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_MASK (0xFFFFFFFFU)
106077 #define VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_SHIFT (0U)
106078 /*! SW_REFER13_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 13 */
106079 #define VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_MASK)
106080 /*! @} */
106081 
106082 /*! @name SWREG218 - Base address LSB (bits 31:0) for reference compress luminance table index 13 */
106083 /*! @{ */
106084 
106085 #define VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_MASK (0xFFFFFFFFU)
106086 #define VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_SHIFT (0U)
106087 /*! SW_REFER13_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 13 */
106088 #define VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_MASK)
106089 /*! @} */
106090 
106091 /*! @name SWREG219 - Base address MSB (bits 63:32) for reference compress luminance table index 14 */
106092 /*! @{ */
106093 
106094 #define VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_MASK (0xFFFFFFFFU)
106095 #define VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_SHIFT (0U)
106096 /*! SW_REFER14_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 14 */
106097 #define VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_MASK)
106098 /*! @} */
106099 
106100 /*! @name SWREG220 - Base address LSB (bits 31:0) for reference compress luminance table index 14 */
106101 /*! @{ */
106102 
106103 #define VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_MASK (0xFFFFFFFFU)
106104 #define VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_SHIFT (0U)
106105 /*! SW_REFER14_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 14 */
106106 #define VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_MASK)
106107 /*! @} */
106108 
106109 /*! @name SWREG221 - Base address MSB (bits 63:32) for reference compress luminance table index 15 */
106110 /*! @{ */
106111 
106112 #define VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_MASK (0xFFFFFFFFU)
106113 #define VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_SHIFT (0U)
106114 /*! SW_REFER15_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 15 */
106115 #define VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_MASK)
106116 /*! @} */
106117 
106118 /*! @name SWREG222 - Base address LSB (bits 31:0) for reference compress luminance table index 15 */
106119 /*! @{ */
106120 
106121 #define VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_MASK (0xFFFFFFFFU)
106122 #define VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_SHIFT (0U)
106123 /*! SW_REFER15_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 15 */
106124 #define VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_MASK)
106125 /*! @} */
106126 
106127 /*! @name SWREG223 - Base address MSB (bits 63:32) for decoder output compress chrominance table */
106128 /*! @{ */
106129 
106130 #define VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_MASK (0xFFFFFFFFU)
106131 #define VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_SHIFT (0U)
106132 /*! SW_DEC_OUT_TCBASE_MSB - Base address MSB (bits 63:32) for decoder output compress chrominance table */
106133 #define VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_MASK)
106134 /*! @} */
106135 
106136 /*! @name SWREG224 - Base address LSB (bits 31:0) for decoder output compress chrominance table */
106137 /*! @{ */
106138 
106139 #define VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_MASK (0xFFFFFFFFU)
106140 #define VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_SHIFT (0U)
106141 /*! SW_DEC_OUT_TCBASE_LSB - Base address LSB (bits 31:0) for decoder output compress chrominance table */
106142 #define VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_MASK)
106143 /*! @} */
106144 
106145 /*! @name SWREG225 - Base address MSB (bits 63:32) for reference compress chrominance table index 0 */
106146 /*! @{ */
106147 
106148 #define VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_MASK (0xFFFFFFFFU)
106149 #define VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_SHIFT (0U)
106150 /*! SW_REFER0_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 0 */
106151 #define VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_MASK)
106152 /*! @} */
106153 
106154 /*! @name SWREG226 - Base address LSB (bits 31:0) for reference compress chrominance table index 0 */
106155 /*! @{ */
106156 
106157 #define VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_MASK (0xFFFFFFFFU)
106158 #define VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_SHIFT (0U)
106159 /*! SW_REFER0_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 0 */
106160 #define VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_MASK)
106161 /*! @} */
106162 
106163 /*! @name SWREG227 - Base address MSB (bits 63:32) for reference compress chrominance table index 1 */
106164 /*! @{ */
106165 
106166 #define VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_MASK (0xFFFFFFFFU)
106167 #define VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_SHIFT (0U)
106168 /*! SW_REFER1_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 1 */
106169 #define VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_MASK)
106170 /*! @} */
106171 
106172 /*! @name SWREG228 - Base address LSB (bits 31:0) for reference compress chrominance table index 1 */
106173 /*! @{ */
106174 
106175 #define VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_MASK (0xFFFFFFFFU)
106176 #define VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_SHIFT (0U)
106177 /*! SW_REFER1_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 1 */
106178 #define VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_MASK)
106179 /*! @} */
106180 
106181 /*! @name SWREG229 - Base address MSB (bits 63:32) for reference compress chrominance table index 2 */
106182 /*! @{ */
106183 
106184 #define VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_MASK (0xFFFFFFFFU)
106185 #define VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_SHIFT (0U)
106186 /*! SW_REFER2_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 2 */
106187 #define VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_MASK)
106188 /*! @} */
106189 
106190 /*! @name SWREG230 - Base address LSB (bits 31:0) for reference compress chrominance table index 2 */
106191 /*! @{ */
106192 
106193 #define VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_MASK (0xFFFFFFFFU)
106194 #define VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_SHIFT (0U)
106195 /*! SW_REFER2_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 2 */
106196 #define VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_MASK)
106197 /*! @} */
106198 
106199 /*! @name SWREG231 - Base address MSB (bits 63:32) for reference compress chrominance table index 3 */
106200 /*! @{ */
106201 
106202 #define VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_MASK (0xFFFFFFFFU)
106203 #define VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_SHIFT (0U)
106204 /*! SW_REFER3_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 3 */
106205 #define VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_MASK)
106206 /*! @} */
106207 
106208 /*! @name SWREG232 - Base address LSB (bits 31:0) for reference compress chrominance table index 3 */
106209 /*! @{ */
106210 
106211 #define VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_MASK (0xFFFFFFFFU)
106212 #define VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_SHIFT (0U)
106213 /*! SW_REFER3_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 3 */
106214 #define VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_MASK)
106215 /*! @} */
106216 
106217 /*! @name SWREG233 - Base address MSB (bits 63:32) for reference compress chrominance table index 4 */
106218 /*! @{ */
106219 
106220 #define VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_MASK (0xFFFFFFFFU)
106221 #define VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_SHIFT (0U)
106222 /*! SW_REFER4_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 4 */
106223 #define VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_MASK)
106224 /*! @} */
106225 
106226 /*! @name SWREG234 - Base address LSB (bits 31:0) for reference compress chrominance table index 4 */
106227 /*! @{ */
106228 
106229 #define VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_MASK (0xFFFFFFFFU)
106230 #define VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_SHIFT (0U)
106231 /*! SW_REFER4_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 4 */
106232 #define VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_MASK)
106233 /*! @} */
106234 
106235 /*! @name SWREG235 - Base address MSB (bits 63:32) for reference compress chrominance table index 5 */
106236 /*! @{ */
106237 
106238 #define VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_MASK (0xFFFFFFFFU)
106239 #define VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_SHIFT (0U)
106240 /*! SW_REFER5_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 5 */
106241 #define VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_MASK)
106242 /*! @} */
106243 
106244 /*! @name SWREG236 - Base address LSB (bits 31:0) for reference compress chrominance table index 5 */
106245 /*! @{ */
106246 
106247 #define VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_MASK (0xFFFFFFFFU)
106248 #define VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_SHIFT (0U)
106249 /*! SW_REFER5_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 5 */
106250 #define VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_MASK)
106251 /*! @} */
106252 
106253 /*! @name SWREG237 - Base address MSB (bits 63:32) for reference compress chrominance table index 6 */
106254 /*! @{ */
106255 
106256 #define VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_MASK (0xFFFFFFFFU)
106257 #define VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_SHIFT (0U)
106258 /*! SW_REFER6_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 6 */
106259 #define VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_MASK)
106260 /*! @} */
106261 
106262 /*! @name SWREG238 - Base address LSB (bits 31:0) for reference compress chrominance table index 6 */
106263 /*! @{ */
106264 
106265 #define VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_MASK (0xFFFFFFFFU)
106266 #define VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_SHIFT (0U)
106267 /*! SW_REFER6_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 6 */
106268 #define VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_MASK)
106269 /*! @} */
106270 
106271 /*! @name SWREG239 - Base address MSB (bits 63:32) for reference compress chrominance table index 7 */
106272 /*! @{ */
106273 
106274 #define VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_MASK (0xFFFFFFFFU)
106275 #define VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_SHIFT (0U)
106276 /*! SW_REFER7_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 7 */
106277 #define VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_MASK)
106278 /*! @} */
106279 
106280 /*! @name SWREG240 - Base address LSB (bits 31:0) for reference compress chrominance table index 7 */
106281 /*! @{ */
106282 
106283 #define VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_MASK (0xFFFFFFFFU)
106284 #define VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_SHIFT (0U)
106285 /*! SW_REFER7_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 7 */
106286 #define VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_MASK)
106287 /*! @} */
106288 
106289 /*! @name SWREG241 - Base address MSB (bits 63:32) for reference compress chrominance table index 8 */
106290 /*! @{ */
106291 
106292 #define VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_MASK (0xFFFFFFFFU)
106293 #define VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_SHIFT (0U)
106294 /*! SW_REFER8_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 8 */
106295 #define VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_MASK)
106296 /*! @} */
106297 
106298 /*! @name SWREG242 - Base address LSB (bits 31:0) for reference compress chrominance table index 8 */
106299 /*! @{ */
106300 
106301 #define VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_MASK (0xFFFFFFFFU)
106302 #define VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_SHIFT (0U)
106303 /*! SW_REFER8_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 8 */
106304 #define VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_MASK)
106305 /*! @} */
106306 
106307 /*! @name SWREG243 - Base address MSB (bits 63:32) for reference compress chrominance table index 9 */
106308 /*! @{ */
106309 
106310 #define VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_MASK (0xFFFFFFFFU)
106311 #define VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_SHIFT (0U)
106312 /*! SW_REFER9_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 9 */
106313 #define VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_MASK)
106314 /*! @} */
106315 
106316 /*! @name SWREG244 - Base address LSB (bits 31:0) for reference compress chrominance table index 9 */
106317 /*! @{ */
106318 
106319 #define VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_MASK (0xFFFFFFFFU)
106320 #define VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_SHIFT (0U)
106321 /*! SW_REFER9_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 9 */
106322 #define VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_MASK)
106323 /*! @} */
106324 
106325 /*! @name SWREG245 - Base address MSB (bits 63:32) for reference compress chrominance table index 10 */
106326 /*! @{ */
106327 
106328 #define VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_MASK (0xFFFFFFFFU)
106329 #define VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_SHIFT (0U)
106330 /*! SW_REFER10_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 10 */
106331 #define VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_MASK)
106332 /*! @} */
106333 
106334 /*! @name SWREG246 - Base address LSB (bits 31:0) for reference compress chrominance table index 10 */
106335 /*! @{ */
106336 
106337 #define VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_MASK (0xFFFFFFFFU)
106338 #define VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_SHIFT (0U)
106339 /*! SW_REFER10_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 10 */
106340 #define VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_MASK)
106341 /*! @} */
106342 
106343 /*! @name SWREG247 - Base address MSB (bits 63:32) for reference compress chrominance table index 11 */
106344 /*! @{ */
106345 
106346 #define VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_MASK (0xFFFFFFFFU)
106347 #define VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_SHIFT (0U)
106348 /*! SW_REFER11_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 11 */
106349 #define VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_MASK)
106350 /*! @} */
106351 
106352 /*! @name SWREG248 - Base address LSB (bits 31:0) for reference compress chrominance table index 11 */
106353 /*! @{ */
106354 
106355 #define VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_MASK (0xFFFFFFFFU)
106356 #define VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_SHIFT (0U)
106357 /*! SW_REFER11_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 11 */
106358 #define VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_MASK)
106359 /*! @} */
106360 
106361 /*! @name SWREG249 - Base address MSB (bits 63:32) for reference compress chrominance table index 12 */
106362 /*! @{ */
106363 
106364 #define VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_MASK (0xFFFFFFFFU)
106365 #define VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_SHIFT (0U)
106366 /*! SW_REFER12_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 12 */
106367 #define VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_MASK)
106368 /*! @} */
106369 
106370 /*! @name SWREG250 - Base address LSB (bits 31:0) for reference compress chrominance table index 12 */
106371 /*! @{ */
106372 
106373 #define VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_MASK (0xFFFFFFFFU)
106374 #define VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_SHIFT (0U)
106375 /*! SW_REFER12_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 12 */
106376 #define VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_MASK)
106377 /*! @} */
106378 
106379 /*! @name SWREG251 - Base address MSB (bits 63:32) for reference compress chrominance table index 13 */
106380 /*! @{ */
106381 
106382 #define VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_MASK (0xFFFFFFFFU)
106383 #define VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_SHIFT (0U)
106384 /*! SW_REFER13_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 13 */
106385 #define VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_MASK)
106386 /*! @} */
106387 
106388 /*! @name SWREG252 - Base address LSB (bits 31:0) for reference compress chrominance table index 13 */
106389 /*! @{ */
106390 
106391 #define VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_MASK (0xFFFFFFFFU)
106392 #define VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_SHIFT (0U)
106393 /*! SW_REFER13_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 13 */
106394 #define VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_MASK)
106395 /*! @} */
106396 
106397 /*! @name SWREG253 - Base address MSB (bits 63:32) for reference compress chrominance table index 14 */
106398 /*! @{ */
106399 
106400 #define VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_MASK (0xFFFFFFFFU)
106401 #define VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_SHIFT (0U)
106402 /*! SW_REFER14_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 14 */
106403 #define VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_MASK)
106404 /*! @} */
106405 
106406 /*! @name SWREG254 - Base address LSB (bits 31:0) for reference compress chrominance table index 14 */
106407 /*! @{ */
106408 
106409 #define VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_MASK (0xFFFFFFFFU)
106410 #define VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_SHIFT (0U)
106411 /*! SW_REFER14_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 14 */
106412 #define VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_MASK)
106413 /*! @} */
106414 
106415 /*! @name SWREG255 - Base address MSB (bits 63:32) for reference compress chrominance table index 15 */
106416 /*! @{ */
106417 
106418 #define VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_MASK (0xFFFFFFFFU)
106419 #define VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_SHIFT (0U)
106420 /*! SW_REFER15_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 15 */
106421 #define VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_MASK)
106422 /*! @} */
106423 
106424 /*! @name SWREG256 - Base address LSB (bits 31:0) for reference compress chrominance table index 15 */
106425 /*! @{ */
106426 
106427 #define VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_MASK (0xFFFFFFFFU)
106428 #define VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_SHIFT (0U)
106429 /*! SW_REFER15_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 15 */
106430 #define VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_MASK)
106431 /*! @} */
106432 
106433 /*! @name SWREG258 - input stream buffer length */
106434 /*! @{ */
106435 
106436 #define VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_MASK  (0xFFFFFFFFU)
106437 #define VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_SHIFT (0U)
106438 /*! SW_STRM_BUFFER_LEN - input stream buffer length */
106439 #define VPU_G2_SWREG258_SW_STRM_BUFFER_LEN(x)    (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_SHIFT)) & VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_MASK)
106440 /*! @} */
106441 
106442 /*! @name SWREG259 - input stream buffer start offset */
106443 /*! @{ */
106444 
106445 #define VPU_G2_SWREG259_SW_STRM_START_OFFSET_MASK (0xFFFFFFFFU)
106446 #define VPU_G2_SWREG259_SW_STRM_START_OFFSET_SHIFT (0U)
106447 /*! SW_STRM_START_OFFSET - input stream buffer start offset */
106448 #define VPU_G2_SWREG259_SW_STRM_START_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG259_SW_STRM_START_OFFSET_SHIFT)) & VPU_G2_SWREG259_SW_STRM_START_OFFSET_MASK)
106449 /*! @} */
106450 
106451 
106452 /*!
106453  * @}
106454  */ /* end of group VPU_G2_Register_Masks */
106455 
106456 
106457 /* VPU_G2 - Peripheral instance base addresses */
106458 /** Peripheral VPU_G2 base address */
106459 #define VPU_G2_BASE                              (0x38310000u)
106460 /** Peripheral VPU_G2 base pointer */
106461 #define VPU_G2                                   ((VPU_G2_Type *)VPU_G2_BASE)
106462 /** Array initializer of VPU_G2 peripheral base addresses */
106463 #define VPU_G2_BASE_ADDRS                        { VPU_G2_BASE }
106464 /** Array initializer of VPU_G2 peripheral base pointers */
106465 #define VPU_G2_BASE_PTRS                         { VPU_G2 }
106466 
106467 /*!
106468  * @}
106469  */ /* end of group VPU_G2_Peripheral_Access_Layer */
106470 
106471 
106472 /* ----------------------------------------------------------------------------
106473    -- VPU_H264 Peripheral Access Layer
106474    ---------------------------------------------------------------------------- */
106475 
106476 /*!
106477  * @addtogroup VPU_H264_Peripheral_Access_Layer VPU_H264 Peripheral Access Layer
106478  * @{
106479  */
106480 
106481 /** VPU_H264 - Register Layout Typedef */
106482 typedef struct {
106483        uint8_t RESERVED_0[4];
106484   __IO uint32_t SWREG1;                            /**< Interrupt register encoder, offset: 0x4 */
106485   __IO uint32_t SWREG2;                            /**< Data configuration register0, offset: 0x8 */
106486   __IO uint32_t SWREG3;                            /**< Data configuration register1, offset: 0xC */
106487   __IO uint32_t SWREG4;                            /**< control register 0, offset: 0x10 */
106488   __IO uint32_t SWREG5;                            /**< control register 1, offset: 0x14 */
106489   __IO uint32_t SWREG6;                            /**< control register 2, offset: 0x18 */
106490   __IO uint32_t SWREG7;                            /**< control register 3, offset: 0x1C */
106491   __IO uint32_t SWREG8;                            /**< stream output buffer0 address, offset: 0x20 */
106492   __IO uint32_t SWREG9;                            /**< stream output buffer0 limit size, offset: 0x24 */
106493   __IO uint32_t SWREG10;                           /**< sizeTblBase, offset: 0x28 */
106494   __IO uint32_t SWREG11;                           /**< encoded Picture order count, offset: 0x2C */
106495   __IO uint32_t SWREG12;                           /**< input lum base address, offset: 0x30 */
106496   __IO uint32_t SWREG13;                           /**< input cb base address, offset: 0x34 */
106497   __IO uint32_t SWREG14;                           /**< input cr base address, offset: 0x38 */
106498   __IO uint32_t SWREG15;                           /**< recon image luma base address, offset: 0x3C */
106499   __IO uint32_t SWREG16;                           /**< recon image chroma base address, offset: 0x40 */
106500        uint8_t RESERVED_1[4];
106501   __IO uint32_t SWREG18;                           /**< reference picture reconstructed list0 luma0, offset: 0x48 */
106502   __IO uint32_t SWREG19;                           /**< reference picture reconstructed list0 chroma0, offset: 0x4C */
106503        uint8_t RESERVED_2[8];
106504   __IO uint32_t SWREG22;                           /**< Cyclic Intra, offset: 0x58 */
106505   __IO uint32_t SWREG23;                           /**< intra Area, offset: 0x5C */
106506   __IO uint32_t SWREG24;                           /**< ROI1 Area, offset: 0x60 */
106507   __IO uint32_t SWREG25;                           /**< ROI2 Area, offset: 0x64 */
106508   __IO uint32_t SWREG26_H2V2;                      /**< intra size factors. For H2V2 or later version., offset: 0x68 */
106509   __IO uint32_t SWREG27_H2V2;                      /**< intra mode factors . For H2V2 or later version., offset: 0x6C */
106510   __IO uint32_t SWREG28_H2V5;                      /**< inter me SATD lambda config 0. For H2V5 or later version., offset: 0x70 */
106511   __IO uint32_t SWREG29_H2V5;                      /**< inter me SATD lambda config 1. For H2V5 or later version., offset: 0x74 */
106512   __IO uint32_t SWREG30_H2V5;                      /**< inter me SATD lambda config 2. For H2V5 or later version., offset: 0x78 */
106513   __IO uint32_t SWREG31_H2V5;                      /**< inter me SATD lambda config 3. For H2V5 or later version., offset: 0x7C */
106514   __IO uint32_t SWREG32_H2V5;                      /**< inter me SATD lambda config 4. For H2V5 or later version., offset: 0x80 */
106515   __IO uint32_t SWREG33_H2V5;                      /**< inter me SATD lambda config 5. For H2V5 or later version., offset: 0x84 */
106516   __IO uint32_t SWREG34_H2V5;                      /**< inter me SATD lambda config 6. For H2V5 or later version., offset: 0x88 */
106517   __IO uint32_t SWREG35;                           /**< inter prediction parameters1, offset: 0x8C */
106518   __IO uint32_t SWREG36;                           /**< inter prediction parameters2, offset: 0x90 */
106519   __IO uint32_t SWREG37;                           /**< SAO lambda parameter, offset: 0x94 */
106520   __IO uint32_t SWREG38;                           /**< Pre-processor configuration, offset: 0x98 */
106521   __IO uint32_t SWREG39;                           /**< Pre-processor color conversion parameters0, offset: 0x9C */
106522   __IO uint32_t SWREG40;                           /**< Pre-processor color conversion parameters1, offset: 0xA0 */
106523   __IO uint32_t SWREG41;                           /**< Pre-processor color conversion parameters2, offset: 0xA4 */
106524   __IO uint32_t SWREG42;                           /**< Pre-processor Base address for down-scaled output, offset: 0xA8 */
106525   __IO uint32_t SWREG43;                           /**< Pre-processor down-scaled configuration0, offset: 0xAC */
106526   __IO uint32_t SWREG44;                           /**< Pre-processor down-scaled configuration1, offset: 0xB0 */
106527   __IO uint32_t SWREG45;                           /**< Pre-processor down-scaled configuration2, offset: 0xB4 */
106528   __IO uint32_t SWREG46;                           /**< compressed coefficients base address for SAN module., offset: 0xB8 */
106529        uint8_t RESERVED_3[52];
106530   __IO uint32_t SWREG60;                           /**< Base address for recon luma compress table LSB., offset: 0xF0 */
106531        uint8_t RESERVED_4[4];
106532   __IO uint32_t SWREG62;                           /**< Base address for recon Chroma compress table LSB, offset: 0xF8 */
106533        uint8_t RESERVED_5[4];
106534   __IO uint32_t SWREG64;                           /**< Base address for list 0 ref 0 luma compress table LSB., offset: 0x100 */
106535        uint8_t RESERVED_6[4];
106536   __IO uint32_t SWREG66;                           /**< Base address for list 0 ref 0 Chroma compress table LSB., offset: 0x108 */
106537        uint8_t RESERVED_7[20];
106538   __IO uint32_t SWREG72;                           /**< Base address for recon luma 4n base LSB., offset: 0x120 */
106539        uint8_t RESERVED_8[4];
106540   __IO uint32_t SWREG74;                           /**< reference picture reconstructed list0 4n 0, offset: 0x128 */
106541        uint8_t RESERVED_9[12];
106542   __IO uint32_t SWREG78_H2V5;                      /**< inter me SATD lambda config 7. For H2V5 or later version., offset: 0x138 */
106543   __IO uint32_t SWREG79_H2V5;                      /**< inter me SSE lambda config 0. For H2V5 or later version., offset: 0x13C */
106544   __I  uint32_t SWREG80;                           /**< HW synthesis config register, read-only, offset: 0x140 */
106545   __IO uint32_t SWREG81;                           /**< hardware configuation 0, offset: 0x144 */
106546   __I  uint32_t SWREG82;                           /**< record hardware performance, offset: 0x148 */
106547   __IO uint32_t SWREG83;                           /**< reference picture reconstructed list1 luma0, offset: 0x14C */
106548   __IO uint32_t SWREG84;                           /**< reference picture reconstructed list1 chroma0, offset: 0x150 */
106549        uint8_t RESERVED_10[24];
106550   __IO uint32_t SWREG91;                           /**< reference pictures list1 config, offset: 0x16C */
106551   __IO uint32_t SWREG92;                           /**< reference picture reconstructed list1 4n 0, offset: 0x170 */
106552        uint8_t RESERVED_11[12];
106553   __IO uint32_t SWREG96;                           /**< Base address for list 1 ref 0 luma compress table LSB., offset: 0x180 */
106554        uint8_t RESERVED_12[4];
106555   __IO uint32_t SWREG98;                           /**< Base address for list 1 ref 0 Chroma compress table LSB., offset: 0x188 */
106556        uint8_t RESERVED_13[28];
106557   __IO uint32_t SWREG106;                          /**< Min picture size, offset: 0x1A8 */
106558   __IO uint32_t SWREG107;                          /**< Max picture size, offset: 0x1AC */
106559        uint8_t RESERVED_14[4];
106560   __IO uint32_t SWREG109;                          /**< Qp delta map, offset: 0x1B4 */
106561        uint8_t RESERVED_15[4];
106562   __I  uint32_t SWREG111;                          /**< adaptive GOP configuration1, offset: 0x1BC */
106563   __I  uint32_t SWREG112;                          /**< adaptive GOP configuration2, offset: 0x1C0 */
106564   __IO uint32_t SWREG113;                          /**< adaptive GOP configuration3, offset: 0x1C4 */
106565   __IO uint32_t SWREG114;                          /**< ctb rate control bit memory address of current frame, offset: 0x1C8 */
106566        uint8_t RESERVED_16[4];
106567   __IO uint32_t SWREG116;                          /**< ctb rate control bit memory address of previous frame, offset: 0x1D0 */
106568        uint8_t RESERVED_17[8];
106569   __IO uint32_t SWREG119;                          /**< min/max lcu bits number of last picture, offset: 0x1DC */
106570   __IO uint32_t SWREG120;                          /**< total bits number of all lcus of last picture not including slice header bits, offset: 0x1E0 */
106571        uint8_t RESERVED_18[4];
106572   __IO uint32_t SWREG122_H2V5;                     /**< inter me SSE lambda config 1. For H2V5 or later version., offset: 0x1E8 */
106573   __IO uint32_t SWREG123_H2V5;                     /**< inter me SSE lambda config 2. For H2V5 or later version., offset: 0x1EC */
106574   __IO uint32_t SWREG124_H2V5;                     /**< inter me SSE lambda config 3. For H2V5 or later version., offset: 0x1F0 */
106575   __IO uint32_t SWREG125;                          /**< intra SATD lambda config 0, offset: 0x1F4 */
106576   __IO uint32_t SWREG126;                          /**< intra SATD lambda config 1, offset: 0x1F8 */
106577   __IO uint32_t SWREG127;                          /**< intra SATD lambda config 2, offset: 0x1FC */
106578   __IO uint32_t SWREG128;                          /**< intra SATD lambda config 3, offset: 0x200 */
106579   __IO uint32_t SWREG129;                          /**< intra SATD lambda config 4, offset: 0x204 */
106580   __IO uint32_t SWREG130;                          /**< intra SATD lambda config 5, offset: 0x208 */
106581   __IO uint32_t SWREG131;                          /**< intra SATD lambda config 6, offset: 0x20C */
106582   __IO uint32_t SWREG132;                          /**< intra SATD lambda config 7, offset: 0x210 */
106583   __IO uint32_t SWREG133;                          /**< SSE devide 256, offset: 0x214 */
106584        uint8_t RESERVED_19[16];
106585   __IO uint32_t SWREG138_H2V5;                     /**< inter me SSE lambda config 4. For H2V5 or later version., offset: 0x228 */
106586   __IO uint32_t SWREG139_H2V5;                     /**< inter me SSE lambda config 5. For H2V5 or later version., offset: 0x22C */
106587   __IO uint32_t SWREG140_H2V5;                     /**< inter me SSE lambda config 6. For H2V5 or later version., offset: 0x230 */
106588   __IO uint32_t SWREG141_H2V5;                     /**< inter me SSE lambda config 7. For H2V5 or later version., offset: 0x234 */
106589   __IO uint32_t SWREG142_H2V5;                     /**< inter me SSE lambda config 8. For H2V5 or later version., offset: 0x238 */
106590   __IO uint32_t SWREG143_H2V5;                     /**< inter me SSE lambda config 9. For H2V5 or later version., offset: 0x23C */
106591   __IO uint32_t SWREG144_H2V5;                     /**< inter me SSE lambda config 10. For H2V5 or later version., offset: 0x240 */
106592   __IO uint32_t SWREG145_H2V5;                     /**< inter me SSE lambda config 11. For H2V5 or later version., offset: 0x244 */
106593   __IO uint32_t SWREG146_H2V5;                     /**< inter me SSE lambda config 12. For H2V5 or later version., offset: 0x248 */
106594   __IO uint32_t SWREG147_H2V5;                     /**< inter me SSE lambda config 13. For H2V5 or later version., offset: 0x24C */
106595   __IO uint32_t SWREG148_H2V5;                     /**< inter me SSE lambda config 14. For H2V5 or later version., offset: 0x250 */
106596   __IO uint32_t SWREG149_H2V5;                     /**< inter me SSE lambda config 15. For H2V5 or later version., offset: 0x254 */
106597   __IO uint32_t SWREG150;                          /**< inter me SATD lambda config 8, offset: 0x258 */
106598   __IO uint32_t SWREG151;                          /**< inter me SATD lambda config 9, offset: 0x25C */
106599   __IO uint32_t SWREG152;                          /**< inter me SATD lambda config 10, offset: 0x260 */
106600   __IO uint32_t SWREG153;                          /**< inter me SATD lambda config 11, offset: 0x264 */
106601   __IO uint32_t SWREG154;                          /**< inter me SATD lambda config 12, offset: 0x268 */
106602   __IO uint32_t SWREG155;                          /**< inter me SATD lambda config 13, offset: 0x26C */
106603   __IO uint32_t SWREG156;                          /**< inter me SATD lambda config 14, offset: 0x270 */
106604   __IO uint32_t SWREG157;                          /**< inter me SATD lambda config 15, offset: 0x274 */
106605   __IO uint32_t SWREG158;                          /**< inter me SSE lambda config 16, offset: 0x278 */
106606   __IO uint32_t SWREG159;                          /**< inter me SSE lambda config 17, offset: 0x27C */
106607   __IO uint32_t SWREG160;                          /**< inter me SSE lambda config 18, offset: 0x280 */
106608   __IO uint32_t SWREG161;                          /**< inter me SSE lambda config 19, offset: 0x284 */
106609   __IO uint32_t SWREG162;                          /**< inter me SSE lambda config 20, offset: 0x288 */
106610   __IO uint32_t SWREG163;                          /**< inter me SSE lambda config 21, offset: 0x28C */
106611   __IO uint32_t SWREG164;                          /**< inter me SSE lambda config 22, offset: 0x290 */
106612   __IO uint32_t SWREG165;                          /**< inter me SSE lambda config 23, offset: 0x294 */
106613   __IO uint32_t SWREG166;                          /**< inter me SSE lambda config 24, offset: 0x298 */
106614   __IO uint32_t SWREG167;                          /**< inter me SSE lambda config 25, offset: 0x29C */
106615   __IO uint32_t SWREG168;                          /**< inter me SSE lambda config 26, offset: 0x2A0 */
106616   __IO uint32_t SWREG169;                          /**< inter me SSE lambda config 27, offset: 0x2A4 */
106617        uint8_t RESERVED_20[8];
106618   __IO uint32_t SWREG172;                          /**< inter me SSE lambda config 30, offset: 0x2B0 */
106619   __IO uint32_t SWREG173;                          /**< inter me SSE lambda config 31, offset: 0x2B4 */
106620   __IO uint32_t SWREG174;                          /**< intra SATD lambda config 8, offset: 0x2B8 */
106621   __IO uint32_t SWREG175;                          /**< intra SATD lambda config 9, offset: 0x2BC */
106622   __IO uint32_t SWREG176;                          /**< intra SATD lambda config 10, offset: 0x2C0 */
106623   __IO uint32_t SWREG177;                          /**< intra SATD lambda config 11, offset: 0x2C4 */
106624   __IO uint32_t SWREG178;                          /**< intra SATD lambda config 12, offset: 0x2C8 */
106625   __IO uint32_t SWREG179;                          /**< intra SATD lambda config 13, offset: 0x2CC */
106626   __IO uint32_t SWREG180;                          /**< intra SATD lambda config 14, offset: 0x2D0 */
106627   __IO uint32_t SWREG181;                          /**< intra SATD lambda config 15, offset: 0x2D4 */
106628   __IO uint32_t SWREG182;                          /**< qp fractional part, offset: 0x2D8 */
106629   __I  uint32_t SWREG183;                          /**< qp sum, offset: 0x2DC */
106630   __I  uint32_t SWREG184;                          /**< qp num, offset: 0x2E0 */
106631   __IO uint32_t SWREG185;                          /**< picture complexity. Timeout cycles MSB., offset: 0x2E4 */
106632        uint8_t RESERVED_21[16];
106633   __IO uint32_t SWREG190;                          /**< Long-term reference pictures config, offset: 0x2F8 */
106634   __IO uint32_t SWREG191;                          /**< Temporal scalable config, offset: 0x2FC */
106635   __IO uint32_t SWREG192;                          /**< encoded Picture frame number (for H.264), offset: 0x300 */
106636   __IO uint32_t SWREG193;                          /**< reference pictures list0 config (for H.264), offset: 0x304 */
106637   __IO uint32_t SWREG194;                          /**< reference pictures list1 config (for H.264), offset: 0x308 */
106638   __IO uint32_t SWREG195;                          /**< register extension for ctu_size=16, offset: 0x30C */
106639   __IO uint32_t SWREG196;                          /**< Low Latency Controls, offset: 0x310 */
106640   __IO uint32_t SWREG197;                          /**< Delta POC extension, offset: 0x314 */
106641   __IO uint32_t SWREG198;                          /**< Long Term Reference Control, offset: 0x318 */
106642   __IO uint32_t SWREG199;                          /**< Hash Code Control, offset: 0x31C */
106643   __IO uint32_t SWREG200;                          /**< Hash Code Value, offset: 0x320 */
106644   __IO uint32_t SWREG201;                          /**< Background SKIP Control 0, offset: 0x324 */
106645        uint8_t RESERVED_22[4];
106646   __IO uint32_t SWREG203;                          /**< Background SKIP Control 2, offset: 0x32C */
106647        uint8_t RESERVED_23[16];
106648   __IO uint32_t SWREG208;                          /**< Background SKIP Control 7, offset: 0x340 */
106649   __IO uint32_t SWREG209;                          /**< IPCM Control 0, offset: 0x344 */
106650   __IO uint32_t SWREG210;                          /**< IPCM Control 1, offset: 0x348 */
106651   __IO uint32_t SWREG211;                          /**< IPCM Control 2, offset: 0x34C */
106652   __IO uint32_t SWREG212;                          /**< IPCM Control 3, offset: 0x350 */
106653   __IO uint32_t SWREG213;                          /**< IPCM Control 4, offset: 0x354 */
106654   __I  uint32_t SWREG214;                          /**< HW synthesis config register 2, read-only, offset: 0x358 */
106655   __I  uint32_t SWREG215;                          /**< AXI Information 0, offset: 0x35C */
106656   __I  uint32_t SWREG216;                          /**< AXI Information 1, offset: 0x360 */
106657   __I  uint32_t SWREG217;                          /**< AXI Information 2, offset: 0x364 */
106658   __I  uint32_t SWREG218;                          /**< AXI Information 3, offset: 0x368 */
106659   __I  uint32_t SWREG219;                          /**< AXI Information 4, offset: 0x36C */
106660   __I  uint32_t SWREG220;                          /**< AXI Information 5, offset: 0x370 */
106661   __I  uint32_t SWREG221;                          /**< AXI Information 6, offset: 0x374 */
106662   __I  uint32_t SWREG222;                          /**< AXI Information 7, offset: 0x378 */
106663   __I  uint32_t SWREG223;                          /**< AXI Information 8, offset: 0x37C */
106664   __IO uint32_t SWREG224;                          /**< control register 4, offset: 0x380 */
106665   __IO uint32_t SWREG225;                          /**< Tile Control, offset: 0x384 */
106666   __I  uint32_t SWREG226;                          /**< HW synthesis config register 3, read-only, offset: 0x388 */
106667        uint8_t RESERVED_24[32];
106668   __IO uint32_t SWREG235;                          /**< RPS encoding control 0, offset: 0x3AC */
106669   __IO uint32_t SWREG236;                          /**< RPS encoding control 1, offset: 0x3B0 */
106670   __IO uint32_t SWREG237;                          /**< Stride Control, offset: 0x3B4 */
106671   __IO uint32_t SWREG238;                          /**< Dummy Read, offset: 0x3B8 */
106672   __IO uint32_t SWREG239;                          /**< Base Address LSB of CTB MADs of current frame., offset: 0x3BC */
106673        uint8_t RESERVED_25[4];
106674   __IO uint32_t SWREG241;                          /**< Base Address LSB of CTB MADs of previous frame., offset: 0x3C4 */
106675        uint8_t RESERVED_26[4];
106676   __IO uint32_t SWREG243;                          /**< CTB RC Control 0, offset: 0x3CC */
106677   __IO uint32_t SWREG244;                          /**< CTB RC Control 1, offset: 0x3D0 */
106678   __IO uint32_t SWREG245;                          /**< CTB RC Control 2, offset: 0x3D4 */
106679   __IO uint32_t SWREG246;                          /**< CTB RC Control 3, offset: 0x3D8 */
106680   __IO uint32_t SWREG247;                          /**< CTB RC Control 4, offset: 0x3DC */
106681   __IO uint32_t SWREG248;                          /**< CTB RC Control 5, offset: 0x3E0 */
106682   __IO uint32_t SWREG249;                          /**< register extension for 8K width, offset: 0x3E4 */
106683   __IO uint32_t SWREG250;                          /**< Global MV Control 0, offset: 0x3E8 */
106684   __IO uint32_t SWREG251;                          /**< Global MV Control 1, offset: 0x3EC */
106685   __IO uint32_t SWREG252;                          /**< ROI3 Area, offset: 0x3F0 */
106686   __IO uint32_t SWREG253;                          /**< ROI3&4 Area, offset: 0x3F4 */
106687   __IO uint32_t SWREG254;                          /**< ROI4&5 Area, offset: 0x3F8 */
106688   __IO uint32_t SWREG255;                          /**< ROI5 Area, offset: 0x3FC */
106689   __IO uint32_t SWREG256;                          /**< ROI6 Area, offset: 0x400 */
106690   __IO uint32_t SWREG257;                          /**< ROI6&7 Area, offset: 0x404 */
106691   __IO uint32_t SWREG258;                          /**< ROI7&8 Area, offset: 0x408 */
106692   __IO uint32_t SWREG259;                          /**< ROI8 Area, offset: 0x40C */
106693   __IO uint32_t SWREG260;                          /**< ROI qp, offset: 0x410 */
106694   __IO uint32_t SWREG261;                          /**< Stride Control, offset: 0x414 */
106695        uint8_t RESERVED_27[12];
106696   __IO uint32_t SWREG265;                          /**< Multicore sync ctrl, offset: 0x424 */
106697   __IO uint32_t SWREG266;                          /**< Multicore sync address L0 LSB, offset: 0x428 */
106698   __IO uint32_t SWREG267;                          /**< Multicore sync address L0 MSB, offset: 0x42C */
106699   __IO uint32_t SWREG268;                          /**< Multicore sync address L1 LSB, offset: 0x430 */
106700   __IO uint32_t SWREG269;                          /**< Multicore sync address L1 MSB, offset: 0x434 */
106701   __IO uint32_t SWREG270;                          /**< Multicore sync address recon LSB, offset: 0x438 */
106702   __IO uint32_t SWREG271;                          /**< Multicore sync address recon MSB, offset: 0x43C */
106703   __IO uint32_t SWREG272;                          /**< Programmable AXI urgent sideband signals, offset: 0x440 */
106704   __IO uint32_t SWREG273;                          /**< roimap cu ctrl index address LSB, offset: 0x444 */
106705   __IO uint32_t SWREG274;                          /**< roimap cu ctrl index address MSB, offset: 0x448 */
106706   __IO uint32_t SWREG275;                          /**< roimap cu ctrl address LSB, offset: 0x44C */
106707   __IO uint32_t SWREG276;                          /**< roimap cu ctrl address MSB, offset: 0x450 */
106708   __IO uint32_t SWREG277;                          /**< poc type/bits setting, offset: 0x454 */
106709   __IO uint32_t SWREG278;                          /**< stream output buffer1 address, offset: 0x458 */
106710        uint8_t RESERVED_28[4];
106711   __IO uint32_t SWREG280;                          /**< stream output buffer1 limit size, offset: 0x460 */
106712   __IO uint32_t SWREG281;                          /**< poc type/bits setting, offset: 0x464 */
106713        uint8_t RESERVED_29[20];
106714   __I  uint32_t SWREG287;                          /**< HW synthesis config register 4, read-only, offset: 0x47C */
106715        uint8_t RESERVED_30[4];
106716   __IO uint32_t SWREG289;                          /**< Pre-processor color conversion parameters1, offset: 0x484 */
106717 } VPU_H264_Type;
106718 
106719 /* ----------------------------------------------------------------------------
106720    -- VPU_H264 Register Masks
106721    ---------------------------------------------------------------------------- */
106722 
106723 /*!
106724  * @addtogroup VPU_H264_Register_Masks VPU_H264 Register Masks
106725  * @{
106726  */
106727 
106728 /*! @name SWREG1 - Interrupt register encoder */
106729 /*! @{ */
106730 
106731 #define VPU_H264_SWREG1_SW_ENC_IRQ_MASK          (0x1U)
106732 #define VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT         (0U)
106733 #define VPU_H264_SWREG1_SW_ENC_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
106734 
106735 #define VPU_H264_SWREG1_SW_ENC_IRQ_DIS_MASK      (0x2U)
106736 #define VPU_H264_SWREG1_SW_ENC_IRQ_DIS_SHIFT     (1U)
106737 #define VPU_H264_SWREG1_SW_ENC_IRQ_DIS(x)        (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_DIS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_DIS_MASK)
106738 
106739 #define VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK (0x4U)
106740 #define VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT (2U)
106741 #define VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK)
106742 
106743 #define VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK (0x8U)
106744 #define VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT (3U)
106745 #define VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK)
106746 
106747 #define VPU_H264_SWREG1_SW_ENC_SW_RESET_MASK     (0x10U)
106748 #define VPU_H264_SWREG1_SW_ENC_SW_RESET_SHIFT    (4U)
106749 #define VPU_H264_SWREG1_SW_ENC_SW_RESET(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_SW_RESET_SHIFT)) & VPU_H264_SWREG1_SW_ENC_SW_RESET_MASK)
106750 
106751 #define VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_MASK  (0x20U)
106752 #define VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_SHIFT (5U)
106753 #define VPU_H264_SWREG1_SW_ENC_BUFFER_FULL(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_SHIFT)) & VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_MASK)
106754 
106755 #define VPU_H264_SWREG1_SW_ENC_TIMEOUT_MASK      (0x40U)
106756 #define VPU_H264_SWREG1_SW_ENC_TIMEOUT_SHIFT     (6U)
106757 #define VPU_H264_SWREG1_SW_ENC_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_TIMEOUT_SHIFT)) & VPU_H264_SWREG1_SW_ENC_TIMEOUT_MASK)
106758 
106759 #define VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK (0x80U)
106760 #define VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT (7U)
106761 #define VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK)
106762 
106763 #define VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK (0x100U)
106764 #define VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT (8U)
106765 #define VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK)
106766 
106767 #define VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK (0x200U)
106768 #define VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT (9U)
106769 #define VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK)
106770 
106771 #define VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_MASK  (0x800U)
106772 #define VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT (11U)
106773 #define VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT)) & VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_MASK)
106774 
106775 #define VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK (0x1000U)
106776 #define VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT (12U)
106777 #define VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT)) & VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK)
106778 /*! @} */
106779 
106780 /*! @name SWREG2 - Data configuration register0 */
106781 /*! @{ */
106782 
106783 #define VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK (0xFU)
106784 #define VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT (0U)
106785 #define VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK)
106786 
106787 #define VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK (0xF0U)
106788 #define VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT (4U)
106789 #define VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK)
106790 
106791 #define VPU_H264_SWREG2_SW_ENC_PIC_SWAP_MASK     (0xF00U)
106792 #define VPU_H264_SWREG2_SW_ENC_PIC_SWAP_SHIFT    (8U)
106793 #define VPU_H264_SWREG2_SW_ENC_PIC_SWAP(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_PIC_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_PIC_SWAP_MASK)
106794 
106795 #define VPU_H264_SWREG2_SW_ENC_STRM_SWAP_MASK    (0xF000U)
106796 #define VPU_H264_SWREG2_SW_ENC_STRM_SWAP_SHIFT   (12U)
106797 #define VPU_H264_SWREG2_SW_ENC_STRM_SWAP(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_STRM_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_STRM_SWAP_MASK)
106798 
106799 #define VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_MASK  (0xFF0000U)
106800 #define VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_SHIFT (16U)
106801 #define VPU_H264_SWREG2_SW_ENC_AXI_READ_ID(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_SHIFT)) & VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_MASK)
106802 
106803 #define VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_MASK (0xFF000000U)
106804 #define VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT (24U)
106805 #define VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT)) & VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_MASK)
106806 /*! @} */
106807 
106808 /*! @name SWREG3 - Data configuration register1 */
106809 /*! @{ */
106810 
106811 #define VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK (0x2U)
106812 #define VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT (1U)
106813 #define VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT)) & VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK)
106814 
106815 #define VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK (0x4U)
106816 #define VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT (2U)
106817 #define VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT)) & VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK)
106818 
106819 #define VPU_H264_SWREG3_SW_ENC_SLICE_INT_MASK    (0x8U)
106820 #define VPU_H264_SWREG3_SW_ENC_SLICE_INT_SHIFT   (3U)
106821 #define VPU_H264_SWREG3_SW_ENC_SLICE_INT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_SLICE_INT_SHIFT)) & VPU_H264_SWREG3_SW_ENC_SLICE_INT_MASK)
106822 
106823 #define VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK (0xF00000U)
106824 #define VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT (20U)
106825 #define VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK)
106826 
106827 #define VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_MASK  (0x1000000U)
106828 #define VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT (24U)
106829 /*! SW_ENC_AXI_RD_ID_E
106830  *  0b0..disable.
106831  *  0b1..enable.
106832  */
106833 #define VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_MASK)
106834 
106835 #define VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_MASK  (0x2000000U)
106836 #define VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT (25U)
106837 /*! SW_ENC_AXI_WR_ID_E
106838  *  0b0..disable.
106839  *  0b1..enable.
106840  */
106841 #define VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_MASK)
106842 
106843 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK (0x4000000U)
106844 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT (26U)
106845 /*! SW_ENC_CLOCK_GATE_INTER_H264_E
106846  *  0b0..clock always on.
106847  *  0b1..hardware clock gating control
106848  */
106849 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK)
106850 
106851 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK (0x8000000U)
106852 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT (27U)
106853 /*! SW_ENC_CLOCK_GATE_INTER_H265_E
106854  *  0b0..clock always on.
106855  *  0b1..hardware clock gating control
106856  */
106857 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK)
106858 
106859 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK (0x10000000U)
106860 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT (28U)
106861 /*! SW_ENC_CLOCK_GATE_INTER_E
106862  *  0b0..clock always on.
106863  *  0b1..hardware clock gating control
106864  */
106865 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK)
106866 
106867 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK (0x20000000U)
106868 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT (29U)
106869 /*! SW_ENC_CLOCK_GATE_ENCODER_H264_E
106870  *  0b0..clock always on.
106871  *  0b1..hardware clock gating control
106872  */
106873 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK)
106874 
106875 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK (0x40000000U)
106876 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT (30U)
106877 /*! SW_ENC_CLOCK_GATE_ENCODER_H265_E
106878  *  0b0..clock always on.
106879  *  0b1..hardware clock gating control
106880  */
106881 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK)
106882 
106883 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK (0x80000000U)
106884 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT (31U)
106885 /*! SW_ENC_CLOCK_GATE_ENCODER_E
106886  *  0b0..clock always on.
106887  *  0b1..hardware clock gating control
106888  */
106889 #define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK)
106890 /*! @} */
106891 
106892 /*! @name SWREG4 - control register 0 */
106893 /*! @{ */
106894 
106895 #define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK (0x7U)
106896 #define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT (0U)
106897 #define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK)
106898 
106899 #define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK (0x38U)
106900 #define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT (3U)
106901 #define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK)
106902 
106903 #define VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK (0x100U)
106904 #define VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT (8U)
106905 #define VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT)) & VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK)
106906 
106907 #define VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_MASK (0x800U)
106908 #define VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT (11U)
106909 #define VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT)) & VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_MASK)
106910 
106911 #define VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK (0x3E000U)
106912 #define VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT (13U)
106913 #define VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT)) & VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK)
106914 
106915 #define VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK (0x40000U)
106916 #define VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT (18U)
106917 /*! SW_ENC_OUTPUT_STRM_MODE
106918  *  0b0..byte stream
106919  *  0b1..Nal stream
106920  */
106921 #define VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK)
106922 
106923 #define VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK (0x180000U)
106924 #define VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT (19U)
106925 /*! SW_ENC_MAX_TRB_SIZE
106926  *  0b00..4x4
106927  *  0b01..8x8
106928  *  0b10..16x16
106929  *  0b11..32x32
106930  */
106931 #define VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK)
106932 
106933 #define VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK (0x600000U)
106934 #define VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT (21U)
106935 /*! SW_ENC_MIN_TRB_SIZE
106936  *  0b00..4x4
106937  *  0b01..8x8
106938  *  0b10..16x16
106939  *  0b11..32x32
106940  */
106941 #define VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK)
106942 
106943 #define VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_MASK  (0x1800000U)
106944 #define VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT (23U)
106945 /*! SW_ENC_MAX_CB_SIZE
106946  *  0b00..8x8
106947  *  0b01..16x16
106948  *  0b10..32x32
106949  *  0b11..64x64
106950  */
106951 #define VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_MASK)
106952 
106953 #define VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_MASK  (0x6000000U)
106954 #define VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT (25U)
106955 /*! SW_ENC_MIN_CB_SIZE
106956  *  0b00..8x8
106957  *  0b01..16x16
106958  *  0b10..32x32
106959  *  0b11..64x64
106960  */
106961 #define VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_MASK)
106962 
106963 #define VPU_H264_SWREG4_SW_ENC_MODE_MASK         (0xE0000000U)
106964 #define VPU_H264_SWREG4_SW_ENC_MODE_SHIFT        (29U)
106965 /*! SW_ENC_MODE
106966  *  0b001..hevc.
106967  *  0b010..h264.
106968  *  0b100..jpeg
106969  */
106970 #define VPU_H264_SWREG4_SW_ENC_MODE(x)           (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MODE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MODE_MASK)
106971 /*! @} */
106972 
106973 /*! @name SWREG5 - control register 1 */
106974 /*! @{ */
106975 
106976 #define VPU_H264_SWREG5_SW_ENC_E_MASK            (0x1U)
106977 #define VPU_H264_SWREG5_SW_ENC_E_SHIFT           (0U)
106978 #define VPU_H264_SWREG5_SW_ENC_E(x)              (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_E_SHIFT)) & VPU_H264_SWREG5_SW_ENC_E_MASK)
106979 
106980 #define VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK (0x6U)
106981 #define VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT (1U)
106982 #define VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT)) & VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK)
106983 
106984 #define VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK (0x100U)
106985 #define VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT (8U)
106986 /*! SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG
106987  *  0b0..no
106988  *  0b1..yes
106989  */
106990 #define VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT)) & VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK)
106991 
106992 #define VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK (0x200U)
106993 #define VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT (9U)
106994 /*! SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG
106995  *  0b0..disable
106996  *  0b1..enable
106997  */
106998 #define VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT)) & VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK)
106999 
107000 #define VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_MASK   (0x3FF800U)
107001 #define VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT  (11U)
107002 #define VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT)) & VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_MASK)
107003 
107004 #define VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_MASK    (0xFFC00000U)
107005 #define VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_SHIFT   (22U)
107006 #define VPU_H264_SWREG5_SW_ENC_PIC_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_SHIFT)) & VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_MASK)
107007 /*! @} */
107008 
107009 /*! @name SWREG6 - control register 2 */
107010 /*! @{ */
107011 
107012 #define VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_MASK (0x1U)
107013 #define VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_SHIFT (0U)
107014 #define VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_SHIFT)) & VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_MASK)
107015 
107016 #define VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_MASK (0x2U)
107017 #define VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_SHIFT (1U)
107018 #define VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_SHIFT)) & VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_MASK)
107019 
107020 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_MASK (0x780U)
107021 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_SHIFT (7U)
107022 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_SHIFT)) & VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_MASK)
107023 
107024 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_MASK (0x7800U)
107025 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_SHIFT (11U)
107026 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_SHIFT)) & VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_MASK)
107027 
107028 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_MASK (0x8000U)
107029 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_SHIFT (15U)
107030 /*! SW_ENC_DEBLOCKING_FILTER_CTRL
107031  *  0b1..filtering is disabled for current picture.
107032  *  0b0..filtering is enabled for current picture.
107033  */
107034 #define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_SHIFT)) & VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_MASK)
107035 
107036 #define VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_MASK   (0xFE000000U)
107037 #define VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_SHIFT  (25U)
107038 #define VPU_H264_SWREG6_SW_ENC_SLICE_SIZE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_SHIFT)) & VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_MASK)
107039 /*! @} */
107040 
107041 /*! @name SWREG7 - control register 3 */
107042 /*! @{ */
107043 
107044 #define VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK (0xFU)
107045 #define VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT (0U)
107046 #define VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK)
107047 
107048 #define VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK (0xF0U)
107049 #define VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT (4U)
107050 #define VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK)
107051 
107052 #define VPU_H264_SWREG7_SW_ENC_PIC_QP_MASK       (0x3F00U)
107053 #define VPU_H264_SWREG7_SW_ENC_PIC_QP_SHIFT      (8U)
107054 #define VPU_H264_SWREG7_SW_ENC_PIC_QP(x)         (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_PIC_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_PIC_QP_MASK)
107055 
107056 #define VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK (0xC000U)
107057 #define VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT (14U)
107058 #define VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT)) & VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK)
107059 
107060 #define VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_MASK (0x1FE0000U)
107061 #define VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT (17U)
107062 #define VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT)) & VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_MASK)
107063 
107064 #define VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK (0x2000000U)
107065 #define VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT (25U)
107066 #define VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT)) & VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK)
107067 
107068 #define VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_MASK  (0xFC000000U)
107069 #define VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT (26U)
107070 #define VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_MASK)
107071 /*! @} */
107072 
107073 /*! @name SWREG8 - stream output buffer0 address */
107074 /*! @{ */
107075 
107076 #define VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK (0xFFFFFFFFU)
107077 #define VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT (0U)
107078 #define VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT)) & VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK)
107079 /*! @} */
107080 
107081 /*! @name SWREG9 - stream output buffer0 limit size */
107082 /*! @{ */
107083 
107084 #define VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK (0xFFFFFFFFU)
107085 #define VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT (0U)
107086 #define VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT)) & VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK)
107087 /*! @} */
107088 
107089 /*! @name SWREG10 - sizeTblBase */
107090 /*! @{ */
107091 
107092 #define VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK (0xFFFFFFFFU)
107093 #define VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT (0U)
107094 #define VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT)) & VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK)
107095 /*! @} */
107096 
107097 /*! @name SWREG11 - encoded Picture order count */
107098 /*! @{ */
107099 
107100 #define VPU_H264_SWREG11_SW_ENC_POC_MASK         (0xFFFFFFFFU)
107101 #define VPU_H264_SWREG11_SW_ENC_POC_SHIFT        (0U)
107102 #define VPU_H264_SWREG11_SW_ENC_POC(x)           (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG11_SW_ENC_POC_SHIFT)) & VPU_H264_SWREG11_SW_ENC_POC_MASK)
107103 /*! @} */
107104 
107105 /*! @name SWREG12 - input lum base address */
107106 /*! @{ */
107107 
107108 #define VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_MASK (0xFFFFFFFFU)
107109 #define VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT (0U)
107110 #define VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT)) & VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_MASK)
107111 /*! @} */
107112 
107113 /*! @name SWREG13 - input cb base address */
107114 /*! @{ */
107115 
107116 #define VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_MASK (0xFFFFFFFFU)
107117 #define VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT (0U)
107118 #define VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT)) & VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_MASK)
107119 /*! @} */
107120 
107121 /*! @name SWREG14 - input cr base address */
107122 /*! @{ */
107123 
107124 #define VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_MASK (0xFFFFFFFFU)
107125 #define VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT (0U)
107126 #define VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT)) & VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_MASK)
107127 /*! @} */
107128 
107129 /*! @name SWREG15 - recon image luma base address */
107130 /*! @{ */
107131 
107132 #define VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_MASK (0xFFFFFFFFU)
107133 #define VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT (0U)
107134 #define VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT)) & VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_MASK)
107135 /*! @} */
107136 
107137 /*! @name SWREG16 - recon image chroma base address */
107138 /*! @{ */
107139 
107140 #define VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK (0xFFFFFFFFU)
107141 #define VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT (0U)
107142 #define VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT)) & VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK)
107143 /*! @} */
107144 
107145 /*! @name SWREG18 - reference picture reconstructed list0 luma0 */
107146 /*! @{ */
107147 
107148 #define VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK (0xFFFFFFFFU)
107149 #define VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT (0U)
107150 #define VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT)) & VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK)
107151 /*! @} */
107152 
107153 /*! @name SWREG19 - reference picture reconstructed list0 chroma0 */
107154 /*! @{ */
107155 
107156 #define VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK (0xFFFFFFFFU)
107157 #define VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT (0U)
107158 #define VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT)) & VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK)
107159 /*! @} */
107160 
107161 /*! @name SWREG22 - Cyclic Intra */
107162 /*! @{ */
107163 
107164 #define VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_MASK (0xFU)
107165 #define VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT (0U)
107166 #define VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT)) & VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_MASK)
107167 
107168 #define VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_MASK (0x3FFF0U)
107169 #define VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT (4U)
107170 #define VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT)) & VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_MASK)
107171 
107172 #define VPU_H264_SWREG22_SW_ENC_CIR_START_MASK   (0xFFFC0000U)
107173 #define VPU_H264_SWREG22_SW_ENC_CIR_START_SHIFT  (18U)
107174 #define VPU_H264_SWREG22_SW_ENC_CIR_START(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG22_SW_ENC_CIR_START_SHIFT)) & VPU_H264_SWREG22_SW_ENC_CIR_START_MASK)
107175 /*! @} */
107176 
107177 /*! @name SWREG23 - intra Area */
107178 /*! @{ */
107179 
107180 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK (0xFFU)
107181 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT (0U)
107182 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK)
107183 
107184 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK (0xFF00U)
107185 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT (8U)
107186 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK)
107187 
107188 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK (0xFF0000U)
107189 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT (16U)
107190 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK)
107191 
107192 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK (0xFF000000U)
107193 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT (24U)
107194 #define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK)
107195 /*! @} */
107196 
107197 /*! @name SWREG24 - ROI1 Area */
107198 /*! @{ */
107199 
107200 #define VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_MASK (0xFFU)
107201 #define VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT (0U)
107202 #define VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_MASK)
107203 
107204 #define VPU_H264_SWREG24_SW_ENC_ROI1_TOP_MASK    (0xFF00U)
107205 #define VPU_H264_SWREG24_SW_ENC_ROI1_TOP_SHIFT   (8U)
107206 #define VPU_H264_SWREG24_SW_ENC_ROI1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_TOP_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_TOP_MASK)
107207 
107208 #define VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_MASK  (0xFF0000U)
107209 #define VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT (16U)
107210 #define VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_MASK)
107211 
107212 #define VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_MASK   (0xFF000000U)
107213 #define VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_SHIFT  (24U)
107214 #define VPU_H264_SWREG24_SW_ENC_ROI1_LEFT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_MASK)
107215 /*! @} */
107216 
107217 /*! @name SWREG25 - ROI2 Area */
107218 /*! @{ */
107219 
107220 #define VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_MASK (0xFFU)
107221 #define VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT (0U)
107222 #define VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_MASK)
107223 
107224 #define VPU_H264_SWREG25_SW_ENC_ROI2_TOP_MASK    (0xFF00U)
107225 #define VPU_H264_SWREG25_SW_ENC_ROI2_TOP_SHIFT   (8U)
107226 #define VPU_H264_SWREG25_SW_ENC_ROI2_TOP(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_TOP_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_TOP_MASK)
107227 
107228 #define VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_MASK  (0xFF0000U)
107229 #define VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT (16U)
107230 #define VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_MASK)
107231 
107232 #define VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_MASK   (0xFF000000U)
107233 #define VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_SHIFT  (24U)
107234 #define VPU_H264_SWREG25_SW_ENC_ROI2_LEFT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_MASK)
107235 /*! @} */
107236 
107237 /*! @name SWREG26_H2V2 - intra size factors. For H2V2 or later version. */
107238 /*! @{ */
107239 
107240 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK (0xFFCU)
107241 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT (2U)
107242 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT)) & VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK)
107243 
107244 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK (0x3FF000U)
107245 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT (12U)
107246 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT)) & VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK)
107247 
107248 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK (0xFFC00000U)
107249 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT (22U)
107250 #define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT)) & VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK)
107251 /*! @} */
107252 
107253 /*! @name SWREG27_H2V2 - intra mode factors . For H2V2 or later version. */
107254 /*! @{ */
107255 
107256 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK (0x7F0U)
107257 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT (4U)
107258 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK)
107259 
107260 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK (0x1F800U)
107261 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT (11U)
107262 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK)
107263 
107264 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK (0x3E0000U)
107265 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT (17U)
107266 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK)
107267 
107268 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK (0xFFC00000U)
107269 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT (22U)
107270 #define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK)
107271 /*! @} */
107272 
107273 /*! @name SWREG28_H2V5 - inter me SATD lambda config 0. For H2V5 or later version. */
107274 /*! @{ */
107275 
107276 #define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK (0x7FFC0U)
107277 #define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT (6U)
107278 #define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK)
107279 
107280 #define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK (0xFFF80000U)
107281 #define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT (19U)
107282 #define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK)
107283 /*! @} */
107284 
107285 /*! @name SWREG29_H2V5 - inter me SATD lambda config 1. For H2V5 or later version. */
107286 /*! @{ */
107287 
107288 #define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK (0x7FFC0U)
107289 #define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT (6U)
107290 #define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK)
107291 
107292 #define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK (0xFFF80000U)
107293 #define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT (19U)
107294 #define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK)
107295 /*! @} */
107296 
107297 /*! @name SWREG30_H2V5 - inter me SATD lambda config 2. For H2V5 or later version. */
107298 /*! @{ */
107299 
107300 #define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK (0x7FFC0U)
107301 #define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT (6U)
107302 #define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK)
107303 
107304 #define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK (0xFFF80000U)
107305 #define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT (19U)
107306 #define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK)
107307 /*! @} */
107308 
107309 /*! @name SWREG31_H2V5 - inter me SATD lambda config 3. For H2V5 or later version. */
107310 /*! @{ */
107311 
107312 #define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK (0x7FFC0U)
107313 #define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT (6U)
107314 #define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK)
107315 
107316 #define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK (0xFFF80000U)
107317 #define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT (19U)
107318 #define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK)
107319 /*! @} */
107320 
107321 /*! @name SWREG32_H2V5 - inter me SATD lambda config 4. For H2V5 or later version. */
107322 /*! @{ */
107323 
107324 #define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK (0x7FFC0U)
107325 #define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT (6U)
107326 #define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK)
107327 
107328 #define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK (0xFFF80000U)
107329 #define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT (19U)
107330 #define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK)
107331 /*! @} */
107332 
107333 /*! @name SWREG33_H2V5 - inter me SATD lambda config 5. For H2V5 or later version. */
107334 /*! @{ */
107335 
107336 #define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK (0x7FFC0U)
107337 #define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT (6U)
107338 #define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK)
107339 
107340 #define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK (0xFFF80000U)
107341 #define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT (19U)
107342 #define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK)
107343 /*! @} */
107344 
107345 /*! @name SWREG34_H2V5 - inter me SATD lambda config 6. For H2V5 or later version. */
107346 /*! @{ */
107347 
107348 #define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK (0x7FFC0U)
107349 #define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT (6U)
107350 #define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK)
107351 
107352 #define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK (0xFFF80000U)
107353 #define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT (19U)
107354 #define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK)
107355 /*! @} */
107356 
107357 /*! @name SWREG35 - inter prediction parameters1 */
107358 /*! @{ */
107359 
107360 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK (0xFFU)
107361 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT (0U)
107362 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT)) & VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK)
107363 
107364 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK (0x7F00U)
107365 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT (8U)
107366 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT)) & VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK)
107367 
107368 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK (0x38000U)
107369 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT (15U)
107370 #define VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT)) & VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK)
107371 
107372 #define VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK (0xFFFC0000U)
107373 #define VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT (18U)
107374 #define VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT)) & VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK)
107375 /*! @} */
107376 
107377 /*! @name SWREG36 - inter prediction parameters2 */
107378 /*! @{ */
107379 
107380 #define VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK (0x3U)
107381 #define VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT (0U)
107382 /*! SW_ENC_OUTPUT_BITWIDTH_CHROMA
107383  *  0b00..8 bit.
107384  *  0b01..9 bit.
107385  *  0b10..10 bit.
107386  */
107387 #define VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT)) & VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK)
107388 
107389 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK (0x3CU)
107390 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT (2U)
107391 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT)) & VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK)
107392 
107393 #define VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK (0x1FC0U)
107394 #define VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT (6U)
107395 #define VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT)) & VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK)
107396 
107397 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK (0x7FE000U)
107398 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT (13U)
107399 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT)) & VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK)
107400 
107401 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK (0xFF800000U)
107402 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT (23U)
107403 #define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT)) & VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK)
107404 /*! @} */
107405 
107406 /*! @name SWREG37 - SAO lambda parameter */
107407 /*! @{ */
107408 
107409 #define VPU_H264_SWREG37_SW_ENC_CHROFFSET_MASK   (0xFU)
107410 #define VPU_H264_SWREG37_SW_ENC_CHROFFSET_SHIFT  (0U)
107411 #define VPU_H264_SWREG37_SW_ENC_CHROFFSET(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG37_SW_ENC_CHROFFSET_SHIFT)) & VPU_H264_SWREG37_SW_ENC_CHROFFSET_MASK)
107412 /*! @} */
107413 
107414 /*! @name SWREG38 - Pre-processor configuration */
107415 /*! @{ */
107416 
107417 #define VPU_H264_SWREG38_SW_ENC_MIRROR_MASK      (0x1U)
107418 #define VPU_H264_SWREG38_SW_ENC_MIRROR_SHIFT     (0U)
107419 #define VPU_H264_SWREG38_SW_ENC_MIRROR(x)        (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_MIRROR_SHIFT)) & VPU_H264_SWREG38_SW_ENC_MIRROR_MASK)
107420 
107421 #define VPU_H264_SWREG38_SW_ENC_YFILL_MASK       (0xEU)
107422 #define VPU_H264_SWREG38_SW_ENC_YFILL_SHIFT      (1U)
107423 #define VPU_H264_SWREG38_SW_ENC_YFILL(x)         (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_YFILL_SHIFT)) & VPU_H264_SWREG38_SW_ENC_YFILL_MASK)
107424 
107425 #define VPU_H264_SWREG38_SW_ENC_XFILL_MASK       (0x30U)
107426 #define VPU_H264_SWREG38_SW_ENC_XFILL_SHIFT      (4U)
107427 #define VPU_H264_SWREG38_SW_ENC_XFILL(x)         (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_XFILL_SHIFT)) & VPU_H264_SWREG38_SW_ENC_XFILL_MASK)
107428 
107429 #define VPU_H264_SWREG38_SW_ENC_ROWLENGTH_MASK   (0xFFFC0U)
107430 #define VPU_H264_SWREG38_SW_ENC_ROWLENGTH_SHIFT  (6U)
107431 #define VPU_H264_SWREG38_SW_ENC_ROWLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_ROWLENGTH_SHIFT)) & VPU_H264_SWREG38_SW_ENC_ROWLENGTH_MASK)
107432 
107433 #define VPU_H264_SWREG38_SW_ENC_LUMOFFSET_MASK   (0xF00000U)
107434 #define VPU_H264_SWREG38_SW_ENC_LUMOFFSET_SHIFT  (20U)
107435 #define VPU_H264_SWREG38_SW_ENC_LUMOFFSET(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_LUMOFFSET_SHIFT)) & VPU_H264_SWREG38_SW_ENC_LUMOFFSET_MASK)
107436 
107437 #define VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK (0x3000000U)
107438 #define VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT (24U)
107439 /*! SW_ENC_OUTPUT_BITWIDTH_LUM
107440  *  0b00..8 bit.
107441  *  0b01..9 bit.
107442  *  0b10..10 bit.
107443  */
107444 #define VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT)) & VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK)
107445 
107446 #define VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_MASK (0xC000000U)
107447 #define VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT (26U)
107448 /*! SW_ENC_INPUT_ROTATION
107449  *  0b00..disabled.
107450  *  0b01..90 degrees right.
107451  *  0b10..90 degrees left.
107452  *  0b11..180 degree right.
107453  */
107454 #define VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT)) & VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_MASK)
107455 
107456 #define VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_MASK (0xF0000000U)
107457 #define VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT (28U)
107458 /*! SW_ENC_INPUT_FORMAT
107459  *  0b0001..YUV420SP
107460  *  0b0010..YUYV422
107461  *  0b0011..UYVY422
107462  *  0b0100..RGB565
107463  *  0b0101..RGB555
107464  *  0b0110..RGB444
107465  *  0b0111..RGB888
107466  *  0b1000..RGB101010
107467  *  0b1001..I010
107468  *  0b1010..P010
107469  *  0b1011..PACKED10BITPLANAR
107470  *  0b1100..Y0L2
107471  *  0b1101..DAHUAHEVC
107472  *  0b1110..DAHUAH264
107473  */
107474 #define VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT)) & VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_MASK)
107475 /*! @} */
107476 
107477 /*! @name SWREG39 - Pre-processor color conversion parameters0 */
107478 /*! @{ */
107479 
107480 #define VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_MASK   (0xFFFFU)
107481 #define VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_SHIFT  (0U)
107482 #define VPU_H264_SWREG39_SW_ENC_RGBCOEFFB(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_SHIFT)) & VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_MASK)
107483 
107484 #define VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_MASK   (0xFFFF0000U)
107485 #define VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_SHIFT  (16U)
107486 #define VPU_H264_SWREG39_SW_ENC_RGBCOEFFA(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_SHIFT)) & VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_MASK)
107487 /*! @} */
107488 
107489 /*! @name SWREG40 - Pre-processor color conversion parameters1 */
107490 /*! @{ */
107491 
107492 #define VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_MASK   (0xFFFFU)
107493 #define VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_SHIFT  (0U)
107494 #define VPU_H264_SWREG40_SW_ENC_RGBCOEFFE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_SHIFT)) & VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_MASK)
107495 
107496 #define VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_MASK   (0xFFFF0000U)
107497 #define VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_SHIFT  (16U)
107498 #define VPU_H264_SWREG40_SW_ENC_RGBCOEFFC(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_SHIFT)) & VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_MASK)
107499 /*! @} */
107500 
107501 /*! @name SWREG41 - Pre-processor color conversion parameters2 */
107502 /*! @{ */
107503 
107504 #define VPU_H264_SWREG41_SW_ENC_BMASKMSB_MASK    (0x3EU)
107505 #define VPU_H264_SWREG41_SW_ENC_BMASKMSB_SHIFT   (1U)
107506 #define VPU_H264_SWREG41_SW_ENC_BMASKMSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_BMASKMSB_SHIFT)) & VPU_H264_SWREG41_SW_ENC_BMASKMSB_MASK)
107507 
107508 #define VPU_H264_SWREG41_SW_ENC_GMASKMSB_MASK    (0x7C0U)
107509 #define VPU_H264_SWREG41_SW_ENC_GMASKMSB_SHIFT   (6U)
107510 #define VPU_H264_SWREG41_SW_ENC_GMASKMSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_GMASKMSB_SHIFT)) & VPU_H264_SWREG41_SW_ENC_GMASKMSB_MASK)
107511 
107512 #define VPU_H264_SWREG41_SW_ENC_RMASKMSB_MASK    (0xF800U)
107513 #define VPU_H264_SWREG41_SW_ENC_RMASKMSB_SHIFT   (11U)
107514 #define VPU_H264_SWREG41_SW_ENC_RMASKMSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_RMASKMSB_SHIFT)) & VPU_H264_SWREG41_SW_ENC_RMASKMSB_MASK)
107515 
107516 #define VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_MASK   (0xFFFF0000U)
107517 #define VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_SHIFT  (16U)
107518 #define VPU_H264_SWREG41_SW_ENC_RGBCOEFFF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_SHIFT)) & VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_MASK)
107519 /*! @} */
107520 
107521 /*! @name SWREG42 - Pre-processor Base address for down-scaled output */
107522 /*! @{ */
107523 
107524 #define VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK (0xFFFFFFFFU)
107525 #define VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT (0U)
107526 #define VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT)) & VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK)
107527 /*! @} */
107528 
107529 /*! @name SWREG43 - Pre-processor down-scaled configuration0 */
107530 /*! @{ */
107531 
107532 #define VPU_H264_SWREG43_SW_ENC_SCALE_MODE_MASK  (0x3U)
107533 #define VPU_H264_SWREG43_SW_ENC_SCALE_MODE_SHIFT (0U)
107534 /*! SW_ENC_SCALE_MODE
107535  *  0b00..disabled.
107536  *  0b01..scaling only.
107537  *  0b10..scale+encode
107538  */
107539 #define VPU_H264_SWREG43_SW_ENC_SCALE_MODE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALE_MODE_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALE_MODE_MASK)
107540 
107541 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK (0x4U)
107542 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT (2U)
107543 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK)
107544 
107545 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK (0x7FFF8U)
107546 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT (3U)
107547 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK)
107548 
107549 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK (0xFFF80000U)
107550 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT (19U)
107551 #define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK)
107552 /*! @} */
107553 
107554 /*! @name SWREG44 - Pre-processor down-scaled configuration1 */
107555 /*! @{ */
107556 
107557 #define VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK (0x3U)
107558 #define VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT (0U)
107559 #define VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT)) & VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK)
107560 
107561 #define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK (0x3FFFCU)
107562 #define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT (2U)
107563 #define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT)) & VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK)
107564 
107565 #define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK (0xFFFC0000U)
107566 #define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT (18U)
107567 #define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT)) & VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK)
107568 /*! @} */
107569 
107570 /*! @name SWREG45 - Pre-processor down-scaled configuration2 */
107571 /*! @{ */
107572 
107573 #define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK (0x4U)
107574 #define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT (2U)
107575 #define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK)
107576 
107577 #define VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK (0x78U)
107578 #define VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT (3U)
107579 #define VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT)) & VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK)
107580 
107581 #define VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK (0x80U)
107582 #define VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT (7U)
107583 #define VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK)
107584 
107585 #define VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK (0x100U)
107586 #define VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT (8U)
107587 #define VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK)
107588 
107589 #define VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK (0x200U)
107590 #define VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT (9U)
107591 #define VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT)) & VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK)
107592 
107593 #define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK (0xC00U)
107594 #define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT (10U)
107595 #define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK)
107596 
107597 #define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK (0x3000U)
107598 #define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT (12U)
107599 #define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK)
107600 
107601 #define VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK (0x7FFC000U)
107602 #define VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT (14U)
107603 #define VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT)) & VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK)
107604 
107605 #define VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_MASK (0x8000000U)
107606 #define VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT (27U)
107607 #define VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT)) & VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_MASK)
107608 
107609 #define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK (0xF0000000U)
107610 #define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT (28U)
107611 #define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK)
107612 /*! @} */
107613 
107614 /*! @name SWREG46 - compressed coefficients base address for SAN module. */
107615 /*! @{ */
107616 
107617 #define VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK (0xFFFFFFFFU)
107618 #define VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT (0U)
107619 #define VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT)) & VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK)
107620 /*! @} */
107621 
107622 /*! @name SWREG60 - Base address for recon luma compress table LSB. */
107623 /*! @{ */
107624 
107625 #define VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
107626 #define VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
107627 #define VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK)
107628 /*! @} */
107629 
107630 /*! @name SWREG62 - Base address for recon Chroma compress table LSB */
107631 /*! @{ */
107632 
107633 #define VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
107634 #define VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
107635 #define VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK)
107636 /*! @} */
107637 
107638 /*! @name SWREG64 - Base address for list 0 ref 0 luma compress table LSB. */
107639 /*! @{ */
107640 
107641 #define VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
107642 #define VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
107643 #define VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
107644 /*! @} */
107645 
107646 /*! @name SWREG66 - Base address for list 0 ref 0 Chroma compress table LSB. */
107647 /*! @{ */
107648 
107649 #define VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
107650 #define VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
107651 #define VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
107652 /*! @} */
107653 
107654 /*! @name SWREG72 - Base address for recon luma 4n base LSB. */
107655 /*! @{ */
107656 
107657 #define VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK (0xFFFFFFFFU)
107658 #define VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT (0U)
107659 #define VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT)) & VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK)
107660 /*! @} */
107661 
107662 /*! @name SWREG74 - reference picture reconstructed list0 4n 0 */
107663 /*! @{ */
107664 
107665 #define VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK (0xFFFFFFFFU)
107666 #define VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT (0U)
107667 #define VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT)) & VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK)
107668 /*! @} */
107669 
107670 /*! @name SWREG78_H2V5 - inter me SATD lambda config 7. For H2V5 or later version. */
107671 /*! @{ */
107672 
107673 #define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK (0x7FFC0U)
107674 #define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT (6U)
107675 #define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK)
107676 
107677 #define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK (0xFFF80000U)
107678 #define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT (19U)
107679 #define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK)
107680 /*! @} */
107681 
107682 /*! @name SWREG79_H2V5 - inter me SSE lambda config 0. For H2V5 or later version. */
107683 /*! @{ */
107684 
107685 #define VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK (0xFFFFF800U)
107686 #define VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT (11U)
107687 #define VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK)
107688 /*! @} */
107689 
107690 /*! @name SWREG80 - HW synthesis config register, read-only */
107691 /*! @{ */
107692 
107693 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU)
107694 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT (0U)
107695 #define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
107696 
107697 #define VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_MASK  (0x6000U)
107698 #define VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_SHIFT (13U)
107699 /*! SW_ENC_HWBUSWIDTH
107700  *  0b00..32b.
107701  *  0b01..64b.
107702  *  0b10..128b
107703  */
107704 #define VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_MASK)
107705 
107706 #define VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_MASK (0x8000U)
107707 #define VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_SHIFT (15U)
107708 /*! SW_ENC_HWJPEGSUPPORT
107709  *  0b0..not supported.
107710  *  0b1..supported
107711  */
107712 #define VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_MASK)
107713 
107714 #define VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_MASK (0x10000U)
107715 #define VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_SHIFT (16U)
107716 /*! SW_ENC_HWTU32SUPPORT
107717  *  0b0..not supported.
107718  *  0b1..supported
107719  */
107720 #define VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_MASK)
107721 
107722 #define VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_MASK (0x20000U)
107723 #define VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_SHIFT (17U)
107724 /*! SW_ENC_HWRFCSUPPORT
107725  *  0b0..not supported.
107726  *  0b1..supported
107727  */
107728 #define VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_MASK)
107729 
107730 #define VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_MASK (0x40000U)
107731 #define VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_SHIFT (18U)
107732 /*! SW_ENC_HWPROGRDOSUPPORT
107733  *  0b0..not supported.
107734  *  0b1..supported
107735  */
107736 #define VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_MASK)
107737 
107738 #define VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_MASK (0x80000U)
107739 #define VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_SHIFT (19U)
107740 /*! SW_ENC_HWLINEBUFSUPPORT
107741  *  0b0..not supported.
107742  *  0b1..supported
107743  */
107744 #define VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_MASK)
107745 
107746 #define VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_MASK (0x100000U)
107747 #define VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_SHIFT (20U)
107748 /*! SW_ENC_HWCAVLCSUPPORT
107749  *  0b0..not supported.
107750  *  0b1..supported
107751  */
107752 #define VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_MASK)
107753 
107754 #define VPU_H264_SWREG80_SW_ENC_HWBUS_MASK       (0xE00000U)
107755 #define VPU_H264_SWREG80_SW_ENC_HWBUS_SHIFT      (21U)
107756 /*! SW_ENC_HWBUS
107757  *  0b001..AHB.
107758  *  0b010..OCP.
107759  *  0b011..AXI.
107760  *  0b100..PCI.
107761  *  0b101..AXIAHB.
107762  *  0b110..AXIAPB.
107763  */
107764 #define VPU_H264_SWREG80_SW_ENC_HWBUS(x)         (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWBUS_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWBUS_MASK)
107765 
107766 #define VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_MASK (0x1000000U)
107767 #define VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_SHIFT (24U)
107768 /*! SW_ENC_HWMAIN10SUPPORT
107769  *  0b0..main8 supported.
107770  *  0b1..main10 supported
107771  */
107772 #define VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_MASK)
107773 
107774 #define VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_MASK (0x2000000U)
107775 #define VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_SHIFT (25U)
107776 /*! SW_ENC_HWDENOISESUPPORT
107777  *  0b0..not supported.
107778  *  0b1..supported
107779  */
107780 #define VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_MASK)
107781 
107782 #define VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_MASK (0x4000000U)
107783 #define VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_SHIFT (26U)
107784 /*! SW_ENC_HWVP9SUPPORT
107785  *  0b0..not supported.
107786  *  0b1..supported
107787  */
107788 #define VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_MASK)
107789 
107790 #define VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_MASK (0x8000000U)
107791 #define VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_SHIFT (27U)
107792 /*! SW_ENC_HWHEVCSUPPORT
107793  *  0b0..not supported.
107794  *  0b1..supported
107795  */
107796 #define VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_MASK)
107797 
107798 #define VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_MASK (0x10000000U)
107799 #define VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_SHIFT (28U)
107800 /*! SW_ENC_HWRGBSUPPORT
107801  *  0b0..not supported.
107802  *  0b1..supported
107803  */
107804 #define VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_MASK)
107805 
107806 #define VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_MASK (0x20000000U)
107807 #define VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_SHIFT (29U)
107808 /*! SW_ENC_HWBFRAMESUPPORT
107809  *  0b0..not support bframe.
107810  *  0b1..support bframe
107811  */
107812 #define VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_MASK)
107813 
107814 #define VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_MASK (0x40000000U)
107815 #define VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_SHIFT (30U)
107816 /*! SW_ENC_HWSCALINGSUPPORT
107817  *  0b0..not supported.
107818  *  0b1..supported
107819  */
107820 #define VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_MASK)
107821 
107822 #define VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_MASK (0x80000000U)
107823 #define VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_SHIFT (31U)
107824 /*! SW_ENC_HWH264SUPPORT
107825  *  0b0..not supported.
107826  *  0b1..supported
107827  */
107828 #define VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_MASK)
107829 /*! @} */
107830 
107831 /*! @name SWREG81 - hardware configuation 0 */
107832 /*! @{ */
107833 
107834 #define VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_MASK  (0x7FFFFFU)
107835 #define VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_SHIFT (0U)
107836 #define VPU_H264_SWREG81_SW_TIMEOUT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_SHIFT)) & VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_MASK)
107837 
107838 #define VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK (0x800000U)
107839 #define VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT (23U)
107840 #define VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT)) & VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK)
107841 
107842 #define VPU_H264_SWREG81_SW_ENC_MAX_BURST_MASK   (0xFF000000U)
107843 #define VPU_H264_SWREG81_SW_ENC_MAX_BURST_SHIFT  (24U)
107844 #define VPU_H264_SWREG81_SW_ENC_MAX_BURST(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG81_SW_ENC_MAX_BURST_SHIFT)) & VPU_H264_SWREG81_SW_ENC_MAX_BURST_MASK)
107845 /*! @} */
107846 
107847 /*! @name SWREG82 - record hardware performance */
107848 /*! @{ */
107849 
107850 #define VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_MASK (0xFFFFFFFFU)
107851 #define VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT (0U)
107852 #define VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT)) & VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_MASK)
107853 /*! @} */
107854 
107855 /*! @name SWREG83 - reference picture reconstructed list1 luma0 */
107856 /*! @{ */
107857 
107858 #define VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK (0xFFFFFFFFU)
107859 #define VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT (0U)
107860 #define VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT)) & VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK)
107861 /*! @} */
107862 
107863 /*! @name SWREG84 - reference picture reconstructed list1 chroma0 */
107864 /*! @{ */
107865 
107866 #define VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK (0xFFFFFFFFU)
107867 #define VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT (0U)
107868 #define VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT)) & VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK)
107869 /*! @} */
107870 
107871 /*! @name SWREG91 - reference pictures list1 config */
107872 /*! @{ */
107873 
107874 #define VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK (0x4U)
107875 #define VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT (2U)
107876 /*! SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE
107877  *  0b0..disable
107878  *  0b1..enable.
107879  */
107880 #define VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK)
107881 
107882 #define VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK (0x8U)
107883 #define VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT (3U)
107884 /*! SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE
107885  *  0b0..disable
107886  *  0b1..enable.
107887  */
107888 #define VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK)
107889 
107890 #define VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK (0x10U)
107891 #define VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT (4U)
107892 #define VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT)) & VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK)
107893 
107894 #define VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK (0xC0U)
107895 #define VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT (6U)
107896 #define VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT)) & VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK)
107897 
107898 #define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK (0x100U)
107899 #define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT (8U)
107900 #define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK)
107901 
107902 #define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK (0x200U)
107903 #define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT (9U)
107904 #define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK)
107905 
107906 #define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_MASK (0xFFC00U)
107907 #define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT (10U)
107908 #define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_MASK)
107909 
107910 #define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK (0x100000U)
107911 #define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT (20U)
107912 #define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK)
107913 
107914 #define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK (0x200000U)
107915 #define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT (21U)
107916 #define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK)
107917 
107918 #define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_MASK (0xFFC00000U)
107919 #define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT (22U)
107920 #define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_MASK)
107921 /*! @} */
107922 
107923 /*! @name SWREG92 - reference picture reconstructed list1 4n 0 */
107924 /*! @{ */
107925 
107926 #define VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK (0xFFFFFFFFU)
107927 #define VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT (0U)
107928 #define VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT)) & VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK)
107929 /*! @} */
107930 
107931 /*! @name SWREG96 - Base address for list 1 ref 0 luma compress table LSB. */
107932 /*! @{ */
107933 
107934 #define VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
107935 #define VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
107936 #define VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
107937 /*! @} */
107938 
107939 /*! @name SWREG98 - Base address for list 1 ref 0 Chroma compress table LSB. */
107940 /*! @{ */
107941 
107942 #define VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
107943 #define VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
107944 #define VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
107945 /*! @} */
107946 
107947 /*! @name SWREG106 - Min picture size */
107948 /*! @{ */
107949 
107950 #define VPU_H264_SWREG106_SW_ENC_MINPICSIZE_MASK (0xFFFFFFFFU)
107951 #define VPU_H264_SWREG106_SW_ENC_MINPICSIZE_SHIFT (0U)
107952 #define VPU_H264_SWREG106_SW_ENC_MINPICSIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG106_SW_ENC_MINPICSIZE_SHIFT)) & VPU_H264_SWREG106_SW_ENC_MINPICSIZE_MASK)
107953 /*! @} */
107954 
107955 /*! @name SWREG107 - Max picture size */
107956 /*! @{ */
107957 
107958 #define VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_MASK (0xFFFFFFFFU)
107959 #define VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_SHIFT (0U)
107960 #define VPU_H264_SWREG107_SW_ENC_MAXPICSIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_SHIFT)) & VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_MASK)
107961 /*! @} */
107962 
107963 /*! @name SWREG109 - Qp delta map */
107964 /*! @{ */
107965 
107966 #define VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK (0xFFFFFFFFU)
107967 #define VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT (0U)
107968 #define VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT)) & VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK)
107969 /*! @} */
107970 
107971 /*! @name SWREG111 - adaptive GOP configuration1 */
107972 /*! @{ */
107973 
107974 #define VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U)
107975 #define VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_SHIFT (12U)
107976 #define VPU_H264_SWREG111_SW_ENC_INTRACU8NUM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_MASK)
107977 /*! @} */
107978 
107979 /*! @name SWREG112 - adaptive GOP configuration2 */
107980 /*! @{ */
107981 
107982 #define VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_MASK (0xFFFFF000U)
107983 #define VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT (12U)
107984 #define VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT)) & VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_MASK)
107985 /*! @} */
107986 
107987 /*! @name SWREG113 - adaptive GOP configuration3 */
107988 /*! @{ */
107989 
107990 #define VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK (0xFFFFFFFFU)
107991 #define VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT (0U)
107992 #define VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT)) & VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK)
107993 /*! @} */
107994 
107995 /*! @name SWREG114 - ctb rate control bit memory address of current frame */
107996 /*! @{ */
107997 
107998 #define VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_MASK (0xFFFFFFFFU)
107999 #define VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_SHIFT (0U)
108000 #define VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_SHIFT)) & VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_MASK)
108001 /*! @} */
108002 
108003 /*! @name SWREG116 - ctb rate control bit memory address of previous frame */
108004 /*! @{ */
108005 
108006 #define VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_MASK (0xFFFFFFFFU)
108007 #define VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_SHIFT (0U)
108008 #define VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_SHIFT)) & VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_MASK)
108009 /*! @} */
108010 
108011 /*! @name SWREG119 - min/max lcu bits number of last picture */
108012 /*! @{ */
108013 
108014 #define VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_MASK (0xFFFFU)
108015 #define VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_SHIFT (0U)
108016 #define VPU_H264_SWREG119_SW_ENC_CTBBITSMAX(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_SHIFT)) & VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_MASK)
108017 
108018 #define VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_MASK (0xFFFF0000U)
108019 #define VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_SHIFT (16U)
108020 #define VPU_H264_SWREG119_SW_ENC_CTBBITSMIN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_SHIFT)) & VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_MASK)
108021 /*! @} */
108022 
108023 /*! @name SWREG120 - total bits number of all lcus of last picture not including slice header bits */
108024 /*! @{ */
108025 
108026 #define VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_MASK (0xFFFFFFFFU)
108027 #define VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT (0U)
108028 #define VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT)) & VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_MASK)
108029 /*! @} */
108030 
108031 /*! @name SWREG122_H2V5 - inter me SSE lambda config 1. For H2V5 or later version. */
108032 /*! @{ */
108033 
108034 #define VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK (0xFFFFF800U)
108035 #define VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT (11U)
108036 #define VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK)
108037 /*! @} */
108038 
108039 /*! @name SWREG123_H2V5 - inter me SSE lambda config 2. For H2V5 or later version. */
108040 /*! @{ */
108041 
108042 #define VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK (0xFFFFF800U)
108043 #define VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT (11U)
108044 #define VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK)
108045 /*! @} */
108046 
108047 /*! @name SWREG124_H2V5 - inter me SSE lambda config 3. For H2V5 or later version. */
108048 /*! @{ */
108049 
108050 #define VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK (0xFFFFF800U)
108051 #define VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT (11U)
108052 #define VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK)
108053 /*! @} */
108054 
108055 /*! @name SWREG125 - intra SATD lambda config 0 */
108056 /*! @{ */
108057 
108058 #define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK (0x3FFF0U)
108059 #define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT (4U)
108060 #define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT)) & VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK)
108061 
108062 #define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK (0xFFFC0000U)
108063 #define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT (18U)
108064 #define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT)) & VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK)
108065 /*! @} */
108066 
108067 /*! @name SWREG126 - intra SATD lambda config 1 */
108068 /*! @{ */
108069 
108070 #define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK (0x3FFF0U)
108071 #define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT (4U)
108072 #define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT)) & VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK)
108073 
108074 #define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK (0xFFFC0000U)
108075 #define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT (18U)
108076 #define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT)) & VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK)
108077 /*! @} */
108078 
108079 /*! @name SWREG127 - intra SATD lambda config 2 */
108080 /*! @{ */
108081 
108082 #define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK (0x3FFF0U)
108083 #define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT (4U)
108084 #define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT)) & VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK)
108085 
108086 #define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK (0xFFFC0000U)
108087 #define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT (18U)
108088 #define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT)) & VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK)
108089 /*! @} */
108090 
108091 /*! @name SWREG128 - intra SATD lambda config 3 */
108092 /*! @{ */
108093 
108094 #define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK (0x3FFF0U)
108095 #define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT (4U)
108096 #define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT)) & VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK)
108097 
108098 #define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK (0xFFFC0000U)
108099 #define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT (18U)
108100 #define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT)) & VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK)
108101 /*! @} */
108102 
108103 /*! @name SWREG129 - intra SATD lambda config 4 */
108104 /*! @{ */
108105 
108106 #define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK (0x3FFF0U)
108107 #define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT (4U)
108108 #define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT)) & VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK)
108109 
108110 #define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK (0xFFFC0000U)
108111 #define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT (18U)
108112 #define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT)) & VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK)
108113 /*! @} */
108114 
108115 /*! @name SWREG130 - intra SATD lambda config 5 */
108116 /*! @{ */
108117 
108118 #define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK (0x3FFF0U)
108119 #define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT (4U)
108120 #define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT)) & VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK)
108121 
108122 #define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK (0xFFFC0000U)
108123 #define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT (18U)
108124 #define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT)) & VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK)
108125 /*! @} */
108126 
108127 /*! @name SWREG131 - intra SATD lambda config 6 */
108128 /*! @{ */
108129 
108130 #define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK (0x3FFF0U)
108131 #define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT (4U)
108132 #define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT)) & VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK)
108133 
108134 #define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK (0xFFFC0000U)
108135 #define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT (18U)
108136 #define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT)) & VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK)
108137 /*! @} */
108138 
108139 /*! @name SWREG132 - intra SATD lambda config 7 */
108140 /*! @{ */
108141 
108142 #define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK (0x3FFF0U)
108143 #define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT (4U)
108144 #define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT)) & VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK)
108145 
108146 #define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK (0xFFFC0000U)
108147 #define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT (18U)
108148 #define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT)) & VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK)
108149 /*! @} */
108150 
108151 /*! @name SWREG133 - SSE devide 256 */
108152 /*! @{ */
108153 
108154 #define VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_MASK (0xFFFFFFFFU)
108155 #define VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_SHIFT (0U)
108156 #define VPU_H264_SWREG133_SW_ENC_SSE_DIV_256(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_SHIFT)) & VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_MASK)
108157 /*! @} */
108158 
108159 /*! @name SWREG138_H2V5 - inter me SSE lambda config 4. For H2V5 or later version. */
108160 /*! @{ */
108161 
108162 #define VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK (0xFFFFF800U)
108163 #define VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT (11U)
108164 #define VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK)
108165 /*! @} */
108166 
108167 /*! @name SWREG139_H2V5 - inter me SSE lambda config 5. For H2V5 or later version. */
108168 /*! @{ */
108169 
108170 #define VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK (0xFFFFF800U)
108171 #define VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT (11U)
108172 #define VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK)
108173 /*! @} */
108174 
108175 /*! @name SWREG140_H2V5 - inter me SSE lambda config 6. For H2V5 or later version. */
108176 /*! @{ */
108177 
108178 #define VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK (0xFFFFF800U)
108179 #define VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT (11U)
108180 #define VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK)
108181 /*! @} */
108182 
108183 /*! @name SWREG141_H2V5 - inter me SSE lambda config 7. For H2V5 or later version. */
108184 /*! @{ */
108185 
108186 #define VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK (0xFFFFF800U)
108187 #define VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT (11U)
108188 #define VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK)
108189 /*! @} */
108190 
108191 /*! @name SWREG142_H2V5 - inter me SSE lambda config 8. For H2V5 or later version. */
108192 /*! @{ */
108193 
108194 #define VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK (0xFFFFF800U)
108195 #define VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT (11U)
108196 #define VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK)
108197 /*! @} */
108198 
108199 /*! @name SWREG143_H2V5 - inter me SSE lambda config 9. For H2V5 or later version. */
108200 /*! @{ */
108201 
108202 #define VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK (0xFFFFF800U)
108203 #define VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT (11U)
108204 #define VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK)
108205 /*! @} */
108206 
108207 /*! @name SWREG144_H2V5 - inter me SSE lambda config 10. For H2V5 or later version. */
108208 /*! @{ */
108209 
108210 #define VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK (0xFFFFF800U)
108211 #define VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT (11U)
108212 #define VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK)
108213 /*! @} */
108214 
108215 /*! @name SWREG145_H2V5 - inter me SSE lambda config 11. For H2V5 or later version. */
108216 /*! @{ */
108217 
108218 #define VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK (0xFFFFF800U)
108219 #define VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT (11U)
108220 #define VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK)
108221 /*! @} */
108222 
108223 /*! @name SWREG146_H2V5 - inter me SSE lambda config 12. For H2V5 or later version. */
108224 /*! @{ */
108225 
108226 #define VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK (0xFFFFF800U)
108227 #define VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT (11U)
108228 #define VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK)
108229 /*! @} */
108230 
108231 /*! @name SWREG147_H2V5 - inter me SSE lambda config 13. For H2V5 or later version. */
108232 /*! @{ */
108233 
108234 #define VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK (0xFFFFF800U)
108235 #define VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT (11U)
108236 #define VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK)
108237 /*! @} */
108238 
108239 /*! @name SWREG148_H2V5 - inter me SSE lambda config 14. For H2V5 or later version. */
108240 /*! @{ */
108241 
108242 #define VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK (0xFFFFF800U)
108243 #define VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT (11U)
108244 #define VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK)
108245 /*! @} */
108246 
108247 /*! @name SWREG149_H2V5 - inter me SSE lambda config 15. For H2V5 or later version. */
108248 /*! @{ */
108249 
108250 #define VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK (0xFFFFF800U)
108251 #define VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT (11U)
108252 #define VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK)
108253 /*! @} */
108254 
108255 /*! @name SWREG150 - inter me SATD lambda config 8 */
108256 /*! @{ */
108257 
108258 #define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK (0x7FFC0U)
108259 #define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT (6U)
108260 #define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT)) & VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK)
108261 
108262 #define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK (0xFFF80000U)
108263 #define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT (19U)
108264 #define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT)) & VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK)
108265 /*! @} */
108266 
108267 /*! @name SWREG151 - inter me SATD lambda config 9 */
108268 /*! @{ */
108269 
108270 #define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK (0x7FFC0U)
108271 #define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT (6U)
108272 #define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT)) & VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK)
108273 
108274 #define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK (0xFFF80000U)
108275 #define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT (19U)
108276 #define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT)) & VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK)
108277 /*! @} */
108278 
108279 /*! @name SWREG152 - inter me SATD lambda config 10 */
108280 /*! @{ */
108281 
108282 #define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK (0x7FFC0U)
108283 #define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT (6U)
108284 #define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT)) & VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK)
108285 
108286 #define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK (0xFFF80000U)
108287 #define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT (19U)
108288 #define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT)) & VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK)
108289 /*! @} */
108290 
108291 /*! @name SWREG153 - inter me SATD lambda config 11 */
108292 /*! @{ */
108293 
108294 #define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK (0x7FFC0U)
108295 #define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT (6U)
108296 #define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT)) & VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK)
108297 
108298 #define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK (0xFFF80000U)
108299 #define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT (19U)
108300 #define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT)) & VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK)
108301 /*! @} */
108302 
108303 /*! @name SWREG154 - inter me SATD lambda config 12 */
108304 /*! @{ */
108305 
108306 #define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK (0x7FFC0U)
108307 #define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT (6U)
108308 #define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT)) & VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK)
108309 
108310 #define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK (0xFFF80000U)
108311 #define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT (19U)
108312 #define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT)) & VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK)
108313 /*! @} */
108314 
108315 /*! @name SWREG155 - inter me SATD lambda config 13 */
108316 /*! @{ */
108317 
108318 #define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK (0x7FFC0U)
108319 #define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT (6U)
108320 #define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT)) & VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK)
108321 
108322 #define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK (0xFFF80000U)
108323 #define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT (19U)
108324 #define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT)) & VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK)
108325 /*! @} */
108326 
108327 /*! @name SWREG156 - inter me SATD lambda config 14 */
108328 /*! @{ */
108329 
108330 #define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK (0x7FFC0U)
108331 #define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT (6U)
108332 #define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT)) & VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK)
108333 
108334 #define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK (0xFFF80000U)
108335 #define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT (19U)
108336 #define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT)) & VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK)
108337 /*! @} */
108338 
108339 /*! @name SWREG157 - inter me SATD lambda config 15 */
108340 /*! @{ */
108341 
108342 #define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK (0x7FFC0U)
108343 #define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT (6U)
108344 #define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT)) & VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK)
108345 
108346 #define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK (0xFFF80000U)
108347 #define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT (19U)
108348 #define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT)) & VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK)
108349 /*! @} */
108350 
108351 /*! @name SWREG158 - inter me SSE lambda config 16 */
108352 /*! @{ */
108353 
108354 #define VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK (0xFFFFF800U)
108355 #define VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT (11U)
108356 #define VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT)) & VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK)
108357 /*! @} */
108358 
108359 /*! @name SWREG159 - inter me SSE lambda config 17 */
108360 /*! @{ */
108361 
108362 #define VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK (0xFFFFF800U)
108363 #define VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT (11U)
108364 #define VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT)) & VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK)
108365 /*! @} */
108366 
108367 /*! @name SWREG160 - inter me SSE lambda config 18 */
108368 /*! @{ */
108369 
108370 #define VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK (0xFFFFF800U)
108371 #define VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT (11U)
108372 #define VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT)) & VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK)
108373 /*! @} */
108374 
108375 /*! @name SWREG161 - inter me SSE lambda config 19 */
108376 /*! @{ */
108377 
108378 #define VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK (0xFFFFF800U)
108379 #define VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT (11U)
108380 #define VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT)) & VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK)
108381 /*! @} */
108382 
108383 /*! @name SWREG162 - inter me SSE lambda config 20 */
108384 /*! @{ */
108385 
108386 #define VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK (0xFFFFF800U)
108387 #define VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT (11U)
108388 #define VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT)) & VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK)
108389 /*! @} */
108390 
108391 /*! @name SWREG163 - inter me SSE lambda config 21 */
108392 /*! @{ */
108393 
108394 #define VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK (0xFFFFF800U)
108395 #define VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT (11U)
108396 #define VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT)) & VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK)
108397 /*! @} */
108398 
108399 /*! @name SWREG164 - inter me SSE lambda config 22 */
108400 /*! @{ */
108401 
108402 #define VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK (0xFFFFF800U)
108403 #define VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT (11U)
108404 #define VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT)) & VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK)
108405 /*! @} */
108406 
108407 /*! @name SWREG165 - inter me SSE lambda config 23 */
108408 /*! @{ */
108409 
108410 #define VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK (0xFFFFF800U)
108411 #define VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT (11U)
108412 #define VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT)) & VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK)
108413 /*! @} */
108414 
108415 /*! @name SWREG166 - inter me SSE lambda config 24 */
108416 /*! @{ */
108417 
108418 #define VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK (0xFFFFF800U)
108419 #define VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT (11U)
108420 #define VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT)) & VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK)
108421 /*! @} */
108422 
108423 /*! @name SWREG167 - inter me SSE lambda config 25 */
108424 /*! @{ */
108425 
108426 #define VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK (0xFFFFF800U)
108427 #define VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT (11U)
108428 #define VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT)) & VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK)
108429 /*! @} */
108430 
108431 /*! @name SWREG168 - inter me SSE lambda config 26 */
108432 /*! @{ */
108433 
108434 #define VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK (0xFFFFF800U)
108435 #define VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT (11U)
108436 #define VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT)) & VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK)
108437 /*! @} */
108438 
108439 /*! @name SWREG169 - inter me SSE lambda config 27 */
108440 /*! @{ */
108441 
108442 #define VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK (0xFFFFF800U)
108443 #define VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT (11U)
108444 #define VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT)) & VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK)
108445 /*! @} */
108446 
108447 /*! @name SWREG172 - inter me SSE lambda config 30 */
108448 /*! @{ */
108449 
108450 #define VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK (0x1FU)
108451 #define VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT (0U)
108452 #define VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT)) & VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK)
108453 
108454 #define VPU_H264_SWREG172_SW_ENC_QP_MIN_MASK     (0x7E0U)
108455 #define VPU_H264_SWREG172_SW_ENC_QP_MIN_SHIFT    (5U)
108456 #define VPU_H264_SWREG172_SW_ENC_QP_MIN(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG172_SW_ENC_QP_MIN_SHIFT)) & VPU_H264_SWREG172_SW_ENC_QP_MIN_MASK)
108457 
108458 #define VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK (0xFFFFF800U)
108459 #define VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT (11U)
108460 #define VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT)) & VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK)
108461 /*! @} */
108462 
108463 /*! @name SWREG173 - inter me SSE lambda config 31 */
108464 /*! @{ */
108465 
108466 #define VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK (0xFU)
108467 #define VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT (0U)
108468 #define VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT)) & VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK)
108469 
108470 #define VPU_H264_SWREG173_SW_ENC_QP_MAX_MASK     (0x7E0U)
108471 #define VPU_H264_SWREG173_SW_ENC_QP_MAX_SHIFT    (5U)
108472 #define VPU_H264_SWREG173_SW_ENC_QP_MAX(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG173_SW_ENC_QP_MAX_SHIFT)) & VPU_H264_SWREG173_SW_ENC_QP_MAX_MASK)
108473 
108474 #define VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK (0xFFFFF800U)
108475 #define VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT (11U)
108476 #define VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT)) & VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK)
108477 /*! @} */
108478 
108479 /*! @name SWREG174 - intra SATD lambda config 8 */
108480 /*! @{ */
108481 
108482 #define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK (0x3FFF0U)
108483 #define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT (4U)
108484 #define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT)) & VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK)
108485 
108486 #define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK (0xFFFC0000U)
108487 #define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT (18U)
108488 #define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT)) & VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK)
108489 /*! @} */
108490 
108491 /*! @name SWREG175 - intra SATD lambda config 9 */
108492 /*! @{ */
108493 
108494 #define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK (0x3FFF0U)
108495 #define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT (4U)
108496 #define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT)) & VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK)
108497 
108498 #define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK (0xFFFC0000U)
108499 #define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT (18U)
108500 #define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT)) & VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK)
108501 /*! @} */
108502 
108503 /*! @name SWREG176 - intra SATD lambda config 10 */
108504 /*! @{ */
108505 
108506 #define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK (0x3FFF0U)
108507 #define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT (4U)
108508 #define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT)) & VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK)
108509 
108510 #define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK (0xFFFC0000U)
108511 #define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT (18U)
108512 #define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT)) & VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK)
108513 /*! @} */
108514 
108515 /*! @name SWREG177 - intra SATD lambda config 11 */
108516 /*! @{ */
108517 
108518 #define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK (0x3FFF0U)
108519 #define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT (4U)
108520 #define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT)) & VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK)
108521 
108522 #define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK (0xFFFC0000U)
108523 #define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT (18U)
108524 #define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT)) & VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK)
108525 /*! @} */
108526 
108527 /*! @name SWREG178 - intra SATD lambda config 12 */
108528 /*! @{ */
108529 
108530 #define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK (0x3FFF0U)
108531 #define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT (4U)
108532 #define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT)) & VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK)
108533 
108534 #define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK (0xFFFC0000U)
108535 #define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT (18U)
108536 #define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT)) & VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK)
108537 /*! @} */
108538 
108539 /*! @name SWREG179 - intra SATD lambda config 13 */
108540 /*! @{ */
108541 
108542 #define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK (0x3FFF0U)
108543 #define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT (4U)
108544 #define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT)) & VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK)
108545 
108546 #define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK (0xFFFC0000U)
108547 #define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT (18U)
108548 #define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT)) & VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK)
108549 /*! @} */
108550 
108551 /*! @name SWREG180 - intra SATD lambda config 14 */
108552 /*! @{ */
108553 
108554 #define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK (0x3FFF0U)
108555 #define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT (4U)
108556 #define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT)) & VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK)
108557 
108558 #define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK (0xFFFC0000U)
108559 #define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT (18U)
108560 #define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT)) & VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK)
108561 /*! @} */
108562 
108563 /*! @name SWREG181 - intra SATD lambda config 15 */
108564 /*! @{ */
108565 
108566 #define VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK (0xCU)
108567 #define VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT (2U)
108568 /*! SW_ENC_RC_BLOCK_SIZE
108569  *  0b00..64x64.
108570  *  0b01..32x32.
108571  *  0b10..16x16
108572  */
108573 #define VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT)) & VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK)
108574 
108575 #define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK (0x3FFF0U)
108576 #define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT (4U)
108577 #define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT)) & VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK)
108578 
108579 #define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK (0xFFFC0000U)
108580 #define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT (18U)
108581 #define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT)) & VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK)
108582 /*! @} */
108583 
108584 /*! @name SWREG182 - qp fractional part */
108585 /*! @{ */
108586 
108587 #define VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK (0xFFFFU)
108588 #define VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT (0U)
108589 #define VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT)) & VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK)
108590 
108591 #define VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_MASK (0xFFFF0000U)
108592 #define VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT (16U)
108593 #define VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT)) & VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_MASK)
108594 /*! @} */
108595 
108596 /*! @name SWREG183 - qp sum */
108597 /*! @{ */
108598 
108599 #define VPU_H264_SWREG183_SW_ENC_QP_SUM_MASK     (0xFFFFFFC0U)
108600 #define VPU_H264_SWREG183_SW_ENC_QP_SUM_SHIFT    (6U)
108601 #define VPU_H264_SWREG183_SW_ENC_QP_SUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG183_SW_ENC_QP_SUM_SHIFT)) & VPU_H264_SWREG183_SW_ENC_QP_SUM_MASK)
108602 /*! @} */
108603 
108604 /*! @name SWREG184 - qp num */
108605 /*! @{ */
108606 
108607 #define VPU_H264_SWREG184_SW_ENC_QP_NUM_MASK     (0xFFFFF000U)
108608 #define VPU_H264_SWREG184_SW_ENC_QP_NUM_SHIFT    (12U)
108609 #define VPU_H264_SWREG184_SW_ENC_QP_NUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG184_SW_ENC_QP_NUM_SHIFT)) & VPU_H264_SWREG184_SW_ENC_QP_NUM_MASK)
108610 /*! @} */
108611 
108612 /*! @name SWREG185 - picture complexity. Timeout cycles MSB. */
108613 /*! @{ */
108614 
108615 #define VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK (0x1FFU)
108616 #define VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT (0U)
108617 #define VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT)) & VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK)
108618 
108619 #define VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK (0xFFFFFE00U)
108620 #define VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT (9U)
108621 #define VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT)) & VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK)
108622 /*! @} */
108623 
108624 /*! @name SWREG190 - Long-term reference pictures config */
108625 /*! @{ */
108626 
108627 #define VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK (0xC0000000U)
108628 #define VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT (30U)
108629 #define VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT)) & VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK)
108630 /*! @} */
108631 
108632 /*! @name SWREG191 - Temporal scalable config */
108633 /*! @{ */
108634 
108635 #define VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK (0xFFFFU)
108636 #define VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT (0U)
108637 #define VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT)) & VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK)
108638 
108639 #define VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_MASK (0x10000U)
108640 #define VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_SHIFT (16U)
108641 /*! SW_ENC_PREFIXNAL_SVC_EXT
108642  *  0b1..enabled (insert H264Scalability SEI).
108643  *  0b0..disabled
108644  */
108645 #define VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_SHIFT)) & VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_MASK)
108646 
108647 #define VPU_H264_SWREG191_SW_ENC_PPS_ID_MASK     (0x7E0000U)
108648 #define VPU_H264_SWREG191_SW_ENC_PPS_ID_SHIFT    (17U)
108649 #define VPU_H264_SWREG191_SW_ENC_PPS_ID(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_PPS_ID_SHIFT)) & VPU_H264_SWREG191_SW_ENC_PPS_ID_MASK)
108650 
108651 #define VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK (0x3800000U)
108652 #define VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT (23U)
108653 #define VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT)) & VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK)
108654 
108655 #define VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK (0xFC000000U)
108656 #define VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT (26U)
108657 #define VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT)) & VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK)
108658 /*! @} */
108659 
108660 /*! @name SWREG192 - encoded Picture frame number (for H.264) */
108661 /*! @{ */
108662 
108663 #define VPU_H264_SWREG192_SW_ENC_FRAMENUM_MASK   (0xFFFFFFFFU)
108664 #define VPU_H264_SWREG192_SW_ENC_FRAMENUM_SHIFT  (0U)
108665 #define VPU_H264_SWREG192_SW_ENC_FRAMENUM(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG192_SW_ENC_FRAMENUM_SHIFT)) & VPU_H264_SWREG192_SW_ENC_FRAMENUM_MASK)
108666 /*! @} */
108667 
108668 /*! @name SWREG193 - reference pictures list0 config (for H.264) */
108669 /*! @{ */
108670 
108671 #define VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_MASK (0x1U)
108672 #define VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_SHIFT (0U)
108673 #define VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_SHIFT)) & VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_MASK)
108674 
108675 #define VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_MASK (0x2U)
108676 #define VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_SHIFT (1U)
108677 #define VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_SHIFT)) & VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_MASK)
108678 
108679 #define VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_MASK (0x4U)
108680 #define VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_SHIFT (2U)
108681 #define VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_SHIFT)) & VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_MASK)
108682 
108683 #define VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_MASK (0x8U)
108684 #define VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_SHIFT (3U)
108685 #define VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_SHIFT)) & VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_MASK)
108686 
108687 #define VPU_H264_SWREG193_SW_ENC_YFILL_MSB_MASK  (0x30U)
108688 #define VPU_H264_SWREG193_SW_ENC_YFILL_MSB_SHIFT (4U)
108689 #define VPU_H264_SWREG193_SW_ENC_YFILL_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_YFILL_MSB_SHIFT)) & VPU_H264_SWREG193_SW_ENC_YFILL_MSB_MASK)
108690 
108691 #define VPU_H264_SWREG193_SW_ENC_XFILL_MSB_MASK  (0xC0U)
108692 #define VPU_H264_SWREG193_SW_ENC_XFILL_MSB_SHIFT (6U)
108693 #define VPU_H264_SWREG193_SW_ENC_XFILL_MSB(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_XFILL_MSB_SHIFT)) & VPU_H264_SWREG193_SW_ENC_XFILL_MSB_MASK)
108694 
108695 #define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_MASK (0x100U)
108696 #define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_SHIFT (8U)
108697 #define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_MASK)
108698 
108699 #define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_MASK (0xFFE00U)
108700 #define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_SHIFT (9U)
108701 #define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_MASK)
108702 
108703 #define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_MASK (0x100000U)
108704 #define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_SHIFT (20U)
108705 #define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_MASK)
108706 
108707 #define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_MASK (0xFFE00000U)
108708 #define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_SHIFT (21U)
108709 #define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_MASK)
108710 /*! @} */
108711 
108712 /*! @name SWREG194 - reference pictures list1 config (for H.264) */
108713 /*! @{ */
108714 
108715 #define VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_MASK (0x1CU)
108716 #define VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_SHIFT (2U)
108717 #define VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_SHIFT)) & VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_MASK)
108718 
108719 #define VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_MASK (0xE0U)
108720 #define VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_SHIFT (5U)
108721 #define VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_SHIFT)) & VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_MASK)
108722 
108723 #define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_MASK (0x100U)
108724 #define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_SHIFT (8U)
108725 #define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_MASK)
108726 
108727 #define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_MASK (0xFFE00U)
108728 #define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_SHIFT (9U)
108729 #define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_MASK)
108730 
108731 #define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_MASK (0x100000U)
108732 #define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_SHIFT (20U)
108733 #define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_MASK)
108734 
108735 #define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_MASK (0xFFE00000U)
108736 #define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_SHIFT (21U)
108737 #define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_MASK)
108738 /*! @} */
108739 
108740 /*! @name SWREG195 - register extension for ctu_size=16 */
108741 /*! @{ */
108742 
108743 #define VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK (0xCU)
108744 #define VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT (2U)
108745 #define VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK)
108746 
108747 #define VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK (0x10U)
108748 #define VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT (4U)
108749 #define VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK)
108750 
108751 #define VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK (0x20U)
108752 #define VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT (5U)
108753 #define VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK)
108754 
108755 #define VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK (0x40U)
108756 #define VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT (6U)
108757 #define VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK)
108758 
108759 #define VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK (0x80U)
108760 #define VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT (7U)
108761 #define VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK)
108762 
108763 #define VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK (0x100U)
108764 #define VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT (8U)
108765 #define VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK)
108766 
108767 #define VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK (0x200U)
108768 #define VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT (9U)
108769 #define VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK)
108770 
108771 #define VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK (0x400U)
108772 #define VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT (10U)
108773 #define VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK)
108774 
108775 #define VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK (0x800U)
108776 #define VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT (11U)
108777 #define VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK)
108778 
108779 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK (0x1000U)
108780 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT (12U)
108781 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK)
108782 
108783 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK (0x2000U)
108784 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT (13U)
108785 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK)
108786 
108787 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK (0x4000U)
108788 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT (14U)
108789 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK)
108790 
108791 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK (0x8000U)
108792 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT (15U)
108793 #define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK)
108794 
108795 #define VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK (0xF0000U)
108796 #define VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT (16U)
108797 #define VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK)
108798 
108799 #define VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_MASK (0xF00000U)
108800 #define VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_SHIFT (20U)
108801 #define VPU_H264_SWREG195_SW_ENC_CIR_START_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_MASK)
108802 
108803 #define VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK (0x3000000U)
108804 #define VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT (24U)
108805 #define VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK)
108806 
108807 #define VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK (0xC000000U)
108808 #define VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT (26U)
108809 #define VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK)
108810 
108811 #define VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK (0xF0000000U)
108812 #define VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT (28U)
108813 #define VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK)
108814 /*! @} */
108815 
108816 /*! @name SWREG196 - Low Latency Controls */
108817 /*! @{ */
108818 
108819 #define VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_MASK (0x3FFU)
108820 #define VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT (0U)
108821 #define VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT)) & VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_MASK)
108822 
108823 #define VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_MASK (0xFFC00U)
108824 #define VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT (10U)
108825 #define VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT)) & VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_MASK)
108826 
108827 #define VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK (0x1FF00000U)
108828 #define VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT (20U)
108829 #define VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT)) & VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK)
108830 
108831 #define VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK (0x20000000U)
108832 #define VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT (29U)
108833 #define VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT)) & VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK)
108834 
108835 #define VPU_H264_SWREG196_SW_LOW_LATENCY_EN_MASK (0x40000000U)
108836 #define VPU_H264_SWREG196_SW_LOW_LATENCY_EN_SHIFT (30U)
108837 #define VPU_H264_SWREG196_SW_LOW_LATENCY_EN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_LOW_LATENCY_EN_SHIFT)) & VPU_H264_SWREG196_SW_LOW_LATENCY_EN_MASK)
108838 
108839 #define VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK (0x80000000U)
108840 #define VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT (31U)
108841 #define VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT)) & VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK)
108842 /*! @} */
108843 
108844 /*! @name SWREG197 - Delta POC extension */
108845 /*! @{ */
108846 
108847 #define VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK (0xFFCU)
108848 #define VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT (2U)
108849 #define VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT)) & VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK)
108850 
108851 #define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK (0x3FF000U)
108852 #define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT (12U)
108853 #define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT)) & VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK)
108854 
108855 #define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK (0xFFC00000U)
108856 #define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT (22U)
108857 #define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT)) & VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK)
108858 /*! @} */
108859 
108860 /*! @name SWREG198 - Long Term Reference Control */
108861 /*! @{ */
108862 
108863 #define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_MASK (0x7U)
108864 #define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_SHIFT (0U)
108865 #define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_MASK)
108866 
108867 #define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_MASK (0x38U)
108868 #define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_SHIFT (3U)
108869 #define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_MASK)
108870 
108871 #define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_MASK (0x1C0U)
108872 #define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_SHIFT (6U)
108873 #define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_MASK)
108874 
108875 #define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_MASK (0xE00U)
108876 #define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_SHIFT (9U)
108877 #define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_MASK)
108878 
108879 #define VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_MASK (0x1000U)
108880 #define VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_SHIFT (12U)
108881 #define VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_SHIFT)) & VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_MASK)
108882 
108883 #define VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_MASK (0x3FE000U)
108884 #define VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_SHIFT (13U)
108885 #define VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_MASK)
108886 
108887 #define VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK (0xFFC00000U)
108888 #define VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT (22U)
108889 #define VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK)
108890 /*! @} */
108891 
108892 /*! @name SWREG199 - Hash Code Control */
108893 /*! @{ */
108894 
108895 #define VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK (0x1U)
108896 #define VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT (0U)
108897 /*! SW_ENC_OSD_ALPHABLEND_ENABLE
108898  *  0b0..disable.
108899  *  0b1..enable.
108900  */
108901 #define VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT)) & VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK)
108902 
108903 #define VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_MASK (0x6U)
108904 #define VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_SHIFT (1U)
108905 #define VPU_H264_SWREG199_SW_ENC_HASH_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_SHIFT)) & VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_MASK)
108906 
108907 #define VPU_H264_SWREG199_SW_ENC_HASH_TYPE_MASK  (0x18U)
108908 #define VPU_H264_SWREG199_SW_ENC_HASH_TYPE_SHIFT (3U)
108909 /*! SW_ENC_HASH_TYPE
108910  *  0b00..none.
108911  *  0b01..crc32.
108912  *  0b10..checksum32
108913  */
108914 #define VPU_H264_SWREG199_SW_ENC_HASH_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_HASH_TYPE_SHIFT)) & VPU_H264_SWREG199_SW_ENC_HASH_TYPE_MASK)
108915 
108916 #define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_MASK (0x3FE0U)
108917 #define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_SHIFT (5U)
108918 #define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_SHIFT)) & VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_MASK)
108919 
108920 #define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_MASK (0x7FC000U)
108921 #define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_SHIFT (14U)
108922 #define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_SHIFT)) & VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_MASK)
108923 
108924 #define VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_MASK (0xFF800000U)
108925 #define VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_SHIFT (23U)
108926 #define VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_SHIFT)) & VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_MASK)
108927 /*! @} */
108928 
108929 /*! @name SWREG200 - Hash Code Value */
108930 /*! @{ */
108931 
108932 #define VPU_H264_SWREG200_SW_ENC_HASH_VAL_MASK   (0xFFFFFFFFU)
108933 #define VPU_H264_SWREG200_SW_ENC_HASH_VAL_SHIFT  (0U)
108934 #define VPU_H264_SWREG200_SW_ENC_HASH_VAL(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG200_SW_ENC_HASH_VAL_SHIFT)) & VPU_H264_SWREG200_SW_ENC_HASH_VAL_MASK)
108935 /*! @} */
108936 
108937 /*! @name SWREG201 - Background SKIP Control 0 */
108938 /*! @{ */
108939 
108940 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR3_MASK  (0xFFU)
108941 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR3_SHIFT (0U)
108942 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR3(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR3_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR3_MASK)
108943 
108944 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR2_MASK  (0xFF00U)
108945 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR2_SHIFT (8U)
108946 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR2(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR2_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR2_MASK)
108947 
108948 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR1_MASK  (0xFF0000U)
108949 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR1_SHIFT (16U)
108950 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR1(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR1_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR1_MASK)
108951 
108952 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR0_MASK  (0xFF000000U)
108953 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR0_SHIFT (24U)
108954 #define VPU_H264_SWREG201_SW_ENC_MEAN_THR0(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR0_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR0_MASK)
108955 /*! @} */
108956 
108957 /*! @name SWREG203 - Background SKIP Control 2 */
108958 /*! @{ */
108959 
108960 #define VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_MASK (0xFFU)
108961 #define VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_SHIFT (0U)
108962 #define VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_SHIFT)) & VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_MASK)
108963 
108964 #define VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_MASK (0xFF00U)
108965 #define VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_SHIFT (8U)
108966 #define VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_SHIFT)) & VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_MASK)
108967 
108968 #define VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_MASK (0xFF000000U)
108969 #define VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_SHIFT (24U)
108970 #define VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_SHIFT)) & VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_MASK)
108971 /*! @} */
108972 
108973 /*! @name SWREG208 - Background SKIP Control 7 */
108974 /*! @{ */
108975 
108976 #define VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK (0x8U)
108977 #define VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT (3U)
108978 #define VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT)) & VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK)
108979 
108980 #define VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_MASK (0x1FF0U)
108981 #define VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT (4U)
108982 #define VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT)) & VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_MASK)
108983 
108984 #define VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_MASK (0x2000U)
108985 #define VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_SHIFT (13U)
108986 #define VPU_H264_SWREG208_SW_ENC_ENABLE_SMART(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_SHIFT)) & VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_MASK)
108987 
108988 #define VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK (0xFC000U)
108989 #define VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT (14U)
108990 #define VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT)) & VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK)
108991 
108992 #define VPU_H264_SWREG208_SW_ENC_SMART_QP_MASK   (0xFC000000U)
108993 #define VPU_H264_SWREG208_SW_ENC_SMART_QP_SHIFT  (26U)
108994 #define VPU_H264_SWREG208_SW_ENC_SMART_QP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_SMART_QP_SHIFT)) & VPU_H264_SWREG208_SW_ENC_SMART_QP_MASK)
108995 /*! @} */
108996 
108997 /*! @name SWREG209 - IPCM Control 0 */
108998 /*! @{ */
108999 
109000 #define VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK (0x8U)
109001 #define VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT (3U)
109002 #define VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK)
109003 
109004 #define VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK (0x10U)
109005 #define VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT (4U)
109006 #define VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT)) & VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK)
109007 
109008 #define VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK (0x3FE0U)
109009 #define VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT (5U)
109010 #define VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK)
109011 
109012 #define VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_MASK  (0x7FC000U)
109013 #define VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_SHIFT (14U)
109014 #define VPU_H264_SWREG209_SW_ENC_IPCM1_TOP(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_MASK)
109015 
109016 #define VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_MASK (0xFF800000U)
109017 #define VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT (23U)
109018 #define VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_MASK)
109019 /*! @} */
109020 
109021 /*! @name SWREG210 - IPCM Control 1 */
109022 /*! @{ */
109023 
109024 #define VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_MASK (0xFF8U)
109025 #define VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT (3U)
109026 #define VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT)) & VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_MASK)
109027 /*! @} */
109028 
109029 /*! @name SWREG211 - IPCM Control 2 */
109030 /*! @{ */
109031 
109032 #define VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_MASK (0xFF8U)
109033 #define VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT (3U)
109034 #define VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT)) & VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_MASK)
109035 /*! @} */
109036 
109037 /*! @name SWREG212 - IPCM Control 3 */
109038 /*! @{ */
109039 
109040 #define VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_MASK  (0xFF8U)
109041 #define VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_SHIFT (3U)
109042 #define VPU_H264_SWREG212_SW_ENC_IPCM2_TOP(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_SHIFT)) & VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_MASK)
109043 /*! @} */
109044 
109045 /*! @name SWREG213 - IPCM Control 4 */
109046 /*! @{ */
109047 
109048 #define VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK (0x3FE0U)
109049 #define VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT (5U)
109050 #define VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT)) & VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK)
109051 /*! @} */
109052 
109053 /*! @name SWREG214 - HW synthesis config register 2, read-only */
109054 /*! @{ */
109055 
109056 #define VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_MASK (0x3FFE000U)
109057 #define VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_SHIFT (13U)
109058 #define VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_MASK)
109059 
109060 #define VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_MASK (0x1C000000U)
109061 #define VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT (26U)
109062 /*! SW_ENC_HWROIMAPVERSION
109063  *  0b000..4 bit per pixel.
109064  *  0b001..8 bit per pixel
109065  */
109066 #define VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_MASK)
109067 
109068 #define VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK (0x40000000U)
109069 #define VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT (30U)
109070 /*! SW_ENC_HWABSQPSUPPORT
109071  *  0b0..not supported.
109072  *  0b1..supported
109073  */
109074 #define VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK)
109075 
109076 #define VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK (0x80000000U)
109077 #define VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT (31U)
109078 /*! SW_ENC_HWLJPEGSUPPORT
109079  *  0b0..not supported.
109080  *  0b1..supported
109081  */
109082 #define VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK)
109083 /*! @} */
109084 
109085 /*! @name SWREG215 - AXI Information 0 */
109086 /*! @{ */
109087 
109088 #define VPU_H264_SWREG215_SW_ENC_TOTALARLEN_MASK (0xFFFFFFFFU)
109089 #define VPU_H264_SWREG215_SW_ENC_TOTALARLEN_SHIFT (0U)
109090 #define VPU_H264_SWREG215_SW_ENC_TOTALARLEN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG215_SW_ENC_TOTALARLEN_SHIFT)) & VPU_H264_SWREG215_SW_ENC_TOTALARLEN_MASK)
109091 /*! @} */
109092 
109093 /*! @name SWREG216 - AXI Information 1 */
109094 /*! @{ */
109095 
109096 #define VPU_H264_SWREG216_SW_ENC_TOTALR_MASK     (0xFFFFFFFFU)
109097 #define VPU_H264_SWREG216_SW_ENC_TOTALR_SHIFT    (0U)
109098 #define VPU_H264_SWREG216_SW_ENC_TOTALR(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG216_SW_ENC_TOTALR_SHIFT)) & VPU_H264_SWREG216_SW_ENC_TOTALR_MASK)
109099 /*! @} */
109100 
109101 /*! @name SWREG217 - AXI Information 2 */
109102 /*! @{ */
109103 
109104 #define VPU_H264_SWREG217_SW_ENC_TOTALAR_MASK    (0xFFFFFFFFU)
109105 #define VPU_H264_SWREG217_SW_ENC_TOTALAR_SHIFT   (0U)
109106 #define VPU_H264_SWREG217_SW_ENC_TOTALAR(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_H264_SWREG217_SW_ENC_TOTALAR_MASK)
109107 /*! @} */
109108 
109109 /*! @name SWREG218 - AXI Information 3 */
109110 /*! @{ */
109111 
109112 #define VPU_H264_SWREG218_SW_ENC_TOTALRLAST_MASK (0xFFFFFFFFU)
109113 #define VPU_H264_SWREG218_SW_ENC_TOTALRLAST_SHIFT (0U)
109114 #define VPU_H264_SWREG218_SW_ENC_TOTALRLAST(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG218_SW_ENC_TOTALRLAST_SHIFT)) & VPU_H264_SWREG218_SW_ENC_TOTALRLAST_MASK)
109115 /*! @} */
109116 
109117 /*! @name SWREG219 - AXI Information 4 */
109118 /*! @{ */
109119 
109120 #define VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_MASK (0xFFFFFFFFU)
109121 #define VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_SHIFT (0U)
109122 #define VPU_H264_SWREG219_SW_ENC_TOTALAWLEN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_SHIFT)) & VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_MASK)
109123 /*! @} */
109124 
109125 /*! @name SWREG220 - AXI Information 5 */
109126 /*! @{ */
109127 
109128 #define VPU_H264_SWREG220_SW_ENC_TOTALW_MASK     (0xFFFFFFFFU)
109129 #define VPU_H264_SWREG220_SW_ENC_TOTALW_SHIFT    (0U)
109130 #define VPU_H264_SWREG220_SW_ENC_TOTALW(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG220_SW_ENC_TOTALW_SHIFT)) & VPU_H264_SWREG220_SW_ENC_TOTALW_MASK)
109131 /*! @} */
109132 
109133 /*! @name SWREG221 - AXI Information 6 */
109134 /*! @{ */
109135 
109136 #define VPU_H264_SWREG221_SW_ENC_TOTALAW_MASK    (0xFFFFFFFFU)
109137 #define VPU_H264_SWREG221_SW_ENC_TOTALAW_SHIFT   (0U)
109138 #define VPU_H264_SWREG221_SW_ENC_TOTALAW(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG221_SW_ENC_TOTALAW_SHIFT)) & VPU_H264_SWREG221_SW_ENC_TOTALAW_MASK)
109139 /*! @} */
109140 
109141 /*! @name SWREG222 - AXI Information 7 */
109142 /*! @{ */
109143 
109144 #define VPU_H264_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU)
109145 #define VPU_H264_SWREG222_SW_ENC_TOTALWLAST_SHIFT (0U)
109146 #define VPU_H264_SWREG222_SW_ENC_TOTALWLAST(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_H264_SWREG222_SW_ENC_TOTALWLAST_MASK)
109147 /*! @} */
109148 
109149 /*! @name SWREG223 - AXI Information 8 */
109150 /*! @{ */
109151 
109152 #define VPU_H264_SWREG223_SW_ENC_TOTALB_MASK     (0xFFFFFFFFU)
109153 #define VPU_H264_SWREG223_SW_ENC_TOTALB_SHIFT    (0U)
109154 #define VPU_H264_SWREG223_SW_ENC_TOTALB(x)       (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG223_SW_ENC_TOTALB_SHIFT)) & VPU_H264_SWREG223_SW_ENC_TOTALB_MASK)
109155 /*! @} */
109156 
109157 /*! @name SWREG224 - control register 4 */
109158 /*! @{ */
109159 
109160 #define VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK (0x3FFU)
109161 #define VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT (0U)
109162 #define VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT)) & VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK)
109163 
109164 #define VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK (0xFFC00U)
109165 #define VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT (10U)
109166 #define VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT)) & VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK)
109167 
109168 #define VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_MASK (0x100000U)
109169 #define VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT (20U)
109170 /*! SW_ENC_SKIPFRAME_EN
109171  *  0b0..no.
109172  *  0b1..yes
109173  */
109174 #define VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT)) & VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_MASK)
109175 
109176 #define VPU_H264_SWREG224_SW_ENC_SSIM_EN_MASK    (0x200000U)
109177 #define VPU_H264_SWREG224_SW_ENC_SSIM_EN_SHIFT   (21U)
109178 /*! SW_ENC_SSIM_EN
109179  *  0b0..Disable.
109180  *  0b1..Enable
109181  */
109182 #define VPU_H264_SWREG224_SW_ENC_SSIM_EN(x)      (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_SSIM_EN_SHIFT)) & VPU_H264_SWREG224_SW_ENC_SSIM_EN_MASK)
109183 
109184 #define VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK (0x80000000U)
109185 #define VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT (31U)
109186 /*! SW_ENC_CHROMA_CONST_EN
109187  *  0b0..no.
109188  *  0b1..yes.
109189  */
109190 #define VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT)) & VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK)
109191 /*! @} */
109192 
109193 /*! @name SWREG225 - Tile Control */
109194 /*! @{ */
109195 
109196 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK (0x1C0U)
109197 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT (6U)
109198 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK)
109199 
109200 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK (0xE00U)
109201 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT (9U)
109202 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK)
109203 
109204 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK (0x1000U)
109205 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT (12U)
109206 /*! SW_ENC_ROIMAP_CUCTRL_ENABLE
109207  *  0b0..Disable.
109208  *  0b1..Enable
109209  */
109210 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK)
109211 
109212 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK (0x2000U)
109213 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT (13U)
109214 /*! SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE
109215  *  0b0..Disable.
109216  *  0b1..Enable
109217  */
109218 #define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK)
109219 /*! @} */
109220 
109221 /*! @name SWREG226 - HW synthesis config register 3, read-only */
109222 /*! @{ */
109223 
109224 #define VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_MASK (0x2U)
109225 #define VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT (1U)
109226 /*! SW_ENC_HWIFRAMEONLY
109227  *  0b0..support I/P/B frame.
109228  *  0b1..only support I frame
109229  */
109230 #define VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_MASK)
109231 
109232 #define VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK (0x4U)
109233 #define VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT (2U)
109234 /*! SW_ENC_HWSTREAMSEGMENTSUPPORT
109235  *  0b0..not supported.
109236  *  0b1..supported
109237  */
109238 #define VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK)
109239 
109240 #define VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK (0x8U)
109241 #define VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT (3U)
109242 /*! SW_ENC_HWSTREAMBUFCHAIN
109243  *  0b0..not supported.
109244  *  0b1..supported
109245  */
109246 #define VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK)
109247 
109248 #define VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK (0x10U)
109249 #define VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT (4U)
109250 /*! SW_ENC_HWINLOOPDSRATIO
109251  *  0b0..1:1
109252  *  0b1..1:2
109253  */
109254 #define VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK)
109255 
109256 #define VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK (0x20U)
109257 #define VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT (5U)
109258 /*! SW_ENC_HWMULTIPASSSUPPORT
109259  *  0b0..not supported.
109260  *  0b1..supported
109261  */
109262 #define VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK)
109263 
109264 #define VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK (0x40U)
109265 #define VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT (6U)
109266 /*! SW_ENC_HWRDOQSUPPORT
109267  *  0b0..not supported.
109268  *  0b1..supported
109269  */
109270 #define VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK)
109271 
109272 #define VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK (0x180U)
109273 #define VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT (7U)
109274 /*! SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE
109275  *  0b00..64.
109276  *  0b01..128.
109277  *  0b10..192.
109278  *  0b11..256
109279  */
109280 #define VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT)) & VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK)
109281 
109282 #define VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U)
109283 #define VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT (9U)
109284 #define VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
109285 
109286 #define VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_MASK (0x400U)
109287 #define VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT (10U)
109288 /*! SW_ENC_HWGMVSUPPORT
109289  *  0b0..not supported.
109290  *  0b1..supported
109291  */
109292 #define VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_MASK)
109293 
109294 #define VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK (0x800U)
109295 #define VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT (11U)
109296 /*! SW_ENC_HWJPEG422SUPPORT
109297  *  0b0..not supported.
109298  *  0b1..supported
109299  */
109300 #define VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK)
109301 
109302 #define VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_MASK (0x7000U)
109303 #define VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT (12U)
109304 #define VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_MASK)
109305 
109306 #define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK (0x1F8000U)
109307 #define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT (15U)
109308 #define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT)) & VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK)
109309 
109310 #define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK (0x7E00000U)
109311 #define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT (21U)
109312 #define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT)) & VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK)
109313 
109314 #define VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_MASK (0x38000000U)
109315 #define VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT (27U)
109316 #define VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_MASK)
109317 
109318 #define VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK (0x40000000U)
109319 #define VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT (30U)
109320 /*! SW_ENC_HWP010REFSUPPORT
109321  *  0b1..P010 tile raster format.
109322  *  0b0..normal format
109323  */
109324 #define VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK)
109325 
109326 #define VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK (0x80000000U)
109327 #define VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT (31U)
109328 /*! SW_ENC_HWSSIMSUPPORT
109329  *  0b0..not supported.
109330  *  0b1..supported
109331  */
109332 #define VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK)
109333 /*! @} */
109334 
109335 /*! @name SWREG235 - RPS encoding control 0 */
109336 /*! @{ */
109337 
109338 #define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK (0x1U)
109339 #define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT (0U)
109340 #define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK)
109341 
109342 #define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK (0x2U)
109343 #define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT (1U)
109344 #define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK)
109345 
109346 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK (0xFFCU)
109347 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT (2U)
109348 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK)
109349 
109350 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK (0x3FF000U)
109351 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT (12U)
109352 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK)
109353 
109354 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK (0xFFC00000U)
109355 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT (22U)
109356 #define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK)
109357 /*! @} */
109358 
109359 /*! @name SWREG236 - RPS encoding control 1 */
109360 /*! @{ */
109361 
109362 #define VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_MASK (0x1000U)
109363 #define VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT (12U)
109364 /*! SW_ENC_P010_REF_ENABLE
109365  *  0b0..not supported.
109366  *  0b1..supported.
109367  */
109368 #define VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT)) & VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_MASK)
109369 
109370 #define VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK (0x2000U)
109371 #define VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT (13U)
109372 #define VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT)) & VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK)
109373 
109374 #define VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK (0x1C000U)
109375 #define VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT (14U)
109376 #define VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK)
109377 
109378 #define VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK (0xE0000U)
109379 #define VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT (17U)
109380 #define VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK)
109381 
109382 #define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK (0x100000U)
109383 #define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT (20U)
109384 #define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK)
109385 
109386 #define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK (0x200000U)
109387 #define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT (21U)
109388 #define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK)
109389 
109390 #define VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK (0xFFC00000U)
109391 #define VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT (22U)
109392 #define VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK)
109393 /*! @} */
109394 
109395 /*! @name SWREG237 - Stride Control */
109396 /*! @{ */
109397 
109398 #define VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_MASK (0x800U)
109399 #define VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_SHIFT (11U)
109400 #define VPU_H264_SWREG237_SW_ENC_DUMMYREADEN(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_SHIFT)) & VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_MASK)
109401 
109402 #define VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_MASK (0xFFFFF000U)
109403 #define VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT (12U)
109404 #define VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT)) & VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_MASK)
109405 /*! @} */
109406 
109407 /*! @name SWREG238 - Dummy Read */
109408 /*! @{ */
109409 
109410 #define VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_MASK (0xFFFFFFFFU)
109411 #define VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT (0U)
109412 #define VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT)) & VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_MASK)
109413 /*! @} */
109414 
109415 /*! @name SWREG239 - Base Address LSB of CTB MADs of current frame. */
109416 /*! @{ */
109417 
109418 #define VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
109419 #define VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT (0U)
109420 #define VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT)) & VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK)
109421 /*! @} */
109422 
109423 /*! @name SWREG241 - Base Address LSB of CTB MADs of previous frame. */
109424 /*! @{ */
109425 
109426 #define VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
109427 #define VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT (0U)
109428 #define VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT)) & VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK)
109429 /*! @} */
109430 
109431 /*! @name SWREG243 - CTB RC Control 0 */
109432 /*! @{ */
109433 
109434 #define VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK (0xFFFFF800U)
109435 #define VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT (11U)
109436 #define VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT)) & VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK)
109437 /*! @} */
109438 
109439 /*! @name SWREG244 - CTB RC Control 1 */
109440 /*! @{ */
109441 
109442 #define VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK (0x4U)
109443 #define VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT (2U)
109444 /*! SW_ENC_ROI3_QP_TYPE
109445  *  0b0..delta
109446  *  0b1..Absolute value
109447  */
109448 #define VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT)) & VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK)
109449 
109450 #define VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK (0x3F8U)
109451 #define VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT (3U)
109452 #define VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT)) & VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK)
109453 
109454 #define VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK (0xFFFFFC00U)
109455 #define VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT (10U)
109456 #define VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT)) & VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK)
109457 /*! @} */
109458 
109459 /*! @name SWREG245 - CTB RC Control 2 */
109460 /*! @{ */
109461 
109462 #define VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK (0x3FFFCU)
109463 #define VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT (2U)
109464 #define VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT)) & VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK)
109465 
109466 #define VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK (0xFFFC0000U)
109467 #define VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT (18U)
109468 #define VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT)) & VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK)
109469 /*! @} */
109470 
109471 /*! @name SWREG246 - CTB RC Control 3 */
109472 /*! @{ */
109473 
109474 #define VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_MASK (0x38U)
109475 #define VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT (3U)
109476 #define VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT)) & VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_MASK)
109477 
109478 #define VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK (0x3FC0U)
109479 #define VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT (6U)
109480 #define VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT)) & VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK)
109481 
109482 #define VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK (0xFFFFC000U)
109483 #define VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT (14U)
109484 #define VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT)) & VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK)
109485 /*! @} */
109486 
109487 /*! @name SWREG247 - CTB RC Control 4 */
109488 /*! @{ */
109489 
109490 #define VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK (0x2U)
109491 #define VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT (1U)
109492 /*! SW_ENC_CTB_RC_PREV_MAD_VALID
109493  *  0b0..no
109494  *  0b1..yes.
109495  */
109496 #define VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT)) & VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK)
109497 
109498 #define VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK (0xFFFFFFC0U)
109499 #define VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT (6U)
109500 #define VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT)) & VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK)
109501 /*! @} */
109502 
109503 /*! @name SWREG248 - CTB RC Control 5 */
109504 /*! @{ */
109505 
109506 #define VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK (0x1U)
109507 #define VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT (0U)
109508 /*! SW_ENC_ROI4_QP_TYPE
109509  *  0b0..delta
109510  *  0b1..Absolute value
109511  */
109512 #define VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT)) & VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK)
109513 
109514 #define VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK (0xFEU)
109515 #define VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT (1U)
109516 #define VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT)) & VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK)
109517 
109518 #define VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK (0xFFFFFF00U)
109519 #define VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT (8U)
109520 #define VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT)) & VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK)
109521 /*! @} */
109522 
109523 /*! @name SWREG249 - register extension for 8K width */
109524 /*! @{ */
109525 
109526 #define VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK (0x8U)
109527 #define VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT (3U)
109528 #define VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK)
109529 
109530 #define VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK (0x10U)
109531 #define VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT (4U)
109532 #define VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK)
109533 
109534 #define VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK (0x20U)
109535 #define VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT (5U)
109536 #define VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK)
109537 
109538 #define VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK (0x40U)
109539 #define VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT (6U)
109540 #define VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK)
109541 
109542 #define VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK (0x80U)
109543 #define VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT (7U)
109544 #define VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK)
109545 
109546 #define VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK (0x100U)
109547 #define VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT (8U)
109548 #define VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK)
109549 
109550 #define VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK (0x200U)
109551 #define VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT (9U)
109552 #define VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK)
109553 
109554 #define VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK (0x400U)
109555 #define VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT (10U)
109556 #define VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK)
109557 
109558 #define VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK (0x800U)
109559 #define VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT (11U)
109560 #define VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK)
109561 
109562 #define VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK (0x1000U)
109563 #define VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT (12U)
109564 #define VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK)
109565 
109566 #define VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK (0x2000U)
109567 #define VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT (13U)
109568 #define VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK)
109569 
109570 #define VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK (0x4000U)
109571 #define VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT (14U)
109572 #define VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK)
109573 
109574 #define VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK (0x8000U)
109575 #define VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT (15U)
109576 #define VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK)
109577 
109578 #define VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK (0x10000U)
109579 #define VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT (16U)
109580 #define VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK)
109581 
109582 #define VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK (0x20000U)
109583 #define VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT (17U)
109584 #define VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK)
109585 
109586 #define VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK (0x40000U)
109587 #define VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT (18U)
109588 #define VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK)
109589 
109590 #define VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK (0x80000U)
109591 #define VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT (19U)
109592 #define VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK)
109593 
109594 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK (0x100000U)
109595 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT (20U)
109596 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK)
109597 
109598 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK (0x200000U)
109599 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT (21U)
109600 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK)
109601 
109602 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK (0x400000U)
109603 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT (22U)
109604 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK)
109605 
109606 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK (0x800000U)
109607 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT (23U)
109608 #define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK)
109609 
109610 #define VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK (0x3000000U)
109611 #define VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT (24U)
109612 #define VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK)
109613 
109614 #define VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_MASK (0xC000000U)
109615 #define VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT (26U)
109616 #define VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_MASK)
109617 
109618 #define VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK (0x10000000U)
109619 #define VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT (28U)
109620 #define VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK)
109621 
109622 #define VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK (0x20000000U)
109623 #define VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT (29U)
109624 #define VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK)
109625 
109626 #define VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK (0xC0000000U)
109627 #define VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT (30U)
109628 #define VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK)
109629 /*! @} */
109630 
109631 /*! @name SWREG250 - Global MV Control 0 */
109632 /*! @{ */
109633 
109634 #define VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK (0x3FFF0U)
109635 #define VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT (4U)
109636 #define VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT)) & VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK)
109637 
109638 #define VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK (0xFFFC0000U)
109639 #define VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT (18U)
109640 #define VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT)) & VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK)
109641 /*! @} */
109642 
109643 /*! @name SWREG251 - Global MV Control 1 */
109644 /*! @{ */
109645 
109646 #define VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK (0x3FFF0U)
109647 #define VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT (4U)
109648 #define VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT)) & VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK)
109649 
109650 #define VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK (0xFFFC0000U)
109651 #define VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT (18U)
109652 #define VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT)) & VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK)
109653 /*! @} */
109654 
109655 /*! @name SWREG252 - ROI3 Area */
109656 /*! @{ */
109657 
109658 #define VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_MASK (0xFFCU)
109659 #define VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT (2U)
109660 #define VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT)) & VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_MASK)
109661 
109662 #define VPU_H264_SWREG252_SW_ENC_ROI3_TOP_MASK   (0x3FF000U)
109663 #define VPU_H264_SWREG252_SW_ENC_ROI3_TOP_SHIFT  (12U)
109664 #define VPU_H264_SWREG252_SW_ENC_ROI3_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG252_SW_ENC_ROI3_TOP_SHIFT)) & VPU_H264_SWREG252_SW_ENC_ROI3_TOP_MASK)
109665 
109666 #define VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_MASK  (0xFFC00000U)
109667 #define VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_SHIFT (22U)
109668 #define VPU_H264_SWREG252_SW_ENC_ROI3_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_SHIFT)) & VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_MASK)
109669 /*! @} */
109670 
109671 /*! @name SWREG253 - ROI3&4 Area */
109672 /*! @{ */
109673 
109674 #define VPU_H264_SWREG253_SW_ENC_ROI4_TOP_MASK   (0xFFCU)
109675 #define VPU_H264_SWREG253_SW_ENC_ROI4_TOP_SHIFT  (2U)
109676 #define VPU_H264_SWREG253_SW_ENC_ROI4_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG253_SW_ENC_ROI4_TOP_SHIFT)) & VPU_H264_SWREG253_SW_ENC_ROI4_TOP_MASK)
109677 
109678 #define VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_MASK  (0x3FF000U)
109679 #define VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_SHIFT (12U)
109680 #define VPU_H264_SWREG253_SW_ENC_ROI4_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_SHIFT)) & VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_MASK)
109681 
109682 #define VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_MASK (0xFFC00000U)
109683 #define VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT (22U)
109684 #define VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT)) & VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_MASK)
109685 /*! @} */
109686 
109687 /*! @name SWREG254 - ROI4&5 Area */
109688 /*! @{ */
109689 
109690 #define VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_MASK  (0xFFCU)
109691 #define VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_SHIFT (2U)
109692 #define VPU_H264_SWREG254_SW_ENC_ROI5_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_SHIFT)) & VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_MASK)
109693 
109694 #define VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_MASK (0x3FF000U)
109695 #define VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT (12U)
109696 #define VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT)) & VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_MASK)
109697 
109698 #define VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_MASK (0xFFC00000U)
109699 #define VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT (22U)
109700 #define VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT)) & VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_MASK)
109701 /*! @} */
109702 
109703 /*! @name SWREG255 - ROI5 Area */
109704 /*! @{ */
109705 
109706 #define VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_MASK (0xFFCU)
109707 #define VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT (2U)
109708 #define VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT)) & VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_MASK)
109709 
109710 #define VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_MASK (0x3FF000U)
109711 #define VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT (12U)
109712 #define VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT)) & VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_MASK)
109713 
109714 #define VPU_H264_SWREG255_SW_ENC_ROI5_TOP_MASK   (0xFFC00000U)
109715 #define VPU_H264_SWREG255_SW_ENC_ROI5_TOP_SHIFT  (22U)
109716 #define VPU_H264_SWREG255_SW_ENC_ROI5_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG255_SW_ENC_ROI5_TOP_SHIFT)) & VPU_H264_SWREG255_SW_ENC_ROI5_TOP_MASK)
109717 /*! @} */
109718 
109719 /*! @name SWREG256 - ROI6 Area */
109720 /*! @{ */
109721 
109722 #define VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_MASK (0xFFCU)
109723 #define VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT (2U)
109724 #define VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT)) & VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_MASK)
109725 
109726 #define VPU_H264_SWREG256_SW_ENC_ROI6_TOP_MASK   (0x3FF000U)
109727 #define VPU_H264_SWREG256_SW_ENC_ROI6_TOP_SHIFT  (12U)
109728 #define VPU_H264_SWREG256_SW_ENC_ROI6_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG256_SW_ENC_ROI6_TOP_SHIFT)) & VPU_H264_SWREG256_SW_ENC_ROI6_TOP_MASK)
109729 
109730 #define VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_MASK  (0xFFC00000U)
109731 #define VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_SHIFT (22U)
109732 #define VPU_H264_SWREG256_SW_ENC_ROI6_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_SHIFT)) & VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_MASK)
109733 /*! @} */
109734 
109735 /*! @name SWREG257 - ROI6&7 Area */
109736 /*! @{ */
109737 
109738 #define VPU_H264_SWREG257_SW_ENC_ROI7_TOP_MASK   (0xFFCU)
109739 #define VPU_H264_SWREG257_SW_ENC_ROI7_TOP_SHIFT  (2U)
109740 #define VPU_H264_SWREG257_SW_ENC_ROI7_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG257_SW_ENC_ROI7_TOP_SHIFT)) & VPU_H264_SWREG257_SW_ENC_ROI7_TOP_MASK)
109741 
109742 #define VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_MASK  (0x3FF000U)
109743 #define VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_SHIFT (12U)
109744 #define VPU_H264_SWREG257_SW_ENC_ROI7_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_SHIFT)) & VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_MASK)
109745 
109746 #define VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_MASK (0xFFC00000U)
109747 #define VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT (22U)
109748 #define VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT)) & VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_MASK)
109749 /*! @} */
109750 
109751 /*! @name SWREG258 - ROI7&8 Area */
109752 /*! @{ */
109753 
109754 #define VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_MASK  (0xFFCU)
109755 #define VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_SHIFT (2U)
109756 #define VPU_H264_SWREG258_SW_ENC_ROI8_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_SHIFT)) & VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_MASK)
109757 
109758 #define VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_MASK (0x3FF000U)
109759 #define VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT (12U)
109760 #define VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT)) & VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_MASK)
109761 
109762 #define VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_MASK (0xFFC00000U)
109763 #define VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT (22U)
109764 #define VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT)) & VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_MASK)
109765 /*! @} */
109766 
109767 /*! @name SWREG259 - ROI8 Area */
109768 /*! @{ */
109769 
109770 #define VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK (0x2U)
109771 #define VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT (1U)
109772 /*! SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE
109773  *  0b0..max tu size 32.
109774  *  0b1..max tu size 16.
109775  */
109776 #define VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT)) & VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK)
109777 
109778 #define VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_MASK (0xFFCU)
109779 #define VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT (2U)
109780 #define VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT)) & VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_MASK)
109781 
109782 #define VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_MASK (0x3FF000U)
109783 #define VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT (12U)
109784 #define VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT)) & VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_MASK)
109785 
109786 #define VPU_H264_SWREG259_SW_ENC_ROI8_TOP_MASK   (0xFFC00000U)
109787 #define VPU_H264_SWREG259_SW_ENC_ROI8_TOP_SHIFT  (22U)
109788 #define VPU_H264_SWREG259_SW_ENC_ROI8_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_ROI8_TOP_SHIFT)) & VPU_H264_SWREG259_SW_ENC_ROI8_TOP_MASK)
109789 /*! @} */
109790 
109791 /*! @name SWREG260 - ROI qp */
109792 /*! @{ */
109793 
109794 #define VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK (0x1U)
109795 #define VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT (0U)
109796 /*! SW_ENC_ROI5_QP_TYPE
109797  *  0b0..delta
109798  *  0b1..Absolute value
109799  */
109800 #define VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK)
109801 
109802 #define VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK (0xFEU)
109803 #define VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT (1U)
109804 #define VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK)
109805 
109806 #define VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK (0x100U)
109807 #define VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT (8U)
109808 /*! SW_ENC_ROI6_QP_TYPE
109809  *  0b0..delta
109810  *  0b1..Absolute value
109811  */
109812 #define VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK)
109813 
109814 #define VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK (0xFE00U)
109815 #define VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT (9U)
109816 #define VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK)
109817 
109818 #define VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK (0x10000U)
109819 #define VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT (16U)
109820 /*! SW_ENC_ROI7_QP_TYPE
109821  *  0b0..delta
109822  *  0b1..Absolute value
109823  */
109824 #define VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK)
109825 
109826 #define VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK (0xFE0000U)
109827 #define VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT (17U)
109828 #define VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK)
109829 
109830 #define VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK (0x1000000U)
109831 #define VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT (24U)
109832 /*! SW_ENC_ROI8_QP_TYPE
109833  *  0b0..delta
109834  *  0b1..Absolute value
109835  */
109836 #define VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK)
109837 
109838 #define VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK (0xFE000000U)
109839 #define VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT (25U)
109840 #define VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK)
109841 /*! @} */
109842 
109843 /*! @name SWREG261 - Stride Control */
109844 /*! @{ */
109845 
109846 #define VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK (0x1U)
109847 #define VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT (0U)
109848 #define VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT)) & VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK)
109849 
109850 #define VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK (0x2U)
109851 #define VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT (1U)
109852 #define VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT)) & VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK)
109853 
109854 #define VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_MASK (0x4U)
109855 #define VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT (2U)
109856 #define VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT)) & VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_MASK)
109857 
109858 #define VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_MASK (0x8U)
109859 #define VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT (3U)
109860 #define VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT)) & VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_MASK)
109861 
109862 #define VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK (0xFF0U)
109863 #define VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT (4U)
109864 #define VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT)) & VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK)
109865 
109866 #define VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK (0x1000U)
109867 #define VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT (12U)
109868 #define VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT)) & VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK)
109869 
109870 #define VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK (0x3E000U)
109871 #define VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT (13U)
109872 #define VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT)) & VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK)
109873 /*! @} */
109874 
109875 /*! @name SWREG265 - Multicore sync ctrl */
109876 /*! @{ */
109877 
109878 #define VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK (0xFFFFU)
109879 #define VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT (0U)
109880 #define VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT)) & VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK)
109881 
109882 #define VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK (0xFFFF0000U)
109883 #define VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT (16U)
109884 #define VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT)) & VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK)
109885 /*! @} */
109886 
109887 /*! @name SWREG266 - Multicore sync address L0 LSB */
109888 /*! @{ */
109889 
109890 #define VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK (0xFFFFFFFFU)
109891 #define VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT (0U)
109892 #define VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT)) & VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK)
109893 /*! @} */
109894 
109895 /*! @name SWREG267 - Multicore sync address L0 MSB */
109896 /*! @{ */
109897 
109898 #define VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK (0xFFFFFFFFU)
109899 #define VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT (0U)
109900 #define VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT)) & VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK)
109901 /*! @} */
109902 
109903 /*! @name SWREG268 - Multicore sync address L1 LSB */
109904 /*! @{ */
109905 
109906 #define VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK (0xFFFFFFFFU)
109907 #define VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT (0U)
109908 #define VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT)) & VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK)
109909 /*! @} */
109910 
109911 /*! @name SWREG269 - Multicore sync address L1 MSB */
109912 /*! @{ */
109913 
109914 #define VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK (0xFFFFFFFFU)
109915 #define VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT (0U)
109916 #define VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT)) & VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK)
109917 /*! @} */
109918 
109919 /*! @name SWREG270 - Multicore sync address recon LSB */
109920 /*! @{ */
109921 
109922 #define VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK (0xFFFFFFFFU)
109923 #define VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT (0U)
109924 #define VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT)) & VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK)
109925 /*! @} */
109926 
109927 /*! @name SWREG271 - Multicore sync address recon MSB */
109928 /*! @{ */
109929 
109930 #define VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK (0xFFFFFFFFU)
109931 #define VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT (0U)
109932 #define VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT)) & VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK)
109933 /*! @} */
109934 
109935 /*! @name SWREG272 - Programmable AXI urgent sideband signals */
109936 /*! @{ */
109937 
109938 #define VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK (0xFFU)
109939 #define VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT (0U)
109940 #define VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK)
109941 
109942 #define VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK (0xFF00U)
109943 #define VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT (8U)
109944 #define VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK)
109945 
109946 #define VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK (0xFF0000U)
109947 #define VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT (16U)
109948 #define VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK)
109949 
109950 #define VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK (0xFF000000U)
109951 #define VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT (24U)
109952 #define VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK)
109953 /*! @} */
109954 
109955 /*! @name SWREG273 - roimap cu ctrl index address LSB */
109956 /*! @{ */
109957 
109958 #define VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK (0xFFFFFFFFU)
109959 #define VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT (0U)
109960 #define VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT)) & VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK)
109961 /*! @} */
109962 
109963 /*! @name SWREG274 - roimap cu ctrl index address MSB */
109964 /*! @{ */
109965 
109966 #define VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK (0xFFFFFFFFU)
109967 #define VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT (0U)
109968 #define VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT)) & VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK)
109969 /*! @} */
109970 
109971 /*! @name SWREG275 - roimap cu ctrl address LSB */
109972 /*! @{ */
109973 
109974 #define VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK (0xFFFFFFFFU)
109975 #define VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT (0U)
109976 #define VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT)) & VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK)
109977 /*! @} */
109978 
109979 /*! @name SWREG276 - roimap cu ctrl address MSB */
109980 /*! @{ */
109981 
109982 #define VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK (0xFFFFFFFFU)
109983 #define VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT (0U)
109984 #define VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT)) & VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK)
109985 /*! @} */
109986 
109987 /*! @name SWREG277 - poc type/bits setting */
109988 /*! @{ */
109989 
109990 #define VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK (0xFFFE0U)
109991 #define VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT (5U)
109992 #define VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT)) & VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK)
109993 
109994 #define VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_MASK (0x300000U)
109995 #define VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_SHIFT (20U)
109996 #define VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_SHIFT)) & VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_MASK)
109997 
109998 #define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_MASK (0x7C00000U)
109999 #define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_SHIFT (22U)
110000 #define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_SHIFT)) & VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_MASK)
110001 
110002 #define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK (0xF8000000U)
110003 #define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT (27U)
110004 #define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT)) & VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK)
110005 /*! @} */
110006 
110007 /*! @name SWREG278 - stream output buffer1 address */
110008 /*! @{ */
110009 
110010 #define VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK (0xFFFFFFFFU)
110011 #define VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT (0U)
110012 #define VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT)) & VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK)
110013 /*! @} */
110014 
110015 /*! @name SWREG280 - stream output buffer1 limit size */
110016 /*! @{ */
110017 
110018 #define VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK (0xFFFFFFFFU)
110019 #define VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT (0U)
110020 #define VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT)) & VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK)
110021 /*! @} */
110022 
110023 /*! @name SWREG281 - poc type/bits setting */
110024 /*! @{ */
110025 
110026 #define VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK (0x3F0U)
110027 #define VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT (4U)
110028 #define VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT)) & VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK)
110029 
110030 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK (0xFFC00U)
110031 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT (10U)
110032 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK)
110033 
110034 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK (0x3FF00000U)
110035 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT (20U)
110036 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK)
110037 
110038 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK (0x40000000U)
110039 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT (30U)
110040 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK)
110041 
110042 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK (0x80000000U)
110043 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT (31U)
110044 #define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK)
110045 /*! @} */
110046 
110047 /*! @name SWREG287 - HW synthesis config register 4, read-only */
110048 /*! @{ */
110049 
110050 #define VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK (0x20000000U)
110051 #define VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT (29U)
110052 /*! SW_ENC_HWSCALER420SUPPORT
110053  *  0b0..not supported.
110054  *  0b1..supported
110055  */
110056 #define VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT)) & VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK)
110057 
110058 #define VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK (0x40000000U)
110059 #define VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT (30U)
110060 /*! SW_ENC_HWCSCEXTENSIONSUPPORT
110061  *  0b0..not supported.
110062  *  0b1..supported
110063  */
110064 #define VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT)) & VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK)
110065 
110066 #define VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK (0x80000000U)
110067 #define VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT (31U)
110068 /*! SW_ENC_HWVIDEOHEIGHTEXT
110069  *  0b0..Not.
110070  *  0b1..Yes.
110071  */
110072 #define VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT)) & VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK)
110073 /*! @} */
110074 
110075 /*! @name SWREG289 - Pre-processor color conversion parameters1 */
110076 /*! @{ */
110077 
110078 #define VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_MASK  (0xFFFFU)
110079 #define VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_SHIFT (0U)
110080 #define VPU_H264_SWREG289_SW_ENC_RGBCOEFFH(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_SHIFT)) & VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_MASK)
110081 
110082 #define VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_MASK  (0xFFFF0000U)
110083 #define VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_SHIFT (16U)
110084 #define VPU_H264_SWREG289_SW_ENC_RGBCOEFFG(x)    (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_SHIFT)) & VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_MASK)
110085 /*! @} */
110086 
110087 
110088 /*!
110089  * @}
110090  */ /* end of group VPU_H264_Register_Masks */
110091 
110092 
110093 /* VPU_H264 - Peripheral instance base addresses */
110094 /** Peripheral VPU_H264 base address */
110095 #define VPU_H264_BASE                            (0x38320000u)
110096 /** Peripheral VPU_H264 base pointer */
110097 #define VPU_H264                                 ((VPU_H264_Type *)VPU_H264_BASE)
110098 /** Array initializer of VPU_H264 peripheral base addresses */
110099 #define VPU_H264_BASE_ADDRS                      { VPU_H264_BASE }
110100 /** Array initializer of VPU_H264 peripheral base pointers */
110101 #define VPU_H264_BASE_PTRS                       { VPU_H264 }
110102 
110103 /*!
110104  * @}
110105  */ /* end of group VPU_H264_Peripheral_Access_Layer */
110106 
110107 
110108 /* ----------------------------------------------------------------------------
110109    -- VPU_HEVC Peripheral Access Layer
110110    ---------------------------------------------------------------------------- */
110111 
110112 /*!
110113  * @addtogroup VPU_HEVC_Peripheral_Access_Layer VPU_HEVC Peripheral Access Layer
110114  * @{
110115  */
110116 
110117 /** VPU_HEVC - Register Layout Typedef */
110118 typedef struct {
110119        uint8_t RESERVED_0[4];
110120   __IO uint32_t SWREG1;                            /**< Interrupt register encoder, offset: 0x4 */
110121   __IO uint32_t SWREG2;                            /**< Data configuration register0, offset: 0x8 */
110122   __IO uint32_t SWREG3;                            /**< Data configuration register1, offset: 0xC */
110123   __IO uint32_t SWREG4;                            /**< control register 0, offset: 0x10 */
110124   __IO uint32_t SWREG5;                            /**< control register 1, offset: 0x14 */
110125        uint8_t RESERVED_1[4];
110126   __IO uint32_t SWREG7;                            /**< control register 3, offset: 0x1C */
110127   __IO uint32_t SWREG8;                            /**< stream output buffer0 address, offset: 0x20 */
110128   __IO uint32_t SWREG9;                            /**< stream output buffer0 limit size, offset: 0x24 */
110129   __IO uint32_t SWREG10;                           /**< sizeTblBase, offset: 0x28 */
110130   __IO uint32_t SWREG11;                           /**< encoded Picture order count, offset: 0x2C */
110131   __IO uint32_t SWREG12;                           /**< input lum base address, offset: 0x30 */
110132   __IO uint32_t SWREG13;                           /**< input cb base address, offset: 0x34 */
110133   __IO uint32_t SWREG14;                           /**< input cr base address, offset: 0x38 */
110134   __IO uint32_t SWREG15;                           /**< recon image luma base address, offset: 0x3C */
110135   __IO uint32_t SWREG16;                           /**< recon image chroma base address, offset: 0x40 */
110136        uint8_t RESERVED_2[4];
110137   __IO uint32_t SWREG18;                           /**< reference picture reconstructed list0 luma0, offset: 0x48 */
110138   __IO uint32_t SWREG19;                           /**< reference picture reconstructed list0 chroma0, offset: 0x4C */
110139        uint8_t RESERVED_3[8];
110140   __IO uint32_t SWREG22;                           /**< Cyclic Intra, offset: 0x58 */
110141   __IO uint32_t SWREG23;                           /**< intra Area, offset: 0x5C */
110142   __IO uint32_t SWREG24;                           /**< ROI1 Area, offset: 0x60 */
110143   __IO uint32_t SWREG25;                           /**< ROI2 Area, offset: 0x64 */
110144   __IO uint32_t SWREG26_H2V2;                      /**< intra size factors. For H2V2 or later version., offset: 0x68 */
110145   __IO uint32_t SWREG27_H2V2;                      /**< intra mode factors . For H2V2 or later version., offset: 0x6C */
110146   __IO uint32_t SWREG28_H2V5;                      /**< inter me SATD lambda config 0. For H2V5 or later version., offset: 0x70 */
110147   __IO uint32_t SWREG29_H2V5;                      /**< inter me SATD lambda config 1.For H2V5 or later version., offset: 0x74 */
110148   __IO uint32_t SWREG30_H2V5;                      /**< inter me SATD lambda config 2. For H2V5 or later version., offset: 0x78 */
110149   __IO uint32_t SWREG31_H2V5;                      /**< inter me SATD lambda config 3. For H2V5 or later version., offset: 0x7C */
110150   __IO uint32_t SWREG32_H2V5;                      /**< inter me SATD lambda config 4. For H2V5 or later version., offset: 0x80 */
110151   __IO uint32_t SWREG33_H2V5;                      /**< inter me SATD lambda config 5. For H2V5 or later version., offset: 0x84 */
110152   __IO uint32_t SWREG34_H2V5;                      /**< inter me SATD lambda config 6. For H2V5 or later version., offset: 0x88 */
110153   __IO uint32_t SWREG35;                           /**< inter prediction parameters1, offset: 0x8C */
110154   __IO uint32_t SWREG36;                           /**< inter prediction parameters2, offset: 0x90 */
110155   __IO uint32_t SWREG37;                           /**< SAO lambda parameter, offset: 0x94 */
110156   __IO uint32_t SWREG38;                           /**< Pre-processor configuration, offset: 0x98 */
110157   __IO uint32_t SWREG39;                           /**< Pre-processor color conversion parameters0, offset: 0x9C */
110158   __IO uint32_t SWREG40;                           /**< Pre-processor color conversion parameters1, offset: 0xA0 */
110159   __IO uint32_t SWREG41;                           /**< Pre-processor color conversion parameters2, offset: 0xA4 */
110160   __IO uint32_t SWREG42;                           /**< Pre-processor Base address for down-scaled output, offset: 0xA8 */
110161   __IO uint32_t SWREG43;                           /**< Pre-processor down-scaled configuration0, offset: 0xAC */
110162   __IO uint32_t SWREG44;                           /**< Pre-processor down-scaled configuration1, offset: 0xB0 */
110163   __IO uint32_t SWREG45;                           /**< Pre-processor down-scaled configuration2, offset: 0xB4 */
110164   __IO uint32_t SWREG46;                           /**< compressed coefficients base address for SAN module., offset: 0xB8 */
110165        uint8_t RESERVED_4[52];
110166   __IO uint32_t SWREG60;                           /**< Base address for recon luma compress table LSB., offset: 0xF0 */
110167        uint8_t RESERVED_5[4];
110168   __IO uint32_t SWREG62;                           /**< Base address for recon Chroma compress table LSB, offset: 0xF8 */
110169        uint8_t RESERVED_6[4];
110170   __IO uint32_t SWREG64;                           /**< Base address for list 0 ref 0 luma compress table LSB., offset: 0x100 */
110171        uint8_t RESERVED_7[4];
110172   __IO uint32_t SWREG66;                           /**< Base address for list 0 ref 0 Chroma compress table LSB., offset: 0x108 */
110173        uint8_t RESERVED_8[20];
110174   __IO uint32_t SWREG72;                           /**< Base address for recon luma 4n base LSB., offset: 0x120 */
110175        uint8_t RESERVED_9[4];
110176   __IO uint32_t SWREG74;                           /**< reference picture reconstructed list0 4n 0, offset: 0x128 */
110177        uint8_t RESERVED_10[12];
110178   __IO uint32_t SWREG78_H2V5;                      /**< inter me SATD lambda config 7. For H2V5 or later version., offset: 0x138 */
110179   __IO uint32_t SWREG79_H2V5;                      /**< inter me SSE lambda config 0. For H2V5 or later version., offset: 0x13C */
110180        uint8_t RESERVED_11[4];
110181   __IO uint32_t SWREG81;                           /**< hardware configuation 0, offset: 0x144 */
110182   __I  uint32_t SWREG82;                           /**< record hardware performance, offset: 0x148 */
110183   __IO uint32_t SWREG83;                           /**< reference picture reconstructed list1 luma0, offset: 0x14C */
110184   __IO uint32_t SWREG84;                           /**< reference picture reconstructed list1 chroma0, offset: 0x150 */
110185        uint8_t RESERVED_12[24];
110186   __IO uint32_t SWREG91;                           /**< reference pictures list1 config, offset: 0x16C */
110187   __IO uint32_t SWREG92;                           /**< reference picture reconstructed list1 4n 0, offset: 0x170 */
110188        uint8_t RESERVED_13[12];
110189   __IO uint32_t SWREG96;                           /**< Base address for list 1 ref 0 luma compress table LSB., offset: 0x180 */
110190        uint8_t RESERVED_14[4];
110191   __IO uint32_t SWREG98;                           /**< Base address for list 1 ref 0 Chroma compress table LSB., offset: 0x188 */
110192        uint8_t RESERVED_15[20];
110193   __IO uint32_t SWREG104;                          /**< reference picture lists modification, offset: 0x1A0 */
110194        uint8_t RESERVED_16[4];
110195   __IO uint32_t SWREG106;                          /**< Min picture size, offset: 0x1A8 */
110196   __IO uint32_t SWREG107;                          /**< Max picture size, offset: 0x1AC */
110197        uint8_t RESERVED_17[4];
110198   __IO uint32_t SWREG109;                          /**< Qp delta map, offset: 0x1B4 */
110199        uint8_t RESERVED_18[4];
110200   __I  uint32_t SWREG111;                          /**< adaptive GOP configuration1, offset: 0x1BC */
110201   __I  uint32_t SWREG112;                          /**< adaptive GOP configuration2, offset: 0x1C0 */
110202   __IO uint32_t SWREG113;                          /**< adaptive GOP configuration3, offset: 0x1C4 */
110203        uint8_t RESERVED_19[20];
110204   __IO uint32_t SWREG119;                          /**< min/max lcu bits number of last picture, offset: 0x1DC */
110205   __IO uint32_t SWREG120;                          /**< total bits number of all lcus of last picture not including slice header bits, offset: 0x1E0 */
110206        uint8_t RESERVED_20[4];
110207   __IO uint32_t SWREG122_H2V5;                     /**< inter me SSE lambda config 1. For H2V5 or later version., offset: 0x1E8 */
110208   __IO uint32_t SWREG123_H2V5;                     /**< inter me SSE lambda config 2. For H2V5 or later version., offset: 0x1EC */
110209   __IO uint32_t SWREG124_H2V5;                     /**< inter me SSE lambda config 3. For H2V5 or later version., offset: 0x1F0 */
110210   __IO uint32_t SWREG125;                          /**< intra SATD lambda config 0, offset: 0x1F4 */
110211   __IO uint32_t SWREG126;                          /**< intra SATD lambda config 1, offset: 0x1F8 */
110212   __IO uint32_t SWREG127;                          /**< intra SATD lambda config 2, offset: 0x1FC */
110213   __IO uint32_t SWREG128;                          /**< intra SATD lambda config 3, offset: 0x200 */
110214   __IO uint32_t SWREG129;                          /**< intra SATD lambda config 4, offset: 0x204 */
110215   __IO uint32_t SWREG130;                          /**< intra SATD lambda config 5, offset: 0x208 */
110216   __IO uint32_t SWREG131;                          /**< intra SATD lambda config 6, offset: 0x20C */
110217   __IO uint32_t SWREG132;                          /**< intra SATD lambda config 7, offset: 0x210 */
110218   __IO uint32_t SWREG133;                          /**< SSE devide 256, offset: 0x214 */
110219   __IO uint32_t SWREG134;                          /**< noise reduction, offset: 0x218 */
110220   __IO uint32_t SWREG135;                          /**< noise reduction 1, offset: 0x21C */
110221   __IO uint32_t SWREG136;                          /**< noise reduction 2, offset: 0x220 */
110222   __IO uint32_t SWREG137;                          /**< noise reduction 3, offset: 0x224 */
110223   __IO uint32_t SWREG138_H2V5;                     /**< inter me SSE lambda config 4. For H2V5 or later version., offset: 0x228 */
110224   __IO uint32_t SWREG139_H2V5;                     /**< inter me SSE lambda config 5. For H2V5 or later version., offset: 0x22C */
110225   __IO uint32_t SWREG140_H2V5;                     /**< inter me SSE lambda config 6. For H2V5 or later version., offset: 0x230 */
110226   __IO uint32_t SWREG141_H2V5;                     /**< inter me SSE lambda config 7. For H2V5 or later version., offset: 0x234 */
110227   __IO uint32_t SWREG142_H2V5;                     /**< inter me SSE lambda config 8. For H2V5 or later version., offset: 0x238 */
110228   __IO uint32_t SWREG143_H2V5;                     /**< inter me SSE lambda config 9. For H2V5 or later version., offset: 0x23C */
110229   __IO uint32_t SWREG144_H2V5;                     /**< inter me SSE lambda config 10. For H2V5 or later version., offset: 0x240 */
110230   __IO uint32_t SWREG145_H2V5;                     /**< inter me SSE lambda config 11. For H2V5 or later version., offset: 0x244 */
110231   __IO uint32_t SWREG146_H2V5;                     /**< inter me SSE lambda config 12. For H2V5 or later version., offset: 0x248 */
110232   __IO uint32_t SWREG147_H2V5;                     /**< inter me SSE lambda config 13. For H2V5 or later version., offset: 0x24C */
110233   __IO uint32_t SWREG148_H2V5;                     /**< inter me SSE lambda config 14. For H2V5 or later version., offset: 0x250 */
110234   __IO uint32_t SWREG149_H2V5;                     /**< inter me SSE lambda config 15. For H2V5 or later version., offset: 0x254 */
110235   __IO uint32_t SWREG150;                          /**< inter me SATD lambda config 8, offset: 0x258 */
110236   __IO uint32_t SWREG151;                          /**< inter me SATD lambda config 9, offset: 0x25C */
110237   __IO uint32_t SWREG152;                          /**< inter me SATD lambda config 10, offset: 0x260 */
110238   __IO uint32_t SWREG153;                          /**< inter me SATD lambda config 11, offset: 0x264 */
110239   __IO uint32_t SWREG154;                          /**< inter me SATD lambda config 12, offset: 0x268 */
110240   __IO uint32_t SWREG155;                          /**< inter me SATD lambda config 13, offset: 0x26C */
110241   __IO uint32_t SWREG156;                          /**< inter me SATD lambda config 14, offset: 0x270 */
110242   __IO uint32_t SWREG157;                          /**< inter me SATD lambda config 15, offset: 0x274 */
110243   __IO uint32_t SWREG158;                          /**< inter me SSE lambda config 16, offset: 0x278 */
110244   __IO uint32_t SWREG159;                          /**< inter me SSE lambda config 17, offset: 0x27C */
110245   __IO uint32_t SWREG160;                          /**< inter me SSE lambda config 18, offset: 0x280 */
110246   __IO uint32_t SWREG161;                          /**< inter me SSE lambda config 19, offset: 0x284 */
110247   __IO uint32_t SWREG162;                          /**< inter me SSE lambda config 20, offset: 0x288 */
110248   __IO uint32_t SWREG163;                          /**< inter me SSE lambda config 21, offset: 0x28C */
110249   __IO uint32_t SWREG164;                          /**< inter me SSE lambda config 22, offset: 0x290 */
110250   __IO uint32_t SWREG165;                          /**< inter me SSE lambda config 23, offset: 0x294 */
110251   __IO uint32_t SWREG166;                          /**< inter me SSE lambda config 24, offset: 0x298 */
110252   __IO uint32_t SWREG167;                          /**< inter me SSE lambda config 25, offset: 0x29C */
110253   __IO uint32_t SWREG168;                          /**< inter me SSE lambda config 26, offset: 0x2A0 */
110254   __IO uint32_t SWREG169;                          /**< inter me SSE lambda config 27, offset: 0x2A4 */
110255        uint8_t RESERVED_21[8];
110256   __IO uint32_t SWREG172;                          /**< inter me SSE lambda config 30, offset: 0x2B0 */
110257   __IO uint32_t SWREG173;                          /**< inter me SSE lambda config 31, offset: 0x2B4 */
110258   __IO uint32_t SWREG174;                          /**< intra SATD lambda config 8, offset: 0x2B8 */
110259   __IO uint32_t SWREG175;                          /**< intra SATD lambda config 9, offset: 0x2BC */
110260   __IO uint32_t SWREG176;                          /**< intra SATD lambda config 10, offset: 0x2C0 */
110261   __IO uint32_t SWREG177;                          /**< intra SATD lambda config 11, offset: 0x2C4 */
110262   __IO uint32_t SWREG178;                          /**< intra SATD lambda config 12, offset: 0x2C8 */
110263   __IO uint32_t SWREG179;                          /**< intra SATD lambda config 13, offset: 0x2CC */
110264   __IO uint32_t SWREG180;                          /**< intra SATD lambda config 14, offset: 0x2D0 */
110265   __IO uint32_t SWREG181;                          /**< intra SATD lambda config 15, offset: 0x2D4 */
110266   __IO uint32_t SWREG182;                          /**< qp fractional part, offset: 0x2D8 */
110267   __I  uint32_t SWREG183;                          /**< qp sum, offset: 0x2DC */
110268   __I  uint32_t SWREG184;                          /**< qp num, offset: 0x2E0 */
110269   __IO uint32_t SWREG185;                          /**< picture complexity. Timeout cycles MSB., offset: 0x2E4 */
110270   __IO uint32_t SWREG186;                          /**< Base address for CU information table LSB, offset: 0x2E8 */
110271        uint8_t RESERVED_22[4];
110272   __IO uint32_t SWREG188;                          /**< Base address for CU information LSB, offset: 0x2F0 */
110273        uint8_t RESERVED_23[4];
110274   __IO uint32_t SWREG190;                          /**< Long-term reference pictures config, offset: 0x2F8 */
110275   __IO uint32_t SWREG191;                          /**< Temporal scalable config, offset: 0x2FC */
110276        uint8_t RESERVED_24[12];
110277   __IO uint32_t SWREG195;                          /**< register extension for ctu_size=16, offset: 0x30C */
110278   __IO uint32_t SWREG196;                          /**< Low Latency Controls, offset: 0x310 */
110279   __IO uint32_t SWREG197;                          /**< Delta POC extension, offset: 0x314 */
110280   __IO uint32_t SWREG198;                          /**< Long Term Reference Control, offset: 0x318 */
110281   __IO uint32_t SWREG199;                          /**< Hash Code Control, offset: 0x31C */
110282   __IO uint32_t SWREG200;                          /**< Hash Code Value, offset: 0x320 */
110283   __IO uint32_t SWREG201;                          /**< Background SKIP Control 0, offset: 0x324 */
110284   __IO uint32_t SWREG202;                          /**< Background SKIP Control 1, offset: 0x328 */
110285   __IO uint32_t SWREG203;                          /**< Background SKIP Control 2, offset: 0x32C */
110286   __IO uint32_t SWREG204;                          /**< Background SKIP Control 3, offset: 0x330 */
110287   __IO uint32_t SWREG205;                          /**< Background SKIP Control 4, offset: 0x334 */
110288   __IO uint32_t SWREG206;                          /**< Background SKIP Control 5, offset: 0x338 */
110289   __IO uint32_t SWREG207;                          /**< Background SKIP Control 6, offset: 0x33C */
110290   __IO uint32_t SWREG208;                          /**< Background SKIP Control 7, offset: 0x340 */
110291   __IO uint32_t SWREG209;                          /**< IPCM Control 0, offset: 0x344 */
110292   __IO uint32_t SWREG210;                          /**< IPCM Control 1, offset: 0x348 */
110293   __IO uint32_t SWREG211;                          /**< IPCM Control 2, offset: 0x34C */
110294   __IO uint32_t SWREG212;                          /**< IPCM Control 3, offset: 0x350 */
110295   __IO uint32_t SWREG213;                          /**< IPCM Control 4, offset: 0x354 */
110296   __I  uint32_t SWREG214;                          /**< HW synthesis config register 2, read-only, offset: 0x358 */
110297   __I  uint32_t SWREG215;                          /**< AXI Information 0, offset: 0x35C */
110298   __I  uint32_t SWREG216;                          /**< AXI Information 1, offset: 0x360 */
110299   __I  uint32_t SWREG217;                          /**< AXI Information 2, offset: 0x364 */
110300   __I  uint32_t SWREG218;                          /**< AXI Information 3, offset: 0x368 */
110301   __I  uint32_t SWREG219;                          /**< AXI Information 4, offset: 0x36C */
110302   __I  uint32_t SWREG220;                          /**< AXI Information 5, offset: 0x370 */
110303   __I  uint32_t SWREG221;                          /**< AXI Information 6, offset: 0x374 */
110304   __I  uint32_t SWREG222;                          /**< AXI Information 7, offset: 0x378 */
110305   __I  uint32_t SWREG223;                          /**< AXI Information 8, offset: 0x37C */
110306   __IO uint32_t SWREG224;                          /**< control register 4, offset: 0x380 */
110307   __IO uint32_t SWREG225;                          /**< Tile Control, offset: 0x384 */
110308   __I  uint32_t SWREG226;                          /**< HW synthesis config register 3, read-only, offset: 0x388 */
110309        uint8_t RESERVED_25[32];
110310   __IO uint32_t SWREG235;                          /**< RPS encoding control 0, offset: 0x3AC */
110311   __IO uint32_t SWREG236;                          /**< RPS encoding control 1, offset: 0x3B0 */
110312   __IO uint32_t SWREG237;                          /**< Stride Control, offset: 0x3B4 */
110313   __IO uint32_t SWREG238;                          /**< Dummy Read, offset: 0x3B8 */
110314   __IO uint32_t SWREG239;                          /**< Base Address LSB of CTB MADs of current frame., offset: 0x3BC */
110315        uint8_t RESERVED_26[4];
110316   __IO uint32_t SWREG241;                          /**< Base Address LSB of CTB MADs of previous frame., offset: 0x3C4 */
110317        uint8_t RESERVED_27[4];
110318   __IO uint32_t SWREG243;                          /**< CTB RC Control 0, offset: 0x3CC */
110319   __IO uint32_t SWREG244;                          /**< CTB RC Control 1, offset: 0x3D0 */
110320   __IO uint32_t SWREG245;                          /**< CTB RC Control 2, offset: 0x3D4 */
110321   __IO uint32_t SWREG246;                          /**< CTB RC Control 3, offset: 0x3D8 */
110322   __IO uint32_t SWREG247;                          /**< CTB RC Control 4, offset: 0x3DC */
110323   __IO uint32_t SWREG248;                          /**< CTB RC Control 5, offset: 0x3E0 */
110324   __IO uint32_t SWREG249;                          /**< register extension for 8K width, offset: 0x3E4 */
110325   __IO uint32_t SWREG250;                          /**< Global MV Control 0, offset: 0x3E8 */
110326   __IO uint32_t SWREG251;                          /**< Global MV Control 1, offset: 0x3EC */
110327   __IO uint32_t SWREG252;                          /**< ROI3 Area, offset: 0x3F0 */
110328   __IO uint32_t SWREG253;                          /**< ROI3&4 Area, offset: 0x3F4 */
110329   __IO uint32_t SWREG254;                          /**< ROI4&5 Area, offset: 0x3F8 */
110330   __IO uint32_t SWREG255;                          /**< ROI5 Area, offset: 0x3FC */
110331   __IO uint32_t SWREG256;                          /**< ROI6 Area, offset: 0x400 */
110332   __IO uint32_t SWREG257;                          /**< ROI6&7 Area, offset: 0x404 */
110333   __IO uint32_t SWREG258;                          /**< ROI7&8 Area, offset: 0x408 */
110334   __IO uint32_t SWREG259;                          /**< ROI8 Area, offset: 0x40C */
110335   __IO uint32_t SWREG260;                          /**< ROI qp, offset: 0x410 */
110336   __IO uint32_t SWREG261;                          /**< Stride Control, offset: 0x414 */
110337        uint8_t RESERVED_28[12];
110338   __IO uint32_t SWREG265;                          /**< Multicore sync ctrl, offset: 0x424 */
110339   __IO uint32_t SWREG266;                          /**< Multicore sync address L0 LSB, offset: 0x428 */
110340   __IO uint32_t SWREG267;                          /**< Multicore sync address L0 MSB, offset: 0x42C */
110341   __IO uint32_t SWREG268;                          /**< Multicore sync address L1 LSB, offset: 0x430 */
110342   __IO uint32_t SWREG269;                          /**< Multicore sync address L1 MSB, offset: 0x434 */
110343   __IO uint32_t SWREG270;                          /**< Multicore sync address recon LSB, offset: 0x438 */
110344   __IO uint32_t SWREG271;                          /**< Multicore sync address recon MSB, offset: 0x43C */
110345   __IO uint32_t SWREG272;                          /**< Programmable AXI urgent sideband signals, offset: 0x440 */
110346   __IO uint32_t SWREG273;                          /**< roimap cu ctrl index address LSB, offset: 0x444 */
110347   __IO uint32_t SWREG274;                          /**< roimap cu ctrl index address MSB, offset: 0x448 */
110348   __IO uint32_t SWREG275;                          /**< roimap cu ctrl address LSB, offset: 0x44C */
110349   __IO uint32_t SWREG276;                          /**< roimap cu ctrl address MSB, offset: 0x450 */
110350   __IO uint32_t SWREG277;                          /**< poc type/bits setting, offset: 0x454 */
110351   __IO uint32_t SWREG278;                          /**< stream output buffer1 address, offset: 0x458 */
110352        uint8_t RESERVED_29[4];
110353   __IO uint32_t SWREG280;                          /**< stream output buffer1 limit size, offset: 0x460 */
110354   __IO uint32_t SWREG281;                          /**< poc type/bits setting, offset: 0x464 */
110355        uint8_t RESERVED_30[20];
110356   __I  uint32_t SWREG287;                          /**< HW synthesis config register 4, read-only, offset: 0x47C */
110357        uint8_t RESERVED_31[4];
110358   __IO uint32_t SWREG289;                          /**< Pre-processor color conversion parameters1, offset: 0x484 */
110359 } VPU_HEVC_Type;
110360 
110361 /* ----------------------------------------------------------------------------
110362    -- VPU_HEVC Register Masks
110363    ---------------------------------------------------------------------------- */
110364 
110365 /*!
110366  * @addtogroup VPU_HEVC_Register_Masks VPU_HEVC Register Masks
110367  * @{
110368  */
110369 
110370 /*! @name SWREG1 - Interrupt register encoder */
110371 /*! @{ */
110372 
110373 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_MASK          (0x1U)
110374 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_SHIFT         (0U)
110375 #define VPU_HEVC_SWREG1_SW_ENC_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_MASK)
110376 
110377 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_MASK      (0x2U)
110378 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_SHIFT     (1U)
110379 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS(x)        (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_MASK)
110380 
110381 #define VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK (0x4U)
110382 #define VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT (2U)
110383 #define VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK)
110384 
110385 #define VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK (0x8U)
110386 #define VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT (3U)
110387 #define VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK)
110388 
110389 #define VPU_HEVC_SWREG1_SW_ENC_SW_RESET_MASK     (0x10U)
110390 #define VPU_HEVC_SWREG1_SW_ENC_SW_RESET_SHIFT    (4U)
110391 #define VPU_HEVC_SWREG1_SW_ENC_SW_RESET(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_SW_RESET_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_SW_RESET_MASK)
110392 
110393 #define VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_MASK  (0x20U)
110394 #define VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_SHIFT (5U)
110395 #define VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_MASK)
110396 
110397 #define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_MASK      (0x40U)
110398 #define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_SHIFT     (6U)
110399 #define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_MASK)
110400 
110401 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK (0x80U)
110402 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT (7U)
110403 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK)
110404 
110405 #define VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK (0x100U)
110406 #define VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT (8U)
110407 #define VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK)
110408 
110409 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK (0x200U)
110410 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT (9U)
110411 #define VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK)
110412 
110413 #define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_MASK  (0x800U)
110414 #define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT (11U)
110415 #define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_MASK)
110416 
110417 #define VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK (0x1000U)
110418 #define VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT (12U)
110419 #define VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK)
110420 /*! @} */
110421 
110422 /*! @name SWREG2 - Data configuration register0 */
110423 /*! @{ */
110424 
110425 #define VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK (0xFU)
110426 #define VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT (0U)
110427 #define VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK)
110428 
110429 #define VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK (0xF0U)
110430 #define VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT (4U)
110431 #define VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK)
110432 
110433 #define VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_MASK     (0xF00U)
110434 #define VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_SHIFT    (8U)
110435 #define VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_MASK)
110436 
110437 #define VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_MASK    (0xF000U)
110438 #define VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_SHIFT   (12U)
110439 #define VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_MASK)
110440 
110441 #define VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_MASK  (0xFF0000U)
110442 #define VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_SHIFT (16U)
110443 #define VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_MASK)
110444 
110445 #define VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_MASK (0xFF000000U)
110446 #define VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT (24U)
110447 #define VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_MASK)
110448 /*! @} */
110449 
110450 /*! @name SWREG3 - Data configuration register1 */
110451 /*! @{ */
110452 
110453 #define VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK (0x2U)
110454 #define VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT (1U)
110455 #define VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK)
110456 
110457 #define VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK (0x4U)
110458 #define VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT (2U)
110459 #define VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK)
110460 
110461 #define VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_MASK    (0x8U)
110462 #define VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_SHIFT   (3U)
110463 #define VPU_HEVC_SWREG3_SW_ENC_SLICE_INT(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_MASK)
110464 
110465 #define VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK (0xF00000U)
110466 #define VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT (20U)
110467 #define VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK)
110468 
110469 #define VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_MASK  (0x1000000U)
110470 #define VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT (24U)
110471 /*! SW_ENC_AXI_RD_ID_E
110472  *  0b0..disable.
110473  *  0b1..enable.
110474  */
110475 #define VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_MASK)
110476 
110477 #define VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_MASK  (0x2000000U)
110478 #define VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT (25U)
110479 /*! SW_ENC_AXI_WR_ID_E
110480  *  0b0..disable.
110481  *  0b1..enable.
110482  */
110483 #define VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_MASK)
110484 
110485 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK (0x4000000U)
110486 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT (26U)
110487 /*! SW_ENC_CLOCK_GATE_INTER_H264_E
110488  *  0b0..clock always on.
110489  *  0b1..hardware clock gating control
110490  */
110491 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK)
110492 
110493 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK (0x8000000U)
110494 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT (27U)
110495 /*! SW_ENC_CLOCK_GATE_INTER_H265_E
110496  *  0b0..clock always on.
110497  *  0b1..hardware clock gating control
110498  */
110499 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK)
110500 
110501 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK (0x10000000U)
110502 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT (28U)
110503 /*! SW_ENC_CLOCK_GATE_INTER_E
110504  *  0b0..clock always on.
110505  *  0b1..hardware clock gating control
110506  */
110507 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK)
110508 
110509 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK (0x20000000U)
110510 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT (29U)
110511 /*! SW_ENC_CLOCK_GATE_ENCODER_H264_E
110512  *  0b0..clock always on.
110513  *  0b1..hardware clock gating control
110514  */
110515 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK)
110516 
110517 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK (0x40000000U)
110518 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT (30U)
110519 /*! SW_ENC_CLOCK_GATE_ENCODER_H265_E
110520  *  0b0..clock always on.
110521  *  0b1..hardware clock gating control
110522  */
110523 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK)
110524 
110525 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK (0x80000000U)
110526 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT (31U)
110527 /*! SW_ENC_CLOCK_GATE_ENCODER_E
110528  *  0b0..clock always on.
110529  *  0b1..hardware clock gating control
110530  */
110531 #define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK)
110532 /*! @} */
110533 
110534 /*! @name SWREG4 - control register 0 */
110535 /*! @{ */
110536 
110537 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK (0x7U)
110538 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT (0U)
110539 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK)
110540 
110541 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK (0x38U)
110542 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT (3U)
110543 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK)
110544 
110545 #define VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_MASK   (0x40U)
110546 #define VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_SHIFT  (6U)
110547 #define VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_MASK)
110548 
110549 #define VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_MASK (0x80U)
110550 #define VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_SHIFT (7U)
110551 #define VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_MASK)
110552 
110553 #define VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK (0x100U)
110554 #define VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT (8U)
110555 #define VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK)
110556 
110557 #define VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_MASK (0x800U)
110558 #define VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT (11U)
110559 #define VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT)) & VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_MASK)
110560 
110561 #define VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_MASK (0x1000U)
110562 #define VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_SHIFT (12U)
110563 #define VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_MASK)
110564 
110565 #define VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK (0x3E000U)
110566 #define VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT (13U)
110567 #define VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK)
110568 
110569 #define VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK (0x40000U)
110570 #define VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT (18U)
110571 /*! SW_ENC_OUTPUT_STRM_MODE
110572  *  0b0..byte stream
110573  *  0b1..Nal stream
110574  */
110575 #define VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK)
110576 
110577 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK (0x180000U)
110578 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT (19U)
110579 /*! SW_ENC_MAX_TRB_SIZE
110580  *  0b00..4x4
110581  *  0b01..8x8
110582  *  0b10..16x16
110583  *  0b11..32x32
110584  */
110585 #define VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK)
110586 
110587 #define VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK (0x600000U)
110588 #define VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT (21U)
110589 /*! SW_ENC_MIN_TRB_SIZE
110590  *  0b00..4x4
110591  *  0b01..8x8
110592  *  0b10..16x16
110593  *  0b11..32x32
110594  */
110595 #define VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK)
110596 
110597 #define VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_MASK  (0x1800000U)
110598 #define VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT (23U)
110599 /*! SW_ENC_MAX_CB_SIZE
110600  *  0b00..8x8
110601  *  0b01..16x16
110602  *  0b10..32x32
110603  *  0b11..64x64
110604  */
110605 #define VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_MASK)
110606 
110607 #define VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_MASK  (0x6000000U)
110608 #define VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT (25U)
110609 /*! SW_ENC_MIN_CB_SIZE
110610  *  0b00..8x8
110611  *  0b01..16x16
110612  *  0b10..32x32
110613  *  0b11..64x64
110614  */
110615 #define VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_MASK)
110616 
110617 #define VPU_HEVC_SWREG4_SW_ENC_MODE_MASK         (0xE0000000U)
110618 #define VPU_HEVC_SWREG4_SW_ENC_MODE_SHIFT        (29U)
110619 /*! SW_ENC_MODE
110620  *  0b001..hevc.
110621  *  0b010..h264.
110622  *  0b100..jpeg
110623  */
110624 #define VPU_HEVC_SWREG4_SW_ENC_MODE(x)           (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MODE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MODE_MASK)
110625 /*! @} */
110626 
110627 /*! @name SWREG5 - control register 1 */
110628 /*! @{ */
110629 
110630 #define VPU_HEVC_SWREG5_SW_ENC_E_MASK            (0x1U)
110631 #define VPU_HEVC_SWREG5_SW_ENC_E_SHIFT           (0U)
110632 #define VPU_HEVC_SWREG5_SW_ENC_E(x)              (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_E_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_E_MASK)
110633 
110634 #define VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK (0x6U)
110635 #define VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT (1U)
110636 #define VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK)
110637 
110638 #define VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_MASK (0x40U)
110639 #define VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_SHIFT (6U)
110640 /*! SW_ENC_OUTPUT_CU_INFO_ENABLED
110641  *  0b0..disable
110642  *  0b1..enable
110643  */
110644 #define VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_MASK)
110645 
110646 #define VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK (0x100U)
110647 #define VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT (8U)
110648 /*! SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG
110649  *  0b0..no
110650  *  0b1..yes
110651  */
110652 #define VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK)
110653 
110654 #define VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK (0x200U)
110655 #define VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT (9U)
110656 /*! SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG
110657  *  0b0..disable
110658  *  0b1..enable
110659  */
110660 #define VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK)
110661 
110662 #define VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_MASK   (0x3FF800U)
110663 #define VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT  (11U)
110664 #define VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_MASK)
110665 
110666 #define VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_MASK    (0xFFC00000U)
110667 #define VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_SHIFT   (22U)
110668 #define VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_MASK)
110669 /*! @} */
110670 
110671 /*! @name SWREG7 - control register 3 */
110672 /*! @{ */
110673 
110674 #define VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK (0xFU)
110675 #define VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT (0U)
110676 #define VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK)
110677 
110678 #define VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK (0xF0U)
110679 #define VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT (4U)
110680 #define VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK)
110681 
110682 #define VPU_HEVC_SWREG7_SW_ENC_PIC_QP_MASK       (0x3F00U)
110683 #define VPU_HEVC_SWREG7_SW_ENC_PIC_QP_SHIFT      (8U)
110684 #define VPU_HEVC_SWREG7_SW_ENC_PIC_QP(x)         (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_PIC_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_PIC_QP_MASK)
110685 
110686 #define VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK (0xC000U)
110687 #define VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT (14U)
110688 #define VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK)
110689 
110690 #define VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_MASK (0x1FE0000U)
110691 #define VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT (17U)
110692 #define VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_MASK)
110693 
110694 #define VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK (0x2000000U)
110695 #define VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT (25U)
110696 #define VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK)
110697 
110698 #define VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_MASK  (0xFC000000U)
110699 #define VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT (26U)
110700 #define VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_MASK)
110701 /*! @} */
110702 
110703 /*! @name SWREG8 - stream output buffer0 address */
110704 /*! @{ */
110705 
110706 #define VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK (0xFFFFFFFFU)
110707 #define VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT (0U)
110708 #define VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT)) & VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK)
110709 /*! @} */
110710 
110711 /*! @name SWREG9 - stream output buffer0 limit size */
110712 /*! @{ */
110713 
110714 #define VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK (0xFFFFFFFFU)
110715 #define VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT (0U)
110716 #define VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT)) & VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK)
110717 /*! @} */
110718 
110719 /*! @name SWREG10 - sizeTblBase */
110720 /*! @{ */
110721 
110722 #define VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK (0xFFFFFFFFU)
110723 #define VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT (0U)
110724 #define VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT)) & VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK)
110725 /*! @} */
110726 
110727 /*! @name SWREG11 - encoded Picture order count */
110728 /*! @{ */
110729 
110730 #define VPU_HEVC_SWREG11_SW_ENC_POC_MASK         (0xFFFFFFFFU)
110731 #define VPU_HEVC_SWREG11_SW_ENC_POC_SHIFT        (0U)
110732 #define VPU_HEVC_SWREG11_SW_ENC_POC(x)           (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG11_SW_ENC_POC_SHIFT)) & VPU_HEVC_SWREG11_SW_ENC_POC_MASK)
110733 /*! @} */
110734 
110735 /*! @name SWREG12 - input lum base address */
110736 /*! @{ */
110737 
110738 #define VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_MASK (0xFFFFFFFFU)
110739 #define VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT (0U)
110740 #define VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT)) & VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_MASK)
110741 /*! @} */
110742 
110743 /*! @name SWREG13 - input cb base address */
110744 /*! @{ */
110745 
110746 #define VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_MASK (0xFFFFFFFFU)
110747 #define VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT (0U)
110748 #define VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT)) & VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_MASK)
110749 /*! @} */
110750 
110751 /*! @name SWREG14 - input cr base address */
110752 /*! @{ */
110753 
110754 #define VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_MASK (0xFFFFFFFFU)
110755 #define VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT (0U)
110756 #define VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT)) & VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_MASK)
110757 /*! @} */
110758 
110759 /*! @name SWREG15 - recon image luma base address */
110760 /*! @{ */
110761 
110762 #define VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_MASK (0xFFFFFFFFU)
110763 #define VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT (0U)
110764 #define VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT)) & VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_MASK)
110765 /*! @} */
110766 
110767 /*! @name SWREG16 - recon image chroma base address */
110768 /*! @{ */
110769 
110770 #define VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK (0xFFFFFFFFU)
110771 #define VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT (0U)
110772 #define VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT)) & VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK)
110773 /*! @} */
110774 
110775 /*! @name SWREG18 - reference picture reconstructed list0 luma0 */
110776 /*! @{ */
110777 
110778 #define VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK (0xFFFFFFFFU)
110779 #define VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT (0U)
110780 #define VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT)) & VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK)
110781 /*! @} */
110782 
110783 /*! @name SWREG19 - reference picture reconstructed list0 chroma0 */
110784 /*! @{ */
110785 
110786 #define VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK (0xFFFFFFFFU)
110787 #define VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT (0U)
110788 #define VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT)) & VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK)
110789 /*! @} */
110790 
110791 /*! @name SWREG22 - Cyclic Intra */
110792 /*! @{ */
110793 
110794 #define VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_MASK (0xFU)
110795 #define VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT (0U)
110796 #define VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT)) & VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_MASK)
110797 
110798 #define VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_MASK (0x3FFF0U)
110799 #define VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT (4U)
110800 #define VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT)) & VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_MASK)
110801 
110802 #define VPU_HEVC_SWREG22_SW_ENC_CIR_START_MASK   (0xFFFC0000U)
110803 #define VPU_HEVC_SWREG22_SW_ENC_CIR_START_SHIFT  (18U)
110804 #define VPU_HEVC_SWREG22_SW_ENC_CIR_START(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG22_SW_ENC_CIR_START_SHIFT)) & VPU_HEVC_SWREG22_SW_ENC_CIR_START_MASK)
110805 /*! @} */
110806 
110807 /*! @name SWREG23 - intra Area */
110808 /*! @{ */
110809 
110810 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK (0xFFU)
110811 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT (0U)
110812 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK)
110813 
110814 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK (0xFF00U)
110815 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT (8U)
110816 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK)
110817 
110818 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK (0xFF0000U)
110819 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT (16U)
110820 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK)
110821 
110822 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK (0xFF000000U)
110823 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT (24U)
110824 #define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK)
110825 /*! @} */
110826 
110827 /*! @name SWREG24 - ROI1 Area */
110828 /*! @{ */
110829 
110830 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_MASK (0xFFU)
110831 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT (0U)
110832 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_MASK)
110833 
110834 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_MASK    (0xFF00U)
110835 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_SHIFT   (8U)
110836 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_MASK)
110837 
110838 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_MASK  (0xFF0000U)
110839 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT (16U)
110840 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_MASK)
110841 
110842 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_MASK   (0xFF000000U)
110843 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_SHIFT  (24U)
110844 #define VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_MASK)
110845 /*! @} */
110846 
110847 /*! @name SWREG25 - ROI2 Area */
110848 /*! @{ */
110849 
110850 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_MASK (0xFFU)
110851 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT (0U)
110852 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_MASK)
110853 
110854 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_MASK    (0xFF00U)
110855 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_SHIFT   (8U)
110856 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_MASK)
110857 
110858 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_MASK  (0xFF0000U)
110859 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT (16U)
110860 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_MASK)
110861 
110862 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_MASK   (0xFF000000U)
110863 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_SHIFT  (24U)
110864 #define VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_MASK)
110865 /*! @} */
110866 
110867 /*! @name SWREG26_H2V2 - intra size factors. For H2V2 or later version. */
110868 /*! @{ */
110869 
110870 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK (0xFFCU)
110871 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT (2U)
110872 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT)) & VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK)
110873 
110874 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK (0x3FF000U)
110875 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT (12U)
110876 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT)) & VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK)
110877 
110878 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK (0xFFC00000U)
110879 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT (22U)
110880 #define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT)) & VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK)
110881 /*! @} */
110882 
110883 /*! @name SWREG27_H2V2 - intra mode factors . For H2V2 or later version. */
110884 /*! @{ */
110885 
110886 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK (0x7F0U)
110887 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT (4U)
110888 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK)
110889 
110890 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK (0x1F800U)
110891 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT (11U)
110892 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK)
110893 
110894 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK (0x3E0000U)
110895 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT (17U)
110896 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK)
110897 
110898 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK (0xFFC00000U)
110899 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT (22U)
110900 #define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK)
110901 /*! @} */
110902 
110903 /*! @name SWREG28_H2V5 - inter me SATD lambda config 0. For H2V5 or later version. */
110904 /*! @{ */
110905 
110906 #define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK (0x7FFC0U)
110907 #define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT (6U)
110908 #define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK)
110909 
110910 #define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK (0xFFF80000U)
110911 #define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT (19U)
110912 #define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK)
110913 /*! @} */
110914 
110915 /*! @name SWREG29_H2V5 - inter me SATD lambda config 1.For H2V5 or later version. */
110916 /*! @{ */
110917 
110918 #define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK (0x7FFC0U)
110919 #define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT (6U)
110920 #define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK)
110921 
110922 #define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK (0xFFF80000U)
110923 #define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT (19U)
110924 #define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK)
110925 /*! @} */
110926 
110927 /*! @name SWREG30_H2V5 - inter me SATD lambda config 2. For H2V5 or later version. */
110928 /*! @{ */
110929 
110930 #define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK (0x7FFC0U)
110931 #define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT (6U)
110932 #define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK)
110933 
110934 #define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK (0xFFF80000U)
110935 #define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT (19U)
110936 #define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK)
110937 /*! @} */
110938 
110939 /*! @name SWREG31_H2V5 - inter me SATD lambda config 3. For H2V5 or later version. */
110940 /*! @{ */
110941 
110942 #define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK (0x7FFC0U)
110943 #define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT (6U)
110944 #define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK)
110945 
110946 #define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK (0xFFF80000U)
110947 #define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT (19U)
110948 #define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK)
110949 /*! @} */
110950 
110951 /*! @name SWREG32_H2V5 - inter me SATD lambda config 4. For H2V5 or later version. */
110952 /*! @{ */
110953 
110954 #define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK (0x7FFC0U)
110955 #define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT (6U)
110956 #define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK)
110957 
110958 #define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK (0xFFF80000U)
110959 #define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT (19U)
110960 #define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK)
110961 /*! @} */
110962 
110963 /*! @name SWREG33_H2V5 - inter me SATD lambda config 5. For H2V5 or later version. */
110964 /*! @{ */
110965 
110966 #define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK (0x7FFC0U)
110967 #define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT (6U)
110968 #define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK)
110969 
110970 #define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK (0xFFF80000U)
110971 #define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT (19U)
110972 #define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK)
110973 /*! @} */
110974 
110975 /*! @name SWREG34_H2V5 - inter me SATD lambda config 6. For H2V5 or later version. */
110976 /*! @{ */
110977 
110978 #define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK (0x7FFC0U)
110979 #define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT (6U)
110980 #define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK)
110981 
110982 #define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK (0xFFF80000U)
110983 #define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT (19U)
110984 #define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK)
110985 /*! @} */
110986 
110987 /*! @name SWREG35 - inter prediction parameters1 */
110988 /*! @{ */
110989 
110990 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK (0xFFU)
110991 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT (0U)
110992 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK)
110993 
110994 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK (0x7F00U)
110995 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT (8U)
110996 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK)
110997 
110998 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK (0x38000U)
110999 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT (15U)
111000 #define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK)
111001 
111002 #define VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK (0xFFFC0000U)
111003 #define VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT (18U)
111004 #define VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK)
111005 /*! @} */
111006 
111007 /*! @name SWREG36 - inter prediction parameters2 */
111008 /*! @{ */
111009 
111010 #define VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK (0x3U)
111011 #define VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT (0U)
111012 /*! SW_ENC_OUTPUT_BITWIDTH_CHROMA
111013  *  0b00..8 bit.
111014  *  0b01..9 bit.
111015  *  0b10..10 bit.
111016  */
111017 #define VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK)
111018 
111019 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK (0x3CU)
111020 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT (2U)
111021 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK)
111022 
111023 #define VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK (0x1FC0U)
111024 #define VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT (6U)
111025 #define VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK)
111026 
111027 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK (0x7FE000U)
111028 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT (13U)
111029 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK)
111030 
111031 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK (0xFF800000U)
111032 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT (23U)
111033 #define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK)
111034 /*! @} */
111035 
111036 /*! @name SWREG37 - SAO lambda parameter */
111037 /*! @{ */
111038 
111039 #define VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_MASK   (0xFU)
111040 #define VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_SHIFT  (0U)
111041 #define VPU_HEVC_SWREG37_SW_ENC_CHROFFSET(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_SHIFT)) & VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_MASK)
111042 
111043 #define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_MASK (0x3FFF0U)
111044 #define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_SHIFT (4U)
111045 #define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_SHIFT)) & VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_MASK)
111046 
111047 #define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_MASK (0xFFFC0000U)
111048 #define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_SHIFT (18U)
111049 #define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_SHIFT)) & VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_MASK)
111050 /*! @} */
111051 
111052 /*! @name SWREG38 - Pre-processor configuration */
111053 /*! @{ */
111054 
111055 #define VPU_HEVC_SWREG38_SW_ENC_MIRROR_MASK      (0x1U)
111056 #define VPU_HEVC_SWREG38_SW_ENC_MIRROR_SHIFT     (0U)
111057 #define VPU_HEVC_SWREG38_SW_ENC_MIRROR(x)        (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_MIRROR_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_MIRROR_MASK)
111058 
111059 #define VPU_HEVC_SWREG38_SW_ENC_YFILL_MASK       (0xEU)
111060 #define VPU_HEVC_SWREG38_SW_ENC_YFILL_SHIFT      (1U)
111061 #define VPU_HEVC_SWREG38_SW_ENC_YFILL(x)         (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_YFILL_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_YFILL_MASK)
111062 
111063 #define VPU_HEVC_SWREG38_SW_ENC_XFILL_MASK       (0x30U)
111064 #define VPU_HEVC_SWREG38_SW_ENC_XFILL_SHIFT      (4U)
111065 #define VPU_HEVC_SWREG38_SW_ENC_XFILL(x)         (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_XFILL_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_XFILL_MASK)
111066 
111067 #define VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_MASK   (0xFFFC0U)
111068 #define VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_SHIFT  (6U)
111069 #define VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_MASK)
111070 
111071 #define VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_MASK   (0xF00000U)
111072 #define VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_SHIFT  (20U)
111073 #define VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_MASK)
111074 
111075 #define VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK (0x3000000U)
111076 #define VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT (24U)
111077 /*! SW_ENC_OUTPUT_BITWIDTH_LUM
111078  *  0b00..8 bit.
111079  *  0b01..9 bit.
111080  *  0b10..10 bit.
111081  */
111082 #define VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK)
111083 
111084 #define VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_MASK (0xC000000U)
111085 #define VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT (26U)
111086 /*! SW_ENC_INPUT_ROTATION
111087  *  0b00..disabled.
111088  *  0b01..90 degrees right.
111089  *  0b10..90 degrees left.
111090  *  0b11..180 degree right.
111091  */
111092 #define VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_MASK)
111093 
111094 #define VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_MASK (0xF0000000U)
111095 #define VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT (28U)
111096 /*! SW_ENC_INPUT_FORMAT
111097  *  0b0001..YUV420SP
111098  *  0b0010..YUYV422
111099  *  0b0011..UYVY422
111100  *  0b0100..RGB565
111101  *  0b0101..RGB555
111102  *  0b0110..RGB444
111103  *  0b0111..RGB888
111104  *  0b1000..RGB101010
111105  *  0b1001..I010
111106  *  0b1010..P010
111107  *  0b1011..PACKED10BITPLANAR
111108  *  0b1100..Y0L2
111109  *  0b1101..DAHUAHEVC
111110  *  0b1110..DAHUAH264
111111  */
111112 #define VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_MASK)
111113 /*! @} */
111114 
111115 /*! @name SWREG39 - Pre-processor color conversion parameters0 */
111116 /*! @{ */
111117 
111118 #define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_MASK   (0xFFFFU)
111119 #define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_SHIFT  (0U)
111120 #define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_SHIFT)) & VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_MASK)
111121 
111122 #define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_MASK   (0xFFFF0000U)
111123 #define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_SHIFT  (16U)
111124 #define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_SHIFT)) & VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_MASK)
111125 /*! @} */
111126 
111127 /*! @name SWREG40 - Pre-processor color conversion parameters1 */
111128 /*! @{ */
111129 
111130 #define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_MASK   (0xFFFFU)
111131 #define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_SHIFT  (0U)
111132 #define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_SHIFT)) & VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_MASK)
111133 
111134 #define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_MASK   (0xFFFF0000U)
111135 #define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_SHIFT  (16U)
111136 #define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_SHIFT)) & VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_MASK)
111137 /*! @} */
111138 
111139 /*! @name SWREG41 - Pre-processor color conversion parameters2 */
111140 /*! @{ */
111141 
111142 #define VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_MASK    (0x3EU)
111143 #define VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_SHIFT   (1U)
111144 #define VPU_HEVC_SWREG41_SW_ENC_BMASKMSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_MASK)
111145 
111146 #define VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_MASK    (0x7C0U)
111147 #define VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_SHIFT   (6U)
111148 #define VPU_HEVC_SWREG41_SW_ENC_GMASKMSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_MASK)
111149 
111150 #define VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_MASK    (0xF800U)
111151 #define VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_SHIFT   (11U)
111152 #define VPU_HEVC_SWREG41_SW_ENC_RMASKMSB(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_MASK)
111153 
111154 #define VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_MASK   (0xFFFF0000U)
111155 #define VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_SHIFT  (16U)
111156 #define VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_MASK)
111157 /*! @} */
111158 
111159 /*! @name SWREG42 - Pre-processor Base address for down-scaled output */
111160 /*! @{ */
111161 
111162 #define VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK (0xFFFFFFFFU)
111163 #define VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT (0U)
111164 #define VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT)) & VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK)
111165 /*! @} */
111166 
111167 /*! @name SWREG43 - Pre-processor down-scaled configuration0 */
111168 /*! @{ */
111169 
111170 #define VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_MASK  (0x3U)
111171 #define VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_SHIFT (0U)
111172 /*! SW_ENC_SCALE_MODE
111173  *  0b00..disabled.
111174  *  0b01..scaling only.
111175  *  0b10..scale+encode
111176  */
111177 #define VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_MASK)
111178 
111179 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK (0x4U)
111180 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT (2U)
111181 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK)
111182 
111183 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK (0x7FFF8U)
111184 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT (3U)
111185 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK)
111186 
111187 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK (0xFFF80000U)
111188 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT (19U)
111189 #define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK)
111190 /*! @} */
111191 
111192 /*! @name SWREG44 - Pre-processor down-scaled configuration1 */
111193 /*! @{ */
111194 
111195 #define VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK (0x3U)
111196 #define VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT (0U)
111197 #define VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT)) & VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK)
111198 
111199 #define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK (0x3FFFCU)
111200 #define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT (2U)
111201 #define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT)) & VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK)
111202 
111203 #define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK (0xFFFC0000U)
111204 #define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT (18U)
111205 #define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT)) & VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK)
111206 /*! @} */
111207 
111208 /*! @name SWREG45 - Pre-processor down-scaled configuration2 */
111209 /*! @{ */
111210 
111211 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK (0x4U)
111212 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT (2U)
111213 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK)
111214 
111215 #define VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK (0x78U)
111216 #define VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT (3U)
111217 #define VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK)
111218 
111219 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK (0x80U)
111220 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT (7U)
111221 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK)
111222 
111223 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK (0x100U)
111224 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT (8U)
111225 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK)
111226 
111227 #define VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK (0x200U)
111228 #define VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT (9U)
111229 #define VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK)
111230 
111231 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK (0xC00U)
111232 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT (10U)
111233 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK)
111234 
111235 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK (0x3000U)
111236 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT (12U)
111237 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK)
111238 
111239 #define VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK (0x7FFC000U)
111240 #define VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT (14U)
111241 #define VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK)
111242 
111243 #define VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_MASK (0x8000000U)
111244 #define VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT (27U)
111245 #define VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_MASK)
111246 
111247 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK (0xF0000000U)
111248 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT (28U)
111249 #define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK)
111250 /*! @} */
111251 
111252 /*! @name SWREG46 - compressed coefficients base address for SAN module. */
111253 /*! @{ */
111254 
111255 #define VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK (0xFFFFFFFFU)
111256 #define VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT (0U)
111257 #define VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT)) & VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK)
111258 /*! @} */
111259 
111260 /*! @name SWREG60 - Base address for recon luma compress table LSB. */
111261 /*! @{ */
111262 
111263 #define VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
111264 #define VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
111265 #define VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK)
111266 /*! @} */
111267 
111268 /*! @name SWREG62 - Base address for recon Chroma compress table LSB */
111269 /*! @{ */
111270 
111271 #define VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
111272 #define VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
111273 #define VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK)
111274 /*! @} */
111275 
111276 /*! @name SWREG64 - Base address for list 0 ref 0 luma compress table LSB. */
111277 /*! @{ */
111278 
111279 #define VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
111280 #define VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
111281 #define VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
111282 /*! @} */
111283 
111284 /*! @name SWREG66 - Base address for list 0 ref 0 Chroma compress table LSB. */
111285 /*! @{ */
111286 
111287 #define VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
111288 #define VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
111289 #define VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
111290 /*! @} */
111291 
111292 /*! @name SWREG72 - Base address for recon luma 4n base LSB. */
111293 /*! @{ */
111294 
111295 #define VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK (0xFFFFFFFFU)
111296 #define VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT (0U)
111297 #define VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT)) & VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK)
111298 /*! @} */
111299 
111300 /*! @name SWREG74 - reference picture reconstructed list0 4n 0 */
111301 /*! @{ */
111302 
111303 #define VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK (0xFFFFFFFFU)
111304 #define VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT (0U)
111305 #define VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT)) & VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK)
111306 /*! @} */
111307 
111308 /*! @name SWREG78_H2V5 - inter me SATD lambda config 7. For H2V5 or later version. */
111309 /*! @{ */
111310 
111311 #define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK (0x7FFC0U)
111312 #define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT (6U)
111313 #define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK)
111314 
111315 #define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK (0xFFF80000U)
111316 #define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT (19U)
111317 #define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK)
111318 /*! @} */
111319 
111320 /*! @name SWREG79_H2V5 - inter me SSE lambda config 0. For H2V5 or later version. */
111321 /*! @{ */
111322 
111323 #define VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK (0xFFFFF800U)
111324 #define VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT (11U)
111325 #define VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK)
111326 /*! @} */
111327 
111328 /*! @name SWREG81 - hardware configuation 0 */
111329 /*! @{ */
111330 
111331 #define VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_MASK  (0x7FFFFFU)
111332 #define VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_SHIFT (0U)
111333 #define VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_SHIFT)) & VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_MASK)
111334 
111335 #define VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK (0x800000U)
111336 #define VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT (23U)
111337 #define VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT)) & VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK)
111338 
111339 #define VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_MASK   (0xFF000000U)
111340 #define VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_SHIFT  (24U)
111341 #define VPU_HEVC_SWREG81_SW_ENC_MAX_BURST(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_SHIFT)) & VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_MASK)
111342 /*! @} */
111343 
111344 /*! @name SWREG82 - record hardware performance */
111345 /*! @{ */
111346 
111347 #define VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_MASK (0xFFFFFFFFU)
111348 #define VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT (0U)
111349 #define VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT)) & VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_MASK)
111350 /*! @} */
111351 
111352 /*! @name SWREG83 - reference picture reconstructed list1 luma0 */
111353 /*! @{ */
111354 
111355 #define VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK (0xFFFFFFFFU)
111356 #define VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT (0U)
111357 #define VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT)) & VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK)
111358 /*! @} */
111359 
111360 /*! @name SWREG84 - reference picture reconstructed list1 chroma0 */
111361 /*! @{ */
111362 
111363 #define VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK (0xFFFFFFFFU)
111364 #define VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT (0U)
111365 #define VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT)) & VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK)
111366 /*! @} */
111367 
111368 /*! @name SWREG91 - reference pictures list1 config */
111369 /*! @{ */
111370 
111371 #define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK (0x4U)
111372 #define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT (2U)
111373 /*! SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE
111374  *  0b0..disable
111375  *  0b1..enable.
111376  */
111377 #define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK)
111378 
111379 #define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK (0x8U)
111380 #define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT (3U)
111381 /*! SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE
111382  *  0b0..disable
111383  *  0b1..enable.
111384  */
111385 #define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK)
111386 
111387 #define VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK (0x10U)
111388 #define VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT (4U)
111389 #define VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK)
111390 
111391 #define VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK (0xC0U)
111392 #define VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT (6U)
111393 #define VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK)
111394 
111395 #define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK (0x100U)
111396 #define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT (8U)
111397 #define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK)
111398 
111399 #define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK (0x200U)
111400 #define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT (9U)
111401 #define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK)
111402 
111403 #define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_MASK (0xFFC00U)
111404 #define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT (10U)
111405 #define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_MASK)
111406 
111407 #define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK (0x100000U)
111408 #define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT (20U)
111409 #define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK)
111410 
111411 #define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK (0x200000U)
111412 #define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT (21U)
111413 #define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK)
111414 
111415 #define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_MASK (0xFFC00000U)
111416 #define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT (22U)
111417 #define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_MASK)
111418 /*! @} */
111419 
111420 /*! @name SWREG92 - reference picture reconstructed list1 4n 0 */
111421 /*! @{ */
111422 
111423 #define VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK (0xFFFFFFFFU)
111424 #define VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT (0U)
111425 #define VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT)) & VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK)
111426 /*! @} */
111427 
111428 /*! @name SWREG96 - Base address for list 1 ref 0 luma compress table LSB. */
111429 /*! @{ */
111430 
111431 #define VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
111432 #define VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
111433 #define VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
111434 /*! @} */
111435 
111436 /*! @name SWREG98 - Base address for list 1 ref 0 Chroma compress table LSB. */
111437 /*! @{ */
111438 
111439 #define VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
111440 #define VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
111441 #define VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
111442 /*! @} */
111443 
111444 /*! @name SWREG104 - reference picture lists modification */
111445 /*! @{ */
111446 
111447 #define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_MASK (0x1U)
111448 #define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_SHIFT (0U)
111449 #define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_MASK)
111450 
111451 #define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_MASK (0x1EU)
111452 #define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_SHIFT (1U)
111453 #define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_MASK)
111454 
111455 #define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_MASK (0x10000U)
111456 #define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_SHIFT (16U)
111457 #define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_MASK)
111458 
111459 #define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_MASK (0x1E0000U)
111460 #define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_SHIFT (17U)
111461 #define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_MASK)
111462 
111463 #define VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_MASK  (0x60000000U)
111464 #define VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_SHIFT (29U)
111465 #define VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_MASK)
111466 
111467 #define VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_MASK (0x80000000U)
111468 #define VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_SHIFT (31U)
111469 #define VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_MASK)
111470 /*! @} */
111471 
111472 /*! @name SWREG106 - Min picture size */
111473 /*! @{ */
111474 
111475 #define VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_MASK (0xFFFFFFFFU)
111476 #define VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_SHIFT (0U)
111477 #define VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_SHIFT)) & VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_MASK)
111478 /*! @} */
111479 
111480 /*! @name SWREG107 - Max picture size */
111481 /*! @{ */
111482 
111483 #define VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_MASK (0xFFFFFFFFU)
111484 #define VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_SHIFT (0U)
111485 #define VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_SHIFT)) & VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_MASK)
111486 /*! @} */
111487 
111488 /*! @name SWREG109 - Qp delta map */
111489 /*! @{ */
111490 
111491 #define VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK (0xFFFFFFFFU)
111492 #define VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT (0U)
111493 #define VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT)) & VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK)
111494 /*! @} */
111495 
111496 /*! @name SWREG111 - adaptive GOP configuration1 */
111497 /*! @{ */
111498 
111499 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U)
111500 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT (12U)
111501 #define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
111502 /*! @} */
111503 
111504 /*! @name SWREG112 - adaptive GOP configuration2 */
111505 /*! @{ */
111506 
111507 #define VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_MASK (0xFFFFF000U)
111508 #define VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT (12U)
111509 #define VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT)) & VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_MASK)
111510 /*! @} */
111511 
111512 /*! @name SWREG113 - adaptive GOP configuration3 */
111513 /*! @{ */
111514 
111515 #define VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK (0xFFFFFFFFU)
111516 #define VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT (0U)
111517 #define VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT)) & VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK)
111518 /*! @} */
111519 
111520 /*! @name SWREG119 - min/max lcu bits number of last picture */
111521 /*! @{ */
111522 
111523 #define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_MASK (0xFFFFU)
111524 #define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_SHIFT (0U)
111525 #define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_SHIFT)) & VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_MASK)
111526 
111527 #define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_MASK (0xFFFF0000U)
111528 #define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_SHIFT (16U)
111529 #define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_SHIFT)) & VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_MASK)
111530 /*! @} */
111531 
111532 /*! @name SWREG120 - total bits number of all lcus of last picture not including slice header bits */
111533 /*! @{ */
111534 
111535 #define VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_MASK (0xFFFFFFFFU)
111536 #define VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT (0U)
111537 #define VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT)) & VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_MASK)
111538 /*! @} */
111539 
111540 /*! @name SWREG122_H2V5 - inter me SSE lambda config 1. For H2V5 or later version. */
111541 /*! @{ */
111542 
111543 #define VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK (0xFFFFF800U)
111544 #define VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT (11U)
111545 #define VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK)
111546 /*! @} */
111547 
111548 /*! @name SWREG123_H2V5 - inter me SSE lambda config 2. For H2V5 or later version. */
111549 /*! @{ */
111550 
111551 #define VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK (0xFFFFF800U)
111552 #define VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT (11U)
111553 #define VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK)
111554 /*! @} */
111555 
111556 /*! @name SWREG124_H2V5 - inter me SSE lambda config 3. For H2V5 or later version. */
111557 /*! @{ */
111558 
111559 #define VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK (0xFFFFF800U)
111560 #define VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT (11U)
111561 #define VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK)
111562 /*! @} */
111563 
111564 /*! @name SWREG125 - intra SATD lambda config 0 */
111565 /*! @{ */
111566 
111567 #define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK (0x3FFF0U)
111568 #define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT (4U)
111569 #define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT)) & VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK)
111570 
111571 #define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK (0xFFFC0000U)
111572 #define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT (18U)
111573 #define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT)) & VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK)
111574 /*! @} */
111575 
111576 /*! @name SWREG126 - intra SATD lambda config 1 */
111577 /*! @{ */
111578 
111579 #define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK (0x3FFF0U)
111580 #define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT (4U)
111581 #define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT)) & VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK)
111582 
111583 #define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK (0xFFFC0000U)
111584 #define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT (18U)
111585 #define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT)) & VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK)
111586 /*! @} */
111587 
111588 /*! @name SWREG127 - intra SATD lambda config 2 */
111589 /*! @{ */
111590 
111591 #define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK (0x3FFF0U)
111592 #define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT (4U)
111593 #define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT)) & VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK)
111594 
111595 #define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK (0xFFFC0000U)
111596 #define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT (18U)
111597 #define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT)) & VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK)
111598 /*! @} */
111599 
111600 /*! @name SWREG128 - intra SATD lambda config 3 */
111601 /*! @{ */
111602 
111603 #define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK (0x3FFF0U)
111604 #define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT (4U)
111605 #define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT)) & VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK)
111606 
111607 #define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK (0xFFFC0000U)
111608 #define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT (18U)
111609 #define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT)) & VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK)
111610 /*! @} */
111611 
111612 /*! @name SWREG129 - intra SATD lambda config 4 */
111613 /*! @{ */
111614 
111615 #define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK (0x3FFF0U)
111616 #define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT (4U)
111617 #define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT)) & VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK)
111618 
111619 #define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK (0xFFFC0000U)
111620 #define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT (18U)
111621 #define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT)) & VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK)
111622 /*! @} */
111623 
111624 /*! @name SWREG130 - intra SATD lambda config 5 */
111625 /*! @{ */
111626 
111627 #define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK (0x3FFF0U)
111628 #define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT (4U)
111629 #define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT)) & VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK)
111630 
111631 #define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK (0xFFFC0000U)
111632 #define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT (18U)
111633 #define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT)) & VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK)
111634 /*! @} */
111635 
111636 /*! @name SWREG131 - intra SATD lambda config 6 */
111637 /*! @{ */
111638 
111639 #define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK (0x3FFF0U)
111640 #define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT (4U)
111641 #define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT)) & VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK)
111642 
111643 #define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK (0xFFFC0000U)
111644 #define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT (18U)
111645 #define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT)) & VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK)
111646 /*! @} */
111647 
111648 /*! @name SWREG132 - intra SATD lambda config 7 */
111649 /*! @{ */
111650 
111651 #define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK (0x3FFF0U)
111652 #define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT (4U)
111653 #define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT)) & VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK)
111654 
111655 #define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK (0xFFFC0000U)
111656 #define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT (18U)
111657 #define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT)) & VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK)
111658 /*! @} */
111659 
111660 /*! @name SWREG133 - SSE devide 256 */
111661 /*! @{ */
111662 
111663 #define VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_MASK (0xFFFFFFFFU)
111664 #define VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_SHIFT (0U)
111665 #define VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_SHIFT)) & VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_MASK)
111666 /*! @} */
111667 
111668 /*! @name SWREG134 - noise reduction */
111669 /*! @{ */
111670 
111671 #define VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_MASK (0xFFFFU)
111672 #define VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_SHIFT (0U)
111673 #define VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_SHIFT)) & VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_MASK)
111674 
111675 #define VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_MASK  (0x3F000000U)
111676 #define VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_SHIFT (24U)
111677 #define VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_SHIFT)) & VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_MASK)
111678 
111679 #define VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_MASK (0xC0000000U)
111680 #define VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_SHIFT (30U)
111681 #define VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_SHIFT)) & VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_MASK)
111682 /*! @} */
111683 
111684 /*! @name SWREG135 - noise reduction 1 */
111685 /*! @{ */
111686 
111687 #define VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_MASK (0x3FFFFE0U)
111688 #define VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_SHIFT (5U)
111689 #define VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_SHIFT)) & VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_MASK)
111690 
111691 #define VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_MASK (0xFC000000U)
111692 #define VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_SHIFT (26U)
111693 #define VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_SHIFT)) & VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_MASK)
111694 /*! @} */
111695 
111696 /*! @name SWREG136 - noise reduction 2 */
111697 /*! @{ */
111698 
111699 #define VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_MASK (0xFFFFU)
111700 #define VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_SHIFT (0U)
111701 #define VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_SHIFT)) & VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_MASK)
111702 
111703 #define VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_MASK  (0xFFFF0000U)
111704 #define VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_SHIFT (16U)
111705 #define VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_SHIFT)) & VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_MASK)
111706 /*! @} */
111707 
111708 /*! @name SWREG137 - noise reduction 3 */
111709 /*! @{ */
111710 
111711 #define VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_MASK (0xFFFFF800U)
111712 #define VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_SHIFT (11U)
111713 #define VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_SHIFT)) & VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_MASK)
111714 /*! @} */
111715 
111716 /*! @name SWREG138_H2V5 - inter me SSE lambda config 4. For H2V5 or later version. */
111717 /*! @{ */
111718 
111719 #define VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK (0xFFFFF800U)
111720 #define VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT (11U)
111721 #define VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK)
111722 /*! @} */
111723 
111724 /*! @name SWREG139_H2V5 - inter me SSE lambda config 5. For H2V5 or later version. */
111725 /*! @{ */
111726 
111727 #define VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK (0xFFFFF800U)
111728 #define VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT (11U)
111729 #define VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK)
111730 /*! @} */
111731 
111732 /*! @name SWREG140_H2V5 - inter me SSE lambda config 6. For H2V5 or later version. */
111733 /*! @{ */
111734 
111735 #define VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK (0xFFFFF800U)
111736 #define VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT (11U)
111737 #define VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK)
111738 /*! @} */
111739 
111740 /*! @name SWREG141_H2V5 - inter me SSE lambda config 7. For H2V5 or later version. */
111741 /*! @{ */
111742 
111743 #define VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK (0xFFFFF800U)
111744 #define VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT (11U)
111745 #define VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK)
111746 /*! @} */
111747 
111748 /*! @name SWREG142_H2V5 - inter me SSE lambda config 8. For H2V5 or later version. */
111749 /*! @{ */
111750 
111751 #define VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK (0xFFFFF800U)
111752 #define VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT (11U)
111753 #define VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK)
111754 /*! @} */
111755 
111756 /*! @name SWREG143_H2V5 - inter me SSE lambda config 9. For H2V5 or later version. */
111757 /*! @{ */
111758 
111759 #define VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK (0xFFFFF800U)
111760 #define VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT (11U)
111761 #define VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK)
111762 /*! @} */
111763 
111764 /*! @name SWREG144_H2V5 - inter me SSE lambda config 10. For H2V5 or later version. */
111765 /*! @{ */
111766 
111767 #define VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK (0xFFFFF800U)
111768 #define VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT (11U)
111769 #define VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK)
111770 /*! @} */
111771 
111772 /*! @name SWREG145_H2V5 - inter me SSE lambda config 11. For H2V5 or later version. */
111773 /*! @{ */
111774 
111775 #define VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK (0xFFFFF800U)
111776 #define VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT (11U)
111777 #define VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK)
111778 /*! @} */
111779 
111780 /*! @name SWREG146_H2V5 - inter me SSE lambda config 12. For H2V5 or later version. */
111781 /*! @{ */
111782 
111783 #define VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK (0xFFFFF800U)
111784 #define VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT (11U)
111785 #define VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK)
111786 /*! @} */
111787 
111788 /*! @name SWREG147_H2V5 - inter me SSE lambda config 13. For H2V5 or later version. */
111789 /*! @{ */
111790 
111791 #define VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK (0xFFFFF800U)
111792 #define VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT (11U)
111793 #define VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK)
111794 /*! @} */
111795 
111796 /*! @name SWREG148_H2V5 - inter me SSE lambda config 14. For H2V5 or later version. */
111797 /*! @{ */
111798 
111799 #define VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK (0xFFFFF800U)
111800 #define VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT (11U)
111801 #define VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK)
111802 /*! @} */
111803 
111804 /*! @name SWREG149_H2V5 - inter me SSE lambda config 15. For H2V5 or later version. */
111805 /*! @{ */
111806 
111807 #define VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK (0xFFFFF800U)
111808 #define VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT (11U)
111809 #define VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK)
111810 /*! @} */
111811 
111812 /*! @name SWREG150 - inter me SATD lambda config 8 */
111813 /*! @{ */
111814 
111815 #define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK (0x7FFC0U)
111816 #define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT (6U)
111817 #define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT)) & VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK)
111818 
111819 #define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK (0xFFF80000U)
111820 #define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT (19U)
111821 #define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT)) & VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK)
111822 /*! @} */
111823 
111824 /*! @name SWREG151 - inter me SATD lambda config 9 */
111825 /*! @{ */
111826 
111827 #define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK (0x7FFC0U)
111828 #define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT (6U)
111829 #define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT)) & VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK)
111830 
111831 #define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK (0xFFF80000U)
111832 #define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT (19U)
111833 #define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT)) & VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK)
111834 /*! @} */
111835 
111836 /*! @name SWREG152 - inter me SATD lambda config 10 */
111837 /*! @{ */
111838 
111839 #define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK (0x7FFC0U)
111840 #define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT (6U)
111841 #define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT)) & VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK)
111842 
111843 #define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK (0xFFF80000U)
111844 #define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT (19U)
111845 #define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT)) & VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK)
111846 /*! @} */
111847 
111848 /*! @name SWREG153 - inter me SATD lambda config 11 */
111849 /*! @{ */
111850 
111851 #define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK (0x7FFC0U)
111852 #define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT (6U)
111853 #define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT)) & VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK)
111854 
111855 #define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK (0xFFF80000U)
111856 #define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT (19U)
111857 #define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT)) & VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK)
111858 /*! @} */
111859 
111860 /*! @name SWREG154 - inter me SATD lambda config 12 */
111861 /*! @{ */
111862 
111863 #define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK (0x7FFC0U)
111864 #define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT (6U)
111865 #define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT)) & VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK)
111866 
111867 #define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK (0xFFF80000U)
111868 #define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT (19U)
111869 #define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT)) & VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK)
111870 /*! @} */
111871 
111872 /*! @name SWREG155 - inter me SATD lambda config 13 */
111873 /*! @{ */
111874 
111875 #define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK (0x7FFC0U)
111876 #define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT (6U)
111877 #define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT)) & VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK)
111878 
111879 #define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK (0xFFF80000U)
111880 #define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT (19U)
111881 #define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT)) & VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK)
111882 /*! @} */
111883 
111884 /*! @name SWREG156 - inter me SATD lambda config 14 */
111885 /*! @{ */
111886 
111887 #define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK (0x7FFC0U)
111888 #define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT (6U)
111889 #define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT)) & VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK)
111890 
111891 #define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK (0xFFF80000U)
111892 #define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT (19U)
111893 #define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT)) & VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK)
111894 /*! @} */
111895 
111896 /*! @name SWREG157 - inter me SATD lambda config 15 */
111897 /*! @{ */
111898 
111899 #define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK (0x7FFC0U)
111900 #define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT (6U)
111901 #define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT)) & VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK)
111902 
111903 #define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK (0xFFF80000U)
111904 #define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT (19U)
111905 #define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT)) & VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK)
111906 /*! @} */
111907 
111908 /*! @name SWREG158 - inter me SSE lambda config 16 */
111909 /*! @{ */
111910 
111911 #define VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK (0xFFFFF800U)
111912 #define VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT (11U)
111913 #define VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT)) & VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK)
111914 /*! @} */
111915 
111916 /*! @name SWREG159 - inter me SSE lambda config 17 */
111917 /*! @{ */
111918 
111919 #define VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK (0xFFFFF800U)
111920 #define VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT (11U)
111921 #define VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT)) & VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK)
111922 /*! @} */
111923 
111924 /*! @name SWREG160 - inter me SSE lambda config 18 */
111925 /*! @{ */
111926 
111927 #define VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK (0xFFFFF800U)
111928 #define VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT (11U)
111929 #define VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT)) & VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK)
111930 /*! @} */
111931 
111932 /*! @name SWREG161 - inter me SSE lambda config 19 */
111933 /*! @{ */
111934 
111935 #define VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK (0xFFFFF800U)
111936 #define VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT (11U)
111937 #define VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT)) & VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK)
111938 /*! @} */
111939 
111940 /*! @name SWREG162 - inter me SSE lambda config 20 */
111941 /*! @{ */
111942 
111943 #define VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK (0xFFFFF800U)
111944 #define VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT (11U)
111945 #define VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT)) & VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK)
111946 /*! @} */
111947 
111948 /*! @name SWREG163 - inter me SSE lambda config 21 */
111949 /*! @{ */
111950 
111951 #define VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK (0xFFFFF800U)
111952 #define VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT (11U)
111953 #define VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT)) & VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK)
111954 /*! @} */
111955 
111956 /*! @name SWREG164 - inter me SSE lambda config 22 */
111957 /*! @{ */
111958 
111959 #define VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK (0xFFFFF800U)
111960 #define VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT (11U)
111961 #define VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT)) & VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK)
111962 /*! @} */
111963 
111964 /*! @name SWREG165 - inter me SSE lambda config 23 */
111965 /*! @{ */
111966 
111967 #define VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK (0xFFFFF800U)
111968 #define VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT (11U)
111969 #define VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT)) & VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK)
111970 /*! @} */
111971 
111972 /*! @name SWREG166 - inter me SSE lambda config 24 */
111973 /*! @{ */
111974 
111975 #define VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK (0xFFFFF800U)
111976 #define VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT (11U)
111977 #define VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT)) & VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK)
111978 /*! @} */
111979 
111980 /*! @name SWREG167 - inter me SSE lambda config 25 */
111981 /*! @{ */
111982 
111983 #define VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK (0xFFFFF800U)
111984 #define VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT (11U)
111985 #define VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT)) & VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK)
111986 /*! @} */
111987 
111988 /*! @name SWREG168 - inter me SSE lambda config 26 */
111989 /*! @{ */
111990 
111991 #define VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK (0xFFFFF800U)
111992 #define VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT (11U)
111993 #define VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT)) & VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK)
111994 /*! @} */
111995 
111996 /*! @name SWREG169 - inter me SSE lambda config 27 */
111997 /*! @{ */
111998 
111999 #define VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK (0xFFFFF800U)
112000 #define VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT (11U)
112001 #define VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT)) & VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK)
112002 /*! @} */
112003 
112004 /*! @name SWREG172 - inter me SSE lambda config 30 */
112005 /*! @{ */
112006 
112007 #define VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK (0x1FU)
112008 #define VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT (0U)
112009 #define VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT)) & VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK)
112010 
112011 #define VPU_HEVC_SWREG172_SW_ENC_QP_MIN_MASK     (0x7E0U)
112012 #define VPU_HEVC_SWREG172_SW_ENC_QP_MIN_SHIFT    (5U)
112013 #define VPU_HEVC_SWREG172_SW_ENC_QP_MIN(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG172_SW_ENC_QP_MIN_SHIFT)) & VPU_HEVC_SWREG172_SW_ENC_QP_MIN_MASK)
112014 
112015 #define VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK (0xFFFFF800U)
112016 #define VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT (11U)
112017 #define VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT)) & VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK)
112018 /*! @} */
112019 
112020 /*! @name SWREG173 - inter me SSE lambda config 31 */
112021 /*! @{ */
112022 
112023 #define VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK (0xFU)
112024 #define VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT (0U)
112025 #define VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT)) & VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK)
112026 
112027 #define VPU_HEVC_SWREG173_SW_ENC_QP_MAX_MASK     (0x7E0U)
112028 #define VPU_HEVC_SWREG173_SW_ENC_QP_MAX_SHIFT    (5U)
112029 #define VPU_HEVC_SWREG173_SW_ENC_QP_MAX(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG173_SW_ENC_QP_MAX_SHIFT)) & VPU_HEVC_SWREG173_SW_ENC_QP_MAX_MASK)
112030 
112031 #define VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK (0xFFFFF800U)
112032 #define VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT (11U)
112033 #define VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT)) & VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK)
112034 /*! @} */
112035 
112036 /*! @name SWREG174 - intra SATD lambda config 8 */
112037 /*! @{ */
112038 
112039 #define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK (0x3FFF0U)
112040 #define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT (4U)
112041 #define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT)) & VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK)
112042 
112043 #define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK (0xFFFC0000U)
112044 #define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT (18U)
112045 #define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT)) & VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK)
112046 /*! @} */
112047 
112048 /*! @name SWREG175 - intra SATD lambda config 9 */
112049 /*! @{ */
112050 
112051 #define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK (0x3FFF0U)
112052 #define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT (4U)
112053 #define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT)) & VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK)
112054 
112055 #define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK (0xFFFC0000U)
112056 #define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT (18U)
112057 #define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT)) & VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK)
112058 /*! @} */
112059 
112060 /*! @name SWREG176 - intra SATD lambda config 10 */
112061 /*! @{ */
112062 
112063 #define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK (0x3FFF0U)
112064 #define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT (4U)
112065 #define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT)) & VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK)
112066 
112067 #define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK (0xFFFC0000U)
112068 #define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT (18U)
112069 #define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT)) & VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK)
112070 /*! @} */
112071 
112072 /*! @name SWREG177 - intra SATD lambda config 11 */
112073 /*! @{ */
112074 
112075 #define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK (0x3FFF0U)
112076 #define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT (4U)
112077 #define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT)) & VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK)
112078 
112079 #define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK (0xFFFC0000U)
112080 #define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT (18U)
112081 #define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT)) & VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK)
112082 /*! @} */
112083 
112084 /*! @name SWREG178 - intra SATD lambda config 12 */
112085 /*! @{ */
112086 
112087 #define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK (0x3FFF0U)
112088 #define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT (4U)
112089 #define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT)) & VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK)
112090 
112091 #define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK (0xFFFC0000U)
112092 #define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT (18U)
112093 #define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT)) & VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK)
112094 /*! @} */
112095 
112096 /*! @name SWREG179 - intra SATD lambda config 13 */
112097 /*! @{ */
112098 
112099 #define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK (0x3FFF0U)
112100 #define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT (4U)
112101 #define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT)) & VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK)
112102 
112103 #define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK (0xFFFC0000U)
112104 #define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT (18U)
112105 #define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT)) & VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK)
112106 /*! @} */
112107 
112108 /*! @name SWREG180 - intra SATD lambda config 14 */
112109 /*! @{ */
112110 
112111 #define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK (0x3FFF0U)
112112 #define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT (4U)
112113 #define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT)) & VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK)
112114 
112115 #define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK (0xFFFC0000U)
112116 #define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT (18U)
112117 #define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT)) & VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK)
112118 /*! @} */
112119 
112120 /*! @name SWREG181 - intra SATD lambda config 15 */
112121 /*! @{ */
112122 
112123 #define VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK (0xCU)
112124 #define VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT (2U)
112125 /*! SW_ENC_RC_BLOCK_SIZE
112126  *  0b00..64x64.
112127  *  0b01..32x32.
112128  *  0b10..16x16
112129  */
112130 #define VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT)) & VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK)
112131 
112132 #define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK (0x3FFF0U)
112133 #define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT (4U)
112134 #define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT)) & VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK)
112135 
112136 #define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK (0xFFFC0000U)
112137 #define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT (18U)
112138 #define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT)) & VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK)
112139 /*! @} */
112140 
112141 /*! @name SWREG182 - qp fractional part */
112142 /*! @{ */
112143 
112144 #define VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK (0xFFFFU)
112145 #define VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT (0U)
112146 #define VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT)) & VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK)
112147 
112148 #define VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_MASK (0xFFFF0000U)
112149 #define VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT (16U)
112150 #define VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT)) & VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_MASK)
112151 /*! @} */
112152 
112153 /*! @name SWREG183 - qp sum */
112154 /*! @{ */
112155 
112156 #define VPU_HEVC_SWREG183_SW_ENC_QP_SUM_MASK     (0xFFFFFFC0U)
112157 #define VPU_HEVC_SWREG183_SW_ENC_QP_SUM_SHIFT    (6U)
112158 #define VPU_HEVC_SWREG183_SW_ENC_QP_SUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG183_SW_ENC_QP_SUM_SHIFT)) & VPU_HEVC_SWREG183_SW_ENC_QP_SUM_MASK)
112159 /*! @} */
112160 
112161 /*! @name SWREG184 - qp num */
112162 /*! @{ */
112163 
112164 #define VPU_HEVC_SWREG184_SW_ENC_QP_NUM_MASK     (0xFFFFF000U)
112165 #define VPU_HEVC_SWREG184_SW_ENC_QP_NUM_SHIFT    (12U)
112166 #define VPU_HEVC_SWREG184_SW_ENC_QP_NUM(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG184_SW_ENC_QP_NUM_SHIFT)) & VPU_HEVC_SWREG184_SW_ENC_QP_NUM_MASK)
112167 /*! @} */
112168 
112169 /*! @name SWREG185 - picture complexity. Timeout cycles MSB. */
112170 /*! @{ */
112171 
112172 #define VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK (0x1FFU)
112173 #define VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT (0U)
112174 #define VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT)) & VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK)
112175 
112176 #define VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK (0xFFFFFE00U)
112177 #define VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT (9U)
112178 #define VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT)) & VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK)
112179 /*! @} */
112180 
112181 /*! @name SWREG186 - Base address for CU information table LSB */
112182 /*! @{ */
112183 
112184 #define VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_MASK (0xFFFFFFFFU)
112185 #define VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_SHIFT (0U)
112186 #define VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_MASK)
112187 /*! @} */
112188 
112189 /*! @name SWREG188 - Base address for CU information LSB */
112190 /*! @{ */
112191 
112192 #define VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_MASK (0xFFFFFFFFU)
112193 #define VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_SHIFT (0U)
112194 #define VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_SHIFT)) & VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_MASK)
112195 /*! @} */
112196 
112197 /*! @name SWREG190 - Long-term reference pictures config */
112198 /*! @{ */
112199 
112200 #define VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK (0xC0000000U)
112201 #define VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT (30U)
112202 #define VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT)) & VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK)
112203 /*! @} */
112204 
112205 /*! @name SWREG191 - Temporal scalable config */
112206 /*! @{ */
112207 
112208 #define VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK (0xFFFFU)
112209 #define VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT (0U)
112210 #define VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK)
112211 
112212 #define VPU_HEVC_SWREG191_SW_ENC_PPS_ID_MASK     (0x7E0000U)
112213 #define VPU_HEVC_SWREG191_SW_ENC_PPS_ID_SHIFT    (17U)
112214 #define VPU_HEVC_SWREG191_SW_ENC_PPS_ID(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_PPS_ID_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_PPS_ID_MASK)
112215 
112216 #define VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK (0x3800000U)
112217 #define VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT (23U)
112218 #define VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK)
112219 
112220 #define VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK (0xFC000000U)
112221 #define VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT (26U)
112222 #define VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK)
112223 /*! @} */
112224 
112225 /*! @name SWREG195 - register extension for ctu_size=16 */
112226 /*! @{ */
112227 
112228 #define VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK (0xCU)
112229 #define VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT (2U)
112230 #define VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK)
112231 
112232 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK (0x10U)
112233 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT (4U)
112234 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK)
112235 
112236 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK (0x20U)
112237 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT (5U)
112238 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK)
112239 
112240 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK (0x40U)
112241 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT (6U)
112242 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK)
112243 
112244 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK (0x80U)
112245 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT (7U)
112246 #define VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK)
112247 
112248 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK (0x100U)
112249 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT (8U)
112250 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK)
112251 
112252 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK (0x200U)
112253 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT (9U)
112254 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK)
112255 
112256 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK (0x400U)
112257 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT (10U)
112258 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK)
112259 
112260 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK (0x800U)
112261 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT (11U)
112262 #define VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK)
112263 
112264 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK (0x1000U)
112265 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT (12U)
112266 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK)
112267 
112268 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK (0x2000U)
112269 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT (13U)
112270 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK)
112271 
112272 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK (0x4000U)
112273 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT (14U)
112274 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK)
112275 
112276 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK (0x8000U)
112277 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT (15U)
112278 #define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK)
112279 
112280 #define VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK (0xF0000U)
112281 #define VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT (16U)
112282 #define VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK)
112283 
112284 #define VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_MASK (0xF00000U)
112285 #define VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_SHIFT (20U)
112286 #define VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_MASK)
112287 
112288 #define VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK (0x3000000U)
112289 #define VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT (24U)
112290 #define VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK)
112291 
112292 #define VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK (0xC000000U)
112293 #define VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT (26U)
112294 #define VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK)
112295 
112296 #define VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK (0xF0000000U)
112297 #define VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT (28U)
112298 #define VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK)
112299 /*! @} */
112300 
112301 /*! @name SWREG196 - Low Latency Controls */
112302 /*! @{ */
112303 
112304 #define VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_MASK (0x3FFU)
112305 #define VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT (0U)
112306 #define VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT)) & VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_MASK)
112307 
112308 #define VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_MASK (0xFFC00U)
112309 #define VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT (10U)
112310 #define VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT)) & VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_MASK)
112311 
112312 #define VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK (0x1FF00000U)
112313 #define VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT (20U)
112314 #define VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT)) & VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK)
112315 
112316 #define VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK (0x20000000U)
112317 #define VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT (29U)
112318 #define VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT)) & VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK)
112319 
112320 #define VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_MASK (0x40000000U)
112321 #define VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_SHIFT (30U)
112322 #define VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_SHIFT)) & VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_MASK)
112323 
112324 #define VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK (0x80000000U)
112325 #define VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT (31U)
112326 #define VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT)) & VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK)
112327 /*! @} */
112328 
112329 /*! @name SWREG197 - Delta POC extension */
112330 /*! @{ */
112331 
112332 #define VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK (0xFFCU)
112333 #define VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT (2U)
112334 #define VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT)) & VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK)
112335 
112336 #define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK (0x3FF000U)
112337 #define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT (12U)
112338 #define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT)) & VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK)
112339 
112340 #define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK (0xFFC00000U)
112341 #define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT (22U)
112342 #define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT)) & VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK)
112343 /*! @} */
112344 
112345 /*! @name SWREG198 - Long Term Reference Control */
112346 /*! @{ */
112347 
112348 #define VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK (0xFFC00000U)
112349 #define VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT (22U)
112350 #define VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT)) & VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK)
112351 /*! @} */
112352 
112353 /*! @name SWREG199 - Hash Code Control */
112354 /*! @{ */
112355 
112356 #define VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK (0x1U)
112357 #define VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT (0U)
112358 /*! SW_ENC_OSD_ALPHABLEND_ENABLE
112359  *  0b0..disable.
112360  *  0b1..enable.
112361  */
112362 #define VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT)) & VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK)
112363 
112364 #define VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_MASK (0x6U)
112365 #define VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_SHIFT (1U)
112366 #define VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_SHIFT)) & VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_MASK)
112367 
112368 #define VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_MASK  (0x18U)
112369 #define VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_SHIFT (3U)
112370 /*! SW_ENC_HASH_TYPE
112371  *  0b00..none.
112372  *  0b01..crc32.
112373  *  0b10..checksum32
112374  */
112375 #define VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_SHIFT)) & VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_MASK)
112376 /*! @} */
112377 
112378 /*! @name SWREG200 - Hash Code Value */
112379 /*! @{ */
112380 
112381 #define VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_MASK   (0xFFFFFFFFU)
112382 #define VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_SHIFT  (0U)
112383 #define VPU_HEVC_SWREG200_SW_ENC_HASH_VAL(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_SHIFT)) & VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_MASK)
112384 /*! @} */
112385 
112386 /*! @name SWREG201 - Background SKIP Control 0 */
112387 /*! @{ */
112388 
112389 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_MASK  (0xFFU)
112390 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_SHIFT (0U)
112391 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_MASK)
112392 
112393 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_MASK  (0xFF00U)
112394 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_SHIFT (8U)
112395 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_MASK)
112396 
112397 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_MASK  (0xFF0000U)
112398 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_SHIFT (16U)
112399 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_MASK)
112400 
112401 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_MASK  (0xFF000000U)
112402 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_SHIFT (24U)
112403 #define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_MASK)
112404 /*! @} */
112405 
112406 /*! @name SWREG202 - Background SKIP Control 1 */
112407 /*! @{ */
112408 
112409 #define VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_MASK (0xFFFFU)
112410 #define VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_SHIFT (0U)
112411 #define VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_SHIFT)) & VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_MASK)
112412 
112413 #define VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_MASK (0xFFFF0000U)
112414 #define VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_SHIFT (16U)
112415 #define VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_SHIFT)) & VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_MASK)
112416 /*! @} */
112417 
112418 /*! @name SWREG203 - Background SKIP Control 2 */
112419 /*! @{ */
112420 
112421 #define VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_MASK (0xFFFFU)
112422 #define VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_SHIFT (0U)
112423 #define VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_SHIFT)) & VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_MASK)
112424 
112425 #define VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_MASK (0xFFFF0000U)
112426 #define VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_SHIFT (16U)
112427 #define VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_SHIFT)) & VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_MASK)
112428 /*! @} */
112429 
112430 /*! @name SWREG204 - Background SKIP Control 3 */
112431 /*! @{ */
112432 
112433 #define VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_MASK (0xFFFFU)
112434 #define VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_SHIFT (0U)
112435 #define VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_SHIFT)) & VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_MASK)
112436 
112437 #define VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_MASK (0xFFFF0000U)
112438 #define VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_SHIFT (16U)
112439 #define VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_SHIFT)) & VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_MASK)
112440 /*! @} */
112441 
112442 /*! @name SWREG205 - Background SKIP Control 4 */
112443 /*! @{ */
112444 
112445 #define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_MASK (0xFFFFU)
112446 #define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_SHIFT (0U)
112447 #define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_SHIFT)) & VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_MASK)
112448 
112449 #define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_MASK (0xFFFF0000U)
112450 #define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_SHIFT (16U)
112451 #define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_SHIFT)) & VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_MASK)
112452 /*! @} */
112453 
112454 /*! @name SWREG206 - Background SKIP Control 5 */
112455 /*! @{ */
112456 
112457 #define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_MASK (0xFFFFU)
112458 #define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_SHIFT (0U)
112459 #define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_SHIFT)) & VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_MASK)
112460 
112461 #define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_MASK (0xFFFF0000U)
112462 #define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_SHIFT (16U)
112463 #define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_SHIFT)) & VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_MASK)
112464 /*! @} */
112465 
112466 /*! @name SWREG207 - Background SKIP Control 6 */
112467 /*! @{ */
112468 
112469 #define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_MASK (0xFFFFU)
112470 #define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_SHIFT (0U)
112471 #define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_SHIFT)) & VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_MASK)
112472 
112473 #define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_MASK (0xFFFF0000U)
112474 #define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_SHIFT (16U)
112475 #define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_SHIFT)) & VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_MASK)
112476 /*! @} */
112477 
112478 /*! @name SWREG208 - Background SKIP Control 7 */
112479 /*! @{ */
112480 
112481 #define VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK (0x8U)
112482 #define VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT (3U)
112483 #define VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK)
112484 
112485 #define VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_MASK (0x1FF0U)
112486 #define VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT (4U)
112487 #define VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_MASK)
112488 
112489 #define VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_MASK (0x2000U)
112490 #define VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_SHIFT (13U)
112491 #define VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_MASK)
112492 
112493 #define VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK (0xFC000U)
112494 #define VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT (14U)
112495 #define VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK)
112496 
112497 #define VPU_HEVC_SWREG208_SW_ENC_MDQPC_MASK      (0x3F00000U)
112498 #define VPU_HEVC_SWREG208_SW_ENC_MDQPC_SHIFT     (20U)
112499 #define VPU_HEVC_SWREG208_SW_ENC_MDQPC(x)        (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPC_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPC_MASK)
112500 
112501 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK      (0xFC000000U)
112502 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT     (26U)
112503 #define VPU_HEVC_SWREG208_SW_ENC_MDQPY(x)        (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
112504 /*! @} */
112505 
112506 /*! @name SWREG209 - IPCM Control 0 */
112507 /*! @{ */
112508 
112509 #define VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK (0x8U)
112510 #define VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT (3U)
112511 #define VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK)
112512 
112513 #define VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK (0x10U)
112514 #define VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT (4U)
112515 #define VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK)
112516 
112517 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK (0x3FE0U)
112518 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT (5U)
112519 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK)
112520 
112521 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_MASK  (0x7FC000U)
112522 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_SHIFT (14U)
112523 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_MASK)
112524 
112525 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_MASK (0xFF800000U)
112526 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT (23U)
112527 #define VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_MASK)
112528 /*! @} */
112529 
112530 /*! @name SWREG210 - IPCM Control 1 */
112531 /*! @{ */
112532 
112533 #define VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_MASK (0xFF8U)
112534 #define VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT (3U)
112535 #define VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT)) & VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_MASK)
112536 /*! @} */
112537 
112538 /*! @name SWREG211 - IPCM Control 2 */
112539 /*! @{ */
112540 
112541 #define VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_MASK (0xFF8U)
112542 #define VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT (3U)
112543 #define VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT)) & VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_MASK)
112544 /*! @} */
112545 
112546 /*! @name SWREG212 - IPCM Control 3 */
112547 /*! @{ */
112548 
112549 #define VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_MASK  (0xFF8U)
112550 #define VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_SHIFT (3U)
112551 #define VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_SHIFT)) & VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_MASK)
112552 /*! @} */
112553 
112554 /*! @name SWREG213 - IPCM Control 4 */
112555 /*! @{ */
112556 
112557 #define VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK (0x3FE0U)
112558 #define VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT (5U)
112559 #define VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT)) & VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK)
112560 /*! @} */
112561 
112562 /*! @name SWREG214 - HW synthesis config register 2, read-only */
112563 /*! @{ */
112564 
112565 #define VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_MASK (0x1C000000U)
112566 #define VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT (26U)
112567 /*! SW_ENC_HWROIMAPVERSION
112568  *  0b000..4 bit per pixel.
112569  *  0b001..8 bit per pixel
112570  */
112571 #define VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_MASK)
112572 
112573 #define VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_MASK (0x20000000U)
112574 #define VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_SHIFT (29U)
112575 /*! SW_ENC_HWINTRATU32SUPPORT
112576  *  0b0..not supported.
112577  *  0b1..supported
112578  */
112579 #define VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_MASK)
112580 
112581 #define VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK (0x40000000U)
112582 #define VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT (30U)
112583 /*! SW_ENC_HWABSQPSUPPORT
112584  *  0b0..not supported.
112585  *  0b1..supported
112586  */
112587 #define VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK)
112588 
112589 #define VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK (0x80000000U)
112590 #define VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT (31U)
112591 /*! SW_ENC_HWLJPEGSUPPORT
112592  *  0b0..not supported.
112593  *  0b1..supported
112594  */
112595 #define VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK)
112596 /*! @} */
112597 
112598 /*! @name SWREG215 - AXI Information 0 */
112599 /*! @{ */
112600 
112601 #define VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_MASK (0xFFFFFFFFU)
112602 #define VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_SHIFT (0U)
112603 #define VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_SHIFT)) & VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_MASK)
112604 /*! @} */
112605 
112606 /*! @name SWREG216 - AXI Information 1 */
112607 /*! @{ */
112608 
112609 #define VPU_HEVC_SWREG216_SW_ENC_TOTALR_MASK     (0xFFFFFFFFU)
112610 #define VPU_HEVC_SWREG216_SW_ENC_TOTALR_SHIFT    (0U)
112611 #define VPU_HEVC_SWREG216_SW_ENC_TOTALR(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG216_SW_ENC_TOTALR_SHIFT)) & VPU_HEVC_SWREG216_SW_ENC_TOTALR_MASK)
112612 /*! @} */
112613 
112614 /*! @name SWREG217 - AXI Information 2 */
112615 /*! @{ */
112616 
112617 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK    (0xFFFFFFFFU)
112618 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT   (0U)
112619 #define VPU_HEVC_SWREG217_SW_ENC_TOTALAR(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
112620 /*! @} */
112621 
112622 /*! @name SWREG218 - AXI Information 3 */
112623 /*! @{ */
112624 
112625 #define VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_MASK (0xFFFFFFFFU)
112626 #define VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_SHIFT (0U)
112627 #define VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_SHIFT)) & VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_MASK)
112628 /*! @} */
112629 
112630 /*! @name SWREG219 - AXI Information 4 */
112631 /*! @{ */
112632 
112633 #define VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_MASK (0xFFFFFFFFU)
112634 #define VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_SHIFT (0U)
112635 #define VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_SHIFT)) & VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_MASK)
112636 /*! @} */
112637 
112638 /*! @name SWREG220 - AXI Information 5 */
112639 /*! @{ */
112640 
112641 #define VPU_HEVC_SWREG220_SW_ENC_TOTALW_MASK     (0xFFFFFFFFU)
112642 #define VPU_HEVC_SWREG220_SW_ENC_TOTALW_SHIFT    (0U)
112643 #define VPU_HEVC_SWREG220_SW_ENC_TOTALW(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG220_SW_ENC_TOTALW_SHIFT)) & VPU_HEVC_SWREG220_SW_ENC_TOTALW_MASK)
112644 /*! @} */
112645 
112646 /*! @name SWREG221 - AXI Information 6 */
112647 /*! @{ */
112648 
112649 #define VPU_HEVC_SWREG221_SW_ENC_TOTALAW_MASK    (0xFFFFFFFFU)
112650 #define VPU_HEVC_SWREG221_SW_ENC_TOTALAW_SHIFT   (0U)
112651 #define VPU_HEVC_SWREG221_SW_ENC_TOTALAW(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG221_SW_ENC_TOTALAW_SHIFT)) & VPU_HEVC_SWREG221_SW_ENC_TOTALAW_MASK)
112652 /*! @} */
112653 
112654 /*! @name SWREG222 - AXI Information 7 */
112655 /*! @{ */
112656 
112657 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU)
112658 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT (0U)
112659 #define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
112660 /*! @} */
112661 
112662 /*! @name SWREG223 - AXI Information 8 */
112663 /*! @{ */
112664 
112665 #define VPU_HEVC_SWREG223_SW_ENC_TOTALB_MASK     (0xFFFFFFFFU)
112666 #define VPU_HEVC_SWREG223_SW_ENC_TOTALB_SHIFT    (0U)
112667 #define VPU_HEVC_SWREG223_SW_ENC_TOTALB(x)       (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG223_SW_ENC_TOTALB_SHIFT)) & VPU_HEVC_SWREG223_SW_ENC_TOTALB_MASK)
112668 /*! @} */
112669 
112670 /*! @name SWREG224 - control register 4 */
112671 /*! @{ */
112672 
112673 #define VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK (0x3FFU)
112674 #define VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT (0U)
112675 #define VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK)
112676 
112677 #define VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK (0xFFC00U)
112678 #define VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT (10U)
112679 #define VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK)
112680 
112681 #define VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_MASK (0x100000U)
112682 #define VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT (20U)
112683 /*! SW_ENC_SKIPFRAME_EN
112684  *  0b0..no.
112685  *  0b1..yes
112686  */
112687 #define VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_MASK)
112688 
112689 #define VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_MASK    (0x200000U)
112690 #define VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_SHIFT   (21U)
112691 /*! SW_ENC_SSIM_EN
112692  *  0b0..Disable.
112693  *  0b1..Enable
112694  */
112695 #define VPU_HEVC_SWREG224_SW_ENC_SSIM_EN(x)      (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_MASK)
112696 
112697 #define VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK (0x80000000U)
112698 #define VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT (31U)
112699 /*! SW_ENC_CHROMA_CONST_EN
112700  *  0b0..no.
112701  *  0b1..yes.
112702  */
112703 #define VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK)
112704 /*! @} */
112705 
112706 /*! @name SWREG225 - Tile Control */
112707 /*! @{ */
112708 
112709 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK (0x1C0U)
112710 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT (6U)
112711 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK)
112712 
112713 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK (0xE00U)
112714 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT (9U)
112715 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK)
112716 
112717 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK (0x1000U)
112718 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT (12U)
112719 /*! SW_ENC_ROIMAP_CUCTRL_ENABLE
112720  *  0b0..Disable.
112721  *  0b1..Enable
112722  */
112723 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK)
112724 
112725 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK (0x2000U)
112726 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT (13U)
112727 /*! SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE
112728  *  0b0..Disable.
112729  *  0b1..Enable
112730  */
112731 #define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK)
112732 
112733 #define VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_MASK (0x4000U)
112734 #define VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_SHIFT (14U)
112735 /*! SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG
112736  *  0b0..disabled.
112737  *  0b1..enabled.
112738  */
112739 #define VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_MASK)
112740 
112741 #define VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_MASK (0x8000U)
112742 #define VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_SHIFT (15U)
112743 /*! SW_ENC_TILES_ENABLED_FLAG
112744  *  0b0..disabled.
112745  *  0b1..enabled.
112746  */
112747 #define VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_MASK)
112748 
112749 #define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_MASK (0xFF0000U)
112750 #define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_SHIFT (16U)
112751 #define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_MASK)
112752 
112753 #define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_MASK (0xFF000000U)
112754 #define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_SHIFT (24U)
112755 #define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_MASK)
112756 /*! @} */
112757 
112758 /*! @name SWREG226 - HW synthesis config register 3, read-only */
112759 /*! @{ */
112760 
112761 #define VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_MASK (0x1U)
112762 #define VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_SHIFT (0U)
112763 /*! SW_ENC_HWDYNAMICMAXTUSIZE
112764  *  0b0..not supported.
112765  *  0b1..supported
112766  */
112767 #define VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_MASK)
112768 
112769 #define VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_MASK (0x2U)
112770 #define VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT (1U)
112771 /*! SW_ENC_HWIFRAMEONLY
112772  *  0b0..support I/P/B frame.
112773  *  0b1..only support I frame
112774  */
112775 #define VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_MASK)
112776 
112777 #define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK (0x4U)
112778 #define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT (2U)
112779 /*! SW_ENC_HWSTREAMSEGMENTSUPPORT
112780  *  0b0..not supported.
112781  *  0b1..supported
112782  */
112783 #define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK)
112784 
112785 #define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK (0x8U)
112786 #define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT (3U)
112787 /*! SW_ENC_HWSTREAMBUFCHAIN
112788  *  0b0..not supported.
112789  *  0b1..supported
112790  */
112791 #define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK)
112792 
112793 #define VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK (0x10U)
112794 #define VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT (4U)
112795 /*! SW_ENC_HWINLOOPDSRATIO
112796  *  0b0..1:1
112797  *  0b1..1:2
112798  */
112799 #define VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK)
112800 
112801 #define VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK (0x20U)
112802 #define VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT (5U)
112803 /*! SW_ENC_HWMULTIPASSSUPPORT
112804  *  0b0..not supported.
112805  *  0b1..supported
112806  */
112807 #define VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK)
112808 
112809 #define VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK (0x40U)
112810 #define VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT (6U)
112811 /*! SW_ENC_HWRDOQSUPPORT
112812  *  0b0..not supported.
112813  *  0b1..supported
112814  */
112815 #define VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK)
112816 
112817 #define VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK (0x180U)
112818 #define VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT (7U)
112819 /*! SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE
112820  *  0b00..64.
112821  *  0b01..128.
112822  *  0b10..192.
112823  *  0b11..256
112824  */
112825 #define VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK)
112826 
112827 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U)
112828 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT (9U)
112829 #define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
112830 
112831 #define VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_MASK (0x400U)
112832 #define VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT (10U)
112833 /*! SW_ENC_HWGMVSUPPORT
112834  *  0b0..not supported.
112835  *  0b1..supported
112836  */
112837 #define VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_MASK)
112838 
112839 #define VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK (0x800U)
112840 #define VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT (11U)
112841 /*! SW_ENC_HWJPEG422SUPPORT
112842  *  0b0..not supported.
112843  *  0b1..supported
112844  */
112845 #define VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK)
112846 
112847 #define VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_MASK (0x7000U)
112848 #define VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT (12U)
112849 #define VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_MASK)
112850 
112851 #define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK (0x1F8000U)
112852 #define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT (15U)
112853 #define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK)
112854 
112855 #define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK (0x7E00000U)
112856 #define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT (21U)
112857 #define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK)
112858 
112859 #define VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_MASK (0x38000000U)
112860 #define VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT (27U)
112861 #define VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_MASK)
112862 
112863 #define VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK (0x40000000U)
112864 #define VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT (30U)
112865 /*! SW_ENC_HWP010REFSUPPORT
112866  *  0b1..P010 tile raster format.
112867  *  0b0..normal format
112868  */
112869 #define VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK)
112870 
112871 #define VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK (0x80000000U)
112872 #define VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT (31U)
112873 /*! SW_ENC_HWSSIMSUPPORT
112874  *  0b0..not supported.
112875  *  0b1..supported
112876  */
112877 #define VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK)
112878 /*! @} */
112879 
112880 /*! @name SWREG235 - RPS encoding control 0 */
112881 /*! @{ */
112882 
112883 #define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK (0x1U)
112884 #define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT (0U)
112885 #define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK)
112886 
112887 #define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK (0x2U)
112888 #define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT (1U)
112889 #define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK)
112890 
112891 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK (0xFFCU)
112892 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT (2U)
112893 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK)
112894 
112895 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK (0x3FF000U)
112896 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT (12U)
112897 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK)
112898 
112899 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK (0xFFC00000U)
112900 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT (22U)
112901 #define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK)
112902 /*! @} */
112903 
112904 /*! @name SWREG236 - RPS encoding control 1 */
112905 /*! @{ */
112906 
112907 #define VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_MASK (0x1000U)
112908 #define VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT (12U)
112909 /*! SW_ENC_P010_REF_ENABLE
112910  *  0b0..not supported.
112911  *  0b1..supported.
112912  */
112913 #define VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_MASK)
112914 
112915 #define VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK (0x2000U)
112916 #define VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT (13U)
112917 #define VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK)
112918 
112919 #define VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK (0x1C000U)
112920 #define VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT (14U)
112921 #define VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK)
112922 
112923 #define VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK (0xE0000U)
112924 #define VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT (17U)
112925 #define VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK)
112926 
112927 #define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK (0x100000U)
112928 #define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT (20U)
112929 #define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK)
112930 
112931 #define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK (0x200000U)
112932 #define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT (21U)
112933 #define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK)
112934 
112935 #define VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK (0xFFC00000U)
112936 #define VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT (22U)
112937 #define VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK)
112938 /*! @} */
112939 
112940 /*! @name SWREG237 - Stride Control */
112941 /*! @{ */
112942 
112943 #define VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_MASK (0x800U)
112944 #define VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_SHIFT (11U)
112945 #define VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_SHIFT)) & VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_MASK)
112946 
112947 #define VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_MASK (0xFFFFF000U)
112948 #define VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT (12U)
112949 #define VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT)) & VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_MASK)
112950 /*! @} */
112951 
112952 /*! @name SWREG238 - Dummy Read */
112953 /*! @{ */
112954 
112955 #define VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_MASK (0xFFFFFFFFU)
112956 #define VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT (0U)
112957 #define VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT)) & VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_MASK)
112958 /*! @} */
112959 
112960 /*! @name SWREG239 - Base Address LSB of CTB MADs of current frame. */
112961 /*! @{ */
112962 
112963 #define VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
112964 #define VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT (0U)
112965 #define VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT)) & VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK)
112966 /*! @} */
112967 
112968 /*! @name SWREG241 - Base Address LSB of CTB MADs of previous frame. */
112969 /*! @{ */
112970 
112971 #define VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
112972 #define VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT (0U)
112973 #define VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT)) & VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK)
112974 /*! @} */
112975 
112976 /*! @name SWREG243 - CTB RC Control 0 */
112977 /*! @{ */
112978 
112979 #define VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK (0xFFFFF800U)
112980 #define VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT (11U)
112981 #define VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT)) & VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK)
112982 /*! @} */
112983 
112984 /*! @name SWREG244 - CTB RC Control 1 */
112985 /*! @{ */
112986 
112987 #define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK (0x4U)
112988 #define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT (2U)
112989 /*! SW_ENC_ROI3_QP_TYPE
112990  *  0b0..delta
112991  *  0b1..Absolute value
112992  */
112993 #define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK)
112994 
112995 #define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK (0x3F8U)
112996 #define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT (3U)
112997 #define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK)
112998 
112999 #define VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK (0xFFFFFC00U)
113000 #define VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT (10U)
113001 #define VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT)) & VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK)
113002 /*! @} */
113003 
113004 /*! @name SWREG245 - CTB RC Control 2 */
113005 /*! @{ */
113006 
113007 #define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK (0x3FFFCU)
113008 #define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT (2U)
113009 #define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT)) & VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK)
113010 
113011 #define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK (0xFFFC0000U)
113012 #define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT (18U)
113013 #define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT)) & VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK)
113014 /*! @} */
113015 
113016 /*! @name SWREG246 - CTB RC Control 3 */
113017 /*! @{ */
113018 
113019 #define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_MASK (0x38U)
113020 #define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT (3U)
113021 #define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT)) & VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_MASK)
113022 
113023 #define VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK (0x3FC0U)
113024 #define VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT (6U)
113025 #define VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT)) & VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK)
113026 
113027 #define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK (0xFFFFC000U)
113028 #define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT (14U)
113029 #define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT)) & VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK)
113030 /*! @} */
113031 
113032 /*! @name SWREG247 - CTB RC Control 4 */
113033 /*! @{ */
113034 
113035 #define VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK (0x2U)
113036 #define VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT (1U)
113037 /*! SW_ENC_CTB_RC_PREV_MAD_VALID
113038  *  0b0..no
113039  *  0b1..yes.
113040  */
113041 #define VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT)) & VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK)
113042 
113043 #define VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK (0xFFFFFFC0U)
113044 #define VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT (6U)
113045 #define VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT)) & VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK)
113046 /*! @} */
113047 
113048 /*! @name SWREG248 - CTB RC Control 5 */
113049 /*! @{ */
113050 
113051 #define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK (0x1U)
113052 #define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT (0U)
113053 /*! SW_ENC_ROI4_QP_TYPE
113054  *  0b0..delta
113055  *  0b1..Absolute value
113056  */
113057 #define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK)
113058 
113059 #define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK (0xFEU)
113060 #define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT (1U)
113061 #define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK)
113062 
113063 #define VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK (0xFFFFFF00U)
113064 #define VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT (8U)
113065 #define VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT)) & VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK)
113066 /*! @} */
113067 
113068 /*! @name SWREG249 - register extension for 8K width */
113069 /*! @{ */
113070 
113071 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK (0x8U)
113072 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT (3U)
113073 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK)
113074 
113075 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK (0x10U)
113076 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT (4U)
113077 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK)
113078 
113079 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK (0x20U)
113080 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT (5U)
113081 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK)
113082 
113083 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK (0x40U)
113084 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT (6U)
113085 #define VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK)
113086 
113087 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK (0x80U)
113088 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT (7U)
113089 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK)
113090 
113091 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK (0x100U)
113092 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT (8U)
113093 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK)
113094 
113095 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK (0x200U)
113096 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT (9U)
113097 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK)
113098 
113099 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK (0x400U)
113100 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT (10U)
113101 #define VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK)
113102 
113103 #define VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK (0x800U)
113104 #define VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT (11U)
113105 #define VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK)
113106 
113107 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK (0x1000U)
113108 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT (12U)
113109 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK)
113110 
113111 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK (0x2000U)
113112 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT (13U)
113113 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK)
113114 
113115 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK (0x4000U)
113116 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT (14U)
113117 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK)
113118 
113119 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK (0x8000U)
113120 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT (15U)
113121 #define VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK)
113122 
113123 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK (0x10000U)
113124 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT (16U)
113125 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK)
113126 
113127 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK (0x20000U)
113128 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT (17U)
113129 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK)
113130 
113131 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK (0x40000U)
113132 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT (18U)
113133 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK)
113134 
113135 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK (0x80000U)
113136 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT (19U)
113137 #define VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK)
113138 
113139 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK (0x100000U)
113140 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT (20U)
113141 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK)
113142 
113143 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK (0x200000U)
113144 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT (21U)
113145 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK)
113146 
113147 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK (0x400000U)
113148 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT (22U)
113149 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK)
113150 
113151 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK (0x800000U)
113152 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT (23U)
113153 #define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK)
113154 
113155 #define VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK (0x3000000U)
113156 #define VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT (24U)
113157 #define VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK)
113158 
113159 #define VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_MASK (0xC000000U)
113160 #define VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT (26U)
113161 #define VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_MASK)
113162 
113163 #define VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK (0x10000000U)
113164 #define VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT (28U)
113165 #define VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK)
113166 
113167 #define VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK (0x20000000U)
113168 #define VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT (29U)
113169 #define VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK)
113170 
113171 #define VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK (0xC0000000U)
113172 #define VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT (30U)
113173 #define VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK)
113174 /*! @} */
113175 
113176 /*! @name SWREG250 - Global MV Control 0 */
113177 /*! @{ */
113178 
113179 #define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK (0x3FFF0U)
113180 #define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT (4U)
113181 #define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT)) & VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK)
113182 
113183 #define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK (0xFFFC0000U)
113184 #define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT (18U)
113185 #define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT)) & VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK)
113186 /*! @} */
113187 
113188 /*! @name SWREG251 - Global MV Control 1 */
113189 /*! @{ */
113190 
113191 #define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK (0x3FFF0U)
113192 #define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT (4U)
113193 #define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT)) & VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK)
113194 
113195 #define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK (0xFFFC0000U)
113196 #define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT (18U)
113197 #define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT)) & VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK)
113198 /*! @} */
113199 
113200 /*! @name SWREG252 - ROI3 Area */
113201 /*! @{ */
113202 
113203 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_MASK (0xFFCU)
113204 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT (2U)
113205 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT)) & VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_MASK)
113206 
113207 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_MASK   (0x3FF000U)
113208 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_SHIFT  (12U)
113209 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_SHIFT)) & VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_MASK)
113210 
113211 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_MASK  (0xFFC00000U)
113212 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_SHIFT (22U)
113213 #define VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_SHIFT)) & VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_MASK)
113214 /*! @} */
113215 
113216 /*! @name SWREG253 - ROI3&4 Area */
113217 /*! @{ */
113218 
113219 #define VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_MASK   (0xFFCU)
113220 #define VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_SHIFT  (2U)
113221 #define VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_SHIFT)) & VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_MASK)
113222 
113223 #define VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_MASK  (0x3FF000U)
113224 #define VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_SHIFT (12U)
113225 #define VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_SHIFT)) & VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_MASK)
113226 
113227 #define VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_MASK (0xFFC00000U)
113228 #define VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT (22U)
113229 #define VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT)) & VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_MASK)
113230 /*! @} */
113231 
113232 /*! @name SWREG254 - ROI4&5 Area */
113233 /*! @{ */
113234 
113235 #define VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_MASK  (0xFFCU)
113236 #define VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_SHIFT (2U)
113237 #define VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_SHIFT)) & VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_MASK)
113238 
113239 #define VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_MASK (0x3FF000U)
113240 #define VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT (12U)
113241 #define VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT)) & VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_MASK)
113242 
113243 #define VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_MASK (0xFFC00000U)
113244 #define VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT (22U)
113245 #define VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT)) & VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_MASK)
113246 /*! @} */
113247 
113248 /*! @name SWREG255 - ROI5 Area */
113249 /*! @{ */
113250 
113251 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_MASK (0xFFCU)
113252 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT (2U)
113253 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT)) & VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_MASK)
113254 
113255 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_MASK (0x3FF000U)
113256 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT (12U)
113257 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT)) & VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_MASK)
113258 
113259 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_MASK   (0xFFC00000U)
113260 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_SHIFT  (22U)
113261 #define VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_SHIFT)) & VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_MASK)
113262 /*! @} */
113263 
113264 /*! @name SWREG256 - ROI6 Area */
113265 /*! @{ */
113266 
113267 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_MASK (0xFFCU)
113268 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT (2U)
113269 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT)) & VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_MASK)
113270 
113271 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_MASK   (0x3FF000U)
113272 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_SHIFT  (12U)
113273 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_SHIFT)) & VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_MASK)
113274 
113275 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_MASK  (0xFFC00000U)
113276 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_SHIFT (22U)
113277 #define VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_SHIFT)) & VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_MASK)
113278 /*! @} */
113279 
113280 /*! @name SWREG257 - ROI6&7 Area */
113281 /*! @{ */
113282 
113283 #define VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_MASK   (0xFFCU)
113284 #define VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_SHIFT  (2U)
113285 #define VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_SHIFT)) & VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_MASK)
113286 
113287 #define VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_MASK  (0x3FF000U)
113288 #define VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_SHIFT (12U)
113289 #define VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_SHIFT)) & VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_MASK)
113290 
113291 #define VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_MASK (0xFFC00000U)
113292 #define VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT (22U)
113293 #define VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT)) & VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_MASK)
113294 /*! @} */
113295 
113296 /*! @name SWREG258 - ROI7&8 Area */
113297 /*! @{ */
113298 
113299 #define VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_MASK  (0xFFCU)
113300 #define VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_SHIFT (2U)
113301 #define VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_SHIFT)) & VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_MASK)
113302 
113303 #define VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_MASK (0x3FF000U)
113304 #define VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT (12U)
113305 #define VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT)) & VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_MASK)
113306 
113307 #define VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_MASK (0xFFC00000U)
113308 #define VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT (22U)
113309 #define VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT)) & VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_MASK)
113310 /*! @} */
113311 
113312 /*! @name SWREG259 - ROI8 Area */
113313 /*! @{ */
113314 
113315 #define VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK (0x2U)
113316 #define VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT (1U)
113317 /*! SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE
113318  *  0b0..max tu size 32.
113319  *  0b1..max tu size 16.
113320  */
113321 #define VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK)
113322 
113323 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_MASK (0xFFCU)
113324 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT (2U)
113325 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_MASK)
113326 
113327 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_MASK (0x3FF000U)
113328 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT (12U)
113329 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT(x)   (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_MASK)
113330 
113331 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_MASK   (0xFFC00000U)
113332 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_SHIFT  (22U)
113333 #define VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP(x)     (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_MASK)
113334 /*! @} */
113335 
113336 /*! @name SWREG260 - ROI qp */
113337 /*! @{ */
113338 
113339 #define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK (0x1U)
113340 #define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT (0U)
113341 /*! SW_ENC_ROI5_QP_TYPE
113342  *  0b0..delta
113343  *  0b1..Absolute value
113344  */
113345 #define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK)
113346 
113347 #define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK (0xFEU)
113348 #define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT (1U)
113349 #define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK)
113350 
113351 #define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK (0x100U)
113352 #define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT (8U)
113353 /*! SW_ENC_ROI6_QP_TYPE
113354  *  0b0..delta
113355  *  0b1..Absolute value
113356  */
113357 #define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK)
113358 
113359 #define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK (0xFE00U)
113360 #define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT (9U)
113361 #define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK)
113362 
113363 #define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK (0x10000U)
113364 #define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT (16U)
113365 /*! SW_ENC_ROI7_QP_TYPE
113366  *  0b0..delta
113367  *  0b1..Absolute value
113368  */
113369 #define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK)
113370 
113371 #define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK (0xFE0000U)
113372 #define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT (17U)
113373 #define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK)
113374 
113375 #define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK (0x1000000U)
113376 #define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT (24U)
113377 /*! SW_ENC_ROI8_QP_TYPE
113378  *  0b0..delta
113379  *  0b1..Absolute value
113380  */
113381 #define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK)
113382 
113383 #define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK (0xFE000000U)
113384 #define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT (25U)
113385 #define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK)
113386 /*! @} */
113387 
113388 /*! @name SWREG261 - Stride Control */
113389 /*! @{ */
113390 
113391 #define VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK (0x1U)
113392 #define VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT (0U)
113393 #define VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK)
113394 
113395 #define VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK (0x2U)
113396 #define VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT (1U)
113397 #define VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK)
113398 
113399 #define VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_MASK (0x4U)
113400 #define VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT (2U)
113401 #define VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_MASK)
113402 
113403 #define VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_MASK (0x8U)
113404 #define VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT (3U)
113405 #define VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_MASK)
113406 
113407 #define VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK (0xFF0U)
113408 #define VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT (4U)
113409 #define VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK)
113410 
113411 #define VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK (0x1000U)
113412 #define VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT (12U)
113413 #define VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK)
113414 
113415 #define VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK (0x3E000U)
113416 #define VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT (13U)
113417 #define VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK)
113418 /*! @} */
113419 
113420 /*! @name SWREG265 - Multicore sync ctrl */
113421 /*! @{ */
113422 
113423 #define VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK (0xFFFFU)
113424 #define VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT (0U)
113425 #define VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT)) & VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK)
113426 
113427 #define VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK (0xFFFF0000U)
113428 #define VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT (16U)
113429 #define VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK)
113430 /*! @} */
113431 
113432 /*! @name SWREG266 - Multicore sync address L0 LSB */
113433 /*! @{ */
113434 
113435 #define VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK (0xFFFFFFFFU)
113436 #define VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT (0U)
113437 #define VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT)) & VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK)
113438 /*! @} */
113439 
113440 /*! @name SWREG267 - Multicore sync address L0 MSB */
113441 /*! @{ */
113442 
113443 #define VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK (0xFFFFFFFFU)
113444 #define VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT (0U)
113445 #define VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK)
113446 /*! @} */
113447 
113448 /*! @name SWREG268 - Multicore sync address L1 LSB */
113449 /*! @{ */
113450 
113451 #define VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK (0xFFFFFFFFU)
113452 #define VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT (0U)
113453 #define VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT)) & VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK)
113454 /*! @} */
113455 
113456 /*! @name SWREG269 - Multicore sync address L1 MSB */
113457 /*! @{ */
113458 
113459 #define VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK (0xFFFFFFFFU)
113460 #define VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT (0U)
113461 #define VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK)
113462 /*! @} */
113463 
113464 /*! @name SWREG270 - Multicore sync address recon LSB */
113465 /*! @{ */
113466 
113467 #define VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK (0xFFFFFFFFU)
113468 #define VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT (0U)
113469 #define VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT)) & VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK)
113470 /*! @} */
113471 
113472 /*! @name SWREG271 - Multicore sync address recon MSB */
113473 /*! @{ */
113474 
113475 #define VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK (0xFFFFFFFFU)
113476 #define VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT (0U)
113477 #define VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK)
113478 /*! @} */
113479 
113480 /*! @name SWREG272 - Programmable AXI urgent sideband signals */
113481 /*! @{ */
113482 
113483 #define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK (0xFFU)
113484 #define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT (0U)
113485 #define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK)
113486 
113487 #define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK (0xFF00U)
113488 #define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT (8U)
113489 #define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK)
113490 
113491 #define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK (0xFF0000U)
113492 #define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT (16U)
113493 #define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK)
113494 
113495 #define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK (0xFF000000U)
113496 #define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT (24U)
113497 #define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK)
113498 /*! @} */
113499 
113500 /*! @name SWREG273 - roimap cu ctrl index address LSB */
113501 /*! @{ */
113502 
113503 #define VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK (0xFFFFFFFFU)
113504 #define VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT (0U)
113505 #define VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT)) & VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK)
113506 /*! @} */
113507 
113508 /*! @name SWREG274 - roimap cu ctrl index address MSB */
113509 /*! @{ */
113510 
113511 #define VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK (0xFFFFFFFFU)
113512 #define VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT (0U)
113513 #define VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK)
113514 /*! @} */
113515 
113516 /*! @name SWREG275 - roimap cu ctrl address LSB */
113517 /*! @{ */
113518 
113519 #define VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK (0xFFFFFFFFU)
113520 #define VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT (0U)
113521 #define VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT)) & VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK)
113522 /*! @} */
113523 
113524 /*! @name SWREG276 - roimap cu ctrl address MSB */
113525 /*! @{ */
113526 
113527 #define VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK (0xFFFFFFFFU)
113528 #define VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT (0U)
113529 #define VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK)
113530 /*! @} */
113531 
113532 /*! @name SWREG277 - poc type/bits setting */
113533 /*! @{ */
113534 
113535 #define VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK (0xFFFE0U)
113536 #define VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT (5U)
113537 #define VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT)) & VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK)
113538 
113539 #define VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK (0xF8000000U)
113540 #define VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT (27U)
113541 #define VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT)) & VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK)
113542 /*! @} */
113543 
113544 /*! @name SWREG278 - stream output buffer1 address */
113545 /*! @{ */
113546 
113547 #define VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK (0xFFFFFFFFU)
113548 #define VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT (0U)
113549 #define VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT)) & VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK)
113550 /*! @} */
113551 
113552 /*! @name SWREG280 - stream output buffer1 limit size */
113553 /*! @{ */
113554 
113555 #define VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK (0xFFFFFFFFU)
113556 #define VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT (0U)
113557 #define VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT)) & VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK)
113558 /*! @} */
113559 
113560 /*! @name SWREG281 - poc type/bits setting */
113561 /*! @{ */
113562 
113563 #define VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK (0x3F0U)
113564 #define VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT (4U)
113565 #define VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT)) & VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK)
113566 
113567 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK (0xFFC00U)
113568 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT (10U)
113569 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK)
113570 
113571 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK (0x3FF00000U)
113572 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT (20U)
113573 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK)
113574 
113575 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK (0x40000000U)
113576 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT (30U)
113577 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK)
113578 
113579 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK (0x80000000U)
113580 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT (31U)
113581 #define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK)
113582 /*! @} */
113583 
113584 /*! @name SWREG287 - HW synthesis config register 4, read-only */
113585 /*! @{ */
113586 
113587 #define VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK (0x20000000U)
113588 #define VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT (29U)
113589 /*! SW_ENC_HWSCALER420SUPPORT
113590  *  0b0..not supported.
113591  *  0b1..supported
113592  */
113593 #define VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT)) & VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK)
113594 
113595 #define VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK (0x40000000U)
113596 #define VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT (30U)
113597 /*! SW_ENC_HWCSCEXTENSIONSUPPORT
113598  *  0b0..not supported.
113599  *  0b1..supported
113600  */
113601 #define VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT)) & VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK)
113602 
113603 #define VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK (0x80000000U)
113604 #define VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT (31U)
113605 /*! SW_ENC_HWVIDEOHEIGHTEXT
113606  *  0b0..Not.
113607  *  0b1..Yes.
113608  */
113609 #define VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT)) & VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK)
113610 /*! @} */
113611 
113612 /*! @name SWREG289 - Pre-processor color conversion parameters1 */
113613 /*! @{ */
113614 
113615 #define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_MASK  (0xFFFFU)
113616 #define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_SHIFT (0U)
113617 #define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_SHIFT)) & VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_MASK)
113618 
113619 #define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_MASK  (0xFFFF0000U)
113620 #define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_SHIFT (16U)
113621 #define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG(x)    (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_SHIFT)) & VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_MASK)
113622 /*! @} */
113623 
113624 
113625 /*!
113626  * @}
113627  */ /* end of group VPU_HEVC_Register_Masks */
113628 
113629 
113630 /* VPU_HEVC - Peripheral instance base addresses */
113631 /** Peripheral VPU_HEVC base address */
113632 #define VPU_HEVC_BASE                            (0x38320000u)
113633 /** Peripheral VPU_HEVC base pointer */
113634 #define VPU_HEVC                                 ((VPU_HEVC_Type *)VPU_HEVC_BASE)
113635 /** Array initializer of VPU_HEVC peripheral base addresses */
113636 #define VPU_HEVC_BASE_ADDRS                      { VPU_HEVC_BASE }
113637 /** Array initializer of VPU_HEVC peripheral base pointers */
113638 #define VPU_HEVC_BASE_PTRS                       { VPU_HEVC }
113639 
113640 /*!
113641  * @}
113642  */ /* end of group VPU_HEVC_Peripheral_Access_Layer */
113643 
113644 
113645 /* ----------------------------------------------------------------------------
113646    -- WDOG Peripheral Access Layer
113647    ---------------------------------------------------------------------------- */
113648 
113649 /*!
113650  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
113651  * @{
113652  */
113653 
113654 /** WDOG - Register Layout Typedef */
113655 typedef struct {
113656   __IO uint16_t WCR;                               /**< Watchdog Control Register, offset: 0x0 */
113657   __IO uint16_t WSR;                               /**< Watchdog Service Register, offset: 0x2 */
113658   __I  uint16_t WRSR;                              /**< Watchdog Reset Status Register, offset: 0x4 */
113659   __IO uint16_t WICR;                              /**< Watchdog Interrupt Control Register, offset: 0x6 */
113660   __IO uint16_t WMCR;                              /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
113661 } WDOG_Type;
113662 
113663 /* ----------------------------------------------------------------------------
113664    -- WDOG Register Masks
113665    ---------------------------------------------------------------------------- */
113666 
113667 /*!
113668  * @addtogroup WDOG_Register_Masks WDOG Register Masks
113669  * @{
113670  */
113671 
113672 /*! @name WCR - Watchdog Control Register */
113673 /*! @{ */
113674 
113675 #define WDOG_WCR_WDZST_MASK                      (0x1U)
113676 #define WDOG_WCR_WDZST_SHIFT                     (0U)
113677 /*! WDZST
113678  *  0b0..Continue timer operation (Default).
113679  *  0b1..Suspend the watchdog timer.
113680  */
113681 #define WDOG_WCR_WDZST(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
113682 
113683 #define WDOG_WCR_WDBG_MASK                       (0x2U)
113684 #define WDOG_WCR_WDBG_SHIFT                      (1U)
113685 /*! WDBG
113686  *  0b0..Continue WDOG timer operation (Default).
113687  *  0b1..Suspend the watchdog timer.
113688  */
113689 #define WDOG_WCR_WDBG(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
113690 
113691 #define WDOG_WCR_WDE_MASK                        (0x4U)
113692 #define WDOG_WCR_WDE_SHIFT                       (2U)
113693 /*! WDE
113694  *  0b0..Disable the Watchdog (Default).
113695  *  0b1..Enable the Watchdog.
113696  */
113697 #define WDOG_WCR_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
113698 
113699 #define WDOG_WCR_WDT_MASK                        (0x8U)
113700 #define WDOG_WCR_WDT_SHIFT                       (3U)
113701 /*! WDT
113702  *  0b0..No effect on WDOG_B (Default).
113703  *  0b1..Assert WDOG_B upon a Watchdog Time-out event.
113704  */
113705 #define WDOG_WCR_WDT(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
113706 
113707 #define WDOG_WCR_SRS_MASK                        (0x10U)
113708 #define WDOG_WCR_SRS_SHIFT                       (4U)
113709 /*! SRS
113710  *  0b0..Assert system reset signal.
113711  *  0b1..No effect on the system (Default).
113712  */
113713 #define WDOG_WCR_SRS(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
113714 
113715 #define WDOG_WCR_WDA_MASK                        (0x20U)
113716 #define WDOG_WCR_WDA_SHIFT                       (5U)
113717 /*! WDA
113718  *  0b0..Assert WDOG_B output.
113719  *  0b1..No effect on system (Default).
113720  */
113721 #define WDOG_WCR_WDA(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
113722 
113723 #define WDOG_WCR_SRE_MASK                        (0x40U)
113724 #define WDOG_WCR_SRE_SHIFT                       (6U)
113725 /*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal (SRS).
113726  *  0b0..Reserved
113727  *  0b1..This bit must be set to 1.
113728  */
113729 #define WDOG_WCR_SRE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
113730 
113731 #define WDOG_WCR_WDW_MASK                        (0x80U)
113732 #define WDOG_WCR_WDW_SHIFT                       (7U)
113733 /*! WDW
113734  *  0b0..Continue WDOG timer operation (Default).
113735  *  0b1..Suspend WDOG timer operation.
113736  */
113737 #define WDOG_WCR_WDW(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
113738 
113739 #define WDOG_WCR_WT_MASK                         (0xFF00U)
113740 #define WDOG_WCR_WT_SHIFT                        (8U)
113741 /*! WT
113742  *  0b00000000..- 0.5 Seconds (Default).
113743  *  0b00000001..- 1.0 Seconds.
113744  *  0b00000010..- 1.5 Seconds.
113745  *  0b00000011..- 2.0 Seconds.
113746  *  0b11111111..- 128 Seconds.
113747  */
113748 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
113749 /*! @} */
113750 
113751 /*! @name WSR - Watchdog Service Register */
113752 /*! @{ */
113753 
113754 #define WDOG_WSR_WSR_MASK                        (0xFFFFU)
113755 #define WDOG_WSR_WSR_SHIFT                       (0U)
113756 /*! WSR
113757  *  0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
113758  *  0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
113759  */
113760 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
113761 /*! @} */
113762 
113763 /*! @name WRSR - Watchdog Reset Status Register */
113764 /*! @{ */
113765 
113766 #define WDOG_WRSR_SFTW_MASK                      (0x1U)
113767 #define WDOG_WRSR_SFTW_SHIFT                     (0U)
113768 /*! SFTW
113769  *  0b0..Reset is not the result of a software reset.
113770  *  0b1..Reset is the result of a software reset.
113771  */
113772 #define WDOG_WRSR_SFTW(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
113773 
113774 #define WDOG_WRSR_TOUT_MASK                      (0x2U)
113775 #define WDOG_WRSR_TOUT_SHIFT                     (1U)
113776 /*! TOUT
113777  *  0b0..Reset is not the result of a WDOG timeout.
113778  *  0b1..Reset is the result of a WDOG timeout.
113779  */
113780 #define WDOG_WRSR_TOUT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
113781 
113782 #define WDOG_WRSR_POR_MASK                       (0x10U)
113783 #define WDOG_WRSR_POR_SHIFT                      (4U)
113784 /*! POR
113785  *  0b0..Reset is not the result of a power on reset.
113786  *  0b1..Reset is the result of a power on reset.
113787  */
113788 #define WDOG_WRSR_POR(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
113789 /*! @} */
113790 
113791 /*! @name WICR - Watchdog Interrupt Control Register */
113792 /*! @{ */
113793 
113794 #define WDOG_WICR_WICT_MASK                      (0xFFU)
113795 #define WDOG_WICR_WICT_SHIFT                     (0U)
113796 /*! WICT
113797  *  0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
113798  *  0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
113799  *  0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
113800  *  0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
113801  */
113802 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
113803 
113804 #define WDOG_WICR_WTIS_MASK                      (0x4000U)
113805 #define WDOG_WICR_WTIS_SHIFT                     (14U)
113806 /*! WTIS
113807  *  0b0..No interrupt has occurred (Default).
113808  *  0b1..Interrupt has occurred
113809  */
113810 #define WDOG_WICR_WTIS(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
113811 
113812 #define WDOG_WICR_WIE_MASK                       (0x8000U)
113813 #define WDOG_WICR_WIE_SHIFT                      (15U)
113814 /*! WIE
113815  *  0b0..Disable Interrupt (Default).
113816  *  0b1..Enable Interrupt.
113817  */
113818 #define WDOG_WICR_WIE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
113819 /*! @} */
113820 
113821 /*! @name WMCR - Watchdog Miscellaneous Control Register */
113822 /*! @{ */
113823 
113824 #define WDOG_WMCR_PDE_MASK                       (0x1U)
113825 #define WDOG_WMCR_PDE_SHIFT                      (0U)
113826 /*! PDE
113827  *  0b0..Power Down Counter of WDOG is disabled.
113828  *  0b1..Power Down Counter of WDOG is enabled (Default).
113829  */
113830 #define WDOG_WMCR_PDE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
113831 /*! @} */
113832 
113833 
113834 /*!
113835  * @}
113836  */ /* end of group WDOG_Register_Masks */
113837 
113838 
113839 /* WDOG - Peripheral instance base addresses */
113840 /** Peripheral WDOG1 base address */
113841 #define WDOG1_BASE                               (0x30280000u)
113842 /** Peripheral WDOG1 base pointer */
113843 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
113844 /** Peripheral WDOG2 base address */
113845 #define WDOG2_BASE                               (0x30290000u)
113846 /** Peripheral WDOG2 base pointer */
113847 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
113848 /** Peripheral WDOG3 base address */
113849 #define WDOG3_BASE                               (0x302A0000u)
113850 /** Peripheral WDOG3 base pointer */
113851 #define WDOG3                                    ((WDOG_Type *)WDOG3_BASE)
113852 /** Array initializer of WDOG peripheral base addresses */
113853 #define WDOG_BASE_ADDRS                          { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE }
113854 /** Array initializer of WDOG peripheral base pointers */
113855 #define WDOG_BASE_PTRS                           { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 }
113856 /** Interrupt vectors for the WDOG peripheral type */
113857 #define WDOG_IRQS                                { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn }
113858 
113859 /*!
113860  * @}
113861  */ /* end of group WDOG_Peripheral_Access_Layer */
113862 
113863 
113864 /* ----------------------------------------------------------------------------
113865    -- XTALOSC Peripheral Access Layer
113866    ---------------------------------------------------------------------------- */
113867 
113868 /*!
113869  * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer
113870  * @{
113871  */
113872 
113873 /** XTALOSC - Register Layout Typedef */
113874 typedef struct {
113875   __IO uint32_t SYS_OSCNML_CTL0;                   /**< OSC Normal Clock Generation Control Register0, offset: 0x0 */
113876   __IO uint32_t SYS_OSCNML_CTL1;                   /**< OSC Normal Clock Generation Control Register1, offset: 0x4 */
113877 } XTALOSC_Type;
113878 
113879 /* ----------------------------------------------------------------------------
113880    -- XTALOSC Register Masks
113881    ---------------------------------------------------------------------------- */
113882 
113883 /*!
113884  * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks
113885  * @{
113886  */
113887 
113888 /*! @name SYS_OSCNML_CTL0 - OSC Normal Clock Generation Control Register0 */
113889 /*! @{ */
113890 
113891 #define XTALOSC_SYS_OSCNML_CTL0_SF0_MASK         (0x1U)
113892 #define XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT        (0U)
113893 #define XTALOSC_SYS_OSCNML_CTL0_SF0(x)           (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF0_MASK)
113894 
113895 #define XTALOSC_SYS_OSCNML_CTL0_SF1_MASK         (0x2U)
113896 #define XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT        (1U)
113897 #define XTALOSC_SYS_OSCNML_CTL0_SF1(x)           (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF1_MASK)
113898 
113899 #define XTALOSC_SYS_OSCNML_CTL0_SP_MASK          (0x4U)
113900 #define XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT         (2U)
113901 #define XTALOSC_SYS_OSCNML_CTL0_SP(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SP_MASK)
113902 
113903 #define XTALOSC_SYS_OSCNML_CTL0_RTO_MASK         (0x10U)
113904 #define XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT        (4U)
113905 #define XTALOSC_SYS_OSCNML_CTL0_RTO(x)           (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_RTO_MASK)
113906 
113907 #define XTALOSC_SYS_OSCNML_CTL0_EN_MASK          (0x80000000U)
113908 #define XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT         (31U)
113909 #define XTALOSC_SYS_OSCNML_CTL0_EN(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_EN_MASK)
113910 /*! @} */
113911 
113912 /*! @name SYS_OSCNML_CTL1 - OSC Normal Clock Generation Control Register1 */
113913 /*! @{ */
113914 
113915 #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK (0x2U)
113916 #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT (1U)
113917 #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK)
113918 
113919 #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK     (0x4U)
113920 #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT    (2U)
113921 #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK)
113922 
113923 #define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK  (0xFF0U)
113924 #define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT (4U)
113925 #define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK)
113926 /*! @} */
113927 
113928 
113929 /*!
113930  * @}
113931  */ /* end of group XTALOSC_Register_Masks */
113932 
113933 
113934 /* XTALOSC - Peripheral instance base addresses */
113935 /** Peripheral XTALOSC base address */
113936 #define XTALOSC_BASE                             (0x30270000u)
113937 /** Peripheral XTALOSC base pointer */
113938 #define XTALOSC                                  ((XTALOSC_Type *)XTALOSC_BASE)
113939 /** Array initializer of XTALOSC peripheral base addresses */
113940 #define XTALOSC_BASE_ADDRS                       { XTALOSC_BASE }
113941 /** Array initializer of XTALOSC peripheral base pointers */
113942 #define XTALOSC_BASE_PTRS                        { XTALOSC }
113943 
113944 /*!
113945  * @}
113946  */ /* end of group XTALOSC_Peripheral_Access_Layer */
113947 
113948 /*!
113949  * @}
113950  */ /* end of group Peripheral_access_layer */
113951 
113952 
113953 /* ----------------------------------------------------------------------------
113954    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
113955    ---------------------------------------------------------------------------- */
113956 
113957 /*!
113958  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
113959  * @{
113960  */
113961 
113962 /**
113963  * @brief Mask and left-shift a bit field value for use in a register bit range.
113964  * @param field Name of the register bit field.
113965  * @param value Value of the bit field.
113966  * @return Masked and shifted value.
113967  */
113968 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
113969 /**
113970  * @brief Mask and right-shift a register value to extract a bit field value.
113971  * @param field Name of the register bit field.
113972  * @param value Value of the register.
113973  * @return Masked and shifted bit field value.
113974  */
113975 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
113976 
113977 /*!
113978  * @}
113979  */ /* end of group Bit_Field_Generic_Macros */
113980 
113981 
113982 /* ----------------------------------------------------------------------------
113983    -- SDK Compatibility
113984    ---------------------------------------------------------------------------- */
113985 
113986 /*!
113987  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
113988  * @{
113989  */
113990 
113991 /* No SDK compatibility issues. */
113992 
113993 /*!
113994  * @}
113995  */ /* end of group SDK_Compatibility_Symbols */
113996 
113997 
113998 #endif  /* _MIMX8ML8_DSP_H_ */
113999 
114000