1 /* 2 ** ################################################################### 3 ** Version: rev. 3.0, 2019-11-05 4 ** Build: b231017 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2017-09-19) 18 ** Initial version. 19 ** - rev. 2.0 (2018-08-22) 20 ** RevB Header EAR 21 ** - rev. 3.0 (2019-11-05) 22 ** RevC Header RFP 23 ** 24 ** ################################################################### 25 */ 26 27 #ifndef _MIMX8DX5_cm4_FEATURES_H_ 28 #define _MIMX8DX5_cm4_FEATURES_H_ 29 30 /* SOC module features */ 31 32 /* @brief APBH availability on the SoC. */ 33 #define FSL_FEATURE_SOC_APBH_COUNT (1) 34 /* @brief ASMC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_ASMC_COUNT (2) 36 /* @brief ASRC availability on the SoC. */ 37 #define FSL_FEATURE_SOC_ASRC_COUNT (2) 38 /* @brief BCH availability on the SoC. */ 39 #define FSL_FEATURE_SOC_BCH_COUNT (1) 40 /* @brief EDMA availability on the SoC. */ 41 #define FSL_FEATURE_SOC_EDMA_COUNT (5) 42 /* @brief ENET availability on the SoC. */ 43 #define FSL_FEATURE_SOC_ENET_COUNT (2) 44 /* @brief ESAI availability on the SoC. */ 45 #define FSL_FEATURE_SOC_ESAI_COUNT (1) 46 /* @brief FLEXCAN availability on the SoC. */ 47 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (3) 48 /* @brief FLEXSPI availability on the SoC. */ 49 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (2) 50 /* @brief FTM availability on the SoC. */ 51 #define FSL_FEATURE_SOC_FTM_COUNT (2) 52 /* @brief GPIO availability on the SoC. */ 53 #define FSL_FEATURE_SOC_GPIO_COUNT (13) 54 /* @brief GPMI availability on the SoC. */ 55 #define FSL_FEATURE_SOC_GPMI_COUNT (1) 56 /* @brief GPT availability on the SoC. */ 57 #define FSL_FEATURE_SOC_GPT_COUNT (11) 58 /* @brief I2S availability on the SoC. */ 59 #define FSL_FEATURE_SOC_I2S_COUNT (6) 60 /* @brief INTMUX availability on the SoC. */ 61 #define FSL_FEATURE_SOC_INTMUX_COUNT (2) 62 /* @brief IRQSTEER availability on the SoC. */ 63 #define FSL_FEATURE_SOC_IRQSTEER_COUNT (1) 64 /* @brief ISI availability on the SoC. */ 65 #define FSL_FEATURE_SOC_ISI_COUNT (6) 66 /* @brief KPP availability on the SoC. */ 67 #define FSL_FEATURE_SOC_KPP_COUNT (1) 68 /* @brief LCDIF availability on the SoC. */ 69 #define FSL_FEATURE_SOC_LCDIF_COUNT (1) 70 /* @brief LMEM availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LMEM_COUNT (1) 72 /* @brief LPADC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 74 /* @brief LPI2C availability on the SoC. */ 75 #define FSL_FEATURE_SOC_LPI2C_COUNT (12) 76 /* @brief LPIT availability on the SoC. */ 77 #define FSL_FEATURE_SOC_LPIT_COUNT (2) 78 /* @brief LPSPI availability on the SoC. */ 79 #define FSL_FEATURE_SOC_LPSPI_COUNT (4) 80 /* @brief LPUART availability on the SoC. */ 81 #define FSL_FEATURE_SOC_LPUART_COUNT (6) 82 /* @brief MCM availability on the SoC. */ 83 #define FSL_FEATURE_SOC_MCM_COUNT (1) 84 /* @brief MIPI_CSI2RX availability on the SoC. */ 85 #define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (1) 86 /* @brief MIPI_DSI_HOST availability on the SoC. */ 87 #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (2) 88 /* @brief MMCAU availability on the SoC. */ 89 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 90 /* @brief MU availability on the SoC. */ 91 #define FSL_FEATURE_SOC_MU_COUNT (41) 92 /* @brief PWM availability on the SoC. */ 93 #define FSL_FEATURE_SOC_PWM_COUNT (13) 94 /* @brief RGPIO availability on the SoC. */ 95 #define FSL_FEATURE_SOC_RGPIO_COUNT (2) 96 /* @brief ROMC availability on the SoC. */ 97 #define FSL_FEATURE_SOC_ROMC_COUNT (1) 98 /* @brief SEMA42 availability on the SoC. */ 99 #define FSL_FEATURE_SOC_SEMA42_COUNT (2) 100 /* @brief SPDIF availability on the SoC. */ 101 #define FSL_FEATURE_SOC_SPDIF_COUNT (1) 102 /* @brief TPM availability on the SoC. */ 103 #define FSL_FEATURE_SOC_TPM_COUNT (2) 104 /* @brief TSTMR availability on the SoC. */ 105 #define FSL_FEATURE_SOC_TSTMR_COUNT (2) 106 /* @brief USB availability on the SoC. */ 107 #define FSL_FEATURE_SOC_USB_COUNT (1) 108 /* @brief USB3 availability on the SoC. */ 109 #define FSL_FEATURE_SOC_USB3_COUNT (1) 110 /* @brief USBDCD availability on the SoC. */ 111 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 112 /* @brief USBNC availability on the SoC. */ 113 #define FSL_FEATURE_SOC_USBNC_COUNT (1) 114 /* @brief USBPHY availability on the SoC. */ 115 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 116 /* @brief USDHC availability on the SoC. */ 117 #define FSL_FEATURE_SOC_USDHC_COUNT (3) 118 /* @brief WDOG availability on the SoC. */ 119 #define FSL_FEATURE_SOC_WDOG_COUNT (2) 120 121 /* LPADC module features */ 122 123 /* @brief FIFO availability on the SoC. */ 124 #define FSL_FEATURE_LPADC_FIFO_COUNT (1) 125 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 126 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 127 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 128 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1) 129 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 130 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1) 131 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 132 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0) 133 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 134 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0) 135 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 136 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 137 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 138 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0) 139 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 140 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0) 141 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 142 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0) 143 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 144 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0) 145 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 146 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 147 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 148 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 149 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 150 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 151 /* @brief Has offset trim (register OFSTRIM). */ 152 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) 153 /* @brief Has Trigger status register. */ 154 #define FSL_FEATURE_LPADC_HAS_TSTAT (0) 155 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 156 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 157 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 158 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 159 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 160 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 161 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 162 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 163 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 164 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 165 /* @brief Conversion averaged bitfiled width. */ 166 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 167 /* @brief Has B side channels. */ 168 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 169 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 170 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (0) 171 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 172 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (0) 173 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 174 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (0) 175 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 176 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 177 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 178 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (0) 179 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 180 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (0) 181 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 182 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (0) 183 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 184 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (0) 185 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 186 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (0) 187 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 188 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (1) 189 190 /* FLEXCAN module features */ 191 192 /* @brief Has more than 64 MBs. */ 193 #define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) 194 /* @brief Message buffer size */ 195 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) 196 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 197 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 198 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 199 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 200 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 201 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 202 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 203 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) 204 /* @brief Instance has extended bit timing register (register CBT). */ 205 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 206 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 207 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 208 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 209 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 210 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ 211 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) 212 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ 213 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) 214 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 215 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (1) 216 /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ 217 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) 218 /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ 219 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) 220 /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ 221 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) 222 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ 223 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) 224 /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ 225 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) 226 /* @brief Has memory error control (register MECR). */ 227 #define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) 228 /* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ 229 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0) 230 /* @brief Has Pretended Networking mode support. */ 231 #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) 232 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ 233 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) 234 235 /* EDMA module features */ 236 237 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 238 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 239 /* @brief If 8 bytes transfer supported. */ 240 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 241 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 242 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 243 /* @brief If 16 bytes transfer supported. */ 244 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 245 /* @brief Has DMA_Error interrupt vector. */ 246 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 247 /* @brief If 64 bytes transfer supported. */ 248 #define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) 249 /* @brief If channel clock controlled independently */ 250 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) 251 /* @brief If 128 bytes transfer supported. */ 252 #define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) 253 /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ 254 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ 255 (((x) == ADMA__EDMA0) ? (32) : \ 256 (((x) == ADMA__EDMA1) ? (16) : \ 257 (((x) == ADMA__EDMA2) ? (32) : \ 258 (((x) == ADMA__EDMA3) ? (16) : \ 259 (((x) == CONNECTIVITY__EDMA) ? (5) : (-1)))))) 260 /* @brief If 128 bytes transfer supported. */ 261 #define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) 262 /* @brief Has no register bit fields MP_CSR[EBW]. */ 263 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (0) 264 /* @brief Has register CH_CSR. */ 265 #define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) 266 /* @brief If dma has common clock gate */ 267 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) 268 /* @brief Has channel mux */ 269 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (0) 270 /* @brief If dma channel IRQ support parameter */ 271 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) 272 /* @brief Instance has channel mux */ 273 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) \ 274 (((x) == ADMA__EDMA0) ? (0) : \ 275 (((x) == ADMA__EDMA1) ? (1) : \ 276 (((x) == ADMA__EDMA2) ? (0) : \ 277 (((x) == ADMA__EDMA3) ? (1) : \ 278 (((x) == CONNECTIVITY__EDMA) ? (1) : (-1)))))) 279 /* @brief NBYTES must be multiple of 8 when using scatter gather. */ 280 #define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) 281 /* @brief Has register CH_SBR. */ 282 #define FSL_FEATURE_EDMA_HAS_SBR (1) 283 /* @brief NBYTES must be multiple of 8 when using scatter gather. */ 284 #define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) 285 /* @brief Has no register bit fields CH_SBR[ATTR]. */ 286 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (0) 287 /* @brief Has register bit fields MP_CSR[GMRC]. */ 288 #define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) 289 /* @brief Has register bit field CH_CSR[SWAP]. */ 290 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) 291 /* @brief Instance has register bit field CH_CSR[SWAP]. */ 292 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) 293 /* @brief Has register bit field CH_SBR[INSTR]. */ 294 #define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) 295 /* @brief Instance has register bit field CH_SBR[INSTR]. */ 296 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) 297 /* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ 298 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) 299 /* @brief Instance has register CH_MATTR. */ 300 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) 301 /* @brief Has register bit field CH_CSR[SIGNEXT]. */ 302 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) 303 /* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ 304 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) 305 /* @brief Has register bit field TCD_CSR[BWC]. */ 306 #define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) 307 /* @brief Instance has register bit field TCD_CSR[BWC]. */ 308 #define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) 309 /* @brief Has register bit fields TCD_CSR[TMC]. */ 310 #define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) 311 /* @brief Instance has register bit fields TCD_CSR[TMC]. */ 312 #define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) 313 314 /* ESAI module features */ 315 316 /* @brief ESAI FIFO Size. */ 317 #define FSL_FEATURE_ESAI_FIFO_SIZEn(x) (128) 318 319 /* FTM module features */ 320 321 /* @brief Number of channels. */ 322 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) (8) 323 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 324 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 325 /* @brief Has extended deadtime value. */ 326 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 327 /* @brief Enable pwm output for the module. */ 328 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1) 329 /* @brief Has half-cycle reload for the module. */ 330 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1) 331 /* @brief Has reload interrupt. */ 332 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1) 333 /* @brief Has reload initialization trigger. */ 334 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1) 335 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 336 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 337 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 338 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (1) 339 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 340 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (1) 341 /* @brief If instance has only TPM function. */ 342 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 343 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 344 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (1) 345 346 /* LPI2C module features */ 347 348 /* @brief Has separate DMA RX and TX requests. */ 349 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 350 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 351 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) \ 352 (((x) == SCU__LPI2C) ? (4) : \ 353 (((x) == CM4__LPI2C) ? (4) : \ 354 (((x) == DI_MIPI_DSI_LVDS_0__LPI2C0) ? (16) : \ 355 (((x) == DI_MIPI_DSI_LVDS_0__LPI2C1) ? (16) : \ 356 (((x) == DI_MIPI_DSI_LVDS_1__LPI2C0) ? (16) : \ 357 (((x) == DI_MIPI_DSI_LVDS_1__LPI2C1) ? (16) : \ 358 (((x) == MIPI_CSI__LPI2C) ? (16) : \ 359 (((x) == CI_PI__LPI2C0) ? (16) : \ 360 (((x) == ADMA__LPI2C0) ? (16) : \ 361 (((x) == ADMA__LPI2C1) ? (16) : \ 362 (((x) == ADMA__LPI2C2) ? (16) : \ 363 (((x) == ADMA__LPI2C3) ? (16) : (-1))))))))))))) 364 365 /* LPSPI module features */ 366 367 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 368 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (64) 369 /* @brief Has separate DMA RX and TX requests. */ 370 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 371 /* @brief Has CCR1 (related to existence of registers CCR1). */ 372 #define FSL_FEATURE_LPSPI_HAS_CCR1 (0) 373 374 /* LPUART module features */ 375 376 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 377 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 378 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 379 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 380 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 381 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 382 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 383 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 384 /* @brief Has 32-bit register MODIR */ 385 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 386 /* @brief Hardware flow control (RTS, CTS) is supported. */ 387 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 388 /* @brief Infrared (modulation) is supported. */ 389 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 390 /* @brief 2 bits long stop bit is available. */ 391 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 392 /* @brief If 10-bit mode is supported. */ 393 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 394 /* @brief If 7-bit mode is supported. */ 395 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 396 /* @brief Baud rate fine adjustment is available. */ 397 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 398 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 399 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 400 /* @brief Baud rate oversampling is available. */ 401 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 402 /* @brief Baud rate oversampling is available. */ 403 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 404 /* @brief Peripheral type. */ 405 #define FSL_FEATURE_LPUART_IS_SCI (1) 406 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 407 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ 408 (((x) == SCU__LPUART) ? (32) : \ 409 (((x) == CM4__LPUART) ? (32) : \ 410 (((x) == ADMA__LPUART0) ? (64) : \ 411 (((x) == ADMA__LPUART1) ? (64) : \ 412 (((x) == ADMA__LPUART2) ? (64) : \ 413 (((x) == ADMA__LPUART3) ? (64) : (-1))))))) 414 /* @brief Supports two match addresses to filter incoming frames. */ 415 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 416 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 417 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 418 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 419 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 420 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 421 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 422 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 423 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 424 /* @brief Has improved smart card (ISO7816 protocol) support. */ 425 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 426 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 427 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 428 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 429 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 430 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 431 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 432 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 433 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 434 /* @brief Has separate DMA RX and TX requests. */ 435 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 436 /* @brief Has separate RX and TX interrupts. */ 437 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 438 /* @brief Has LPAURT_PARAM. */ 439 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 440 /* @brief Has LPUART_VERID. */ 441 #define FSL_FEATURE_LPUART_HAS_VERID (1) 442 /* @brief Has LPUART_GLOBAL. */ 443 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 444 /* @brief Has LPUART_PINCFG. */ 445 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 446 /* @brief Has register MODEM Control. */ 447 #define FSL_FEATURE_LPUART_HAS_MCR (0) 448 /* @brief Has register Half Duplex Control. */ 449 #define FSL_FEATURE_LPUART_HAS_HDCR (0) 450 /* @brief Has register Timeout. */ 451 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) 452 453 /* SAI module features */ 454 455 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 456 #define FSL_FEATURE_SAI_HAS_FIFO (1) 457 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 458 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (64) 459 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 460 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (1) 461 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 462 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 463 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 464 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 465 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 466 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 467 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 468 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 469 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 470 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 471 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 472 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 473 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 474 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 475 /* @brief Interrupt source number */ 476 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) 477 /* @brief Has register of MCR. */ 478 #define FSL_FEATURE_SAI_HAS_MCR (0) 479 /* @brief Has bit field MICS of the MCR register. */ 480 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 481 /* @brief Has register of MDR */ 482 #define FSL_FEATURE_SAI_HAS_MDR (0) 483 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 484 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) 485 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 486 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 487 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 488 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 489 /* @brief Support synchronous with another SAI. */ 490 #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) 491 492 /* ASMC module features */ 493 494 /* @brief Has high speed run mode. */ 495 #define FSL_FEATURE_ASMC_HAS_HIGH_SPEED_RUN_MODE (0) 496 497 /* INTMUX module features */ 498 499 /* @brief Number of INTMUX channels (related to number of register CHn_CSR). */ 500 #define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8) 501 /* @brief Number of INTMUX IRQ source. */ 502 #define FSL_FEATURE_INTMUX_IRQ_COUNT (32) 503 /* @brief The start IRQ index of first INTMUX source IRQ. */ 504 #define FSL_FEATURE_INTMUX_IRQ_START_INDEX (563) 505 /* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */ 506 #define FSL_FEATURE_INTMUX_DIRECTION_OUT (1) 507 /* @brief The total number of level1 interrupt vectors. */ 508 #define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (51) 509 510 /* LPIT module features */ 511 512 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 513 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 514 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 515 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 516 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 517 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 518 519 /* MU module features */ 520 521 /* @brief MU side for current core */ 522 #define FSL_FEATURE_MU_SIDE_B (1) 523 /* @brief MU side for current core */ 524 #define FSL_FEATURE_MU_SIDE_A (1) 525 /* @brief MU Has register CCR */ 526 #define FSL_FEATURE_MU_HAS_CCR (0) 527 /* @brief MU Has register SR[RS], BSR[ARS] */ 528 #define FSL_FEATURE_MU_HAS_SR_RS (1) 529 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ 530 #define FSL_FEATURE_MU_HAS_RESET_INT (0) 531 /* @brief MU Has register SR[MURIP] */ 532 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 533 /* @brief MU Has register SR[HRIP] */ 534 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 535 /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 536 #define FSL_FEATURE_MU_NO_CLKE (1) 537 /* @brief MU does not support NMI, CR[NMI]. */ 538 #define FSL_FEATURE_MU_NO_NMI (1) 539 /* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ 540 #define FSL_FEATURE_MU_NO_RSTH (1) 541 /* @brief MU does not supports MU reset, CR[MUR]. */ 542 #define FSL_FEATURE_MU_NO_MUR (1) 543 /* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ 544 #define FSL_FEATURE_MU_NO_HR (1) 545 /* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ 546 #define FSL_FEATURE_MU_HAS_HRM (1) 547 /* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */ 548 #define FSL_FEATURE_MU_NO_PM (1) 549 /* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */ 550 #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0) 551 /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ 552 #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0) 553 554 /* RGPIO module features */ 555 556 /* @brief Has GPIO attribute checker register (GACR). */ 557 #define FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER (0) 558 /* @brief There is ICR registers */ 559 #define FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG (0) 560 /* @brief There is PIDR register */ 561 #define FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE (0) 562 563 /* SEMA42 module features */ 564 565 /* @brief Gate counts */ 566 #define FSL_FEATURE_SEMA42_GATE_COUNT (16) 567 568 /* TPM module features */ 569 570 /* @brief Number of channels. */ 571 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (6) 572 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 573 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 574 /* @brief Has TPM_PARAM. */ 575 #define FSL_FEATURE_TPM_HAS_PARAM (1) 576 /* @brief Has TPM_VERID. */ 577 #define FSL_FEATURE_TPM_HAS_VERID (1) 578 /* @brief Has TPM_GLOBAL. */ 579 #define FSL_FEATURE_TPM_HAS_GLOBAL (1) 580 /* @brief Has TPM_TRIG. */ 581 #define FSL_FEATURE_TPM_HAS_TRIG (1) 582 /* @brief Whether TRIG register has effect. */ 583 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (1) 584 /* @brief Has counter pause on trigger. */ 585 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 586 /* @brief Has external trigger selection. */ 587 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 588 /* @brief Has TPM_COMBINE register. */ 589 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 590 /* @brief Whether COMBINE register has effect. */ 591 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 592 /* @brief Has TPM_POL. */ 593 #define FSL_FEATURE_TPM_HAS_POL (1) 594 /* @brief Whether POL register has effect. */ 595 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 596 /* @brief Has TPM_FILTER register. */ 597 #define FSL_FEATURE_TPM_HAS_FILTER (1) 598 /* @brief Whether FILTER register has effect. */ 599 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 600 /* @brief Has TPM_QDCTRL register. */ 601 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 602 /* @brief Whether QDCTRL register has effect. */ 603 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 604 /* @brief Has pause level select. */ 605 #define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (0) 606 /* @brief Whether 32 bits counter has effect. */ 607 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (1) 608 609 /* TSTMR module features */ 610 611 /* @brief TSTMR clock frequency is 1MHZ. */ 612 #define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (0) 613 /* @brief TSTMR clock frequency is 1MHZ. */ 614 #define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ (1) 615 616 /* WDOG module features */ 617 618 /* @brief Watchdog is available. */ 619 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 620 /* @brief WDOG_CNT can be 32-bit written. */ 621 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 622 623 /* ENET module features */ 624 625 /* @brief Support Interrupt Coalesce */ 626 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) 627 /* @brief Queue Size. */ 628 #define FSL_FEATURE_ENET_QUEUE (3) 629 /* @brief Has AVB Support. */ 630 #define FSL_FEATURE_ENET_HAS_AVB (1) 631 /* @brief Has Timer Pulse Width control. */ 632 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) 633 /* @brief Has Extend MDIO Support. */ 634 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) 635 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 636 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) 637 /* @brief Support Interrupt Coalesce for each instance */ 638 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) 639 /* @brief Queue Size for each instance. */ 640 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) 641 /* @brief Has AVB Support for each instance. */ 642 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) 643 /* @brief Has Timer Pulse Width control for each instance. */ 644 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1) 645 /* @brief Has Extend MDIO Support for each instance. */ 646 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) 647 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 648 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) 649 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 650 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 651 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 652 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) 653 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 654 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) 655 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ 656 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) 657 /* @brief ENET Has Extra Clock Gate.(RW610). */ 658 #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) 659 /* @brief ENET need workaround for ERRATA_007885. */ 660 #define FSL_FEATURE_ENET_HAS_ERRATA_007885 (1) 661 662 /* USDHC module features */ 663 664 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 665 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) 666 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 667 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 668 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 669 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 670 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 671 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 672 /* @brief USDHC has reset control */ 673 #define FSL_FEATURE_USDHC_HAS_RESET (0) 674 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 675 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) 676 /* @brief If USDHC instance support 8 bit width */ 677 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 678 /* @brief If USDHC instance support HS400 mode */ 679 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) 680 /* @brief If USDHC instance support 1v8 signal */ 681 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 682 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 683 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) 684 /* @brief Has no VSELECT bit in VEND_SPEC register */ 685 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) 686 687 /* MIPI_DSI_HOST module features */ 688 689 /* @brief Does not have DPHY PLL */ 690 #define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1) 691 /* @brief Support TX ULPS */ 692 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (1) 693 /* @brief Has control register to enable or disable TX ULPS */ 694 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (1) 695 /* @brief Has pixel-link to DPI remap */ 696 #define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (1) 697 /* @brief Offset between MIPI DSI controller and CSR in the MIPI DSI subsystem. */ 698 #define FSL_FEATURE_DSI_CSR_OFFSET (0x7000) 699 /* @brief Use Mixel combo PHY. */ 700 #define FSL_FEATURE_LDB_COMBO_PHY (1) 701 702 /* IRQSTEER module features */ 703 704 /* @brief Number of IRQSTEER CHn_MASK register. */ 705 #define FSL_FEATURE_IRQSTEER_CHn_MASK_COUNT (16) 706 /* @brief The start IRQ index of first IRQSTEER source IRQ. */ 707 #define FSL_FEATURE_IRQSTEER_IRQ_START_INDEX (51) 708 /* @brief Number of IRQSTEER master. */ 709 #define FSL_FEATURE_IRQSTEER_MASTER_COUNT (8) 710 711 /* LMEM module features */ 712 713 /* @brief Has process identifier support. */ 714 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1) 715 /* @brief Support instruction cache demote. */ 716 #define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1) 717 /* @brief Has no NONCACHEABLE section. */ 718 #define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) 719 /* @brief L1 ICACHE line size in byte. */ 720 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 721 /* @brief L1 DCACHE line size in byte. */ 722 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 723 724 /* FLEXSPI module features */ 725 726 /* @brief FlexSPI AHB buffer count */ 727 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 728 /* @brief FlexSPI has no data learn. */ 729 #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) 730 /* @brief There is AHBBUSERROREN bit in INTEN register. */ 731 #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) 732 /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ 733 #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0) 734 /* @brief FLEXSPI has no IP parallel mode. */ 735 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) 736 /* @brief FLEXSPI has no AHB parallel mode. */ 737 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) 738 /* @brief FLEXSPI support address shift. */ 739 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 740 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 741 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) 742 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 743 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) 744 745 /* MEMORY module features */ 746 747 /* @brief Memory map has offset between subsystems. */ 748 #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) 749 750 /* MIPI_CSI2RX module features */ 751 752 /* @brief Offset between MIPI CSI controller and CSR in the MIPI CSI subsystem. */ 753 #define FSL_FEATURE_CSI2RX_CSR_OFFSET (0x6100) 754 755 #endif /* _MIMX8DX5_cm4_FEATURES_H_ */ 756 757
