1 /*
2 * Copyright 2017 - 2021 , 2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.3. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 3))
26 /*@}*/
27
28 /*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40 #endif
41
42 /*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51 #endif
52
53 /* Definition for delay API in clock driver, users can redefine it to the real application. */
54 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL)
56 #endif
57
58 /*! @brief Clock ip name array for ROM. */
59 #define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63 /*! @brief Clock ip name array for SRAM. */
64 #define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \
67 }
68 /*! @brief Clock ip name array for FLASH. */
69 #define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73 /*! @brief Clock ip name array for FMC. */
74 #define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78 /*! @brief Clock ip name array for INPUTMUX. */
79 #define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux \
82 }
83 /*! @brief Clock ip name array for IOCON. */
84 #define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88 /*! @brief Clock ip name array for GPIO. */
89 #define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \
92 }
93 /*! @brief Clock ip name array for PINT. */
94 #define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98 /*! @brief Clock ip name array for GINT. */
99 #define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103 /*! @brief Clock ip name array for DMA. */
104 #define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108 /*! @brief Clock ip name array for CRC. */
109 #define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc0 \
112 }
113 /*! @brief Clock ip name array for WWDT. */
114 #define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118 /*! @brief Clock ip name array for RTC. */
119 #define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc0 \
122 }
123 /*! @brief Clock ip name array for Mailbox. */
124 #define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128 /*! @brief Clock ip name array for LPADC. */
129 #define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0, kCLOCK_Adc1 \
132 }
133 /*! @brief Clock ip name array for DAC. */
134 #define LPDAC_CLOCKS \
135 { \
136 kCLOCK_Dac0, kCLOCK_Dac1, kCLOCK_Dac2 \
137 }
138 /*! @brief Clock ip name array for MRT. */
139 #define MRT_CLOCKS \
140 { \
141 kCLOCK_Mrt \
142 }
143 /*! @brief Clock ip name array for OSTIMER. */
144 #define OSTIMER_CLOCKS \
145 { \
146 kCLOCK_Ostimer \
147 }
148 /*! @brief Clock ip name array for SCT0. */
149 #define SCT_CLOCKS \
150 { \
151 kCLOCK_Sct \
152 }
153 /*! @brief Clock ip name array for MCAN. */
154 #define MCAN_CLOCKS \
155 { \
156 kCLOCK_Mcan \
157 }
158 /*! @brief Clock ip name array for UTICK. */
159 #define UTICK_CLOCKS \
160 { \
161 kCLOCK_Utick \
162 }
163 /*! @brief Clock ip name array for FLEXCOMM. */
164 #define FLEXCOMM_CLOCKS \
165 { \
166 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
167 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
168 }
169 /*! @brief Clock ip name array for LPUART. */
170 #define LPUART_CLOCKS \
171 { \
172 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
173 kCLOCK_MinUart6, kCLOCK_MinUart7 \
174 }
175
176 /*! @brief Clock ip name array for BI2C. */
177 #define BI2C_CLOCKS \
178 { \
179 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
180 }
181 /*! @brief Clock ip name array for LSPI. */
182 #define LPSPI_CLOCKS \
183 { \
184 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
185 }
186 /*! @brief Clock ip name array for FLEXI2S. */
187 #define FLEXI2S_CLOCKS \
188 { \
189 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
190 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
191 }
192 /*! @brief Clock ip name array for CTIMER. */
193 #define CTIMER_CLOCKS \
194 { \
195 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
196 }
197 /*! @brief Clock ip name array for COMP */
198 #define COMP_CLOCKS \
199 { \
200 kCLOCK_Comp \
201 }
202 /*! @brief Clock ip name array for FREQME. */
203 #define FREQME_CLOCKS \
204 { \
205 kCLOCK_Freqme \
206 }
207 /*! @brief Clock ip name array for CDOG. */
208 #define CDOG_CLOCKS \
209 { \
210 kCLOCK_Cdog \
211 }
212 /*! @brief Clock ip name array for RNG. */
213 #define RNG_CLOCKS \
214 { \
215 kCLOCK_Rng \
216 }
217 /*! @brief Clock ip name array for USBHMR0. */
218 #define USBHMR0_CLOCKS \
219 { \
220 kCLOCK_Usbhmr0 \
221 }
222 /*! @brief Clock ip name array for USBHSL0. */
223 #define USBHSL0_CLOCKS \
224 { \
225 kCLOCK_Usbhsl0 \
226 }
227 /*! @brief Clock ip name array for ANALOGCTRL. */
228 #define ANALOGCTRL_CLOCKS \
229 { \
230 kCLOCK_AnalogCtrl \
231 }
232 /*! @brief Clock ip name array for HS_LSPI. */
233 #define HS_LSPI_CLOCKS \
234 { \
235 kCLOCK_Hs_Lspi \
236 }
237 /*! @brief Clock ip name array for GPIO_SEC. */
238 #define GPIO_SEC_CLOCKS \
239 { \
240 kCLOCK_Gpio_Sec \
241 }
242 /*! @brief Clock ip name array for GPIO_SEC_INT. */
243 #define GPIO_SEC_INT_CLOCKS \
244 { \
245 kCLOCK_Gpio_Sec_Int \
246 }
247 /*! @brief Clock ip name array for USBD. */
248 #define USBD_CLOCKS \
249 { \
250 kCLOCK_Usbd0 \
251 }
252 /*! @brief Clock ip name array for SYSCTL. */
253 #define SYSCTL_CLOCKS \
254 { \
255 kCLOCK_Sysctl \
256 }
257 /*! @brief Clock ip name array for DMIC. */
258 #define DMIC_CLOCKS \
259 { \
260 kCLOCK_Dmic \
261 }
262 /*! @brief Clock ip name array for PWM. */
263 #define PWM_CLOCKS \
264 { \
265 {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \
266 { \
267 kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \
268 } \
269 }
270 /*! @brief Clock ip name array for ENC. */
271 #define ENC_CLOCKS \
272 { \
273 kCLOCK_Enc0, kCLOCK_Enc1 \
274 }
275 /*! @brief Clock ip name array for OPAMP. */
276 #define OPAMP_CLOCKS \
277 { \
278 kCLOCK_Opamp0, kCLOCK_Opamp1, kCLOCK_Opamp2 \
279 }
280 /*! @brief Clock ip name array for VREF. */
281 #define VREF_CLOCKS \
282 { \
283 kCLOCK_Vref \
284 }
285 /*! @brief Clock ip name array for FLEXSPI */
286 #define FLEXSPI_CLOCKS \
287 { \
288 kCLOCK_Flexspi \
289 }
290 /*! @brief Clock ip name array for Cache64 */
291 #define CACHE64_CLOCKS \
292 { \
293 kCLOCK_Flexspi \
294 }
295 /*! @brief Clock ip name array for I3C */
296 #define I3C_CLOCKS \
297 { \
298 kCLOCK_I3c0 \
299 }
300 /*! @brief Clock ip name array for HSCMP */
301 #define HSCMP_CLOCKS \
302 { \
303 kCLOCK_Hscmp0, kCLOCK_Hscmp1, kCLOCK_Hscmp2 \
304 }
305 /*! @brief Clock ip name array for PowerQuad. */
306 #define POWERQUAD_CLOCKS \
307 { \
308 kCLOCK_PowerQuad \
309 }
310 /*! @brief Clock ip name array for AOI. */
311 #define AOI_CLOCKS \
312 { \
313 kCLOCK_Aoi0, kCLOCK_Aoi1 \
314 }
315 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
316 /*------------------------------------------------------------------------------
317 clock_ip_name_t definition:
318 ------------------------------------------------------------------------------*/
319
320 #define CLK_GATE_REG_OFFSET_SHIFT 8U
321 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
322 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
323 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
324
325 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
326 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
327 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
328
329 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
330 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
331
332 #define AHB_CLK_CTRL0 0
333 #define AHB_CLK_CTRL1 1
334 #define AHB_CLK_CTRL2 2
335 #define AHB_CLK_CTRL3 3
336 #define REG_PWM0SUBCTL 250
337 #define REG_PWM1SUBCTL 251
338
339 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
340 typedef enum _clock_ip_name
341 {
342 kCLOCK_IpInvalid = 0U, /*!< Invalid IP name. */
343 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */
344 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3U), /*!< Clock gate name: Sram1. */
345 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Sram2. */
346 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5U), /*!< Clock gate name: Sram3. */
347 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Sram4. */
348 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Flash. */
349 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8U), /*!< Clock gate name: Fmc. */
350 kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Flexspi. */
351 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11U), /*!< Clock gate name: InputMux. */
352 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Iocon. */
353 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Gpio0. */
354 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Gpio1. */
355 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16U), /*!< Clock gate name: Gpio2. */
356 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Gpio3. */
357 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Pint. */
358 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Gint. */
359 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20U), /*!< Clock gate name: Dma0. */
360 kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21U), /*!< Clock gate name: Crc. */
361 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22U), /*!< Clock gate name: Wwdt. */
362 kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23U), /*!< Clock gate name: Rtc0. */
363 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26U), /*!< Clock gate name: Mailbox. */
364 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27U), /*!< Clock gate name: Adc0. */
365 kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28U), /*!< Clock gate name: Adc1. */
366 kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29U), /*!< Clock gate name: Dac0. */
367
368 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0U), /*!< Clock gate name: Mrt. */
369 kCLOCK_Ostimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1U), /*!< Clock gate name: Ostimer. */
370 kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2U), /*!< Clock gate name: Sct. */
371 kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7U), /*!< Clock gate name: Mcan. */
372 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10U), /*!< Clock gate name: Utick. */
373 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11U), /*!< Clock gate name: FlexComm0. */
374 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12U), /*!< Clock gate name: FlexComm1. */
375 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13U), /*!< Clock gate name: FlexComm2. */
376 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14U), /*!< Clock gate name: FlexComm3. */
377 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15U), /*!< Clock gate name: FlexComm4. */
378 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16U), /*!< Clock gate name: FlexComm5. */
379 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17U), /*!< Clock gate name: FlexComm6. */
380 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18U), /*!< Clock gate name: FlexComm7. */
381 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
382 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
383 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
384 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
385 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
386 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
387 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
388 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
389 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
390 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
391 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
392 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
393 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
394 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
395 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
396 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
397 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
398 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
399 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
400 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
401 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
402 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
403 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
404 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
405 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
406 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
407 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
408 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
409 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
410 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
411 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
412 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
413 kCLOCK_Dmic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19U), /*!< Clock gate name: Dmic. */
414 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22U), /*!< Clock gate name: Timer2. */
415 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25U), /*!< Clock gate name: Usbd0. */
416 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26U), /*!< Clock gate name: Timer0. */
417 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27U), /*!< Clock gate name: Timer1. */
418 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */
419
420 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1U), /*!< Clock gate name: Dma1. */
421 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2U), /*!< Clock gate name: Comp. */
422 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8U), /*!< Clock gate name: Freqme. */
423 kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11U), /*!< Clock gate name: Cdog. */
424 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13U), /*!< Clock gate name: Rng. */
425 kCLOCK_Pmux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14U), /*!< Clock gate name: Pmux1. */
426 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15U), /*!< Clock gate name: Sysctl. */
427 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16U), /*!< Clock gate name: Usbhmr0. */
428 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17U), /*!< Clock gate name: Usbhsl0. */
429 kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18U), /*!< Clock gate name: Css. */
430 kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19U), /*!< Clock gate name: PowerQuad. */
431 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21U), /*!< Clock gate name: Timer3. */
432 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22U), /*!< Clock gate name: Timer4. */
433 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23U), /*!< Clock gate name: Puf. */
434 kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24U), /*!< Clock gate name: Pkc. */
435 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27U), /*!< Clock gate name: AnalogCtrl. */
436 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28U), /*!< Clock gate name: Lspi. */
437 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29U), /*!< Clock gate name: Sec. */
438 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30U), /*!< Clock gate name: Int. */
439 kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0U), /*!< Clock gate name: I3c0. */
440 kCLOCK_Enc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3U), /*!< Clock gate name: Enc0. */
441 kCLOCK_Enc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4U), /*!< Clock gate name: Enc1. */
442 kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5U), /*!< Clock gate name: Pwm0. */
443 kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6U), /*!< Clock gate name: Pwm1. */
444 kCLOCK_Aoi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7U), /*!< Clock gate name: Aoi0. */
445 kCLOCK_Aoi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8U), /*!< Clock gate name: Aoi1. */
446 kCLOCK_Ftm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 9U), /*!< Clock gate name: Ftm0. */
447 kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 10U), /*!< Clock gate name: Dac1. */
448 kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11U), /*!< Clock gate name: Dac2. */
449 kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12U), /*!< Clock gate name: Opamp0. */
450 kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13U), /*!< Clock gate name: Opamp1. */
451 kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14U), /*!< Clock gate name: Opamp2. */
452 kCLOCK_Hscmp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15U), /*!< Clock gate name: Hscmp0. */
453 kCLOCK_Hscmp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 16U), /*!< Clock gate name: Hscmp1. */
454 kCLOCK_Hscmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 17U), /*!< Clock gate name: Hscmp2. */
455 kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18U), /*!< Clock gate name: Vref. */
456
457 kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 0U), /*!< Clock gate name: PWM0 SM0. */
458 kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 1U), /*!< Clock gate name: PWM0 SM1. */
459 kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 2U), /*!< Clock gate name: PWM0 SM2. */
460 kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 3U), /*!< Clock gate name: PWM0 SM3. */
461
462 kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 0U), /*!< Clock gate name: PWM1 SM0. */
463 kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 1U), /*!< Clock gate name: PWM1 SM1. */
464 kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 2U), /*!< Clock gate name: PWM1 SM2. */
465 kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 3U) /*!< Clock gate name: PWM1 SM3. */
466
467 } clock_ip_name_t;
468
469 /*! @brief Peripherals clock source definition. */
470 #define BUS_CLK kCLOCK_BusClk
471
472 #define I2C0_CLK_SRC BUS_CLK
473
474 /*! @brief Clock name used to get clock frequency. */
475 typedef enum _clock_name
476 {
477 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
478 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
479 kCLOCK_ClockOut, /*!< CLOCKOUT */
480 kCLOCK_FroHf, /*!< FRO48/96 */
481 kCLOCK_Pll1Out, /*!< PLL1 Output */
482 kCLOCK_Mclk, /*!< MCLK */
483 kCLOCK_Fro12M, /*!< FRO12M */
484 kCLOCK_Fro1M, /*!< FRO1M */
485 kCLOCK_ExtClk, /*!< External Clock */
486 kCLOCK_Pll0Out, /*!< PLL0 Output */
487 kCLOCK_PllClkDiv, /*!< PLLCLKDIV clock */
488 kCLOCK_FlexI2S, /*!< FlexI2S clock */
489 } clock_name_t;
490
491 /*! @brief Clock Mux Switches
492 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
493 * starting from LSB upwards
494 *
495 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
496 *
497 */
498
499 #define CLK_ATTACH_ID(mux, sel, pos) \
500 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U))
501 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
502 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
503
504 #define GET_ID_ITEM(connection) ((connection)&0xFFFFU)
505 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U)
506 #define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU)
507 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U))
508 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
509
510 #define CM_SYSTICKCLKSEL0 (0)
511 #define CM_TRACECLKSEL (2)
512 #define CM_CTIMERCLKSEL0 (3)
513 #define CM_CTIMERCLKSEL1 (4)
514 #define CM_CTIMERCLKSEL2 (5)
515 #define CM_CTIMERCLKSEL3 (6)
516 #define CM_CTIMERCLKSEL4 (7)
517 #define CM_MAINCLKSELA (8)
518 #define CM_MAINCLKSELB (9)
519 #define CM_CLKOUTCLKSEL (10)
520 #define CM_PLL0CLKSEL (12)
521 #define CM_PLL1CLKSEL (13)
522 #define CM_MCANCLKSEL (16)
523 #define CM_ADC0CLKSEL (17)
524 #define CM_USB0CLKSEL (18)
525 #define CM_FXCOMCLKSEL0 (20)
526 #define CM_FXCOMCLKSEL1 (21)
527 #define CM_FXCOMCLKSEL2 (22)
528 #define CM_FXCOMCLKSEL3 (23)
529 #define CM_FXCOMCLKSEL4 (24)
530 #define CM_FXCOMCLKSEL5 (25)
531 #define CM_FXCOMCLKSEL6 (26)
532 #define CM_FXCOMCLKSEL7 (27)
533 #define CM_HSLSPICLKSEL (28)
534 #define CM_MCLKCLKSEL (32)
535 #define CM_SCTCLKSEL (36)
536
537 #define CM_ADC1CLKSEL ((0x464 - 0x260) / 4)
538 #define CM_DAC0CLKSEL ((0x490 - 0x260) / 4)
539 #define CM_DAC1CLKSEL ((0x498 - 0x260) / 4)
540 #define CM_DAC2CLKSEL ((0x4A0 - 0x260) / 4)
541 #define CM_FLEXSPICLKSEL ((0x4A8 - 0x260) / 4)
542 #define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4)
543 #define CM_I3CFCLKSEL ((0x530 - 0x260) / 4)
544 #define CM_I3CFCLKSTCSEL ((0x534 - 0x260) / 4)
545 #define CM_I3CFCLKSSEL ((0x534 - 0x260) / 4)
546 #define CM_DMICFCLKSEL ((0x548 - 0x260) / 4)
547 #define CM_FC32KCLKSEL ((0x82C - 0x260) / 4)
548 #define CM_FRGCLKSEL0 ((0x830 - 0x260) / 4)
549 #define CM_FRGCLKSEL1 ((0x834 - 0x260) / 4)
550 #define CM_FRGCLKSEL2 ((0x838 - 0x260) / 4)
551 #define CM_FRGCLKSEL3 ((0x83C - 0x260) / 4)
552 #define CM_FRGCLKSEL4 ((0x840 - 0x260) / 4)
553 #define CM_FRGCLKSEL5 ((0x844 - 0x260) / 4)
554 #define CM_FRGCLKSEL6 ((0x848 - 0x260) / 4)
555 #define CM_FRGCLKSEL7 ((0x84C - 0x260) / 4)
556
557 #define CM_OSTIMERCLKSEL (252U)
558 #define CM_RTCOSC32KCLKSEL (253U)
559
560 /*!
561 * @brief The enumerator of clock attach Id.
562 */
563 typedef enum _clock_attach_id
564 {
565
566 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
567 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
568 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */
569 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
570 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */
571 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */
572 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
573
574 kSYSTICK_DIV_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV to SYSTICK0. */
575 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */
576 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */
577 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */
578
579 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */
580 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */
581 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */
582 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */
583
584 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */
585 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */
586 kPLL1_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1 to CTIMER0. */
587 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */
588 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */
589 kMCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
590 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */
591 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */
592
593 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */
594 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */
595 kPLL1_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1 to CTIMER1. */
596 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */
597 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */
598 kMCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK_IN to CTIMER1. */
599 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */
600 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */
601
602 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */
603 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */
604 kPLL1_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1 to CTIMER2. */
605 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */
606 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */
607 kMCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK_IN to CTIMER2. */
608 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */
609 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */
610
611 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */
612 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */
613 kPLL1_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1 to CTIMER3. */
614 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */
615 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */
616 kMCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK_IN to CTIMER3. */
617 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */
618 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */
619
620 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */
621 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */
622 kPLL1_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1 to CTIMER4. */
623 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */
624 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */
625 kMCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK_IN to CTIMER4. */
626 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */
627 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */
628
629 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */
630 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */
631 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */
632 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */
633 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */
634 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */
635 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */
636 kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to CLKOUT. */
637
638 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */
639 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */
640 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */
641 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */
642 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */
643
644 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */
645 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */
646 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */
647 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */
648 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */
649
650 kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */
651 kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */
652 kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */
653 kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */
654
655 kMAIN_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 0), /*!< Attach MAIN_CLK to ADC0. */
656 kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */
657 kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */
658 kEXT_CLK_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach XO to ADC0. */
659 kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */
660
661 kMAIN_CLK_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 0), /*!< Attach MAIN_CLK to ADC1. */
662 kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */
663 kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */
664 kEXT_CLK_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach XO to ADC1. */
665 kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */
666
667 kMAIN_CLK_to_USB0 = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0. */
668 kPLL0_to_USB0 = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0. */
669 kFRO_HF_to_USB0 = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0. */
670 kPLL1_to_USB0 = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0. */
671 kNONE_to_USB0 = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0. */
672
673 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */
674 kMAIN_CLK_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 0, 0), /*!< Attach Main clock
675 to FlexComm0. */
676 kPLL_CLK_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 1, 0), /*!< Attach PLL clock
677 DIV Frg to FlexComm0. */
678 kFRO_HF_DIV_FRG0_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1) | MUX_B(CM_FRGCLKSEL0, 2, 0), /*!< Attach FRO HF DIV
679 FRG to FlexComm0. */
680 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */
681 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */
682 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */
683 kMCLK_IN_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK_IN to FLEXCOMM0. */
684 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */
685 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
686
687 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */
688 kMAIN_CLK_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 0, 0), /*!< Attach Main clock
689 to FlexComm1. */
690 kPLL_CLK_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 1, 0), /*!< Attach PLL clock
691 DIV Frg to FlexComm1. */
692 kFRO_HF_DIV_FRG1_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1) | MUX_B(CM_FRGCLKSEL1, 2, 0), /*!< Attach FRO HF DIV
693 FRG to FlexComm1. */
694 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */
695 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */
696 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */
697 kMCLK_IN_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK_IN to FLEXCOMM1. */
698 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */
699 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
700
701 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */
702 kMAIN_CLK_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 0, 0), /*!< Attach Main clock
703 to FlexComm2. */
704 kPLL_CLK_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 1, 0), /*!< Attach PLL clock
705 DIV Frg to FlexComm2. */
706 kFRO_HF_DIV_FRG2_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1) | MUX_B(CM_FRGCLKSEL2, 2, 0), /*!< Attach FRO HF DIV
707 FRG to FlexComm2. */
708 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */
709 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */
710 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */
711 kMCLK_IN_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK_IN to FLEXCOMM2. */
712 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */
713 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
714
715 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */
716 kMAIN_CLK_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 0, 0), /*!< Attach Main clock
717 to FlexComm3. */
718 kPLL_CLK_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 1, 0), /*!< Attach PLL clock
719 DIV Frg to FlexComm3. */
720 kFRO_HF_DIV_FRG3_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1) | MUX_B(CM_FRGCLKSEL3, 2, 0), /*!< Attach FRO HF DIV
721 FRG to FlexComm3. */
722 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */
723 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */
724 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */
725 kMCLK_IN_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK_IN to FLEXCOMM3. */
726 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */
727 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
728
729 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */
730 kMAIN_CLK_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 0, 0), /*!< Attach Main clock
731 to FlexComm4. */
732 kPLL_CLK_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 1, 0), /*!< Attach PLL clock
733 DIV Frg to FlexComm4. */
734 kFRO_HF_DIV_FRG4_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1) | MUX_B(CM_FRGCLKSEL4, 2, 0), /*!< Attach FRO HF DIV
735 FRG to FlexComm4. */
736 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */
737 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */
738 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */
739 kMCLK_IN_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK_IN to FLEXCOMM4. */
740 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */
741 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
742
743 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */
744 kMAIN_CLK_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 0, 0), /*!< Attach Main clock
745 to FlexComm5. */
746 kPLL_CLK_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 1, 0), /*!< Attach PLL clock
747 DIV Frg to FlexComm5. */
748 kFRO_HF_DIV_FRG5_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1) | MUX_B(CM_FRGCLKSEL5, 2, 0), /*!< Attach FRO HF DIV
749 FRG to FlexComm5. */
750 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */
751 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */
752 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */
753 kMCLK_IN_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK_IN to FLEXCOMM5. */
754 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */
755 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
756
757 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */
758 kMAIN_CLK_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 0, 0), /*!< Attach Main clock
759 to FlexComm6. */
760 kPLL_CLK_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 1, 0), /*!< Attach PLL clock
761 DIV Frg to FlexComm6. */
762 kFRO_HF_DIV_FRG6_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1) | MUX_B(CM_FRGCLKSEL6, 2, 0), /*!< Attach FRO HF DIV
763 FRG to FlexComm6. */
764 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */
765 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */
766 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */
767 kMCLK_IN_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK_IN to FLEXCOMM6. */
768 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */
769 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
770
771 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */
772 kMAIN_CLK_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 0, 0), /*!< Attach Main clock
773 to FlexComm7. */
774 kPLL_CLK_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 1, 0), /*!< Attach PLL clock
775 DIV Frg to FlexComm7. */
776 kFRO_HF_DIV_FRG7_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1) | MUX_B(CM_FRGCLKSEL7, 2, 0), /*!< Attach PLL clock
777 DIV Frg to FlexComm7. */
778 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */
779 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */
780 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */
781 kMCLK_IN_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK_IN to FLEXCOMM7. */
782 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */
783 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
784
785 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */
786 kPLL_CLK_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL_CLK_DIV to HSLSPI. */
787 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */
788 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */
789 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */
790 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */
791 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */
792
793 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
794 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */
795 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
796
797 kMAIN_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT. */
798 kPLL0_to_SCT = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT. */
799 kEXT_CLK_to_SCT = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT. */
800 kFRO_HF_to_SCT = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT. */
801 kPLL1_to_SCT = MUX_A(CM_SCTCLKSEL, 4), /*!< Attach PLL1 to SCT. */
802 kMCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK_IN to SCT. */
803 kNONE_to_SCT = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT. */
804
805 kMAIN_CLK_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 0), /*!< Attach MAIN_CLK to DAC0. */
806 kPLL0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 1), /*!< Attach PLL0 to DAC0. */
807 kFRO_HF_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 3), /*!< Attach FRO_HF to DAC0. */
808 kFRO12M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 4), /*!< Attach FRO12M to DAC0. */
809 kPLL1_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 5), /*!< Attach PLL1 to DAC0. */
810 kFRO1M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 6), /*!< Attach FRO1M to DAC0. */
811 kNONE_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 7), /*!< Attach NONE to DAC0. */
812
813 kMAIN_CLK_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 0), /*!< Attach MAIN_CLK to DAC1. */
814 kPLL0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 1), /*!< Attach PLL0 to DAC1. */
815 kFRO_HF_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 3), /*!< Attach FRO_HF to DAC1. */
816 kFRO12M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 4), /*!< Attach FRO12M to DAC1. */
817 kPLL1_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 5), /*!< Attach PLL1 to DAC1. */
818 kFRO1M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 6), /*!< Attach FRO1M to DAC1. */
819 kNONE_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 7), /*!< Attach NONE to DAC1. */
820
821 kMAIN_CLK_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 0), /*!< Attach MAIN_CLK to DAC2. */
822 kPLL0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 1), /*!< Attach PLL0 to DAC2. */
823 kFRO_HF_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 3), /*!< Attach FRO_HF to DAC2. */
824 kFRO12M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 4), /*!< Attach FRO12M to DAC2. */
825 kPLL1_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 5), /*!< Attach PLL1 to DAC2. */
826 kFRO1M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 6), /*!< Attach FRO1M to DAC2. */
827 kNONE_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 7), /*!< Attach NONE to DAC2. */
828
829 kMAIN_CLK_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 0), /*!< Attach MAIN_CLK to FLEXSPI. */
830 kPLL0_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 1), /*!< Attach PLL0 to FLEXSPI. */
831 kFRO_HF_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 3), /*!< Attach FRO_HF to FLEXSPI. */
832 kPLL1_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 5), /*!< Attach PLL1 to FLEXSPI. */
833 kNONE_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 7), /*!< Attach NONE to FLEXSPI. */
834
835 kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */
836 kPLL1_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach PLL1 to PLLCLKDIV. */
837 kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 7), /*!< Attach NONE to PLLCLKDIV. */
838
839 kMAIN_CLK_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 0), /*!< Attach MAIN_CLK to I3CFCLK. */
840 kFRO_HF_DIV_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 1), /*!< Attach FRO_HF_DIV to I3CFCLK. */
841 kNONE_to_I3CFCLK = MUX_A(CM_I3CFCLKSEL, 7), /*!< Attach NONE to I3CFCLK. */
842
843 kI3CFCLKSEL_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 0), /*!< Attach I3CFCLKSEL to I3CFCLKSTC. */
844 kFRO1M_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 1), /*!< Attach FRO1M to I3CFCLKSTC. */
845 kNONE_to_I3CFCLKSTC = MUX_A(CM_I3CFCLKSTCSEL, 7), /*!< Attach NONE to I3CFCLKSTC. */
846
847 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 0), /*!< Attach MAIN_CLK to DMIC. */
848 kPLL0_to_DMIC = MUX_A(CM_DMICFCLKSEL, 1), /*!< Attach PLL0 to DMIC. */
849 kEXT_CLK_to_DMIC = MUX_A(CM_DMICFCLKSEL, 2), /*!< Attach EXT_CLK to DMIC. */
850 kFRO_HF_to_DMIC = MUX_A(CM_DMICFCLKSEL, 3), /*!< Attach FRO_HF to DMIC. */
851 kPLL1_to_DMIC = MUX_A(CM_DMICFCLKSEL, 4), /*!< Attach PLL1 to DMIC. */
852 kMCLK_IN_to_DMIC = MUX_A(CM_DMICFCLKSEL, 5), /*!< Attach MCLK_IN to DMIC. */
853 kNONE_to_DMIC = MUX_A(CM_DMICFCLKSEL, 7), /*!< Attach NONE to DMIC. */
854
855 kFRO32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 0), /*!< Attach FRO32K to FCOSC32K. */
856 kXTAL32K_to_FCOSC32K = MUX_A(CM_FC32KCLKSEL, 1), /*!< Attach XTAL32K to FCOSC32K. */
857 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */
858 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */
859 kFRO32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 0), /*!< Attach FRO32K to FC32K. */
860 kXTAL32K_to_FC32K = MUX_A(CM_FC32KCLKSEL, 1), /*!< Attach XTAL32K to FC32K. */
861
862 kFRO32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach FRO32K to OSTIMER. */
863 kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach OSC32K to OSTIMER. */
864 kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach FRO1M to OSTIMER. */
865 kAHB_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach AHB_CLK to OSTIMER. */
866
867 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
868
869 } clock_attach_id_t;
870
871 /*! @brief Clock dividers */
872 typedef enum _clock_div_name
873 {
874 kCLOCK_DivSystickClk = (0), /*!< Systick Clock Divider. */
875 kCLOCK_DivArmTrClkDiv = ((0x308 - 0x300) / 4), /*!< Trace Clock Divider. */
876 kCLOCK_DivCanClk = ((0x30C - 0x300) / 4), /*!< Can Clock Divider. */
877 kCLOCK_DivFlexFrg0 = ((0x320 - 0x300) / 4), /*!< FRGCTRL0 register. */
878 kCLOCK_DivFlexFrg1 = ((0x324 - 0x300) / 4), /*!< FRGCTRL1 register. */
879 kCLOCK_DivFlexFrg2 = ((0x328 - 0x300) / 4), /*!< FRGCTRL2 register. */
880 kCLOCK_DivFlexFrg3 = ((0x32C - 0x300) / 4), /*!< FRGCTRL3 register. */
881 kCLOCK_DivFlexFrg4 = ((0x330 - 0x300) / 4), /*!< FRGCTRL4 register. */
882 kCLOCK_DivFlexFrg5 = ((0x334 - 0x300) / 4), /*!< FRGCTRL5 register. */
883 kCLOCK_DivFlexFrg6 = ((0x338 - 0x300) / 4), /*!< FRGCTRL6 register. */
884 kCLOCK_DivFlexFrg7 = ((0x33C - 0x300) / 4), /*!< FRGCTRL7 register. */
885 kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clock Divider. */
886 kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< Clk Out Divider. */
887 kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Divider. */
888 kCLOCK_DivWdtClk = ((0x38C - 0x300) / 4), /*!< Wdt Clock Divider. */
889 kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clock Divider. */
890 kCLOCK_DivUsb0Clk = ((0x398 - 0x300) / 4), /*!< Usb0 Clock Divider. */
891 kCLOCK_DivMclk = ((0x3AC - 0x300) / 4), /*!< Mclk Divider. */
892 kCLOCK_DivSctClk = ((0x3B4 - 0x300) / 4), /*!< Sct Clock Divider. */
893 kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll0 Clock Divider. */
894 kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clock Divider. */
895 kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clock Divider. */
896 kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clock Divider. */
897 kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clock Divider. */
898 kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clock Divider. */
899 kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clock Divider. */
900 kCLOCK_DivDac0Clk = ((0x494 - 0x300) / 4), /*!< Dac0 Clock Divider. */
901 kCLOCK_DivDac1Clk = ((0x49C - 0x300) / 4), /*!< Dac1 Clock Divider. */
902 kCLOCK_DivDac2Clk = ((0x4A4 - 0x300) / 4), /*!< Dac2 Clock Divider. */
903 kCLOCK_DivFlexSpiClk = ((0x4AC - 0x300) / 4), /*!< Flex Spi Clock Divider. */
904 kCLOCK_DivI3cFclkStc = ((0x538 - 0x300) / 4), /*!< I3c Fclk Stc Divider. */
905 kCLOCK_DivI3cFclkS = ((0x53C - 0x300) / 4), /*!< I3c Fclk S Divider. */
906 kCLOCK_DivI3cFclk = ((0x540 - 0x300) / 4), /*!< I3c Fclk Divider. */
907 kCLOCK_DivDmicClk = ((0x54C - 0x300) / 4), /*!< Dmic Clock Divider. */
908 kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clock Divider. */
909 kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clock Divider. */
910 kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clock Divider. */
911 kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clock Divider. */
912 kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clock Divider. */
913 kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clock Divider. */
914 kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clock Divider. */
915 kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clock Divider. */
916 } clock_div_name_t;
917
918 /*******************************************************************************
919 * API
920 ******************************************************************************/
921
922 #if defined(__cplusplus)
923 extern "C" {
924 #endif /* __cplusplus */
925 /**
926 * @brief Enable the clock for specific IP.
927 * @param clk : Clock to be enabled.
928 * @return Nothing
929 */
CLOCK_EnableClock(clock_ip_name_t clk)930 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
931 {
932 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
933 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk);
934
935 if (index == (uint32_t)REG_PWM0SUBCTL)
936 {
937 SYSCON->PWM0SUBCTL |= (1UL << bit);
938 SYSCON->AHBCLKCTRLSET[3] = 0x20U;
939 }
940 else if (index == (uint32_t)REG_PWM1SUBCTL)
941 {
942 SYSCON->PWM1SUBCTL |= (1UL << bit);
943 SYSCON->AHBCLKCTRLSET[3] = 0x40U;
944 }
945 else
946 {
947 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit);
948 }
949 }
950 /**
951 * @brief Disable the clock for specific IP.
952 * @param clk : Clock to be Disabled.
953 * @return Nothing
954 */
CLOCK_DisableClock(clock_ip_name_t clk)955 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
956 {
957 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
958 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk);
959
960 if (index == (uint32_t)REG_PWM0SUBCTL)
961 {
962 SYSCON->PWM0SUBCTL &= ~(1UL << bit);
963 if (0U == (SYSCON->PWM0SUBCTL & 0xFU))
964 {
965 SYSCON->AHBCLKCTRLCLR[3] = 0x20U;
966 }
967 }
968 else if (index == (uint32_t)REG_PWM1SUBCTL)
969 {
970 SYSCON->PWM1SUBCTL &= ~(1UL << bit);
971 if (0U == (SYSCON->PWM1SUBCTL & 0xFU))
972 {
973 SYSCON->AHBCLKCTRLCLR[3] = 0x40U;
974 }
975 }
976 else
977 {
978 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit);
979 }
980 }
981 /**
982 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
983 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
984 * enabled.
985 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
986 * @return returns success or fail status.
987 */
988 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
989 /**
990 * @brief Set the flash wait states for the input freuqency.
991 * @param system_freq_hz: Input frequency
992 * @return Nothing
993 */
994 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz);
995 /**
996 * @brief Initialize the external osc clock to given frequency.
997 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
998 * @return returns success or fail status.
999 */
1000 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
1001 /**
1002 * @brief Initialize the I2S MCLK clock to given frequency.
1003 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
1004 * @return returns success or fail status.
1005 */
1006 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
1007 /**
1008 * @brief Configure the clock selection muxes.
1009 * @param connection : Clock to be configured.
1010 * @return Nothing
1011 */
1012 void CLOCK_AttachClk(clock_attach_id_t connection);
1013 /**
1014 * @brief Get the actual clock attach id.
1015 * This fuction uses the offset in input attach id, then it reads the actual source value in
1016 * the register and combine the offset to obtain an actual attach id.
1017 * @param attachId : Clock attach id to get.
1018 * @return Clock source value.
1019 */
1020 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
1021 /**
1022 * @brief Setup peripheral clock dividers.
1023 * @param div_name : Clock divider name
1024 * @param divided_by_value: Value to be divided
1025 * @param reset : Whether to reset the divider counter.
1026 * @return Nothing
1027 */
1028 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
1029 /*! @brief Return Frequency of selected clock
1030 * @return Frequency of selected clock
1031 */
1032 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1033 /*! @brief Return Frequency of FRO 12MHz
1034 * @return Frequency of FRO 12MHz
1035 */
1036 uint32_t CLOCK_GetFro12MFreq(void);
1037 /*! @brief Return Frequency of FRO 1MHz
1038 * @return Frequency of FRO 1MHz
1039 */
1040 uint32_t CLOCK_GetFro1MFreq(void);
1041 /*! @brief Return Frequency of ClockOut
1042 * @return Frequency of ClockOut
1043 */
1044 uint32_t CLOCK_GetClockOutClkFreq(void);
1045 /*! @brief Return Frequency of Can Clock
1046 * @return Frequency of Can.
1047 */
1048 uint32_t CLOCK_GetMCanClkFreq(void);
1049 /*! @brief Return Frequency of Adc Clock
1050 * @return Frequency of Adc.
1051 */
1052 uint32_t CLOCK_GetAdcClkFreq(uint32_t id);
1053 /*! @brief Return Frequency of Usb0 Clock
1054 * @return Frequency of Usb0 Clock.
1055 */
1056 uint32_t CLOCK_GetUsb0ClkFreq(void);
1057 /*! @brief Return Frequency of MClk Clock
1058 * @return Frequency of MClk Clock.
1059 */
1060 uint32_t CLOCK_GetMclkClkFreq(void);
1061 /*! @brief Return Frequency of SCTimer Clock
1062 * @return Frequency of SCTimer Clock.
1063 */
1064 uint32_t CLOCK_GetSctClkFreq(void);
1065 /*! @brief Return Frequency of External Clock
1066 * @return Frequency of External Clock. If no external clock is used returns 0.
1067 */
1068 uint32_t CLOCK_GetExtClkFreq(void);
1069 /*! @brief Return Frequency of Watchdog
1070 * @return Frequency of Watchdog
1071 */
1072 uint32_t CLOCK_GetWdtClkFreq(void);
1073 /*! @brief Return Frequency of High-Freq output of FRO
1074 * @return Frequency of High-Freq output of FRO
1075 */
1076 uint32_t CLOCK_GetFroHfFreq(void);
1077 /*! @brief Return Frequency of PLL
1078 * @return Frequency of PLL
1079 */
1080 uint32_t CLOCK_GetPll0OutFreq(void);
1081 /*! @brief Return Frequency of USB PLL
1082 * @return Frequency of PLL
1083 */
1084 uint32_t CLOCK_GetPll1OutFreq(void);
1085 /*! @brief Return Frequency of PLL_CLK_DIV
1086 * @return Frequency of PLL_CLK_DIV
1087 */
1088 uint32_t CLOCK_GetPllClkDivFreq(void);
1089 /*! @brief Return Frequency of 32kHz osc
1090 * @return Frequency of 32kHz osc
1091 */
1092 uint32_t CLOCK_GetOsc32KFreq(void);
1093 /*! @brief Return Frequency of Flexcomm 32kHz osc
1094 * @return Frequency of Flexcomm 32kHz osc
1095 */
1096 uint32_t CLOCK_GetFC32KFreq(void);
1097 /*! @brief Return Frequency of Core System
1098 * @return Frequency of Core System
1099 */
1100 uint32_t CLOCK_GetCoreSysClkFreq(void);
1101 /*! @brief Return Frequency of I2S MCLK Clock
1102 * @return Frequency of I2S MCLK Clock
1103 */
1104 uint32_t CLOCK_GetI2SMClkFreq(void);
1105 /*! @brief Return Frequency of FRG Clock
1106 * @return Frequency of FRG Clock
1107 */
1108 uint32_t CLOCK_GetFrgFreq(uint32_t id);
1109 /*! @brief Return Frequency of FlexComm Clock
1110 * @return Frequency of FlexComm Clock
1111 */
1112 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1113 /*! @brief Return Frequency of High speed SPI Clock
1114 * @return Frequency of High speed SPI Clock
1115 */
1116 uint32_t CLOCK_GetHsLspiClkFreq(void);
1117 /*! @brief Return Frequency of CTimer functional Clock
1118 * @return Frequency of CTimer functional Clock
1119 */
1120 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
1121 /*! @brief Return Frequency of SystickClock
1122 * @return Frequency of Systick Clock
1123 */
1124 uint32_t CLOCK_GetSystickClkFreq(void);
1125
1126 /*! @brief Return Frequency of FlexSPI
1127 * @return Frequency of FlexSPI Clock
1128 */
1129 uint32_t CLOCK_GetFlexSpiClkFreq(void);
1130
1131 /*! @brief Return Frequency of DMIC
1132 * @return Frequency of DMIC Clock
1133 */
1134 uint32_t CLOCK_GetDmicClkFreq(void);
1135
1136 /*! @brief Return Frequency of DAC Clock
1137 * @return Frequency of DAC Clock
1138 */
1139 uint32_t CLOCK_GetDacClkFreq(uint32_t id);
1140 /*! @brief Return Frequency of I3C function slow TC Clock
1141 * @return Frequency of I3C function slow TC Clock
1142 */
1143 uint32_t CLOCK_GetI3cSTCClkFreq(void);
1144 /*! @brief Return Frequency of I3C function slow Clock
1145 * @return Frequency of I3C function slow Clock
1146 */
1147 uint32_t CLOCK_GetI3cSClkFreq(void);
1148 /*! @brief Return Frequency of I3C function Clock
1149 * @return Frequency of I3C function Clock
1150 */
1151 uint32_t CLOCK_GetI3cClkFreq(void);
1152
1153 /*! @brief Return PLL0 input clock rate
1154 * @return PLL0 input clock rate
1155 */
1156 uint32_t CLOCK_GetPLL0InClockRate(void);
1157
1158 /*! @brief Return PLL1 input clock rate
1159 * @return PLL1 input clock rate
1160 */
1161 uint32_t CLOCK_GetPLL1InClockRate(void);
1162
1163 /*! @brief Return PLL0 output clock rate
1164 * @param recompute : Forces a PLL rate recomputation if true
1165 * @return PLL0 output clock rate
1166 * @note The PLL rate is cached in the driver in a variable as
1167 * the rate computation function can take some time to perform. It
1168 * is recommended to use 'false' with the 'recompute' parameter.
1169 */
1170 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
1171
1172 /*! @brief Return PLL1 output clock rate
1173 * @param recompute : Forces a PLL rate recomputation if true
1174 * @return PLL1 output clock rate
1175 * @note The PLL rate is cached in the driver in a variable as
1176 * the rate computation function can take some time to perform. It
1177 * is recommended to use 'false' with the 'recompute' parameter.
1178 */
1179 uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);
1180
1181 /*! @brief Enables and disables PLL0 bypass mode
1182 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
1183 * @return PLL0 output clock rate
1184 */
CLOCK_SetBypassPLL0(bool bypass)1185 __STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
1186 {
1187 if (bypass)
1188 {
1189 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1190 }
1191 else
1192 {
1193 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1194 }
1195 }
1196
1197 /*! @brief Enables and disables PLL1 bypass mode
1198 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
1199 * @return PLL1 output clock rate
1200 */
CLOCK_SetBypassPLL1(bool bypass)1201 __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
1202 {
1203 if (bypass)
1204 {
1205 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1206 }
1207 else
1208 {
1209 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1210 }
1211 }
1212
1213 /*! @brief Check if PLL is locked or not
1214 * @return true if the PLL is locked, false if not locked
1215 */
CLOCK_IsPLL0Locked(void)1216 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
1217 {
1218 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
1219 }
1220
1221 /*! @brief Check if PLL1 is locked or not
1222 * @return true if the PLL1 is locked, false if not locked
1223 */
CLOCK_IsPLL1Locked(void)1224 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
1225 {
1226 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
1227 }
1228
1229 /*! @brief Store the current PLL0 rate
1230 * @param rate: Current rate of the PLL0
1231 * @return Nothing
1232 **/
1233 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
1234
1235 /*! @brief PLL configuration structure flags for 'flags' field
1236 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1237 *
1238 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1239 * configuration structure must be assigned with the expected PLL frequency. If the
1240 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1241 * function and the driver will determine the PLL rate from the currently selected
1242 * PLL source. This flag might be used to configure the PLL input clock more accurately
1243 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1244 *
1245 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1246 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1247 * are not used.<br>
1248 */
1249 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1250 #define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1251 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1252
1253 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1254 * See (MF) field in the PLL0SSCG1 register in the UM.
1255 */
1256 typedef enum _ss_progmodfm
1257 {
1258 kSS_MF_512 = (0U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1259 kSS_MF_384 = (1U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1260 kSS_MF_256 = (2U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1261 kSS_MF_128 = (3U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1262 kSS_MF_64 = (4U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1263 kSS_MF_32 = (5U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1264 kSS_MF_24 = (6U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1265 kSS_MF_16 = (7U << SYSCON_PLL0SSCG1_MF_SHIFT) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1266 } ss_progmodfm_t;
1267
1268 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1269 * See (MR) field in the PLL0SSCG1 register in the UM.
1270 */
1271 typedef enum _ss_progmoddp
1272 {
1273 kSS_MR_K0 = (0U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 0 (no spread spectrum) */
1274 kSS_MR_K1 = (1U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1 */
1275 kSS_MR_K1_5 = (2U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1.5 */
1276 kSS_MR_K2 = (3U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 2 */
1277 kSS_MR_K3 = (4U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 3 */
1278 kSS_MR_K4 = (5U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 4 */
1279 kSS_MR_K6 = (6U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 6 */
1280 kSS_MR_K8 = (7U << SYSCON_PLL0SSCG1_MR_SHIFT) /*!< k = 8 */
1281 } ss_progmoddp_t;
1282
1283 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1284 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1285 * Compensation for low pass filtering of the PLL to get a triangular
1286 * modulation at the output of the PLL, giving a flat frequency spectrum.
1287 */
1288 typedef enum _ss_modwvctrl
1289 {
1290 kSS_MC_NOC = (0U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< no compensation */
1291 kSS_MC_RECC = (2U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< recommended setting */
1292 kSS_MC_MAXC = (3U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< max. compensation */
1293 } ss_modwvctrl_t;
1294
1295 /*! @brief PLL configuration structure
1296 *
1297 * This structure can be used to configure the settings for a PLL
1298 * setup structure. Fill in the desired configuration for the PLL
1299 * and call the PLL setup function to fill in a PLL setup structure.
1300 */
1301 typedef struct _pll_config
1302 {
1303 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1304 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1305 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1306 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1307 PLL_CONFIGFLAG_FORCENOFRACT flag */
1308 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1309 PLL_CONFIGFLAG_FORCENOFRACT flag */
1310 ss_modwvctrl_t
1311 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1312 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1313 PLL_CONFIGFLAG_FORCENOFRACT flag */
1314
1315 } pll_config_t;
1316
1317 /*! @brief PLL setup structure flags for 'flags' field
1318 * These flags control how the PLL setup function sets up the PLL
1319 */
1320 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1321 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1322 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1323 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1324
1325 /*! @brief PLL0 setup structure
1326 * This structure can be used to pre-build a PLL setup configuration
1327 * at run-time and quickly set the PLL to the configuration. It can be
1328 * populated with the PLL setup function. If powering up or waiting
1329 * for PLL lock, the PLL input clock source should be configured prior
1330 * to PLL setup.
1331 */
1332 typedef struct _pll_setup
1333 {
1334 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1335 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1336 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1337 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1338 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1339 uint32_t pllRate; /*!< Acutal PLL rate */
1340 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1341 } pll_setup_t;
1342
1343 /*! @brief PLL status definitions
1344 */
1345 typedef enum _pll_error
1346 {
1347 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1348 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1349 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1350 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1351 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1352 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1353 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1354 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1355 } pll_error_t;
1356
1357 /*! @brief USB FS clock source definition. */
1358 typedef enum _clock_usbfs_src
1359 {
1360 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
1361 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
1362 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1363 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
1364
1365 kCLOCK_UsbfsSrcNone =
1366 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
1367 } clock_usbfs_src_t;
1368
1369 /*! @brief Source of the USB HS PHY. */
1370 typedef enum _clock_usb_phy_src
1371 {
1372 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
1373 } clock_usb_phy_src_t;
1374
1375 /*! @brief Return PLL0 output clock rate from setup structure
1376 * @param pSetup : Pointer to a PLL setup structure
1377 * @return System PLL output clock rate the setup structure will generate
1378 */
1379 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1380
1381 /*! @brief Return PLL1 output clock rate from setup structure
1382 * @param pSetup : Pointer to a PLL setup structure
1383 * @return PLL0 output clock rate the setup structure will generate
1384 */
1385 uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup);
1386
1387 /*! @brief Set PLL0 output based on the passed PLL setup data
1388 * @param pControl : Pointer to populated PLL control structure to generate setup with
1389 * @param pSetup : Pointer to PLL setup structure to be filled
1390 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1391 * @note Actual frequency for setup may vary from the desired frequency based on the
1392 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1393 */
1394 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1395
1396 /*! @brief Set PLL output from PLL setup structure (precise frequency)
1397 * @param pSetup : Pointer to populated PLL setup structure
1398 * @param flagcfg : Flag configuration for PLL config structure
1399 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1400 * @note This function will power off the PLL, setup the PLL with the
1401 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1402 * and adjust system voltages to the new PLL rate. The function will not
1403 * alter any source clocks (ie, main systen clock) that may use the PLL,
1404 * so these should be setup prior to and after exiting the function.
1405 */
1406 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1407
1408 /**
1409 * @brief Set PLL output from PLL setup structure (precise frequency)
1410 * @param pSetup : Pointer to populated PLL setup structure
1411 * @return kStatus_PLL_Success on success, or PLL setup error code
1412 * @note This function will power off the PLL, setup the PLL with the
1413 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1414 * and adjust system voltages to the new PLL rate. The function will not
1415 * alter any source clocks (ie, main systen clock) that may use the PLL,
1416 * so these should be setup prior to and after exiting the function.
1417 */
1418 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1419
1420 /**
1421 * @brief Set PLL output from PLL setup structure (precise frequency)
1422 * @param pSetup : Pointer to populated PLL setup structure
1423 * @return kStatus_PLL_Success on success, or PLL setup error code
1424 * @note This function will power off the PLL, setup the PLL with the
1425 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1426 * and adjust system voltages to the new PLL rate. The function will not
1427 * alter any source clocks (ie, main systen clock) that may use the PLL,
1428 * so these should be setup prior to and after exiting the function.
1429 */
1430 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1431
1432 /*! @brief Set PLL0 output based on the multiplier and input frequency
1433 * @param multiply_by : multiplier
1434 * @param input_freq : Clock input frequency of the PLL
1435 * @return Nothing
1436 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1437 * function does not disable or enable PLL power, wait for PLL lock,
1438 * or adjust system voltages. These must be done in the application.
1439 * The function will not alter any source clocks (ie, main systen clock)
1440 * that may use the PLL, so these should be setup prior to and after
1441 * exiting the function.
1442 */
1443 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1444
1445 /*! @brief Disable USB clock.
1446 *
1447 * Disable USB clock.
1448 */
CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)1449 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1450 {
1451 CLOCK_DisableClock(clk);
1452 }
1453
1454 /*! @brief Enable USB Device FS clock.
1455 * @param src : clock source
1456 * @param freq: clock frequency
1457 * Enable USB Device Full Speed clock.
1458 */
1459 bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
1460
1461 /*! @brief Enable USB HOST FS clock.
1462 * @param src : clock source
1463 * @param freq: clock frequency
1464 * Enable USB HOST Full Speed clock.
1465 */
1466 bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
1467
1468 /*! @brief Enable the OSTIMER 32k clock.
1469 * @return Nothing
1470 */
1471 void CLOCK_EnableOstimer32kClock(void);
1472
1473 /**
1474 * @brief Sets board-specific trim values for High Frequency crystal oscillator
1475 * @param pi32_hfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
1476 * @param pi32_hfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
1477 * becomes 120
1478 * @param pi32_hfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
1479 * becomes 120
1480 * @return none
1481 * @note Following default Values can be used:
1482 * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
1483 * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20
1484 * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
1485 */
1486 void CLOCK_XtalHfCapabankTrim(int32_t pi32_hfXtalIecLoadpF_x100,
1487 int32_t pi32_hfXtalPPcbParCappF_x100,
1488 int32_t pi32_hfXtalNPcbParCappF_x100);
1489 /**
1490 * @brief Sets board-specific trim values for 32kHz XTAL
1491 * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
1492 * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
1493 becomes 120
1494 * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
1495 becomes 120
1496
1497 * @return none
1498 * @note Following default Values can be used:
1499 * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
1500 * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40
1501 * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
1502 */
1503 void CLOCK_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
1504 int32_t pi32_32kfXtalPPcbParCappF_x100,
1505 int32_t pi32_32kfXtalNPcbParCappF_x100);
1506
1507 /**
1508 * @brief Initialize the trim value for FRO HF
1509 * @return none
1510 */
1511 void CLOCK_FroHfTrim(void);
1512
1513 #if defined(__cplusplus)
1514 }
1515 #endif /* __cplusplus */
1516
1517 /*! @} */
1518
1519 #endif /* _FSL_CLOCK_H_ */
1520
