1 /*
2 * Copyright 2017 - 2021 , NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.6. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6))
26 /*@}*/
27
28 /*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40 #endif
41
42 /*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51 #endif
52
53 /* Definition for delay API in clock driver, users can redefine it to the real application. */
54 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL)
56 #endif
57
58 /*! @brief Clock ip name array for ROM. */
59 #define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63 /*! @brief Clock ip name array for SRAM. */
64 #define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2 \
67 }
68 /*! @brief Clock ip name array for FLASH. */
69 #define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73 /*! @brief Clock ip name array for FMC. */
74 #define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78 /*! @brief Clock ip name array for INPUTMUX. */
79 #define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux0 \
82 }
83 /*! @brief Clock ip name array for IOCON. */
84 #define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88 /*! @brief Clock ip name array for GPIO. */
89 #define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1 \
92 }
93 /*! @brief Clock ip name array for PINT. */
94 #define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98 /*! @brief Clock ip name array for GINT. */
99 #define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103 /*! @brief Clock ip name array for DMA. */
104 #define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108 /*! @brief Clock ip name array for CRC. */
109 #define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc \
112 }
113 /*! @brief Clock ip name array for WWDT. */
114 #define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118 /*! @brief Clock ip name array for RTC. */
119 #define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc \
122 }
123 /*! @brief Clock ip name array for Mailbox. */
124 #define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128 /*! @brief Clock ip name array for LPADC. */
129 #define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0 \
132 }
133 /*! @brief Clock ip name array for MRT. */
134 #define MRT_CLOCKS \
135 { \
136 kCLOCK_Mrt \
137 }
138 /*! @brief Clock ip name array for OSTIMER. */
139 #define OSTIMER_CLOCKS \
140 { \
141 kCLOCK_OsTimer0 \
142 }
143 /*! @brief Clock ip name array for SCT0. */
144 #define SCT_CLOCKS \
145 { \
146 kCLOCK_Sct0 \
147 }
148 /*! @brief Clock ip name array for MCAN. */
149 #define MCAN_CLOCKS \
150 { \
151 kCLOCK_Mcan \
152 }
153 /*! @brief Clock ip name array for UTICK. */
154 #define UTICK_CLOCKS \
155 { \
156 kCLOCK_Utick0 \
157 }
158 /*! @brief Clock ip name array for FLEXCOMM. */
159 #define FLEXCOMM_CLOCKS \
160 { \
161 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
162 kCLOCK_FlexComm6, kCLOCK_Hs_Lspi \
163 }
164 /*! @brief Clock ip name array for LPUART. */
165 #define LPUART_CLOCKS \
166 { \
167 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
168 kCLOCK_MinUart6 \
169 }
170
171 /*! @brief Clock ip name array for BI2C. */
172 #define BI2C_CLOCKS \
173 { \
174 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6 \
175 }
176 /*! @brief Clock ip name array for LSPI. */
177 #define LPSPI_CLOCKS \
178 { \
179 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6 \
180 }
181 /*! @brief Clock ip name array for FLEXI2S. */
182 #define FLEXI2S_CLOCKS \
183 { \
184 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
185 kCLOCK_FlexI2s6 \
186 }
187 /*! @brief Clock ip name array for CTIMER. */
188 #define CTIMER_CLOCKS \
189 { \
190 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
191 }
192 /*! @brief Clock ip name array for COMP */
193 #define COMP_CLOCKS \
194 { \
195 kCLOCK_Comp \
196 }
197 /*! @brief Clock ip name array for FREQME. */
198 #define FREQME_CLOCKS \
199 { \
200 kCLOCK_Freqme \
201 }
202 /*! @brief Clock ip name array for CDOG. */
203 #define CDOG_CLOCKS \
204 { \
205 kCLOCK_Cdog \
206 }
207 /*! @brief Clock ip name array for RNG. */
208 #define RNG_CLOCKS \
209 { \
210 kCLOCK_Rng \
211 }
212 /*! @brief Clock ip name array for HashCrypt. */
213 #define HASHCRYPT_CLOCKS \
214 { \
215 kCLOCK_HashCrypt \
216 }
217 /*! @brief Clock ip name array for PLULUT. */
218 #define PLULUT_CLOCKS \
219 { \
220 kCLOCK_PluLut \
221 }
222 /*! @brief Clock ip name array for PUF. */
223 #define PUF_CLOCKS \
224 { \
225 kCLOCK_Puf \
226 }
227 /*! @brief Clock ip name array for CASPER. */
228 #define CASPER_CLOCKS \
229 { \
230 kCLOCK_Casper \
231 }
232 /*! @brief Clock ip name array for ANALOGCTRL. */
233 #define ANALOGCTRL_CLOCKS \
234 { \
235 kCLOCK_AnalogCtrl \
236 }
237 /*! @brief Clock ip name array for HS_LSPI. */
238 #define HS_LSPI_CLOCKS \
239 { \
240 kCLOCK_Hs_Lspi \
241 }
242 /*! @brief Clock ip name array for GPIO_SEC. */
243 #define GPIO_SEC_CLOCKS \
244 { \
245 kCLOCK_Gpio_Sec \
246 }
247 /*! @brief Clock ip name array for GPIO_SEC_INT. */
248 #define GPIO_SEC_INT_CLOCKS \
249 { \
250 kCLOCK_Gpio_Sec_Int \
251 }
252 #define PLU_CLOCKS \
253 { \
254 kCLOCK_PluLut \
255 }
256 #define SYSCTL_CLOCKS \
257 { \
258 kCLOCK_Sysctl \
259 }
260 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
261 /*------------------------------------------------------------------------------
262 clock_ip_name_t definition:
263 ------------------------------------------------------------------------------*/
264
265 #define CLK_GATE_REG_OFFSET_SHIFT 8U
266 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
267 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
268 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
269
270 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
271 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
272 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
273
274 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
275 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
276
277 #define AHB_CLK_CTRL0 0
278 #define AHB_CLK_CTRL1 1
279 #define AHB_CLK_CTRL2 2
280
281 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
282 typedef enum _clock_ip_name
283 {
284 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
285 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
286
287 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */
288
289 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */
290
291 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */
292
293 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */
294
295 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
296
297 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
298
299 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
300
301 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
302
303 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
304
305 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */
306
307 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */
308
309 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
310
311 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
312
313 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
314
315 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */
316
317 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
318
319 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
320
321 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */
322
323 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
324
325 kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan. */
326
327 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */
328
329 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
330
331 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
332
333 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
334
335 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
336
337 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
338
339 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
340
341 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
342
343 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
344
345 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
346
347 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
348
349 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
350
351 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
352
353 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
354
355 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
356
357 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
358
359 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
360
361 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
362
363 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
364
365 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
366
367 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
368
369 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
370
371 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
372
373 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
374
375 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
376
377 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
378
379 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
380
381 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
382
383 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
384
385 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
386
387 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
388
389 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
390
391 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
392
393 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
394
395 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
396
397 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
398
399 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */
400
401 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */
402
403 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */
404
405 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */
406
407 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */
408
409 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sram3. */
410
411 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */
412
413 kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Cdog. */
414
415 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */
416
417 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */
418
419 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */
420
421 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */
422
423 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */
424
425 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */
426
427 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */
428
429 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */
430
431 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */
432
433 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */
434
435 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Sec. */
436
437 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */
438 } clock_ip_name_t;
439
440 /*! @brief Peripherals clock source definition. */
441 #define BUS_CLK kCLOCK_BusClk
442
443 #define I2C0_CLK_SRC BUS_CLK
444
445 /*! @brief Clock name used to get clock frequency. */
446 typedef enum _clock_name
447 {
448 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
449 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
450 kCLOCK_ClockOut, /*!< CLOCKOUT */
451 kCLOCK_FroHf, /*!< FRO48/96 */
452 kCLOCK_Pll1Out, /*!< PLL1 Output */
453 kCLOCK_Mclk, /*!< MCLK */
454 kCLOCK_Fro12M, /*!< FRO12M */
455 kCLOCK_Fro1M, /*!< FRO1M */
456 kCLOCK_ExtClk, /*!< External Clock */
457 kCLOCK_Pll0Out, /*!< PLL0 Output */
458 kCLOCK_FlexI2S, /*!< FlexI2S clock */
459
460 } clock_name_t;
461
462 /*! @brief Clock Mux Switches
463 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
464 * starting from LSB upwards
465 *
466 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
467 *
468 */
469
470 #define CLK_ATTACH_ID(mux, sel, pos) \
471 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
472 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
473 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
474
475 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
476 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
477 #define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
478 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
479 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
480
481 #define CM_SYSTICKCLKSEL0 0
482 #define CM_TRACECLKSEL 2
483 #define CM_CTIMERCLKSEL0 3
484 #define CM_CTIMERCLKSEL1 4
485 #define CM_CTIMERCLKSEL2 5
486 #define CM_CTIMERCLKSEL3 6
487 #define CM_CTIMERCLKSEL4 7
488 #define CM_MAINCLKSELA 8
489 #define CM_MAINCLKSELB 9
490 #define CM_CLKOUTCLKSEL 10
491 #define CM_PLL0CLKSEL 12
492 #define CM_PLL1CLKSEL 13
493 #define CM_MCANCLKSEL 16
494 #define CM_ADCASYNCCLKSEL 17
495 #define CM_CLK32KCLKSEL 19
496 #define CM_FXCOMCLKSEL0 20
497 #define CM_FXCOMCLKSEL1 21
498 #define CM_FXCOMCLKSEL2 22
499 #define CM_FXCOMCLKSEL3 23
500 #define CM_FXCOMCLKSEL4 24
501 #define CM_FXCOMCLKSEL5 25
502 #define CM_FXCOMCLKSEL6 26
503 #define CM_HSLSPICLKSEL 28
504 #define CM_MCLKCLKSEL 32
505 #define CM_SCTCLKSEL 36
506
507 #define CM_OSTIMERCLKSEL (62U)
508 #define CM_RTCOSC32KCLKSEL 63U
509
510 /*!
511 * @brief The enumerator of clock attach Id.
512 */
513 typedef enum _clock_attach_id
514 {
515
516 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
517
518 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
519
520 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */
521
522 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
523
524 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */
525
526 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */
527
528 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
529
530 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */
531
532 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */
533
534 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */
535
536 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */
537
538 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */
539
540 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */
541
542 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */
543
544 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */
545
546 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */
547
548 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */
549
550 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */
551
552 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */
553
554 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */
555
556 kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */
557
558 kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */
559
560 kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */
561
562 kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */
563
564 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */
565
566 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */
567
568 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */
569
570 kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4), /*!< Attach EXT_CLK to ADC_CLK. */
571
572 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
573
574 kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0), /*!< Attach OSC32K to CLK32K. */
575
576 kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1), /*!< Attach FRO1MDIV to CLK32K. */
577
578 kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7), /*!< Attach NONE to CLK32K. */
579
580 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */
581
582 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */
583
584 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */
585
586 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */
587
588 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */
589
590 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */
591
592 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */
593
594 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
595
596 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */
597
598 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */
599
600 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */
601
602 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */
603
604 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */
605
606 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */
607
608 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */
609
610 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
611
612 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */
613
614 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */
615
616 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */
617
618 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */
619
620 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */
621
622 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */
623
624 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */
625
626 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
627
628 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */
629
630 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */
631
632 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */
633
634 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */
635
636 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */
637
638 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */
639
640 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */
641
642 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
643
644 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */
645
646 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */
647
648 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */
649
650 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */
651
652 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */
653
654 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */
655
656 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */
657
658 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
659
660 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */
661
662 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */
663
664 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */
665
666 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */
667
668 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */
669
670 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */
671
672 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */
673
674 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
675
676 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */
677
678 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */
679
680 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */
681
682 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */
683
684 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */
685
686 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */
687
688 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */
689
690 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
691
692 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */
693
694 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */
695
696 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */
697
698 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */
699
700 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */
701
702 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */
703
704 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */
705
706 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
707
708 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */
709
710 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
711
712 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
713
714 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */
715
716 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */
717
718 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */
719
720 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */
721
722 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */
723
724 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */
725
726 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */
727
728 kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach OSC32K to OSTIMER. */
729
730 kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach FRO1M to OSTIMER. */
731
732 kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach MAIN_CLK to OSTIMER. */
733
734 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */
735
736 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */
737
738 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */
739
740 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */
741
742 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */
743
744 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */
745
746 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */
747
748 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */
749
750 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */
751
752 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */
753
754 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */
755
756 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */
757
758 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */
759
760 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */
761
762 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */
763
764 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */
765
766 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */
767
768 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */
769
770 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */
771
772 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */
773
774 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */
775
776 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */
777
778 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */
779
780 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */
781
782 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */
783
784 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */
785
786 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */
787
788 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */
789
790 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */
791
792 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */
793
794 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */
795
796 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */
797
798 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */
799
800 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */
801
802 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */
803
804 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */
805
806 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */
807
808 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */
809
810 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */
811
812 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */
813
814 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */
815
816 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */
817
818 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */
819
820 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */
821
822 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */
823
824 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */
825
826 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */
827
828 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */
829
830 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
831
832 } clock_attach_id_t;
833
834 /*! @brief Clock dividers */
835 typedef enum _clock_div_name
836 {
837 kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */
838
839 kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */
840
841 kCLOCK_DivCanClk = 3, /*!< Can Clock Divider. */
842
843 kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */
844
845 kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */
846
847 kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */
848
849 kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */
850
851 kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */
852
853 kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */
854
855 kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */
856
857 kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */
858
859 kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */
860
861 kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */
862
863 kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */
864
865 kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */
866
867 kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */
868
869 kCLOCK_DivFro1mClk = 40, /*!< Fro1m Clock Divider. */
870
871 kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */
872
873 kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */
874
875 kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */
876 } clock_div_name_t;
877
878 /*******************************************************************************
879 * API
880 ******************************************************************************/
881
882 #if defined(__cplusplus)
883 extern "C" {
884 #endif /* __cplusplus */
885
886 /**
887 * @brief Enable the clock for specific IP.
888 * @param clk : Clock to be enabled.
889 * @return Nothing
890 */
CLOCK_EnableClock(clock_ip_name_t clk)891 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
892 {
893 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
894 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
895 }
896 /**
897 * @brief Disable the clock for specific IP.
898 * @param clk : Clock to be Disabled.
899 * @return Nothing
900 */
CLOCK_DisableClock(clock_ip_name_t clk)901 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
902 {
903 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
904 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
905 }
906 /**
907 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
908 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
909 * enabled.
910 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
911 * @return returns success or fail status.
912 */
913 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
914 /**
915 * @brief Set the flash wait states for the input freuqency.
916 * @param system_freq_hz : Input frequency
917 * @return Nothing
918 */
919 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz);
920 /**
921 * @brief Initialize the external osc clock to given frequency.
922 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
923 * @return returns success or fail status.
924 */
925 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
926 /**
927 * @brief Initialize the I2S MCLK clock to given frequency.
928 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
929 * @return returns success or fail status.
930 */
931 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
932 /**
933 * @brief Initialize the PLU CLKIN clock to given frequency.
934 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
935 * @return returns success or fail status.
936 */
937 status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
938 /**
939 * @brief Configure the clock selection muxes.
940 * @param connection : Clock to be configured.
941 * @return Nothing
942 */
943 void CLOCK_AttachClk(clock_attach_id_t connection);
944 /**
945 * @brief Get the actual clock attach id.
946 * This fuction uses the offset in input attach id, then it reads the actual source value in
947 * the register and combine the offset to obtain an actual attach id.
948 * @param attachId : Clock attach id to get.
949 * @return Clock source value.
950 */
951 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
952 /**
953 * @brief Setup peripheral clock dividers.
954 * @param div_name : Clock divider name
955 * @param divided_by_value: Value to be divided
956 * @param reset : Whether to reset the divider counter.
957 * @return Nothing
958 */
959 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
960 /**
961 * @brief Setup rtc 1khz clock divider.
962 * @param divided_by_value: Value to be divided
963 * @return Nothing
964 */
965 void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
966 /**
967 * @brief Setup rtc 1hz clock divider.
968 * @param divided_by_value: Value to be divided
969 * @return Nothing
970 */
971 void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
972
973 /**
974 * @brief Set the flexcomm output frequency.
975 * @param id : flexcomm instance id
976 * @param freq : output frequency
977 * @return 0 : the frequency range is out of range.
978 * 1 : switch successfully.
979 */
980 uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
981
982 /*! @brief Return Frequency of flexcomm input clock
983 * @param id : flexcomm instance id
984 * @return Frequency value
985 */
986 uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
987
988 /*! @brief Return Frequency of selected clock
989 * @return Frequency of selected clock
990 */
991 uint32_t CLOCK_GetFreq(clock_name_t clockName);
992 /*! @brief Return Frequency of FRO 12MHz
993 * @return Frequency of FRO 12MHz
994 */
995 uint32_t CLOCK_GetFro12MFreq(void);
996 /*! @brief Return Frequency of FRO 1MHz
997 * @return Frequency of FRO 1MHz
998 */
999 uint32_t CLOCK_GetFro1MFreq(void);
1000 /*! @brief Return Frequency of ClockOut
1001 * @return Frequency of ClockOut
1002 */
1003 uint32_t CLOCK_GetClockOutClkFreq(void);
1004 /*! @brief Return Frequency of Can Clock
1005 * @return Frequency of Can.
1006 */
1007 uint32_t CLOCK_GetMCanClkFreq(void);
1008 /*! @brief Return Frequency of Adc Clock
1009 * @return Frequency of Adc.
1010 */
1011 uint32_t CLOCK_GetAdcClkFreq(void);
1012 /*! @brief Return Frequency of MClk Clock
1013 * @return Frequency of MClk Clock.
1014 */
1015 uint32_t CLOCK_GetMclkClkFreq(void);
1016 /*! @brief Return Frequency of SCTimer Clock
1017 * @return Frequency of SCTimer Clock.
1018 */
1019 uint32_t CLOCK_GetSctClkFreq(void);
1020 /*! @brief Return Frequency of External Clock
1021 * @return Frequency of External Clock. If no external clock is used returns 0.
1022 */
1023 uint32_t CLOCK_GetExtClkFreq(void);
1024 /*! @brief Return Frequency of Watchdog
1025 * @return Frequency of Watchdog
1026 */
1027 uint32_t CLOCK_GetWdtClkFreq(void);
1028 /*! @brief Return Frequency of High-Freq output of FRO
1029 * @return Frequency of High-Freq output of FRO
1030 */
1031 uint32_t CLOCK_GetFroHfFreq(void);
1032 /*! @brief Return Frequency of PLL
1033 * @return Frequency of PLL
1034 */
1035 uint32_t CLOCK_GetPll0OutFreq(void);
1036 /*! @brief Return Frequency of USB PLL
1037 * @return Frequency of PLL
1038 */
1039 uint32_t CLOCK_GetPll1OutFreq(void);
1040 /*! @brief Return Frequency of 32kHz osc
1041 * @return Frequency of 32kHz osc
1042 */
1043 uint32_t CLOCK_GetOsc32KFreq(void);
1044 /*! @brief Return Frequency of Core System
1045 * @return Frequency of Core System
1046 */
1047 uint32_t CLOCK_GetCoreSysClkFreq(void);
1048 /*! @brief Return Frequency of I2S MCLK Clock
1049 * @return Frequency of I2S MCLK Clock
1050 */
1051 uint32_t CLOCK_GetI2SMClkFreq(void);
1052 /*! @brief Return Frequency of PLU CLKIN Clock
1053 * @return Frequency of PLU CLKIN Clock
1054 */
1055 uint32_t CLOCK_GetPLUClkInFreq(void);
1056 /*! @brief Return Frequency of FlexComm Clock
1057 * @return Frequency of FlexComm Clock
1058 */
1059 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1060 /*! @brief Return Frequency of High speed SPI Clock
1061 * @return Frequency of High speed SPI Clock
1062 */
1063 uint32_t CLOCK_GetHsLspiClkFreq(void);
1064 /*! @brief Return Frequency of CTimer functional Clock
1065 * @return Frequency of CTimer functional Clock
1066 */
1067 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
1068 /*! @brief Return Frequency of SystickClock
1069 * @return Frequency of Systick Clock
1070 */
1071 uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
1072
1073 /*! @brief Return PLL0 input clock rate
1074 * @return PLL0 input clock rate
1075 */
1076 uint32_t CLOCK_GetPLL0InClockRate(void);
1077
1078 /*! @brief Return PLL1 input clock rate
1079 * @return PLL1 input clock rate
1080 */
1081 uint32_t CLOCK_GetPLL1InClockRate(void);
1082
1083 /*! @brief Return PLL0 output clock rate
1084 * @param recompute : Forces a PLL rate recomputation if true
1085 * @return PLL0 output clock rate
1086 * @note The PLL rate is cached in the driver in a variable as
1087 * the rate computation function can take some time to perform. It
1088 * is recommended to use 'false' with the 'recompute' parameter.
1089 */
1090 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
1091
1092 /*! @brief Return PLL1 output clock rate
1093 * @param recompute : Forces a PLL rate recomputation if true
1094 * @return PLL1 output clock rate
1095 * @note The PLL rate is cached in the driver in a variable as
1096 * the rate computation function can take some time to perform. It
1097 * is recommended to use 'false' with the 'recompute' parameter.
1098 */
1099 uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);
1100
1101 /*! @brief Enables and disables PLL0 bypass mode
1102 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
1103 * @return PLL0 output clock rate
1104 */
CLOCK_SetBypassPLL0(bool bypass)1105 __STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
1106 {
1107 if (bypass)
1108 {
1109 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1110 }
1111 else
1112 {
1113 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1114 }
1115 }
1116
1117 /*! @brief Enables and disables PLL1 bypass mode
1118 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
1119 * @return PLL1 output clock rate
1120 */
CLOCK_SetBypassPLL1(bool bypass)1121 __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
1122 {
1123 if (bypass)
1124 {
1125 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1126 }
1127 else
1128 {
1129 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1130 }
1131 }
1132
1133 /*! @brief Check if PLL is locked or not
1134 * @return true if the PLL is locked, false if not locked
1135 */
CLOCK_IsPLL0Locked(void)1136 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
1137 {
1138 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
1139 }
1140
1141 /*! @brief Check if PLL1 is locked or not
1142 * @return true if the PLL1 is locked, false if not locked
1143 */
CLOCK_IsPLL1Locked(void)1144 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
1145 {
1146 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
1147 }
1148
1149 /*! @brief Store the current PLL0 rate
1150 * @param rate: Current rate of the PLL0
1151 * @return Nothing
1152 **/
1153 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
1154
1155 /*! @brief PLL configuration structure flags for 'flags' field
1156 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1157 *
1158 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1159 * configuration structure must be assigned with the expected PLL frequency. If the
1160 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1161 * function and the driver will determine the PLL rate from the currently selected
1162 * PLL source. This flag might be used to configure the PLL input clock more accurately
1163 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1164 *
1165 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1166 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1167 * are not used.<br>
1168 */
1169 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1170 #define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1171 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1172
1173 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1174 * See (MF) field in the PLL0SSCG1 register in the UM.
1175 */
1176 typedef enum _ss_progmodfm
1177 {
1178 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1179 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1180 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1181 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1182 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1183 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1184 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1185 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1186 } ss_progmodfm_t;
1187
1188 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1189 * See (MR) field in the PLL0SSCG1 register in the UM.
1190 */
1191 typedef enum _ss_progmoddp
1192 {
1193 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
1194 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
1195 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
1196 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
1197 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
1198 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
1199 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
1200 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
1201 } ss_progmoddp_t;
1202
1203 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1204 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1205 * Compensation for low pass filtering of the PLL to get a triangular
1206 * modulation at the output of the PLL, giving a flat frequency spectrum.
1207 */
1208 typedef enum _ss_modwvctrl
1209 {
1210 kSS_MC_NOC = (0 << 26), /*!< no compensation */
1211 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
1212 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
1213 } ss_modwvctrl_t;
1214
1215 /*! @brief PLL configuration structure
1216 *
1217 * This structure can be used to configure the settings for a PLL
1218 * setup structure. Fill in the desired configuration for the PLL
1219 * and call the PLL setup function to fill in a PLL setup structure.
1220 */
1221 typedef struct _pll_config
1222 {
1223 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1224 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1225 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1226 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1227 PLL_CONFIGFLAG_FORCENOFRACT flag */
1228 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1229 PLL_CONFIGFLAG_FORCENOFRACT flag */
1230 ss_modwvctrl_t
1231 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1232 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1233 PLL_CONFIGFLAG_FORCENOFRACT flag */
1234
1235 } pll_config_t;
1236
1237 /*! @brief PLL setup structure flags for 'flags' field
1238 * These flags control how the PLL setup function sets up the PLL
1239 */
1240 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1241 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1242 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1243 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1244
1245 /*! @brief PLL0 setup structure
1246 * This structure can be used to pre-build a PLL setup configuration
1247 * at run-time and quickly set the PLL to the configuration. It can be
1248 * populated with the PLL setup function. If powering up or waiting
1249 * for PLL lock, the PLL input clock source should be configured prior
1250 * to PLL setup.
1251 */
1252 typedef struct _pll_setup
1253 {
1254 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1255 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1256 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1257 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1258 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1259 uint32_t pllRate; /*!< Acutal PLL rate */
1260 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1261 } pll_setup_t;
1262
1263 /*! @brief PLL status definitions
1264 */
1265 typedef enum _pll_error
1266 {
1267 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1268 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1269 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1270 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1271 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1272 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1273 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1274 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1275 } pll_error_t;
1276
1277 /*! @brief Return PLL0 output clock rate from setup structure
1278 * @param pSetup : Pointer to a PLL setup structure
1279 * @return System PLL output clock rate the setup structure will generate
1280 */
1281 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1282
1283 /*! @brief Return PLL1 output clock rate from setup structure
1284 * @param pSetup : Pointer to a PLL setup structure
1285 * @return PLL0 output clock rate the setup structure will generate
1286 */
1287 uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup);
1288
1289 /*! @brief Set PLL0 output based on the passed PLL setup data
1290 * @param pControl : Pointer to populated PLL control structure to generate setup with
1291 * @param pSetup : Pointer to PLL setup structure to be filled
1292 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1293 * @note Actual frequency for setup may vary from the desired frequency based on the
1294 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1295 */
1296 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1297
1298 /*! @brief Set PLL output from PLL setup structure (precise frequency)
1299 * @param pSetup : Pointer to populated PLL setup structure
1300 * @param flagcfg : Flag configuration for PLL config structure
1301 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1302 * @note This function will power off the PLL, setup the PLL with the
1303 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1304 * and adjust system voltages to the new PLL rate. The function will not
1305 * alter any source clocks (ie, main systen clock) that may use the PLL,
1306 * so these should be setup prior to and after exiting the function.
1307 */
1308 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1309
1310 /**
1311 * @brief Set PLL output from PLL setup structure (precise frequency)
1312 * @param pSetup : Pointer to populated PLL setup structure
1313 * @return kStatus_PLL_Success on success, or PLL setup error code
1314 * @note This function will power off the PLL, setup the PLL with the
1315 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1316 * and adjust system voltages to the new PLL rate. The function will not
1317 * alter any source clocks (ie, main systen clock) that may use the PLL,
1318 * so these should be setup prior to and after exiting the function.
1319 */
1320 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1321
1322 /**
1323 * @brief Set PLL output from PLL setup structure (precise frequency)
1324 * @param pSetup : Pointer to populated PLL setup structure
1325 * @return kStatus_PLL_Success on success, or PLL setup error code
1326 * @note This function will power off the PLL, setup the PLL with the
1327 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1328 * and adjust system voltages to the new PLL rate. The function will not
1329 * alter any source clocks (ie, main systen clock) that may use the PLL,
1330 * so these should be setup prior to and after exiting the function.
1331 */
1332 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1333
1334 /*! @brief Set PLL0 output based on the multiplier and input frequency
1335 * @param multiply_by : multiplier
1336 * @param input_freq : Clock input frequency of the PLL
1337 * @return Nothing
1338 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1339 * function does not disable or enable PLL power, wait for PLL lock,
1340 * or adjust system voltages. These must be done in the application.
1341 * The function will not alter any source clocks (ie, main systen clock)
1342 * that may use the PLL, so these should be setup prior to and after
1343 * exiting the function.
1344 */
1345 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1346
1347 /*! @brief Enable the OSTIMER 32k clock.
1348 * @return Nothing
1349 */
1350 void CLOCK_EnableOstimer32kClock(void);
1351
1352 #if defined(__cplusplus)
1353 }
1354 #endif /* __cplusplus */
1355
1356 /*! @} */
1357
1358 #endif /* _FSL_CLOCK_H_ */
1359
