1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, 2021 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #ifndef _FSL_CLOCK_H_
11 #define _FSL_CLOCK_H_
12
13 #include "fsl_common.h"
14
15 /*! @addtogroup clock */
16 /*! @{ */
17
18 /*! @file */
19
20 /*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief CLOCK driver version 2.5.2. */
27 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
28 /*@}*/
29
30 /*! @brief Configure whether driver controls clock
31 *
32 * When set to 0, peripheral drivers will enable clock in initialize function
33 * and disable clock in de-initialize function. When set to 1, peripheral
34 * driver will not control the clock, application could control the clock out of
35 * the driver.
36 *
37 * @note All drivers share this feature switcher. If it is set to 1, application
38 * should handle clock enable and disable for all drivers.
39 */
40 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
41 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
42 #endif
43
44 /*!
45 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
46 *
47 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
48 * would cache the recent calulation and accelerate the execution to get the
49 * right settings.
50 */
51 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
52 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
53 #endif
54
55 /*! @brief FROHF clock setting API address in ROM. */
56 #define CLOCK_FROHF_SETTING_API_ROM_ADDRESS (0x030091DFU)
57
58 /* Definition for delay API in clock driver, users can redefine it to the real application. */
59 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
60 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
61 #endif
62
63 /**
64 * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
65 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
66 * output is enabled.
67 * Usage: set_fro_frequency(frequency), (frequency must be one of 12, 48 or 96 MHz)
68 */
69
70 #define set_fro_frequency(iFreq) (*((void (*)(uint32_t iFreq))(CLOCK_FROHF_SETTING_API_ROM_ADDRESS)))(iFreq)
71
72 /*! @brief Clock ip name array for ROM. */
73 #define ADC_CLOCKS \
74 { \
75 kCLOCK_Adc0 \
76 }
77 /*! @brief Clock ip name array for ROM. */
78 #define ROM_CLOCKS \
79 { \
80 kCLOCK_Rom \
81 }
82 /*! @brief Clock ip name array for SRAM. */
83 #define SRAM_CLOCKS \
84 { \
85 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
86 }
87 /*! @brief Clock ip name array for FLASH. */
88 #define FLASH_CLOCKS \
89 { \
90 kCLOCK_Flash \
91 }
92 /*! @brief Clock ip name array for FMC. */
93 #define FMC_CLOCKS \
94 { \
95 kCLOCK_Fmc \
96 }
97 /*! @brief Clock ip name array for EEPROM. */
98 #define EEPROM_CLOCKS \
99 { \
100 kCLOCK_Eeprom \
101 }
102 /*! @brief Clock ip name array for SPIFI. */
103 #define SPIFI_CLOCKS \
104 { \
105 kCLOCK_Spifi \
106 }
107 /*! @brief Clock ip name array for INPUTMUX. */
108 #define INPUTMUX_CLOCKS \
109 { \
110 kCLOCK_InputMux \
111 }
112 /*! @brief Clock ip name array for IOCON. */
113 #define IOCON_CLOCKS \
114 { \
115 kCLOCK_Iocon \
116 }
117 /*! @brief Clock ip name array for GPIO. */
118 #define GPIO_CLOCKS \
119 { \
120 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
121 }
122 /*! @brief Clock ip name array for PINT. */
123 #define PINT_CLOCKS \
124 { \
125 kCLOCK_Pint \
126 }
127 /*! @brief Clock ip name array for GINT. */
128 #define GINT_CLOCKS \
129 { \
130 kCLOCK_Gint, kCLOCK_Gint \
131 }
132 /*! @brief Clock ip name array for DMA. */
133 #define DMA_CLOCKS \
134 { \
135 kCLOCK_Dma \
136 }
137 /*! @brief Clock ip name array for CRC. */
138 #define CRC_CLOCKS \
139 { \
140 kCLOCK_Crc \
141 }
142 /*! @brief Clock ip name array for WWDT. */
143 #define WWDT_CLOCKS \
144 { \
145 kCLOCK_Wwdt \
146 }
147 /*! @brief Clock ip name array for RTC. */
148 #define RTC_CLOCKS \
149 { \
150 kCLOCK_Rtc \
151 }
152 /*! @brief Clock ip name array for ADC0. */
153 #define ADC0_CLOCKS \
154 { \
155 kCLOCK_Adc0 \
156 }
157 /*! @brief Clock ip name array for MRT. */
158 #define MRT_CLOCKS \
159 { \
160 kCLOCK_Mrt \
161 }
162 /*! @brief Clock ip name array for RIT. */
163 #define RIT_CLOCKS \
164 { \
165 kCLOCK_Rit \
166 }
167 /*! @brief Clock ip name array for SCT0. */
168 #define SCT_CLOCKS \
169 { \
170 kCLOCK_Sct0 \
171 }
172 /*! @brief Clock ip name array for MCAN. */
173 #define MCAN_CLOCKS \
174 { \
175 kCLOCK_Mcan0, kCLOCK_Mcan1 \
176 }
177 /*! @brief Clock ip name array for UTICK. */
178 #define UTICK_CLOCKS \
179 { \
180 kCLOCK_Utick \
181 }
182 /*! @brief Clock ip name array for FLEXCOMM. */
183 #define FLEXCOMM_CLOCKS \
184 { \
185 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
186 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9 \
187 }
188 /*! @brief Clock ip name array for LPUART. */
189 #define LPUART_CLOCKS \
190 { \
191 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
192 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
193 }
194
195 /*! @brief Clock ip name array for BI2C. */
196 #define BI2C_CLOCKS \
197 { \
198 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
199 kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
200 }
201 /*! @brief Clock ip name array for LSPI. */
202 #define LPSI_CLOCKS \
203 { \
204 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
205 kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
206 }
207 /*! @brief Clock ip name array for FLEXI2S. */
208 #define FLEXI2S_CLOCKS \
209 { \
210 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
211 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
212 }
213 /*! @brief Clock ip name array for DMIC. */
214 #define DMIC_CLOCKS \
215 { \
216 kCLOCK_DMic \
217 }
218 /*! @brief Clock ip name array for CT32B. */
219 #define CTIMER_CLOCKS \
220 { \
221 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
222 }
223 /*! @brief Clock ip name array for LCD. */
224 #define LCD_CLOCKS \
225 { \
226 kCLOCK_Lcd \
227 }
228 /*! @brief Clock ip name array for SDIO. */
229 #define SDIO_CLOCKS \
230 { \
231 kCLOCK_Sdio \
232 }
233 /*! @brief Clock ip name array for USBRAM. */
234 #define USBRAM_CLOCKS \
235 { \
236 kCLOCK_UsbRam1 \
237 }
238 /*! @brief Clock ip name array for EMC. */
239 #define EMC_CLOCKS \
240 { \
241 kCLOCK_Emc \
242 }
243 /*! @brief Clock ip name array for ETH. */
244 #define ETH_CLOCKS \
245 { \
246 kCLOCK_Eth \
247 }
248 /*! @brief Clock ip name array for AES. */
249 #define AES_CLOCKS \
250 { \
251 kCLOCK_Aes \
252 }
253 /*! @brief Clock ip name array for OTP. */
254 #define OTP_CLOCKS \
255 { \
256 kCLOCK_Otp \
257 }
258 /*! @brief Clock ip name array for RNG. */
259 #define RNG_CLOCKS \
260 { \
261 kCLOCK_Rng \
262 }
263 /*! @brief Clock ip name array for USBHMR0. */
264 #define USBHMR0_CLOCKS \
265 { \
266 kCLOCK_Usbhmr0 \
267 }
268 /*! @brief Clock ip name array for USBHSL0. */
269 #define USBHSL0_CLOCKS \
270 { \
271 kCLOCK_Usbhsl0 \
272 }
273 /*! @brief Clock ip name array for SHA0. */
274 #define SHA0_CLOCKS \
275 { \
276 kCLOCK_Sha0 \
277 }
278 /*! @brief Clock ip name array for SMARTCARD. */
279 #define SMARTCARD_CLOCKS \
280 { \
281 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
282 }
283 /*! @brief Clock ip name array for USBD. */
284 #define USBD_CLOCKS \
285 { \
286 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
287 }
288 /*! @brief Clock ip name array for USBH. */
289 #define USBH_CLOCKS \
290 { \
291 kCLOCK_Usbh1 \
292 }
293 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
294 /*------------------------------------------------------------------------------
295 clock_ip_name_t definition:
296 ------------------------------------------------------------------------------*/
297
298 #define CLK_GATE_REG_OFFSET_SHIFT 8U
299 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
300 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
301 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
302
303 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
304 ((((uint32_t)(reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
305 (((uint32_t)(bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
306
307 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
308 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
309
310 #define AHB_CLK_CTRL0 0U
311 #define AHB_CLK_CTRL1 1U
312 #define AHB_CLK_CTRL2 2U
313 #define ASYNC_CLK_CTRL0 3U
314
315 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
316 typedef enum _clock_ip_name
317 {
318 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
320
321 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */
322
323 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */
324
325 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */
326
327 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */
328
329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */
330
331 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Eeprom. */
332
333 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Spifi. */
334
335 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
336
337 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
338
339 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
340
341 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
342
343 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */
344
345 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */
346
347 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
348
349 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */
350
351 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma. */
352
353 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
354
355 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
356
357 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
358
359 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
360
361 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
362
363 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: Rit. */
364
365 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
366
367 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan0. */
368
369 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), /*!< Clock gate name: Mcan1. */
370
371 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */
372
373 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
374
375 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
376
377 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
378
379 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
380
381 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
382
383 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
384
385 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
386
387 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */
388
389 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
390
391 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
392
393 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
394
395 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
396
397 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
398
399 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
400
401 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
402
403 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
404
405 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
406
407 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
408
409 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
410
411 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
412
413 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
414
415 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
416
417 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
418
419 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
420
421 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
422
423 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
424
425 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
426
427 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
428
429 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
430
431 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
432
433 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
434
435 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
436
437 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
438
439 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
440
441 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
442
443 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
444
445 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
446
447 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
448
449 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
450
451 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
452
453 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: DMic. */
454
455 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Ct32b2. */
456
457 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */
458
459 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Ct32b0. */
460
461 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Ct32b1. */
462
463 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: BodyBias0. */
464
465 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: EzhArchB0. */
466
467 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Lcd. */
468
469 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */
470
471 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */
472
473 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */
474
475 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */
476
477 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Emc. */
478
479 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Eth. */
480
481 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), /*!< Clock gate name: Gpio4. */
482
483 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), /*!< Clock gate name: Gpio5. */
484
485 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Aes. */
486
487 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), /*!< Clock gate name: Otp. */
488
489 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */
490
491 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: FlexComm8. */
492
493 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: FlexComm9. */
494
495 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: MinUart8. */
496
497 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: MinUart9. */
498
499 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: LSpi8. */
500
501 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: LSpi9. */
502
503 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: BI2c8. */
504
505 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: BI2c9. */
506
507 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: FlexI2s8. */
508
509 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: FlexI2s9. */
510
511 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */
512
513 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */
514
515 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Sha0. */
516
517 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: SmartCard0. */
518
519 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: SmartCard1. */
520
521 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), /*!< Clock gate name: Ct32b3. */
522
523 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) /*!< Clock gate name: Ct32b4. */
524 } clock_ip_name_t;
525
526 /*! @brief Clock name used to get clock frequency. */
527 typedef enum _clock_name
528 {
529 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
530 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
531 kCLOCK_ClockOut, /*!< CLOCKOUT */
532 kCLOCK_FroHf, /*!< FRO48/96 */
533 kCLOCK_UsbPll, /*!< USB1 PLL */
534 kCLOCK_Mclk, /*!< MCLK */
535 kCLOCK_Fro12M, /*!< FRO12M */
536 kCLOCK_ExtClk, /*!< External Clock */
537 kCLOCK_PllOut, /*!< PLL Output */
538 kCLOCK_UsbClk, /*!< USB input */
539 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
540 kCLOCK_Frg, /*!< Frg Clock */
541 kCLOCK_AsyncApbClk, /*!< Async APB clock */
542 kCLOCK_FlexI2S, /*!< FlexI2S clock */
543 } clock_name_t;
544
545 /**
546 * @brief Clock source selections for the asynchronous APB clock
547 */
548 typedef enum _async_clock_src
549 {
550 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
551 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
552 kCLOCK_AsyncAudioPllClk, /*!< Async Audio PLL clock. */
553 kCLOCK_AsyncI2cClkFc6, /*!< Async I2C clock. */
554
555 } async_clock_src_t;
556
557 /*! @brief Clock Mux Switches
558 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
559 * starting from LSB upwards
560 *
561 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
562 *
563 */
564
565 #define CLK_ATTACH_ID(mux, sel, pos) \
566 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
567 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
568 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
569
570 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
571 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
572 #define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
573 #define GET_ID_ITEM_SEL(connection) (uint8_t)(((((connection)&0xF00U) >> 8U) - 1U))
574 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
575
576 #define CM_MAINCLKSELA 0
577 #define CM_MAINCLKSELB 1
578 #define CM_CLKOUTCLKSELA 2
579 #define CM_SYSPLLCLKSEL 4
580 #define CM_AUDPLLCLKSEL 6
581 #define CM_SPIFICLKSEL 8
582 #define CM_ADCASYNCCLKSEL 9
583 #define CM_USB0CLKSEL 10
584 #define CM_USB1CLKSEL 11
585 #define CM_FXCOMCLKSEL0 12
586 #define CM_FXCOMCLKSEL1 13
587 #define CM_FXCOMCLKSEL2 14
588 #define CM_FXCOMCLKSEL3 15
589 #define CM_FXCOMCLKSEL4 16
590 #define CM_FXCOMCLKSEL5 17
591 #define CM_FXCOMCLKSEL6 18
592 #define CM_FXCOMCLKSEL7 19
593 #define CM_FXCOMCLKSEL8 20
594 #define CM_FXCOMCLKSEL9 21
595 #define CM_MCLKCLKSEL 24
596 #define CM_FRGCLKSEL 26
597 #define CM_DMICCLKSEL 27
598 #define CM_SCTCLKSEL 28
599 #define CM_LCDCLKSEL 29
600 #define CM_SDIOCLKSEL 30
601
602 #define CM_ASYNCAPB 31U
603
604 /*!
605 * @brief The enumerator of clock attach Id.
606 */
607 typedef enum _clock_attach_id
608 {
609
610 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
611
612 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
613
614 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach WDT_OSC to MAIN_CLK. */
615
616 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
617
618 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach SYS_PLL to MAIN_CLK. */
619
620 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
621
622 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), /*!< Attach MAIN_CLK to CLKOUT. */
623
624 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), /*!< Attach EXT_CLK to CLKOUT. */
625
626 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), /*!< Attach WDT_OSC to CLKOUT. */
627
628 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), /*!< Attach FRO_HF to CLKOUT. */
629
630 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), /*!< Attach SYS_PLL to CLKOUT. */
631
632 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), /*!< Attach USB_PLL to CLKOUT. */
633
634 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), /*!< Attach AUDIO_PLL to CLKOUT. */
635
636 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), /*!< Attach OSC32K_OSC to CLKOUT. */
637
638 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), /*!< Attach FRO12M to SYS_PLL. */
639
640 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), /*!< Attach EXT_CLK to SYS_PLL. */
641
642 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), /*!< Attach WDT_OSC to SYS_PLL. */
643
644 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), /*!< Attach OSC32K to SYS_PLL. */
645
646 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), /*!< Attach NONE to SYS_PLL. */
647
648 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), /*!< Attach FRO12M to AUDIO_PLL. */
649
650 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1), /*!< Attach EXT_CLK to AUDIO_PLL. */
651
652 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), /*!< Attach NONE to AUDIO_PLL. */
653
654 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), /*!< Attach MAIN_CLK to SPIFI_CLK. */
655
656 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), /*!< Attach SYS_PLL to SPIFI_CLK. */
657
658 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), /*!< Attach USB_PLL to SPIFI_CLK. */
659
660 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), /*!< Attach FRO_HF to SPIFI_CLK. */
661
662 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4), /*!< Attach AUDIO_PLL to SPIFI_CLK. */
663
664 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), /*!< Attach NONE to SPIFI_CLK. */
665
666 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach FRO_HF to ADC_CLK. */
667
668 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach SYS_PLL to ADC_CLK. */
669
670 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach USB_PLL to ADC_CLK. */
671
672 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /*!< Attach AUDIO_PLL to ADC_CLK. */
673
674 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
675
676 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach FRO_HF to USB0_CLK. */
677
678 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach SYS_PLL to USB0_CLK. */
679
680 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2), /*!< Attach USB_PLL to USB0_CLK. */
681
682 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */
683
684 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), /*!< Attach FRO_HF to USB1_CLK. */
685
686 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1), /*!< Attach SYS_PLL to USB1_CLK. */
687
688 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2), /*!< Attach USB_PLL to USB1_CLK. */
689
690 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), /*!< Attach NONE to USB1_CLK. */
691
692 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach FRO12M to FLEXCOMM0. */
693
694 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach FRO_HF to FLEXCOMM0. */
695
696 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach AUDIO_PLL to FLEXCOMM0. */
697
698 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach MCLK to FLEXCOMM0. */
699
700 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRG to FLEXCOMM0. */
701
702 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
703
704 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach FRO12M to FLEXCOMM1. */
705
706 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach FRO_HF to FLEXCOMM1. */
707
708 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach AUDIO_PLL to FLEXCOMM1. */
709
710 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach MCLK to FLEXCOMM1. */
711
712 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRG to FLEXCOMM1. */
713
714 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
715
716 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach FRO12M to FLEXCOMM2. */
717
718 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach FRO_HF to FLEXCOMM2. */
719
720 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach AUDIO_PLL to FLEXCOMM2. */
721
722 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach MCLK to FLEXCOMM2. */
723
724 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRG to FLEXCOMM2. */
725
726 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
727
728 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach FRO12M to FLEXCOMM3. */
729
730 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach FRO_HF to FLEXCOMM3. */
731
732 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach AUDIO_PLL to FLEXCOMM3. */
733
734 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach MCLK to FLEXCOMM3. */
735
736 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRG to FLEXCOMM3. */
737
738 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
739
740 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach FRO12M to FLEXCOMM4. */
741
742 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach FRO_HF to FLEXCOMM4. */
743
744 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach AUDIO_PLL to FLEXCOMM4. */
745
746 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach MCLK to FLEXCOMM4. */
747
748 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRG to FLEXCOMM4. */
749
750 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
751
752 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach FRO12M to FLEXCOMM5. */
753
754 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach FRO_HF to FLEXCOMM5. */
755
756 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach AUDIO_PLL to FLEXCOMM5. */
757
758 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach MCLK to FLEXCOMM5. */
759
760 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRG to FLEXCOMM5. */
761
762 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
763
764 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach FRO12M to FLEXCOMM6. */
765
766 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach FRO_HF to FLEXCOMM6. */
767
768 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach AUDIO_PLL to FLEXCOMM6. */
769
770 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach MCLK to FLEXCOMM6. */
771
772 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRG to FLEXCOMM6. */
773
774 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
775
776 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach FRO12M to FLEXCOMM7. */
777
778 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach FRO_HF to FLEXCOMM7. */
779
780 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach AUDIO_PLL to FLEXCOMM7. */
781
782 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach MCLK to FLEXCOMM7. */
783
784 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRG to FLEXCOMM7. */
785
786 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
787
788 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), /*!< Attach FRO12M to FLEXCOMM8. */
789
790 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), /*!< Attach FRO_HF to FLEXCOMM8. */
791
792 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2), /*!< Attach AUDIO_PLL to FLEXCOMM8. */
793
794 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), /*!< Attach MCLK to FLEXCOMM8. */
795
796 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), /*!< Attach FRG to FLEXCOMM8. */
797
798 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), /*!< Attach NONE to FLEXCOMM8. */
799
800 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), /*!< Attach FRO12M to FLEXCOMM9. */
801
802 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), /*!< Attach FRO_HF to FLEXCOMM9. */
803
804 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2), /*!< Attach AUDIO_PLL to FLEXCOMM9. */
805
806 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), /*!< Attach MCLK to FLEXCOMM9. */
807
808 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), /*!< Attach FRG to FLEXCOMM9. */
809
810 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), /*!< Attach NONE to FLEXCOMM9. */
811
812 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
813
814 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach AUDIO_PLL to MCLK. */
815
816 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
817
818 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), /*!< Attach MAIN_CLK to FRG. */
819
820 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), /*!< Attach SYS_PLL to FRG. */
821
822 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), /*!< Attach FRO12M to FRG. */
823
824 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), /*!< Attach FRO_HF to FRG. */
825
826 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), /*!< Attach NONE to FRG. */
827
828 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), /*!< Attach FRO12M to DMIC. */
829
830 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), /*!< Attach FRO_HF_DIV to DMIC. */
831
832 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), /*!< Attach AUDIO_PLL to DMIC. */
833
834 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), /*!< Attach MCLK to DMIC. */
835
836 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), /*!< Attach NONE to DMIC. */
837
838 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
839
840 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach SYS_PLL to SCT_CLK. */
841
842 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach FRO_HF to SCT_CLK. */
843
844 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach AUDIO_PLL to SCT_CLK. */
845
846 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */
847
848 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */
849
850 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach SYS_PLL to SDIO_CLK. */
851
852 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), /*!< Attach USB_PLL to SDIO_CLK. */
853
854 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */
855
856 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), /*!< Attach AUDIO_PLL to SDIO_CLK. */
857
858 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */
859
860 kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), /*!< Attach MAIN_CLK to LCD_CLK. */
861
862 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), /*!< Attach LCDCLKIN to LCD_CLK. */
863
864 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), /*!< Attach FRO_HF to LCD_CLK. */
865
866 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), /*!< Attach NONE to LCD_CLK. */
867
868 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Attach MAIN_CLK to ASYNC_APB. */
869
870 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), /*!< Attach FRO12M to ASYNC_APB. */
871
872 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), /*!< Attach AUDIO_PLL to ASYNC_APB. */
873
874 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3), /*!< Attach I2C_CLK_FC6 to ASYNC_APB. */
875
876 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
877
878 } clock_attach_id_t;
879
880 /*! @brief Clock dividers */
881 typedef enum _clock_div_name
882 {
883 kCLOCK_DivSystickClk = 0, /*!< Systick Clock Divider. */
884
885 kCLOCK_DivArmTrClkDiv = 1, /*!< Arm Tr Clk Div Divider. */
886
887 kCLOCK_DivCan0Clk = 2, /*!< Can0 Clock Divider. */
888
889 kCLOCK_DivCan1Clk = 3, /*!< Can1 Clock Divider. */
890
891 kCLOCK_DivSmartCard0Clk = 4, /*!< Smart Card0 Clock Divider. */
892
893 kCLOCK_DivSmartCard1Clk = 5, /*!< Smart Card1 Clock Divider. */
894
895 kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */
896
897 kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */
898
899 kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */
900
901 kCLOCK_DivSpifiClk = 36, /*!< Spifi Clock Divider. */
902
903 kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */
904
905 kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */
906
907 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */
908
909 kCLOCK_DivFrg = 40, /*!< Frg Divider. */
910
911 kCLOCK_DivDmicClk = 42, /*!< Dmic Clock Divider. */
912
913 kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */
914
915 kCLOCK_DivLcdClk = 44, /*!< Lcd Clock Divider. */
916
917 kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */
918
919 kCLOCK_DivEmcClk = 46, /*!< Emc Clock Divider. */
920
921 kCLOCK_DivSdioClk = 47 /*!< Sdio clock divider. */
922 } clock_div_name_t;
923
924 /*******************************************************************************
925 * API
926 ******************************************************************************/
927
928 #if defined(__cplusplus)
929 extern "C" {
930 #endif /* __cplusplus */
931
CLOCK_EnableClock(clock_ip_name_t clk)932 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
933 {
934 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
935 if (index < 3U)
936 {
937 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
938 }
939 else
940 {
941 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
942 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
943 }
944 }
945
CLOCK_DisableClock(clock_ip_name_t clk)946 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
947 {
948 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
949 if (index < 3U)
950 {
951 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
952 }
953 else
954 {
955 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
956 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
957 }
958 }
959 /**
960 * @brief FLASH Access time definitions
961 */
962 typedef enum _clock_flashtim
963 {
964 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */
965 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
966 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
967 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
968 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
969 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
970 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
971 kCLOCK_Flash8Cycle, /*!< Flash accesses use 8 CPU clocks */
972 kCLOCK_Flash9Cycle /*!< Flash accesses use 9 CPU clocks */
973 } clock_flashtim_t;
974
975 /**
976 * @brief Set FLASH memory access time in clocks
977 * @param clks : Clock cycles for FLASH access
978 * @return Nothing
979 */
CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)980 static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
981 {
982 uint32_t tmp;
983
984 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
985
986 /* Don't alter lower bits */
987 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
988 }
989
990 /**
991 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
992 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
993 * enabled.
994 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
995 * @return returns success or fail status.
996 */
997 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
998 /**
999 * @brief Configure the clock selection muxes.
1000 * @param connection : Clock to be configured.
1001 * @return Nothing
1002 */
1003 void CLOCK_AttachClk(clock_attach_id_t connection);
1004 /**
1005 * @brief Get the actual clock attach id.
1006 * This fuction uses the offset in input attach id, then it reads the actual source value in
1007 * the register and combine the offset to obtain an actual attach id.
1008 * @param attachId : Clock attach id to get.
1009 * @return Clock source value.
1010 */
1011 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
1012 /**
1013 * @brief Setup peripheral clock dividers.
1014 * @param div_name : Clock divider name
1015 * @param divided_by_value: Value to be divided
1016 * @param reset : Whether to reset the divider counter.
1017 * @return Nothing
1018 */
1019 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
1020 /**
1021 * @brief Set the flash wait states for the input freuqency.
1022 * @param iFreq : Input frequency
1023 * @return Nothing
1024 */
1025 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
1026
1027 /**
1028 * @brief Set the frg output frequency.
1029 * @param freq : output frequency
1030 * @return 0 : the frequency range is out of range.
1031 * 1 : switch successfully.
1032 */
1033 uint32_t CLOCK_SetFRGClock(uint32_t freq);
1034
1035 /*! @brief Return Frequency of FRG input clock
1036 * @return Frequency value
1037 */
1038 uint32_t CLOCK_GetFRGInputClock(void);
1039
1040 /*! @brief Return Frequency of selected clock
1041 * @return Frequency of selected clock
1042 */
1043 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1044 /*! @brief Return Frequency of FRO 12MHz
1045 * @return Frequency of FRO 12MHz
1046 */
1047 uint32_t CLOCK_GetFro12MFreq(void);
1048 /*! @brief Return Frequency of ClockOut
1049 * @return Frequency of ClockOut
1050 */
1051 uint32_t CLOCK_GetClockOutClkFreq(void);
1052 /*! @brief Return Frequency of Spifi Clock
1053 * @return Frequency of Spifi.
1054 */
1055 uint32_t CLOCK_GetSpifiClkFreq(void);
1056 /*! @brief Return Frequency of Adc Clock
1057 * @return Frequency of Adc Clock.
1058 */
1059 uint32_t CLOCK_GetAdcClkFreq(void);
1060 /*! brief Return Frequency of MCAN Clock
1061 * param MCanSel : 0U: MCAN0; 1U: MCAN1
1062 * return Frequency of MCAN Clock
1063 */
1064 uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
1065 /*! @brief Return Frequency of Usb0 Clock
1066 * @return Frequency of Usb0 Clock.
1067 */
1068 uint32_t CLOCK_GetUsb0ClkFreq(void);
1069 /*! @brief Return Frequency of Usb1 Clock
1070 * @return Frequency of Usb1 Clock.
1071 */
1072 uint32_t CLOCK_GetUsb1ClkFreq(void);
1073 /*! @brief Return Frequency of MClk Clock
1074 * @return Frequency of MClk Clock.
1075 */
1076 uint32_t CLOCK_GetMclkClkFreq(void);
1077 /*! @brief Return Frequency of SCTimer Clock
1078 * @return Frequency of SCTimer Clock.
1079 */
1080 uint32_t CLOCK_GetSctClkFreq(void);
1081 /*! @brief Return Frequency of SDIO Clock
1082 * @return Frequency of SDIO Clock.
1083 */
1084 uint32_t CLOCK_GetSdioClkFreq(void);
1085 /*! @brief Return Frequency of LCD Clock
1086 * @return Frequency of LCD Clock.
1087 */
1088 uint32_t CLOCK_GetLcdClkFreq(void);
1089 /*! @brief Return Frequency of LCD CLKIN Clock
1090 * @return Frequency of LCD CLKIN Clock.
1091 */
1092 uint32_t CLOCK_GetLcdClkIn(void);
1093 /*! @brief Return Frequency of External Clock
1094 * @return Frequency of External Clock. If no external clock is used returns 0.
1095 */
1096 uint32_t CLOCK_GetExtClkFreq(void);
1097 /*! @brief Return Frequency of Watchdog Oscillator
1098 * @return Frequency of Watchdog Oscillator
1099 */
1100 uint32_t CLOCK_GetWdtOscFreq(void);
1101 /*! @brief Return Frequency of High-Freq output of FRO
1102 * @return Frequency of High-Freq output of FRO
1103 */
1104 uint32_t CLOCK_GetFroHfFreq(void);
1105 /*! @brief Return Frequency of frg
1106 * @return Frequency of FRG
1107 */
1108 uint32_t CLOCK_GetFrgClkFreq(void);
1109 /*! @brief Return Frequency of dmic
1110 * @return Frequency of DMIC
1111 */
1112 uint32_t CLOCK_GetDmicClkFreq(void);
1113 /*! @brief Return Frequency of PLL
1114 * @return Frequency of PLL
1115 */
1116 uint32_t CLOCK_GetPllOutFreq(void);
1117 /*! @brief Return Frequency of USB PLL
1118 * @return Frequency of PLL
1119 */
1120 uint32_t CLOCK_GetUsbPllOutFreq(void);
1121 /*! @brief Return Frequency of AUDIO PLL
1122 * @return Frequency of PLL
1123 */
1124 uint32_t CLOCK_GetAudioPllOutFreq(void);
1125 /*! @brief Return Frequency of 32kHz osc
1126 * @return Frequency of 32kHz osc
1127 */
1128 uint32_t CLOCK_GetOsc32KFreq(void);
1129 /*! @brief Return Frequency of Core System
1130 * @return Frequency of Core System
1131 */
1132 uint32_t CLOCK_GetCoreSysClkFreq(void);
1133 /*! @brief Return Frequency of I2S MCLK Clock
1134 * @return Frequency of I2S MCLK Clock
1135 */
1136 uint32_t CLOCK_GetI2SMClkFreq(void);
1137 /*! @brief Return Frequency of Flexcomm functional Clock
1138 * @return Frequency of Flexcomm functional Clock
1139 */
1140 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1141 /*! @brief Return Asynchronous APB Clock source
1142 * @return Asynchronous APB CLock source
1143 */
CLOCK_GetAsyncApbClkSrc(void)1144 __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
1145 {
1146 return (async_clock_src_t)(uint8_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
1147 }
1148 /*! @brief Return Frequency of Asynchronous APB Clock
1149 * @return Frequency of Asynchronous APB Clock Clock
1150 */
1151 uint32_t CLOCK_GetAsyncApbClkFreq(void);
1152 /*! @brief Return EMC source
1153 * @return EMC source
1154 */
CLOCK_GetEmcClkFreq(void)1155 __STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
1156 {
1157 uint32_t freqtmp;
1158
1159 freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
1160 return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
1161 }
1162 /*! @brief Return Audio PLL input clock rate
1163 * @return Audio PLL input clock rate
1164 */
1165 uint32_t CLOCK_GetAudioPLLInClockRate(void);
1166 /*! @brief Return System PLL input clock rate
1167 * @return System PLL input clock rate
1168 */
1169 uint32_t CLOCK_GetSystemPLLInClockRate(void);
1170
1171 /*! @brief Return System PLL output clock rate
1172 * @param recompute : Forces a PLL rate recomputation if true
1173 * @return System PLL output clock rate
1174 * @note The PLL rate is cached in the driver in a variable as
1175 * the rate computation function can take some time to perform. It
1176 * is recommended to use 'false' with the 'recompute' parameter.
1177 */
1178 uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
1179
1180 /*! @brief Return System AUDIO PLL output clock rate
1181 * @param recompute : Forces a AUDIO PLL rate recomputation if true
1182 * @return System AUDIO PLL output clock rate
1183 * @note The AUDIO PLL rate is cached in the driver in a variable as
1184 * the rate computation function can take some time to perform. It
1185 * is recommended to use 'false' with the 'recompute' parameter.
1186 */
1187 uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
1188
1189 /*! @brief Return System USB PLL output clock rate
1190 * @param recompute : Forces a USB PLL rate recomputation if true
1191 * @return System USB PLL output clock rate
1192 * @note The USB PLL rate is cached in the driver in a variable as
1193 * the rate computation function can take some time to perform. It
1194 * is recommended to use 'false' with the 'recompute' parameter.
1195 */
1196 uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
1197
1198 /*! @brief Enables and disables PLL bypass mode
1199 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
1200 * @return System PLL output clock rate
1201 */
CLOCK_SetBypassPLL(bool bypass)1202 __STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
1203 {
1204 if (bypass)
1205 {
1206 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
1207 }
1208 else
1209 {
1210 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
1211 }
1212 }
1213
1214 /*! @brief Check if PLL is locked or not
1215 * @return true if the PLL is locked, false if not locked
1216 */
CLOCK_IsSystemPLLLocked(void)1217 __STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
1218 {
1219 return ((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
1220 }
1221
1222 /*! @brief Check if USB PLL is locked or not
1223 * @return true if the USB PLL is locked, false if not locked
1224 */
CLOCK_IsUsbPLLLocked(void)1225 __STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
1226 {
1227 return ((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
1228 }
1229
1230 /*! @brief Check if AUDIO PLL is locked or not
1231 * @return true if the AUDIO PLL is locked, false if not locked
1232 */
CLOCK_IsAudioPLLLocked(void)1233 __STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
1234 {
1235 return ((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
1236 }
1237
1238 /*! @brief Enables and disables SYS OSC
1239 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
1240 */
CLOCK_Enable_SysOsc(bool enable)1241 __STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
1242 {
1243 if (enable)
1244 {
1245 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
1246 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
1247 }
1248
1249 else
1250 {
1251 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
1252 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
1253 }
1254 }
1255
1256 /*! @brief Store the current PLL rate
1257 * @param rate: Current rate of the PLL
1258 * @return Nothing
1259 **/
1260 void CLOCK_SetStoredPLLClockRate(uint32_t rate);
1261
1262 /*! @brief Store the current AUDIO PLL rate
1263 * @param rate: Current rate of the PLL
1264 * @return Nothing
1265 **/
1266 void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
1267
1268 /*! @brief PLL configuration structure flags for 'flags' field
1269 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1270 *
1271 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1272 * configuration structure must be assigned with the expected PLL frequency. If the
1273 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1274 * function and the driver will determine the PLL rate from the currently selected
1275 * PLL source. This flag might be used to configure the PLL input clock more accurately
1276 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1277 *
1278 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1279 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1280 * are not used.<br>
1281 */
1282 #define PLL_CONFIGFLAG_USEINRATE (1UL << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1283 #define PLL_CONFIGFLAG_FORCENOFRACT \
1284 (1UL << 2U) /*!< Force non-fractional output mode, \
1285 PLL output will not use the fractional, \
1286 automatic bandwidth, or SS hardware */
1287
1288 /*! @brief PLL configuration structure
1289 *
1290 * This structure can be used to configure the settings for a PLL
1291 * setup structure. Fill in the desired configuration for the PLL
1292 * and call the PLL setup function to fill in a PLL setup structure.
1293 */
1294 typedef struct _pll_config
1295 {
1296 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1297 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1298 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1299 } pll_config_t;
1300
1301 /*! @brief PLL setup structure flags for 'flags' field
1302 * These flags control how the PLL setup function sets up the PLL
1303 */
1304 #define PLL_SETUPFLAG_POWERUP (1UL << 0U) /*!< Setup will power on the PLL after setup */
1305 #define PLL_SETUPFLAG_WAITLOCK (1UL << 1U) /*!< Setup will wait for PLL lock, implying the PLL will be pwoered on */
1306 #define PLL_SETUPFLAG_ADGVOLT (1UL << 2U) /*!< Optimize system voltage for the new PLL rate */
1307
1308 /*! @brief PLL setup structure
1309 * This structure can be used to pre-build a PLL setup configuration
1310 * at run-time and quickly set the PLL to the configuration. It can be
1311 * populated with the PLL setup function. If powering up or waiting
1312 * for PLL lock, the PLL input clock source should be configured prior
1313 * to PLL setup.
1314 */
1315 typedef struct _pll_setup
1316 {
1317 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
1318 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
1319 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
1320 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
1321 uint32_t pllRate; /*!< Acutal PLL rate */
1322 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
1323 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1324 } pll_setup_t;
1325
1326 /*! @brief PLL status definitions
1327 */
1328 typedef enum _pll_error
1329 {
1330 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1331 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1332 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1333 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1334 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1335 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1336 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1337 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1338 } pll_error_t;
1339
1340 /*! @brief USB clock source definition. */
1341 typedef enum _clock_usb_src
1342 {
1343 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
1344 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
1345 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1346 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
1347
1348 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
1349 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
1350 } clock_usb_src_t;
1351
1352 /*! @brief USB PDEL Divider. */
1353 typedef enum _usb_pll_psel
1354 {
1355 pSel_Divide_1 = 0U,
1356 pSel_Divide_2,
1357 pSel_Divide_4,
1358 pSel_Divide_8
1359 } usb_pll_psel;
1360
1361 /*! @brief PLL setup structure
1362 * This structure can be used to pre-build a USB PLL setup configuration
1363 * at run-time and quickly set the usb PLL to the configuration. It can be
1364 * populated with the USB PLL setup function. If powering up or waiting
1365 * for USB PLL lock, the PLL input clock source should be configured prior
1366 * to USB PLL setup.
1367 */
1368 typedef struct _usb_pll_setup
1369 {
1370 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
1371 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
1372 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
1373 bool direct; /*!< USB PLL CCO output control */
1374 bool bypass; /*!< USB PLL inout clock bypass control */
1375 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
1376 uint32_t inputRate; /*!< USB PLL input rate */
1377 } usb_pll_setup_t;
1378
1379 /*! @brief Return System PLL output clock rate from setup structure
1380 * @param pSetup : Pointer to a PLL setup structure
1381 * @return System PLL output clock rate the setup structure will generate
1382 */
1383 uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
1384
1385 /*! @brief Return System AUDIO PLL output clock rate from setup structure
1386 * @param pSetup : Pointer to a PLL setup structure
1387 * @return System PLL output clock rate the setup structure will generate
1388 */
1389 uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
1390
1391 /*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
1392 * @param pSetup : Pointer to a PLL setup structure
1393 * @return System PLL output clock rate the setup structure will generate
1394 */
1395 uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
1396
1397 /*! @brief Return System USB PLL output clock rate from setup structure
1398 * @param pSetup : Pointer to a PLL setup structure
1399 * @return System PLL output clock rate the setup structure will generate
1400 */
1401 uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
1402
1403 /*! @brief Set USB PLL output frequency
1404 * @param rate : frequency value
1405 *
1406 */
1407 void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
1408 /*! @brief Set PLL output based on the passed PLL setup data
1409 * @param pControl : Pointer to populated PLL control structure to generate setup with
1410 * @param pSetup : Pointer to PLL setup structure to be filled
1411 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1412 * @note Actual frequency for setup may vary from the desired frequency based on the
1413 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1414 */
1415 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1416
1417 /*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
1418 * @param pControl : Pointer to populated PLL control structure to generate setup with
1419 * @param pSetup : Pointer to PLL setup structure to be filled
1420 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1421 * @note Actual frequency for setup may vary from the desired frequency based on the
1422 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1423 */
1424 pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1425
1426 /*! @brief Set PLL output from PLL setup structure (precise frequency)
1427 * @param pSetup : Pointer to populated PLL setup structure
1428 * @param flagcfg : Flag configuration for PLL config structure
1429 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1430 * @note This function will power off the PLL, setup the PLL with the
1431 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1432 * and adjust system voltages to the new PLL rate. The function will not
1433 * alter any source clocks (ie, main systen clock) that may use the PLL,
1434 * so these should be setup prior to and after exiting the function.
1435 */
1436 pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1437
1438 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
1439 * @param pSetup : Pointer to populated PLL setup structure
1440 * @param flagcfg : Flag configuration for PLL config structure
1441 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1442 * @note This function will power off the PLL, setup the PLL with the
1443 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1444 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1445 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1446 * so these should be setup prior to and after exiting the function.
1447 */
1448 pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1449
1450 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
1451 * frequency)
1452 * @param pSetup : Pointer to populated PLL setup structure
1453 * @param flagcfg : Flag configuration for PLL config structure
1454 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1455 * @note This function will power off the PLL, setup the PLL with the
1456 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1457 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1458 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1459 * so these should be setup prior to and after exiting the function.
1460 */
1461 pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
1462
1463 /**
1464 * @brief Set PLL output from PLL setup structure (precise frequency)
1465 * @param pSetup : Pointer to populated PLL setup structure
1466 * @return kStatus_PLL_Success on success, or PLL setup error code
1467 * @note This function will power off the PLL, setup the PLL with the
1468 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1469 * and adjust system voltages to the new PLL rate. The function will not
1470 * alter any source clocks (ie, main systen clock) that may use the PLL,
1471 * so these should be setup prior to and after exiting the function.
1472 */
1473 pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
1474
1475 /**
1476 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
1477 * @param pSetup : Pointer to populated PLL setup structure
1478 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
1479 * @note This function will power off the PLL, setup the Audio PLL with the
1480 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
1481 * and adjust system voltages to the new PLL rate. The function will not
1482 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
1483 * so these should be setup prior to and after exiting the function.
1484 */
1485 pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
1486
1487 /**
1488 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
1489 * @param pSetup : Pointer to populated USB PLL setup structure
1490 * @return kStatus_PLL_Success on success, or USB PLL setup error code
1491 * @note This function will power off the USB PLL, setup the PLL with the
1492 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
1493 * and adjust system voltages to the new USB PLL rate. The function will not
1494 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
1495 * so these should be setup prior to and after exiting the function.
1496 */
1497 pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
1498
1499 /*! @brief Set PLL output based on the multiplier and input frequency
1500 * @param multiply_by : multiplier
1501 * @param input_freq : Clock input frequency of the PLL
1502 * @return Nothing
1503 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1504 * function does not disable or enable PLL power, wait for PLL lock,
1505 * or adjust system voltages. These must be done in the application.
1506 * The function will not alter any source clocks (ie, main systen clock)
1507 * that may use the PLL, so these should be setup prior to and after
1508 * exiting the function.
1509 */
1510 void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
1511
1512 /*! @brief Disable USB clock.
1513 *
1514 * Disable USB clock.
1515 */
CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)1516 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1517 {
1518 CLOCK_DisableClock(clk);
1519 }
1520
1521 /*! @brief Enable USB Device FS clock.
1522 * @param src : clock source
1523 * @param freq: clock frequency
1524 * Enable USB Device Full Speed clock.
1525 */
1526 bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1527
1528 /*! @brief Enable USB HOST FS clock.
1529 * @param src : clock source
1530 * @param freq: clock frequency
1531 * Enable USB HOST Full Speed clock.
1532 */
1533 bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
1534
1535 /*! @brief Enable USB Device HS clock.
1536 * @param src : clock source
1537 * @param freq: clock frequency
1538 * Enable USB Device High Speed clock.
1539 */
1540 bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1541
1542 /*! @brief Enable USB HOST HS clock.
1543 * @param src : clock source
1544 * @param freq: clock frequency
1545 * Enable USB HOST High Speed clock.
1546 */
1547 bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
1548
1549 #if defined(__cplusplus)
1550 }
1551 #endif /* __cplusplus */
1552
1553 /*! @} */
1554
1555 #endif /* _FSL_CLOCK_H_ */
1556
