1 /*
2 ** ###################################################################
3 ** Processors: LPC54605J256BD100
4 ** LPC54605J256ET100
5 ** LPC54605J256ET180
6 ** LPC54605J512BD100
7 ** LPC54605J512ET100
8 ** LPC54605J512ET180
9 **
10 ** Compilers: GNU C Compiler
11 ** IAR ANSI C/C++ Compiler for ARM
12 ** Keil ARM C/C++ Compiler
13 ** MCUXpresso Compiler
14 **
15 ** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
16 ** Version: rev. 1.2, 2017-06-08
17 ** Build: b201015
18 **
19 ** Abstract:
20 ** Provides a system configuration function and a global variable that
21 ** contains the system frequency. It configures the device and initializes
22 ** the oscillator (PLL) that is part of the microcontroller device.
23 **
24 ** Copyright 2016 Freescale Semiconductor, Inc.
25 ** Copyright 2016-2020 NXP
26 ** All rights reserved.
27 **
28 ** SPDX-License-Identifier: BSD-3-Clause
29 **
30 ** http: www.nxp.com
31 ** mail: support@nxp.com
32 **
33 ** Revisions:
34 ** - rev. 1.0 (2016-08-12)
35 ** Initial version.
36 ** - rev. 1.1 (2016-11-25)
37 ** Update CANFD and Classic CAN register.
38 ** Add MAC TIMERSTAMP registers.
39 ** - rev. 1.2 (2017-06-08)
40 ** Remove RTC_CTRL_RTC_OSC_BYPASS.
41 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
42 ** Remove RESET and HALT from SYSCON_AHBCLKDIV.
43 **
44 ** ###################################################################
45 */
46
47 /*!
48 * @file LPC54605
49 * @version 1.2
50 * @date 2017-06-08
51 * @brief Device specific configuration file for LPC54605 (implementation file)
52 *
53 * Provides a system configuration function and a global variable that contains
54 * the system frequency. It configures the device and initializes the oscillator
55 * (PLL) that is part of the microcontroller device.
56 */
57
58 #include <stdint.h>
59 #include "fsl_device_registers.h"
60
61 #define NVALMAX (0x100)
62 #define PVALMAX (0x20U)
63 #define MVALMAX (0x8000U)
64 #define PLL_MDEC_VAL_P (0U) /* MDEC is in bits 16:0 */
65 #define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
66 #define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
67 #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
68 #define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
69 #define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
70
71 static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
72 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
73 /* Get WATCH DOG Clk */
getWdtOscFreq(void)74 static uint32_t getWdtOscFreq(void)
75 {
76 uint8_t freq_sel, div_sel;
77 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) == SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
78 {
79 return 0U;
80 }
81 else
82 {
83 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
84 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
85 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
86 }
87 }
88 /* Find decoded N value for raw NDEC value */
pllDecodeN(uint32_t NDEC)89 static uint32_t pllDecodeN(uint32_t NDEC)
90 {
91 uint32_t n, x, i;
92
93 /* Find NDec */
94 switch (NDEC)
95 {
96 case 0x3FFU:
97 n = 0UL;
98 break;
99 case 0x302U:
100 n = 1UL;
101 break;
102 case 0x202U:
103 n = 2UL;
104 break;
105 default:
106 x = 0x080UL;
107 n = 0xFFFFFFFFUL;
108 for (i = NVALMAX; i >= 3UL; i--)
109 {
110 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
111 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
112 {
113 /* Decoded value of NDEC */
114 n = i;
115 }
116 if (n != 0xFFFFFFFFUL)
117 {
118 break;
119 }
120 }
121 break;
122 }
123 return n;
124 }
125
126 /* Find decoded P value for raw PDEC value */
pllDecodeP(uint32_t PDEC)127 static uint32_t pllDecodeP(uint32_t PDEC)
128 {
129 uint32_t p, x, i;
130 /* Find PDec */
131 switch (PDEC)
132 {
133 case 0x7FU:
134 p = 0UL;
135 break;
136 case 0x62U:
137 p = 1UL;
138 break;
139 case 0x42U:
140 p = 2UL;
141 break;
142 default:
143 x = 0x10UL;
144 p = 0xFFFFFFFFUL;
145 for (i = PVALMAX; i >= 3UL; i--)
146 {
147 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
148 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
149 {
150 /* Decoded value of PDEC */
151 p = i;
152 }
153 if (p != 0xFFFFFFFFUL)
154 {
155 break;
156 }
157 }
158 break;
159 }
160 return p;
161 }
162
163 /* Find decoded M value for raw MDEC value */
pllDecodeM(uint32_t MDEC)164 static uint32_t pllDecodeM(uint32_t MDEC)
165 {
166 uint32_t m, i, x;
167
168 /* Find MDec */
169 switch (MDEC)
170 {
171 case 0x1FFFFU:
172 m = 0UL;
173 break;
174 case 0x18003U:
175 m = 1UL;
176 break;
177 case 0x10003U:
178 m = 2UL;
179 break;
180 default:
181 x = 0x04000UL;
182 m = 0xFFFFFFFFUL;
183 for (i = MVALMAX; i >= 3UL; i--)
184 {
185 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
186 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
187 {
188 /* Decoded value of MDEC */
189 m = i;
190 }
191 if (m != 0xFFFFFFFFUL)
192 {
193 break;
194 }
195 }
196 break;
197 }
198 return m;
199 }
200
201 /* Get predivider (N) from PLL NDEC setting */
findPllPreDiv(uint32_t ctrlReg,uint32_t nDecReg)202 static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
203 {
204 uint32_t preDiv = 1U;
205
206 /* Direct input is not used? */
207 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U)
208 {
209 /* Decode NDEC value to get (N) pre divider */
210 preDiv = pllDecodeN(nDecReg & 0x3FFU);
211 if (preDiv == 0U)
212 {
213 preDiv = 1U;
214 }
215 }
216 /* Adjusted by 1, directi is used to bypass */
217 return preDiv;
218 }
219
220 /* Get postdivider (P) from PLL PDEC setting */
findPllPostDiv(uint32_t ctrlReg,uint32_t pDecReg)221 static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
222 {
223 uint32_t postDiv = 1U;
224
225 /* Direct input is not used? */
226 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
227 {
228 /* Decode PDEC value to get (P) post divider */
229 postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
230 if (postDiv == 0U)
231 {
232 postDiv = 2U;
233 }
234 }
235 /* Adjusted by 1, directo is used to bypass */
236 return postDiv;
237 }
238
239 /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
findPllMMult(uint32_t ctrlReg,uint32_t mDecReg)240 static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
241 {
242 uint32_t mMult = 1U;
243
244 /* Decode MDEC value to get (M) multiplier */
245 mMult = pllDecodeM(mDecReg & 0x1FFFFU);
246 if (mMult == 0U)
247 {
248 mMult = 1U;
249 }
250 return mMult;
251 }
252
253
254
255 /* ----------------------------------------------------------------------------
256 -- Core clock
257 ---------------------------------------------------------------------------- */
258
259 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
260
261 /* ----------------------------------------------------------------------------
262 -- SystemInit()
263 ---------------------------------------------------------------------------- */
264
SystemInit(void)265 void SystemInit (void) {
266 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
267 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
268 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
269
270 #if defined(__MCUXPRESSO)
271 extern void(*const g_pfnVectors[]) (void);
272 SCB->VTOR = (uint32_t) &g_pfnVectors;
273 #else
274 extern void *__Vectors;
275 SCB->VTOR = (uint32_t) &__Vectors;
276 #endif
277 SYSCON->ARMTRACECLKDIV = 0U;
278 /* Optionally enable RAM banks that may be off by default at reset */
279 #if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
280 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
281 #endif
282 SystemInitHook();
283 }
284
285 /* ----------------------------------------------------------------------------
286 -- SystemCoreClockUpdate()
287 ---------------------------------------------------------------------------- */
288
SystemCoreClockUpdate(void)289 void SystemCoreClockUpdate (void) {
290 uint32_t clkRate = 0U;
291 uint32_t prediv, postdiv;
292 uint64_t workRate;
293
294 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
295 {
296 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
297 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
298 {
299 case 0x00U: /* FRO 12 MHz (fro_12m) */
300 clkRate = CLK_FRO_12MHZ;
301 break;
302 case 0x01U: /* CLKIN Source (clk_in) */
303 clkRate = CLK_CLK_IN;
304 break;
305 case 0x02U: /* Watchdog oscillator (wdt_clk) */
306 clkRate = getWdtOscFreq();
307 break;
308 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
309 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
310 {
311 clkRate = CLK_FRO_96MHZ;
312 }
313 else
314 {
315 clkRate = CLK_FRO_48MHZ;
316 }
317 break;
318 }
319 break;
320 case 0x02U: /* System PLL clock (pll_clk)*/
321 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
322 {
323 case 0x00U: /* FRO 12 MHz (fro_12m) */
324 clkRate = CLK_FRO_12MHZ;
325 break;
326 case 0x01U: /* CLKIN Source (clk_in) */
327 clkRate = CLK_CLK_IN;
328 break;
329 case 0x02U: /* Watchdog oscillator (wdt_clk) */
330 clkRate = getWdtOscFreq();
331 break;
332 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
333 clkRate = CLK_RTC_32K_CLK;
334 break;
335 default:
336 clkRate = 0U;
337 break;
338 }
339 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
340 {
341 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
342 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
343 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
344 /* Adjust input clock */
345 clkRate = clkRate / prediv;
346
347 /* MDEC used for rate */
348 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
349 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
350 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
351 }
352 break;
353 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
354 clkRate = CLK_RTC_32K_CLK;
355 break;
356 default:
357 clkRate = 0U;
358 break;
359 }
360 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
361 }
362
363 /* ----------------------------------------------------------------------------
364 -- SystemInitHook()
365 ---------------------------------------------------------------------------- */
366
SystemInitHook(void)367 __attribute__ ((weak)) void SystemInitHook (void) {
368 /* Void implementation of the weak function. */
369 }
370
