1 /* 2 ** ################################################################### 3 ** Processors: LPC54114J256BD64_cm0plus 4 ** LPC54114J256UK49_cm0plus 5 ** 6 ** Compilers: GNU C Compiler 7 ** IAR ANSI C/C++ Compiler for ARM 8 ** Keil ARM C/C++ Compiler 9 ** MCUXpresso Compiler 10 ** 11 ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 12 ** Version: rev. 1.0, 2016-04-29 13 ** Build: b200304 14 ** 15 ** Abstract: 16 ** CMSIS Peripheral Access Layer for LPC54114_cm0plus 17 ** 18 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 19 ** Copyright 2016-2020 NXP 20 ** All rights reserved. 21 ** 22 ** SPDX-License-Identifier: BSD-3-Clause 23 ** 24 ** http: www.nxp.com 25 ** mail: support@nxp.com 26 ** 27 ** Revisions: 28 ** - rev. 1.0 (2016-04-29) 29 ** Initial version. 30 ** 31 ** ################################################################### 32 */ 33 34 /*! 35 * @file LPC54114_cm0plus.h 36 * @version 1.0 37 * @date 2016-04-29 38 * @brief CMSIS Peripheral Access Layer for LPC54114_cm0plus 39 * 40 * CMSIS Peripheral Access Layer for LPC54114_cm0plus 41 */ 42 43 #ifndef _LPC54114_CM0PLUS_H_ 44 #define _LPC54114_CM0PLUS_H_ /**< Symbol preventing repeated inclusion */ 45 46 /** Memory map major version (memory maps with equal major version number are 47 * compatible) */ 48 #define MCU_MEM_MAP_VERSION 0x0100U 49 /** Memory map minor version */ 50 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 51 52 53 /* ---------------------------------------------------------------------------- 54 -- Interrupt vector numbers 55 ---------------------------------------------------------------------------- */ 56 57 /*! 58 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 59 * @{ 60 */ 61 62 /** Interrupt Number Definitions */ 63 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 64 65 typedef enum IRQn { 66 /* Auxiliary constants */ 67 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 68 69 /* Core interrupts */ 70 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 71 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 72 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 73 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 74 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 75 76 /* Device specific interrupts */ 77 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ 78 DMA0_IRQn = 1, /**< DMA controller */ 79 GINT0_IRQn = 2, /**< GPIO group 0 */ 80 GINT1_IRQn = 3, /**< GPIO group 1 */ 81 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ 82 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ 83 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ 84 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ 85 UTICK0_IRQn = 8, /**< Micro-tick Timer */ 86 MRT0_IRQn = 9, /**< Multi-rate timer */ 87 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ 88 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ 89 SCT0_IRQn = 12, /**< SCTimer/PWM */ 90 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ 91 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ 92 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ 93 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ 94 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ 95 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ 96 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ 97 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ 98 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ 99 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ 100 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ 101 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ 102 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ 103 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ 104 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ 105 USB0_IRQn = 28, /**< USB device */ 106 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ 107 IOH_IRQn = 30, /**< IOH */ 108 MAILBOX_IRQn = 31 /**< Mailbox interrupt (present on selected devices) */ 109 } IRQn_Type; 110 111 /*! 112 * @} 113 */ /* end of group Interrupt_vector_numbers */ 114 115 116 /* ---------------------------------------------------------------------------- 117 -- Cortex M0 Core Configuration 118 ---------------------------------------------------------------------------- */ 119 120 /*! 121 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 122 * @{ 123 */ 124 125 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 126 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 127 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 128 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 129 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 130 131 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 132 #include "system_LPC54114_cm0plus.h" /* Device specific configuration file */ 133 134 /*! 135 * @} 136 */ /* end of group Cortex_Core_Configuration */ 137 138 139 /* ---------------------------------------------------------------------------- 140 -- Device Peripheral Access Layer 141 ---------------------------------------------------------------------------- */ 142 143 /*! 144 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 145 * @{ 146 */ 147 148 149 /* 150 ** Start of section using anonymous unions 151 */ 152 153 #if defined(__ARMCC_VERSION) 154 #if (__ARMCC_VERSION >= 6010050) 155 #pragma clang diagnostic push 156 #else 157 #pragma push 158 #pragma anon_unions 159 #endif 160 #elif defined(__GNUC__) 161 /* anonymous unions are enabled by default */ 162 #elif defined(__IAR_SYSTEMS_ICC__) 163 #pragma language=extended 164 #else 165 #error Not supported compiler type 166 #endif 167 168 /* ---------------------------------------------------------------------------- 169 -- ADC Peripheral Access Layer 170 ---------------------------------------------------------------------------- */ 171 172 /*! 173 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 174 * @{ 175 */ 176 177 /** ADC - Register Layout Typedef */ 178 typedef struct { 179 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ 180 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ 181 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ 182 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ 183 uint8_t RESERVED_0[8]; 184 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ 185 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ 186 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ 187 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ 188 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ 189 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ 190 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ 191 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ 192 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ 193 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ 194 } ADC_Type; 195 196 /* ---------------------------------------------------------------------------- 197 -- ADC Register Masks 198 ---------------------------------------------------------------------------- */ 199 200 /*! 201 * @addtogroup ADC_Register_Masks ADC Register Masks 202 * @{ 203 */ 204 205 /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ 206 /*! @{ */ 207 #define ADC_CTRL_CLKDIV_MASK (0xFFU) 208 #define ADC_CTRL_CLKDIV_SHIFT (0U) 209 /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce 210 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, 211 * software should program the smallest value in this field that yields this maximum clock rate or 212 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may 213 * be desirable. This field is ignored in the asynchronous operating mode. 214 */ 215 #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) 216 #define ADC_CTRL_ASYNMODE_MASK (0x100U) 217 #define ADC_CTRL_ASYNMODE_SHIFT (8U) 218 /*! ASYNMODE - Select clock mode. 219 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in 220 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to 221 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. 222 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC 223 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger 224 * pulse. 225 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. 226 */ 227 #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) 228 #define ADC_CTRL_RESOL_MASK (0x600U) 229 #define ADC_CTRL_RESOL_SHIFT (9U) 230 /*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher 231 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the 232 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when 233 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable 234 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate 235 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system 236 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution 237 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. 238 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. 239 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field. 240 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field. 241 */ 242 #define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) 243 #define ADC_CTRL_BYPASSCAL_MASK (0x800U) 244 #define ADC_CTRL_BYPASSCAL_SHIFT (11U) 245 /*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset 246 * error is not a concern in the application. 247 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for 248 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may 249 * be warranted periodically - especially if operating conditions have changed. 250 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - 251 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set. 252 */ 253 #define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) 254 #define ADC_CTRL_TSAMP_MASK (0x7000U) 255 #define ADC_CTRL_TSAMP_SHIFT (12U) 256 /*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion 257 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions 258 * and the output impedance of the analog source, longer sampling times may be required. See 259 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to 260 * seven, by which the sample period will be extended. The total conversion time will increase by 261 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A 262 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will 263 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will 264 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock 265 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be 266 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 267 * 22 ADC clocks. 268 */ 269 #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) 270 /*! @} */ 271 272 /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ 273 /*! @{ */ 274 #define ADC_INSEL_SEL_MASK (0x3U) 275 #define ADC_INSEL_SEL_SHIFT (0U) 276 /*! SEL - Selects the input source for channel 0. All other values are reserved. 277 * 0b00..ADC0_IN0 function. 278 * 0b11..Internal temperature sensor. 279 */ 280 #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) 281 /*! @} */ 282 283 /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ 284 /*! @{ */ 285 #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) 286 #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) 287 /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this 288 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be 289 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 290 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via 291 * software command, ADC conversions will be performed on each enabled channel, in sequence, 292 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) 293 * is LOW. It is allowed to change this field and set bit 31 in the same write. 294 */ 295 #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) 296 #define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) 297 #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) 298 /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion 299 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order 300 * to avoid generating a spurious trigger, it is recommended writing to this field only when 301 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 302 */ 303 #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) 304 #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) 305 #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) 306 /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In 307 * order to avoid generating a spurious trigger, it is recommended writing to this field only when 308 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 309 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 310 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 311 */ 312 #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) 313 #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) 314 #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) 315 /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization 316 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a 317 * conversion. There are slightly different criteria for whether or not this bit can be set 318 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): 319 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already 320 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). 321 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system 322 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be 323 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse 324 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and 325 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be 326 * maintained for one system clock period. 327 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. 328 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. 329 */ 330 #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) 331 #define ADC_SEQ_CTRL_START_MASK (0x4000000U) 332 #define ADC_SEQ_CTRL_START_SHIFT (26U) 333 /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The 334 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this 335 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a 336 * conversion sequence. It will consequently always read back as a zero. 337 */ 338 #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) 339 #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) 340 #define ADC_SEQ_CTRL_BURST_SHIFT (27U) 341 /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled 342 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions 343 * can be halted by clearing this bit. The sequence currently in progress will be completed before 344 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 345 */ 346 #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) 347 #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) 348 #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) 349 /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a 350 * single conversion on the next channel in the sequence instead of the default response of 351 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have 352 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled 353 * channel. Interrupt generation will still occur either after each individual conversion or at 354 * the end of the entire sequence, depending on the state of the MODE bit. 355 */ 356 #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) 357 #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) 358 #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) 359 /*! LOWPRIO - Set priority for sequence A. 360 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 361 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence 362 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion 363 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume 364 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the 365 * conversion sequence will resume from that point. 366 */ 367 #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) 368 #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) 369 #define ADC_SEQ_CTRL_MODE_SHIFT (30U) 370 /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence 371 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each 372 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts 373 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which 374 * overrun conditions contribute to an overrun interrupt as described below. 375 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC 376 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The 377 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger 378 * if enabled. 379 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A 380 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in 381 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun 382 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. 383 */ 384 #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) 385 #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) 386 #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) 387 /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be 388 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state 389 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered 390 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care 391 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE 392 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be 393 * triggered immediately upon being enabled. 394 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence 395 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is 396 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 397 * 0b1..Enabled. Sequence n is enabled. 398 */ 399 #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) 400 /*! @} */ 401 402 /* The count of ADC_SEQ_CTRL */ 403 #define ADC_SEQ_CTRL_COUNT (2U) 404 405 /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ 406 /*! @{ */ 407 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) 408 #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) 409 /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion 410 * performed under conversion sequence associated with this register. The result is a binary 411 * fraction representing the voltage on the currently-selected input channel as it falls within the 412 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less 413 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input 414 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this 415 * result has not yet been read. 416 */ 417 #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) 418 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) 419 #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) 420 /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or 421 * within the range established by the designated threshold comparison registers (THRn_LOW and 422 * THRn_HIGH). 423 */ 424 #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) 425 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) 426 #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) 427 /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a 428 * crossing of the threshold level established by the designated LOW threshold comparison register 429 * (THRn_LOW) and, if so, in what direction the crossing occurred. 430 */ 431 #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) 432 #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) 433 #define ADC_SEQ_GDAT_CHN_SHIFT (26U) 434 /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 435 * identifies channel 0, 0001 channel 1, etc.). 436 */ 437 #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) 438 #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) 439 #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) 440 /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a 441 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along 442 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun 443 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set 444 * to '0' (and if the overrun interrupt is enabled). 445 */ 446 #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) 447 #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) 448 #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) 449 /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded 450 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a 451 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that 452 * sequence is set to 0 (and if the interrupt is enabled). 453 */ 454 #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) 455 /*! @} */ 456 457 /* The count of ADC_SEQ_GDAT */ 458 #define ADC_SEQ_GDAT_COUNT (2U) 459 460 /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ 461 /*! @{ */ 462 #define ADC_DAT_RESULT_MASK (0xFFF0U) 463 #define ADC_DAT_RESULT_SHIFT (4U) 464 /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed 465 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, 466 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on 467 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that 468 * the voltage on the input was close to, equal to, or greater than that on VREFP. 469 */ 470 #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) 471 #define ADC_DAT_THCMPRANGE_MASK (0x30000U) 472 #define ADC_DAT_THCMPRANGE_SHIFT (16U) 473 /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion 474 * was greater than or equal to the value programmed into the designated LOW threshold register 475 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold 476 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value 477 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last 478 * completed conversion was greater than the value programmed into the designated HIGH threshold 479 * register (THRn_HIGH). 0x3 = Reserved. 480 */ 481 #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) 482 #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) 483 #define ADC_DAT_THCMPCROSS_SHIFT (18U) 484 /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The 485 * most recent completed conversion on this channel had the same relationship (above or below) to 486 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the 487 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing 488 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the 489 * previous sample on this channel was above the threshold value established by the designated LOW 490 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward 491 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred 492 * - i.e. the previous sample on this channel was below the threshold value established by the 493 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 494 */ 495 #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) 496 #define ADC_DAT_CHANNEL_MASK (0x3C000000U) 497 #define ADC_DAT_CHANNEL_SHIFT (26U) 498 /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register 499 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 500 * register, etc) 501 */ 502 #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) 503 #define ADC_DAT_OVERRUN_MASK (0x40000000U) 504 #define ADC_DAT_OVERRUN_SHIFT (30U) 505 /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and 506 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit 507 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when 508 * the data related to this channel is read from either of the global SEQn_GDAT registers. This 509 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if 510 * the overrun interrupt is enabled. While it is allowed to include the same channels in both 511 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the 512 * data registers associated with any of the channels that are shared between the two sequences. Any 513 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 514 */ 515 #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) 516 #define ADC_DAT_DATAVALID_MASK (0x80000000U) 517 #define ADC_DAT_DATAVALID_SHIFT (31U) 518 /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is 519 * cleared whenever this register is read or when the data related to this channel is read from 520 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in 521 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in 522 * the data registers associated with any of the channels that are shared between the two 523 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 524 */ 525 #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) 526 /*! @} */ 527 528 /* The count of ADC_DAT */ 529 #define ADC_DAT_COUNT (12U) 530 531 /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 532 /*! @{ */ 533 #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) 534 #define ADC_THR0_LOW_THRLOW_SHIFT (4U) 535 /*! THRLOW - Low threshold value against which ADC results will be compared 536 */ 537 #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) 538 /*! @} */ 539 540 /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 541 /*! @{ */ 542 #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) 543 #define ADC_THR1_LOW_THRLOW_SHIFT (4U) 544 /*! THRLOW - Low threshold value against which ADC results will be compared 545 */ 546 #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) 547 /*! @} */ 548 549 /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 550 /*! @{ */ 551 #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) 552 #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) 553 /*! THRHIGH - High threshold value against which ADC results will be compared 554 */ 555 #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) 556 /*! @} */ 557 558 /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 559 /*! @{ */ 560 #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) 561 #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) 562 /*! THRHIGH - High threshold value against which ADC results will be compared 563 */ 564 #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) 565 /*! @} */ 566 567 /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ 568 /*! @{ */ 569 #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) 570 #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) 571 /*! CH0_THRSEL - Threshold select for channel 0. 572 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. 573 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. 574 */ 575 #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) 576 #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) 577 #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) 578 /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0. 579 */ 580 #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) 581 #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) 582 #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) 583 /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0. 584 */ 585 #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) 586 #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) 587 #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) 588 /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0. 589 */ 590 #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) 591 #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) 592 #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) 593 /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0. 594 */ 595 #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) 596 #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) 597 #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) 598 /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0. 599 */ 600 #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) 601 #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) 602 #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) 603 /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0. 604 */ 605 #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) 606 #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) 607 #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) 608 /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0. 609 */ 610 #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) 611 #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) 612 #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) 613 /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0. 614 */ 615 #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) 616 #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) 617 #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) 618 /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0. 619 */ 620 #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) 621 #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) 622 #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) 623 /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0. 624 */ 625 #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) 626 #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) 627 #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) 628 /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0. 629 */ 630 #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) 631 /*! @} */ 632 633 /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ 634 /*! @{ */ 635 #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) 636 #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) 637 /*! SEQA_INTEN - Sequence A interrupt enable. 638 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. 639 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of 640 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of 641 * conversions, depending on the MODE bit in the SEQA_CTRL register. 642 */ 643 #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) 644 #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) 645 #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) 646 /*! SEQB_INTEN - Sequence B interrupt enable. 647 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. 648 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of 649 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of 650 * conversions, depending on the MODE bit in the SEQB_CTRL register. 651 */ 652 #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) 653 #define ADC_INTEN_OVR_INTEN_MASK (0x4U) 654 #define ADC_INTEN_OVR_INTEN_SHIFT (2U) 655 /*! OVR_INTEN - Overrun interrupt enable. 656 * 0b0..Disabled. The overrun interrupt is disabled. 657 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel 658 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular 659 * sequence is 0, then an overrun in the global data register for that sequence will also cause this 660 * interrupt/DMA trigger to be asserted. 661 */ 662 #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) 663 #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) 664 #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) 665 /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. 666 * 0b00..Disabled. 667 * 0b01..Outside threshold. 668 * 0b10..Crossing threshold. 669 * 0b11..Reserved 670 */ 671 #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) 672 #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) 673 #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) 674 /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0. 675 */ 676 #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) 677 #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) 678 #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) 679 /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0. 680 */ 681 #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) 682 #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) 683 #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) 684 /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0. 685 */ 686 #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) 687 #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) 688 #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) 689 /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0. 690 */ 691 #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) 692 #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) 693 #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) 694 /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0. 695 */ 696 #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) 697 #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) 698 #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) 699 /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0. 700 */ 701 #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) 702 #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) 703 #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) 704 /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0. 705 */ 706 #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) 707 #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) 708 #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) 709 /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0. 710 */ 711 #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) 712 #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) 713 #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) 714 /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0. 715 */ 716 #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) 717 #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) 718 #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) 719 /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0. 720 */ 721 #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) 722 #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) 723 #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) 724 /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0. 725 */ 726 #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) 727 /*! @} */ 728 729 /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ 730 /*! @{ */ 731 #define ADC_FLAGS_THCMP0_MASK (0x1U) 732 #define ADC_FLAGS_THCMP0_SHIFT (0U) 733 /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or 734 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by 735 * writing a 1. 736 */ 737 #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) 738 #define ADC_FLAGS_THCMP1_MASK (0x2U) 739 #define ADC_FLAGS_THCMP1_SHIFT (1U) 740 /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0. 741 */ 742 #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) 743 #define ADC_FLAGS_THCMP2_MASK (0x4U) 744 #define ADC_FLAGS_THCMP2_SHIFT (2U) 745 /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0. 746 */ 747 #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) 748 #define ADC_FLAGS_THCMP3_MASK (0x8U) 749 #define ADC_FLAGS_THCMP3_SHIFT (3U) 750 /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0. 751 */ 752 #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) 753 #define ADC_FLAGS_THCMP4_MASK (0x10U) 754 #define ADC_FLAGS_THCMP4_SHIFT (4U) 755 /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0. 756 */ 757 #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) 758 #define ADC_FLAGS_THCMP5_MASK (0x20U) 759 #define ADC_FLAGS_THCMP5_SHIFT (5U) 760 /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0. 761 */ 762 #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) 763 #define ADC_FLAGS_THCMP6_MASK (0x40U) 764 #define ADC_FLAGS_THCMP6_SHIFT (6U) 765 /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0. 766 */ 767 #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) 768 #define ADC_FLAGS_THCMP7_MASK (0x80U) 769 #define ADC_FLAGS_THCMP7_SHIFT (7U) 770 /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0. 771 */ 772 #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) 773 #define ADC_FLAGS_THCMP8_MASK (0x100U) 774 #define ADC_FLAGS_THCMP8_SHIFT (8U) 775 /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0. 776 */ 777 #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) 778 #define ADC_FLAGS_THCMP9_MASK (0x200U) 779 #define ADC_FLAGS_THCMP9_SHIFT (9U) 780 /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0. 781 */ 782 #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) 783 #define ADC_FLAGS_THCMP10_MASK (0x400U) 784 #define ADC_FLAGS_THCMP10_SHIFT (10U) 785 /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0. 786 */ 787 #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) 788 #define ADC_FLAGS_THCMP11_MASK (0x800U) 789 #define ADC_FLAGS_THCMP11_SHIFT (11U) 790 /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0. 791 */ 792 #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) 793 #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) 794 #define ADC_FLAGS_OVERRUN0_SHIFT (12U) 795 /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0 796 */ 797 #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) 798 #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) 799 #define ADC_FLAGS_OVERRUN1_SHIFT (13U) 800 /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1 801 */ 802 #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) 803 #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) 804 #define ADC_FLAGS_OVERRUN2_SHIFT (14U) 805 /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2 806 */ 807 #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) 808 #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) 809 #define ADC_FLAGS_OVERRUN3_SHIFT (15U) 810 /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3 811 */ 812 #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) 813 #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) 814 #define ADC_FLAGS_OVERRUN4_SHIFT (16U) 815 /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4 816 */ 817 #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) 818 #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) 819 #define ADC_FLAGS_OVERRUN5_SHIFT (17U) 820 /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5 821 */ 822 #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) 823 #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) 824 #define ADC_FLAGS_OVERRUN6_SHIFT (18U) 825 /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6 826 */ 827 #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) 828 #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) 829 #define ADC_FLAGS_OVERRUN7_SHIFT (19U) 830 /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7 831 */ 832 #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) 833 #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) 834 #define ADC_FLAGS_OVERRUN8_SHIFT (20U) 835 /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8 836 */ 837 #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) 838 #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) 839 #define ADC_FLAGS_OVERRUN9_SHIFT (21U) 840 /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9 841 */ 842 #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) 843 #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) 844 #define ADC_FLAGS_OVERRUN10_SHIFT (22U) 845 /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10 846 */ 847 #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) 848 #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) 849 #define ADC_FLAGS_OVERRUN11_SHIFT (23U) 850 /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11 851 */ 852 #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) 853 #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) 854 #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) 855 /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register 856 */ 857 #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) 858 #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) 859 #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) 860 /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register 861 */ 862 #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) 863 #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) 864 #define ADC_FLAGS_SEQA_INT_SHIFT (28U) 865 /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, 866 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which 867 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared 868 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register 869 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be 870 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN 871 * register. 872 */ 873 #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) 874 #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) 875 #define ADC_FLAGS_SEQB_INT_SHIFT (29U) 876 /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, 877 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which 878 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared 879 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register 880 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be 881 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN 882 * register. 883 */ 884 #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) 885 #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) 886 #define ADC_FLAGS_THCMP_INT_SHIFT (30U) 887 /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in 888 * the lower bits of this register are set to 1 (due to an enabled out-of-range or 889 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be 890 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared 891 * when all of the individual threshold flags are cleared via writing 1s to those bits. 892 */ 893 #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) 894 #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) 895 #define ADC_FLAGS_OVR_INT_SHIFT (31U) 896 /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data 897 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers 898 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this 899 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all 900 * of the individual overrun bits have been cleared via reading the corresponding data registers. 901 */ 902 #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) 903 /*! @} */ 904 905 /*! @name STARTUP - ADC Startup register. */ 906 /*! @{ */ 907 #define ADC_STARTUP_ADC_ENA_MASK (0x1U) 908 #define ADC_STARTUP_ADC_ENA_SHIFT (0U) 909 /*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared 910 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds 911 * after the ADC is powered up (typically by altering a system-level ADC power control bit). 912 */ 913 #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) 914 #define ADC_STARTUP_ADC_INIT_MASK (0x2U) 915 #define ADC_STARTUP_ADC_INIT_SHIFT (1U) 916 /*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine 917 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not 918 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is 919 * required if a calibration is not performed. It will also reload the stored calibration value from 920 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the 921 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or 922 * an ADC dummy conversion cycle is required. It should not be set during the same write that 923 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically 924 * when the 'dummy' conversion cycle completes. 925 */ 926 #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) 927 /*! @} */ 928 929 /*! @name CALIB - ADC Calibration register. */ 930 /*! @{ */ 931 #define ADC_CALIB_CALIB_MASK (0x1U) 932 #define ADC_CALIB_CALIB_SHIFT (0U) 933 /*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can 934 * only be set to a '1' by software. It is cleared automatically when the calibration cycle 935 * completes. 936 */ 937 #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) 938 #define ADC_CALIB_CALREQD_MASK (0x2U) 939 #define ADC_CALIB_CALREQD_SHIFT (1U) 940 /*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when 941 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was 942 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to 943 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP 944 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. 945 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks 946 * required for calibration. 947 */ 948 #define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) 949 #define ADC_CALIB_CALVALUE_MASK (0x1FCU) 950 #define ADC_CALIB_CALVALUE_SHIFT (2U) 951 /*! CALVALUE - Calibration Value. This read-only field displays the calibration value established 952 * during last calibration cycle. This value is not typically of any use to the user. 953 */ 954 #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) 955 /*! @} */ 956 957 958 /*! 959 * @} 960 */ /* end of group ADC_Register_Masks */ 961 962 963 /* ADC - Peripheral instance base addresses */ 964 /** Peripheral ADC0 base address */ 965 #define ADC0_BASE (0x400A0000u) 966 /** Peripheral ADC0 base pointer */ 967 #define ADC0 ((ADC_Type *)ADC0_BASE) 968 /** Array initializer of ADC peripheral base addresses */ 969 #define ADC_BASE_ADDRS { ADC0_BASE } 970 /** Array initializer of ADC peripheral base pointers */ 971 #define ADC_BASE_PTRS { ADC0 } 972 /** Interrupt vectors for the ADC peripheral type */ 973 #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } 974 #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } 975 976 /*! 977 * @} 978 */ /* end of group ADC_Peripheral_Access_Layer */ 979 980 981 /* ---------------------------------------------------------------------------- 982 -- ASYNC_SYSCON Peripheral Access Layer 983 ---------------------------------------------------------------------------- */ 984 985 /*! 986 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer 987 * @{ 988 */ 989 990 /** ASYNC_SYSCON - Register Layout Typedef */ 991 typedef struct { 992 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ 993 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ 994 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ 995 uint8_t RESERVED_0[4]; 996 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ 997 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ 998 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ 999 uint8_t RESERVED_1[4]; 1000 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ 1001 } ASYNC_SYSCON_Type; 1002 1003 /* ---------------------------------------------------------------------------- 1004 -- ASYNC_SYSCON Register Masks 1005 ---------------------------------------------------------------------------- */ 1006 1007 /*! 1008 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks 1009 * @{ 1010 */ 1011 1012 /*! @name ASYNCPRESETCTRL - Async peripheral reset control */ 1013 /*! @{ */ 1014 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) 1015 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) 1016 /*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 1017 */ 1018 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) 1019 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) 1020 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) 1021 /*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 1022 */ 1023 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) 1024 /*! @} */ 1025 1026 /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ 1027 /*! @{ */ 1028 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) 1029 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) 1030 /*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the 1031 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1032 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 1033 */ 1034 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) 1035 /*! @} */ 1036 1037 /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ 1038 /*! @{ */ 1039 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) 1040 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) 1041 /*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the 1042 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1043 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 1044 */ 1045 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) 1046 /*! @} */ 1047 1048 /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ 1049 /*! @{ */ 1050 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) 1051 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) 1052 /*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable. 1053 */ 1054 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) 1055 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) 1056 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) 1057 /*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable. 1058 */ 1059 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) 1060 /*! @} */ 1061 1062 /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ 1063 /*! @{ */ 1064 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) 1065 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) 1066 /*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the 1067 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1068 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. 1069 */ 1070 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) 1071 /*! @} */ 1072 1073 /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ 1074 /*! @{ */ 1075 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) 1076 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) 1077 /*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the 1078 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in 1079 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them. 1080 */ 1081 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) 1082 /*! @} */ 1083 1084 /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ 1085 /*! @{ */ 1086 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) 1087 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) 1088 /*! SEL - Clock source for asynchronous clock source selector A 1089 * 0b00..Main clock 1090 * 0b01..FRO 12 MHz 1091 * 0b10..Reserved setting 1092 * 0b11..Reserved setting 1093 */ 1094 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) 1095 /*! @} */ 1096 1097 1098 /*! 1099 * @} 1100 */ /* end of group ASYNC_SYSCON_Register_Masks */ 1101 1102 1103 /* ASYNC_SYSCON - Peripheral instance base addresses */ 1104 /** Peripheral ASYNC_SYSCON base address */ 1105 #define ASYNC_SYSCON_BASE (0x40040000u) 1106 /** Peripheral ASYNC_SYSCON base pointer */ 1107 #define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) 1108 /** Array initializer of ASYNC_SYSCON peripheral base addresses */ 1109 #define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } 1110 /** Array initializer of ASYNC_SYSCON peripheral base pointers */ 1111 #define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } 1112 1113 /*! 1114 * @} 1115 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ 1116 1117 1118 /* ---------------------------------------------------------------------------- 1119 -- CRC Peripheral Access Layer 1120 ---------------------------------------------------------------------------- */ 1121 1122 /*! 1123 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 1124 * @{ 1125 */ 1126 1127 /** CRC - Register Layout Typedef */ 1128 typedef struct { 1129 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ 1130 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ 1131 union { /* offset: 0x8 */ 1132 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ 1133 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ 1134 }; 1135 } CRC_Type; 1136 1137 /* ---------------------------------------------------------------------------- 1138 -- CRC Register Masks 1139 ---------------------------------------------------------------------------- */ 1140 1141 /*! 1142 * @addtogroup CRC_Register_Masks CRC Register Masks 1143 * @{ 1144 */ 1145 1146 /*! @name MODE - CRC mode register */ 1147 /*! @{ */ 1148 #define CRC_MODE_CRC_POLY_MASK (0x3U) 1149 #define CRC_MODE_CRC_POLY_SHIFT (0U) 1150 /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 1151 */ 1152 #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) 1153 #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) 1154 #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) 1155 /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 1156 */ 1157 #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) 1158 #define CRC_MODE_CMPL_WR_MASK (0x8U) 1159 #define CRC_MODE_CMPL_WR_SHIFT (3U) 1160 /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 1161 */ 1162 #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) 1163 #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) 1164 #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) 1165 /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 1166 */ 1167 #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) 1168 #define CRC_MODE_CMPL_SUM_MASK (0x20U) 1169 #define CRC_MODE_CMPL_SUM_SHIFT (5U) 1170 /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 1171 */ 1172 #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) 1173 /*! @} */ 1174 1175 /*! @name SEED - CRC seed register */ 1176 /*! @{ */ 1177 #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) 1178 #define CRC_SEED_CRC_SEED_SHIFT (0U) 1179 /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with 1180 * selected bit order and 1's complement pre-processes. A write access to this register will 1181 * overrule the CRC calculation in progresses. 1182 */ 1183 #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) 1184 /*! @} */ 1185 1186 /*! @name SUM - CRC checksum register */ 1187 /*! @{ */ 1188 #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) 1189 #define CRC_SUM_CRC_SUM_SHIFT (0U) 1190 /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 1191 */ 1192 #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) 1193 /*! @} */ 1194 1195 /*! @name WR_DATA - CRC data register */ 1196 /*! @{ */ 1197 #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) 1198 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) 1199 /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with 1200 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and 1201 * accept back-to-back transactions. 1202 */ 1203 #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) 1204 /*! @} */ 1205 1206 1207 /*! 1208 * @} 1209 */ /* end of group CRC_Register_Masks */ 1210 1211 1212 /* CRC - Peripheral instance base addresses */ 1213 /** Peripheral CRC_ENGINE base address */ 1214 #define CRC_ENGINE_BASE (0x40095000u) 1215 /** Peripheral CRC_ENGINE base pointer */ 1216 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) 1217 /** Array initializer of CRC peripheral base addresses */ 1218 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } 1219 /** Array initializer of CRC peripheral base pointers */ 1220 #define CRC_BASE_PTRS { CRC_ENGINE } 1221 1222 /*! 1223 * @} 1224 */ /* end of group CRC_Peripheral_Access_Layer */ 1225 1226 1227 /* ---------------------------------------------------------------------------- 1228 -- CTIMER Peripheral Access Layer 1229 ---------------------------------------------------------------------------- */ 1230 1231 /*! 1232 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer 1233 * @{ 1234 */ 1235 1236 /** CTIMER - Register Layout Typedef */ 1237 typedef struct { 1238 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ 1239 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ 1240 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ 1241 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ 1242 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ 1243 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ 1244 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ 1245 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ 1246 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ 1247 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ 1248 uint8_t RESERVED_0[48]; 1249 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ 1250 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ 1251 } CTIMER_Type; 1252 1253 /* ---------------------------------------------------------------------------- 1254 -- CTIMER Register Masks 1255 ---------------------------------------------------------------------------- */ 1256 1257 /*! 1258 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks 1259 * @{ 1260 */ 1261 1262 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ 1263 /*! @{ */ 1264 #define CTIMER_IR_MR0INT_MASK (0x1U) 1265 #define CTIMER_IR_MR0INT_SHIFT (0U) 1266 /*! MR0INT - Interrupt flag for match channel 0. 1267 */ 1268 #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) 1269 #define CTIMER_IR_MR1INT_MASK (0x2U) 1270 #define CTIMER_IR_MR1INT_SHIFT (1U) 1271 /*! MR1INT - Interrupt flag for match channel 1. 1272 */ 1273 #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) 1274 #define CTIMER_IR_MR2INT_MASK (0x4U) 1275 #define CTIMER_IR_MR2INT_SHIFT (2U) 1276 /*! MR2INT - Interrupt flag for match channel 2. 1277 */ 1278 #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) 1279 #define CTIMER_IR_MR3INT_MASK (0x8U) 1280 #define CTIMER_IR_MR3INT_SHIFT (3U) 1281 /*! MR3INT - Interrupt flag for match channel 3. 1282 */ 1283 #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) 1284 #define CTIMER_IR_CR0INT_MASK (0x10U) 1285 #define CTIMER_IR_CR0INT_SHIFT (4U) 1286 /*! CR0INT - Interrupt flag for capture channel 0 event. 1287 */ 1288 #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) 1289 #define CTIMER_IR_CR1INT_MASK (0x20U) 1290 #define CTIMER_IR_CR1INT_SHIFT (5U) 1291 /*! CR1INT - Interrupt flag for capture channel 1 event. 1292 */ 1293 #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) 1294 #define CTIMER_IR_CR2INT_MASK (0x40U) 1295 #define CTIMER_IR_CR2INT_SHIFT (6U) 1296 /*! CR2INT - Interrupt flag for capture channel 2 event. 1297 */ 1298 #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) 1299 #define CTIMER_IR_CR3INT_MASK (0x80U) 1300 #define CTIMER_IR_CR3INT_SHIFT (7U) 1301 /*! CR3INT - Interrupt flag for capture channel 3 event. 1302 */ 1303 #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) 1304 /*! @} */ 1305 1306 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ 1307 /*! @{ */ 1308 #define CTIMER_TCR_CEN_MASK (0x1U) 1309 #define CTIMER_TCR_CEN_SHIFT (0U) 1310 /*! CEN - Counter enable. 1311 * 0b0..Disabled.The counters are disabled. 1312 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. 1313 */ 1314 #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) 1315 #define CTIMER_TCR_CRST_MASK (0x2U) 1316 #define CTIMER_TCR_CRST_SHIFT (1U) 1317 /*! CRST - Counter reset. 1318 * 0b0..Disabled. Do nothing. 1319 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of 1320 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 1321 */ 1322 #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) 1323 /*! @} */ 1324 1325 /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ 1326 /*! @{ */ 1327 #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) 1328 #define CTIMER_TC_TCVAL_SHIFT (0U) 1329 /*! TCVAL - Timer counter value. 1330 */ 1331 #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) 1332 /*! @} */ 1333 1334 /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ 1335 /*! @{ */ 1336 #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) 1337 #define CTIMER_PR_PRVAL_SHIFT (0U) 1338 /*! PRVAL - Prescale counter value. 1339 */ 1340 #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) 1341 /*! @} */ 1342 1343 /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ 1344 /*! @{ */ 1345 #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) 1346 #define CTIMER_PC_PCVAL_SHIFT (0U) 1347 /*! PCVAL - Prescale counter value. 1348 */ 1349 #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) 1350 /*! @} */ 1351 1352 /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ 1353 /*! @{ */ 1354 #define CTIMER_MCR_MR0I_MASK (0x1U) 1355 #define CTIMER_MCR_MR0I_SHIFT (0U) 1356 /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. 1357 */ 1358 #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) 1359 #define CTIMER_MCR_MR0R_MASK (0x2U) 1360 #define CTIMER_MCR_MR0R_SHIFT (1U) 1361 /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. 1362 */ 1363 #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) 1364 #define CTIMER_MCR_MR0S_MASK (0x4U) 1365 #define CTIMER_MCR_MR0S_SHIFT (2U) 1366 /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. 1367 */ 1368 #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) 1369 #define CTIMER_MCR_MR1I_MASK (0x8U) 1370 #define CTIMER_MCR_MR1I_SHIFT (3U) 1371 /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = 1372 * disabled. 1 = enabled. 0 = disabled. 1 = enabled. 1373 */ 1374 #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) 1375 #define CTIMER_MCR_MR1R_MASK (0x10U) 1376 #define CTIMER_MCR_MR1R_SHIFT (4U) 1377 /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. 1378 */ 1379 #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) 1380 #define CTIMER_MCR_MR1S_MASK (0x20U) 1381 #define CTIMER_MCR_MR1S_SHIFT (5U) 1382 /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. 1383 */ 1384 #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) 1385 #define CTIMER_MCR_MR2I_MASK (0x40U) 1386 #define CTIMER_MCR_MR2I_SHIFT (6U) 1387 /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. 1388 */ 1389 #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) 1390 #define CTIMER_MCR_MR2R_MASK (0x80U) 1391 #define CTIMER_MCR_MR2R_SHIFT (7U) 1392 /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. 1393 */ 1394 #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) 1395 #define CTIMER_MCR_MR2S_MASK (0x100U) 1396 #define CTIMER_MCR_MR2S_SHIFT (8U) 1397 /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. 1398 */ 1399 #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) 1400 #define CTIMER_MCR_MR3I_MASK (0x200U) 1401 #define CTIMER_MCR_MR3I_SHIFT (9U) 1402 /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. 1403 */ 1404 #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) 1405 #define CTIMER_MCR_MR3R_MASK (0x400U) 1406 #define CTIMER_MCR_MR3R_SHIFT (10U) 1407 /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. 1408 */ 1409 #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) 1410 #define CTIMER_MCR_MR3S_MASK (0x800U) 1411 #define CTIMER_MCR_MR3S_SHIFT (11U) 1412 /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. 1413 */ 1414 #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) 1415 /*! @} */ 1416 1417 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ 1418 /*! @{ */ 1419 #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) 1420 #define CTIMER_MR_MATCH_SHIFT (0U) 1421 /*! MATCH - Timer counter match value. 1422 */ 1423 #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) 1424 /*! @} */ 1425 1426 /* The count of CTIMER_MR */ 1427 #define CTIMER_MR_COUNT (4U) 1428 1429 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ 1430 /*! @{ */ 1431 #define CTIMER_CCR_CAP0RE_MASK (0x1U) 1432 #define CTIMER_CCR_CAP0RE_SHIFT (0U) 1433 /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with 1434 * the contents of TC. 0 = disabled. 1 = enabled. 1435 */ 1436 #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) 1437 #define CTIMER_CCR_CAP0FE_MASK (0x2U) 1438 #define CTIMER_CCR_CAP0FE_SHIFT (1U) 1439 /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with 1440 * the contents of TC. 0 = disabled. 1 = enabled. 1441 */ 1442 #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) 1443 #define CTIMER_CCR_CAP0I_MASK (0x4U) 1444 #define CTIMER_CCR_CAP0I_SHIFT (2U) 1445 /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 1446 */ 1447 #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) 1448 #define CTIMER_CCR_CAP1RE_MASK (0x8U) 1449 #define CTIMER_CCR_CAP1RE_SHIFT (3U) 1450 /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with 1451 * the contents of TC. 0 = disabled. 1 = enabled. 1452 */ 1453 #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) 1454 #define CTIMER_CCR_CAP1FE_MASK (0x10U) 1455 #define CTIMER_CCR_CAP1FE_SHIFT (4U) 1456 /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with 1457 * the contents of TC. 0 = disabled. 1 = enabled. 1458 */ 1459 #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) 1460 #define CTIMER_CCR_CAP1I_MASK (0x20U) 1461 #define CTIMER_CCR_CAP1I_SHIFT (5U) 1462 /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 1463 */ 1464 #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) 1465 #define CTIMER_CCR_CAP2RE_MASK (0x40U) 1466 #define CTIMER_CCR_CAP2RE_SHIFT (6U) 1467 /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with 1468 * the contents of TC. 0 = disabled. 1 = enabled. 1469 */ 1470 #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) 1471 #define CTIMER_CCR_CAP2FE_MASK (0x80U) 1472 #define CTIMER_CCR_CAP2FE_SHIFT (7U) 1473 /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with 1474 * the contents of TC. 0 = disabled. 1 = enabled. 1475 */ 1476 #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) 1477 #define CTIMER_CCR_CAP2I_MASK (0x100U) 1478 #define CTIMER_CCR_CAP2I_SHIFT (8U) 1479 /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 1480 */ 1481 #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) 1482 #define CTIMER_CCR_CAP3RE_MASK (0x200U) 1483 #define CTIMER_CCR_CAP3RE_SHIFT (9U) 1484 /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with 1485 * the contents of TC. 0 = disabled. 1 = enabled. 1486 */ 1487 #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) 1488 #define CTIMER_CCR_CAP3FE_MASK (0x400U) 1489 #define CTIMER_CCR_CAP3FE_SHIFT (10U) 1490 /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with 1491 * the contents of TC. 0 = disabled. 1 = enabled. 1492 */ 1493 #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) 1494 #define CTIMER_CCR_CAP3I_MASK (0x800U) 1495 #define CTIMER_CCR_CAP3I_SHIFT (11U) 1496 /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. 1497 */ 1498 #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) 1499 /*! @} */ 1500 1501 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ 1502 /*! @{ */ 1503 #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) 1504 #define CTIMER_CR_CAP_SHIFT (0U) 1505 /*! CAP - Timer counter capture value. 1506 */ 1507 #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) 1508 /*! @} */ 1509 1510 /* The count of CTIMER_CR */ 1511 #define CTIMER_CR_COUNT (4U) 1512 1513 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ 1514 /*! @{ */ 1515 #define CTIMER_EMR_EM0_MASK (0x1U) 1516 #define CTIMER_EMR_EM0_SHIFT (0U) 1517 /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output 1518 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, 1519 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if 1520 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1521 */ 1522 #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) 1523 #define CTIMER_EMR_EM1_MASK (0x2U) 1524 #define CTIMER_EMR_EM1_SHIFT (1U) 1525 /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output 1526 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, 1527 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if 1528 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1529 */ 1530 #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) 1531 #define CTIMER_EMR_EM2_MASK (0x4U) 1532 #define CTIMER_EMR_EM2_SHIFT (2U) 1533 /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output 1534 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, 1535 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if 1536 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1537 */ 1538 #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) 1539 #define CTIMER_EMR_EM3_MASK (0x8U) 1540 #define CTIMER_EMR_EM3_SHIFT (3U) 1541 /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output 1542 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, 1543 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins 1544 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1545 */ 1546 #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) 1547 #define CTIMER_EMR_EMC0_MASK (0x30U) 1548 #define CTIMER_EMR_EMC0_SHIFT (4U) 1549 /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. 1550 * 0b00..Do Nothing. 1551 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 1552 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 1553 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1554 */ 1555 #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) 1556 #define CTIMER_EMR_EMC1_MASK (0xC0U) 1557 #define CTIMER_EMR_EMC1_SHIFT (6U) 1558 /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. 1559 * 0b00..Do Nothing. 1560 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 1561 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 1562 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1563 */ 1564 #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) 1565 #define CTIMER_EMR_EMC2_MASK (0x300U) 1566 #define CTIMER_EMR_EMC2_SHIFT (8U) 1567 /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. 1568 * 0b00..Do Nothing. 1569 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 1570 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 1571 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1572 */ 1573 #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) 1574 #define CTIMER_EMR_EMC3_MASK (0xC00U) 1575 #define CTIMER_EMR_EMC3_SHIFT (10U) 1576 /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. 1577 * 0b00..Do Nothing. 1578 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 1579 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 1580 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1581 */ 1582 #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) 1583 /*! @} */ 1584 1585 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ 1586 /*! @{ */ 1587 #define CTIMER_CTCR_CTMODE_MASK (0x3U) 1588 #define CTIMER_CTCR_CTMODE_SHIFT (0U) 1589 /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment 1590 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC 1591 * is incremented when the Prescale Counter matches the Prescale Register. 1592 * 0b00..Timer Mode. Incremented every rising APB bus clock edge. 1593 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 1594 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 1595 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 1596 */ 1597 #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) 1598 #define CTIMER_CTCR_CINSEL_MASK (0xCU) 1599 #define CTIMER_CTCR_CINSEL_SHIFT (2U) 1600 /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which 1601 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input 1602 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be 1603 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the 1604 * same timer. 1605 * 0b00..Channel 0. CAPn.0 for CTIMERn 1606 * 0b01..Channel 1. CAPn.1 for CTIMERn 1607 * 0b10..Channel 2. CAPn.2 for CTIMERn 1608 * 0b11..Channel 3. CAPn.3 for CTIMERn 1609 */ 1610 #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) 1611 #define CTIMER_CTCR_ENCC_MASK (0x10U) 1612 #define CTIMER_CTCR_ENCC_SHIFT (4U) 1613 /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the 1614 * capture-edge event specified in bits 7:5 occurs. 1615 */ 1616 #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) 1617 #define CTIMER_CTCR_SELCC_MASK (0xE0U) 1618 #define CTIMER_CTCR_SELCC_SHIFT (5U) 1619 /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the 1620 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 1621 * 0x3 and 0x6 to 0x7 are reserved. 1622 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1623 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1624 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 1625 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 1626 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 1627 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 1628 */ 1629 #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) 1630 /*! @} */ 1631 1632 /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ 1633 /*! @{ */ 1634 #define CTIMER_PWMC_PWMEN0_MASK (0x1U) 1635 #define CTIMER_PWMC_PWMEN0_SHIFT (0U) 1636 /*! PWMEN0 - PWM mode enable for channel0. 1637 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. 1638 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. 1639 */ 1640 #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) 1641 #define CTIMER_PWMC_PWMEN1_MASK (0x2U) 1642 #define CTIMER_PWMC_PWMEN1_SHIFT (1U) 1643 /*! PWMEN1 - PWM mode enable for channel1. 1644 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. 1645 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. 1646 */ 1647 #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) 1648 #define CTIMER_PWMC_PWMEN2_MASK (0x4U) 1649 #define CTIMER_PWMC_PWMEN2_SHIFT (2U) 1650 /*! PWMEN2 - PWM mode enable for channel2. 1651 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. 1652 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. 1653 */ 1654 #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) 1655 #define CTIMER_PWMC_PWMEN3_MASK (0x8U) 1656 #define CTIMER_PWMC_PWMEN3_SHIFT (3U) 1657 /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 1658 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. 1659 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. 1660 */ 1661 #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) 1662 /*! @} */ 1663 1664 1665 /*! 1666 * @} 1667 */ /* end of group CTIMER_Register_Masks */ 1668 1669 1670 /* CTIMER - Peripheral instance base addresses */ 1671 /** Peripheral CTIMER0 base address */ 1672 #define CTIMER0_BASE (0x40008000u) 1673 /** Peripheral CTIMER0 base pointer */ 1674 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) 1675 /** Peripheral CTIMER1 base address */ 1676 #define CTIMER1_BASE (0x40009000u) 1677 /** Peripheral CTIMER1 base pointer */ 1678 #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) 1679 /** Peripheral CTIMER2 base address */ 1680 #define CTIMER2_BASE (0x40028000u) 1681 /** Peripheral CTIMER2 base pointer */ 1682 #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) 1683 /** Peripheral CTIMER3 base address */ 1684 #define CTIMER3_BASE (0x40048000u) 1685 /** Peripheral CTIMER3 base pointer */ 1686 #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) 1687 /** Peripheral CTIMER4 base address */ 1688 #define CTIMER4_BASE (0x40049000u) 1689 /** Peripheral CTIMER4 base pointer */ 1690 #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) 1691 /** Array initializer of CTIMER peripheral base addresses */ 1692 #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } 1693 /** Array initializer of CTIMER peripheral base pointers */ 1694 #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } 1695 /** Interrupt vectors for the CTIMER peripheral type */ 1696 #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, NotAvail_IRQn, CTIMER3_IRQn, NotAvail_IRQn } 1697 1698 /*! 1699 * @} 1700 */ /* end of group CTIMER_Peripheral_Access_Layer */ 1701 1702 1703 /* ---------------------------------------------------------------------------- 1704 -- DMA Peripheral Access Layer 1705 ---------------------------------------------------------------------------- */ 1706 1707 /*! 1708 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 1709 * @{ 1710 */ 1711 1712 /** DMA - Register Layout Typedef */ 1713 typedef struct { 1714 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ 1715 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ 1716 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ 1717 uint8_t RESERVED_0[20]; 1718 struct { /* offset: 0x20, array step: 0x5C */ 1719 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ 1720 uint8_t RESERVED_0[4]; 1721 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ 1722 uint8_t RESERVED_1[4]; 1723 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ 1724 uint8_t RESERVED_2[4]; 1725 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ 1726 uint8_t RESERVED_3[4]; 1727 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ 1728 uint8_t RESERVED_4[4]; 1729 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ 1730 uint8_t RESERVED_5[4]; 1731 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ 1732 uint8_t RESERVED_6[4]; 1733 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ 1734 uint8_t RESERVED_7[4]; 1735 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ 1736 uint8_t RESERVED_8[4]; 1737 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ 1738 uint8_t RESERVED_9[4]; 1739 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ 1740 uint8_t RESERVED_10[4]; 1741 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ 1742 } COMMON[1]; 1743 uint8_t RESERVED_1[900]; 1744 struct { /* offset: 0x400, array step: 0x10 */ 1745 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ 1746 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ 1747 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ 1748 uint8_t RESERVED_0[4]; 1749 } CHANNEL[20]; 1750 } DMA_Type; 1751 1752 /* ---------------------------------------------------------------------------- 1753 -- DMA Register Masks 1754 ---------------------------------------------------------------------------- */ 1755 1756 /*! 1757 * @addtogroup DMA_Register_Masks DMA Register Masks 1758 * @{ 1759 */ 1760 1761 /*! @name CTRL - DMA control. */ 1762 /*! @{ */ 1763 #define DMA_CTRL_ENABLE_MASK (0x1U) 1764 #define DMA_CTRL_ENABLE_SHIFT (0U) 1765 /*! ENABLE - DMA controller master enable. 1766 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when 1767 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 1768 * 0b1..Enabled. The DMA controller is enabled. 1769 */ 1770 #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) 1771 /*! @} */ 1772 1773 /*! @name INTSTAT - Interrupt status. */ 1774 /*! @{ */ 1775 #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) 1776 #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) 1777 /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. 1778 * 0b0..Not pending. No enabled interrupts are pending. 1779 * 0b1..Pending. At least one enabled interrupt is pending. 1780 */ 1781 #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) 1782 #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) 1783 #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) 1784 /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. 1785 * 0b0..Not pending. No error interrupts are pending. 1786 * 0b1..Pending. At least one error interrupt is pending. 1787 */ 1788 #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) 1789 /*! @} */ 1790 1791 /*! @name SRAMBASE - SRAM address of the channel configuration table. */ 1792 /*! @{ */ 1793 #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) 1794 #define DMA_SRAMBASE_OFFSET_SHIFT (9U) 1795 /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the 1796 * table must begin on a 512 byte boundary. 1797 */ 1798 #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) 1799 /*! @} */ 1800 1801 /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ 1802 /*! @{ */ 1803 #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) 1804 #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) 1805 /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = 1806 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 1807 */ 1808 #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) 1809 /*! @} */ 1810 1811 /* The count of DMA_COMMON_ENABLESET */ 1812 #define DMA_COMMON_ENABLESET_COUNT (1U) 1813 1814 /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ 1815 /*! @{ */ 1816 #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) 1817 #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) 1818 /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears 1819 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits 1820 * are reserved. 1821 */ 1822 #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) 1823 /*! @} */ 1824 1825 /* The count of DMA_COMMON_ENABLECLR */ 1826 #define DMA_COMMON_ENABLECLR_COUNT (1U) 1827 1828 /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ 1829 /*! @{ */ 1830 #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) 1831 #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) 1832 /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = 1833 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 1834 */ 1835 #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) 1836 /*! @} */ 1837 1838 /* The count of DMA_COMMON_ACTIVE */ 1839 #define DMA_COMMON_ACTIVE_COUNT (1U) 1840 1841 /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ 1842 /*! @{ */ 1843 #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) 1844 #define DMA_COMMON_BUSY_BSY_SHIFT (0U) 1845 /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = 1846 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 1847 */ 1848 #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) 1849 /*! @} */ 1850 1851 /* The count of DMA_COMMON_BUSY */ 1852 #define DMA_COMMON_BUSY_COUNT (1U) 1853 1854 /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ 1855 /*! @{ */ 1856 #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) 1857 #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) 1858 /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of 1859 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is 1860 * not active. 1 = error interrupt is active. 1861 */ 1862 #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) 1863 /*! @} */ 1864 1865 /* The count of DMA_COMMON_ERRINT */ 1866 #define DMA_COMMON_ERRINT_COUNT (1U) 1867 1868 /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ 1869 /*! @{ */ 1870 #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) 1871 #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) 1872 /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The 1873 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = 1874 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 1875 */ 1876 #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) 1877 /*! @} */ 1878 1879 /* The count of DMA_COMMON_INTENSET */ 1880 #define DMA_COMMON_INTENSET_COUNT (1U) 1881 1882 /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ 1883 /*! @{ */ 1884 #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) 1885 #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) 1886 /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n 1887 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are 1888 * reserved. 1889 */ 1890 #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) 1891 /*! @} */ 1892 1893 /* The count of DMA_COMMON_INTENCLR */ 1894 #define DMA_COMMON_INTENCLR_COUNT (1U) 1895 1896 /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ 1897 /*! @{ */ 1898 #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) 1899 #define DMA_COMMON_INTA_IA_SHIFT (0U) 1900 /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of 1901 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel 1902 * interrupt A is not active. 1 = the DMA channel interrupt A is active. 1903 */ 1904 #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) 1905 /*! @} */ 1906 1907 /* The count of DMA_COMMON_INTA */ 1908 #define DMA_COMMON_INTA_COUNT (1U) 1909 1910 /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ 1911 /*! @{ */ 1912 #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) 1913 #define DMA_COMMON_INTB_IB_SHIFT (0U) 1914 /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of 1915 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel 1916 * interrupt B is not active. 1 = the DMA channel interrupt B is active. 1917 */ 1918 #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) 1919 /*! @} */ 1920 1921 /* The count of DMA_COMMON_INTB */ 1922 #define DMA_COMMON_INTB_COUNT (1U) 1923 1924 /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ 1925 /*! @{ */ 1926 #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) 1927 #define DMA_COMMON_SETVALID_SV_SHIFT (0U) 1928 /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits 1929 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the 1930 * VALIDPENDING control bit for DMA channel n 1931 */ 1932 #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) 1933 /*! @} */ 1934 1935 /* The count of DMA_COMMON_SETVALID */ 1936 #define DMA_COMMON_SETVALID_COUNT (1U) 1937 1938 /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ 1939 /*! @{ */ 1940 #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) 1941 #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) 1942 /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number 1943 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = 1944 * sets the TRIG bit for DMA channel n. 1945 */ 1946 #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) 1947 /*! @} */ 1948 1949 /* The count of DMA_COMMON_SETTRIG */ 1950 #define DMA_COMMON_SETTRIG_COUNT (1U) 1951 1952 /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ 1953 /*! @{ */ 1954 #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) 1955 #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) 1956 /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1957 * 1 = aborts DMA operations on channel n. 1958 */ 1959 #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) 1960 /*! @} */ 1961 1962 /* The count of DMA_COMMON_ABORT */ 1963 #define DMA_COMMON_ABORT_COUNT (1U) 1964 1965 /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ 1966 /*! @{ */ 1967 #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) 1968 #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) 1969 /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory 1970 * move, any peripheral DMA request associated with that channel can be disabled to prevent any 1971 * interaction between the peripheral and the DMA controller. 1972 * 0b0..Disabled. Peripheral DMA requests are disabled. 1973 * 0b1..Enabled. Peripheral DMA requests are enabled. 1974 */ 1975 #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) 1976 #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) 1977 #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) 1978 /*! HWTRIGEN - Hardware Triggering Enable for this channel. 1979 * 0b0..Disabled. Hardware triggering is not used. 1980 * 0b1..Enabled. Use hardware triggering. 1981 */ 1982 #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) 1983 #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) 1984 #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) 1985 /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 1986 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 1987 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 1988 */ 1989 #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) 1990 #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) 1991 #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) 1992 /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. 1993 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. 1994 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 1995 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the 1996 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger 1997 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the 1998 * current BURSTPOWER length are completed. 1999 */ 2000 #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) 2001 #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) 2002 #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) 2003 /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 2004 * 0b0..Single transfer. Hardware trigger causes a single transfer. 2005 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a 2006 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a 2007 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is 2008 * complete. 2009 */ 2010 #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) 2011 #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) 2012 #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) 2013 /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when 2014 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). 2015 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many 2016 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that 2017 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: 2018 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 2019 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The 2020 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even 2021 * multiple of the burst size. 2022 */ 2023 #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) 2024 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) 2025 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) 2026 /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 2027 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this 2028 * could be used to read several sequential registers from a peripheral for each DMA burst, 2029 * reading the same registers again for each burst. 2030 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. 2031 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. 2032 */ 2033 #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) 2034 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) 2035 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) 2036 /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 2037 * 'wrapped', meaning that the destination address range for each burst will be the same. As an 2038 * example, this could be used to write several sequential registers to a peripheral for each DMA 2039 * burst, writing the same registers again for each burst. 2040 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. 2041 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. 2042 */ 2043 #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) 2044 #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) 2045 #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) 2046 /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority 2047 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 2048 */ 2049 #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) 2050 /*! @} */ 2051 2052 /* The count of DMA_CHANNEL_CFG */ 2053 #define DMA_CHANNEL_CFG_COUNT (20U) 2054 2055 /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ 2056 /*! @{ */ 2057 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) 2058 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) 2059 /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the 2060 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 2061 * 0b0..No effect. No effect on DMA operation. 2062 * 0b1..Valid pending. 2063 */ 2064 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) 2065 #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) 2066 #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) 2067 /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is 2068 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2069 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 2070 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 2071 */ 2072 #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) 2073 /*! @} */ 2074 2075 /* The count of DMA_CHANNEL_CTLSTAT */ 2076 #define DMA_CHANNEL_CTLSTAT_COUNT (20U) 2077 2078 /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ 2079 /*! @{ */ 2080 #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) 2081 #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) 2082 /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor 2083 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 2084 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 2085 * 0b1..Valid. The current channel descriptor is considered valid. 2086 */ 2087 #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) 2088 #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) 2089 #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) 2090 /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current 2091 * descriptor is exhausted. Reloading allows ping-pong and linked transfers. 2092 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 2093 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. 2094 */ 2095 #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) 2096 #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) 2097 #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) 2098 /*! SWTRIG - Software Trigger. 2099 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by 2100 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 2101 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not 2102 * be used with level triggering when TRIGBURST = 0. 2103 */ 2104 #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) 2105 #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) 2106 #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) 2107 /*! CLRTRIG - Clear Trigger. 2108 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 2109 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted 2110 */ 2111 #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) 2112 #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) 2113 #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) 2114 /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between 2115 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By 2116 * convention, interrupt A may be used when only one interrupt flag is needed. 2117 * 0b0..No effect. 2118 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 2119 */ 2120 #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) 2121 #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) 2122 #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) 2123 /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between 2124 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By 2125 * convention, interrupt A may be used when only one interrupt flag is needed. 2126 * 0b0..No effect. 2127 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 2128 */ 2129 #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) 2130 #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) 2131 #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) 2132 /*! WIDTH - Transfer width used for this DMA channel. 2133 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 2134 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 2135 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 2136 * 0b11..Reserved. Reserved setting, do not use. 2137 */ 2138 #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) 2139 #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) 2140 #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) 2141 /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. 2142 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 2143 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is 2144 * the usual case when the source is memory. 2145 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 2146 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 2147 */ 2148 #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) 2149 #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) 2150 #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) 2151 /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. 2152 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when 2153 * the destination is a peripheral device. 2154 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. 2155 * This is the usual case when the destination is memory. 2156 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 2157 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 2158 */ 2159 #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) 2160 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) 2161 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) 2162 /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes 2163 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller 2164 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read 2165 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 2166 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 2167 * 1,024 transfers will be performed. 2168 */ 2169 #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) 2170 /*! @} */ 2171 2172 /* The count of DMA_CHANNEL_XFERCFG */ 2173 #define DMA_CHANNEL_XFERCFG_COUNT (20U) 2174 2175 2176 /*! 2177 * @} 2178 */ /* end of group DMA_Register_Masks */ 2179 2180 2181 /* DMA - Peripheral instance base addresses */ 2182 /** Peripheral DMA0 base address */ 2183 #define DMA0_BASE (0x40082000u) 2184 /** Peripheral DMA0 base pointer */ 2185 #define DMA0 ((DMA_Type *)DMA0_BASE) 2186 /** Array initializer of DMA peripheral base addresses */ 2187 #define DMA_BASE_ADDRS { DMA0_BASE } 2188 /** Array initializer of DMA peripheral base pointers */ 2189 #define DMA_BASE_PTRS { DMA0 } 2190 /** Interrupt vectors for the DMA peripheral type */ 2191 #define DMA_IRQS { DMA0_IRQn } 2192 2193 /*! 2194 * @} 2195 */ /* end of group DMA_Peripheral_Access_Layer */ 2196 2197 2198 /* ---------------------------------------------------------------------------- 2199 -- DMIC Peripheral Access Layer 2200 ---------------------------------------------------------------------------- */ 2201 2202 /*! 2203 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer 2204 * @{ 2205 */ 2206 2207 /** DMIC - Register Layout Typedef */ 2208 typedef struct { 2209 struct { /* offset: 0x0, array step: 0x100 */ 2210 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ 2211 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ 2212 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ 2213 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ 2214 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ 2215 uint8_t RESERVED_0[108]; 2216 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ 2217 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ 2218 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ 2219 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ 2220 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ 2221 uint8_t RESERVED_1[108]; 2222 } CHANNEL[2]; 2223 uint8_t RESERVED_0[3328]; 2224 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ 2225 uint8_t RESERVED_1[8]; 2226 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ 2227 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ 2228 uint8_t RESERVED_2[108]; 2229 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ 2230 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ 2231 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ 2232 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ 2233 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ 2234 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ 2235 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ 2236 uint8_t RESERVED_3[96]; 2237 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ 2238 } DMIC_Type; 2239 2240 /* ---------------------------------------------------------------------------- 2241 -- DMIC Register Masks 2242 ---------------------------------------------------------------------------- */ 2243 2244 /*! 2245 * @addtogroup DMIC_Register_Masks DMIC Register Masks 2246 * @{ 2247 */ 2248 2249 /*! @name CHANNEL_OSR - Oversample Rate register 0 */ 2250 /*! @{ */ 2251 #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) 2252 #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) 2253 /*! OSR - Selects the oversample rate for the related input channel. 2254 */ 2255 #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) 2256 /*! @} */ 2257 2258 /* The count of DMIC_CHANNEL_OSR */ 2259 #define DMIC_CHANNEL_OSR_COUNT (2U) 2260 2261 /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ 2262 /*! @{ */ 2263 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) 2264 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) 2265 /*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by 2266 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = 2267 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others = 2268 * reserved. 2269 */ 2270 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) 2271 /*! @} */ 2272 2273 /* The count of DMIC_CHANNEL_DIVHFCLK */ 2274 #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) 2275 2276 /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ 2277 /*! @{ */ 2278 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) 2279 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) 2280 /*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2281 * 2 = Compensation = 15 3 = Compensation = 13 2282 */ 2283 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) 2284 /*! @} */ 2285 2286 /* The count of DMIC_CHANNEL_PREAC2FSCOEF */ 2287 #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) 2288 2289 /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ 2290 /*! @{ */ 2291 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) 2292 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) 2293 /*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2294 * 2 = Compensation = 15 3 = Compensation = 13 2295 */ 2296 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) 2297 /*! @} */ 2298 2299 /* The count of DMIC_CHANNEL_PREAC4FSCOEF */ 2300 #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) 2301 2302 /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ 2303 /*! @{ */ 2304 #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) 2305 #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) 2306 /*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift. 2307 */ 2308 #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) 2309 /*! @} */ 2310 2311 /* The count of DMIC_CHANNEL_GAINSHIFT */ 2312 #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) 2313 2314 /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ 2315 /*! @{ */ 2316 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) 2317 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) 2318 /*! ENABLE - FIFO enable. 2319 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being 2320 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a 2321 * period when the data was not needed. 2322 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register. 2323 */ 2324 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) 2325 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) 2326 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) 2327 /*! RESETN - FIFO reset. 2328 * 0b0..Reset the FIFO. 2329 * 0b1..Normal operation 2330 */ 2331 #define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) 2332 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) 2333 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) 2334 /*! INTEN - Interrupt enable. 2335 * 0b0..FIFO level interrupts are not enabled. 2336 * 0b1..FIFO level interrupts are enabled. 2337 */ 2338 #define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) 2339 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) 2340 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) 2341 /*! DMAEN - DMA enable 2342 * 0b0..DMA requests are not enabled. 2343 * 0b1..DMA requests based on FIFO level are enabled. 2344 */ 2345 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) 2346 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) 2347 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) 2348 /*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If 2349 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then 2350 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = 2351 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has 2352 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full). 2353 */ 2354 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) 2355 /*! @} */ 2356 2357 /* The count of DMIC_CHANNEL_FIFO_CTRL */ 2358 #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) 2359 2360 /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ 2361 /*! @{ */ 2362 #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) 2363 #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) 2364 /*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL 2365 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC 2366 * subsystem must be running in order for an interrupt to occur. 2367 */ 2368 #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) 2369 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) 2370 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) 2371 /*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one 2372 * to this bit clears the flag. This flag does not cause an interrupt. 2373 */ 2374 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) 2375 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) 2376 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) 2377 /*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag. 2378 */ 2379 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) 2380 /*! @} */ 2381 2382 /* The count of DMIC_CHANNEL_FIFO_STATUS */ 2383 #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) 2384 2385 /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ 2386 /*! @{ */ 2387 #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) 2388 #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) 2389 /*! DATA - Data from the top of the input filter FIFO. 2390 */ 2391 #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) 2392 /*! @} */ 2393 2394 /* The count of DMIC_CHANNEL_FIFO_DATA */ 2395 #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) 2396 2397 /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ 2398 /*! @{ */ 2399 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) 2400 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) 2401 /*! PHY_FALL - Capture PDM_DATA 2402 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK. 2403 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK. 2404 */ 2405 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) 2406 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) 2407 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) 2408 /*! PHY_HALF - Half rate sampling 2409 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. 2410 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing. 2411 */ 2412 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) 2413 /*! @} */ 2414 2415 /* The count of DMIC_CHANNEL_PHY_CTRL */ 2416 #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) 2417 2418 /*! @name CHANNEL_DC_CTRL - DC Control register 0 */ 2419 /*! @{ */ 2420 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) 2421 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) 2422 /*! DCPOLE - DC block filter 2423 * 0b00..Flat response, no filter. 2424 * 0b01..155 Hz. 2425 * 0b10..78 Hz. 2426 * 0b11..39 Hz 2427 */ 2428 #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) 2429 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) 2430 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) 2431 /*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift. 2432 */ 2433 #define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) 2434 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) 2435 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) 2436 /*! SATURATEAT16BIT - Selects 16-bit saturation. 2437 * 0b0..Results roll over if out range and do not saturate. 2438 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow. 2439 */ 2440 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) 2441 /*! @} */ 2442 2443 /* The count of DMIC_CHANNEL_DC_CTRL */ 2444 #define DMIC_CHANNEL_DC_CTRL_COUNT (2U) 2445 2446 /*! @name CHANEN - Channel Enable register */ 2447 /*! @{ */ 2448 #define DMIC_CHANEN_EN_CH0_MASK (0x1U) 2449 #define DMIC_CHANEN_EN_CH0_SHIFT (0U) 2450 /*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled. 2451 */ 2452 #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) 2453 #define DMIC_CHANEN_EN_CH1_MASK (0x2U) 2454 #define DMIC_CHANEN_EN_CH1_SHIFT (1U) 2455 /*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled. 2456 */ 2457 #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) 2458 /*! @} */ 2459 2460 /*! @name IOCFG - I/O Configuration register */ 2461 /*! @{ */ 2462 #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) 2463 #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) 2464 /*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides 2465 * for the possibility of an external codec taking over the PDM bus. 2466 */ 2467 #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) 2468 #define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) 2469 #define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) 2470 /*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides 2471 * for the possibility of an external codec taking over the PDM bus. 2472 */ 2473 #define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) 2474 #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) 2475 #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) 2476 /*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a 2477 * configuration that supports a single stereo digital microphone. 2478 */ 2479 #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) 2480 /*! @} */ 2481 2482 /*! @name USE2FS - Use 2FS register */ 2483 /*! @{ */ 2484 #define DMIC_USE2FS_USE2FS_MASK (0x1U) 2485 #define DMIC_USE2FS_USE2FS_SHIFT (0U) 2486 /*! USE2FS - Use 2FS register 2487 * 0b0..Use 1FS output for PCM data. 2488 * 0b1..Use 2FS output for PCM data. 2489 */ 2490 #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) 2491 /*! @} */ 2492 2493 /*! @name HWVADGAIN - HWVAD input gain register */ 2494 /*! @{ */ 2495 #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) 2496 #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) 2497 /*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04 2498 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10 2499 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved. 2500 */ 2501 #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) 2502 /*! @} */ 2503 2504 /*! @name HWVADHPFS - HWVAD filter control register */ 2505 /*! @{ */ 2506 #define DMIC_HWVADHPFS_HPFS_MASK (0x3U) 2507 #define DMIC_HWVADHPFS_HPFS_SHIFT (0U) 2508 /*! HPFS - High pass filter 2509 * 0b00..First filter by-pass. 2510 * 0b01..High pass filter with -3dB cut-off at 1750Hz. 2511 * 0b10..High pass filter with -3dB cut-off at 215Hz. 2512 * 0b11..Reserved. 2513 */ 2514 #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) 2515 /*! @} */ 2516 2517 /*! @name HWVADST10 - HWVAD control register */ 2518 /*! @{ */ 2519 #define DMIC_HWVADST10_ST10_MASK (0x1U) 2520 #define DMIC_HWVADST10_ST10_SHIFT (0U) 2521 /*! ST10 - Stage 0 2522 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0). 2523 * 0b1..Reset internal interrupt flag by writing a '1' pulse. 2524 */ 2525 #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) 2526 /*! @} */ 2527 2528 /*! @name HWVADRSTT - HWVAD filter reset register */ 2529 /*! @{ */ 2530 #define DMIC_HWVADRSTT_RSTT_MASK (0x1U) 2531 #define DMIC_HWVADRSTT_RSTT_SHIFT (0U) 2532 /*! RSTT - Writing a 1 resets all filter values 2533 */ 2534 #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) 2535 /*! @} */ 2536 2537 /*! @name HWVADTHGN - HWVAD noise estimator gain register */ 2538 /*! @{ */ 2539 #define DMIC_HWVADTHGN_THGN_MASK (0xFU) 2540 #define DMIC_HWVADTHGN_THGN_SHIFT (0U) 2541 /*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1. 2542 */ 2543 #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) 2544 /*! @} */ 2545 2546 /*! @name HWVADTHGS - HWVAD signal estimator gain register */ 2547 /*! @{ */ 2548 #define DMIC_HWVADTHGS_THGS_MASK (0xFU) 2549 #define DMIC_HWVADTHGS_THGS_SHIFT (0U) 2550 /*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1. 2551 */ 2552 #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) 2553 /*! @} */ 2554 2555 /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ 2556 /*! @{ */ 2557 #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) 2558 #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) 2559 /*! LOWZ - Noise envelope estimator value. 2560 */ 2561 #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) 2562 /*! @} */ 2563 2564 /*! @name ID - Module Identification register */ 2565 /*! @{ */ 2566 #define DMIC_ID_ID_MASK (0xFFFFFFFFU) 2567 #define DMIC_ID_ID_SHIFT (0U) 2568 /*! ID - Indicates module ID and the number of channels in this DMIC interface. 2569 */ 2570 #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) 2571 /*! @} */ 2572 2573 2574 /*! 2575 * @} 2576 */ /* end of group DMIC_Register_Masks */ 2577 2578 2579 /* DMIC - Peripheral instance base addresses */ 2580 /** Peripheral DMIC0 base address */ 2581 #define DMIC0_BASE (0x40090000u) 2582 /** Peripheral DMIC0 base pointer */ 2583 #define DMIC0 ((DMIC_Type *)DMIC0_BASE) 2584 /** Array initializer of DMIC peripheral base addresses */ 2585 #define DMIC_BASE_ADDRS { DMIC0_BASE } 2586 /** Array initializer of DMIC peripheral base pointers */ 2587 #define DMIC_BASE_PTRS { DMIC0 } 2588 /** Interrupt vectors for the DMIC peripheral type */ 2589 #define DMIC_IRQS { DMIC0_IRQn } 2590 #define DMIC_HWVAD_IRQS { HWVAD0_IRQn } 2591 2592 /*! 2593 * @} 2594 */ /* end of group DMIC_Peripheral_Access_Layer */ 2595 2596 2597 /* ---------------------------------------------------------------------------- 2598 -- FLEXCOMM Peripheral Access Layer 2599 ---------------------------------------------------------------------------- */ 2600 2601 /*! 2602 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer 2603 * @{ 2604 */ 2605 2606 /** FLEXCOMM - Register Layout Typedef */ 2607 typedef struct { 2608 uint8_t RESERVED_0[4088]; 2609 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ 2610 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ 2611 } FLEXCOMM_Type; 2612 2613 /* ---------------------------------------------------------------------------- 2614 -- FLEXCOMM Register Masks 2615 ---------------------------------------------------------------------------- */ 2616 2617 /*! 2618 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks 2619 * @{ 2620 */ 2621 2622 /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ 2623 /*! @{ */ 2624 #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) 2625 #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) 2626 /*! PERSEL - Peripheral Select. This field is writable by software. 2627 * 0b000..No peripheral selected. 2628 * 0b001..USART function selected. 2629 * 0b010..SPI function selected. 2630 * 0b011..I2C function selected. 2631 * 0b100..I2S transmit function selected. 2632 * 0b101..I2S receive function selected. 2633 * 0b110..Reserved 2634 * 0b111..Reserved 2635 */ 2636 #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) 2637 #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) 2638 #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) 2639 /*! LOCK - Lock the peripheral select. This field is writable by software. 2640 * 0b0..Peripheral select can be changed by software. 2641 * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. 2642 */ 2643 #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) 2644 #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) 2645 #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) 2646 /*! USARTPRESENT - USART present indicator. This field is Read-only. 2647 * 0b0..This Flexcomm does not include the USART function. 2648 * 0b1..This Flexcomm includes the USART function. 2649 */ 2650 #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) 2651 #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) 2652 #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) 2653 /*! SPIPRESENT - SPI present indicator. This field is Read-only. 2654 * 0b0..This Flexcomm does not include the SPI function. 2655 * 0b1..This Flexcomm includes the SPI function. 2656 */ 2657 #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) 2658 #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) 2659 #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) 2660 /*! I2CPRESENT - I2C present indicator. This field is Read-only. 2661 * 0b0..This Flexcomm does not include the I2C function. 2662 * 0b1..This Flexcomm includes the I2C function. 2663 */ 2664 #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) 2665 #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) 2666 #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) 2667 /*! I2SPRESENT - I 2S present indicator. This field is Read-only. 2668 * 0b0..This Flexcomm does not include the I2S function. 2669 * 0b1..This Flexcomm includes the I2S function. 2670 */ 2671 #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) 2672 #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) 2673 #define FLEXCOMM_PSELID_ID_SHIFT (12U) 2674 /*! ID - Flexcomm ID. 2675 */ 2676 #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) 2677 /*! @} */ 2678 2679 /*! @name PID - Peripheral identification register. */ 2680 /*! @{ */ 2681 #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) 2682 #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) 2683 /*! Minor_Rev - Minor revision of module implementation. 2684 */ 2685 #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) 2686 #define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) 2687 #define FLEXCOMM_PID_Major_Rev_SHIFT (12U) 2688 /*! Major_Rev - Major revision of module implementation. 2689 */ 2690 #define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) 2691 #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) 2692 #define FLEXCOMM_PID_ID_SHIFT (16U) 2693 /*! ID - Module identifier for the selected function. 2694 */ 2695 #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) 2696 /*! @} */ 2697 2698 2699 /*! 2700 * @} 2701 */ /* end of group FLEXCOMM_Register_Masks */ 2702 2703 2704 /* FLEXCOMM - Peripheral instance base addresses */ 2705 /** Peripheral FLEXCOMM0 base address */ 2706 #define FLEXCOMM0_BASE (0x40086000u) 2707 /** Peripheral FLEXCOMM0 base pointer */ 2708 #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) 2709 /** Peripheral FLEXCOMM1 base address */ 2710 #define FLEXCOMM1_BASE (0x40087000u) 2711 /** Peripheral FLEXCOMM1 base pointer */ 2712 #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) 2713 /** Peripheral FLEXCOMM2 base address */ 2714 #define FLEXCOMM2_BASE (0x40088000u) 2715 /** Peripheral FLEXCOMM2 base pointer */ 2716 #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) 2717 /** Peripheral FLEXCOMM3 base address */ 2718 #define FLEXCOMM3_BASE (0x40089000u) 2719 /** Peripheral FLEXCOMM3 base pointer */ 2720 #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) 2721 /** Peripheral FLEXCOMM4 base address */ 2722 #define FLEXCOMM4_BASE (0x4008A000u) 2723 /** Peripheral FLEXCOMM4 base pointer */ 2724 #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) 2725 /** Peripheral FLEXCOMM5 base address */ 2726 #define FLEXCOMM5_BASE (0x40096000u) 2727 /** Peripheral FLEXCOMM5 base pointer */ 2728 #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) 2729 /** Peripheral FLEXCOMM6 base address */ 2730 #define FLEXCOMM6_BASE (0x40097000u) 2731 /** Peripheral FLEXCOMM6 base pointer */ 2732 #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) 2733 /** Peripheral FLEXCOMM7 base address */ 2734 #define FLEXCOMM7_BASE (0x40098000u) 2735 /** Peripheral FLEXCOMM7 base pointer */ 2736 #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) 2737 /** Array initializer of FLEXCOMM peripheral base addresses */ 2738 #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } 2739 /** Array initializer of FLEXCOMM peripheral base pointers */ 2740 #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } 2741 /** Interrupt vectors for the FLEXCOMM peripheral type */ 2742 #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 2743 2744 /*! 2745 * @} 2746 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ 2747 2748 2749 /* ---------------------------------------------------------------------------- 2750 -- GINT Peripheral Access Layer 2751 ---------------------------------------------------------------------------- */ 2752 2753 /*! 2754 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer 2755 * @{ 2756 */ 2757 2758 /** GINT - Register Layout Typedef */ 2759 typedef struct { 2760 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ 2761 uint8_t RESERVED_0[28]; 2762 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ 2763 uint8_t RESERVED_1[24]; 2764 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ 2765 } GINT_Type; 2766 2767 /* ---------------------------------------------------------------------------- 2768 -- GINT Register Masks 2769 ---------------------------------------------------------------------------- */ 2770 2771 /*! 2772 * @addtogroup GINT_Register_Masks GINT Register Masks 2773 * @{ 2774 */ 2775 2776 /*! @name CTRL - GPIO grouped interrupt control register */ 2777 /*! @{ */ 2778 #define GINT_CTRL_INT_MASK (0x1U) 2779 #define GINT_CTRL_INT_SHIFT (0U) 2780 /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. 2781 * 0b0..No request. No interrupt request is pending. 2782 * 0b1..Request active. Interrupt request is active. 2783 */ 2784 #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) 2785 #define GINT_CTRL_COMB_MASK (0x2U) 2786 #define GINT_CTRL_COMB_SHIFT (1U) 2787 /*! COMB - Combine enabled inputs for group interrupt 2788 * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 2789 * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 2790 */ 2791 #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) 2792 #define GINT_CTRL_TRIG_MASK (0x4U) 2793 #define GINT_CTRL_TRIG_SHIFT (2U) 2794 /*! TRIG - Group interrupt trigger 2795 * 0b0..Edge-triggered. 2796 * 0b1..Level-triggered. 2797 */ 2798 #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) 2799 /*! @} */ 2800 2801 /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ 2802 /*! @{ */ 2803 #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) 2804 #define GINT_PORT_POL_POL_SHIFT (0U) 2805 /*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n 2806 * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to 2807 * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin 2808 * contributes to the group interrupt. 2809 */ 2810 #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) 2811 /*! @} */ 2812 2813 /* The count of GINT_PORT_POL */ 2814 #define GINT_PORT_POL_COUNT (2U) 2815 2816 /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ 2817 /*! @{ */ 2818 #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) 2819 #define GINT_PORT_ENA_ENA_SHIFT (0U) 2820 /*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the 2821 * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is 2822 * enabled and contributes to the grouped interrupt. 2823 */ 2824 #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) 2825 /*! @} */ 2826 2827 /* The count of GINT_PORT_ENA */ 2828 #define GINT_PORT_ENA_COUNT (2U) 2829 2830 2831 /*! 2832 * @} 2833 */ /* end of group GINT_Register_Masks */ 2834 2835 2836 /* GINT - Peripheral instance base addresses */ 2837 /** Peripheral GINT0 base address */ 2838 #define GINT0_BASE (0x40002000u) 2839 /** Peripheral GINT0 base pointer */ 2840 #define GINT0 ((GINT_Type *)GINT0_BASE) 2841 /** Peripheral GINT1 base address */ 2842 #define GINT1_BASE (0x40003000u) 2843 /** Peripheral GINT1 base pointer */ 2844 #define GINT1 ((GINT_Type *)GINT1_BASE) 2845 /** Array initializer of GINT peripheral base addresses */ 2846 #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } 2847 /** Array initializer of GINT peripheral base pointers */ 2848 #define GINT_BASE_PTRS { GINT0, GINT1 } 2849 /** Interrupt vectors for the GINT peripheral type */ 2850 #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } 2851 2852 /*! 2853 * @} 2854 */ /* end of group GINT_Peripheral_Access_Layer */ 2855 2856 2857 /* ---------------------------------------------------------------------------- 2858 -- GPIO Peripheral Access Layer 2859 ---------------------------------------------------------------------------- */ 2860 2861 /*! 2862 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2863 * @{ 2864 */ 2865 2866 /** GPIO - Register Layout Typedef */ 2867 typedef struct { 2868 __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ 2869 uint8_t RESERVED_0[4032]; 2870 __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ 2871 uint8_t RESERVED_1[3840]; 2872 __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ 2873 uint8_t RESERVED_2[120]; 2874 __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ 2875 uint8_t RESERVED_3[120]; 2876 __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ 2877 uint8_t RESERVED_4[120]; 2878 __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ 2879 uint8_t RESERVED_5[120]; 2880 __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ 2881 uint8_t RESERVED_6[120]; 2882 __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ 2883 uint8_t RESERVED_7[120]; 2884 __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ 2885 uint8_t RESERVED_8[120]; 2886 __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ 2887 uint8_t RESERVED_9[120]; 2888 __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ 2889 uint8_t RESERVED_10[120]; 2890 __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ 2891 } GPIO_Type; 2892 2893 /* ---------------------------------------------------------------------------- 2894 -- GPIO Register Masks 2895 ---------------------------------------------------------------------------- */ 2896 2897 /*! 2898 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2899 * @{ 2900 */ 2901 2902 /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ 2903 /*! @{ */ 2904 #define GPIO_B_PBYTE_MASK (0x1U) 2905 #define GPIO_B_PBYTE_SHIFT (0U) 2906 /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, 2907 * except that pins configured as analog I/O always read as 0. One register for each port pin. 2908 * Supported pins depends on the specific device and package. Write: loads the pin's output bit. 2909 * One register for each port pin. Supported pins depends on the specific device and package. 2910 */ 2911 #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) 2912 /*! @} */ 2913 2914 /* The count of GPIO_B */ 2915 #define GPIO_B_COUNT (2U) 2916 2917 /* The count of GPIO_B */ 2918 #define GPIO_B_COUNT2 (32U) 2919 2920 /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ 2921 /*! @{ */ 2922 #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) 2923 #define GPIO_W_PWORD_SHIFT (0U) 2924 /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is 2925 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be 2926 * read. Writing any value other than 0 will set the output bit. One register for each port pin. 2927 * Supported pins depends on the specific device and package. 2928 */ 2929 #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) 2930 /*! @} */ 2931 2932 /* The count of GPIO_W */ 2933 #define GPIO_W_COUNT (2U) 2934 2935 /* The count of GPIO_W */ 2936 #define GPIO_W_COUNT2 (32U) 2937 2938 /*! @name DIR - Direction registers */ 2939 /*! @{ */ 2940 #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) 2941 #define GPIO_DIR_DIRP_SHIFT (0U) 2942 /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2943 * pins depends on the specific device and package. 0 = input. 1 = output. 2944 */ 2945 #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) 2946 /*! @} */ 2947 2948 /* The count of GPIO_DIR */ 2949 #define GPIO_DIR_COUNT (2U) 2950 2951 /*! @name MASK - Mask register */ 2952 /*! @{ */ 2953 #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) 2954 #define GPIO_MASK_MASKP_SHIFT (0U) 2955 /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = 2956 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = 2957 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit 2958 * not affected. 2959 */ 2960 #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) 2961 /*! @} */ 2962 2963 /* The count of GPIO_MASK */ 2964 #define GPIO_MASK_COUNT (2U) 2965 2966 /*! @name PIN - Port pin register */ 2967 /*! @{ */ 2968 #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) 2969 #define GPIO_PIN_PORT_SHIFT (0U) 2970 /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2971 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 2972 * 1 = Read: pin is high; write: set output bit. 2973 */ 2974 #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) 2975 /*! @} */ 2976 2977 /* The count of GPIO_PIN */ 2978 #define GPIO_PIN_COUNT (2U) 2979 2980 /*! @name MPIN - Masked port register */ 2981 /*! @{ */ 2982 #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) 2983 #define GPIO_MPIN_MPORTP_SHIFT (0U) 2984 /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2985 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK 2986 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 2987 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit 2988 * if the corresponding bit in the MASK register is 0. 2989 */ 2990 #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) 2991 /*! @} */ 2992 2993 /* The count of GPIO_MPIN */ 2994 #define GPIO_MPIN_COUNT (2U) 2995 2996 /*! @name SET - Write: Set register for port Read: output bits for port */ 2997 /*! @{ */ 2998 #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) 2999 #define GPIO_SET_SETP_SHIFT (0U) 3000 /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3001 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output 3002 * bit; write: set output bit. 3003 */ 3004 #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) 3005 /*! @} */ 3006 3007 /* The count of GPIO_SET */ 3008 #define GPIO_SET_COUNT (2U) 3009 3010 /*! @name CLR - Clear port */ 3011 /*! @{ */ 3012 #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) 3013 #define GPIO_CLR_CLRP_SHIFT (0U) 3014 /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 3015 * specific device and package. 0 = No operation. 1 = Clear output bit. 3016 */ 3017 #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) 3018 /*! @} */ 3019 3020 /* The count of GPIO_CLR */ 3021 #define GPIO_CLR_COUNT (2U) 3022 3023 /*! @name NOT - Toggle port */ 3024 /*! @{ */ 3025 #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) 3026 #define GPIO_NOT_NOTP_SHIFT (0U) 3027 /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 3028 * specific device and package. 0 = no operation. 1 = Toggle output bit. 3029 */ 3030 #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) 3031 /*! @} */ 3032 3033 /* The count of GPIO_NOT */ 3034 #define GPIO_NOT_COUNT (2U) 3035 3036 /*! @name DIRSET - Set pin direction bits for port */ 3037 /*! @{ */ 3038 #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) 3039 #define GPIO_DIRSET_DIRSETP_SHIFT (0U) 3040 /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3041 * the specific device and package. 0 = No operation. 1 = Set direction bit. 3042 */ 3043 #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) 3044 /*! @} */ 3045 3046 /* The count of GPIO_DIRSET */ 3047 #define GPIO_DIRSET_COUNT (2U) 3048 3049 /*! @name DIRCLR - Clear pin direction bits for port */ 3050 /*! @{ */ 3051 #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) 3052 #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) 3053 /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3054 * the specific device and package. 0 = No operation. 1 = Clear direction bit. 3055 */ 3056 #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) 3057 /*! @} */ 3058 3059 /* The count of GPIO_DIRCLR */ 3060 #define GPIO_DIRCLR_COUNT (2U) 3061 3062 /*! @name DIRNOT - Toggle pin direction bits for port */ 3063 /*! @{ */ 3064 #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) 3065 #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) 3066 /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends 3067 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 3068 */ 3069 #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) 3070 /*! @} */ 3071 3072 /* The count of GPIO_DIRNOT */ 3073 #define GPIO_DIRNOT_COUNT (2U) 3074 3075 3076 /*! 3077 * @} 3078 */ /* end of group GPIO_Register_Masks */ 3079 3080 3081 /* GPIO - Peripheral instance base addresses */ 3082 /** Peripheral GPIO base address */ 3083 #define GPIO_BASE (0x4008C000u) 3084 /** Peripheral GPIO base pointer */ 3085 #define GPIO ((GPIO_Type *)GPIO_BASE) 3086 /** Array initializer of GPIO peripheral base addresses */ 3087 #define GPIO_BASE_ADDRS { GPIO_BASE } 3088 /** Array initializer of GPIO peripheral base pointers */ 3089 #define GPIO_BASE_PTRS { GPIO } 3090 3091 /*! 3092 * @} 3093 */ /* end of group GPIO_Peripheral_Access_Layer */ 3094 3095 3096 /* ---------------------------------------------------------------------------- 3097 -- I2C Peripheral Access Layer 3098 ---------------------------------------------------------------------------- */ 3099 3100 /*! 3101 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 3102 * @{ 3103 */ 3104 3105 /** I2C - Register Layout Typedef */ 3106 typedef struct { 3107 uint8_t RESERVED_0[2048]; 3108 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ 3109 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ 3110 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ 3111 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ 3112 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ 3113 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ 3114 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ 3115 uint8_t RESERVED_1[4]; 3116 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ 3117 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ 3118 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ 3119 uint8_t RESERVED_2[20]; 3120 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ 3121 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ 3122 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ 3123 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ 3124 uint8_t RESERVED_3[36]; 3125 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ 3126 } I2C_Type; 3127 3128 /* ---------------------------------------------------------------------------- 3129 -- I2C Register Masks 3130 ---------------------------------------------------------------------------- */ 3131 3132 /*! 3133 * @addtogroup I2C_Register_Masks I2C Register Masks 3134 * @{ 3135 */ 3136 3137 /*! @name CFG - Configuration for shared functions. */ 3138 /*! @{ */ 3139 #define I2C_CFG_MSTEN_MASK (0x1U) 3140 #define I2C_CFG_MSTEN_SHIFT (0U) 3141 /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not 3142 * changed, but the Master function is internally reset. 3143 * 0b0..Disabled. The I2C Master function is disabled. 3144 * 0b1..Enabled. The I2C Master function is enabled. 3145 */ 3146 #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) 3147 #define I2C_CFG_SLVEN_MASK (0x2U) 3148 #define I2C_CFG_SLVEN_SHIFT (1U) 3149 /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not 3150 * changed, but the Slave function is internally reset. 3151 * 0b0..Disabled. The I2C slave function is disabled. 3152 * 0b1..Enabled. The I2C slave function is enabled. 3153 */ 3154 #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) 3155 #define I2C_CFG_MONEN_MASK (0x4U) 3156 #define I2C_CFG_MONEN_SHIFT (2U) 3157 /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not 3158 * changed, but the Monitor function is internally reset. 3159 * 0b0..Disabled. The I2C Monitor function is disabled. 3160 * 0b1..Enabled. The I2C Monitor function is enabled. 3161 */ 3162 #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) 3163 #define I2C_CFG_TIMEOUTEN_MASK (0x8U) 3164 #define I2C_CFG_TIMEOUTEN_SHIFT (3U) 3165 /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3166 * 0b0..Disabled. Time-out function is disabled. 3167 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause 3168 * interrupts if they are enabled. Typically, only one time-out will be used in a system. 3169 */ 3170 #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) 3171 #define I2C_CFG_MONCLKSTR_MASK (0x10U) 3172 #define I2C_CFG_MONCLKSTR_SHIFT (4U) 3173 /*! MONCLKSTR - Monitor function Clock Stretching. 3174 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able 3175 * to read data provided by the Monitor function before it is overwritten. This mode may be used when 3176 * non-invasive monitoring is critical. 3177 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can 3178 * read all incoming data supplied by the Monitor function. 3179 */ 3180 #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) 3181 #define I2C_CFG_HSCAPABLE_MASK (0x20U) 3182 #define I2C_CFG_HSCAPABLE_SHIFT (5U) 3183 /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive 3184 * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies 3185 * to all functions: Master, Slave, and Monitor. 3186 * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the 3187 * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, 3188 * such as changing the drive strength or filtering, must be made by software via the IOCON register associated 3189 * with each I2C pin, 3190 * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support 3191 * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more 3192 * information. 3193 */ 3194 #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) 3195 /*! @} */ 3196 3197 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ 3198 /*! @{ */ 3199 #define I2C_STAT_MSTPENDING_MASK (0x1U) 3200 #define I2C_STAT_MSTPENDING_SHIFT (0U) 3201 /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on 3202 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what 3203 * type of software service if any the master expects. This flag will cause an interrupt when set 3204 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling 3205 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle 3206 * state, and no communication is needed, mask this interrupt. 3207 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 3208 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the 3209 * idle state, it is waiting to receive or transmit data or the NACK bit. 3210 */ 3211 #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) 3212 #define I2C_STAT_MSTSTATE_MASK (0xEU) 3213 #define I2C_STAT_MSTSTATE_SHIFT (1U) 3214 /*! MSTSTATE - Master State code. The master state code reflects the master state when the 3215 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field 3216 * indicates a specific required service for the Master function. All other values are reserved. See 3217 * Table 400 for details of state values and appropriate responses. 3218 * 0b000..Idle. The Master function is available to be used for a new transaction. 3219 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 3220 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 3221 * 0b011..NACK Address. Slave NACKed address. 3222 * 0b100..NACK Data. Slave NACKed transmitted data. 3223 */ 3224 #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) 3225 #define I2C_STAT_MSTARBLOSS_MASK (0x10U) 3226 #define I2C_STAT_MSTARBLOSS_SHIFT (4U) 3227 /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to 3228 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 3229 * 0b0..No Arbitration Loss has occurred. 3230 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master 3231 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, 3232 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 3233 */ 3234 #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) 3235 #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) 3236 #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) 3237 /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to 3238 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 3239 * 0b0..No Start/Stop Error has occurred. 3240 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is 3241 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an 3242 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure 3243 * that the bus has not stalled. 3244 */ 3245 #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) 3246 #define I2C_STAT_SLVPENDING_MASK (0x100U) 3247 #define I2C_STAT_SLVPENDING_SHIFT (8U) 3248 /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue 3249 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if 3250 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the 3251 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is 3252 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time 3253 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 3254 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are 3255 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must 3256 * also be detected automatically, since the address must be acknowledged before the clock can be 3257 * stretched. 3258 * 0b0..In progress. The Slave function does not currently need service. 3259 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 3260 */ 3261 #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) 3262 #define I2C_STAT_SLVSTATE_MASK (0x600U) 3263 #define I2C_STAT_SLVSTATE_SHIFT (9U) 3264 /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for 3265 * the Slave function. All other values are reserved. See Table 401 for state values and actions. 3266 * note that the occurrence of some states and how they are handled are affected by DMA mode and 3267 * Automatic Operation modes. 3268 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 3269 * 0b01..Slave receive. Received data is available (Slave Receiver mode). 3270 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). 3271 */ 3272 #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) 3273 #define I2C_STAT_SLVNOTSTR_MASK (0x800U) 3274 #define I2C_STAT_SLVNOTSTR_SHIFT (11U) 3275 /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. 3276 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave 3277 * operation. This read-only flag reflects the slave function status in real time. 3278 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 3279 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or 3280 * Power-down mode could be entered at this time. 3281 */ 3282 #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) 3283 #define I2C_STAT_SLVIDX_MASK (0x3000U) 3284 #define I2C_STAT_SLVIDX_SHIFT (12U) 3285 /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been 3286 * selected by receiving an address that matches one of the slave addresses defined by any enabled 3287 * slave address registers, and provides an identification of the address that was matched. It is 3288 * possible that more than one address could be matched, but only one match can be reported here. 3289 * 0b00..Address 0. Slave address 0 was matched. 3290 * 0b01..Address 1. Slave address 1 was matched. 3291 * 0b10..Address 2. Slave address 2 was matched. 3292 * 0b11..Address 3. Slave address 3 was matched. 3293 */ 3294 #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) 3295 #define I2C_STAT_SLVSEL_MASK (0x4000U) 3296 #define I2C_STAT_SLVSEL_SHIFT (14U) 3297 /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave 3298 * function to acknowledge the address, or when the address has been automatically acknowledged. 3299 * It is cleared when another address cycle presents an address that does not match an enabled 3300 * address on the Slave function, when slave software decides to NACK a matched address, when 3301 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of 3302 * Automatic Operation. SLVSEL is not cleared if software NACKs data. 3303 * 0b0..Not selected. The Slave function is not currently selected. 3304 * 0b1..Selected. The Slave function is currently selected. 3305 */ 3306 #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) 3307 #define I2C_STAT_SLVDESEL_MASK (0x8000U) 3308 #define I2C_STAT_SLVDESEL_SHIFT (15U) 3309 /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via 3310 * INTENSET. This flag can be cleared by writing a 1 to this bit. 3311 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently 3312 * selected. That information can be found in the SLVSEL flag. 3313 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag 3314 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 3315 */ 3316 #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) 3317 #define I2C_STAT_MONRDY_MASK (0x10000U) 3318 #define I2C_STAT_MONRDY_SHIFT (16U) 3319 /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. 3320 * 0b0..No data. The Monitor function does not currently have data available. 3321 * 0b1..Data waiting. The Monitor function has data waiting to be read. 3322 */ 3323 #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) 3324 #define I2C_STAT_MONOV_MASK (0x20000U) 3325 #define I2C_STAT_MONOV_SHIFT (17U) 3326 /*! MONOV - Monitor Overflow flag. 3327 * 0b0..No overrun. Monitor data has not overrun. 3328 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not 3329 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 3330 */ 3331 #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) 3332 #define I2C_STAT_MONACTIVE_MASK (0x40000U) 3333 #define I2C_STAT_MONACTIVE_SHIFT (18U) 3334 /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to 3335 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred 3336 * more recently than a bus Stop. 3337 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. 3338 * 0b1..Active. The Monitor function considers the I2C bus to be active. 3339 */ 3340 #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) 3341 #define I2C_STAT_MONIDLE_MASK (0x80000U) 3342 #define I2C_STAT_MONIDLE_SHIFT (19U) 3343 /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change 3344 * from active to inactive. This can be used by software to decide when to process data 3345 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the 3346 * INTENSET register. The flag can be cleared by writing a 1 to this bit. 3347 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. 3348 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 3349 */ 3350 #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) 3351 #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) 3352 #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) 3353 /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been 3354 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock 3355 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus 3356 * is idle. 3357 * 0b0..No time-out. I2C bus events have not caused a time-out. 3358 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 3359 */ 3360 #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) 3361 #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) 3362 #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) 3363 /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the 3364 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 3365 * 0b0..No time-out. SCL low time has not caused a time-out. 3366 * 0b1..Time-out. SCL low time has caused a time-out. 3367 */ 3368 #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) 3369 /*! @} */ 3370 3371 /*! @name INTENSET - Interrupt Enable Set and read register. */ 3372 /*! @{ */ 3373 #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) 3374 #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) 3375 /*! MSTPENDINGEN - Master Pending interrupt Enable. 3376 * 0b0..Disabled. The MstPending interrupt is disabled. 3377 * 0b1..Enabled. The MstPending interrupt is enabled. 3378 */ 3379 #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) 3380 #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) 3381 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) 3382 /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. 3383 * 0b0..Disabled. The MstArbLoss interrupt is disabled. 3384 * 0b1..Enabled. The MstArbLoss interrupt is enabled. 3385 */ 3386 #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) 3387 #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) 3388 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) 3389 /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. 3390 * 0b0..Disabled. The MstStStpErr interrupt is disabled. 3391 * 0b1..Enabled. The MstStStpErr interrupt is enabled. 3392 */ 3393 #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) 3394 #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) 3395 #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) 3396 /*! SLVPENDINGEN - Slave Pending interrupt Enable. 3397 * 0b0..Disabled. The SlvPending interrupt is disabled. 3398 * 0b1..Enabled. The SlvPending interrupt is enabled. 3399 */ 3400 #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) 3401 #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) 3402 #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) 3403 /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. 3404 * 0b0..Disabled. The SlvNotStr interrupt is disabled. 3405 * 0b1..Enabled. The SlvNotStr interrupt is enabled. 3406 */ 3407 #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) 3408 #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) 3409 #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) 3410 /*! SLVDESELEN - Slave Deselect interrupt Enable. 3411 * 0b0..Disabled. The SlvDeSel interrupt is disabled. 3412 * 0b1..Enabled. The SlvDeSel interrupt is enabled. 3413 */ 3414 #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) 3415 #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) 3416 #define I2C_INTENSET_MONRDYEN_SHIFT (16U) 3417 /*! MONRDYEN - Monitor data Ready interrupt Enable. 3418 * 0b0..Disabled. The MonRdy interrupt is disabled. 3419 * 0b1..Enabled. The MonRdy interrupt is enabled. 3420 */ 3421 #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) 3422 #define I2C_INTENSET_MONOVEN_MASK (0x20000U) 3423 #define I2C_INTENSET_MONOVEN_SHIFT (17U) 3424 /*! MONOVEN - Monitor Overrun interrupt Enable. 3425 * 0b0..Disabled. The MonOv interrupt is disabled. 3426 * 0b1..Enabled. The MonOv interrupt is enabled. 3427 */ 3428 #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) 3429 #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) 3430 #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) 3431 /*! MONIDLEEN - Monitor Idle interrupt Enable. 3432 * 0b0..Disabled. The MonIdle interrupt is disabled. 3433 * 0b1..Enabled. The MonIdle interrupt is enabled. 3434 */ 3435 #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) 3436 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) 3437 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) 3438 /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. 3439 * 0b0..Disabled. The Event time-out interrupt is disabled. 3440 * 0b1..Enabled. The Event time-out interrupt is enabled. 3441 */ 3442 #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) 3443 #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) 3444 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) 3445 /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. 3446 * 0b0..Disabled. The SCL time-out interrupt is disabled. 3447 * 0b1..Enabled. The SCL time-out interrupt is enabled. 3448 */ 3449 #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) 3450 /*! @} */ 3451 3452 /*! @name INTENCLR - Interrupt Enable Clear register. */ 3453 /*! @{ */ 3454 #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) 3455 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) 3456 /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding 3457 * bit in the INTENSET register if implemented. 3458 */ 3459 #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) 3460 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) 3461 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) 3462 /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. 3463 */ 3464 #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) 3465 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) 3466 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) 3467 /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. 3468 */ 3469 #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) 3470 #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) 3471 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) 3472 /*! SLVPENDINGCLR - Slave Pending interrupt clear. 3473 */ 3474 #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) 3475 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) 3476 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) 3477 /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. 3478 */ 3479 #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) 3480 #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) 3481 #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) 3482 /*! SLVDESELCLR - Slave Deselect interrupt clear. 3483 */ 3484 #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) 3485 #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) 3486 #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) 3487 /*! MONRDYCLR - Monitor data Ready interrupt clear. 3488 */ 3489 #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) 3490 #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) 3491 #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) 3492 /*! MONOVCLR - Monitor Overrun interrupt clear. 3493 */ 3494 #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) 3495 #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) 3496 #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) 3497 /*! MONIDLECLR - Monitor Idle interrupt clear. 3498 */ 3499 #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) 3500 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) 3501 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) 3502 /*! EVENTTIMEOUTCLR - Event time-out interrupt clear. 3503 */ 3504 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) 3505 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) 3506 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) 3507 /*! SCLTIMEOUTCLR - SCL time-out interrupt clear. 3508 */ 3509 #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) 3510 /*! @} */ 3511 3512 /*! @name TIMEOUT - Time-out value register. */ 3513 /*! @{ */ 3514 #define I2C_TIMEOUT_TOMIN_MASK (0xFU) 3515 #define I2C_TIMEOUT_TOMIN_SHIFT (0U) 3516 /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum 3517 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 3518 */ 3519 #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) 3520 #define I2C_TIMEOUT_TO_MASK (0xFFF0U) 3521 #define I2C_TIMEOUT_TO_SHIFT (4U) 3522 /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C 3523 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, 3524 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A 3525 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 3526 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the 3527 * I2C function clock. 3528 */ 3529 #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) 3530 /*! @} */ 3531 3532 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ 3533 /*! @{ */ 3534 #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) 3535 #define I2C_CLKDIV_DIVVAL_SHIFT (0U) 3536 /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that 3537 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = 3538 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is 3539 * divided by 65,536 before use. 3540 */ 3541 #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) 3542 /*! @} */ 3543 3544 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ 3545 /*! @{ */ 3546 #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) 3547 #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) 3548 /*! MSTPENDING - Master Pending. 3549 */ 3550 #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) 3551 #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) 3552 #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) 3553 /*! MSTARBLOSS - Master Arbitration Loss flag. 3554 */ 3555 #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) 3556 #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) 3557 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) 3558 /*! MSTSTSTPERR - Master Start/Stop Error flag. 3559 */ 3560 #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) 3561 #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) 3562 #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) 3563 /*! SLVPENDING - Slave Pending. 3564 */ 3565 #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) 3566 #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) 3567 #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) 3568 /*! SLVNOTSTR - Slave Not Stretching status. 3569 */ 3570 #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) 3571 #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) 3572 #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) 3573 /*! SLVDESEL - Slave Deselected flag. 3574 */ 3575 #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) 3576 #define I2C_INTSTAT_MONRDY_MASK (0x10000U) 3577 #define I2C_INTSTAT_MONRDY_SHIFT (16U) 3578 /*! MONRDY - Monitor Ready. 3579 */ 3580 #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) 3581 #define I2C_INTSTAT_MONOV_MASK (0x20000U) 3582 #define I2C_INTSTAT_MONOV_SHIFT (17U) 3583 /*! MONOV - Monitor Overflow flag. 3584 */ 3585 #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) 3586 #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) 3587 #define I2C_INTSTAT_MONIDLE_SHIFT (19U) 3588 /*! MONIDLE - Monitor Idle flag. 3589 */ 3590 #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) 3591 #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) 3592 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) 3593 /*! EVENTTIMEOUT - Event time-out Interrupt flag. 3594 */ 3595 #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) 3596 #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) 3597 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) 3598 /*! SCLTIMEOUT - SCL time-out Interrupt flag. 3599 */ 3600 #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) 3601 /*! @} */ 3602 3603 /*! @name MSTCTL - Master control register. */ 3604 /*! @{ */ 3605 #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) 3606 #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) 3607 /*! MSTCONTINUE - Master Continue. This bit is write-only. 3608 * 0b0..No effect. 3609 * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing 3610 * transmit data, reading received data, or any other housekeeping related to the next bus operation. 3611 */ 3612 #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) 3613 #define I2C_MSTCTL_MSTSTART_MASK (0x2U) 3614 #define I2C_MSTCTL_MSTSTART_SHIFT (1U) 3615 /*! MSTSTART - Master Start control. This bit is write-only. 3616 * 0b0..No effect. 3617 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. 3618 */ 3619 #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) 3620 #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) 3621 #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) 3622 /*! MSTSTOP - Master Stop control. This bit is write-only. 3623 * 0b0..No effect. 3624 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave 3625 * if the master is receiving data from the slave (Master Receiver mode). 3626 */ 3627 #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) 3628 #define I2C_MSTCTL_MSTDMA_MASK (0x8U) 3629 #define I2C_MSTCTL_MSTDMA_SHIFT (3U) 3630 /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type 3631 * operations such as Start, address, Stop, and address match must always be done with software, 3632 * typically via an interrupt. Address acknowledgement must also be done by software except when 3633 * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by 3634 * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA 3635 * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is 3636 * read/write. 3637 * 0b0..Disable. No DMA requests are generated for master operation. 3638 * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating 3639 * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 3640 */ 3641 #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) 3642 /*! @} */ 3643 3644 /*! @name MSTTIME - Master timing configuration. */ 3645 /*! @{ */ 3646 #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) 3647 #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) 3648 /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this 3649 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This 3650 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters 3651 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 3652 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 3653 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 3654 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 3655 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 3656 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 3657 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 3658 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 3659 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 3660 */ 3661 #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) 3662 #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) 3663 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) 3664 /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this 3665 * master on SCL. Other masters in a multi-master system could shorten this time. This 3666 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters 3667 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 3668 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 3669 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 3670 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 3671 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 3672 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 3673 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 3674 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 3675 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 3676 */ 3677 #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) 3678 /*! @} */ 3679 3680 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ 3681 /*! @{ */ 3682 #define I2C_MSTDAT_DATA_MASK (0xFFU) 3683 #define I2C_MSTDAT_DATA_SHIFT (0U) 3684 /*! DATA - Master function data register. Read: read the most recently received data for the Master 3685 * function. Write: transmit data using the Master function. 3686 */ 3687 #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) 3688 /*! @} */ 3689 3690 /*! @name SLVCTL - Slave control register. */ 3691 /*! @{ */ 3692 #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) 3693 #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) 3694 /*! SLVCONTINUE - Slave Continue. 3695 * 0b0..No effect. 3696 * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag 3697 * in the STAT register. This must be done after writing transmit data, reading received data, or any other 3698 * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE 3699 * should not be set unless SLVPENDING = 1. 3700 */ 3701 #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) 3702 #define I2C_SLVCTL_SLVNACK_MASK (0x2U) 3703 #define I2C_SLVCTL_SLVNACK_SHIFT (1U) 3704 /*! SLVNACK - Slave NACK. 3705 * 0b0..No effect. 3706 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 3707 */ 3708 #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) 3709 #define I2C_SLVCTL_SLVDMA_MASK (0x8U) 3710 #define I2C_SLVCTL_SLVDMA_SHIFT (3U) 3711 /*! SLVDMA - Slave DMA enable. 3712 * 0b0..Disabled. No DMA requests are issued for Slave mode operation. 3713 * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. 3714 */ 3715 #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) 3716 #define I2C_SLVCTL_AUTOACK_MASK (0x100U) 3717 #define I2C_SLVCTL_AUTOACK_SHIFT (8U) 3718 /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches 3719 * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA 3720 * to allow processing of the data without intervention. If this bit is clear and a header 3721 * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or 3722 * interrupt. 3723 * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching 3724 * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). 3725 * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, 3726 * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does 3727 * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK 3728 * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. 3729 */ 3730 #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) 3731 #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) 3732 #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) 3733 /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write 3734 * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to 3735 * match the transfer direction, the direction needs to be specified. This bit allows a direction to 3736 * be chosen for the next operation. 3737 * 0b0..The expected next operation in Automatic Mode is an I2C write. 3738 * 0b1..The expected next operation in Automatic Mode is an I2C read. 3739 */ 3740 #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) 3741 /*! @} */ 3742 3743 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ 3744 /*! @{ */ 3745 #define I2C_SLVDAT_DATA_MASK (0xFFU) 3746 #define I2C_SLVDAT_DATA_SHIFT (0U) 3747 /*! DATA - Slave function data register. Read: read the most recently received data for the Slave 3748 * function. Write: transmit data using the Slave function. 3749 */ 3750 #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) 3751 /*! @} */ 3752 3753 /*! @name SLVADR - Slave address register. */ 3754 /*! @{ */ 3755 #define I2C_SLVADR_SADISABLE_MASK (0x1U) 3756 #define I2C_SLVADR_SADISABLE_SHIFT (0U) 3757 /*! SADISABLE - Slave Address n Disable. 3758 * 0b0..Enabled. Slave Address n is enabled. 3759 * 0b1..Ignored Slave Address n is ignored. 3760 */ 3761 #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) 3762 #define I2C_SLVADR_SLVADR_MASK (0xFEU) 3763 #define I2C_SLVADR_SLVADR_SHIFT (1U) 3764 /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. 3765 */ 3766 #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) 3767 #define I2C_SLVADR_AUTONACK_MASK (0x8000U) 3768 #define I2C_SLVADR_AUTONACK_SHIFT (15U) 3769 /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows 3770 * software to ignore I2C traffic while handling previous I2C data or other operations. 3771 * 0b0..Normal operation, matching I2C addresses are not ignored. 3772 * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches 3773 * SLVADRn, and AUTOMATCHREAD matches the direction. 3774 */ 3775 #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) 3776 /*! @} */ 3777 3778 /* The count of I2C_SLVADR */ 3779 #define I2C_SLVADR_COUNT (4U) 3780 3781 /*! @name SLVQUAL0 - Slave Qualification for address 0. */ 3782 /*! @{ */ 3783 #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) 3784 #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) 3785 /*! QUALMODE0 - Qualify mode for slave address 0. 3786 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 3787 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 3788 */ 3789 #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) 3790 #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) 3791 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) 3792 /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to 3793 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is 3794 * set to 1 will cause an automatic match of the corresponding bit of the received address when it 3795 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for 3796 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 3797 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 3798 */ 3799 #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) 3800 /*! @} */ 3801 3802 /*! @name MONRXDAT - Monitor receiver data register. */ 3803 /*! @{ */ 3804 #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) 3805 #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) 3806 /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 3807 */ 3808 #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) 3809 #define I2C_MONRXDAT_MONSTART_MASK (0x100U) 3810 #define I2C_MONRXDAT_MONSTART_SHIFT (8U) 3811 /*! MONSTART - Monitor Received Start. 3812 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. 3813 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. 3814 */ 3815 #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) 3816 #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) 3817 #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) 3818 /*! MONRESTART - Monitor Received Repeated Start. 3819 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 3820 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 3821 */ 3822 #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) 3823 #define I2C_MONRXDAT_MONNACK_MASK (0x400U) 3824 #define I2C_MONRXDAT_MONNACK_SHIFT (10U) 3825 /*! MONNACK - Monitor Received NACK. 3826 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 3827 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 3828 */ 3829 #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) 3830 /*! @} */ 3831 3832 3833 /*! 3834 * @} 3835 */ /* end of group I2C_Register_Masks */ 3836 3837 3838 /* I2C - Peripheral instance base addresses */ 3839 /** Peripheral I2C0 base address */ 3840 #define I2C0_BASE (0x40086000u) 3841 /** Peripheral I2C0 base pointer */ 3842 #define I2C0 ((I2C_Type *)I2C0_BASE) 3843 /** Peripheral I2C1 base address */ 3844 #define I2C1_BASE (0x40087000u) 3845 /** Peripheral I2C1 base pointer */ 3846 #define I2C1 ((I2C_Type *)I2C1_BASE) 3847 /** Peripheral I2C2 base address */ 3848 #define I2C2_BASE (0x40088000u) 3849 /** Peripheral I2C2 base pointer */ 3850 #define I2C2 ((I2C_Type *)I2C2_BASE) 3851 /** Peripheral I2C3 base address */ 3852 #define I2C3_BASE (0x40089000u) 3853 /** Peripheral I2C3 base pointer */ 3854 #define I2C3 ((I2C_Type *)I2C3_BASE) 3855 /** Peripheral I2C4 base address */ 3856 #define I2C4_BASE (0x4008A000u) 3857 /** Peripheral I2C4 base pointer */ 3858 #define I2C4 ((I2C_Type *)I2C4_BASE) 3859 /** Peripheral I2C5 base address */ 3860 #define I2C5_BASE (0x40096000u) 3861 /** Peripheral I2C5 base pointer */ 3862 #define I2C5 ((I2C_Type *)I2C5_BASE) 3863 /** Peripheral I2C6 base address */ 3864 #define I2C6_BASE (0x40097000u) 3865 /** Peripheral I2C6 base pointer */ 3866 #define I2C6 ((I2C_Type *)I2C6_BASE) 3867 /** Peripheral I2C7 base address */ 3868 #define I2C7_BASE (0x40098000u) 3869 /** Peripheral I2C7 base pointer */ 3870 #define I2C7 ((I2C_Type *)I2C7_BASE) 3871 /** Array initializer of I2C peripheral base addresses */ 3872 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } 3873 /** Array initializer of I2C peripheral base pointers */ 3874 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } 3875 /** Interrupt vectors for the I2C peripheral type */ 3876 #define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 3877 3878 /*! 3879 * @} 3880 */ /* end of group I2C_Peripheral_Access_Layer */ 3881 3882 3883 /* ---------------------------------------------------------------------------- 3884 -- I2S Peripheral Access Layer 3885 ---------------------------------------------------------------------------- */ 3886 3887 /*! 3888 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer 3889 * @{ 3890 */ 3891 3892 /** I2S - Register Layout Typedef */ 3893 typedef struct { 3894 uint8_t RESERVED_0[3072]; 3895 __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ 3896 __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ 3897 __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ 3898 uint8_t RESERVED_1[16]; 3899 __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ 3900 uint8_t RESERVED_2[480]; 3901 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ 3902 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ 3903 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ 3904 uint8_t RESERVED_3[4]; 3905 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ 3906 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ 3907 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ 3908 uint8_t RESERVED_4[4]; 3909 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ 3910 __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ 3911 uint8_t RESERVED_5[8]; 3912 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ 3913 __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ 3914 uint8_t RESERVED_6[8]; 3915 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ 3916 __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ 3917 } I2S_Type; 3918 3919 /* ---------------------------------------------------------------------------- 3920 -- I2S Register Masks 3921 ---------------------------------------------------------------------------- */ 3922 3923 /*! 3924 * @addtogroup I2S_Register_Masks I2S Register Masks 3925 * @{ 3926 */ 3927 3928 /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ 3929 /*! @{ */ 3930 #define I2S_CFG1_MAINENABLE_MASK (0x1U) 3931 #define I2S_CFG1_MAINENABLE_SHIFT (0U) 3932 /*! MAINENABLE - Main enable for I 2S function in this Flexcomm 3933 * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags 3934 * are reset. No other channel pairs can be enabled. 3935 * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. 3936 */ 3937 #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) 3938 #define I2S_CFG1_DATAPAUSE_MASK (0x2U) 3939 #define I2S_CFG1_DATAPAUSE_SHIFT (1U) 3940 /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer 3941 * and the FIFO. This could be done in order to change streams, or while restarting after a data 3942 * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is 3943 * in the process of being sent or received. Once a data pause has been requested, the interface 3944 * may need to complete sending data that was in progress before interrupting the flow of data. 3945 * Software must check that the pause is actually in effect before taking action. This is done by 3946 * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer 3947 * will resume at the beginning of the next frame. 3948 * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. 3949 * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. 3950 */ 3951 #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) 3952 #define I2S_CFG1_PAIRCOUNT_MASK (0xCU) 3953 #define I2S_CFG1_PAIRCOUNT_SHIFT (2U) 3954 /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field 3955 * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this 3956 * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs 3957 * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. 3958 * 0b00..1 I2S channel pairs in this flexcomm 3959 * 0b01..2 I2S channel pairs in this flexcomm 3960 * 0b10..3 I2S channel pairs in this flexcomm 3961 * 0b11..4 I2S channel pairs in this flexcomm 3962 */ 3963 #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) 3964 #define I2S_CFG1_MSTSLVCFG_MASK (0x30U) 3965 #define I2S_CFG1_MSTSLVCFG_SHIFT (4U) 3966 /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. 3967 * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. 3968 * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of 3969 * SCK, when divided from the Flexcomm function clock. 3970 * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. 3971 * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. 3972 */ 3973 #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) 3974 #define I2S_CFG1_MODE_MASK (0xC0U) 3975 #define I2S_CFG1_MODE_SHIFT (6U) 3976 /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all 3977 * supported cases. See Formats and modes for examples. 3978 * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece 3979 * of left channel data occurring during the first phase, and one pieces of right channel data occurring 3980 * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the 3981 * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If 3982 * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. 3983 * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. 3984 * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. 3985 * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. 3986 */ 3987 #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) 3988 #define I2S_CFG1_RIGHTLOW_MASK (0x100U) 3989 #define I2S_CFG1_RIGHTLOW_SHIFT (8U) 3990 /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left 3991 * and right channel data as it is transferred to or from the FIFO. This bit is not used if the 3992 * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 3993 * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION 3994 * can still place that data in the frame where right channel data is normally located. if all 3995 * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. 3996 * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO 3997 * bits 31:16 are used for the right channel. 3998 * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO 3999 * bits 15:0 are used for the right channel. 4000 */ 4001 #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) 4002 #define I2S_CFG1_LEFTJUST_MASK (0x200U) 4003 #define I2S_CFG1_LEFTJUST_SHIFT (9U) 4004 /*! LEFTJUST - Left Justify data. 4005 * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting 4006 * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data 4007 * in the stream on the data bus. 4008 * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting 4009 * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would 4010 * correspond to left justified data in the stream on the data bus. 4011 */ 4012 #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) 4013 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) 4014 #define I2S_CFG1_ONECHANNEL_SHIFT (10U) 4015 /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit 4016 * applies only to the first I2S channel pair. Other channel pairs may select this mode 4017 * independently in their separate CFG1 registers. 4018 * 0b0..I2S data for this channel pair is treated as left and right channels. 4019 * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this 4020 * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a 4021 * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel 4022 * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side 4023 * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data 4024 * for the single channel of data is placed at the clock defined by POSITION. 4025 */ 4026 #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) 4027 #define I2S_CFG1_PDMDATA_MASK (0x800U) 4028 #define I2S_CFG1_PDMDATA_SHIFT (11U) 4029 /*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be 4030 * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a 4031 * D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7. 4032 * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. 4033 * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in 4034 * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample 4035 * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. 4036 */ 4037 #define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) 4038 #define I2S_CFG1_SCK_POL_MASK (0x1000U) 4039 #define I2S_CFG1_SCK_POL_SHIFT (12U) 4040 /*! SCK_POL - SCK polarity. 4041 * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). 4042 * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. 4043 */ 4044 #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) 4045 #define I2S_CFG1_WS_POL_MASK (0x2000U) 4046 #define I2S_CFG1_WS_POL_SHIFT (13U) 4047 /*! WS_POL - WS polarity. 4048 * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). 4049 * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). 4050 */ 4051 #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) 4052 #define I2S_CFG1_DATALEN_MASK (0x1F0000U) 4053 #define I2S_CFG1_DATALEN_SHIFT (16U) 4054 /*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or 4055 * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received 4056 * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the 4057 * I2S: Determines the size of data transfers between the FIFO and the I2S 4058 * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of 4059 * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse 4060 * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 4061 * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = 4062 * data is 32 bits in length 4063 */ 4064 #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) 4065 /*! @} */ 4066 4067 /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ 4068 /*! @{ */ 4069 #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) 4070 #define I2S_CFG2_FRAMELEN_SHIFT (0U) 4071 /*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the 4072 * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 4073 * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 4074 * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in 4075 * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger 4076 * than DATALEN in order for the WS pulse to be generated correctly. 4077 */ 4078 #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) 4079 #define I2S_CFG2_POSITION_MASK (0x1FF0000U) 4080 #define I2S_CFG2_POSITION_SHIFT (16U) 4081 /*! POSITION - Data Position. Defines the location within the frame of the data for this channel 4082 * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION 4083 * defines the location of data in both the left phase and right phase, starting one clock after 4084 * the WS edge. In other modes, POSITION defines the location of data within the entire frame. 4085 * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The 4086 * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels 4087 * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit 4088 * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS 4089 * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. 4090 */ 4091 #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) 4092 /*! @} */ 4093 4094 /*! @name STAT - Status register for the primary channel pair. */ 4095 /*! @{ */ 4096 #define I2S_STAT_BUSY_MASK (0x1U) 4097 #define I2S_STAT_BUSY_SHIFT (0U) 4098 /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. 4099 * 0b0..The transmitter/receiver for channel pair is currently idle. 4100 * 0b1..The transmitter/receiver for channel pair is currently processing data. 4101 */ 4102 #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) 4103 #define I2S_STAT_SLVFRMERR_MASK (0x2U) 4104 #define I2S_STAT_SLVFRMERR_SHIFT (1U) 4105 /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as 4106 * a slave. An error indicates that the incoming WS signal did not transition as expected due to 4107 * a mismatch between FRAMELEN and the actual incoming I2S stream. 4108 * 0b0..No error has been recorded. 4109 * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. 4110 */ 4111 #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) 4112 #define I2S_STAT_LR_MASK (0x4U) 4113 #define I2S_STAT_LR_SHIFT (2U) 4114 /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to 4115 * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data 4116 * being processed for the currently busy channel pair. 4117 * 0b0..Left channel. 4118 * 0b1..Right channel. 4119 */ 4120 #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) 4121 #define I2S_STAT_DATAPAUSED_MASK (0x8U) 4122 #define I2S_STAT_DATAPAUSED_SHIFT (3U) 4123 /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels 4124 * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for 4125 * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. 4126 * 0b1..A data pause has been requested and is now in force. 4127 */ 4128 #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) 4129 /*! @} */ 4130 4131 /*! @name DIV - Clock divider, used by all channel pairs. */ 4132 /*! @{ */ 4133 #define I2S_DIV_DIV_MASK (0xFFFU) 4134 #define I2S_DIV_DIV_SHIFT (0U) 4135 /*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The 4136 * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 4137 * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is 4138 * divided by 4,096. 4139 */ 4140 #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) 4141 /*! @} */ 4142 4143 /*! @name FIFOCFG - FIFO configuration and enable register. */ 4144 /*! @{ */ 4145 #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) 4146 #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) 4147 /*! ENABLETX - Enable the transmit FIFO. 4148 * 0b0..The transmit FIFO is not enabled. 4149 * 0b1..The transmit FIFO is enabled. 4150 */ 4151 #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) 4152 #define I2S_FIFOCFG_ENABLERX_MASK (0x2U) 4153 #define I2S_FIFOCFG_ENABLERX_SHIFT (1U) 4154 /*! ENABLERX - Enable the receive FIFO. 4155 * 0b0..The receive FIFO is not enabled. 4156 * 0b1..The receive FIFO is enabled. 4157 */ 4158 #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) 4159 #define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) 4160 #define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) 4161 /*! TXI2SSE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX 4162 * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is 4163 * cleared, new data is provided, and the I2S is un-paused. 4164 * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 4165 * bits or less, or when MONO = 1 for this channel pair. 4166 * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. 4167 */ 4168 #define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) 4169 #define I2S_FIFOCFG_PACK48_MASK (0x8U) 4170 #define I2S_FIFOCFG_PACK48_SHIFT (3U) 4171 /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. 4172 * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. 4173 * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. 4174 */ 4175 #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) 4176 #define I2S_FIFOCFG_SIZE_MASK (0x30U) 4177 #define I2S_FIFOCFG_SIZE_SHIFT (4U) 4178 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 4179 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4180 */ 4181 #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) 4182 #define I2S_FIFOCFG_DMATX_MASK (0x1000U) 4183 #define I2S_FIFOCFG_DMATX_SHIFT (12U) 4184 /*! DMATX - DMA configuration for transmit. 4185 * 0b0..DMA is not used for the transmit function. 4186 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 4187 */ 4188 #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) 4189 #define I2S_FIFOCFG_DMARX_MASK (0x2000U) 4190 #define I2S_FIFOCFG_DMARX_SHIFT (13U) 4191 /*! DMARX - DMA configuration for receive. 4192 * 0b0..DMA is not used for the receive function. 4193 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 4194 */ 4195 #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) 4196 #define I2S_FIFOCFG_WAKETX_MASK (0x4000U) 4197 #define I2S_FIFOCFG_WAKETX_SHIFT (14U) 4198 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power 4199 * modes (up to power-down, as long as the peripheral function works in that power mode) without 4200 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 4201 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 4202 * Wake-up control register. 4203 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 4204 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in 4205 * FIFOTRIG, even when the TXLVL interrupt is not enabled. 4206 */ 4207 #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) 4208 #define I2S_FIFOCFG_WAKERX_MASK (0x8000U) 4209 #define I2S_FIFOCFG_WAKERX_SHIFT (15U) 4210 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power 4211 * modes (up to power-down, as long as the peripheral function works in that power mode) without 4212 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 4213 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 4214 * Wake-up control register. 4215 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 4216 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in 4217 * FIFOTRIG, even when the RXLVL interrupt is not enabled. 4218 */ 4219 #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) 4220 #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) 4221 #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) 4222 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 4223 */ 4224 #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) 4225 #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) 4226 #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) 4227 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 4228 */ 4229 #define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) 4230 #define I2S_FIFOCFG_POPDBG_MASK (0x40000U) 4231 #define I2S_FIFOCFG_POPDBG_SHIFT (18U) 4232 /*! POPDBG - Pop FIFO for debug reads. 4233 * 0b0..Debug reads of the FIFO do not pop the FIFO. 4234 * 0b1..A debug read will cause the FIFO to pop. 4235 */ 4236 #define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) 4237 /*! @} */ 4238 4239 /*! @name FIFOSTAT - FIFO status register. */ 4240 /*! @{ */ 4241 #define I2S_FIFOSTAT_TXERR_MASK (0x1U) 4242 #define I2S_FIFOSTAT_TXERR_SHIFT (0U) 4243 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow 4244 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is 4245 * needed. Cleared by writing a 1 to this bit. 4246 */ 4247 #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) 4248 #define I2S_FIFOSTAT_RXERR_MASK (0x2U) 4249 #define I2S_FIFOSTAT_RXERR_SHIFT (1U) 4250 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA 4251 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 4252 */ 4253 #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) 4254 #define I2S_FIFOSTAT_PERINT_MASK (0x8U) 4255 #define I2S_FIFOSTAT_PERINT_SHIFT (3U) 4256 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted 4257 * an interrupt. The details can be found by reading the peripheral's STAT register. 4258 */ 4259 #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) 4260 #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) 4261 #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) 4262 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4263 */ 4264 #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) 4265 #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) 4266 #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) 4267 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be 4268 * written. When 0, the transmit FIFO is full and another write would cause it to overflow. 4269 */ 4270 #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) 4271 #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) 4272 #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) 4273 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 4274 */ 4275 #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) 4276 #define I2S_FIFOSTAT_RXFULL_MASK (0x80U) 4277 #define I2S_FIFOSTAT_RXFULL_SHIFT (7U) 4278 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to 4279 * prevent the peripheral from causing an overflow. 4280 */ 4281 #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) 4282 #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) 4283 #define I2S_FIFOSTAT_TXLVL_SHIFT (8U) 4284 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY 4285 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at 4286 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 4287 * 0. 4288 */ 4289 #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) 4290 #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) 4291 #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) 4292 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and 4293 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the 4294 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 4295 * 1. 4296 */ 4297 #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) 4298 /*! @} */ 4299 4300 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ 4301 /*! @{ */ 4302 #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) 4303 #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) 4304 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled 4305 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 4306 * 0b0..Transmit FIFO level does not generate a FIFO level trigger. 4307 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 4308 */ 4309 #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) 4310 #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) 4311 #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) 4312 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled 4313 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 4314 * 0b0..Receive FIFO level does not generate a FIFO level trigger. 4315 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 4316 */ 4317 #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) 4318 #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) 4319 #define I2S_FIFOTRIG_TXLVL_SHIFT (8U) 4320 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled 4321 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to 4322 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO 4323 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX 4324 * FIFO level decreases to 15 entries (is no longer full). 4325 */ 4326 #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) 4327 #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) 4328 #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) 4329 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data 4330 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level 4331 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See 4332 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no 4333 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX 4334 * FIFO has received 16 entries (has become full). 4335 */ 4336 #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) 4337 /*! @} */ 4338 4339 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ 4340 /*! @{ */ 4341 #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) 4342 #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) 4343 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 4344 * 0b0..No interrupt will be generated for a transmit error. 4345 * 0b1..An interrupt will be generated when a transmit error occurs. 4346 */ 4347 #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) 4348 #define I2S_FIFOINTENSET_RXERR_MASK (0x2U) 4349 #define I2S_FIFOINTENSET_RXERR_SHIFT (1U) 4350 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 4351 * 0b0..No interrupt will be generated for a receive error. 4352 * 0b1..An interrupt will be generated when a receive error occurs. 4353 */ 4354 #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) 4355 #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) 4356 #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) 4357 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level 4358 * specified by the TXLVL field in the FIFOTRIG register. 4359 * 0b0..No interrupt will be generated based on the TX FIFO level. 4360 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases 4361 * to the level specified by TXLVL in the FIFOTRIG register. 4362 */ 4363 #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) 4364 #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) 4365 #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) 4366 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level 4367 * specified by the TXLVL field in the FIFOTRIG register. 4368 * 0b0..No interrupt will be generated based on the RX FIFO level. 4369 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level 4370 * increases to the level specified by RXLVL in the FIFOTRIG register. 4371 */ 4372 #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) 4373 /*! @} */ 4374 4375 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ 4376 /*! @{ */ 4377 #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) 4378 #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) 4379 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 4380 */ 4381 #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) 4382 #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) 4383 #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) 4384 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 4385 */ 4386 #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) 4387 #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) 4388 #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) 4389 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 4390 */ 4391 #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) 4392 #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) 4393 #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) 4394 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 4395 */ 4396 #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) 4397 /*! @} */ 4398 4399 /*! @name FIFOINTSTAT - FIFO interrupt status register. */ 4400 /*! @{ */ 4401 #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) 4402 #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) 4403 /*! TXERR - TX FIFO error. 4404 */ 4405 #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) 4406 #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) 4407 #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) 4408 /*! RXERR - RX FIFO error. 4409 */ 4410 #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) 4411 #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) 4412 #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) 4413 /*! TXLVL - Transmit FIFO level interrupt. 4414 */ 4415 #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) 4416 #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) 4417 #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) 4418 /*! RXLVL - Receive FIFO level interrupt. 4419 */ 4420 #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) 4421 #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) 4422 #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) 4423 /*! PERINT - Peripheral interrupt. 4424 */ 4425 #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) 4426 /*! @} */ 4427 4428 /*! @name FIFOWR - FIFO write data. */ 4429 /*! @{ */ 4430 #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) 4431 #define I2S_FIFOWR_TXDATA_SHIFT (0U) 4432 /*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. 4433 */ 4434 #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) 4435 /*! @} */ 4436 4437 /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ 4438 /*! @{ */ 4439 #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) 4440 #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) 4441 /*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. 4442 */ 4443 #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) 4444 /*! @} */ 4445 4446 /*! @name FIFORD - FIFO read data. */ 4447 /*! @{ */ 4448 #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) 4449 #define I2S_FIFORD_RXDATA_SHIFT (0U) 4450 /*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. 4451 */ 4452 #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) 4453 /*! @} */ 4454 4455 /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ 4456 /*! @{ */ 4457 #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) 4458 #define I2S_FIFORD48H_RXDATA_SHIFT (0U) 4459 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 4460 */ 4461 #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) 4462 /*! @} */ 4463 4464 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ 4465 /*! @{ */ 4466 #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) 4467 #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) 4468 /*! RXDATA - Received data from the FIFO. 4469 */ 4470 #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) 4471 /*! @} */ 4472 4473 /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ 4474 /*! @{ */ 4475 #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) 4476 #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) 4477 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 4478 */ 4479 #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) 4480 /*! @} */ 4481 4482 4483 /*! 4484 * @} 4485 */ /* end of group I2S_Register_Masks */ 4486 4487 4488 /* I2S - Peripheral instance base addresses */ 4489 /** Peripheral I2S0 base address */ 4490 #define I2S0_BASE (0x40097000u) 4491 /** Peripheral I2S0 base pointer */ 4492 #define I2S0 ((I2S_Type *)I2S0_BASE) 4493 /** Peripheral I2S1 base address */ 4494 #define I2S1_BASE (0x40098000u) 4495 /** Peripheral I2S1 base pointer */ 4496 #define I2S1 ((I2S_Type *)I2S1_BASE) 4497 /** Array initializer of I2S peripheral base addresses */ 4498 #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } 4499 /** Array initializer of I2S peripheral base pointers */ 4500 #define I2S_BASE_PTRS { I2S0, I2S1 } 4501 /** Interrupt vectors for the I2S peripheral type */ 4502 #define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 4503 4504 /*! 4505 * @} 4506 */ /* end of group I2S_Peripheral_Access_Layer */ 4507 4508 4509 /* ---------------------------------------------------------------------------- 4510 -- INPUTMUX Peripheral Access Layer 4511 ---------------------------------------------------------------------------- */ 4512 4513 /*! 4514 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer 4515 * @{ 4516 */ 4517 4518 /** INPUTMUX - Register Layout Typedef */ 4519 typedef struct { 4520 uint8_t RESERVED_0[192]; 4521 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ 4522 __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ 4523 uint8_t RESERVED_1[40]; 4524 __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ 4525 uint8_t RESERVED_2[16]; 4526 __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ 4527 __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ 4528 } INPUTMUX_Type; 4529 4530 /* ---------------------------------------------------------------------------- 4531 -- INPUTMUX Register Masks 4532 ---------------------------------------------------------------------------- */ 4533 4534 /*! 4535 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks 4536 * @{ 4537 */ 4538 4539 /*! @name PINTSEL - Pin interrupt select register */ 4540 /*! @{ */ 4541 #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) 4542 #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) 4543 /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63). 4544 */ 4545 #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) 4546 /*! @} */ 4547 4548 /* The count of INPUTMUX_PINTSEL */ 4549 #define INPUTMUX_PINTSEL_COUNT (8U) 4550 4551 /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ 4552 /*! @{ */ 4553 #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) 4554 #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) 4555 /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A 4556 * interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = 4557 * Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match 4558 * 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer 4559 * CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin 4560 * interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 4561 * 19 = DMA output trigger mux 3 4562 */ 4563 #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) 4564 /*! @} */ 4565 4566 /* The count of INPUTMUX_DMA_ITRIG_INMUX */ 4567 #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) 4568 4569 /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ 4570 /*! @{ */ 4571 #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) 4572 #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) 4573 /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19). 4574 */ 4575 #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) 4576 /*! @} */ 4577 4578 /* The count of INPUTMUX_DMA_OTRIG_INMUX */ 4579 #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) 4580 4581 /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ 4582 /*! @{ */ 4583 #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) 4584 #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) 4585 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = 4586 * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock 4587 * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 4588 */ 4589 #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) 4590 /*! @} */ 4591 4592 /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ 4593 /*! @{ */ 4594 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) 4595 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) 4596 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = 4597 * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock 4598 * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 4599 */ 4600 #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) 4601 /*! @} */ 4602 4603 4604 /*! 4605 * @} 4606 */ /* end of group INPUTMUX_Register_Masks */ 4607 4608 4609 /* INPUTMUX - Peripheral instance base addresses */ 4610 /** Peripheral INPUTMUX base address */ 4611 #define INPUTMUX_BASE (0x40005000u) 4612 /** Peripheral INPUTMUX base pointer */ 4613 #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) 4614 /** Array initializer of INPUTMUX peripheral base addresses */ 4615 #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } 4616 /** Array initializer of INPUTMUX peripheral base pointers */ 4617 #define INPUTMUX_BASE_PTRS { INPUTMUX } 4618 4619 /*! 4620 * @} 4621 */ /* end of group INPUTMUX_Peripheral_Access_Layer */ 4622 4623 4624 /* ---------------------------------------------------------------------------- 4625 -- IOCON Peripheral Access Layer 4626 ---------------------------------------------------------------------------- */ 4627 4628 /*! 4629 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer 4630 * @{ 4631 */ 4632 4633 /** IOCON - Register Layout Typedef */ 4634 typedef struct { 4635 __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ 4636 } IOCON_Type; 4637 4638 /* ---------------------------------------------------------------------------- 4639 -- IOCON Register Masks 4640 ---------------------------------------------------------------------------- */ 4641 4642 /*! 4643 * @addtogroup IOCON_Register_Masks IOCON Register Masks 4644 * @{ 4645 */ 4646 4647 /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ 4648 /*! @{ */ 4649 #define IOCON_PIO_FUNC_MASK (0x7U) 4650 #define IOCON_PIO_FUNC_SHIFT (0U) 4651 /*! FUNC - Selects pin function. 4652 * 0b000..Alternative connection 0. 4653 * 0b001..Alternative connection 1. 4654 * 0b010..Alternative connection 2. 4655 * 0b011..Alternative connection 3. 4656 * 0b100..Alternative connection 4. 4657 * 0b101..Alternative connection 5. 4658 * 0b110..Alternative connection 6. 4659 * 0b111..Alternative connection 7. 4660 */ 4661 #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) 4662 #define IOCON_PIO_MODE_MASK (0x18U) 4663 #define IOCON_PIO_MODE_SHIFT (3U) 4664 /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). 4665 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). 4666 * 0b01..Pull-down. Pull-down resistor enabled. 4667 * 0b10..Pull-up. Pull-up resistor enabled. 4668 * 0b11..Repeater. Repeater mode. 4669 */ 4670 #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) 4671 #define IOCON_PIO_I2CSLEW_MASK (0x20U) 4672 #define IOCON_PIO_I2CSLEW_SHIFT (5U) 4673 /*! I2CSLEW - Controls slew rate of I2C pad. 4674 * 0b0..I2C mode. 4675 * 0b1..GPIO mode. 4676 */ 4677 #define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) 4678 #define IOCON_PIO_INVERT_MASK (0x40U) 4679 #define IOCON_PIO_INVERT_SHIFT (6U) 4680 /*! INVERT - Input polarity. 4681 * 0b0..Disabled. Input function is not inverted. 4682 * 0b1..Enabled. Input is function inverted. 4683 */ 4684 #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) 4685 #define IOCON_PIO_DIGIMODE_MASK (0x80U) 4686 #define IOCON_PIO_DIGIMODE_SHIFT (7U) 4687 /*! DIGIMODE - Select Analog/Digital mode. 4688 * 0b0..Analog mode. 4689 * 0b1..Digital mode. 4690 */ 4691 #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) 4692 #define IOCON_PIO_FILTEROFF_MASK (0x100U) 4693 #define IOCON_PIO_FILTEROFF_SHIFT (8U) 4694 /*! FILTEROFF - Controls input glitch filter. 4695 * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. 4696 * 0b1..Filter disabled. No input filtering is done. 4697 */ 4698 #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) 4699 #define IOCON_PIO_I2CDRIVE_MASK (0x200U) 4700 #define IOCON_PIO_I2CDRIVE_SHIFT (9U) 4701 /*! I2CDRIVE - Controls the current sink capability of the pin. 4702 * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 4703 * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate 4704 * specific device data sheet for details. 4705 */ 4706 #define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) 4707 #define IOCON_PIO_SLEW_MASK (0x200U) 4708 #define IOCON_PIO_SLEW_SHIFT (9U) 4709 /*! SLEW - Driver slew rate. 4710 * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 4711 * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 4712 */ 4713 #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) 4714 #define IOCON_PIO_I2CFILTER_MASK (0x400U) 4715 #define IOCON_PIO_I2CFILTER_SHIFT (10U) 4716 /*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. 4717 * 0b0..Enabled. I2C 50 ns glitch filter enabled. 4718 * 0b1..Disabled. I2C 50 ns glitch filter disabled. 4719 */ 4720 #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) 4721 #define IOCON_PIO_OD_MASK (0x400U) 4722 #define IOCON_PIO_OD_SHIFT (10U) 4723 /*! OD - Controls open-drain mode. 4724 * 0b0..Normal. Normal push-pull output 4725 * 0b1..Open-drain. Simulated open-drain output (high drive disabled). 4726 */ 4727 #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) 4728 /*! @} */ 4729 4730 /* The count of IOCON_PIO */ 4731 #define IOCON_PIO_COUNT (2U) 4732 4733 /* The count of IOCON_PIO */ 4734 #define IOCON_PIO_COUNT2 (32U) 4735 4736 4737 /*! 4738 * @} 4739 */ /* end of group IOCON_Register_Masks */ 4740 4741 4742 /* IOCON - Peripheral instance base addresses */ 4743 /** Peripheral IOCON base address */ 4744 #define IOCON_BASE (0x40001000u) 4745 /** Peripheral IOCON base pointer */ 4746 #define IOCON ((IOCON_Type *)IOCON_BASE) 4747 /** Array initializer of IOCON peripheral base addresses */ 4748 #define IOCON_BASE_ADDRS { IOCON_BASE } 4749 /** Array initializer of IOCON peripheral base pointers */ 4750 #define IOCON_BASE_PTRS { IOCON } 4751 4752 /*! 4753 * @} 4754 */ /* end of group IOCON_Peripheral_Access_Layer */ 4755 4756 4757 /* ---------------------------------------------------------------------------- 4758 -- MAILBOX Peripheral Access Layer 4759 ---------------------------------------------------------------------------- */ 4760 4761 /*! 4762 * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer 4763 * @{ 4764 */ 4765 4766 /** MAILBOX - Register Layout Typedef */ 4767 typedef struct { 4768 struct { /* offset: 0x0, array step: 0x10 */ 4769 __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ 4770 __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ 4771 __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ 4772 uint8_t RESERVED_0[4]; 4773 } MBOXIRQ[2]; 4774 uint8_t RESERVED_0[216]; 4775 __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ 4776 } MAILBOX_Type; 4777 4778 /* ---------------------------------------------------------------------------- 4779 -- MAILBOX Register Masks 4780 ---------------------------------------------------------------------------- */ 4781 4782 /*! 4783 * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks 4784 * @{ 4785 */ 4786 4787 /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ 4788 /*! @{ */ 4789 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) 4790 #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) 4791 /*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. 4792 */ 4793 #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) 4794 /*! @} */ 4795 4796 /* The count of MAILBOX_MBOXIRQ_IRQ */ 4797 #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) 4798 4799 /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ 4800 /*! @{ */ 4801 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) 4802 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) 4803 /*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. 4804 */ 4805 #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) 4806 /*! @} */ 4807 4808 /* The count of MAILBOX_MBOXIRQ_IRQSET */ 4809 #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) 4810 4811 /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ 4812 /*! @{ */ 4813 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) 4814 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) 4815 /*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. 4816 */ 4817 #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) 4818 /*! @} */ 4819 4820 /* The count of MAILBOX_MBOXIRQ_IRQCLR */ 4821 #define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) 4822 4823 /*! @name MUTEX - Mutual exclusion register[1] */ 4824 /*! @{ */ 4825 #define MAILBOX_MUTEX_EX_MASK (0x1U) 4826 #define MAILBOX_MUTEX_EX_SHIFT (0U) 4827 /*! EX - Cleared when read, set when written. See usage description above. 4828 */ 4829 #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) 4830 /*! @} */ 4831 4832 4833 /*! 4834 * @} 4835 */ /* end of group MAILBOX_Register_Masks */ 4836 4837 4838 /* MAILBOX - Peripheral instance base addresses */ 4839 /** Peripheral MAILBOX base address */ 4840 #define MAILBOX_BASE (0x4008B000u) 4841 /** Peripheral MAILBOX base pointer */ 4842 #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) 4843 /** Array initializer of MAILBOX peripheral base addresses */ 4844 #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } 4845 /** Array initializer of MAILBOX peripheral base pointers */ 4846 #define MAILBOX_BASE_PTRS { MAILBOX } 4847 /** Interrupt vectors for the MAILBOX peripheral type */ 4848 #define MAILBOX_IRQS { MAILBOX_IRQn } 4849 4850 /*! 4851 * @} 4852 */ /* end of group MAILBOX_Peripheral_Access_Layer */ 4853 4854 4855 /* ---------------------------------------------------------------------------- 4856 -- MRT Peripheral Access Layer 4857 ---------------------------------------------------------------------------- */ 4858 4859 /*! 4860 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer 4861 * @{ 4862 */ 4863 4864 /** MRT - Register Layout Typedef */ 4865 typedef struct { 4866 struct { /* offset: 0x0, array step: 0x10 */ 4867 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ 4868 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ 4869 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ 4870 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ 4871 } CHANNEL[4]; 4872 uint8_t RESERVED_0[176]; 4873 __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ 4874 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ 4875 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ 4876 } MRT_Type; 4877 4878 /* ---------------------------------------------------------------------------- 4879 -- MRT Register Masks 4880 ---------------------------------------------------------------------------- */ 4881 4882 /*! 4883 * @addtogroup MRT_Register_Masks MRT Register Masks 4884 * @{ 4885 */ 4886 4887 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ 4888 /*! @{ */ 4889 #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) 4890 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) 4891 /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT 4892 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to 4893 * this bit field starts the timer immediately. If the timer is running, writing a zero to this 4894 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer 4895 * stops at the end of the time interval. 4896 */ 4897 #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) 4898 #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) 4899 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) 4900 /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. 4901 * This bit is write-only. Reading this bit always returns 0. 4902 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the 4903 * time interval if the repeat mode is selected. 4904 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 4905 */ 4906 #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) 4907 /*! @} */ 4908 4909 /* The count of MRT_CHANNEL_INTVAL */ 4910 #define MRT_CHANNEL_INTVAL_COUNT (4U) 4911 4912 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ 4913 /*! @{ */ 4914 #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) 4915 #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) 4916 /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn 4917 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval 4918 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn 4919 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields 4920 * returns -1 (0x00FF FFFF). 4921 */ 4922 #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) 4923 /*! @} */ 4924 4925 /* The count of MRT_CHANNEL_TIMER */ 4926 #define MRT_CHANNEL_TIMER_COUNT (4U) 4927 4928 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ 4929 /*! @{ */ 4930 #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) 4931 #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) 4932 /*! INTEN - Enable the TIMERn interrupt. 4933 * 0b0..Disabled. TIMERn interrupt is disabled. 4934 * 0b1..Enabled. TIMERn interrupt is enabled. 4935 */ 4936 #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) 4937 #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) 4938 #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) 4939 /*! MODE - Selects timer mode. 4940 * 0b00..Repeat interrupt mode. 4941 * 0b01..One-shot interrupt mode. 4942 * 0b10..One-shot stall mode. 4943 * 0b11..Reserved. 4944 */ 4945 #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) 4946 /*! @} */ 4947 4948 /* The count of MRT_CHANNEL_CTRL */ 4949 #define MRT_CHANNEL_CTRL_COUNT (4U) 4950 4951 /*! @name CHANNEL_STAT - MRT Status register. */ 4952 /*! @{ */ 4953 #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) 4954 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) 4955 /*! INTFLAG - Monitors the interrupt flag. 4956 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 4957 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If 4958 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt 4959 * are raised. Writing a 1 to this bit clears the interrupt request. 4960 */ 4961 #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) 4962 #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) 4963 #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) 4964 /*! RUN - Indicates the state of TIMERn. This bit is read-only. 4965 * 0b0..Idle state. TIMERn is stopped. 4966 * 0b1..Running. TIMERn is running. 4967 */ 4968 #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) 4969 #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) 4970 #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) 4971 /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG 4972 * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating 4973 * modes. 4974 * 0b0..This channel is not in use. 4975 * 0b1..This channel is in use. 4976 */ 4977 #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) 4978 /*! @} */ 4979 4980 /* The count of MRT_CHANNEL_STAT */ 4981 #define MRT_CHANNEL_STAT_COUNT (4U) 4982 4983 /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ 4984 /*! @{ */ 4985 #define MRT_MODCFG_NOC_MASK (0xFU) 4986 #define MRT_MODCFG_NOC_SHIFT (0U) 4987 /*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) 4988 */ 4989 #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) 4990 #define MRT_MODCFG_NOB_MASK (0x1F0U) 4991 #define MRT_MODCFG_NOB_SHIFT (4U) 4992 /*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) 4993 */ 4994 #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) 4995 #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) 4996 #define MRT_MODCFG_MULTITASK_SHIFT (31U) 4997 /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. 4998 * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. 4999 * 0b1..Multi-task mode. 5000 */ 5001 #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) 5002 /*! @} */ 5003 5004 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ 5005 /*! @{ */ 5006 #define MRT_IDLE_CH_CHAN_MASK (0xF0U) 5007 #define MRT_IDLE_CH_CHAN_SHIFT (4U) 5008 /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is 5009 * positioned such that it can be used as an offset from the MRT base address in order to access 5010 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See 5011 * text above for more details. 5012 */ 5013 #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) 5014 /*! @} */ 5015 5016 /*! @name IRQ_FLAG - Global interrupt flag register */ 5017 /*! @{ */ 5018 #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) 5019 #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) 5020 /*! GFLAG0 - Monitors the interrupt flag of TIMER0. 5021 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 5022 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If 5023 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global 5024 * interrupt are raised. Writing a 1 to this bit clears the interrupt request. 5025 */ 5026 #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) 5027 #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) 5028 #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) 5029 /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. 5030 */ 5031 #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) 5032 #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) 5033 #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) 5034 /*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. 5035 */ 5036 #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) 5037 #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) 5038 #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) 5039 /*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. 5040 */ 5041 #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) 5042 /*! @} */ 5043 5044 5045 /*! 5046 * @} 5047 */ /* end of group MRT_Register_Masks */ 5048 5049 5050 /* MRT - Peripheral instance base addresses */ 5051 /** Peripheral MRT0 base address */ 5052 #define MRT0_BASE (0x4000D000u) 5053 /** Peripheral MRT0 base pointer */ 5054 #define MRT0 ((MRT_Type *)MRT0_BASE) 5055 /** Array initializer of MRT peripheral base addresses */ 5056 #define MRT_BASE_ADDRS { MRT0_BASE } 5057 /** Array initializer of MRT peripheral base pointers */ 5058 #define MRT_BASE_PTRS { MRT0 } 5059 /** Interrupt vectors for the MRT peripheral type */ 5060 #define MRT_IRQS { MRT0_IRQn } 5061 5062 /*! 5063 * @} 5064 */ /* end of group MRT_Peripheral_Access_Layer */ 5065 5066 5067 /* ---------------------------------------------------------------------------- 5068 -- PINT Peripheral Access Layer 5069 ---------------------------------------------------------------------------- */ 5070 5071 /*! 5072 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer 5073 * @{ 5074 */ 5075 5076 /** PINT - Register Layout Typedef */ 5077 typedef struct { 5078 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ 5079 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ 5080 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ 5081 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ 5082 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ 5083 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ 5084 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ 5085 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ 5086 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ 5087 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ 5088 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ 5089 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ 5090 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ 5091 } PINT_Type; 5092 5093 /* ---------------------------------------------------------------------------- 5094 -- PINT Register Masks 5095 ---------------------------------------------------------------------------- */ 5096 5097 /*! 5098 * @addtogroup PINT_Register_Masks PINT Register Masks 5099 * @{ 5100 */ 5101 5102 /*! @name ISEL - Pin Interrupt Mode register */ 5103 /*! @{ */ 5104 #define PINT_ISEL_PMODE_MASK (0xFFU) 5105 #define PINT_ISEL_PMODE_SHIFT (0U) 5106 /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt 5107 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 5108 */ 5109 #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) 5110 /*! @} */ 5111 5112 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ 5113 /*! @{ */ 5114 #define PINT_IENR_ENRL_MASK (0xFFU) 5115 #define PINT_IENR_ENRL_SHIFT (0U) 5116 /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the 5117 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable 5118 * rising edge or level interrupt. 5119 */ 5120 #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) 5121 /*! @} */ 5122 5123 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ 5124 /*! @{ */ 5125 #define PINT_SIENR_SETENRL_MASK (0xFFU) 5126 #define PINT_SIENR_SETENRL_SHIFT (0U) 5127 /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n 5128 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 5129 */ 5130 #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) 5131 /*! @} */ 5132 5133 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ 5134 /*! @{ */ 5135 #define PINT_CIENR_CENRL_MASK (0xFFU) 5136 #define PINT_CIENR_CENRL_SHIFT (0U) 5137 /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit 5138 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level 5139 * interrupt. 5140 */ 5141 #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) 5142 /*! @} */ 5143 5144 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ 5145 /*! @{ */ 5146 #define PINT_IENF_ENAF_MASK (0xFFU) 5147 #define PINT_IENF_ENAF_SHIFT (0U) 5148 /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. 5149 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt 5150 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active 5151 * interrupt level HIGH. 5152 */ 5153 #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) 5154 /*! @} */ 5155 5156 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ 5157 /*! @{ */ 5158 #define PINT_SIENF_SETENAF_MASK (0xFFU) 5159 #define PINT_SIENF_SETENAF_SHIFT (0U) 5160 /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n 5161 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable 5162 * falling edge interrupt. 5163 */ 5164 #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) 5165 /*! @} */ 5166 5167 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ 5168 /*! @{ */ 5169 #define PINT_CIENF_CENAF_MASK (0xFFU) 5170 #define PINT_CIENF_CENAF_SHIFT (0U) 5171 /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n 5172 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or 5173 * falling edge interrupt disabled. 5174 */ 5175 #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) 5176 /*! @} */ 5177 5178 /*! @name RISE - Pin interrupt rising edge register */ 5179 /*! @{ */ 5180 #define PINT_RISE_RDET_MASK (0xFFU) 5181 #define PINT_RISE_RDET_SHIFT (0U) 5182 /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 5183 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written 5184 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the 5185 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 5186 */ 5187 #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) 5188 /*! @} */ 5189 5190 /*! @name FALL - Pin interrupt falling edge register */ 5191 /*! @{ */ 5192 #define PINT_FALL_FDET_MASK (0xFFU) 5193 #define PINT_FALL_FDET_SHIFT (0U) 5194 /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 5195 * 0: No falling edge has been detected on this pin since Reset or the last time a one was 5196 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or 5197 * the last time a one was written to this bit. Write 1: clear falling edge detection for this 5198 * pin. 5199 */ 5200 #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) 5201 /*! @} */ 5202 5203 /*! @name IST - Pin interrupt status register */ 5204 /*! @{ */ 5205 #define PINT_IST_PSTAT_MASK (0xFFU) 5206 #define PINT_IST_PSTAT_SHIFT (0U) 5207 /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts 5208 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for 5209 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this 5210 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. 5211 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 5212 */ 5213 #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) 5214 /*! @} */ 5215 5216 /*! @name PMCTRL - Pattern match interrupt control register */ 5217 /*! @{ */ 5218 #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) 5219 #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) 5220 /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 5221 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 5222 * 0b1..Pattern match. Interrupts are driven in response to pattern matches. 5223 */ 5224 #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) 5225 #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) 5226 #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) 5227 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 5228 * 0b0..Disabled. RXEV output to the CPU is disabled. 5229 * 0b1..Enabled. RXEV output to the CPU is enabled. 5230 */ 5231 #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) 5232 #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) 5233 #define PINT_PMCTRL_PMAT_SHIFT (24U) 5234 /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field 5235 * indicates that the corresponding product term is matched by the current state of the appropriate 5236 * inputs. 5237 */ 5238 #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) 5239 /*! @} */ 5240 5241 /*! @name PMSRC - Pattern match interrupt bit-slice source register */ 5242 /*! @{ */ 5243 #define PINT_PMSRC_SRC0_MASK (0x700U) 5244 #define PINT_PMSRC_SRC0_SHIFT (8U) 5245 /*! SRC0 - Selects the input source for bit slice 0 5246 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 5247 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 5248 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 5249 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 5250 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 5251 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 5252 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 5253 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 5254 */ 5255 #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) 5256 #define PINT_PMSRC_SRC1_MASK (0x3800U) 5257 #define PINT_PMSRC_SRC1_SHIFT (11U) 5258 /*! SRC1 - Selects the input source for bit slice 1 5259 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 5260 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 5261 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 5262 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 5263 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 5264 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 5265 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 5266 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 5267 */ 5268 #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) 5269 #define PINT_PMSRC_SRC2_MASK (0x1C000U) 5270 #define PINT_PMSRC_SRC2_SHIFT (14U) 5271 /*! SRC2 - Selects the input source for bit slice 2 5272 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 5273 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 5274 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 5275 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 5276 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 5277 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 5278 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 5279 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 5280 */ 5281 #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) 5282 #define PINT_PMSRC_SRC3_MASK (0xE0000U) 5283 #define PINT_PMSRC_SRC3_SHIFT (17U) 5284 /*! SRC3 - Selects the input source for bit slice 3 5285 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 5286 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 5287 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 5288 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 5289 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 5290 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 5291 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 5292 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 5293 */ 5294 #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) 5295 #define PINT_PMSRC_SRC4_MASK (0x700000U) 5296 #define PINT_PMSRC_SRC4_SHIFT (20U) 5297 /*! SRC4 - Selects the input source for bit slice 4 5298 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 5299 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 5300 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 5301 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 5302 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 5303 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 5304 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 5305 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 5306 */ 5307 #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) 5308 #define PINT_PMSRC_SRC5_MASK (0x3800000U) 5309 #define PINT_PMSRC_SRC5_SHIFT (23U) 5310 /*! SRC5 - Selects the input source for bit slice 5 5311 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 5312 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 5313 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 5314 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 5315 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 5316 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 5317 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 5318 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 5319 */ 5320 #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) 5321 #define PINT_PMSRC_SRC6_MASK (0x1C000000U) 5322 #define PINT_PMSRC_SRC6_SHIFT (26U) 5323 /*! SRC6 - Selects the input source for bit slice 6 5324 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 5325 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 5326 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 5327 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 5328 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 5329 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 5330 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 5331 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 5332 */ 5333 #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) 5334 #define PINT_PMSRC_SRC7_MASK (0xE0000000U) 5335 #define PINT_PMSRC_SRC7_SHIFT (29U) 5336 /*! SRC7 - Selects the input source for bit slice 7 5337 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 5338 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 5339 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 5340 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 5341 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 5342 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 5343 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 5344 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 5345 */ 5346 #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) 5347 /*! @} */ 5348 5349 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ 5350 /*! @{ */ 5351 #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) 5352 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) 5353 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. 5354 * 0b0..No effect. Slice 0 is not an endpoint. 5355 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 5356 */ 5357 #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) 5358 #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) 5359 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) 5360 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. 5361 * 0b0..No effect. Slice 1 is not an endpoint. 5362 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 5363 */ 5364 #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) 5365 #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) 5366 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) 5367 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. 5368 * 0b0..No effect. Slice 2 is not an endpoint. 5369 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 5370 */ 5371 #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) 5372 #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) 5373 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) 5374 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. 5375 * 0b0..No effect. Slice 3 is not an endpoint. 5376 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 5377 */ 5378 #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) 5379 #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) 5380 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) 5381 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. 5382 * 0b0..No effect. Slice 4 is not an endpoint. 5383 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 5384 */ 5385 #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) 5386 #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) 5387 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) 5388 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. 5389 * 0b0..No effect. Slice 5 is not an endpoint. 5390 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 5391 */ 5392 #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) 5393 #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) 5394 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) 5395 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. 5396 * 0b0..No effect. Slice 6 is not an endpoint. 5397 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 5398 */ 5399 #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) 5400 #define PINT_PMCFG_CFG0_MASK (0x700U) 5401 #define PINT_PMCFG_CFG0_SHIFT (8U) 5402 /*! CFG0 - Specifies the match contribution condition for bit slice 0. 5403 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5404 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5405 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5406 * PMSRC registers are written to. 5407 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5408 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5409 * PMSRC registers are written to. 5410 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5411 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5412 * cleared when the PMCFG or the PMSRC registers are written to. 5413 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5414 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5415 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5416 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5417 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5418 * is cleared after one clock cycle. 5419 */ 5420 #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) 5421 #define PINT_PMCFG_CFG1_MASK (0x3800U) 5422 #define PINT_PMCFG_CFG1_SHIFT (11U) 5423 /*! CFG1 - Specifies the match contribution condition for bit slice 1. 5424 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5425 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5426 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5427 * PMSRC registers are written to. 5428 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5429 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5430 * PMSRC registers are written to. 5431 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5432 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5433 * cleared when the PMCFG or the PMSRC registers are written to. 5434 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5435 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5436 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5437 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5438 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5439 * is cleared after one clock cycle. 5440 */ 5441 #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) 5442 #define PINT_PMCFG_CFG2_MASK (0x1C000U) 5443 #define PINT_PMCFG_CFG2_SHIFT (14U) 5444 /*! CFG2 - Specifies the match contribution condition for bit slice 2. 5445 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5446 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5447 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5448 * PMSRC registers are written to. 5449 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5450 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5451 * PMSRC registers are written to. 5452 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5453 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5454 * cleared when the PMCFG or the PMSRC registers are written to. 5455 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5456 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5457 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5458 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5459 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5460 * is cleared after one clock cycle. 5461 */ 5462 #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) 5463 #define PINT_PMCFG_CFG3_MASK (0xE0000U) 5464 #define PINT_PMCFG_CFG3_SHIFT (17U) 5465 /*! CFG3 - Specifies the match contribution condition for bit slice 3. 5466 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5467 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5468 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5469 * PMSRC registers are written to. 5470 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5471 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5472 * PMSRC registers are written to. 5473 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5474 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5475 * cleared when the PMCFG or the PMSRC registers are written to. 5476 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5477 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5478 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5479 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5480 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5481 * is cleared after one clock cycle. 5482 */ 5483 #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) 5484 #define PINT_PMCFG_CFG4_MASK (0x700000U) 5485 #define PINT_PMCFG_CFG4_SHIFT (20U) 5486 /*! CFG4 - Specifies the match contribution condition for bit slice 4. 5487 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5488 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5489 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5490 * PMSRC registers are written to. 5491 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5492 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5493 * PMSRC registers are written to. 5494 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5495 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5496 * cleared when the PMCFG or the PMSRC registers are written to. 5497 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5498 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5499 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5500 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5501 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5502 * is cleared after one clock cycle. 5503 */ 5504 #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) 5505 #define PINT_PMCFG_CFG5_MASK (0x3800000U) 5506 #define PINT_PMCFG_CFG5_SHIFT (23U) 5507 /*! CFG5 - Specifies the match contribution condition for bit slice 5. 5508 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5509 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5510 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5511 * PMSRC registers are written to. 5512 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5513 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5514 * PMSRC registers are written to. 5515 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5516 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5517 * cleared when the PMCFG or the PMSRC registers are written to. 5518 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5519 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5520 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5521 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5522 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5523 * is cleared after one clock cycle. 5524 */ 5525 #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) 5526 #define PINT_PMCFG_CFG6_MASK (0x1C000000U) 5527 #define PINT_PMCFG_CFG6_SHIFT (26U) 5528 /*! CFG6 - Specifies the match contribution condition for bit slice 6. 5529 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5530 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5531 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5532 * PMSRC registers are written to. 5533 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5534 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5535 * PMSRC registers are written to. 5536 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5537 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5538 * cleared when the PMCFG or the PMSRC registers are written to. 5539 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5540 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5541 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5542 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5543 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5544 * is cleared after one clock cycle. 5545 */ 5546 #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) 5547 #define PINT_PMCFG_CFG7_MASK (0xE0000000U) 5548 #define PINT_PMCFG_CFG7_SHIFT (29U) 5549 /*! CFG7 - Specifies the match contribution condition for bit slice 7. 5550 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 5551 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 5552 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5553 * PMSRC registers are written to. 5554 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 5555 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 5556 * PMSRC registers are written to. 5557 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 5558 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 5559 * cleared when the PMCFG or the PMSRC registers are written to. 5560 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 5561 * 0b101..Low level. Match occurs when there is a low level on the specified input. 5562 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 5563 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 5564 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 5565 * is cleared after one clock cycle. 5566 */ 5567 #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) 5568 /*! @} */ 5569 5570 5571 /*! 5572 * @} 5573 */ /* end of group PINT_Register_Masks */ 5574 5575 5576 /* PINT - Peripheral instance base addresses */ 5577 /** Peripheral PINT base address */ 5578 #define PINT_BASE (0x40004000u) 5579 /** Peripheral PINT base pointer */ 5580 #define PINT ((PINT_Type *)PINT_BASE) 5581 /** Array initializer of PINT peripheral base addresses */ 5582 #define PINT_BASE_ADDRS { PINT_BASE } 5583 /** Array initializer of PINT peripheral base pointers */ 5584 #define PINT_BASE_PTRS { PINT } 5585 /** Interrupt vectors for the PINT peripheral type */ 5586 #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn } 5587 5588 /*! 5589 * @} 5590 */ /* end of group PINT_Peripheral_Access_Layer */ 5591 5592 5593 /* ---------------------------------------------------------------------------- 5594 -- RTC Peripheral Access Layer 5595 ---------------------------------------------------------------------------- */ 5596 5597 /*! 5598 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 5599 * @{ 5600 */ 5601 5602 /** RTC - Register Layout Typedef */ 5603 typedef struct { 5604 __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ 5605 __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ 5606 __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ 5607 __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ 5608 } RTC_Type; 5609 5610 /* ---------------------------------------------------------------------------- 5611 -- RTC Register Masks 5612 ---------------------------------------------------------------------------- */ 5613 5614 /*! 5615 * @addtogroup RTC_Register_Masks RTC Register Masks 5616 * @{ 5617 */ 5618 5619 /*! @name CTRL - RTC control register */ 5620 /*! @{ */ 5621 #define RTC_CTRL_SWRESET_MASK (0x1U) 5622 #define RTC_CTRL_SWRESET_SHIFT (0U) 5623 /*! SWRESET - Software reset control 5624 * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 5625 * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value 5626 * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes 5627 * to set any of the other bits within this register. Do not attempt to write to any bits of this register at 5628 * the same time that the reset bit is being cleared. 5629 */ 5630 #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) 5631 #define RTC_CTRL_ALARM1HZ_MASK (0x4U) 5632 #define RTC_CTRL_ALARM1HZ_SHIFT (2U) 5633 /*! ALARM1HZ - RTC 1 Hz timer alarm flag status. 5634 * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. 5635 * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt 5636 * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. 5637 */ 5638 #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) 5639 #define RTC_CTRL_WAKE1KHZ_MASK (0x8U) 5640 #define RTC_CTRL_WAKE1KHZ_SHIFT (3U) 5641 /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. 5642 * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. 5643 * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up 5644 * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. 5645 */ 5646 #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) 5647 #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) 5648 #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) 5649 /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. 5650 * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. 5651 * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. 5652 */ 5653 #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) 5654 #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) 5655 #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) 5656 /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. 5657 * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 5658 * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. 5659 */ 5660 #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) 5661 #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) 5662 #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) 5663 /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz 5664 * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). 5665 * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 5666 * 0b1..Enable. The 1 kHz RTC timer is enabled. 5667 */ 5668 #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) 5669 #define RTC_CTRL_RTC_EN_MASK (0x80U) 5670 #define RTC_CTRL_RTC_EN_SHIFT (7U) 5671 /*! RTC_EN - RTC enable. 5672 * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should 5673 * be 0 when writing to load a value in the RTC counter register. 5674 * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate 5675 * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the 5676 * high-resolution, 1 kHz clock, set bit 6 in this register. 5677 */ 5678 #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) 5679 #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) 5680 #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) 5681 /*! RTC_OSC_PD - RTC oscillator power-down control. 5682 * 0b0..See RTC_OSC_BYPASS 5683 * 0b1..RTC oscillator is powered-down. 5684 */ 5685 #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) 5686 #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) 5687 #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) 5688 /*! RTC_OSC_BYPASS - RTC oscillator bypass control. 5689 * 0b0..RTC oscillator is in normal crystal oscillation mode. 5690 * 0b1..RTC oscillator is bypassed. RTCXIN may be driven by an external clock. 5691 */ 5692 #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) 5693 /*! @} */ 5694 5695 /*! @name MATCH - RTC match register */ 5696 /*! @{ */ 5697 #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) 5698 #define RTC_MATCH_MATVAL_SHIFT (0U) 5699 /*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the 5700 * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. 5701 */ 5702 #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) 5703 /*! @} */ 5704 5705 /*! @name COUNT - RTC counter register */ 5706 /*! @{ */ 5707 #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) 5708 #define RTC_COUNT_VAL_SHIFT (0U) 5709 /*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial 5710 * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC 5711 * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this 5712 * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after 5713 * the RTC_EN bit is set. 5714 */ 5715 #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) 5716 /*! @} */ 5717 5718 /*! @name WAKE - High-resolution/wake-up timer control register */ 5719 /*! @{ */ 5720 #define RTC_WAKE_VAL_MASK (0xFFFFU) 5721 #define RTC_WAKE_VAL_SHIFT (0U) 5722 /*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads 5723 * a start count value into the wake-up timer and initializes a count-down sequence. Do not write 5724 * to this register while counting is in progress. 5725 */ 5726 #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) 5727 /*! @} */ 5728 5729 5730 /*! 5731 * @} 5732 */ /* end of group RTC_Register_Masks */ 5733 5734 5735 /* RTC - Peripheral instance base addresses */ 5736 /** Peripheral RTC base address */ 5737 #define RTC_BASE (0x4002C000u) 5738 /** Peripheral RTC base pointer */ 5739 #define RTC ((RTC_Type *)RTC_BASE) 5740 /** Array initializer of RTC peripheral base addresses */ 5741 #define RTC_BASE_ADDRS { RTC_BASE } 5742 /** Array initializer of RTC peripheral base pointers */ 5743 #define RTC_BASE_PTRS { RTC } 5744 /** Interrupt vectors for the RTC peripheral type */ 5745 #define RTC_IRQS { RTC_IRQn } 5746 5747 /*! 5748 * @} 5749 */ /* end of group RTC_Peripheral_Access_Layer */ 5750 5751 5752 /* ---------------------------------------------------------------------------- 5753 -- SCT Peripheral Access Layer 5754 ---------------------------------------------------------------------------- */ 5755 5756 /*! 5757 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer 5758 * @{ 5759 */ 5760 5761 /** SCT - Register Layout Typedef */ 5762 typedef struct { 5763 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ 5764 union { /* offset: 0x4 */ 5765 struct { /* offset: 0x4 */ 5766 __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ 5767 __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ 5768 } CTRL_ACCESS16BIT; 5769 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ 5770 }; 5771 union { /* offset: 0x8 */ 5772 struct { /* offset: 0x8 */ 5773 __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ 5774 __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ 5775 } LIMIT_ACCESS16BIT; 5776 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ 5777 }; 5778 union { /* offset: 0xC */ 5779 struct { /* offset: 0xC */ 5780 __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ 5781 __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ 5782 } HALT_ACCESS16BIT; 5783 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ 5784 }; 5785 union { /* offset: 0x10 */ 5786 struct { /* offset: 0x10 */ 5787 __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ 5788 __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ 5789 } STOP_ACCESS16BIT; 5790 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ 5791 }; 5792 union { /* offset: 0x14 */ 5793 struct { /* offset: 0x14 */ 5794 __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ 5795 __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ 5796 } START_ACCESS16BIT; 5797 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ 5798 }; 5799 uint8_t RESERVED_0[40]; 5800 union { /* offset: 0x40 */ 5801 struct { /* offset: 0x40 */ 5802 __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ 5803 __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ 5804 } COUNT_ACCESS16BIT; 5805 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ 5806 }; 5807 union { /* offset: 0x44 */ 5808 struct { /* offset: 0x44 */ 5809 __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ 5810 __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ 5811 } STATE_ACCESS16BIT; 5812 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ 5813 }; 5814 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ 5815 union { /* offset: 0x4C */ 5816 struct { /* offset: 0x4C */ 5817 __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ 5818 __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ 5819 } REGMODE_ACCESS16BIT; 5820 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ 5821 }; 5822 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ 5823 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ 5824 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ 5825 __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ 5826 __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ 5827 uint8_t RESERVED_1[140]; 5828 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ 5829 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ 5830 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ 5831 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ 5832 union { /* offset: 0x100 */ 5833 union { /* offset: 0x100, array step: 0x4 */ 5834 struct { /* offset: 0x100, array step: 0x4 */ 5835 __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ 5836 __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ 5837 } CAP_ACCESS16BIT[10]; 5838 __IO uint32_t CAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ 5839 }; 5840 union { /* offset: 0x100, array step: 0x4 */ 5841 struct { /* offset: 0x100, array step: 0x4 */ 5842 __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ 5843 __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ 5844 } MATCH_ACCESS16BIT[10]; 5845 __IO uint32_t MATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ 5846 }; 5847 }; 5848 uint8_t RESERVED_2[216]; 5849 union { /* offset: 0x200 */ 5850 union { /* offset: 0x200, array step: 0x4 */ 5851 struct { /* offset: 0x200, array step: 0x4 */ 5852 __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ 5853 __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ 5854 } CAPCTRL_ACCESS16BIT[10]; 5855 __IO uint32_t CAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ 5856 }; 5857 union { /* offset: 0x200, array step: 0x4 */ 5858 struct { /* offset: 0x200, array step: 0x4 */ 5859 __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ 5860 __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ 5861 } MATCHREL_ACCESS16BIT[10]; 5862 __IO uint32_t MATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ 5863 }; 5864 }; 5865 uint8_t RESERVED_3[216]; 5866 struct { /* offset: 0x300, array step: 0x8 */ 5867 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ 5868 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ 5869 } EV[10]; 5870 uint8_t RESERVED_4[432]; 5871 struct { /* offset: 0x500, array step: 0x8 */ 5872 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ 5873 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ 5874 } OUT[8]; 5875 } SCT_Type; 5876 5877 /* ---------------------------------------------------------------------------- 5878 -- SCT Register Masks 5879 ---------------------------------------------------------------------------- */ 5880 5881 /*! 5882 * @addtogroup SCT_Register_Masks SCT Register Masks 5883 * @{ 5884 */ 5885 5886 /*! @name CONFIG - SCT configuration register */ 5887 /*! @{ */ 5888 #define SCT_CONFIG_UNIFY_MASK (0x1U) 5889 #define SCT_CONFIG_UNIFY_SHIFT (0U) 5890 /*! UNIFY - SCT operation 5891 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 5892 * 0b1..The SCT operates as a unified 32-bit counter. 5893 */ 5894 #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) 5895 #define SCT_CONFIG_CLKMODE_MASK (0x6U) 5896 #define SCT_CONFIG_CLKMODE_SHIFT (1U) 5897 /*! CLKMODE - SCT clock mode 5898 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 5899 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are 5900 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The 5901 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the 5902 * high-performance, sampled-clock mode. 5903 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the 5904 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the 5905 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 5906 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL 5907 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system 5908 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than 5909 * the system clock. 5910 */ 5911 #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) 5912 #define SCT_CONFIG_CKSEL_MASK (0x78U) 5913 #define SCT_CONFIG_CKSEL_SHIFT (3U) 5914 /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent 5915 * on the CLKMODE bit selection in this register. 5916 * 0b0000..Rising edges on input 0. 5917 * 0b0001..Falling edges on input 0. 5918 * 0b0010..Rising edges on input 1. 5919 * 0b0011..Falling edges on input 1. 5920 * 0b0100..Rising edges on input 2. 5921 * 0b0101..Falling edges on input 2. 5922 * 0b0110..Rising edges on input 3. 5923 * 0b0111..Falling edges on input 3. 5924 * 0b1000..Rising edges on input 4. 5925 * 0b1001..Falling edges on input 4. 5926 * 0b1010..Rising edges on input 5. 5927 * 0b1011..Falling edges on input 5. 5928 * 0b1100..Rising edges on input 6. 5929 * 0b1101..Falling edges on input 6. 5930 * 0b1110..Rising edges on input 7. 5931 * 0b1111..Falling edges on input 7. 5932 */ 5933 #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) 5934 #define SCT_CONFIG_NORELOAD_L_MASK (0x80U) 5935 #define SCT_CONFIG_NORELOAD_L_SHIFT (7U) 5936 /*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their 5937 * respective reload registers. Setting this bit eliminates the need to write to the reload 5938 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any 5939 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 5940 */ 5941 #define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) 5942 #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) 5943 #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) 5944 /*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their 5945 * respective reload registers. Setting this bit eliminates the need to write to the reload 5946 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at 5947 * any time. This bit is not used when the UNIFY bit is set. 5948 */ 5949 #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) 5950 #define SCT_CONFIG_INSYNC_MASK (0x1E00U) 5951 #define SCT_CONFIG_INSYNC_SHIFT (9U) 5952 /*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all 5953 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to 5954 * synchronization to the SCT clock, before it is used to create an event. If an input is known to 5955 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: 5956 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input 5957 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. 5958 * It does not apply to the clock input specified in the CKSEL field. 5959 */ 5960 #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) 5961 #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) 5962 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) 5963 /*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto 5964 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this 5965 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change 5966 * the direction of count in bi-directional mode. Software can write to set or clear this bit at 5967 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 5968 */ 5969 #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) 5970 #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) 5971 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) 5972 /*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a 5973 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, 5974 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to 5975 * change the direction of count in bi-directional mode. Software can write to set or clear this bit 5976 * at any time. This bit is not used when the UNIFY bit is set. 5977 */ 5978 #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) 5979 /*! @} */ 5980 5981 /*! @name CTRLL - SCT_CTRLL register */ 5982 /*! @{ */ 5983 #define SCT_CTRLL_DOWN_L_MASK (0x1U) 5984 #define SCT_CTRLL_DOWN_L_SHIFT (0U) 5985 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 5986 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit 5987 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 5988 */ 5989 #define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) 5990 #define SCT_CTRLL_STOP_L_MASK (0x2U) 5991 #define SCT_CTRLL_STOP_L_SHIFT (1U) 5992 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 5993 * related to the counter can occur. If a designated start event occurs, this bit is cleared and 5994 * counting resumes. 5995 */ 5996 #define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) 5997 #define SCT_CTRLL_HALT_L_MASK (0x4U) 5998 #define SCT_CTRLL_HALT_L_SHIFT (2U) 5999 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A 6000 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to 6001 * remove the halt condition while keeping the SCT in the stop condition (not running) with a 6002 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, 6003 * only software can clear this bit to restore counter operation. This bit is set on reset. 6004 */ 6005 #define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) 6006 #define SCT_CTRLL_CLRCTR_L_MASK (0x8U) 6007 #define SCT_CTRLL_CLRCTR_L_SHIFT (3U) 6008 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 6009 */ 6010 #define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) 6011 #define SCT_CTRLL_BIDIR_L_MASK (0x10U) 6012 #define SCT_CTRLL_BIDIR_L_SHIFT (4U) 6013 /*! BIDIR_L - L or unified counter direction select 6014 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. 6015 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 6016 */ 6017 #define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) 6018 #define SCT_CTRLL_PRE_L_MASK (0x1FE0U) 6019 #define SCT_CTRLL_PRE_L_SHIFT (5U) 6020 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified 6021 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. 6022 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6023 */ 6024 #define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) 6025 /*! @} */ 6026 6027 /*! @name CTRLH - SCT_CTRLH register */ 6028 /*! @{ */ 6029 #define SCT_CTRLH_DOWN_H_MASK (0x1U) 6030 #define SCT_CTRLH_DOWN_H_SHIFT (0U) 6031 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 6032 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit 6033 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 6034 */ 6035 #define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) 6036 #define SCT_CTRLH_STOP_H_MASK (0x2U) 6037 #define SCT_CTRLH_STOP_H_SHIFT (1U) 6038 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to 6039 * the counter can occur. If such an event matches the mask in the Start register, this bit is 6040 * cleared and counting resumes. 6041 */ 6042 #define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) 6043 #define SCT_CTRLH_HALT_H_MASK (0x4U) 6044 #define SCT_CTRLH_HALT_H_SHIFT (2U) 6045 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 6046 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the 6047 * halt condition while keeping the SCT in the stop condition (not running) with a single write to 6048 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit 6049 * can only be cleared by software to restore counter operation. This bit is set on reset. 6050 */ 6051 #define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) 6052 #define SCT_CTRLH_CLRCTR_H_MASK (0x8U) 6053 #define SCT_CTRLH_CLRCTR_H_SHIFT (3U) 6054 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 6055 */ 6056 #define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) 6057 #define SCT_CTRLH_BIDIR_H_MASK (0x10U) 6058 #define SCT_CTRLH_BIDIR_H_SHIFT (4U) 6059 /*! BIDIR_H - Direction select 6060 * 0b0..The H counter counts up to its limit condition, then is cleared to zero. 6061 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. 6062 */ 6063 #define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) 6064 #define SCT_CTRLH_PRE_H_MASK (0x1FE0U) 6065 #define SCT_CTRLH_PRE_H_SHIFT (5U) 6066 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. 6067 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the 6068 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6069 */ 6070 #define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) 6071 /*! @} */ 6072 6073 /*! @name CTRL - SCT control register */ 6074 /*! @{ */ 6075 #define SCT_CTRL_DOWN_L_MASK (0x1U) 6076 #define SCT_CTRL_DOWN_L_SHIFT (0U) 6077 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 6078 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit 6079 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 6080 */ 6081 #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) 6082 #define SCT_CTRL_STOP_L_MASK (0x2U) 6083 #define SCT_CTRL_STOP_L_SHIFT (1U) 6084 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 6085 * related to the counter can occur. If a designated start event occurs, this bit is cleared and 6086 * counting resumes. 6087 */ 6088 #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) 6089 #define SCT_CTRL_HALT_L_MASK (0x4U) 6090 #define SCT_CTRL_HALT_L_SHIFT (2U) 6091 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A 6092 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to 6093 * remove the halt condition while keeping the SCT in the stop condition (not running) with a 6094 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, 6095 * only software can clear this bit to restore counter operation. This bit is set on reset. 6096 */ 6097 #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) 6098 #define SCT_CTRL_CLRCTR_L_MASK (0x8U) 6099 #define SCT_CTRL_CLRCTR_L_SHIFT (3U) 6100 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 6101 */ 6102 #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) 6103 #define SCT_CTRL_BIDIR_L_MASK (0x10U) 6104 #define SCT_CTRL_BIDIR_L_SHIFT (4U) 6105 /*! BIDIR_L - L or unified counter direction select 6106 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. 6107 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 6108 */ 6109 #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) 6110 #define SCT_CTRL_PRE_L_MASK (0x1FE0U) 6111 #define SCT_CTRL_PRE_L_SHIFT (5U) 6112 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified 6113 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. 6114 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6115 */ 6116 #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) 6117 #define SCT_CTRL_DOWN_H_MASK (0x10000U) 6118 #define SCT_CTRL_DOWN_H_SHIFT (16U) 6119 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 6120 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit 6121 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 6122 */ 6123 #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) 6124 #define SCT_CTRL_STOP_H_MASK (0x20000U) 6125 #define SCT_CTRL_STOP_H_SHIFT (17U) 6126 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to 6127 * the counter can occur. If such an event matches the mask in the Start register, this bit is 6128 * cleared and counting resumes. 6129 */ 6130 #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) 6131 #define SCT_CTRL_HALT_H_MASK (0x40000U) 6132 #define SCT_CTRL_HALT_H_SHIFT (18U) 6133 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 6134 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the 6135 * halt condition while keeping the SCT in the stop condition (not running) with a single write to 6136 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit 6137 * can only be cleared by software to restore counter operation. This bit is set on reset. 6138 */ 6139 #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) 6140 #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) 6141 #define SCT_CTRL_CLRCTR_H_SHIFT (19U) 6142 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 6143 */ 6144 #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) 6145 #define SCT_CTRL_BIDIR_H_MASK (0x100000U) 6146 #define SCT_CTRL_BIDIR_H_SHIFT (20U) 6147 /*! BIDIR_H - Direction select 6148 * 0b0..The H counter counts up to its limit condition, then is cleared to zero. 6149 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. 6150 */ 6151 #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) 6152 #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) 6153 #define SCT_CTRL_PRE_H_SHIFT (21U) 6154 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. 6155 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the 6156 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 6157 */ 6158 #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) 6159 /*! @} */ 6160 6161 /*! @name LIMITL - SCT_LIMITL register */ 6162 /*! @{ */ 6163 #define SCT_LIMITL_LIMITL_MASK (0xFFFFU) 6164 #define SCT_LIMITL_LIMITL_SHIFT (0U) 6165 #define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) 6166 /*! @} */ 6167 6168 /*! @name LIMITH - SCT_LIMITH register */ 6169 /*! @{ */ 6170 #define SCT_LIMITH_LIMITH_MASK (0xFFFFU) 6171 #define SCT_LIMITH_LIMITH_SHIFT (0U) 6172 #define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) 6173 /*! @} */ 6174 6175 /*! @name LIMIT - SCT limit event select register */ 6176 /*! @{ */ 6177 #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) 6178 #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) 6179 /*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter 6180 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6181 */ 6182 #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) 6183 #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) 6184 #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) 6185 /*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 6186 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6187 */ 6188 #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) 6189 /*! @} */ 6190 6191 /*! @name HALTL - SCT_HALTL register */ 6192 /*! @{ */ 6193 #define SCT_HALTL_HALTL_MASK (0xFFFFU) 6194 #define SCT_HALTL_HALTL_SHIFT (0U) 6195 #define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) 6196 /*! @} */ 6197 6198 /*! @name HALTH - SCT_HALTH register */ 6199 /*! @{ */ 6200 #define SCT_HALTH_HALTH_MASK (0xFFFFU) 6201 #define SCT_HALTH_HALTH_SHIFT (0U) 6202 #define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) 6203 /*! @} */ 6204 6205 /*! @name HALT - SCT halt event select register */ 6206 /*! @{ */ 6207 #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) 6208 #define SCT_HALT_HALTMSK_L_SHIFT (0U) 6209 /*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, 6210 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6211 */ 6212 #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) 6213 #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) 6214 #define SCT_HALT_HALTMSK_H_SHIFT (16U) 6215 /*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, 6216 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6217 */ 6218 #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) 6219 /*! @} */ 6220 6221 /*! @name STOPL - SCT_STOPL register */ 6222 /*! @{ */ 6223 #define SCT_STOPL_STOPL_MASK (0xFFFFU) 6224 #define SCT_STOPL_STOPL_SHIFT (0U) 6225 #define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) 6226 /*! @} */ 6227 6228 /*! @name STOPH - SCT_STOPH register */ 6229 /*! @{ */ 6230 #define SCT_STOPH_STOPH_MASK (0xFFFFU) 6231 #define SCT_STOPH_STOPH_SHIFT (0U) 6232 #define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) 6233 /*! @} */ 6234 6235 /*! @name STOP - SCT stop event select register */ 6236 /*! @{ */ 6237 #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) 6238 #define SCT_STOP_STOPMSK_L_SHIFT (0U) 6239 /*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, 6240 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6241 */ 6242 #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) 6243 #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) 6244 #define SCT_STOP_STOPMSK_H_SHIFT (16U) 6245 /*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, 6246 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6247 */ 6248 #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) 6249 /*! @} */ 6250 6251 /*! @name STARTL - SCT_STARTL register */ 6252 /*! @{ */ 6253 #define SCT_STARTL_STARTL_MASK (0xFFFFU) 6254 #define SCT_STARTL_STARTL_SHIFT (0U) 6255 #define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) 6256 /*! @} */ 6257 6258 /*! @name STARTH - SCT_STARTH register */ 6259 /*! @{ */ 6260 #define SCT_STARTH_STARTH_MASK (0xFFFFU) 6261 #define SCT_STARTH_STARTH_SHIFT (0U) 6262 #define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) 6263 /*! @} */ 6264 6265 /*! @name START - SCT start event select register */ 6266 /*! @{ */ 6267 #define SCT_START_STARTMSK_L_MASK (0xFFFFU) 6268 #define SCT_START_STARTMSK_L_SHIFT (0U) 6269 /*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 6270 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6271 */ 6272 #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) 6273 #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) 6274 #define SCT_START_STARTMSK_H_SHIFT (16U) 6275 /*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 6276 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 6277 */ 6278 #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) 6279 /*! @} */ 6280 6281 /*! @name COUNTL - SCT_COUNTL register */ 6282 /*! @{ */ 6283 #define SCT_COUNTL_COUNTL_MASK (0xFFFFU) 6284 #define SCT_COUNTL_COUNTL_SHIFT (0U) 6285 #define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) 6286 /*! @} */ 6287 6288 /*! @name COUNTH - SCT_COUNTH register */ 6289 /*! @{ */ 6290 #define SCT_COUNTH_COUNTH_MASK (0xFFFFU) 6291 #define SCT_COUNTH_COUNTH_SHIFT (0U) 6292 #define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) 6293 /*! @} */ 6294 6295 /*! @name COUNT - SCT counter register */ 6296 /*! @{ */ 6297 #define SCT_COUNT_CTR_L_MASK (0xFFFFU) 6298 #define SCT_COUNT_CTR_L_SHIFT (0U) 6299 /*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write 6300 * the lower 16 bits of the 32-bit unified counter. 6301 */ 6302 #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) 6303 #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) 6304 #define SCT_COUNT_CTR_H_SHIFT (16U) 6305 /*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write 6306 * the upper 16 bits of the 32-bit unified counter. 6307 */ 6308 #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) 6309 /*! @} */ 6310 6311 /*! @name STATEL - SCT_STATEL register */ 6312 /*! @{ */ 6313 #define SCT_STATEL_STATEL_MASK (0xFFFFU) 6314 #define SCT_STATEL_STATEL_SHIFT (0U) 6315 #define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) 6316 /*! @} */ 6317 6318 /*! @name STATEH - SCT_STATEH register */ 6319 /*! @{ */ 6320 #define SCT_STATEH_STATEH_MASK (0xFFFFU) 6321 #define SCT_STATEH_STATEH_SHIFT (0U) 6322 #define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) 6323 /*! @} */ 6324 6325 /*! @name STATE - SCT state register */ 6326 /*! @{ */ 6327 #define SCT_STATE_STATE_L_MASK (0x1FU) 6328 #define SCT_STATE_STATE_L_SHIFT (0U) 6329 /*! STATE_L - State variable. 6330 */ 6331 #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) 6332 #define SCT_STATE_STATE_H_MASK (0x1F0000U) 6333 #define SCT_STATE_STATE_H_SHIFT (16U) 6334 /*! STATE_H - State variable. 6335 */ 6336 #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) 6337 /*! @} */ 6338 6339 /*! @name INPUT - SCT input register */ 6340 /*! @{ */ 6341 #define SCT_INPUT_AIN0_MASK (0x1U) 6342 #define SCT_INPUT_AIN0_SHIFT (0U) 6343 /*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. 6344 */ 6345 #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) 6346 #define SCT_INPUT_AIN1_MASK (0x2U) 6347 #define SCT_INPUT_AIN1_SHIFT (1U) 6348 /*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. 6349 */ 6350 #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) 6351 #define SCT_INPUT_AIN2_MASK (0x4U) 6352 #define SCT_INPUT_AIN2_SHIFT (2U) 6353 /*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. 6354 */ 6355 #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) 6356 #define SCT_INPUT_AIN3_MASK (0x8U) 6357 #define SCT_INPUT_AIN3_SHIFT (3U) 6358 /*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. 6359 */ 6360 #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) 6361 #define SCT_INPUT_AIN4_MASK (0x10U) 6362 #define SCT_INPUT_AIN4_SHIFT (4U) 6363 /*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. 6364 */ 6365 #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) 6366 #define SCT_INPUT_AIN5_MASK (0x20U) 6367 #define SCT_INPUT_AIN5_SHIFT (5U) 6368 /*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. 6369 */ 6370 #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) 6371 #define SCT_INPUT_AIN6_MASK (0x40U) 6372 #define SCT_INPUT_AIN6_SHIFT (6U) 6373 /*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. 6374 */ 6375 #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) 6376 #define SCT_INPUT_AIN7_MASK (0x80U) 6377 #define SCT_INPUT_AIN7_SHIFT (7U) 6378 /*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. 6379 */ 6380 #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) 6381 #define SCT_INPUT_AIN8_MASK (0x100U) 6382 #define SCT_INPUT_AIN8_SHIFT (8U) 6383 /*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. 6384 */ 6385 #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) 6386 #define SCT_INPUT_AIN9_MASK (0x200U) 6387 #define SCT_INPUT_AIN9_SHIFT (9U) 6388 /*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. 6389 */ 6390 #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) 6391 #define SCT_INPUT_AIN10_MASK (0x400U) 6392 #define SCT_INPUT_AIN10_SHIFT (10U) 6393 /*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. 6394 */ 6395 #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) 6396 #define SCT_INPUT_AIN11_MASK (0x800U) 6397 #define SCT_INPUT_AIN11_SHIFT (11U) 6398 /*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. 6399 */ 6400 #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) 6401 #define SCT_INPUT_AIN12_MASK (0x1000U) 6402 #define SCT_INPUT_AIN12_SHIFT (12U) 6403 /*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. 6404 */ 6405 #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) 6406 #define SCT_INPUT_AIN13_MASK (0x2000U) 6407 #define SCT_INPUT_AIN13_SHIFT (13U) 6408 /*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. 6409 */ 6410 #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) 6411 #define SCT_INPUT_AIN14_MASK (0x4000U) 6412 #define SCT_INPUT_AIN14_SHIFT (14U) 6413 /*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. 6414 */ 6415 #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) 6416 #define SCT_INPUT_AIN15_MASK (0x8000U) 6417 #define SCT_INPUT_AIN15_SHIFT (15U) 6418 /*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. 6419 */ 6420 #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) 6421 #define SCT_INPUT_SIN0_MASK (0x10000U) 6422 #define SCT_INPUT_SIN0_SHIFT (16U) 6423 /*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. 6424 */ 6425 #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) 6426 #define SCT_INPUT_SIN1_MASK (0x20000U) 6427 #define SCT_INPUT_SIN1_SHIFT (17U) 6428 /*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. 6429 */ 6430 #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) 6431 #define SCT_INPUT_SIN2_MASK (0x40000U) 6432 #define SCT_INPUT_SIN2_SHIFT (18U) 6433 /*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. 6434 */ 6435 #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) 6436 #define SCT_INPUT_SIN3_MASK (0x80000U) 6437 #define SCT_INPUT_SIN3_SHIFT (19U) 6438 /*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. 6439 */ 6440 #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) 6441 #define SCT_INPUT_SIN4_MASK (0x100000U) 6442 #define SCT_INPUT_SIN4_SHIFT (20U) 6443 /*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. 6444 */ 6445 #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) 6446 #define SCT_INPUT_SIN5_MASK (0x200000U) 6447 #define SCT_INPUT_SIN5_SHIFT (21U) 6448 /*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. 6449 */ 6450 #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) 6451 #define SCT_INPUT_SIN6_MASK (0x400000U) 6452 #define SCT_INPUT_SIN6_SHIFT (22U) 6453 /*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. 6454 */ 6455 #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) 6456 #define SCT_INPUT_SIN7_MASK (0x800000U) 6457 #define SCT_INPUT_SIN7_SHIFT (23U) 6458 /*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. 6459 */ 6460 #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) 6461 #define SCT_INPUT_SIN8_MASK (0x1000000U) 6462 #define SCT_INPUT_SIN8_SHIFT (24U) 6463 /*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. 6464 */ 6465 #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) 6466 #define SCT_INPUT_SIN9_MASK (0x2000000U) 6467 #define SCT_INPUT_SIN9_SHIFT (25U) 6468 /*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. 6469 */ 6470 #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) 6471 #define SCT_INPUT_SIN10_MASK (0x4000000U) 6472 #define SCT_INPUT_SIN10_SHIFT (26U) 6473 /*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. 6474 */ 6475 #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) 6476 #define SCT_INPUT_SIN11_MASK (0x8000000U) 6477 #define SCT_INPUT_SIN11_SHIFT (27U) 6478 /*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. 6479 */ 6480 #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) 6481 #define SCT_INPUT_SIN12_MASK (0x10000000U) 6482 #define SCT_INPUT_SIN12_SHIFT (28U) 6483 /*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. 6484 */ 6485 #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) 6486 #define SCT_INPUT_SIN13_MASK (0x20000000U) 6487 #define SCT_INPUT_SIN13_SHIFT (29U) 6488 /*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. 6489 */ 6490 #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) 6491 #define SCT_INPUT_SIN14_MASK (0x40000000U) 6492 #define SCT_INPUT_SIN14_SHIFT (30U) 6493 /*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. 6494 */ 6495 #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) 6496 #define SCT_INPUT_SIN15_MASK (0x80000000U) 6497 #define SCT_INPUT_SIN15_SHIFT (31U) 6498 /*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. 6499 */ 6500 #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) 6501 /*! @} */ 6502 6503 /*! @name REGMODEL - SCT_REGMODEL register */ 6504 /*! @{ */ 6505 #define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) 6506 #define SCT_REGMODEL_REGMODEL_SHIFT (0U) 6507 #define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) 6508 /*! @} */ 6509 6510 /*! @name REGMODEH - SCT_REGMODEH register */ 6511 /*! @{ */ 6512 #define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) 6513 #define SCT_REGMODEH_REGMODEH_SHIFT (0U) 6514 #define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) 6515 /*! @} */ 6516 6517 /*! @name REGMODE - SCT match/capture mode register */ 6518 /*! @{ */ 6519 #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) 6520 #define SCT_REGMODE_REGMOD_L_SHIFT (0U) 6521 /*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, 6522 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as 6523 * match register. 1 = register operates as capture register. 6524 */ 6525 #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) 6526 #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) 6527 #define SCT_REGMODE_REGMOD_H_SHIFT (16U) 6528 /*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 6529 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as 6530 * match registers. 1 = register operates as capture registers. 6531 */ 6532 #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) 6533 /*! @} */ 6534 6535 /*! @name OUTPUT - SCT output register */ 6536 /*! @{ */ 6537 #define SCT_OUTPUT_OUT_MASK (0xFFFFU) 6538 #define SCT_OUTPUT_OUT_SHIFT (0U) 6539 /*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the 6540 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of 6541 * outputs in this SCT. 6542 */ 6543 #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) 6544 /*! @} */ 6545 6546 /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ 6547 /*! @{ */ 6548 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) 6549 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) 6550 /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 6551 * 0b00..Set and clear do not depend on the direction of any counter. 6552 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6553 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6554 */ 6555 #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) 6556 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) 6557 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) 6558 /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 6559 * 0b00..Set and clear do not depend on the direction of any counter. 6560 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6561 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6562 */ 6563 #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) 6564 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) 6565 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) 6566 /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 6567 * 0b00..Set and clear do not depend on the direction of any counter. 6568 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6569 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6570 */ 6571 #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) 6572 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) 6573 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) 6574 /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 6575 * 0b00..Set and clear do not depend on the direction of any counter. 6576 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6577 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6578 */ 6579 #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) 6580 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) 6581 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) 6582 /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 6583 * 0b00..Set and clear do not depend on the direction of any counter. 6584 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6585 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6586 */ 6587 #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) 6588 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) 6589 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) 6590 /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 6591 * 0b00..Set and clear do not depend on the direction of any counter. 6592 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6593 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6594 */ 6595 #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) 6596 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) 6597 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) 6598 /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 6599 * 0b00..Set and clear do not depend on the direction of any counter. 6600 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6601 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6602 */ 6603 #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) 6604 #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) 6605 #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) 6606 /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. 6607 * 0b00..Set and clear do not depend on the direction of any counter. 6608 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6609 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6610 */ 6611 #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) 6612 #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) 6613 #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) 6614 /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. 6615 * 0b00..Set and clear do not depend on the direction of any counter. 6616 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6617 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6618 */ 6619 #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) 6620 #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) 6621 #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) 6622 /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. 6623 * 0b00..Set and clear do not depend on the direction of any counter. 6624 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6625 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6626 */ 6627 #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) 6628 #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) 6629 #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) 6630 /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. 6631 * 0b00..Set and clear do not depend on the direction of any counter. 6632 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6633 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6634 */ 6635 #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) 6636 #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) 6637 #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) 6638 /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. 6639 * 0b00..Set and clear do not depend on the direction of any counter. 6640 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6641 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6642 */ 6643 #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) 6644 #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) 6645 #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) 6646 /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. 6647 * 0b00..Set and clear do not depend on the direction of any counter. 6648 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6649 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6650 */ 6651 #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) 6652 #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) 6653 #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) 6654 /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 6655 * 0b00..Set and clear do not depend on the direction of any counter. 6656 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6657 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6658 */ 6659 #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) 6660 #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) 6661 #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) 6662 /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 6663 * 0b00..Set and clear do not depend on the direction of any counter. 6664 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6665 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6666 */ 6667 #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) 6668 #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) 6669 #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) 6670 /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 6671 * 0b00..Set and clear do not depend on the direction of any counter. 6672 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 6673 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 6674 */ 6675 #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) 6676 /*! @} */ 6677 6678 /*! @name RES - SCT conflict resolution register */ 6679 /*! @{ */ 6680 #define SCT_RES_O0RES_MASK (0x3U) 6681 #define SCT_RES_O0RES_SHIFT (0U) 6682 /*! O0RES - Effect of simultaneous set and clear on output 0. 6683 * 0b00..No change. 6684 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). 6685 * 0b10..Clear output (or set based on the SETCLR0 field). 6686 * 0b11..Toggle output. 6687 */ 6688 #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) 6689 #define SCT_RES_O1RES_MASK (0xCU) 6690 #define SCT_RES_O1RES_SHIFT (2U) 6691 /*! O1RES - Effect of simultaneous set and clear on output 1. 6692 * 0b00..No change. 6693 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). 6694 * 0b10..Clear output (or set based on the SETCLR1 field). 6695 * 0b11..Toggle output. 6696 */ 6697 #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) 6698 #define SCT_RES_O2RES_MASK (0x30U) 6699 #define SCT_RES_O2RES_SHIFT (4U) 6700 /*! O2RES - Effect of simultaneous set and clear on output 2. 6701 * 0b00..No change. 6702 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). 6703 * 0b10..Clear output n (or set based on the SETCLR2 field). 6704 * 0b11..Toggle output. 6705 */ 6706 #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) 6707 #define SCT_RES_O3RES_MASK (0xC0U) 6708 #define SCT_RES_O3RES_SHIFT (6U) 6709 /*! O3RES - Effect of simultaneous set and clear on output 3. 6710 * 0b00..No change. 6711 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). 6712 * 0b10..Clear output (or set based on the SETCLR3 field). 6713 * 0b11..Toggle output. 6714 */ 6715 #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) 6716 #define SCT_RES_O4RES_MASK (0x300U) 6717 #define SCT_RES_O4RES_SHIFT (8U) 6718 /*! O4RES - Effect of simultaneous set and clear on output 4. 6719 * 0b00..No change. 6720 * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). 6721 * 0b10..Clear output (or set based on the SETCLR4 field). 6722 * 0b11..Toggle output. 6723 */ 6724 #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) 6725 #define SCT_RES_O5RES_MASK (0xC00U) 6726 #define SCT_RES_O5RES_SHIFT (10U) 6727 /*! O5RES - Effect of simultaneous set and clear on output 5. 6728 * 0b00..No change. 6729 * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). 6730 * 0b10..Clear output (or set based on the SETCLR5 field). 6731 * 0b11..Toggle output. 6732 */ 6733 #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) 6734 #define SCT_RES_O6RES_MASK (0x3000U) 6735 #define SCT_RES_O6RES_SHIFT (12U) 6736 /*! O6RES - Effect of simultaneous set and clear on output 6. 6737 * 0b00..No change. 6738 * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). 6739 * 0b10..Clear output (or set based on the SETCLR6 field). 6740 * 0b11..Toggle output. 6741 */ 6742 #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) 6743 #define SCT_RES_O7RES_MASK (0xC000U) 6744 #define SCT_RES_O7RES_SHIFT (14U) 6745 /*! O7RES - Effect of simultaneous set and clear on output 7. 6746 * 0b00..No change. 6747 * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). 6748 * 0b10..Clear output n (or set based on the SETCLR7 field). 6749 * 0b11..Toggle output. 6750 */ 6751 #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) 6752 #define SCT_RES_O8RES_MASK (0x30000U) 6753 #define SCT_RES_O8RES_SHIFT (16U) 6754 /*! O8RES - Effect of simultaneous set and clear on output 8. 6755 * 0b00..No change. 6756 * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). 6757 * 0b10..Clear output (or set based on the SETCLR8 field). 6758 * 0b11..Toggle output. 6759 */ 6760 #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) 6761 #define SCT_RES_O9RES_MASK (0xC0000U) 6762 #define SCT_RES_O9RES_SHIFT (18U) 6763 /*! O9RES - Effect of simultaneous set and clear on output 9. 6764 * 0b00..No change. 6765 * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). 6766 * 0b10..Clear output (or set based on the SETCLR9 field). 6767 * 0b11..Toggle output. 6768 */ 6769 #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) 6770 #define SCT_RES_O10RES_MASK (0x300000U) 6771 #define SCT_RES_O10RES_SHIFT (20U) 6772 /*! O10RES - Effect of simultaneous set and clear on output 10. 6773 * 0b00..No change. 6774 * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). 6775 * 0b10..Clear output (or set based on the SETCLR10 field). 6776 * 0b11..Toggle output. 6777 */ 6778 #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) 6779 #define SCT_RES_O11RES_MASK (0xC00000U) 6780 #define SCT_RES_O11RES_SHIFT (22U) 6781 /*! O11RES - Effect of simultaneous set and clear on output 11. 6782 * 0b00..No change. 6783 * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). 6784 * 0b10..Clear output (or set based on the SETCLR11 field). 6785 * 0b11..Toggle output. 6786 */ 6787 #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) 6788 #define SCT_RES_O12RES_MASK (0x3000000U) 6789 #define SCT_RES_O12RES_SHIFT (24U) 6790 /*! O12RES - Effect of simultaneous set and clear on output 12. 6791 * 0b00..No change. 6792 * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). 6793 * 0b10..Clear output (or set based on the SETCLR12 field). 6794 * 0b11..Toggle output. 6795 */ 6796 #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) 6797 #define SCT_RES_O13RES_MASK (0xC000000U) 6798 #define SCT_RES_O13RES_SHIFT (26U) 6799 /*! O13RES - Effect of simultaneous set and clear on output 13. 6800 * 0b00..No change. 6801 * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). 6802 * 0b10..Clear output (or set based on the SETCLR13 field). 6803 * 0b11..Toggle output. 6804 */ 6805 #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) 6806 #define SCT_RES_O14RES_MASK (0x30000000U) 6807 #define SCT_RES_O14RES_SHIFT (28U) 6808 /*! O14RES - Effect of simultaneous set and clear on output 14. 6809 * 0b00..No change. 6810 * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). 6811 * 0b10..Clear output (or set based on the SETCLR14 field). 6812 * 0b11..Toggle output. 6813 */ 6814 #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) 6815 #define SCT_RES_O15RES_MASK (0xC0000000U) 6816 #define SCT_RES_O15RES_SHIFT (30U) 6817 /*! O15RES - Effect of simultaneous set and clear on output 15. 6818 * 0b00..No change. 6819 * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). 6820 * 0b10..Clear output (or set based on the SETCLR15 field). 6821 * 0b11..Toggle output. 6822 */ 6823 #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) 6824 /*! @} */ 6825 6826 /*! @name DMAREQ0 - SCT DMA request 0 register */ 6827 /*! @{ */ 6828 #define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) 6829 #define SCT_DMAREQ0_DEV_0_SHIFT (0U) 6830 /*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, 6831 * etc.). The number of bits = number of events in this SCT. 6832 */ 6833 #define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) 6834 #define SCT_DMAREQ0_DRL0_MASK (0x40000000U) 6835 #define SCT_DMAREQ0_DRL0_SHIFT (30U) 6836 /*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 6837 */ 6838 #define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) 6839 #define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) 6840 #define SCT_DMAREQ0_DRQ0_SHIFT (31U) 6841 /*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA 6842 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will 6843 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA 6844 * setup. 6845 */ 6846 #define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) 6847 /*! @} */ 6848 6849 /*! @name DMAREQ1 - SCT DMA request 1 register */ 6850 /*! @{ */ 6851 #define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) 6852 #define SCT_DMAREQ1_DEV_1_SHIFT (0U) 6853 /*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, 6854 * etc.). The number of bits = number of events in this SCT. 6855 */ 6856 #define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) 6857 #define SCT_DMAREQ1_DRL1_MASK (0x40000000U) 6858 #define SCT_DMAREQ1_DRL1_SHIFT (30U) 6859 /*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 6860 */ 6861 #define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) 6862 #define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) 6863 #define SCT_DMAREQ1_DRQ1_SHIFT (31U) 6864 /*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA 6865 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will 6866 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA 6867 * setup. 6868 */ 6869 #define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) 6870 /*! @} */ 6871 6872 /*! @name EVEN - SCT event interrupt enable register */ 6873 /*! @{ */ 6874 #define SCT_EVEN_IEN_MASK (0xFFFFU) 6875 #define SCT_EVEN_IEN_SHIFT (0U) 6876 /*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are 6877 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in 6878 * this SCT. 6879 */ 6880 #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) 6881 /*! @} */ 6882 6883 /*! @name EVFLAG - SCT event flag register */ 6884 /*! @{ */ 6885 #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) 6886 #define SCT_EVFLAG_FLAG_SHIFT (0U) 6887 /*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit 6888 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6889 */ 6890 #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) 6891 /*! @} */ 6892 6893 /*! @name CONEN - SCT conflict interrupt enable register */ 6894 /*! @{ */ 6895 #define SCT_CONEN_NCEN_MASK (0xFFFFU) 6896 #define SCT_CONEN_NCEN_SHIFT (0U) 6897 /*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag 6898 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of 6899 * outputs in this SCT. 6900 */ 6901 #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) 6902 /*! @} */ 6903 6904 /*! @name CONFLAG - SCT conflict flag register */ 6905 /*! @{ */ 6906 #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) 6907 #define SCT_CONFLAG_NCFLAG_SHIFT (0U) 6908 /*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was 6909 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = 6910 * number of outputs in this SCT. 6911 */ 6912 #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) 6913 #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) 6914 #define SCT_CONFLAG_BUSERRL_SHIFT (30U) 6915 /*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE 6916 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write 6917 * to certain L and H registers can be half successful and half unsuccessful. 6918 */ 6919 #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) 6920 #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) 6921 #define SCT_CONFLAG_BUSERRH_SHIFT (31U) 6922 /*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or 6923 * the Output register when the H counter was not halted. 6924 */ 6925 #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) 6926 /*! @} */ 6927 6928 /*! @name CAPL - SCT_CAPL register */ 6929 /*! @{ */ 6930 #define SCT_CAPL_CAPL_MASK (0xFFFFU) 6931 #define SCT_CAPL_CAPL_SHIFT (0U) 6932 #define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) 6933 /*! @} */ 6934 6935 /* The count of SCT_CAPL */ 6936 #define SCT_CAPL_COUNT (10U) 6937 6938 /*! @name CAPH - SCT_CAPH register */ 6939 /*! @{ */ 6940 #define SCT_CAPH_CAPH_MASK (0xFFFFU) 6941 #define SCT_CAPH_CAPH_SHIFT (0U) 6942 #define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) 6943 /*! @} */ 6944 6945 /* The count of SCT_CAPH */ 6946 #define SCT_CAPH_COUNT (10U) 6947 6948 /*! @name CAP - SCT capture register of capture channel */ 6949 /*! @{ */ 6950 #define SCT_CAP_CAPn_L_MASK (0xFFFFU) 6951 #define SCT_CAP_CAPn_L_SHIFT (0U) 6952 /*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. 6953 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last 6954 * captured. 6955 */ 6956 #define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) 6957 #define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) 6958 #define SCT_CAP_CAPn_H_SHIFT (16U) 6959 /*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. 6960 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last 6961 * captured. 6962 */ 6963 #define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) 6964 /*! @} */ 6965 6966 /* The count of SCT_CAP */ 6967 #define SCT_CAP_COUNT (10U) 6968 6969 /*! @name MATCHL - SCT_MATCHL register */ 6970 /*! @{ */ 6971 #define SCT_MATCHL_MATCHL_MASK (0xFFFFU) 6972 #define SCT_MATCHL_MATCHL_SHIFT (0U) 6973 #define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) 6974 /*! @} */ 6975 6976 /* The count of SCT_MATCHL */ 6977 #define SCT_MATCHL_COUNT (10U) 6978 6979 /*! @name MATCHH - SCT_MATCHH register */ 6980 /*! @{ */ 6981 #define SCT_MATCHH_MATCHH_MASK (0xFFFFU) 6982 #define SCT_MATCHH_MATCHH_SHIFT (0U) 6983 #define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) 6984 /*! @} */ 6985 6986 /* The count of SCT_MATCHH */ 6987 #define SCT_MATCHH_COUNT (10U) 6988 6989 /*! @name MATCH - SCT match value register of match channels */ 6990 /*! @{ */ 6991 #define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) 6992 #define SCT_MATCH_MATCHn_L_SHIFT (0U) 6993 /*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When 6994 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified 6995 * counter. 6996 */ 6997 #define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) 6998 #define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) 6999 #define SCT_MATCH_MATCHn_H_SHIFT (16U) 7000 /*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When 7001 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified 7002 * counter. 7003 */ 7004 #define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) 7005 /*! @} */ 7006 7007 /* The count of SCT_MATCH */ 7008 #define SCT_MATCH_COUNT (10U) 7009 7010 /*! @name CAPCTRLL - SCT_CAPCTRLL register */ 7011 /*! @{ */ 7012 #define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) 7013 #define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) 7014 #define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) 7015 /*! @} */ 7016 7017 /* The count of SCT_CAPCTRLL */ 7018 #define SCT_CAPCTRLL_COUNT (10U) 7019 7020 /*! @name CAPCTRLH - SCT_CAPCTRLH register */ 7021 /*! @{ */ 7022 #define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) 7023 #define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) 7024 #define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) 7025 /*! @} */ 7026 7027 /* The count of SCT_CAPCTRLH */ 7028 #define SCT_CAPCTRLH_COUNT (10U) 7029 7030 /*! @name CAPCTRL - SCT capture control register */ 7031 /*! @{ */ 7032 #define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) 7033 #define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) 7034 /*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) 7035 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of 7036 * match/captures in this SCT. 7037 */ 7038 #define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) 7039 #define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) 7040 #define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) 7041 /*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 7042 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 7043 */ 7044 #define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) 7045 /*! @} */ 7046 7047 /* The count of SCT_CAPCTRL */ 7048 #define SCT_CAPCTRL_COUNT (10U) 7049 7050 /*! @name MATCHRELL - SCT_MATCHRELL register */ 7051 /*! @{ */ 7052 #define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) 7053 #define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) 7054 #define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) 7055 /*! @} */ 7056 7057 /* The count of SCT_MATCHRELL */ 7058 #define SCT_MATCHRELL_COUNT (10U) 7059 7060 /*! @name MATCHRELH - SCT_MATCHRELH register */ 7061 /*! @{ */ 7062 #define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) 7063 #define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) 7064 #define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) 7065 /*! @} */ 7066 7067 /* The count of SCT_MATCHRELH */ 7068 #define SCT_MATCHRELH_COUNT (10U) 7069 7070 /*! @name MATCHREL - SCT match reload value register */ 7071 /*! @{ */ 7072 #define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) 7073 #define SCT_MATCHREL_RELOADn_L_SHIFT (0U) 7074 /*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. 7075 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn 7076 * register. 7077 */ 7078 #define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) 7079 #define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) 7080 #define SCT_MATCHREL_RELOADn_H_SHIFT (16U) 7081 /*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When 7082 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn 7083 * register. 7084 */ 7085 #define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) 7086 /*! @} */ 7087 7088 /* The count of SCT_MATCHREL */ 7089 #define SCT_MATCHREL_COUNT (10U) 7090 7091 /*! @name EV_STATE - SCT event state register 0 */ 7092 /*! @{ */ 7093 #define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) 7094 #define SCT_EV_STATE_STATEMSKn_SHIFT (0U) 7095 /*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT 7096 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of 7097 * bits = number of states in this SCT. 7098 */ 7099 #define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) 7100 /*! @} */ 7101 7102 /* The count of SCT_EV_STATE */ 7103 #define SCT_EV_STATE_COUNT (10U) 7104 7105 /*! @name EV_CTRL - SCT event control register 0 */ 7106 /*! @{ */ 7107 #define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) 7108 #define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) 7109 /*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur 7110 * only when the counter selected by the HEVENT bit is running. 7111 */ 7112 #define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) 7113 #define SCT_EV_CTRL_HEVENT_MASK (0x10U) 7114 #define SCT_EV_CTRL_HEVENT_SHIFT (4U) 7115 /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. 7116 * 0b0..Selects the L state and the L match register selected by MATCHSEL. 7117 * 0b1..Selects the H state and the H match register selected by MATCHSEL. 7118 */ 7119 #define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) 7120 #define SCT_EV_CTRL_OUTSEL_MASK (0x20U) 7121 #define SCT_EV_CTRL_OUTSEL_SHIFT (5U) 7122 /*! OUTSEL - Input/output select 7123 * 0b0..Selects the inputs selected by IOSEL. 7124 * 0b1..Selects the outputs selected by IOSEL. 7125 */ 7126 #define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) 7127 #define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) 7128 #define SCT_EV_CTRL_IOSEL_SHIFT (6U) 7129 /*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not 7130 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit 7131 * ingredient of every event. 7132 */ 7133 #define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) 7134 #define SCT_EV_CTRL_IOCOND_MASK (0xC00U) 7135 #define SCT_EV_CTRL_IOCOND_SHIFT (10U) 7136 /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the 7137 * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state 7138 * detection, an input must have a minimum pulse width of at least one SCT clock period . 7139 * 0b00..LOW 7140 * 0b01..Rise 7141 * 0b10..Fall 7142 * 0b11..HIGH 7143 */ 7144 #define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) 7145 #define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) 7146 #define SCT_EV_CTRL_COMBMODE_SHIFT (12U) 7147 /*! COMBMODE - Selects how the specified match and I/O condition are used and combined. 7148 * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. 7149 * 0b01..MATCH. Uses the specified match only. 7150 * 0b10..IO. Uses the specified I/O condition only. 7151 * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. 7152 */ 7153 #define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) 7154 #define SCT_EV_CTRL_STATELD_MASK (0x4000U) 7155 #define SCT_EV_CTRL_STATELD_SHIFT (14U) 7156 /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this 7157 * event is the highest-numbered event occurring for that state. 7158 * 0b0..STATEV value is added into STATE (the carry-out is ignored). 7159 * 0b1..STATEV value is loaded into STATE. 7160 */ 7161 #define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) 7162 #define SCT_EV_CTRL_STATEV_MASK (0xF8000U) 7163 #define SCT_EV_CTRL_STATEV_SHIFT (15U) 7164 /*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on 7165 * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and 7166 * STATEV are both zero, there is no change to the STATE value. 7167 */ 7168 #define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) 7169 #define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) 7170 #define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) 7171 /*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the 7172 * triggering of this event, then a match is considered to be active whenever the counter value is 7173 * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR 7174 * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active 7175 * during the cycle when the counter is equal to the match value. 7176 */ 7177 #define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) 7178 #define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) 7179 #define SCT_EV_CTRL_DIRECTION_SHIFT (21U) 7180 /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters 7181 * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 7182 * 0b00..Direction independent. This event is triggered regardless of the count direction. 7183 * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. 7184 * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. 7185 */ 7186 #define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) 7187 /*! @} */ 7188 7189 /* The count of SCT_EV_CTRL */ 7190 #define SCT_EV_CTRL_COUNT (10U) 7191 7192 /*! @name OUT_SET - SCT output 0 set register */ 7193 /*! @{ */ 7194 #define SCT_OUT_SET_SET_MASK (0xFFFFU) 7195 #define SCT_OUT_SET_SET_SHIFT (0U) 7196 /*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 7197 * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the 7198 * counter is used in bi-directional mode, it is possible to reverse the action specified by the 7199 * output set and clear registers when counting down, See the OUTPUTCTRL register. 7200 */ 7201 #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) 7202 /*! @} */ 7203 7204 /* The count of SCT_OUT_SET */ 7205 #define SCT_OUT_SET_COUNT (8U) 7206 7207 /*! @name OUT_CLR - SCT output 0 clear register */ 7208 /*! @{ */ 7209 #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) 7210 #define SCT_OUT_CLR_CLR_SHIFT (0U) 7211 /*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 7212 * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the 7213 * counter is used in bi-directional mode, it is possible to reverse the action specified by the 7214 * output set and clear registers when counting down, See the OUTPUTCTRL register. 7215 */ 7216 #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) 7217 /*! @} */ 7218 7219 /* The count of SCT_OUT_CLR */ 7220 #define SCT_OUT_CLR_COUNT (8U) 7221 7222 7223 /*! 7224 * @} 7225 */ /* end of group SCT_Register_Masks */ 7226 7227 7228 /* SCT - Peripheral instance base addresses */ 7229 /** Peripheral SCT0 base address */ 7230 #define SCT0_BASE (0x40085000u) 7231 /** Peripheral SCT0 base pointer */ 7232 #define SCT0 ((SCT_Type *)SCT0_BASE) 7233 /** Array initializer of SCT peripheral base addresses */ 7234 #define SCT_BASE_ADDRS { SCT0_BASE } 7235 /** Array initializer of SCT peripheral base pointers */ 7236 #define SCT_BASE_PTRS { SCT0 } 7237 /** Interrupt vectors for the SCT peripheral type */ 7238 #define SCT_IRQS { SCT0_IRQn } 7239 7240 /*! 7241 * @} 7242 */ /* end of group SCT_Peripheral_Access_Layer */ 7243 7244 7245 /* ---------------------------------------------------------------------------- 7246 -- SPI Peripheral Access Layer 7247 ---------------------------------------------------------------------------- */ 7248 7249 /*! 7250 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 7251 * @{ 7252 */ 7253 7254 /** SPI - Register Layout Typedef */ 7255 typedef struct { 7256 uint8_t RESERVED_0[1024]; 7257 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ 7258 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ 7259 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ 7260 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ 7261 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ 7262 uint8_t RESERVED_1[16]; 7263 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ 7264 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ 7265 uint8_t RESERVED_2[2516]; 7266 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ 7267 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ 7268 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ 7269 uint8_t RESERVED_3[4]; 7270 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ 7271 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ 7272 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ 7273 uint8_t RESERVED_4[4]; 7274 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ 7275 uint8_t RESERVED_5[12]; 7276 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ 7277 uint8_t RESERVED_6[12]; 7278 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ 7279 } SPI_Type; 7280 7281 /* ---------------------------------------------------------------------------- 7282 -- SPI Register Masks 7283 ---------------------------------------------------------------------------- */ 7284 7285 /*! 7286 * @addtogroup SPI_Register_Masks SPI Register Masks 7287 * @{ 7288 */ 7289 7290 /*! @name CFG - SPI Configuration register */ 7291 /*! @{ */ 7292 #define SPI_CFG_ENABLE_MASK (0x1U) 7293 #define SPI_CFG_ENABLE_SHIFT (0U) 7294 /*! ENABLE - SPI enable. 7295 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. 7296 * 0b1..Enabled. The SPI is enabled for operation. 7297 */ 7298 #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) 7299 #define SPI_CFG_MASTER_MASK (0x4U) 7300 #define SPI_CFG_MASTER_SHIFT (2U) 7301 /*! MASTER - Master mode select. 7302 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 7303 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 7304 */ 7305 #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) 7306 #define SPI_CFG_LSBF_MASK (0x8U) 7307 #define SPI_CFG_LSBF_SHIFT (3U) 7308 /*! LSBF - LSB First mode enable. 7309 * 0b0..Standard. Data is transmitted and received in standard MSB first order. 7310 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). 7311 */ 7312 #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) 7313 #define SPI_CFG_CPHA_MASK (0x10U) 7314 #define SPI_CFG_CPHA_SHIFT (4U) 7315 /*! CPHA - Clock Phase select. 7316 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock 7317 * changes away from the rest state). Data is changed on the following edge. 7318 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock 7319 * changes away from the rest state). Data is captured on the following edge. 7320 */ 7321 #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) 7322 #define SPI_CFG_CPOL_MASK (0x20U) 7323 #define SPI_CFG_CPOL_SHIFT (5U) 7324 /*! CPOL - Clock Polarity select. 7325 * 0b0..Low. The rest state of the clock (between transfers) is low. 7326 * 0b1..High. The rest state of the clock (between transfers) is high. 7327 */ 7328 #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) 7329 #define SPI_CFG_LOOP_MASK (0x80U) 7330 #define SPI_CFG_LOOP_SHIFT (7U) 7331 /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit 7332 * and receive data connected together to allow simple software testing. 7333 * 0b0..Disabled. 7334 * 0b1..Enabled. 7335 */ 7336 #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) 7337 #define SPI_CFG_SPOL0_MASK (0x100U) 7338 #define SPI_CFG_SPOL0_SHIFT (8U) 7339 /*! SPOL0 - SSEL0 Polarity select. 7340 * 0b0..Low. The SSEL0 pin is active low. 7341 * 0b1..High. The SSEL0 pin is active high. 7342 */ 7343 #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) 7344 #define SPI_CFG_SPOL1_MASK (0x200U) 7345 #define SPI_CFG_SPOL1_SHIFT (9U) 7346 /*! SPOL1 - SSEL1 Polarity select. 7347 * 0b0..Low. The SSEL1 pin is active low. 7348 * 0b1..High. The SSEL1 pin is active high. 7349 */ 7350 #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) 7351 #define SPI_CFG_SPOL2_MASK (0x400U) 7352 #define SPI_CFG_SPOL2_SHIFT (10U) 7353 /*! SPOL2 - SSEL2 Polarity select. 7354 * 0b0..Low. The SSEL2 pin is active low. 7355 * 0b1..High. The SSEL2 pin is active high. 7356 */ 7357 #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) 7358 #define SPI_CFG_SPOL3_MASK (0x800U) 7359 #define SPI_CFG_SPOL3_SHIFT (11U) 7360 /*! SPOL3 - SSEL3 Polarity select. 7361 * 0b0..Low. The SSEL3 pin is active low. 7362 * 0b1..High. The SSEL3 pin is active high. 7363 */ 7364 #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) 7365 /*! @} */ 7366 7367 /*! @name DLY - SPI Delay register */ 7368 /*! @{ */ 7369 #define SPI_DLY_PRE_DELAY_MASK (0xFU) 7370 #define SPI_DLY_PRE_DELAY_SHIFT (0U) 7371 /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data 7372 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This 7373 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI 7374 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are 7375 * inserted. 7376 */ 7377 #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) 7378 #define SPI_DLY_POST_DELAY_MASK (0xF0U) 7379 #define SPI_DLY_POST_DELAY_SHIFT (4U) 7380 /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL 7381 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock 7382 * times are inserted. 0xF = 15 SPI clock times are inserted. 7383 */ 7384 #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) 7385 #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) 7386 #define SPI_DLY_FRAME_DELAY_SHIFT (8U) 7387 /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current 7388 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 7389 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock 7390 * times are inserted. 7391 */ 7392 #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) 7393 #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) 7394 #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) 7395 /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between 7396 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 7397 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that 7398 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 7399 * SPI clock times. 7400 */ 7401 #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) 7402 /*! @} */ 7403 7404 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ 7405 /*! @{ */ 7406 #define SPI_STAT_SSA_MASK (0x10U) 7407 #define SPI_STAT_SSA_SHIFT (4U) 7408 /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from 7409 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI 7410 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a 7411 * slave mode access begins. This flag is cleared by software. 7412 */ 7413 #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) 7414 #define SPI_STAT_SSD_MASK (0x20U) 7415 #define SPI_STAT_SSD_SHIFT (5U) 7416 /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to 7417 * deasserted, in both master and slave modes. This allows determining when the SPI 7418 * transmit/receive functions become idle. This flag is cleared by software. 7419 */ 7420 #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) 7421 #define SPI_STAT_STALLED_MASK (0x40U) 7422 #define SPI_STAT_STALLED_SHIFT (6U) 7423 /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. 7424 */ 7425 #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) 7426 #define SPI_STAT_ENDTRANSFER_MASK (0x80U) 7427 #define SPI_STAT_ENDTRANSFER_SHIFT (7U) 7428 /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current 7429 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag 7430 * had been set prior to the last transmission. This capability is included to support cases where 7431 * it is not known when transmit data is written that it will be the end of a transfer. The bit 7432 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end 7433 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7434 */ 7435 #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) 7436 #define SPI_STAT_MSTIDLE_MASK (0x100U) 7437 #define SPI_STAT_MSTIDLE_SHIFT (8U) 7438 /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. 7439 * This means that the transmit holding register is empty and the transmitter is not in the 7440 * process of sending data. 7441 */ 7442 #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) 7443 /*! @} */ 7444 7445 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 7446 /*! @{ */ 7447 #define SPI_INTENSET_SSAEN_MASK (0x10U) 7448 #define SPI_INTENSET_SSAEN_SHIFT (4U) 7449 /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. 7450 * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 7451 * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 7452 */ 7453 #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) 7454 #define SPI_INTENSET_SSDEN_MASK (0x20U) 7455 #define SPI_INTENSET_SSDEN_SHIFT (5U) 7456 /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. 7457 * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. 7458 * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. 7459 */ 7460 #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) 7461 #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) 7462 #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) 7463 /*! MSTIDLEEN - Master idle interrupt enable. 7464 * 0b0..No interrupt will be generated when the SPI master function is idle. 7465 * 0b1..An interrupt will be generated when the SPI master function is fully idle. 7466 */ 7467 #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) 7468 /*! @} */ 7469 7470 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ 7471 /*! @{ */ 7472 #define SPI_INTENCLR_SSAEN_MASK (0x10U) 7473 #define SPI_INTENCLR_SSAEN_SHIFT (4U) 7474 /*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. 7475 */ 7476 #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) 7477 #define SPI_INTENCLR_SSDEN_MASK (0x20U) 7478 #define SPI_INTENCLR_SSDEN_SHIFT (5U) 7479 /*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. 7480 */ 7481 #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) 7482 #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) 7483 #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) 7484 /*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. 7485 */ 7486 #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) 7487 /*! @} */ 7488 7489 /*! @name DIV - SPI clock Divider */ 7490 /*! @{ */ 7491 #define SPI_DIV_DIVVAL_MASK (0xFFFFU) 7492 #define SPI_DIV_DIVVAL_SHIFT (0U) 7493 /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the 7494 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, 7495 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results 7496 * in FCLK/65536. 7497 */ 7498 #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) 7499 /*! @} */ 7500 7501 /*! @name INTSTAT - SPI Interrupt Status */ 7502 /*! @{ */ 7503 #define SPI_INTSTAT_SSA_MASK (0x10U) 7504 #define SPI_INTSTAT_SSA_SHIFT (4U) 7505 /*! SSA - Slave Select Assert. 7506 */ 7507 #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) 7508 #define SPI_INTSTAT_SSD_MASK (0x20U) 7509 #define SPI_INTSTAT_SSD_SHIFT (5U) 7510 /*! SSD - Slave Select Deassert. 7511 */ 7512 #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) 7513 #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) 7514 #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) 7515 /*! MSTIDLE - Master Idle status flag. 7516 */ 7517 #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) 7518 /*! @} */ 7519 7520 /*! @name FIFOCFG - FIFO configuration and enable register. */ 7521 /*! @{ */ 7522 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) 7523 #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) 7524 /*! ENABLETX - Enable the transmit FIFO. 7525 * 0b0..The transmit FIFO is not enabled. 7526 * 0b1..The transmit FIFO is enabled. 7527 */ 7528 #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) 7529 #define SPI_FIFOCFG_ENABLERX_MASK (0x2U) 7530 #define SPI_FIFOCFG_ENABLERX_SHIFT (1U) 7531 /*! ENABLERX - Enable the receive FIFO. 7532 * 0b0..The receive FIFO is not enabled. 7533 * 0b1..The receive FIFO is enabled. 7534 */ 7535 #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) 7536 #define SPI_FIFOCFG_SIZE_MASK (0x30U) 7537 #define SPI_FIFOCFG_SIZE_SHIFT (4U) 7538 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 7539 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 7540 */ 7541 #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) 7542 #define SPI_FIFOCFG_DMATX_MASK (0x1000U) 7543 #define SPI_FIFOCFG_DMATX_SHIFT (12U) 7544 /*! DMATX - DMA configuration for transmit. 7545 * 0b0..DMA is not used for the transmit function. 7546 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 7547 */ 7548 #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) 7549 #define SPI_FIFOCFG_DMARX_MASK (0x2000U) 7550 #define SPI_FIFOCFG_DMARX_SHIFT (13U) 7551 /*! DMARX - DMA configuration for receive. 7552 * 0b0..DMA is not used for the receive function. 7553 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 7554 */ 7555 #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) 7556 #define SPI_FIFOCFG_WAKETX_MASK (0x4000U) 7557 #define SPI_FIFOCFG_WAKETX_SHIFT (14U) 7558 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power 7559 * modes (up to power-down, as long as the peripheral function works in that power mode) without 7560 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 7561 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 7562 * Wake-up control register. 7563 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 7564 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in 7565 * FIFOTRIG, even when the TXLVL interrupt is not enabled. 7566 */ 7567 #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) 7568 #define SPI_FIFOCFG_WAKERX_MASK (0x8000U) 7569 #define SPI_FIFOCFG_WAKERX_SHIFT (15U) 7570 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power 7571 * modes (up to power-down, as long as the peripheral function works in that power mode) without 7572 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 7573 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 7574 * Wake-up control register. 7575 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 7576 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in 7577 * FIFOTRIG, even when the RXLVL interrupt is not enabled. 7578 */ 7579 #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) 7580 #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) 7581 #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) 7582 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 7583 */ 7584 #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) 7585 #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) 7586 #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) 7587 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 7588 */ 7589 #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) 7590 /*! @} */ 7591 7592 /*! @name FIFOSTAT - FIFO status register. */ 7593 /*! @{ */ 7594 #define SPI_FIFOSTAT_TXERR_MASK (0x1U) 7595 #define SPI_FIFOSTAT_TXERR_SHIFT (0U) 7596 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow 7597 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is 7598 * needed. Cleared by writing a 1 to this bit. 7599 */ 7600 #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) 7601 #define SPI_FIFOSTAT_RXERR_MASK (0x2U) 7602 #define SPI_FIFOSTAT_RXERR_SHIFT (1U) 7603 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA 7604 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 7605 */ 7606 #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) 7607 #define SPI_FIFOSTAT_PERINT_MASK (0x8U) 7608 #define SPI_FIFOSTAT_PERINT_SHIFT (3U) 7609 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted 7610 * an interrupt. The details can be found by reading the peripheral's STAT register. 7611 */ 7612 #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) 7613 #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) 7614 #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) 7615 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 7616 */ 7617 #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) 7618 #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) 7619 #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) 7620 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be 7621 * written. When 0, the transmit FIFO is full and another write would cause it to overflow. 7622 */ 7623 #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) 7624 #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) 7625 #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) 7626 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 7627 */ 7628 #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) 7629 #define SPI_FIFOSTAT_RXFULL_MASK (0x80U) 7630 #define SPI_FIFOSTAT_RXFULL_SHIFT (7U) 7631 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to 7632 * prevent the peripheral from causing an overflow. 7633 */ 7634 #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) 7635 #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) 7636 #define SPI_FIFOSTAT_TXLVL_SHIFT (8U) 7637 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY 7638 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at 7639 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 7640 * 0. 7641 */ 7642 #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) 7643 #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) 7644 #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) 7645 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and 7646 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the 7647 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 7648 * 1. 7649 */ 7650 #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) 7651 /*! @} */ 7652 7653 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ 7654 /*! @{ */ 7655 #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) 7656 #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) 7657 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled 7658 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 7659 * 0b0..Transmit FIFO level does not generate a FIFO level trigger. 7660 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 7661 */ 7662 #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) 7663 #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) 7664 #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) 7665 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled 7666 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 7667 * 0b0..Receive FIFO level does not generate a FIFO level trigger. 7668 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 7669 */ 7670 #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) 7671 #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) 7672 #define SPI_FIFOTRIG_TXLVL_SHIFT (8U) 7673 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled 7674 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to 7675 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO 7676 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX 7677 * FIFO level decreases to 15 entries (is no longer full). 7678 */ 7679 #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) 7680 #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) 7681 #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) 7682 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data 7683 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level 7684 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See 7685 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no 7686 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX 7687 * FIFO has received 16 entries (has become full). 7688 */ 7689 #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) 7690 /*! @} */ 7691 7692 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ 7693 /*! @{ */ 7694 #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) 7695 #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) 7696 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 7697 * 0b0..No interrupt will be generated for a transmit error. 7698 * 0b1..An interrupt will be generated when a transmit error occurs. 7699 */ 7700 #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) 7701 #define SPI_FIFOINTENSET_RXERR_MASK (0x2U) 7702 #define SPI_FIFOINTENSET_RXERR_SHIFT (1U) 7703 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 7704 * 0b0..No interrupt will be generated for a receive error. 7705 * 0b1..An interrupt will be generated when a receive error occurs. 7706 */ 7707 #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) 7708 #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) 7709 #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) 7710 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level 7711 * specified by the TXLVL field in the FIFOTRIG register. 7712 * 0b0..No interrupt will be generated based on the TX FIFO level. 7713 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases 7714 * to the level specified by TXLVL in the FIFOTRIG register. 7715 */ 7716 #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) 7717 #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) 7718 #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) 7719 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level 7720 * specified by the TXLVL field in the FIFOTRIG register. 7721 * 0b0..No interrupt will be generated based on the RX FIFO level. 7722 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level 7723 * increases to the level specified by RXLVL in the FIFOTRIG register. 7724 */ 7725 #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) 7726 /*! @} */ 7727 7728 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ 7729 /*! @{ */ 7730 #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) 7731 #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) 7732 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 7733 */ 7734 #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) 7735 #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) 7736 #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) 7737 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 7738 */ 7739 #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) 7740 #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) 7741 #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) 7742 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 7743 */ 7744 #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) 7745 #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) 7746 #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) 7747 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 7748 */ 7749 #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) 7750 /*! @} */ 7751 7752 /*! @name FIFOINTSTAT - FIFO interrupt status register. */ 7753 /*! @{ */ 7754 #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) 7755 #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) 7756 /*! TXERR - TX FIFO error. 7757 */ 7758 #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) 7759 #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) 7760 #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) 7761 /*! RXERR - RX FIFO error. 7762 */ 7763 #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) 7764 #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) 7765 #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) 7766 /*! TXLVL - Transmit FIFO level interrupt. 7767 */ 7768 #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) 7769 #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) 7770 #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) 7771 /*! RXLVL - Receive FIFO level interrupt. 7772 */ 7773 #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) 7774 #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) 7775 #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) 7776 /*! PERINT - Peripheral interrupt. 7777 */ 7778 #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) 7779 /*! @} */ 7780 7781 /*! @name FIFOWR - FIFO write data. */ 7782 /*! @{ */ 7783 #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) 7784 #define SPI_FIFOWR_TXDATA_SHIFT (0U) 7785 /*! TXDATA - Transmit data to the FIFO. 7786 */ 7787 #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) 7788 #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) 7789 #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) 7790 /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. 7791 * 0b0..SSEL0 asserted. 7792 * 0b1..SSEL0 not asserted. 7793 */ 7794 #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) 7795 #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) 7796 #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) 7797 /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. 7798 * 0b0..SSEL1 asserted. 7799 * 0b1..SSEL1 not asserted. 7800 */ 7801 #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) 7802 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) 7803 #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) 7804 /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. 7805 * 0b0..SSEL2 asserted. 7806 * 0b1..SSEL2 not asserted. 7807 */ 7808 #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) 7809 #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) 7810 #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) 7811 /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. 7812 * 0b0..SSEL3 asserted. 7813 * 0b1..SSEL3 not asserted. 7814 */ 7815 #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) 7816 #define SPI_FIFOWR_EOT_MASK (0x100000U) 7817 #define SPI_FIFOWR_EOT_SHIFT (20U) 7818 /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain 7819 * so far at least the time specified by the Transfer_delay value in the DLY register. 7820 * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 7821 * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 7822 */ 7823 #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) 7824 #define SPI_FIFOWR_EOF_MASK (0x200000U) 7825 #define SPI_FIFOWR_EOF_SHIFT (21U) 7826 /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value 7827 * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay 7828 * value = 0. This control can be used as part of the support for frame lengths greater than 16 7829 * bits. 7830 * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. 7831 * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be 7832 * inserted before subsequent data is transmitted. 7833 */ 7834 #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) 7835 #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) 7836 #define SPI_FIFOWR_RXIGNORE_SHIFT (22U) 7837 /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to 7838 * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can 7839 * be used with the DMA. 7840 * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit 7841 * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data 7842 * is not read before new data is received. 7843 * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received 7844 * data. No receiver flags are generated. 7845 */ 7846 #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) 7847 #define SPI_FIFOWR_LEN_MASK (0xF000000U) 7848 #define SPI_FIFOWR_LEN_SHIFT (24U) 7849 /*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths 7850 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 7851 * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data 7852 * transfer is 16 bits in length. 7853 */ 7854 #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) 7855 /*! @} */ 7856 7857 /*! @name FIFORD - FIFO read data. */ 7858 /*! @{ */ 7859 #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) 7860 #define SPI_FIFORD_RXDATA_SHIFT (0U) 7861 /*! RXDATA - Received data from the FIFO. 7862 */ 7863 #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) 7864 #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) 7865 #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) 7866 /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved 7867 * along with received data. The value will reflect the SSEL0 pin for both master and slave 7868 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7869 * pin is configured by the related SPOL bit in CFG. 7870 */ 7871 #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) 7872 #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) 7873 #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) 7874 /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved 7875 * along with received data. The value will reflect the SSEL1 pin for both master and slave 7876 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7877 * pin is configured by the related SPOL bit in CFG. 7878 */ 7879 #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) 7880 #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) 7881 #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) 7882 /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved 7883 * along with received data. The value will reflect the SSEL2 pin for both master and slave 7884 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7885 * pin is configured by the related SPOL bit in CFG. 7886 */ 7887 #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) 7888 #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) 7889 #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) 7890 /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved 7891 * along with received data. The value will reflect the SSEL3 pin for both master and slave 7892 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 7893 * pin is configured by the related SPOL bit in CFG. 7894 */ 7895 #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) 7896 #define SPI_FIFORD_SOT_MASK (0x100000U) 7897 #define SPI_FIFORD_SOT_SHIFT (20U) 7898 /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went 7899 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be 7900 * used to identify the first piece of data in cases where the transfer length is greater than 16 7901 * bits. 7902 */ 7903 #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) 7904 /*! @} */ 7905 7906 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ 7907 /*! @{ */ 7908 #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) 7909 #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) 7910 /*! RXDATA - Received data from the FIFO. 7911 */ 7912 #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) 7913 #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) 7914 #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) 7915 /*! RXSSEL0_N - Slave Select for receive. 7916 */ 7917 #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) 7918 #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) 7919 #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) 7920 /*! RXSSEL1_N - Slave Select for receive. 7921 */ 7922 #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) 7923 #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) 7924 #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) 7925 /*! RXSSEL2_N - Slave Select for receive. 7926 */ 7927 #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) 7928 #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) 7929 #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) 7930 /*! RXSSEL3_N - Slave Select for receive. 7931 */ 7932 #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) 7933 #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) 7934 #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) 7935 /*! SOT - Start of transfer flag. 7936 */ 7937 #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) 7938 /*! @} */ 7939 7940 7941 /*! 7942 * @} 7943 */ /* end of group SPI_Register_Masks */ 7944 7945 7946 /* SPI - Peripheral instance base addresses */ 7947 /** Peripheral SPI0 base address */ 7948 #define SPI0_BASE (0x40086000u) 7949 /** Peripheral SPI0 base pointer */ 7950 #define SPI0 ((SPI_Type *)SPI0_BASE) 7951 /** Peripheral SPI1 base address */ 7952 #define SPI1_BASE (0x40087000u) 7953 /** Peripheral SPI1 base pointer */ 7954 #define SPI1 ((SPI_Type *)SPI1_BASE) 7955 /** Peripheral SPI2 base address */ 7956 #define SPI2_BASE (0x40088000u) 7957 /** Peripheral SPI2 base pointer */ 7958 #define SPI2 ((SPI_Type *)SPI2_BASE) 7959 /** Peripheral SPI3 base address */ 7960 #define SPI3_BASE (0x40089000u) 7961 /** Peripheral SPI3 base pointer */ 7962 #define SPI3 ((SPI_Type *)SPI3_BASE) 7963 /** Peripheral SPI4 base address */ 7964 #define SPI4_BASE (0x4008A000u) 7965 /** Peripheral SPI4 base pointer */ 7966 #define SPI4 ((SPI_Type *)SPI4_BASE) 7967 /** Peripheral SPI5 base address */ 7968 #define SPI5_BASE (0x40096000u) 7969 /** Peripheral SPI5 base pointer */ 7970 #define SPI5 ((SPI_Type *)SPI5_BASE) 7971 /** Peripheral SPI6 base address */ 7972 #define SPI6_BASE (0x40097000u) 7973 /** Peripheral SPI6 base pointer */ 7974 #define SPI6 ((SPI_Type *)SPI6_BASE) 7975 /** Peripheral SPI7 base address */ 7976 #define SPI7_BASE (0x40098000u) 7977 /** Peripheral SPI7 base pointer */ 7978 #define SPI7 ((SPI_Type *)SPI7_BASE) 7979 /** Array initializer of SPI peripheral base addresses */ 7980 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } 7981 /** Array initializer of SPI peripheral base pointers */ 7982 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } 7983 /** Interrupt vectors for the SPI peripheral type */ 7984 #define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 7985 7986 /*! 7987 * @} 7988 */ /* end of group SPI_Peripheral_Access_Layer */ 7989 7990 7991 /* ---------------------------------------------------------------------------- 7992 -- SPIFI Peripheral Access Layer 7993 ---------------------------------------------------------------------------- */ 7994 7995 /*! 7996 * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer 7997 * @{ 7998 */ 7999 8000 /** SPIFI - Register Layout Typedef */ 8001 typedef struct { 8002 __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ 8003 __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ 8004 __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ 8005 __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ 8006 __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ 8007 __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ 8008 __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ 8009 __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ 8010 } SPIFI_Type; 8011 8012 /* ---------------------------------------------------------------------------- 8013 -- SPIFI Register Masks 8014 ---------------------------------------------------------------------------- */ 8015 8016 /*! 8017 * @addtogroup SPIFI_Register_Masks SPIFI Register Masks 8018 * @{ 8019 */ 8020 8021 /*! @name CTRL - SPIFI control register */ 8022 /*! @{ */ 8023 #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) 8024 #define SPIFI_CTRL_TIMEOUT_SHIFT (0U) 8025 /*! TIMEOUT - This field contains the number of serial clock periods without the processor reading 8026 * data in memory mode, which will cause the SPIFI hardware to terminate the command by driving 8027 * the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory 8028 * to enter a lower-power state.) If the processor reads data from the flash region after a 8029 * time-out, the command in the Memory Command Register is issued again. 8030 */ 8031 #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) 8032 #define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) 8033 #define SPIFI_CTRL_CSHIGH_SHIFT (16U) 8034 /*! CSHIGH - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. 8035 */ 8036 #define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) 8037 #define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) 8038 #define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) 8039 /*! D_PRFTCH_DIS - This bit allows conditioning of memory mode prefetches based on the AHB HPROT 8040 * (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt 8041 * a speculative prefetch when it encounters data accesses. 8042 */ 8043 #define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) 8044 #define SPIFI_CTRL_INTEN_MASK (0x400000U) 8045 #define SPIFI_CTRL_INTEN_SHIFT (22U) 8046 /*! INTEN - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request 8047 * output. See INTRQ in the status register for further details. 8048 */ 8049 #define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) 8050 #define SPIFI_CTRL_MODE3_MASK (0x800000U) 8051 #define SPIFI_CTRL_MODE3_SHIFT (23U) 8052 /*! MODE3 - SPI Mode 3 select. 8053 * 0b0..SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is 8054 * captured, and keeps it low while CS is HIGH. 8055 * 0b1..SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is 8056 * HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but 8057 * some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 8058 * 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the 8059 * frame. 8060 */ 8061 #define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) 8062 #define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) 8063 #define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) 8064 /*! PRFTCH_DIS - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. 8065 * 0b0..Enable. Cache prefetching enabled. 8066 * 0b1..Disable. Disables prefetching of cache lines. 8067 */ 8068 #define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) 8069 #define SPIFI_CTRL_DUAL_MASK (0x10000000U) 8070 #define SPIFI_CTRL_DUAL_SHIFT (28U) 8071 /*! DUAL - Select dual protocol. 8072 * 0b0..Quad protocol. This protocol uses IO3:0. 8073 * 0b1..Dual protocol. This protocol uses IO1:0. 8074 */ 8075 #define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) 8076 #define SPIFI_CTRL_RFCLK_MASK (0x20000000U) 8077 #define SPIFI_CTRL_RFCLK_SHIFT (29U) 8078 /*! RFCLK - Select active clock edge for input data. 8079 * 0b0..Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation. 8080 * 0b1..Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time 8081 * in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in 8082 * this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 8083 */ 8084 #define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) 8085 #define SPIFI_CTRL_FBCLK_MASK (0x40000000U) 8086 #define SPIFI_CTRL_FBCLK_SHIFT (30U) 8087 /*! FBCLK - Feedback clock select. 8088 * 0b0..Internal clock. The SPIFI samples read data using an internal clock. 8089 * 0b1..Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more 8090 * time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no 8091 * final falling edge on SCK on which to sample the last data bit of the frame. 8092 */ 8093 #define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) 8094 #define SPIFI_CTRL_DMAEN_MASK (0x80000000U) 8095 #define SPIFI_CTRL_DMAEN_SHIFT (31U) 8096 /*! DMAEN - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a 8097 * DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA 8098 * channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used 8099 * in Command mode. 8100 */ 8101 #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) 8102 /*! @} */ 8103 8104 /*! @name CMD - SPIFI command register */ 8105 /*! @{ */ 8106 #define SPIFI_CMD_DATALEN_MASK (0x3FFFU) 8107 #define SPIFI_CMD_DATALEN_SHIFT (0U) 8108 /*! DATALEN - Except when the POLL bit in this register is 1, this field controls how many data 8109 * bytes are in the command. 0 indicates that the command does not contain a data field. 8110 */ 8111 #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) 8112 #define SPIFI_CMD_POLL_MASK (0x4000U) 8113 #define SPIFI_CMD_POLL_SHIFT (14U) 8114 /*! POLL - This bit should be written as 1 only with an opcode that a) contains an input data field, 8115 * and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status 8116 * command). When this bit is 1, the SPIFI hardware continues to read bytes until the test 8117 * specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by 8118 * DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, 8119 * the SPIFI captures the byte that meets this test so that it can be read from the Data 8120 * Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to 8121 * inform software when this occurs 8122 */ 8123 #define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) 8124 #define SPIFI_CMD_DOUT_MASK (0x8000U) 8125 #define SPIFI_CMD_DOUT_SHIFT (15U) 8126 /*! DOUT - If the DATALEN field is not zero, this bit controls the direction of the data: 8127 * 0b0..Input from serial flash. 8128 * 0b1..Output to serial flash. 8129 */ 8130 #define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) 8131 #define SPIFI_CMD_INTLEN_MASK (0x70000U) 8132 #define SPIFI_CMD_INTLEN_SHIFT (16U) 8133 /*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may 8134 * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 8135 * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control 8136 * information, dummy and delay bytes. See the description of the Intermediate Data register for 8137 * the contents of such bytes. 8138 */ 8139 #define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) 8140 #define SPIFI_CMD_FIELDFORM_MASK (0x180000U) 8141 #define SPIFI_CMD_FIELDFORM_SHIFT (19U) 8142 /*! FIELDFORM - This field controls how the fields of the command are sent. 8143 * 0b00..All serial. All fields of the command are serial. 8144 * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial. 8145 * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual. 8146 * 0b11..All quad/dual. All fields of the command are in quad/dual format. 8147 */ 8148 #define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) 8149 #define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) 8150 #define SPIFI_CMD_FRAMEFORM_SHIFT (21U) 8151 /*! FRAMEFORM - This field controls the opcode and address fields. 8152 * 0b000..Reserved. 8153 * 0b001..Opcode. Opcode only, no address. 8154 * 0b010..Opcode one byte. Opcode, least significant byte of address. 8155 * 0b011..Opcode two bytes. Opcode, two least significant bytes of address. 8156 * 0b100..Opcode three bytes. Opcode, three least significant bytes of address. 8157 * 0b101..Opcode four bytes. Opcode, 4 bytes of address. 8158 * 0b110..No opcode three bytes. No opcode, 3 least significant bytes of address. 8159 * 0b111..No opcode four bytes. No opcode, 4 bytes of address. 8160 */ 8161 #define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) 8162 #define SPIFI_CMD_OPCODE_MASK (0xFF000000U) 8163 #define SPIFI_CMD_OPCODE_SHIFT (24U) 8164 /*! OPCODE - The opcode of the command (not used for some FRAMEFORM values). 8165 */ 8166 #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) 8167 /*! @} */ 8168 8169 /*! @name ADDR - SPIFI address register */ 8170 /*! @{ */ 8171 #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) 8172 #define SPIFI_ADDR_ADDRESS_SHIFT (0U) 8173 /*! ADDRESS - Address. 8174 */ 8175 #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) 8176 /*! @} */ 8177 8178 /*! @name IDATA - SPIFI intermediate data register */ 8179 /*! @{ */ 8180 #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) 8181 #define SPIFI_IDATA_IDATA_SHIFT (0U) 8182 /*! IDATA - Value of intermediate bytes. 8183 */ 8184 #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) 8185 /*! @} */ 8186 8187 /*! @name CLIMIT - SPIFI limit register */ 8188 /*! @{ */ 8189 #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) 8190 #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) 8191 /*! CLIMIT - Zero-based upper limit of cacheable memory 8192 */ 8193 #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) 8194 /*! @} */ 8195 8196 /*! @name DATA - SPIFI data register */ 8197 /*! @{ */ 8198 #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) 8199 #define SPIFI_DATA_DATA_SHIFT (0U) 8200 /*! DATA - Input or output data 8201 */ 8202 #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) 8203 /*! @} */ 8204 8205 /*! @name MCMD - SPIFI memory command register */ 8206 /*! @{ */ 8207 #define SPIFI_MCMD_POLL_MASK (0x4000U) 8208 #define SPIFI_MCMD_POLL_SHIFT (14U) 8209 /*! POLL - This bit should be written as 0. 8210 */ 8211 #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) 8212 #define SPIFI_MCMD_DOUT_MASK (0x8000U) 8213 #define SPIFI_MCMD_DOUT_SHIFT (15U) 8214 /*! DOUT - This bit should be written as 0. 8215 */ 8216 #define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) 8217 #define SPIFI_MCMD_INTLEN_MASK (0x70000U) 8218 #define SPIFI_MCMD_INTLEN_SHIFT (16U) 8219 /*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may 8220 * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 8221 * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control 8222 * information, dummy and delay bytes. See the description of the Intermediate Data register for 8223 * the contents of such bytes. 8224 */ 8225 #define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) 8226 #define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) 8227 #define SPIFI_MCMD_FIELDFORM_SHIFT (19U) 8228 /*! FIELDFORM - This field controls how the fields of the command are sent. 8229 * 0b00..All serial. All fields of the command are serial. 8230 * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial. 8231 * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual. 8232 * 0b11..All quad/dual. All fields of the command are in quad/dual format. 8233 */ 8234 #define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) 8235 #define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) 8236 #define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) 8237 /*! FRAMEFORM - This field controls the opcode and address fields. 8238 * 0b000..Reserved. 8239 * 0b001..Opcode. Opcode only, no address. 8240 * 0b010..Opcode one byte. Opcode, least-significant byte of address. 8241 * 0b011..Opcode two bytes. Opcode, 2 least-significant bytes of address. 8242 * 0b100..Opcode three bytes. Opcode, 3 least-significant bytes of address. 8243 * 0b101..Opcode four bytes. Opcode, 4 bytes of address. 8244 * 0b110..No opcode three bytes. No opcode, 3 least-significant bytes of address. 8245 * 0b111..No opcode, 4 bytes of address. 8246 */ 8247 #define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) 8248 #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) 8249 #define SPIFI_MCMD_OPCODE_SHIFT (24U) 8250 /*! OPCODE - The opcode of the command (not used for some FRAMEFORM values). 8251 */ 8252 #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) 8253 /*! @} */ 8254 8255 /*! @name STAT - SPIFI status register */ 8256 /*! @{ */ 8257 #define SPIFI_STAT_MCINIT_MASK (0x1U) 8258 #define SPIFI_STAT_MCINIT_SHIFT (0U) 8259 /*! MCINIT - This bit is set when software successfully writes the Memory Command register, and is 8260 * cleared by Reset or by writing a 1 to the RESET bit in this register. 8261 */ 8262 #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) 8263 #define SPIFI_STAT_CMD_MASK (0x2U) 8264 #define SPIFI_STAT_CMD_SHIFT (1U) 8265 /*! CMD - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a 8266 * write to the RESET bit in this register, or the deassertion of CS which indicates that the 8267 * command has completed communication with the SPI Flash. 8268 */ 8269 #define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) 8270 #define SPIFI_STAT_RESET_MASK (0x10U) 8271 #define SPIFI_STAT_RESET_SHIFT (4U) 8272 /*! RESET - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared 8273 * when the hardware is ready for a new command to be written to the Command register. 8274 */ 8275 #define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) 8276 #define SPIFI_STAT_INTRQ_MASK (0x20U) 8277 #define SPIFI_STAT_INTRQ_SHIFT (5U) 8278 /*! INTRQ - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This 8279 * bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. 8280 */ 8281 #define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) 8282 #define SPIFI_STAT_VERSION_MASK (0xFF000000U) 8283 #define SPIFI_STAT_VERSION_SHIFT (24U) 8284 /*! VERSION - - 8285 */ 8286 #define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) 8287 /*! @} */ 8288 8289 8290 /*! 8291 * @} 8292 */ /* end of group SPIFI_Register_Masks */ 8293 8294 8295 /* SPIFI - Peripheral instance base addresses */ 8296 /** Peripheral SPIFI0 base address */ 8297 #define SPIFI0_BASE (0x40080000u) 8298 /** Peripheral SPIFI0 base pointer */ 8299 #define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) 8300 /** Array initializer of SPIFI peripheral base addresses */ 8301 #define SPIFI_BASE_ADDRS { SPIFI0_BASE } 8302 /** Array initializer of SPIFI peripheral base pointers */ 8303 #define SPIFI_BASE_PTRS { SPIFI0 } 8304 8305 /*! 8306 * @} 8307 */ /* end of group SPIFI_Peripheral_Access_Layer */ 8308 8309 8310 /* ---------------------------------------------------------------------------- 8311 -- SYSCON Peripheral Access Layer 8312 ---------------------------------------------------------------------------- */ 8313 8314 /*! 8315 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer 8316 * @{ 8317 */ 8318 8319 /** SYSCON - Register Layout Typedef */ 8320 typedef struct { 8321 uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ 8322 uint8_t RESERVED_0[12]; 8323 __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ 8324 uint8_t RESERVED_1[44]; 8325 __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ 8326 uint8_t RESERVED_2[4]; 8327 __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ 8328 __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ 8329 uint8_t RESERVED_3[112]; 8330 __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ 8331 uint8_t RESERVED_4[8]; 8332 __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ 8333 uint8_t RESERVED_5[40]; 8334 __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ 8335 uint8_t RESERVED_6[24]; 8336 __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ 8337 uint8_t RESERVED_7[24]; 8338 __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ 8339 uint8_t RESERVED_8[168]; 8340 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ 8341 uint8_t RESERVED_9[12]; 8342 __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ 8343 uint8_t RESERVED_10[24]; 8344 __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ 8345 uint8_t RESERVED_11[24]; 8346 __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ 8347 uint8_t RESERVED_12[56]; 8348 __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ 8349 __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ 8350 __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ 8351 uint8_t RESERVED_13[4]; 8352 __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ 8353 uint8_t RESERVED_14[12]; 8354 __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ 8355 __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ 8356 __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ 8357 uint8_t RESERVED_15[4]; 8358 __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ 8359 uint8_t RESERVED_16[16]; 8360 __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ 8361 uint8_t RESERVED_17[4]; 8362 __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ 8363 __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */ 8364 uint8_t RESERVED_18[16]; 8365 __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ 8366 __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */ 8367 uint8_t RESERVED_19[120]; 8368 __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ 8369 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ 8370 uint8_t RESERVED_20[8]; 8371 __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ 8372 __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ 8373 __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ 8374 uint8_t RESERVED_21[4]; 8375 __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ 8376 uint8_t RESERVED_22[4]; 8377 __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ 8378 __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ 8379 uint8_t RESERVED_23[80]; 8380 __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ 8381 uint8_t RESERVED_24[8]; 8382 __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ 8383 __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ 8384 uint8_t RESERVED_25[4]; 8385 __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ 8386 uint8_t RESERVED_26[4]; 8387 __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ 8388 uint8_t RESERVED_27[220]; 8389 __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ 8390 uint8_t RESERVED_28[4]; 8391 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ 8392 __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ 8393 uint8_t RESERVED_29[112]; 8394 __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ 8395 __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ 8396 __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ 8397 __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ 8398 __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ 8399 __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ 8400 uint8_t RESERVED_30[104]; 8401 __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ 8402 uint8_t RESERVED_31[8]; 8403 __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */ 8404 uint8_t RESERVED_32[8]; 8405 __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ 8406 uint8_t RESERVED_33[8]; 8407 __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ 8408 uint8_t RESERVED_34[72]; 8409 __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ 8410 uint8_t RESERVED_35[24]; 8411 __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ 8412 uint8_t RESERVED_36[24]; 8413 __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ 8414 uint8_t RESERVED_37[184]; 8415 __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ 8416 uint8_t RESERVED_38[124]; 8417 __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ 8418 __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ 8419 __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ 8420 __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ 8421 uint8_t RESERVED_39[1524]; 8422 __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ 8423 uint8_t RESERVED_40[492]; 8424 __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ 8425 __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ 8426 __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ 8427 uint8_t RESERVED_41[127044]; 8428 __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ 8429 } SYSCON_Type; 8430 8431 /* ---------------------------------------------------------------------------- 8432 -- SYSCON Register Masks 8433 ---------------------------------------------------------------------------- */ 8434 8435 /*! 8436 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks 8437 * @{ 8438 */ 8439 8440 /*! @name AHBMATPRIO - AHB multilayer matrix priority control */ 8441 /*! @{ */ 8442 #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) 8443 #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) 8444 /*! PRI_ICODE - Cortex-M4 I-Code bus priority. Should typically be lower than PRI_DCODE for best operation. 8445 */ 8446 #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) 8447 #define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) 8448 #define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) 8449 /*! PRI_DCODE - Cortex M4 D-Code bus priority. 8450 */ 8451 #define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) 8452 #define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) 8453 #define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) 8454 /*! PRI_SYS - Cortex M4 System bus priority. 8455 */ 8456 #define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) 8457 #define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) 8458 #define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) 8459 /*! PRI_M0 - Cortex-M0+ bus priority. Present on selected devices. 8460 */ 8461 #define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) 8462 #define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) 8463 #define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) 8464 /*! PRI_USB - USB interface priority. 8465 */ 8466 #define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) 8467 #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) 8468 #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) 8469 /*! PRI_DMA - DMA controller priority. 8470 */ 8471 #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) 8472 /*! @} */ 8473 8474 /*! @name SYSTCKCAL - System tick counter calibration */ 8475 /*! @{ */ 8476 #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) 8477 #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) 8478 /*! CAL - System tick timer calibration value. 8479 */ 8480 #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) 8481 #define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) 8482 #define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) 8483 /*! SKEW - Initial value for the Systick timer. 8484 */ 8485 #define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) 8486 #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) 8487 #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) 8488 /*! NOREF - Initial value for the Systick timer. 8489 */ 8490 #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) 8491 /*! @} */ 8492 8493 /*! @name NMISRC - NMI Source Select */ 8494 /*! @{ */ 8495 #define SYSCON_NMISRC_IRQM4_MASK (0x3FU) 8496 #define SYSCON_NMISRC_IRQM4_SHIFT (0U) 8497 /*! IRQM4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4. 8498 */ 8499 #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) 8500 #define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) 8501 #define SYSCON_NMISRC_IRQM0_SHIFT (8U) 8502 /*! IRQM0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the 8503 * Cortex-M0+, if enabled by NMIENM0. Present on selected devices. 8504 */ 8505 #define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) 8506 #define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) 8507 #define SYSCON_NMISRC_NMIENM0_SHIFT (30U) 8508 /*! NMIENM0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices. 8509 */ 8510 #define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) 8511 #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) 8512 #define SYSCON_NMISRC_NMIENM4_SHIFT (31U) 8513 /*! NMIENM4 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4. 8514 */ 8515 #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) 8516 /*! @} */ 8517 8518 /*! @name ASYNCAPBCTRL - Asynchronous APB Control */ 8519 /*! @{ */ 8520 #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) 8521 #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) 8522 /*! ENABLE - Enables the asynchronous APB bridge and subsystem. 8523 * 0b0..Disabled. Asynchronous APB bridge is disabled. 8524 * 0b1..Enabled. Asynchronous APB bridge is enabled. 8525 */ 8526 #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) 8527 /*! @} */ 8528 8529 /*! @name PIOPORCAP - POR captured value of port n */ 8530 /*! @{ */ 8531 #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) 8532 #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) 8533 /*! PIOPORCAP - State of PIOn_31 through PIOn_0 at power-on reset 8534 */ 8535 #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) 8536 /*! @} */ 8537 8538 /* The count of SYSCON_PIOPORCAP */ 8539 #define SYSCON_PIOPORCAP_COUNT (2U) 8540 8541 /*! @name PIORESCAP - Reset captured value of port n */ 8542 /*! @{ */ 8543 #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) 8544 #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) 8545 /*! PIORESCAP - State of PIOn_31 through PIOn_0 for resets other than POR. 8546 */ 8547 #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) 8548 /*! @} */ 8549 8550 /* The count of SYSCON_PIORESCAP */ 8551 #define SYSCON_PIORESCAP_COUNT (2U) 8552 8553 /*! @name PRESETCTRL - Peripheral reset control n */ 8554 /*! @{ */ 8555 #define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) 8556 #define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) 8557 /*! MRT0_RST - Multi-rate timer (MRT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8558 */ 8559 #define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) 8560 #define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) 8561 #define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) 8562 /*! SCT0_RST - State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8563 */ 8564 #define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) 8565 #define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) 8566 #define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) 8567 /*! FLASH_RST - Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8568 */ 8569 #define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) 8570 #define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) 8571 #define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) 8572 /*! FMC_RST - Flash accelerator reset control. Note that the FMC must not be reset while executing 8573 * from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert 8574 * reset to this function. 8575 */ 8576 #define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) 8577 #define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) 8578 #define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) 8579 /*! UTICK0_RST - Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8580 */ 8581 #define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) 8582 #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) 8583 #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) 8584 /*! FC0_RST - Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8585 */ 8586 #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) 8587 #define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) 8588 #define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) 8589 /*! MUX_RST - Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8590 */ 8591 #define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) 8592 #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) 8593 #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) 8594 /*! FC1_RST - Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8595 */ 8596 #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) 8597 #define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) 8598 #define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) 8599 /*! FC2_RST - Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8600 */ 8601 #define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) 8602 #define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) 8603 #define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) 8604 /*! IOCON_RST - IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8605 */ 8606 #define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) 8607 #define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) 8608 #define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) 8609 /*! FC3_RST - Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8610 */ 8611 #define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) 8612 #define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) 8613 #define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) 8614 /*! GPIO0_RST - GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8615 */ 8616 #define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) 8617 #define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) 8618 #define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) 8619 /*! FC4_RST - Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8620 */ 8621 #define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) 8622 #define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) 8623 #define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) 8624 /*! GPIO1_RST - GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8625 */ 8626 #define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) 8627 #define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) 8628 #define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) 8629 /*! FC5_RST - Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8630 */ 8631 #define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) 8632 #define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) 8633 #define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) 8634 /*! FC6_RST - Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8635 */ 8636 #define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) 8637 #define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) 8638 #define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) 8639 /*! FC7_RST - Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8640 */ 8641 #define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) 8642 #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) 8643 #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) 8644 /*! PINT_RST - Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8645 */ 8646 #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) 8647 #define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) 8648 #define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) 8649 /*! DMIC0_RST - Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8650 */ 8651 #define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) 8652 #define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) 8653 #define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) 8654 /*! GINT_RST - Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8655 */ 8656 #define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) 8657 #define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) 8658 #define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) 8659 /*! DMA0_RST - DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8660 */ 8661 #define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) 8662 #define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) 8663 #define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) 8664 /*! CRC_RST - CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8665 */ 8666 #define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) 8667 #define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) 8668 #define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) 8669 /*! CTIMER2_RST - CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function 8670 */ 8671 #define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) 8672 #define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) 8673 #define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) 8674 /*! WWDT_RST - Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8675 */ 8676 #define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) 8677 #define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) 8678 #define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) 8679 /*! USB0_RST - USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8680 */ 8681 #define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) 8682 #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) 8683 #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) 8684 /*! CTIMER0_RST - CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8685 */ 8686 #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) 8687 #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) 8688 #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) 8689 /*! ADC0_RST - ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8690 */ 8691 #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) 8692 #define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) 8693 #define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) 8694 /*! CTIMER1_RST - CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. 8695 */ 8696 #define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) 8697 /*! @} */ 8698 8699 /* The count of SYSCON_PRESETCTRL */ 8700 #define SYSCON_PRESETCTRL_COUNT (2U) 8701 8702 /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ 8703 /*! @{ */ 8704 #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) 8705 #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) 8706 /*! RST_SET - Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn 8707 * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn 8708 * are reserved and only zeroes should be written to them. 8709 */ 8710 #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) 8711 /*! @} */ 8712 8713 /* The count of SYSCON_PRESETCTRLSET */ 8714 #define SYSCON_PRESETCTRLSET_COUNT (2U) 8715 8716 /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ 8717 /*! @{ */ 8718 #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) 8719 #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) 8720 /*! RST_CLR - Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn 8721 * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn 8722 * are reserved and only zeroes should be written to them. 8723 */ 8724 #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) 8725 /*! @} */ 8726 8727 /* The count of SYSCON_PRESETCTRLCLR */ 8728 #define SYSCON_PRESETCTRLCLR_COUNT (2U) 8729 8730 /*! @name SYSRSTSTAT - System reset status register */ 8731 /*! @{ */ 8732 #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) 8733 #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) 8734 /*! POR - POR reset status 8735 * 0b0..No POR detected 8736 * 0b1..POR detected. Writing a one clears this reset. 8737 */ 8738 #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) 8739 #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) 8740 #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) 8741 /*! EXTRST - Status of the external RESET pin. External reset status 8742 * 0b0..No reset event detected. 8743 * 0b1..Reset detected. Writing a one clears this reset. 8744 */ 8745 #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) 8746 #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) 8747 #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) 8748 /*! WDT - Status of the Watchdog reset 8749 * 0b0..No WDT reset detected 8750 * 0b1..WDT reset detected. Writing a one clears this reset. 8751 */ 8752 #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) 8753 #define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) 8754 #define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) 8755 /*! BOD - Status of the Brown-out detect reset 8756 * 0b0..No BOD reset detected 8757 * 0b1..BOD reset detected. Writing a one clears this reset. 8758 */ 8759 #define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) 8760 #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) 8761 #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) 8762 /*! SYSRST - Status of the software system reset 8763 * 0b0..No System reset detected 8764 * 0b1..System reset detected. Writing a one clears this reset. 8765 */ 8766 #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) 8767 /*! @} */ 8768 8769 /*! @name AHBCLKCTRL - AHB Clock control n */ 8770 /*! @{ */ 8771 #define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) 8772 #define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) 8773 /*! MRT0 - Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable. 8774 */ 8775 #define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) 8776 #define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) 8777 #define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) 8778 /*! ROM - Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable. 8779 */ 8780 #define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) 8781 #define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) 8782 #define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) 8783 /*! SCT0 - Enables the clock for SCT0. 0 = Disable; 1 = Enable. 8784 */ 8785 #define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) 8786 #define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) 8787 #define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) 8788 /*! SRAM1 - Enables the clock for SRAM1. 0 = Disable; 1 = Enable. 8789 */ 8790 #define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) 8791 #define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) 8792 #define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) 8793 /*! SRAM2 - Enables the clock for SRAM2. 0 = Disable; 1 = Enable. 8794 */ 8795 #define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) 8796 #define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) 8797 #define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) 8798 /*! FLASH - Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is 8799 * needed for flash programming, not for flash read. 8800 */ 8801 #define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) 8802 #define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) 8803 #define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) 8804 /*! FMC - Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read. 8805 */ 8806 #define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) 8807 #define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) 8808 #define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) 8809 /*! UTICK0 - Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable. 8810 */ 8811 #define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) 8812 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) 8813 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) 8814 /*! FLEXCOMM0 - Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable. 8815 */ 8816 #define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) 8817 #define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) 8818 #define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) 8819 /*! INPUTMUX - Enables the clock for the input muxes. 0 = Disable; 1 = Enable. 8820 */ 8821 #define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) 8822 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) 8823 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) 8824 /*! FLEXCOMM1 - Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable. 8825 */ 8826 #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) 8827 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) 8828 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) 8829 /*! FLEXCOMM2 - Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable. 8830 */ 8831 #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) 8832 #define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) 8833 #define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) 8834 /*! IOCON - Enables the clock for the IOCON block. 0 = Disable; 1 = Enable. 8835 */ 8836 #define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) 8837 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) 8838 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) 8839 /*! FLEXCOMM3 - Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable. 8840 */ 8841 #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) 8842 #define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) 8843 #define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) 8844 /*! GPIO0 - Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable. 8845 */ 8846 #define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) 8847 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) 8848 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) 8849 /*! FLEXCOMM4 - Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable. 8850 */ 8851 #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) 8852 #define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) 8853 #define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) 8854 /*! GPIO1 - Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable. 8855 */ 8856 #define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) 8857 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) 8858 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) 8859 /*! FLEXCOMM5 - Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable. 8860 */ 8861 #define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) 8862 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) 8863 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) 8864 /*! FLEXCOMM6 - Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable. 8865 */ 8866 #define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) 8867 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) 8868 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) 8869 /*! FLEXCOMM7 - Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable. 8870 */ 8871 #define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) 8872 #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) 8873 #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) 8874 /*! PINT - Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable. 8875 */ 8876 #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) 8877 #define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) 8878 #define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) 8879 /*! DMIC0 - Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable. 8880 */ 8881 #define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) 8882 #define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) 8883 #define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) 8884 /*! GINT - Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable. 8885 */ 8886 #define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) 8887 #define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) 8888 #define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) 8889 /*! DMA0 - Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable. 8890 */ 8891 #define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) 8892 #define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) 8893 #define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) 8894 /*! CRC - Enables the clock for the CRC engine. 0 = Disable; 1 = Enable. 8895 */ 8896 #define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) 8897 #define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) 8898 #define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) 8899 /*! CTIMER2 - Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable. 8900 */ 8901 #define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) 8902 #define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) 8903 #define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) 8904 /*! WWDT - Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable. 8905 */ 8906 #define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) 8907 #define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) 8908 #define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) 8909 /*! RTC - Enables the bus clock for the RTC. 0 = Disable; 1 = Enable. 8910 */ 8911 #define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) 8912 #define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) 8913 #define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) 8914 /*! USB0 - Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable. 8915 */ 8916 #define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) 8917 #define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) 8918 #define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) 8919 /*! CTIMER0 - Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable. 8920 */ 8921 #define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) 8922 #define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) 8923 #define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) 8924 /*! MAILBOX - Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on selected devices 8925 */ 8926 #define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) 8927 #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) 8928 #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) 8929 /*! ADC0 - Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable. 8930 */ 8931 #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) 8932 #define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) 8933 #define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) 8934 /*! CTIMER1 - Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable. 8935 */ 8936 #define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) 8937 /*! @} */ 8938 8939 /* The count of SYSCON_AHBCLKCTRL */ 8940 #define SYSCON_AHBCLKCTRL_COUNT (2U) 8941 8942 /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ 8943 /*! @{ */ 8944 #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) 8945 #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) 8946 /*! CLK_SET - Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn 8947 * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn 8948 * are reserved and only zeroes should be written to them. 8949 */ 8950 #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) 8951 /*! @} */ 8952 8953 /* The count of SYSCON_AHBCLKCTRLSET */ 8954 #define SYSCON_AHBCLKCTRLSET_COUNT (2U) 8955 8956 /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ 8957 /*! @{ */ 8958 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) 8959 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) 8960 /*! CLK_CLR - Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn 8961 * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn 8962 * are reserved and only zeroes should be written to them. 8963 */ 8964 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) 8965 /*! @} */ 8966 8967 /* The count of SYSCON_AHBCLKCTRLCLR */ 8968 #define SYSCON_AHBCLKCTRLCLR_COUNT (2U) 8969 8970 /*! @name MAINCLKSELA - Main clock source select A */ 8971 /*! @{ */ 8972 #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) 8973 #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) 8974 /*! SEL - Clock source for main clock source selector A 8975 * 0b00..FRO 12 MHz (fro_12m) 8976 * 0b01..CLKIN (clk_in) 8977 * 0b10..Watchdog oscillator (wdt_clk) 8978 * 0b11..FRO 96 or 48 MHz (fro_hf) 8979 */ 8980 #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) 8981 /*! @} */ 8982 8983 /*! @name MAINCLKSELB - Main clock source select B */ 8984 /*! @{ */ 8985 #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) 8986 #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) 8987 /*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock. 8988 * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register. 8989 * 0b01..Reserved setting 8990 * 0b10..System PLL output (pll_clk) 8991 * 0b11..RTC oscillator 32 kHz output (32k_clk) 8992 */ 8993 #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) 8994 /*! @} */ 8995 8996 /*! @name CLKOUTSELA - CLKOUT clock source select A */ 8997 /*! @{ */ 8998 #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) 8999 #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) 9000 /*! SEL - CLKOUT clock source selection 9001 * 0b000..Main clock (main_clk) 9002 * 0b001..CLKIN (clk_in) 9003 * 0b010..Watchdog oscillator (wdt_clk) 9004 * 0b011..FRO 96 or 48 MHz (fro_hf) 9005 * 0b100..PLL output (pll_clk) 9006 * 0b101..FRO 12 MHz (fro_12m) 9007 * 0b110..RTC oscillator 32 kHz output (32k_clk) 9008 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9009 */ 9010 #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) 9011 /*! @} */ 9012 9013 /*! @name SYSPLLCLKSEL - PLL clock source select */ 9014 /*! @{ */ 9015 #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) 9016 #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) 9017 /*! SEL - System PLL clock source selection 9018 * 0b000..FRO 12 MHz (fro_12m) 9019 * 0b001..CLKIN (clk_in) 9020 * 0b010..Watchdog oscillator (wdt_clk) 9021 * 0b011..RTC 32 kHz clock (32k_clk) 9022 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9023 */ 9024 #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) 9025 /*! @} */ 9026 9027 /*! @name SPIFICLKSEL - SPIFI clock source select */ 9028 /*! @{ */ 9029 #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) 9030 #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) 9031 /*! SEL - System PLL clock source selection 9032 * 0b000..Main clock (main_clk) 9033 * 0b001..System PLL output (pll_clk) 9034 * 0b011..FRO 96 or 48 MHz (fro_hf) 9035 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9036 */ 9037 #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) 9038 /*! @} */ 9039 9040 /*! @name ADCCLKSEL - ADC clock source select */ 9041 /*! @{ */ 9042 #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) 9043 #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) 9044 /*! SEL - ADC clock source selection 9045 * 0b000..Main clock (main_clk) 9046 * 0b001..System PLL output (pll_clk) 9047 * 0b010..FRO 96 or 48 MHz (fro_hf) 9048 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9049 */ 9050 #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) 9051 /*! @} */ 9052 9053 /*! @name USBCLKSEL - USB clock source select */ 9054 /*! @{ */ 9055 #define SYSCON_USBCLKSEL_SEL_MASK (0x7U) 9056 #define SYSCON_USBCLKSEL_SEL_SHIFT (0U) 9057 /*! SEL - USB device clock source selection 9058 * 0b000..FRO 96 or 48 MHz (fro_hf) 9059 * 0b001..System PLL output (pll_clk) 9060 * 0b010..Main clock (main_clk) 9061 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9062 */ 9063 #define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) 9064 /*! @} */ 9065 9066 /*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ 9067 /*! @{ */ 9068 #define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) 9069 #define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) 9070 /*! SEL - Flexcomm clock source selection. One per Flexcomm. 9071 * 0b000..FRO 12 MHz (fro_12m) 9072 * 0b001..FRO 96 or 48 MHz (fro_hf) 9073 * 0b010..System PLL output (pll_clk) 9074 * 0b011..MCLK pin input, when selected in IOCON (mclk_in) 9075 * 0b100..FRG clock, the output of the fractional rate generator (frg_clk) 9076 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9077 */ 9078 #define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) 9079 /*! @} */ 9080 9081 /* The count of SYSCON_FXCOMCLKSEL */ 9082 #define SYSCON_FXCOMCLKSEL_COUNT (8U) 9083 9084 /*! @name MCLKCLKSEL - MCLK clock source select */ 9085 /*! @{ */ 9086 #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) 9087 #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) 9088 /*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem. 9089 * 0b000..FRO 96 or 48 MHz (fro_hf) 9090 * 0b001..System PLL output (pll_clk) 9091 * 0b010..Main clock (main_clk) 9092 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9093 */ 9094 #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) 9095 /*! @} */ 9096 9097 /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ 9098 /*! @{ */ 9099 #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) 9100 #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) 9101 /*! SEL - Fractional Rate Generator clock source select. 9102 * 0b000..Main clock (main_clk) 9103 * 0b001..System PLL output (pll_clk) 9104 * 0b010..FRO 12 MHz (fro_12m) 9105 * 0b011..FRO 96 or 48 MHz (fro_hf) 9106 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9107 */ 9108 #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) 9109 /*! @} */ 9110 9111 /*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ 9112 /*! @{ */ 9113 #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) 9114 #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) 9115 /*! SEL - D-Mic subsystem clock source select. 9116 * 0b000..FRO 12 MHz (fro_12m) 9117 * 0b001..FRO 96 or 48 MHz (fro_hf) 9118 * 0b010..System PLL output (pll_clk) 9119 * 0b011..MCLK pin input, when selected in IOCON (mclk_in) 9120 * 0b100..Main clock (main_clk) 9121 * 0b101..Watchdog oscillator (wdt_clk) 9122 * 0b110..Reserved setting 9123 * 0b111..None, this may be selected in order to reduce power when no output is needed. 9124 */ 9125 #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) 9126 /*! @} */ 9127 9128 /*! @name SYSTICKCLKDIV - SYSTICK clock divider */ 9129 /*! @{ */ 9130 #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) 9131 #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) 9132 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9133 */ 9134 #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) 9135 #define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) 9136 #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) 9137 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9138 * away rather than completing the previous count. 9139 */ 9140 #define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) 9141 #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) 9142 #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) 9143 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9144 * without the risk of a glitch at the output. 9145 */ 9146 #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) 9147 /*! @} */ 9148 9149 /*! @name TRACECLKDIV - Trace clock divider */ 9150 /*! @{ */ 9151 #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) 9152 #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) 9153 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9154 */ 9155 #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) 9156 #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) 9157 #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) 9158 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9159 * away rather than completing the previous count. 9160 */ 9161 #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) 9162 #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) 9163 #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) 9164 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9165 * without the risk of a glitch at the output. 9166 */ 9167 #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) 9168 /*! @} */ 9169 9170 /*! @name AHBCLKDIV - AHB clock divider */ 9171 /*! @{ */ 9172 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) 9173 #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) 9174 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9175 */ 9176 #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) 9177 #define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) 9178 #define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) 9179 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9180 * away rather than completing the previous count. 9181 */ 9182 #define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) 9183 #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) 9184 #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) 9185 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9186 * without the risk of a glitch at the output. 9187 */ 9188 #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) 9189 /*! @} */ 9190 9191 /*! @name CLKOUTDIV - CLKOUT clock divider */ 9192 /*! @{ */ 9193 #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) 9194 #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) 9195 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9196 */ 9197 #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) 9198 #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) 9199 #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) 9200 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9201 * away rather than completing the previous count. 9202 */ 9203 #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) 9204 #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) 9205 #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) 9206 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9207 * without the risk of a glitch at the output. 9208 */ 9209 #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) 9210 /*! @} */ 9211 9212 /*! @name SPIFICLKDIV - SPIFI clock divider */ 9213 /*! @{ */ 9214 #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) 9215 #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) 9216 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9217 */ 9218 #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) 9219 #define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) 9220 #define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) 9221 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9222 * away rather than completing the previous count. 9223 */ 9224 #define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) 9225 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) 9226 #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) 9227 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9228 * without the risk of a glitch at the output. 9229 */ 9230 #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) 9231 /*! @} */ 9232 9233 /*! @name ADCCLKDIV - ADC clock divider */ 9234 /*! @{ */ 9235 #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) 9236 #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) 9237 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9238 */ 9239 #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) 9240 #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) 9241 #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) 9242 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9243 * away rather than completing the previous count. 9244 */ 9245 #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) 9246 #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) 9247 #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) 9248 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9249 * without the risk of a glitch at the output. 9250 */ 9251 #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) 9252 /*! @} */ 9253 9254 /*! @name USBCLKDIV - USB clock divider */ 9255 /*! @{ */ 9256 #define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) 9257 #define SYSCON_USBCLKDIV_DIV_SHIFT (0U) 9258 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9259 */ 9260 #define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) 9261 #define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U) 9262 #define SYSCON_USBCLKDIV_RESET_SHIFT (29U) 9263 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9264 * away rather than completing the previous count. 9265 */ 9266 #define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK) 9267 #define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) 9268 #define SYSCON_USBCLKDIV_HALT_SHIFT (30U) 9269 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9270 * without the risk of a glitch at the output. 9271 */ 9272 #define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) 9273 /*! @} */ 9274 9275 /*! @name FRGCTRL - Fractional rate divider */ 9276 /*! @{ */ 9277 #define SYSCON_FRGCTRL_DIV_MASK (0xFFU) 9278 #define SYSCON_FRGCTRL_DIV_SHIFT (0U) 9279 /*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set 9280 * to 0xFF to use with the fractional baud rate generator. 9281 */ 9282 #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) 9283 #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) 9284 #define SYSCON_FRGCTRL_MULT_SHIFT (8U) 9285 /*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value. 9286 */ 9287 #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) 9288 /*! @} */ 9289 9290 /*! @name DMICCLKDIV - DMIC clock divider */ 9291 /*! @{ */ 9292 #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) 9293 #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) 9294 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9295 */ 9296 #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) 9297 #define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) 9298 #define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) 9299 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9300 * away rather than completing the previous count. 9301 */ 9302 #define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) 9303 #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) 9304 #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) 9305 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9306 * without the risk of a glitch at the output. 9307 */ 9308 #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) 9309 /*! @} */ 9310 9311 /*! @name MCLKDIV - I2S MCLK clock divider */ 9312 /*! @{ */ 9313 #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) 9314 #define SYSCON_MCLKDIV_DIV_SHIFT (0U) 9315 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256. 9316 */ 9317 #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) 9318 #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) 9319 #define SYSCON_MCLKDIV_RESET_SHIFT (29U) 9320 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right 9321 * away rather than completing the previous count. 9322 */ 9323 #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) 9324 #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) 9325 #define SYSCON_MCLKDIV_HALT_SHIFT (30U) 9326 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed 9327 * without the risk of a glitch at the output. 9328 */ 9329 #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) 9330 /*! @} */ 9331 9332 /*! @name FLASHCFG - Flash wait states configuration */ 9333 /*! @{ */ 9334 #define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) 9335 #define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) 9336 /*! FETCHCFG - Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches. 9337 * 0b00..Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of 9338 * the flash memory. This setting may use significantly more power than when buffering is enabled. 9339 * 0b01..One buffer is used for all instruction fetches. 9340 * 0b10..All buffers may be used for instruction fetches. 9341 * 0b11..Reserved setting, do not use. 9342 */ 9343 #define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) 9344 #define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) 9345 #define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) 9346 /*! DATACFG - Data read configuration. This field determines how flash accelerator buffers are used for data accesses. 9347 * 0b00..Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory. 9348 * 0b01..One buffer is used for all data accesses. 9349 * 0b10..All buffers may be used for data accesses. 9350 * 0b11..Reserved setting, do not use. 9351 */ 9352 #define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) 9353 #define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) 9354 #define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) 9355 /*! ACCEL - Acceleration enable. 9356 * 0b0..Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM 9357 * + 1 system clocks. This allows more determinism at a cost of performance. 9358 * 0b1..Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings. 9359 */ 9360 #define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) 9361 #define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) 9362 #define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) 9363 /*! PREFEN - Prefetch enable. 9364 * 0b0..No instruction prefetch is performed. 9365 * 0b1..If the FETCHCFG field is not 0, the next flash line following the current execution address is 9366 * automatically prefetched if it is not already buffered. 9367 */ 9368 #define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) 9369 #define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) 9370 #define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) 9371 /*! PREFOVR - Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is 9372 * completing for which the next flash line is not already buffered or being prefetched. 9373 * 0b0..Any previously initiated prefetch will be completed. 9374 * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current 9375 * execution address will be prefetched if not already buffered. 9376 */ 9377 #define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) 9378 #define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) 9379 #define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) 9380 /*! FLASHTIM - Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. 9381 * 0b0000..1 system clock flash access time (for system clock rates up to 12 MHz). 9382 * 0b0001..2 system clocks flash access time (for system clock rates up to 30 MHz). 9383 * 0b0010..3 system clocks flash access time (for system clock rates up to 60 MHz). 9384 * 0b0011..4 system clocks flash access time (for system clock rates up to 85 MHz). 9385 * 0b0100..5 system clocks flash access time (for system clock rates up to 100 MHz). 9386 */ 9387 #define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) 9388 /*! @} */ 9389 9390 /*! @name USBCLKCTRL - USB clock control */ 9391 /*! @{ */ 9392 #define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) 9393 #define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) 9394 /*! POL_CLK - USB_NEED_CLK polarity for triggering the USB wake-up interrupt 9395 * 0b0..Falling edge of the USB_NEED_CLK triggers the USB wake-up (default). 9396 * 0b1..Rising edge of the USB_NEED_CLK triggers the USB wake-up. 9397 */ 9398 #define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) 9399 /*! @} */ 9400 9401 /*! @name USBCLKSTAT - USB clock status */ 9402 /*! @{ */ 9403 #define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) 9404 #define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) 9405 /*! NEED_CLKST - USB_NEED_CLK signal status 9406 * 0b0..Low 9407 * 0b1..High 9408 */ 9409 #define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) 9410 /*! @} */ 9411 9412 /*! @name FREQMECTRL - Frequency measure register */ 9413 /*! @{ */ 9414 #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) 9415 #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) 9416 /*! CAPVAL - Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only. 9417 */ 9418 #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) 9419 #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) 9420 #define SYSCON_FREQMECTRL_PROG_SHIFT (31U) 9421 /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit 9422 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field 9423 * (bits 13:0). 9424 */ 9425 #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) 9426 /*! @} */ 9427 9428 /*! @name MCLKIO - MCLK input/output control */ 9429 /*! @{ */ 9430 #define SYSCON_MCLKIO_DIR_MASK (0x1U) 9431 #define SYSCON_MCLKIO_DIR_SHIFT (0U) 9432 /*! DIR - MCLK direction control. 9433 * 0b0..The MCLK function is an input. 9434 * 0b1..The MCLK function is an output. 9435 */ 9436 #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) 9437 /*! @} */ 9438 9439 /*! @name FROCTRL - FRO oscillator control */ 9440 /*! @{ */ 9441 #define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) 9442 #define SYSCON_FROCTRL_TRIM_SHIFT (0U) 9443 /*! TRIM - This value is factory trimmed to account for bias and temperature compensation. The value 9444 * should not be changed by software. Also see the WRTRIM bit description. 9445 */ 9446 #define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) 9447 #define SYSCON_FROCTRL_SEL_MASK (0x4000U) 9448 #define SYSCON_FROCTRL_SEL_SHIFT (14U) 9449 /*! SEL - Select the fro_hf output frequency. This bit can only be changed by software when the 9450 * WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only. 9451 * 0b0..48 MHz 9452 * 0b1..96 MHz 9453 */ 9454 #define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) 9455 #define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) 9456 #define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) 9457 /*! FREQTRIM - Frequency trim. Boot code configures this to a device-specific factory trim value for 9458 * the 96 MHz FRO. If USBCLKADJ = 1, this field is read-only and provides the value resulting 9459 * from USB rate adjustment. See the USBMODCFG flag regarding reading this field. Application code 9460 * may adjust this field when USBCLKADJ = 0. A single step of FREQTRIM is roughly equivalent to 9461 * 0.1% of the selected FRO frequency. 9462 */ 9463 #define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) 9464 #define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) 9465 #define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) 9466 /*! USBCLKADJ - USB clock adjust mode. 9467 * 0b0..Normal operation. 9468 * 0b1..Automatic USB rate adjustment mode. If the USB FS device peripheral is enabled and connected to a USB 9469 * host, it provides clock adjustment information to the FRO based on SOF packets. USB rate adjustment requires 9470 * a number of cycles to take place. the USBMODCHG bit (see below) indicates when initial adjustment is 9471 * complete, and when later adjustments are in progress. software must not alter TRIM and FREQTRIM while USBCLKADJ 9472 * = 1. see USBCLKADJ usage notes below this table. 9473 */ 9474 #define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) 9475 #define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) 9476 #define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) 9477 /*! USBMODCHG - USB Mode value Change flag. When 1, indicates that the USB trim is currently being 9478 * updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at 9479 * most once per millisecond. 9480 */ 9481 #define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) 9482 #define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) 9483 #define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) 9484 /*! HSPDCLK - High speed clock disable. Allows disabling the highs-speed FRO output if it is not needed. 9485 * 0b0..The high-speed FRO output is disabled. 9486 * 0b1..The selected high-speed FRO output (48 MHz or 96 MHz) is enabled. 9487 */ 9488 #define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) 9489 #define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) 9490 #define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) 9491 /*! WRTRIM - Write Trim value. Must be written to 1 to modify the SEL or TRIM fields, during the 9492 * same write. This bit always reads as 0. 9493 */ 9494 #define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) 9495 /*! @} */ 9496 9497 /*! @name WDTOSCCTRL - Watchdog oscillator control */ 9498 /*! @{ */ 9499 #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) 9500 #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) 9501 /*! DIVSEL - Divider select. Selects the value of the divider that adjusts the output of the 9502 * oscillator. 0x00 = divide by 2 0x01 = divide by 4 0x02 = divide by 6 up to 0x1E = divide by 62 0x1F = 9503 * divide by 64 9504 */ 9505 #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) 9506 #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) 9507 #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) 9508 /*! FREQSEL - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when 9509 * watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 9510 * 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 = 1.5 MHz 0x0A = 1.6 MHz 0x0B 9511 * = 1.7 MHz 0x0C = 1.8 MHz 0x0D = 1.9 MHz 0x0E = 2.0 MHz 0x0F = 2.05 MHz 0x10 = 2.1 MHz 0x11 = 9512 * 2.2 MHz 0x12 = 2.25 MHz 0x13 = 2.3 MHz 0x14 = 2.4 MHz 0x15 = 2.45 MHz 0x16 = 2.5 MHz 0x17 = 2.6 9513 * MHz 0x18 = 2.65 MHz 0x19 = 2.7 MHz 0x1A = 2.8 MHz 0x1B = 2.85 MHz 0x1C = 2.9 MHz 0x1D = 2.95 9514 * MHz 0x1E = 3.0 MHz 0x1F = 3.05 MHz 9515 */ 9516 #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) 9517 /*! @} */ 9518 9519 /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ 9520 /*! @{ */ 9521 #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) 9522 #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) 9523 /*! EN - RTC 32 kHz clock enable. 9524 * 0b0..Disabled. RTC clock off. 9525 * 0b1..Enabled. RTC clock on. 9526 */ 9527 #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) 9528 /*! @} */ 9529 9530 /*! @name SYSPLLCTRL - PLL control */ 9531 /*! @{ */ 9532 #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) 9533 #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) 9534 /*! SELR - Bandwidth select R value 9535 */ 9536 #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) 9537 #define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) 9538 #define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) 9539 /*! SELI - Bandwidth select I value. 9540 */ 9541 #define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) 9542 #define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) 9543 #define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) 9544 /*! SELP - Bandwidth select P value 9545 */ 9546 #define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) 9547 #define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) 9548 #define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) 9549 /*! BYPASS - PLL bypass control. 9550 * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers. 9551 * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default). 9552 */ 9553 #define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) 9554 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) 9555 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) 9556 /*! BYPASSCCODIV2 - Bypass feedback clock divide by 2. 9557 * 0b0..Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide. 9558 * 0b1..Bypass. The CCO feedback clock is divided only by the programmed M divide. 9559 */ 9560 #define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) 9561 #define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) 9562 #define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) 9563 /*! UPLIMOFF - Disable upper frequency limiter. 9564 * 0b0..Normal mode. 9565 * 0b1..Upper frequency limiter disabled. 9566 */ 9567 #define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) 9568 #define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) 9569 #define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) 9570 /*! BANDSEL - PLL filter control. Set this bit to one when the spread spectrum controller is 9571 * disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. 9572 * 0b0..SSCG control. The PLL filter uses the parameters derived from the spread spectrum controller. 9573 * 0b1..MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants. 9574 */ 9575 #define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) 9576 #define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) 9577 #define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) 9578 /*! DIRECTI - PLL0 direct input enable 9579 * 0b0..Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO. 9580 * 0b1..Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO input. 9581 */ 9582 #define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) 9583 #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) 9584 #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) 9585 /*! DIRECTO - PLL0 direct output enable. 9586 * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output. 9587 * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. 9588 */ 9589 #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) 9590 /*! @} */ 9591 9592 /*! @name SYSPLLSTAT - PLL status */ 9593 /*! @{ */ 9594 #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) 9595 #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) 9596 /*! LOCK - PLL0 lock indicator 9597 */ 9598 #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) 9599 /*! @} */ 9600 9601 /*! @name SYSPLLNDEC - PLL N decoder */ 9602 /*! @{ */ 9603 #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) 9604 #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) 9605 /*! NDEC - Decoded N-divider coefficient value. 9606 */ 9607 #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) 9608 #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) 9609 #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) 9610 /*! NREQ - NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the 9611 * PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and 9612 * back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed. 9613 */ 9614 #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) 9615 /*! @} */ 9616 9617 /*! @name SYSPLLPDEC - PLL P decoder */ 9618 /*! @{ */ 9619 #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) 9620 #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) 9621 /*! PDEC - Decoded P-divider coefficient value. 9622 */ 9623 #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) 9624 #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) 9625 #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) 9626 /*! PREQ - PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the 9627 * PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and 9628 * back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed. 9629 */ 9630 #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) 9631 /*! @} */ 9632 9633 /*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ 9634 /*! @{ */ 9635 #define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) 9636 #define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) 9637 /*! MDEC - Decoded M-divider coefficient value. 9638 */ 9639 #define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) 9640 #define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) 9641 #define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) 9642 /*! MREQ - MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the 9643 * PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and 9644 * back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed. 9645 */ 9646 #define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) 9647 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) 9648 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) 9649 /*! SEL_EXT - Select spread spectrum mode. Selects the source of the feedback divider value. For 9650 * normal mode, this must be the value from the MDEC field in this register. For spread spectrum 9651 * mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. 9652 */ 9653 #define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) 9654 /*! @} */ 9655 9656 /*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ 9657 /*! @{ */ 9658 #define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) 9659 #define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) 9660 /*! MD - M- divider value with fraction. MD[18:11]: integer portion of the feedback divider value. 9661 * MD[10:0]: fractional portion of the feedback divider value. In fractional mode, fcco = (2 - 9662 * BYPASSCCODIV2) x (MD x 2^-11) x Fref 9663 */ 9664 #define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) 9665 #define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) 9666 #define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) 9667 /*! MDREQ - MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. 9668 * This bit is cleared when the load is complete 9669 */ 9670 #define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) 9671 #define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) 9672 #define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) 9673 /*! MF - Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 9674 * 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 9675 * kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm _ 32.3 - 64.5 kHz) 0b101 => 9676 * Nss = 32 (fm _ 62.5- 125 kHz) 0b110 => Nss _ 24 (fm _ 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm 9677 * _ 125- 250 kHz) 9678 */ 9679 #define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) 9680 #define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) 9681 #define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) 9682 /*! MR - Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = 9683 * k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => 9684 * k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8 9685 */ 9686 #define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) 9687 #define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) 9688 #define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) 9689 /*! MC - Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of 9690 * the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency 9691 * spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation 9692 */ 9693 #define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) 9694 #define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) 9695 #define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) 9696 /*! PD - Spread spectrum power-down. 9697 * 0b0..Enabled. Spread spectrum controller is enabled 9698 * 0b1..Disabled. Spread spectrum controller is disabled. 9699 */ 9700 #define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) 9701 #define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) 9702 #define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) 9703 /*! DITHER - Select modulation frequency. 9704 * 0b0..Fixed. Fixed modulation frequency. 9705 * 0b1..Dither. Randomly dither between two modulation frequencies. 9706 */ 9707 #define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) 9708 /*! @} */ 9709 9710 /*! @name PDSLEEPCFG - Sleep configuration register n */ 9711 /*! @{ */ 9712 #define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) 9713 #define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) 9714 /*! PD_SLEEP - See bit descriptions in the PDRUNCFGn register. 9715 */ 9716 #define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) 9717 /*! @} */ 9718 9719 /* The count of SYSCON_PDSLEEPCFG */ 9720 #define SYSCON_PDSLEEPCFG_COUNT (2U) 9721 9722 /*! @name PDRUNCFG - Power configuration register n */ 9723 /*! @{ */ 9724 #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) 9725 #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) 9726 /*! PDEN_FRO - FRO oscillator. 0 = Powered; 1 = Powered down. 9727 */ 9728 #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) 9729 #define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U) 9730 #define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U) 9731 /*! PD_FLASH - Part of flash power control. 9732 */ 9733 #define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK) 9734 #define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) 9735 #define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) 9736 /*! PDEN_TS - Temp sensor. 0 = Powered; 1 = Powered down. 9737 */ 9738 #define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) 9739 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) 9740 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) 9741 /*! PDEN_BOD_RST - Brown-out Detect reset. 0 = Powered; 1 = Powered down. 9742 */ 9743 #define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) 9744 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) 9745 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) 9746 /*! PDEN_BOD_INTR - Brown-out Detect interrupt. 0 = Powered; 1 = Powered down. 9747 */ 9748 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) 9749 #define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) 9750 #define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) 9751 /*! PDEN_ADC0 - ADC0. 0 = Powered; 1 = Powered down. 9752 */ 9753 #define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) 9754 #define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U) 9755 #define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U) 9756 /*! PD_VDDFLASH - Part of flash power control. 9757 */ 9758 #define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK) 9759 #define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U) 9760 #define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U) 9761 /*! LP_VDDFLASH - Part of flash power control. 9762 */ 9763 #define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK) 9764 #define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) 9765 #define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) 9766 /*! PDEN_SRAM0 - SRAM0. 0 = Powered; 1 = Powered down. 9767 */ 9768 #define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) 9769 #define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U) 9770 #define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U) 9771 /*! PDEN_SRAM1 - SRAM1. 0 = Powered; 1 = Powered down. 9772 */ 9773 #define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK) 9774 #define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U) 9775 #define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U) 9776 /*! PDEN_SRAM2 - SRAM2. 0 = Powered; 1 = Powered down. 9777 */ 9778 #define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) 9779 #define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) 9780 #define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) 9781 /*! PDEN_SRAMX - SRAMX. 0 = Powered; 1 = Powered down. 9782 */ 9783 #define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) 9784 #define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) 9785 #define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) 9786 /*! PDEN_ROM - ROM. 0 = Powered; 1 = Powered down. 9787 */ 9788 #define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) 9789 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U) 9790 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U) 9791 /*! PD_VDDHV_ENA - Part of flash power control. 9792 */ 9793 #define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK) 9794 #define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) 9795 #define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) 9796 /*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down. 9797 */ 9798 #define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) 9799 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) 9800 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) 9801 /*! PDEN_WDT_OSC - Watchdog oscillator. 0 = Powered; 1 = Powered down. 9802 */ 9803 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) 9804 #define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) 9805 #define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) 9806 /*! PDEN_USB_PHY - USB pin interface. 0 = Powered; 1 = Powered down. 9807 */ 9808 #define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) 9809 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) 9810 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) 9811 /*! PDEN_SYS_PLL - PLL0. 0 = Powered; 1 = Powered down. 9812 */ 9813 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) 9814 #define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) 9815 #define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) 9816 /*! PDEN_VREFP - Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down. 9817 */ 9818 #define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) 9819 #define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U) 9820 #define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U) 9821 /*! PD_FLASH_BG - Part of flash power control. 9822 */ 9823 #define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK) 9824 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U) 9825 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U) 9826 /*! PD_ALT_FLASH_IBG - Part of flash power control. 9827 */ 9828 #define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK) 9829 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) 9830 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) 9831 /*! SEL_ALT_FLASH_IBG - Part of flash power control. 9832 */ 9833 #define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) 9834 /*! @} */ 9835 9836 /* The count of SYSCON_PDRUNCFG */ 9837 #define SYSCON_PDRUNCFG_COUNT (2U) 9838 9839 /*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ 9840 /*! @{ */ 9841 #define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) 9842 #define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) 9843 /*! PD_SET - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG 9844 * register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are 9845 * reserved and only zeroes should be written to them. 9846 */ 9847 #define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) 9848 /*! @} */ 9849 9850 /* The count of SYSCON_PDRUNCFGSET */ 9851 #define SYSCON_PDRUNCFGSET_COUNT (2U) 9852 9853 /*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ 9854 /*! @{ */ 9855 #define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) 9856 #define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) 9857 /*! PD_CLR - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG 9858 * register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are 9859 * reserved and only zeroes should be written to them. 9860 */ 9861 #define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) 9862 /*! @} */ 9863 9864 /* The count of SYSCON_PDRUNCFGCLR */ 9865 #define SYSCON_PDRUNCFGCLR_COUNT (2U) 9866 9867 /*! @name STARTERP - Start logic n wake-up enable register */ 9868 /*! @{ */ 9869 #define SYSCON_STARTERP_PINT4_MASK (0x1U) 9870 #define SYSCON_STARTERP_PINT4_SHIFT (0U) 9871 /*! PINT4 - GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9872 */ 9873 #define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) 9874 #define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) 9875 #define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) 9876 /*! WDT_BOD - WWDT and BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9877 */ 9878 #define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) 9879 #define SYSCON_STARTERP_DMA0_MASK (0x2U) 9880 #define SYSCON_STARTERP_DMA0_SHIFT (1U) 9881 /*! DMA0 - DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode 9882 * only since the peripheral clock must be running for it to function. 9883 */ 9884 #define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) 9885 #define SYSCON_STARTERP_PINT5_MASK (0x2U) 9886 #define SYSCON_STARTERP_PINT5_SHIFT (1U) 9887 /*! PINT5 - GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9888 */ 9889 #define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) 9890 #define SYSCON_STARTERP_GINT0_MASK (0x4U) 9891 #define SYSCON_STARTERP_GINT0_SHIFT (2U) 9892 /*! GINT0 - Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9893 */ 9894 #define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) 9895 #define SYSCON_STARTERP_PINT6_MASK (0x4U) 9896 #define SYSCON_STARTERP_PINT6_SHIFT (2U) 9897 /*! PINT6 - GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9898 */ 9899 #define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK) 9900 #define SYSCON_STARTERP_GINT1_MASK (0x8U) 9901 #define SYSCON_STARTERP_GINT1_SHIFT (3U) 9902 /*! GINT1 - Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9903 */ 9904 #define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK) 9905 #define SYSCON_STARTERP_PINT7_MASK (0x8U) 9906 #define SYSCON_STARTERP_PINT7_SHIFT (3U) 9907 /*! PINT7 - GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9908 */ 9909 #define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK) 9910 #define SYSCON_STARTERP_CTIMER2_MASK (0x10U) 9911 #define SYSCON_STARTERP_CTIMER2_SHIFT (4U) 9912 /*! CTIMER2 - Standard counter/timer CTIMER2 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9913 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9914 */ 9915 #define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK) 9916 #define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) 9917 #define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) 9918 /*! PIN_INT0 - GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9919 */ 9920 #define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) 9921 #define SYSCON_STARTERP_CTIMER4_MASK (0x20U) 9922 #define SYSCON_STARTERP_CTIMER4_SHIFT (5U) 9923 /*! CTIMER4 - Standard counter/timer CTIMER4 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9924 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9925 */ 9926 #define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) 9927 #define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) 9928 #define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) 9929 /*! PIN_INT1 - GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9930 */ 9931 #define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) 9932 #define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) 9933 #define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) 9934 /*! PIN_INT2 - GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9935 */ 9936 #define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) 9937 #define SYSCON_STARTERP_PIN_INT3_MASK (0x80U) 9938 #define SYSCON_STARTERP_PIN_INT3_SHIFT (7U) 9939 /*! PIN_INT3 - GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match. 9940 */ 9941 #define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK) 9942 #define SYSCON_STARTERP_UTICK0_MASK (0x100U) 9943 #define SYSCON_STARTERP_UTICK0_SHIFT (8U) 9944 /*! UTICK0 - Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9945 */ 9946 #define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK) 9947 #define SYSCON_STARTERP_MRT0_MASK (0x200U) 9948 #define SYSCON_STARTERP_MRT0_SHIFT (9U) 9949 /*! MRT0 - Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in 9950 * sleep mode only since the peripheral clock must be running for it to function. 9951 */ 9952 #define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK) 9953 #define SYSCON_STARTERP_CTIMER0_MASK (0x400U) 9954 #define SYSCON_STARTERP_CTIMER0_SHIFT (10U) 9955 /*! CTIMER0 - Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9956 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9957 */ 9958 #define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK) 9959 #define SYSCON_STARTERP_CTIMER1_MASK (0x800U) 9960 #define SYSCON_STARTERP_CTIMER1_SHIFT (11U) 9961 /*! CTIMER1 - Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9962 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9963 */ 9964 #define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK) 9965 #define SYSCON_STARTERP_SCT0_MASK (0x1000U) 9966 #define SYSCON_STARTERP_SCT0_SHIFT (12U) 9967 /*! SCT0 - SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only 9968 * since the peripheral clock must be running for it to function. 9969 */ 9970 #define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK) 9971 #define SYSCON_STARTERP_CTIMER3_MASK (0x2000U) 9972 #define SYSCON_STARTERP_CTIMER3_SHIFT (13U) 9973 /*! CTIMER3 - Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up 9974 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 9975 */ 9976 #define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK) 9977 #define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U) 9978 #define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U) 9979 /*! FLEXCOMM0 - Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9980 */ 9981 #define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK) 9982 #define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U) 9983 #define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U) 9984 /*! FLEXCOMM1 - Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9985 */ 9986 #define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK) 9987 #define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U) 9988 #define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U) 9989 /*! FLEXCOMM2 - Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9990 */ 9991 #define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK) 9992 #define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U) 9993 #define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U) 9994 /*! FLEXCOMM3 - Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 9995 */ 9996 #define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK) 9997 #define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U) 9998 #define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U) 9999 /*! FLEXCOMM4 - Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10000 */ 10001 #define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK) 10002 #define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U) 10003 #define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U) 10004 /*! FLEXCOMM5 - Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10005 */ 10006 #define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK) 10007 #define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U) 10008 #define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U) 10009 /*! FLEXCOMM6 - Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10010 */ 10011 #define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK) 10012 #define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U) 10013 #define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U) 10014 /*! FLEXCOMM7 - Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10015 */ 10016 #define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK) 10017 #define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U) 10018 #define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U) 10019 /*! ADC0_SEQA - ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up 10020 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 10021 */ 10022 #define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK) 10023 #define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U) 10024 #define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U) 10025 /*! ADC0_SEQB - ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up 10026 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function. 10027 */ 10028 #define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK) 10029 #define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U) 10030 #define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U) 10031 /*! ADC0_THCMP - ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up 10032 * enabled.Typically used in sleep mode only since the peripheral clock must be running for it to 10033 * function. 10034 */ 10035 #define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK) 10036 #define SYSCON_STARTERP_DMIC0_MASK (0x2000000U) 10037 #define SYSCON_STARTERP_DMIC0_SHIFT (25U) 10038 /*! DMIC0 - Digital microphone interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10039 */ 10040 #define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK) 10041 #define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U) 10042 #define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U) 10043 /*! USB0_NEEDCLK - USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10044 */ 10045 #define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK) 10046 #define SYSCON_STARTERP_USB0_MASK (0x10000000U) 10047 #define SYSCON_STARTERP_USB0_SHIFT (28U) 10048 /*! USB0 - USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. 10049 */ 10050 #define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK) 10051 #define SYSCON_STARTERP_RTC_MASK (0x20000000U) 10052 #define SYSCON_STARTERP_RTC_SHIFT (29U) 10053 /*! RTC - RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled. 10054 */ 10055 #define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK) 10056 #define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) 10057 #define SYSCON_STARTERP_MAILBOX_SHIFT (31U) 10058 /*! MAILBOX - Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU 10059 * must be running in order for a mailbox interrupt to occur. Present on selected devices. 10060 */ 10061 #define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) 10062 /*! @} */ 10063 10064 /* The count of SYSCON_STARTERP */ 10065 #define SYSCON_STARTERP_COUNT (2U) 10066 10067 /*! @name STARTERSET - Set bits in STARTERn */ 10068 /*! @{ */ 10069 #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) 10070 #define SYSCON_STARTERSET_START_SET_SHIFT (0U) 10071 /*! START_SET - Writing ones to this register sets the corresponding bit or bits in the STARTERn 10072 * register, if they are implemented. Bits that do not correspond to defined bits in STARTERn are 10073 * reserved and only zeroes should be written to them. 10074 */ 10075 #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) 10076 /*! @} */ 10077 10078 /* The count of SYSCON_STARTERSET */ 10079 #define SYSCON_STARTERSET_COUNT (2U) 10080 10081 /*! @name STARTERCLR - Clear bits in STARTERn */ 10082 /*! @{ */ 10083 #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) 10084 #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) 10085 /*! START_CLR - Writing ones to this register clears the corresponding bit or bits in the STARTERn 10086 * register, if they are implemented. Bits that do not correspond to defined bits in STARTERn are 10087 * reserved and only zeroes should be written to them. 10088 */ 10089 #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) 10090 /*! @} */ 10091 10092 /* The count of SYSCON_STARTERCLR */ 10093 #define SYSCON_STARTERCLR_COUNT (2U) 10094 10095 /*! @name HWWAKE - Configures special cases of hardware wake-up */ 10096 /*! @{ */ 10097 #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) 10098 #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) 10099 /*! FORCEWAKE - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1, 10100 * clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and 10101 * Power-down modes. This is intended to allow a coprocessor to continue operating while the main 10102 * CPU(s) are shut down. 10103 */ 10104 #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) 10105 #define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) 10106 #define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) 10107 /*! FCWAKE - Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own 10108 * TXLVL will cause peripheral clocking to wake up temporarily while the related status is 10109 * asserted. 10110 */ 10111 #define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) 10112 #define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) 10113 #define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) 10114 /*! WAKEDMIC - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the 10115 * level specified by TRIGLVL of either channel will cause peripheral clocking to wake up 10116 * temporarily while the related status is asserted. 10117 */ 10118 #define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) 10119 #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) 10120 #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) 10121 /*! WAKEDMA - Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running 10122 * until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to 10123 * prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but 10124 * before DMA has completed its related activity. 10125 */ 10126 #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) 10127 /*! @} */ 10128 10129 /*! @name CPUCTRL - CPU Control for multiple processors */ 10130 /*! @{ */ 10131 #define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) 10132 #define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) 10133 /*! MASTERCPU - Indicates which CPU is considered the master. This is factory set assign the 10134 * Cortex-M4 as the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit 10135 * or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly 10136 * following device reset, then goes back to sleep until activated by the master CPU. 10137 * 0b0..M0+. Cortex-M0+ is the master CPU. 10138 * 0b1..M4. Cortex-M4 is the master CPU. 10139 */ 10140 #define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) 10141 #define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) 10142 #define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) 10143 /*! CM4CLKEN - Cortex-M4 clock enable 10144 * 0b0..Disabled. The Cortex-M4 clock is not enabled 10145 * 0b1..Enabled. The Cortex-M4 clock is enabled. 10146 */ 10147 #define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) 10148 #define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) 10149 #define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) 10150 /*! CM0CLKEN - Cortex-M0+ clock enable 10151 * 0b0..Disabled. The Cortex-M0+ clock is not enabled. 10152 * 0b1..Enabled. The Cortex-M0+ clock is enabled. 10153 */ 10154 #define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) 10155 #define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) 10156 #define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) 10157 /*! CM4RSTEN - Cortex-M4 reset. 10158 * 0b0..Disabled. The Cortex-M4 is not being reset. 10159 * 0b1..Enabled. The Cortex-M4 is being reset. 10160 */ 10161 #define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) 10162 #define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) 10163 #define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) 10164 /*! CM0RSTEN - Cortex-M0+ reset. 10165 * 0b0..Disabled. The Cortex-M0+ is not being reset. 10166 * 0b1..Enabled. The Cortex-M0+ is being reset. 10167 */ 10168 #define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) 10169 #define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) 10170 #define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) 10171 /*! POWERCPU - Identifies the owner of reduced power mode control: which CPU can cause the device to 10172 * enter Deep Sleep, Power-down, and Deep Power-down modes. 10173 * 0b0..M0+. Cortex-M0+ is the owner of reduced power mode control. 10174 * 0b1..M4. Cortex-M4 is the owner of reduced power mode control. 10175 */ 10176 #define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) 10177 /*! @} */ 10178 10179 /*! @name CPBOOT - Coprocessor Boot Address */ 10180 /*! @{ */ 10181 #define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) 10182 #define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) 10183 /*! BOOTADDR - Slave processor boot address 10184 */ 10185 #define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) 10186 /*! @} */ 10187 10188 /*! @name CPSTACK - Coprocessor Stack Address */ 10189 /*! @{ */ 10190 #define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) 10191 #define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) 10192 /*! STACKADDR - Slave processor stack address 10193 */ 10194 #define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) 10195 /*! @} */ 10196 10197 /*! @name CPSTAT - Coprocessor Status */ 10198 /*! @{ */ 10199 #define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) 10200 #define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) 10201 /*! CM4SLEEPING - When 1, the Cortex-M4 CPU is sleeping 10202 */ 10203 #define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) 10204 #define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U) 10205 #define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U) 10206 /*! CM0SLEEPING - When 1, the Cortex-M0+ CPU is sleeping 10207 */ 10208 #define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK) 10209 #define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U) 10210 #define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U) 10211 /*! CM4LOCKUP - When 1, the Cortex-M4 CPU is in lockup 10212 */ 10213 #define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK) 10214 #define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) 10215 #define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) 10216 /*! CM0LOCKUP - When 1, the Cortex-M0+ CPU is in lockup. 10217 */ 10218 #define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) 10219 /*! @} */ 10220 10221 /*! @name AUTOCGOR - Auto Clock-Gate Override Register */ 10222 /*! @{ */ 10223 #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) 10224 #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) 10225 /*! RAM0X - When 1, automatic clock gating for RAMX and RAM0 are turned off. 10226 */ 10227 #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) 10228 #define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) 10229 #define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) 10230 /*! RAM1 - When 1, automatic clock gating for RAM1 is turned off. 10231 */ 10232 #define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) 10233 #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) 10234 #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) 10235 /*! RAM2 - When 1, automatic clock gating for RAM2 is turned off. 10236 */ 10237 #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) 10238 /*! @} */ 10239 10240 /*! @name JTAGIDCODE - JTAG ID code register */ 10241 /*! @{ */ 10242 #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) 10243 #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) 10244 /*! JTAGID - JTAG ID code. 10245 */ 10246 #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) 10247 /*! @} */ 10248 10249 /*! @name DEVICE_ID0 - Part ID register */ 10250 /*! @{ */ 10251 #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) 10252 #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) 10253 /*! PARTID - Part ID 10254 */ 10255 #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) 10256 /*! @} */ 10257 10258 /*! @name DEVICE_ID1 - Boot ROM and die revision register */ 10259 /*! @{ */ 10260 #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) 10261 #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) 10262 /*! REVID - Revision. 10263 */ 10264 #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) 10265 /*! @} */ 10266 10267 /*! @name BODCTRL - Brown-Out Detect control */ 10268 /*! @{ */ 10269 #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) 10270 #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) 10271 /*! BODRSTLEV - BOD reset level 10272 * 0b00..Level 0: 1.5 V 10273 * 0b01..Level 1: 1.85 V 10274 * 0b10..Level 2: 2.0 V 10275 * 0b11..Level 3: 2.3 V 10276 */ 10277 #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) 10278 #define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) 10279 #define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) 10280 /*! BODRSTENA - BOD reset enable 10281 * 0b0..Disable reset function. 10282 * 0b1..Enable reset function. 10283 */ 10284 #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) 10285 #define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) 10286 #define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) 10287 /*! BODINTLEV - BOD interrupt level 10288 * 0b00..Level 0: 2.05 V 10289 * 0b01..Level 1: 2.45 V 10290 * 0b10..Level 2: 2.75 V 10291 * 0b11..Level 3: 3.05 V 10292 */ 10293 #define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) 10294 #define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) 10295 #define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) 10296 /*! BODINTENA - BOD interrupt enable 10297 * 0b0..Disable interrupt function. 10298 * 0b1..Enable interrupt function. 10299 */ 10300 #define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) 10301 #define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) 10302 #define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) 10303 /*! BODRSTSTAT - BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit. 10304 */ 10305 #define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) 10306 #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) 10307 #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) 10308 /*! BODINTSTAT - BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit. 10309 */ 10310 #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) 10311 /*! @} */ 10312 10313 10314 /*! 10315 * @} 10316 */ /* end of group SYSCON_Register_Masks */ 10317 10318 10319 /* SYSCON - Peripheral instance base addresses */ 10320 /** Peripheral SYSCON base address */ 10321 #define SYSCON_BASE (0x40000000u) 10322 /** Peripheral SYSCON base pointer */ 10323 #define SYSCON ((SYSCON_Type *)SYSCON_BASE) 10324 /** Array initializer of SYSCON peripheral base addresses */ 10325 #define SYSCON_BASE_ADDRS { SYSCON_BASE } 10326 /** Array initializer of SYSCON peripheral base pointers */ 10327 #define SYSCON_BASE_PTRS { SYSCON } 10328 10329 /*! 10330 * @} 10331 */ /* end of group SYSCON_Peripheral_Access_Layer */ 10332 10333 10334 /* ---------------------------------------------------------------------------- 10335 -- USART Peripheral Access Layer 10336 ---------------------------------------------------------------------------- */ 10337 10338 /*! 10339 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer 10340 * @{ 10341 */ 10342 10343 /** USART - Register Layout Typedef */ 10344 typedef struct { 10345 __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ 10346 __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ 10347 __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ 10348 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ 10349 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ 10350 uint8_t RESERVED_0[12]; 10351 __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ 10352 __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ 10353 __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ 10354 __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ 10355 uint8_t RESERVED_1[3536]; 10356 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ 10357 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ 10358 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ 10359 uint8_t RESERVED_2[4]; 10360 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ 10361 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ 10362 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ 10363 uint8_t RESERVED_3[4]; 10364 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ 10365 uint8_t RESERVED_4[12]; 10366 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ 10367 uint8_t RESERVED_5[12]; 10368 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ 10369 } USART_Type; 10370 10371 /* ---------------------------------------------------------------------------- 10372 -- USART Register Masks 10373 ---------------------------------------------------------------------------- */ 10374 10375 /*! 10376 * @addtogroup USART_Register_Masks USART Register Masks 10377 * @{ 10378 */ 10379 10380 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ 10381 /*! @{ */ 10382 #define USART_CFG_ENABLE_MASK (0x1U) 10383 #define USART_CFG_ENABLE_SHIFT (0U) 10384 /*! ENABLE - USART Enable. 10385 * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, 10386 * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control 10387 * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the 10388 * transmitter has been reset and is therefore available. 10389 * 0b1..Enabled. The USART is enabled for operation. 10390 */ 10391 #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) 10392 #define USART_CFG_DATALEN_MASK (0xCU) 10393 #define USART_CFG_DATALEN_SHIFT (2U) 10394 /*! DATALEN - Selects the data size for the USART. 10395 * 0b00..7 bit Data length. 10396 * 0b01..8 bit Data length. 10397 * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 10398 * 0b11..Reserved. 10399 */ 10400 #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) 10401 #define USART_CFG_PARITYSEL_MASK (0x30U) 10402 #define USART_CFG_PARITYSEL_SHIFT (4U) 10403 /*! PARITYSEL - Selects what type of parity is used by the USART. 10404 * 0b00..No parity. 10405 * 0b01..Reserved. 10406 * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, 10407 * and the number of 1s in a received character is expected to be even. 10408 * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, 10409 * and the number of 1s in a received character is expected to be odd. 10410 */ 10411 #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) 10412 #define USART_CFG_STOPLEN_MASK (0x40U) 10413 #define USART_CFG_STOPLEN_SHIFT (6U) 10414 /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 10415 * 0b0..1 stop bit. 10416 * 0b1..2 stop bits. This setting should only be used for asynchronous communication. 10417 */ 10418 #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) 10419 #define USART_CFG_MODE32K_MASK (0x80U) 10420 #define USART_CFG_MODE32K_SHIFT (7U) 10421 /*! MODE32K - Selects standard or 32 kHz clocking mode. 10422 * 0b0..Disabled. USART uses standard clocking. 10423 * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 10424 */ 10425 #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) 10426 #define USART_CFG_LINMODE_MASK (0x100U) 10427 #define USART_CFG_LINMODE_SHIFT (8U) 10428 /*! LINMODE - LIN break mode enable. 10429 * 0b0..Disabled. Break detect and generate is configured for normal operation. 10430 * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. 10431 */ 10432 #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) 10433 #define USART_CFG_CTSEN_MASK (0x200U) 10434 #define USART_CFG_CTSEN_SHIFT (9U) 10435 /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input 10436 * pin, or from the USART's own RTS if loopback mode is enabled. 10437 * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. 10438 * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 10439 */ 10440 #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) 10441 #define USART_CFG_SYNCEN_MASK (0x800U) 10442 #define USART_CFG_SYNCEN_SHIFT (11U) 10443 /*! SYNCEN - Selects synchronous or asynchronous operation. 10444 * 0b0..Asynchronous mode. 10445 * 0b1..Synchronous mode. 10446 */ 10447 #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) 10448 #define USART_CFG_CLKPOL_MASK (0x1000U) 10449 #define USART_CFG_CLKPOL_SHIFT (12U) 10450 /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. 10451 * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. 10452 * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. 10453 */ 10454 #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) 10455 #define USART_CFG_SYNCMST_MASK (0x4000U) 10456 #define USART_CFG_SYNCMST_SHIFT (14U) 10457 /*! SYNCMST - Synchronous mode Master select. 10458 * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. 10459 * 0b1..Master. When synchronous mode is enabled, the USART is a master. 10460 */ 10461 #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) 10462 #define USART_CFG_LOOP_MASK (0x8000U) 10463 #define USART_CFG_LOOP_SHIFT (15U) 10464 /*! LOOP - Selects data loopback mode. 10465 * 0b0..Normal operation. 10466 * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial 10467 * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD 10468 * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device 10469 * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 10470 */ 10471 #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) 10472 #define USART_CFG_IOMODE_MASK (0x10000U) 10473 #define USART_CFG_IOMODE_SHIFT (16U) 10474 /*! IOMODE - I/O output mode. 10475 * 0b0..Standard. USART output and input operate in standard fashion. 10476 * 0b1..IrDA. USART output and input operate in IrDA mode. 10477 */ 10478 #define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK) 10479 #define USART_CFG_OETA_MASK (0x40000U) 10480 #define USART_CFG_OETA_SHIFT (18U) 10481 /*! OETA - Output Enable Turnaround time enable for RS-485 operation. 10482 * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 10483 * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the 10484 * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins 10485 * before it is deasserted. 10486 */ 10487 #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) 10488 #define USART_CFG_AUTOADDR_MASK (0x80000U) 10489 #define USART_CFG_AUTOADDR_SHIFT (19U) 10490 /*! AUTOADDR - Automatic Address matching enable. 10491 * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the 10492 * possibility of versatile addressing (e.g. respond to more than one address). 10493 * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in 10494 * the ADDR register as the address to match. 10495 */ 10496 #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) 10497 #define USART_CFG_OESEL_MASK (0x100000U) 10498 #define USART_CFG_OESEL_SHIFT (20U) 10499 /*! OESEL - Output Enable Select. 10500 * 0b0..Standard. The RTS signal is used as the standard flow control function. 10501 * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 10502 */ 10503 #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) 10504 #define USART_CFG_OEPOL_MASK (0x200000U) 10505 #define USART_CFG_OEPOL_SHIFT (21U) 10506 /*! OEPOL - Output Enable Polarity. 10507 * 0b0..Low. If selected by OESEL, the output enable is active low. 10508 * 0b1..High. If selected by OESEL, the output enable is active high. 10509 */ 10510 #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) 10511 #define USART_CFG_RXPOL_MASK (0x400000U) 10512 #define USART_CFG_RXPOL_SHIFT (22U) 10513 /*! RXPOL - Receive data polarity. 10514 * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start 10515 * bit is 0, data is not inverted, and the stop bit is 1. 10516 * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 10517 * 0, start bit is 1, data is inverted, and the stop bit is 0. 10518 */ 10519 #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) 10520 #define USART_CFG_TXPOL_MASK (0x800000U) 10521 #define USART_CFG_TXPOL_SHIFT (23U) 10522 /*! TXPOL - Transmit data polarity. 10523 * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 10524 * 0, data is not inverted, and the stop bit is 1. 10525 * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value 10526 * is 0, start bit is 1, data is inverted, and the stop bit is 0. 10527 */ 10528 #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) 10529 /*! @} */ 10530 10531 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ 10532 /*! @{ */ 10533 #define USART_CTL_TXBRKEN_MASK (0x2U) 10534 #define USART_CTL_TXBRKEN_SHIFT (1U) 10535 /*! TXBRKEN - Break Enable. 10536 * 0b0..Normal operation. 10537 * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit 10538 * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the 10539 * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled 10540 * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 10541 */ 10542 #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) 10543 #define USART_CTL_ADDRDET_MASK (0x4U) 10544 #define USART_CTL_ADDRDET_SHIFT (2U) 10545 /*! ADDRDET - Enable address detect mode. 10546 * 0b0..Disabled. The USART presents all incoming data. 10547 * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data 10548 * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, 10549 * generating a received data interrupt. Software can then check the data to see if this is an address that 10550 * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled 10551 * normally. 10552 */ 10553 #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) 10554 #define USART_CTL_TXDIS_MASK (0x40U) 10555 #define USART_CTL_TXDIS_SHIFT (6U) 10556 /*! TXDIS - Transmit Disable. 10557 * 0b0..Not disabled. USART transmitter is not disabled. 10558 * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This 10559 * feature can be used to facilitate software flow control. 10560 */ 10561 #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) 10562 #define USART_CTL_CC_MASK (0x100U) 10563 #define USART_CTL_CC_SHIFT (8U) 10564 /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 10565 * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to 10566 * complete a character that is being received. 10567 * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on 10568 * Un_RxD independently from transmission on Un_TXD). 10569 */ 10570 #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) 10571 #define USART_CTL_CLRCCONRX_MASK (0x200U) 10572 #define USART_CTL_CLRCCONRX_SHIFT (9U) 10573 /*! CLRCCONRX - Clear Continuous Clock. 10574 * 0b0..No effect. No effect on the CC bit. 10575 * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 10576 */ 10577 #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) 10578 #define USART_CTL_AUTOBAUD_MASK (0x10000U) 10579 #define USART_CTL_AUTOBAUD_SHIFT (16U) 10580 /*! AUTOBAUD - Autobaud enable. 10581 * 0b0..Disabled. USART is in normal operating mode. 10582 * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The 10583 * first start bit of RX is measured and used the update the BRG register to match the received data rate. 10584 * AUTOBAUD is cleared once this process is complete, or if there is an AERR. 10585 */ 10586 #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) 10587 /*! @} */ 10588 10589 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ 10590 /*! @{ */ 10591 #define USART_STAT_RXIDLE_MASK (0x2U) 10592 #define USART_STAT_RXIDLE_SHIFT (1U) 10593 /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of 10594 * receiving data. When 1, indicates that the receiver is not currently in the process of receiving 10595 * data. 10596 */ 10597 #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) 10598 #define USART_STAT_TXIDLE_MASK (0x8U) 10599 #define USART_STAT_TXIDLE_SHIFT (3U) 10600 /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of 10601 * sending data.When 1, indicate that the transmitter is not currently in the process of sending 10602 * data. 10603 */ 10604 #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) 10605 #define USART_STAT_CTS_MASK (0x10U) 10606 #define USART_STAT_CTS_SHIFT (4U) 10607 /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the 10608 * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode 10609 * is enabled. 10610 */ 10611 #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) 10612 #define USART_STAT_DELTACTS_MASK (0x20U) 10613 #define USART_STAT_DELTACTS_SHIFT (5U) 10614 /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 10615 */ 10616 #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) 10617 #define USART_STAT_TXDISSTAT_MASK (0x40U) 10618 #define USART_STAT_TXDISSTAT_SHIFT (6U) 10619 /*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART 10620 * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). 10621 */ 10622 #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) 10623 #define USART_STAT_RXBRK_MASK (0x400U) 10624 #define USART_STAT_RXBRK_SHIFT (10U) 10625 /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection 10626 * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also 10627 * be set when this condition occurs because the stop bit(s) for the character would be missing. 10628 * RXBRK is cleared when the Un_RXD pin goes high. 10629 */ 10630 #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) 10631 #define USART_STAT_DELTARXBRK_MASK (0x800U) 10632 #define USART_STAT_DELTARXBRK_SHIFT (11U) 10633 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. 10634 */ 10635 #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) 10636 #define USART_STAT_START_MASK (0x1000U) 10637 #define USART_STAT_START_SHIFT (12U) 10638 /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily 10639 * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. 10640 * Cleared by software. 10641 */ 10642 #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) 10643 #define USART_STAT_FRAMERRINT_MASK (0x2000U) 10644 #define USART_STAT_FRAMERRINT_SHIFT (13U) 10645 /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a 10646 * missing stop bit at the expected location. This could be an indication of a baud rate or 10647 * configuration mismatch with the transmitting source. 10648 */ 10649 #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) 10650 #define USART_STAT_PARITYERRINT_MASK (0x4000U) 10651 #define USART_STAT_PARITYERRINT_SHIFT (14U) 10652 /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 10653 */ 10654 #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) 10655 #define USART_STAT_RXNOISEINT_MASK (0x8000U) 10656 #define USART_STAT_RXNOISEINT_SHIFT (15U) 10657 /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to 10658 * determine the value of each received data bit, except in synchronous mode. This acts as a 10659 * noise filter if one sample disagrees. This flag is set when a received data bit contains one 10660 * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or 10661 * loss of synchronization during data reception. 10662 */ 10663 #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) 10664 #define USART_STAT_ABERR_MASK (0x10000U) 10665 #define USART_STAT_ABERR_SHIFT (16U) 10666 /*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the 10667 * end of the start bit that is being measured, essentially an auto baud time-out. 10668 */ 10669 #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) 10670 /*! @} */ 10671 10672 /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 10673 /*! @{ */ 10674 #define USART_INTENSET_TXIDLEEN_MASK (0x8U) 10675 #define USART_INTENSET_TXIDLEEN_SHIFT (3U) 10676 /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 10677 */ 10678 #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) 10679 #define USART_INTENSET_DELTACTSEN_MASK (0x20U) 10680 #define USART_INTENSET_DELTACTSEN_SHIFT (5U) 10681 /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. 10682 */ 10683 #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) 10684 #define USART_INTENSET_TXDISEN_MASK (0x40U) 10685 #define USART_INTENSET_TXDISEN_SHIFT (6U) 10686 /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by 10687 * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 10688 */ 10689 #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) 10690 #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) 10691 #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) 10692 /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection 10693 * of a received break condition (break condition asserted or deasserted). 10694 */ 10695 #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) 10696 #define USART_INTENSET_STARTEN_MASK (0x1000U) 10697 #define USART_INTENSET_STARTEN_SHIFT (12U) 10698 /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. 10699 */ 10700 #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) 10701 #define USART_INTENSET_FRAMERREN_MASK (0x2000U) 10702 #define USART_INTENSET_FRAMERREN_SHIFT (13U) 10703 /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. 10704 */ 10705 #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) 10706 #define USART_INTENSET_PARITYERREN_MASK (0x4000U) 10707 #define USART_INTENSET_PARITYERREN_SHIFT (14U) 10708 /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. 10709 */ 10710 #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) 10711 #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) 10712 #define USART_INTENSET_RXNOISEEN_SHIFT (15U) 10713 /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. 10714 */ 10715 #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) 10716 #define USART_INTENSET_ABERREN_MASK (0x10000U) 10717 #define USART_INTENSET_ABERREN_SHIFT (16U) 10718 /*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. 10719 */ 10720 #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) 10721 /*! @} */ 10722 10723 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ 10724 /*! @{ */ 10725 #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) 10726 #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) 10727 /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. 10728 */ 10729 #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) 10730 #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) 10731 #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) 10732 /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10733 */ 10734 #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) 10735 #define USART_INTENCLR_TXDISCLR_MASK (0x40U) 10736 #define USART_INTENCLR_TXDISCLR_SHIFT (6U) 10737 /*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10738 */ 10739 #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) 10740 #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) 10741 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) 10742 /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10743 */ 10744 #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) 10745 #define USART_INTENCLR_STARTCLR_MASK (0x1000U) 10746 #define USART_INTENCLR_STARTCLR_SHIFT (12U) 10747 /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10748 */ 10749 #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) 10750 #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) 10751 #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) 10752 /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10753 */ 10754 #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) 10755 #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) 10756 #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) 10757 /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10758 */ 10759 #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) 10760 #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) 10761 #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) 10762 /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. 10763 */ 10764 #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) 10765 #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) 10766 #define USART_INTENCLR_ABERRCLR_SHIFT (16U) 10767 /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 10768 */ 10769 #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) 10770 /*! @} */ 10771 10772 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ 10773 /*! @{ */ 10774 #define USART_BRG_BRGVAL_MASK (0xFFFFU) 10775 #define USART_BRG_BRGVAL_SHIFT (0U) 10776 /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on 10777 * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is 10778 * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART 10779 * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 10780 */ 10781 #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) 10782 /*! @} */ 10783 10784 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ 10785 /*! @{ */ 10786 #define USART_INTSTAT_TXIDLE_MASK (0x8U) 10787 #define USART_INTSTAT_TXIDLE_SHIFT (3U) 10788 /*! TXIDLE - Transmitter Idle status. 10789 */ 10790 #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) 10791 #define USART_INTSTAT_DELTACTS_MASK (0x20U) 10792 #define USART_INTSTAT_DELTACTS_SHIFT (5U) 10793 /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. 10794 */ 10795 #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) 10796 #define USART_INTSTAT_TXDISINT_MASK (0x40U) 10797 #define USART_INTSTAT_TXDISINT_SHIFT (6U) 10798 /*! TXDISINT - Transmitter Disabled Interrupt flag. 10799 */ 10800 #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) 10801 #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) 10802 #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) 10803 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. 10804 */ 10805 #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) 10806 #define USART_INTSTAT_START_MASK (0x1000U) 10807 #define USART_INTSTAT_START_SHIFT (12U) 10808 /*! START - This bit is set when a start is detected on the receiver input. 10809 */ 10810 #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) 10811 #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) 10812 #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) 10813 /*! FRAMERRINT - Framing Error interrupt flag. 10814 */ 10815 #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) 10816 #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) 10817 #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) 10818 /*! PARITYERRINT - Parity Error interrupt flag. 10819 */ 10820 #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) 10821 #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) 10822 #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) 10823 /*! RXNOISEINT - Received Noise interrupt flag. 10824 */ 10825 #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) 10826 #define USART_INTSTAT_ABERRINT_MASK (0x10000U) 10827 #define USART_INTSTAT_ABERRINT_SHIFT (16U) 10828 /*! ABERRINT - Auto baud Error Interrupt flag. 10829 */ 10830 #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) 10831 /*! @} */ 10832 10833 /*! @name OSR - Oversample selection register for asynchronous communication. */ 10834 /*! @{ */ 10835 #define USART_OSR_OSRVAL_MASK (0xFU) 10836 #define USART_OSR_OSRVAL_SHIFT (0U) 10837 /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to 10838 * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive 10839 * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 10840 */ 10841 #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) 10842 /*! @} */ 10843 10844 /*! @name ADDR - Address register for automatic address matching. */ 10845 /*! @{ */ 10846 #define USART_ADDR_ADDRESS_MASK (0xFFU) 10847 #define USART_ADDR_ADDRESS_SHIFT (0U) 10848 /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is 10849 * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 10850 */ 10851 #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) 10852 /*! @} */ 10853 10854 /*! @name FIFOCFG - FIFO configuration and enable register. */ 10855 /*! @{ */ 10856 #define USART_FIFOCFG_ENABLETX_MASK (0x1U) 10857 #define USART_FIFOCFG_ENABLETX_SHIFT (0U) 10858 /*! ENABLETX - Enable the transmit FIFO. 10859 * 0b0..The transmit FIFO is not enabled. 10860 * 0b1..The transmit FIFO is enabled. 10861 */ 10862 #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) 10863 #define USART_FIFOCFG_ENABLERX_MASK (0x2U) 10864 #define USART_FIFOCFG_ENABLERX_SHIFT (1U) 10865 /*! ENABLERX - Enable the receive FIFO. 10866 * 0b0..The receive FIFO is not enabled. 10867 * 0b1..The receive FIFO is enabled. 10868 */ 10869 #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) 10870 #define USART_FIFOCFG_SIZE_MASK (0x30U) 10871 #define USART_FIFOCFG_SIZE_SHIFT (4U) 10872 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 10873 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 10874 */ 10875 #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) 10876 #define USART_FIFOCFG_DMATX_MASK (0x1000U) 10877 #define USART_FIFOCFG_DMATX_SHIFT (12U) 10878 /*! DMATX - DMA configuration for transmit. 10879 * 0b0..DMA is not used for the transmit function. 10880 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 10881 */ 10882 #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) 10883 #define USART_FIFOCFG_DMARX_MASK (0x2000U) 10884 #define USART_FIFOCFG_DMARX_SHIFT (13U) 10885 /*! DMARX - DMA configuration for receive. 10886 * 0b0..DMA is not used for the receive function. 10887 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 10888 */ 10889 #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) 10890 #define USART_FIFOCFG_WAKETX_MASK (0x4000U) 10891 #define USART_FIFOCFG_WAKETX_SHIFT (14U) 10892 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power 10893 * modes (up to power-down, as long as the peripheral function works in that power mode) without 10894 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 10895 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 10896 * Wake-up control register. 10897 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 10898 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in 10899 * FIFOTRIG, even when the TXLVL interrupt is not enabled. 10900 */ 10901 #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) 10902 #define USART_FIFOCFG_WAKERX_MASK (0x8000U) 10903 #define USART_FIFOCFG_WAKERX_SHIFT (15U) 10904 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power 10905 * modes (up to power-down, as long as the peripheral function works in that power mode) without 10906 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The 10907 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware 10908 * Wake-up control register. 10909 * 0b0..Only enabled interrupts will wake up the device form reduced power modes. 10910 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in 10911 * FIFOTRIG, even when the RXLVL interrupt is not enabled. 10912 */ 10913 #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) 10914 #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) 10915 #define USART_FIFOCFG_EMPTYTX_SHIFT (16U) 10916 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 10917 */ 10918 #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) 10919 #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) 10920 #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) 10921 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 10922 */ 10923 #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) 10924 /*! @} */ 10925 10926 /*! @name FIFOSTAT - FIFO status register. */ 10927 /*! @{ */ 10928 #define USART_FIFOSTAT_TXERR_MASK (0x1U) 10929 #define USART_FIFOSTAT_TXERR_SHIFT (0U) 10930 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow 10931 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is 10932 * needed. Cleared by writing a 1 to this bit. 10933 */ 10934 #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) 10935 #define USART_FIFOSTAT_RXERR_MASK (0x2U) 10936 #define USART_FIFOSTAT_RXERR_SHIFT (1U) 10937 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA 10938 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 10939 */ 10940 #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) 10941 #define USART_FIFOSTAT_PERINT_MASK (0x8U) 10942 #define USART_FIFOSTAT_PERINT_SHIFT (3U) 10943 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted 10944 * an interrupt. The details can be found by reading the peripheral's STAT register. 10945 */ 10946 #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) 10947 #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) 10948 #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) 10949 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 10950 */ 10951 #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) 10952 #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) 10953 #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) 10954 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be 10955 * written. When 0, the transmit FIFO is full and another write would cause it to overflow. 10956 */ 10957 #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) 10958 #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) 10959 #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) 10960 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 10961 */ 10962 #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) 10963 #define USART_FIFOSTAT_RXFULL_MASK (0x80U) 10964 #define USART_FIFOSTAT_RXFULL_SHIFT (7U) 10965 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to 10966 * prevent the peripheral from causing an overflow. 10967 */ 10968 #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) 10969 #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) 10970 #define USART_FIFOSTAT_TXLVL_SHIFT (8U) 10971 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY 10972 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at 10973 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 10974 * 0. 10975 */ 10976 #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) 10977 #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) 10978 #define USART_FIFOSTAT_RXLVL_SHIFT (16U) 10979 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and 10980 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the 10981 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 10982 * 1. 10983 */ 10984 #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) 10985 /*! @} */ 10986 10987 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ 10988 /*! @{ */ 10989 #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) 10990 #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) 10991 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled 10992 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 10993 * 0b0..Transmit FIFO level does not generate a FIFO level trigger. 10994 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 10995 */ 10996 #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) 10997 #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) 10998 #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) 10999 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled 11000 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 11001 * 0b0..Receive FIFO level does not generate a FIFO level trigger. 11002 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 11003 */ 11004 #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) 11005 #define USART_FIFOTRIG_TXLVL_MASK (0xF00U) 11006 #define USART_FIFOTRIG_TXLVL_SHIFT (8U) 11007 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled 11008 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to 11009 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO 11010 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX 11011 * FIFO level decreases to 15 entries (is no longer full). 11012 */ 11013 #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) 11014 #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) 11015 #define USART_FIFOTRIG_RXLVL_SHIFT (16U) 11016 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data 11017 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level 11018 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See 11019 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no 11020 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX 11021 * FIFO has received 16 entries (has become full). 11022 */ 11023 #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) 11024 /*! @} */ 11025 11026 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ 11027 /*! @{ */ 11028 #define USART_FIFOINTENSET_TXERR_MASK (0x1U) 11029 #define USART_FIFOINTENSET_TXERR_SHIFT (0U) 11030 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 11031 * 0b0..No interrupt will be generated for a transmit error. 11032 * 0b1..An interrupt will be generated when a transmit error occurs. 11033 */ 11034 #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) 11035 #define USART_FIFOINTENSET_RXERR_MASK (0x2U) 11036 #define USART_FIFOINTENSET_RXERR_SHIFT (1U) 11037 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 11038 * 0b0..No interrupt will be generated for a receive error. 11039 * 0b1..An interrupt will be generated when a receive error occurs. 11040 */ 11041 #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) 11042 #define USART_FIFOINTENSET_TXLVL_MASK (0x4U) 11043 #define USART_FIFOINTENSET_TXLVL_SHIFT (2U) 11044 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level 11045 * specified by the TXLVL field in the FIFOTRIG register. 11046 * 0b0..No interrupt will be generated based on the TX FIFO level. 11047 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases 11048 * to the level specified by TXLVL in the FIFOTRIG register. 11049 */ 11050 #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) 11051 #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) 11052 #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) 11053 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level 11054 * specified by the TXLVL field in the FIFOTRIG register. 11055 * 0b0..No interrupt will be generated based on the RX FIFO level. 11056 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level 11057 * increases to the level specified by RXLVL in the FIFOTRIG register. 11058 */ 11059 #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) 11060 /*! @} */ 11061 11062 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ 11063 /*! @{ */ 11064 #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) 11065 #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) 11066 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 11067 */ 11068 #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) 11069 #define USART_FIFOINTENCLR_RXERR_MASK (0x2U) 11070 #define USART_FIFOINTENCLR_RXERR_SHIFT (1U) 11071 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. 11072 */ 11073 #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) 11074 #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) 11075 #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) 11076 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 11077 */ 11078 #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) 11079 #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) 11080 #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) 11081 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. 11082 */ 11083 #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) 11084 /*! @} */ 11085 11086 /*! @name FIFOINTSTAT - FIFO interrupt status register. */ 11087 /*! @{ */ 11088 #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) 11089 #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) 11090 /*! TXERR - TX FIFO error. 11091 */ 11092 #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) 11093 #define USART_FIFOINTSTAT_RXERR_MASK (0x2U) 11094 #define USART_FIFOINTSTAT_RXERR_SHIFT (1U) 11095 /*! RXERR - RX FIFO error. 11096 */ 11097 #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) 11098 #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) 11099 #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) 11100 /*! TXLVL - Transmit FIFO level interrupt. 11101 */ 11102 #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) 11103 #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) 11104 #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) 11105 /*! RXLVL - Receive FIFO level interrupt. 11106 */ 11107 #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) 11108 #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) 11109 #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) 11110 /*! PERINT - Peripheral interrupt. 11111 */ 11112 #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) 11113 /*! @} */ 11114 11115 /*! @name FIFOWR - FIFO write data. */ 11116 /*! @{ */ 11117 #define USART_FIFOWR_TXDATA_MASK (0x1FFU) 11118 #define USART_FIFOWR_TXDATA_SHIFT (0U) 11119 /*! TXDATA - Transmit data to the FIFO. 11120 */ 11121 #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) 11122 /*! @} */ 11123 11124 /*! @name FIFORD - FIFO read data. */ 11125 /*! @{ */ 11126 #define USART_FIFORD_RXDATA_MASK (0x1FFU) 11127 #define USART_FIFORD_RXDATA_SHIFT (0U) 11128 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 11129 */ 11130 #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) 11131 #define USART_FIFORD_FRAMERR_MASK (0x2000U) 11132 #define USART_FIFORD_FRAMERR_SHIFT (13U) 11133 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along 11134 * with from the FIFO, and indicates that the character was received with a missing stop bit at 11135 * the expected location. This could be an indication of a baud rate or configuration mismatch 11136 * with the transmitting source. 11137 */ 11138 #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) 11139 #define USART_FIFORD_PARITYERR_MASK (0x4000U) 11140 #define USART_FIFORD_PARITYERR_SHIFT (14U) 11141 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along 11142 * with from the FIFO. This bit will be set when a parity error is detected in a received 11143 * character. 11144 */ 11145 #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) 11146 #define USART_FIFORD_RXNOISE_MASK (0x8000U) 11147 #define USART_FIFORD_RXNOISE_SHIFT (15U) 11148 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. 11149 */ 11150 #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) 11151 /*! @} */ 11152 11153 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ 11154 /*! @{ */ 11155 #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) 11156 #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) 11157 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 11158 */ 11159 #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) 11160 #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) 11161 #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) 11162 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along 11163 * with from the FIFO, and indicates that the character was received with a missing stop bit at 11164 * the expected location. This could be an indication of a baud rate or configuration mismatch 11165 * with the transmitting source. 11166 */ 11167 #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) 11168 #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) 11169 #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) 11170 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along 11171 * with from the FIFO. This bit will be set when a parity error is detected in a received 11172 * character. 11173 */ 11174 #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) 11175 #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) 11176 #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) 11177 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. 11178 */ 11179 #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) 11180 /*! @} */ 11181 11182 11183 /*! 11184 * @} 11185 */ /* end of group USART_Register_Masks */ 11186 11187 11188 /* USART - Peripheral instance base addresses */ 11189 /** Peripheral USART0 base address */ 11190 #define USART0_BASE (0x40086000u) 11191 /** Peripheral USART0 base pointer */ 11192 #define USART0 ((USART_Type *)USART0_BASE) 11193 /** Peripheral USART1 base address */ 11194 #define USART1_BASE (0x40087000u) 11195 /** Peripheral USART1 base pointer */ 11196 #define USART1 ((USART_Type *)USART1_BASE) 11197 /** Peripheral USART2 base address */ 11198 #define USART2_BASE (0x40088000u) 11199 /** Peripheral USART2 base pointer */ 11200 #define USART2 ((USART_Type *)USART2_BASE) 11201 /** Peripheral USART3 base address */ 11202 #define USART3_BASE (0x40089000u) 11203 /** Peripheral USART3 base pointer */ 11204 #define USART3 ((USART_Type *)USART3_BASE) 11205 /** Peripheral USART4 base address */ 11206 #define USART4_BASE (0x4008A000u) 11207 /** Peripheral USART4 base pointer */ 11208 #define USART4 ((USART_Type *)USART4_BASE) 11209 /** Peripheral USART5 base address */ 11210 #define USART5_BASE (0x40096000u) 11211 /** Peripheral USART5 base pointer */ 11212 #define USART5 ((USART_Type *)USART5_BASE) 11213 /** Peripheral USART6 base address */ 11214 #define USART6_BASE (0x40097000u) 11215 /** Peripheral USART6 base pointer */ 11216 #define USART6 ((USART_Type *)USART6_BASE) 11217 /** Peripheral USART7 base address */ 11218 #define USART7_BASE (0x40098000u) 11219 /** Peripheral USART7 base pointer */ 11220 #define USART7 ((USART_Type *)USART7_BASE) 11221 /** Array initializer of USART peripheral base addresses */ 11222 #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } 11223 /** Array initializer of USART peripheral base pointers */ 11224 #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } 11225 /** Interrupt vectors for the USART peripheral type */ 11226 #define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } 11227 11228 /*! 11229 * @} 11230 */ /* end of group USART_Peripheral_Access_Layer */ 11231 11232 11233 /* ---------------------------------------------------------------------------- 11234 -- USB Peripheral Access Layer 11235 ---------------------------------------------------------------------------- */ 11236 11237 /*! 11238 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 11239 * @{ 11240 */ 11241 11242 /** USB - Register Layout Typedef */ 11243 typedef struct { 11244 __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ 11245 __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ 11246 __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ 11247 __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ 11248 __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ 11249 __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ 11250 __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ 11251 __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ 11252 __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ 11253 __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ 11254 __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ 11255 uint8_t RESERVED_0[8]; 11256 __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ 11257 } USB_Type; 11258 11259 /* ---------------------------------------------------------------------------- 11260 -- USB Register Masks 11261 ---------------------------------------------------------------------------- */ 11262 11263 /*! 11264 * @addtogroup USB_Register_Masks USB Register Masks 11265 * @{ 11266 */ 11267 11268 /*! @name DEVCMDSTAT - USB Device Command/Status register */ 11269 /*! @{ */ 11270 #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) 11271 #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) 11272 /*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit 11273 * is set, the device will respond on packets for function address DEV_ADDR. When receiving a 11274 * SetAddress Control Request from the USB host, software must program the new address before 11275 * completing the status phase of the SetAddress Control Request. 11276 */ 11277 #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) 11278 #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) 11279 #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) 11280 /*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. 11281 */ 11282 #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) 11283 #define USB_DEVCMDSTAT_SETUP_MASK (0x100U) 11284 #define USB_DEVCMDSTAT_SETUP_SHIFT (8U) 11285 /*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this 11286 * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW 11287 * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the 11288 * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. 11289 */ 11290 #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) 11291 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) 11292 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) 11293 /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: 11294 * 0b0..USB_NEEDCLK has normal function. 11295 * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. 11296 */ 11297 #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) 11298 #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) 11299 #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) 11300 /*! LPM_SUP - LPM Supported: 11301 * 0b0..LPM not supported. 11302 * 0b1..LPM supported. 11303 */ 11304 #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) 11305 #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) 11306 #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) 11307 /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP 11308 * 0b0..Only acknowledged packets generate an interrupt 11309 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11310 */ 11311 #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) 11312 #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) 11313 #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) 11314 /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP 11315 * 0b0..Only acknowledged packets generate an interrupt 11316 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11317 */ 11318 #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) 11319 #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) 11320 #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) 11321 /*! INTONNAK_CO - Interrupt on NAK for control OUT EP 11322 * 0b0..Only acknowledged packets generate an interrupt 11323 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11324 */ 11325 #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) 11326 #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) 11327 #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) 11328 /*! INTONNAK_CI - Interrupt on NAK for control IN EP 11329 * 0b0..Only acknowledged packets generate an interrupt 11330 * 0b1..Both acknowledged and NAKed packets generate interrupts. 11331 */ 11332 #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) 11333 #define USB_DEVCMDSTAT_DCON_MASK (0x10000U) 11334 #define USB_DEVCMDSTAT_DCON_SHIFT (16U) 11335 /*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device 11336 * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and 11337 * the VBUSDEBOUNCED bit is one. 11338 */ 11339 #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) 11340 #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) 11341 #define USB_DEVCMDSTAT_DSUS_SHIFT (17U) 11342 /*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set 11343 * to 1 when the device hasn't seen any activity on its upstream port for more than 3 11344 * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and 11345 * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen 11346 * when the device is connected (Connect bit = 1). When the device is not connected or not 11347 * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. 11348 */ 11349 #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) 11350 #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) 11351 #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) 11352 /*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is 11353 * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the 11354 * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend 11355 * bit = 1) and the software writes a zero to this bit, the device will generate a remote 11356 * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this 11357 * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the 11358 * LPM_SUPP bit is equal to one. 11359 */ 11360 #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) 11361 #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) 11362 #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) 11363 /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake 11364 * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the 11365 * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset 11366 * is received. Software can use this bit to check if the remote wake-up feature is enabled by the 11367 * host for the LPM transaction. 11368 */ 11369 #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) 11370 #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) 11371 #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) 11372 /*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up 11373 * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. 11374 */ 11375 #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) 11376 #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) 11377 #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) 11378 /*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit 11379 * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The 11380 * device is disconnected - The device receives resume signaling on its upstream port. The bit is 11381 * reset by writing a one to it. 11382 */ 11383 #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) 11384 #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) 11385 #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) 11386 /*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On 11387 * a bus reset the device will automatically go to the default state (unconfigured and responding 11388 * to address 0). The bit is reset by writing a one to it. 11389 */ 11390 #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) 11391 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) 11392 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) 11393 /*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when 11394 * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and 11395 * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. 11396 */ 11397 #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) 11398 /*! @} */ 11399 11400 /*! @name INFO - USB Info register */ 11401 /*! @{ */ 11402 #define USB_INFO_FRAME_NR_MASK (0x7FFU) 11403 #define USB_INFO_FRAME_NR_SHIFT (0U) 11404 /*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. 11405 * In case no SOF was received by the device at the beginning of a frame, the frame number 11406 * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC 11407 * error, the frame number returned will be the corrupted frame number as received by the device. 11408 */ 11409 #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) 11410 #define USB_INFO_ERR_CODE_MASK (0x7800U) 11411 #define USB_INFO_ERR_CODE_SHIFT (11U) 11412 /*! ERR_CODE - The error code which last occurred: 11413 * 0b0000..No error 11414 * 0b0001..PID encoding error 11415 * 0b0010..PID unknown 11416 * 0b0011..Packet unexpected 11417 * 0b0100..Token CRC error 11418 * 0b0101..Data CRC error 11419 * 0b0110..Time out 11420 * 0b0111..Babble 11421 * 0b1000..Truncated EOP 11422 * 0b1001..Sent/Received NAK 11423 * 0b1010..Sent Stall 11424 * 0b1011..Overrun 11425 * 0b1100..Sent empty packet 11426 * 0b1101..Bitstuff error 11427 * 0b1110..Sync error 11428 * 0b1111..Wrong data toggle 11429 */ 11430 #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) 11431 /*! @} */ 11432 11433 /*! @name EPLISTSTART - USB EP Command/Status List start address */ 11434 /*! @{ */ 11435 #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) 11436 #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) 11437 /*! EP_LIST - Start address of the USB EP Command/Status List. 11438 */ 11439 #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) 11440 /*! @} */ 11441 11442 /*! @name DATABUFSTART - USB Data buffer start address */ 11443 /*! @{ */ 11444 #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) 11445 #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) 11446 /*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. 11447 */ 11448 #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) 11449 /*! @} */ 11450 11451 /*! @name LPM - USB Link Power Management register */ 11452 /*! @{ */ 11453 #define USB_LPM_HIRD_HW_MASK (0xFU) 11454 #define USB_LPM_HIRD_HW_SHIFT (0U) 11455 /*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token 11456 */ 11457 #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) 11458 #define USB_LPM_HIRD_SW_MASK (0xF0U) 11459 #define USB_LPM_HIRD_SW_SHIFT (4U) 11460 /*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB 11461 * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. 11462 */ 11463 #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) 11464 #define USB_LPM_DATA_PENDING_MASK (0x100U) 11465 #define USB_LPM_DATA_PENDING_SHIFT (8U) 11466 /*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will 11467 * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and 11468 * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has 11469 * still data pending and LPM is supported, it must set this bit to 1. 11470 */ 11471 #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) 11472 /*! @} */ 11473 11474 /*! @name EPSKIP - USB Endpoint skip */ 11475 /*! @{ */ 11476 #define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) 11477 #define USB_EPSKIP_SKIP_SHIFT (0U) 11478 /*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must 11479 * deactivate the buffer assigned to this endpoint and return control back to software. When HW has 11480 * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An 11481 * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, 11482 * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. 11483 */ 11484 #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) 11485 /*! @} */ 11486 11487 /*! @name EPINUSE - USB Endpoint Buffer in use */ 11488 /*! @{ */ 11489 #define USB_EPINUSE_BUF_MASK (0x3FCU) 11490 #define USB_EPINUSE_BUF_SHIFT (2U) 11491 /*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 11492 * 0. 1: HW is accessing buffer 1. 11493 */ 11494 #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) 11495 /*! @} */ 11496 11497 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ 11498 /*! @{ */ 11499 #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) 11500 #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) 11501 /*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: 11502 * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding 11503 * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle 11504 * the EPINUSE bit when it clears the Active bit for the buffer. 11505 */ 11506 #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) 11507 /*! @} */ 11508 11509 /*! @name INTSTAT - USB interrupt status register */ 11510 /*! @{ */ 11511 #define USB_INTSTAT_EP0OUT_MASK (0x1U) 11512 #define USB_INTSTAT_EP0OUT_SHIFT (0U) 11513 /*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set 11514 * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is 11515 * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a 11516 * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a 11517 * one to it. 11518 */ 11519 #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) 11520 #define USB_INTSTAT_EP0IN_MASK (0x2U) 11521 #define USB_INTSTAT_EP0IN_SHIFT (1U) 11522 /*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if 11523 * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this 11524 * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can 11525 * clear this bit by writing a one to it. 11526 */ 11527 #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) 11528 #define USB_INTSTAT_EP1OUT_MASK (0x4U) 11529 #define USB_INTSTAT_EP1OUT_SHIFT (2U) 11530 /*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the 11531 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11532 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11533 * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by 11534 * writing a one to it. 11535 */ 11536 #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) 11537 #define USB_INTSTAT_EP1IN_MASK (0x8U) 11538 #define USB_INTSTAT_EP1IN_SHIFT (3U) 11539 /*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the 11540 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11541 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11542 * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing 11543 * a one to it. 11544 */ 11545 #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) 11546 #define USB_INTSTAT_EP2OUT_MASK (0x10U) 11547 #define USB_INTSTAT_EP2OUT_SHIFT (4U) 11548 /*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the 11549 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11550 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11551 * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by 11552 * writing a one to it. 11553 */ 11554 #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) 11555 #define USB_INTSTAT_EP2IN_MASK (0x20U) 11556 #define USB_INTSTAT_EP2IN_SHIFT (5U) 11557 /*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the 11558 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11559 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11560 * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing 11561 * a one to it. 11562 */ 11563 #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) 11564 #define USB_INTSTAT_EP3OUT_MASK (0x40U) 11565 #define USB_INTSTAT_EP3OUT_SHIFT (6U) 11566 /*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the 11567 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11568 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11569 * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by 11570 * writing a one to it. 11571 */ 11572 #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) 11573 #define USB_INTSTAT_EP3IN_MASK (0x80U) 11574 #define USB_INTSTAT_EP3IN_SHIFT (7U) 11575 /*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the 11576 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11577 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11578 * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing 11579 * a one to it. 11580 */ 11581 #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) 11582 #define USB_INTSTAT_EP4OUT_MASK (0x100U) 11583 #define USB_INTSTAT_EP4OUT_SHIFT (8U) 11584 /*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the 11585 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes 11586 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be 11587 * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by 11588 * writing a one to it. 11589 */ 11590 #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) 11591 #define USB_INTSTAT_EP4IN_MASK (0x200U) 11592 #define USB_INTSTAT_EP4IN_SHIFT (9U) 11593 /*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the 11594 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions 11595 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be 11596 * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing 11597 * a one to it. 11598 */ 11599 #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) 11600 #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) 11601 #define USB_INTSTAT_FRAME_INT_SHIFT (30U) 11602 /*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit 11603 * and the DCON bit are set. This bit can be used by software when handling isochronous 11604 * endpoints. Software can clear this bit by writing a one to it. 11605 */ 11606 #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) 11607 #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) 11608 #define USB_INTSTAT_DEV_INT_SHIFT (31U) 11609 /*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device 11610 * Status Change register are set. Software can clear this bit by writing a one to it. 11611 */ 11612 #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) 11613 /*! @} */ 11614 11615 /*! @name INTEN - USB interrupt enable register */ 11616 /*! @{ */ 11617 #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) 11618 #define USB_INTEN_EP_INT_EN_SHIFT (0U) 11619 /*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW 11620 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing 11621 * bit. 11622 */ 11623 #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) 11624 #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) 11625 #define USB_INTEN_FRAME_INT_EN_SHIFT (30U) 11626 /*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW 11627 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt 11628 * routing bit. 11629 */ 11630 #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) 11631 #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) 11632 #define USB_INTEN_DEV_INT_EN_SHIFT (31U) 11633 /*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW 11634 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing 11635 * bit. 11636 */ 11637 #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) 11638 /*! @} */ 11639 11640 /*! @name INTSETSTAT - USB set interrupt status register */ 11641 /*! @{ */ 11642 #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) 11643 #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) 11644 /*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt 11645 * status bit is set. When this register is read, the same value as the USB interrupt status register 11646 * is returned. 11647 */ 11648 #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) 11649 #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) 11650 #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) 11651 /*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt 11652 * status bit is set. When this register is read, the same value as the USB interrupt status 11653 * register is returned. 11654 */ 11655 #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) 11656 #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) 11657 #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) 11658 /*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt 11659 * status bit is set. When this register is read, the same value as the USB interrupt status 11660 * register is returned. 11661 */ 11662 #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) 11663 /*! @} */ 11664 11665 /*! @name EPTOGGLE - USB Endpoint toggle register */ 11666 /*! @{ */ 11667 #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) 11668 #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) 11669 /*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 11670 */ 11671 #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) 11672 /*! @} */ 11673 11674 11675 /*! 11676 * @} 11677 */ /* end of group USB_Register_Masks */ 11678 11679 11680 /* USB - Peripheral instance base addresses */ 11681 /** Peripheral USB0 base address */ 11682 #define USB0_BASE (0x40084000u) 11683 /** Peripheral USB0 base pointer */ 11684 #define USB0 ((USB_Type *)USB0_BASE) 11685 /** Array initializer of USB peripheral base addresses */ 11686 #define USB_BASE_ADDRS { USB0_BASE } 11687 /** Array initializer of USB peripheral base pointers */ 11688 #define USB_BASE_PTRS { USB0 } 11689 /** Interrupt vectors for the USB peripheral type */ 11690 #define USB_IRQS { USB0_IRQn } 11691 #define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } 11692 11693 /*! 11694 * @} 11695 */ /* end of group USB_Peripheral_Access_Layer */ 11696 11697 11698 /* ---------------------------------------------------------------------------- 11699 -- UTICK Peripheral Access Layer 11700 ---------------------------------------------------------------------------- */ 11701 11702 /*! 11703 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer 11704 * @{ 11705 */ 11706 11707 /** UTICK - Register Layout Typedef */ 11708 typedef struct { 11709 __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ 11710 __IO uint32_t STAT; /**< Status register., offset: 0x4 */ 11711 __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ 11712 __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ 11713 __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ 11714 } UTICK_Type; 11715 11716 /* ---------------------------------------------------------------------------- 11717 -- UTICK Register Masks 11718 ---------------------------------------------------------------------------- */ 11719 11720 /*! 11721 * @addtogroup UTICK_Register_Masks UTICK Register Masks 11722 * @{ 11723 */ 11724 11725 /*! @name CTRL - Control register. */ 11726 /*! @{ */ 11727 #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) 11728 #define UTICK_CTRL_DELAYVAL_SHIFT (0U) 11729 /*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer 11730 * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. 11731 */ 11732 #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) 11733 #define UTICK_CTRL_REPEAT_MASK (0x80000000U) 11734 #define UTICK_CTRL_REPEAT_SHIFT (31U) 11735 /*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. 11736 */ 11737 #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) 11738 /*! @} */ 11739 11740 /*! @name STAT - Status register. */ 11741 /*! @{ */ 11742 #define UTICK_STAT_INTR_MASK (0x1U) 11743 #define UTICK_STAT_INTR_SHIFT (0U) 11744 /*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any 11745 * value to this register clears this flag. 11746 */ 11747 #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) 11748 #define UTICK_STAT_ACTIVE_MASK (0x2U) 11749 #define UTICK_STAT_ACTIVE_SHIFT (1U) 11750 /*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. 11751 */ 11752 #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) 11753 /*! @} */ 11754 11755 /*! @name CFG - Capture configuration register. */ 11756 /*! @{ */ 11757 #define UTICK_CFG_CAPEN0_MASK (0x1U) 11758 #define UTICK_CFG_CAPEN0_SHIFT (0U) 11759 /*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. 11760 */ 11761 #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) 11762 #define UTICK_CFG_CAPEN1_MASK (0x2U) 11763 #define UTICK_CFG_CAPEN1_SHIFT (1U) 11764 /*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. 11765 */ 11766 #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) 11767 #define UTICK_CFG_CAPEN2_MASK (0x4U) 11768 #define UTICK_CFG_CAPEN2_SHIFT (2U) 11769 /*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. 11770 */ 11771 #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) 11772 #define UTICK_CFG_CAPEN3_MASK (0x8U) 11773 #define UTICK_CFG_CAPEN3_SHIFT (3U) 11774 /*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. 11775 */ 11776 #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) 11777 #define UTICK_CFG_CAPPOL0_MASK (0x100U) 11778 #define UTICK_CFG_CAPPOL0_SHIFT (8U) 11779 /*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. 11780 */ 11781 #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) 11782 #define UTICK_CFG_CAPPOL1_MASK (0x200U) 11783 #define UTICK_CFG_CAPPOL1_SHIFT (9U) 11784 /*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. 11785 */ 11786 #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) 11787 #define UTICK_CFG_CAPPOL2_MASK (0x400U) 11788 #define UTICK_CFG_CAPPOL2_SHIFT (10U) 11789 /*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. 11790 */ 11791 #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) 11792 #define UTICK_CFG_CAPPOL3_MASK (0x800U) 11793 #define UTICK_CFG_CAPPOL3_SHIFT (11U) 11794 /*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. 11795 */ 11796 #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) 11797 /*! @} */ 11798 11799 /*! @name CAPCLR - Capture clear register. */ 11800 /*! @{ */ 11801 #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) 11802 #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) 11803 /*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. 11804 */ 11805 #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) 11806 #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) 11807 #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) 11808 /*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. 11809 */ 11810 #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) 11811 #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) 11812 #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) 11813 /*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. 11814 */ 11815 #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) 11816 #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) 11817 #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) 11818 /*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. 11819 */ 11820 #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) 11821 /*! @} */ 11822 11823 /*! @name CAP - Capture register . */ 11824 /*! @{ */ 11825 #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) 11826 #define UTICK_CAP_CAP_VALUE_SHIFT (0U) 11827 /*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower 11828 * than the actual value of the Micro-tick Timer at the moment of the capture event. 11829 */ 11830 #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) 11831 #define UTICK_CAP_VALID_MASK (0x80000000U) 11832 #define UTICK_CAP_VALID_SHIFT (31U) 11833 /*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related 11834 * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. 11835 */ 11836 #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) 11837 /*! @} */ 11838 11839 /* The count of UTICK_CAP */ 11840 #define UTICK_CAP_COUNT (4U) 11841 11842 11843 /*! 11844 * @} 11845 */ /* end of group UTICK_Register_Masks */ 11846 11847 11848 /* UTICK - Peripheral instance base addresses */ 11849 /** Peripheral UTICK0 base address */ 11850 #define UTICK0_BASE (0x4000E000u) 11851 /** Peripheral UTICK0 base pointer */ 11852 #define UTICK0 ((UTICK_Type *)UTICK0_BASE) 11853 /** Array initializer of UTICK peripheral base addresses */ 11854 #define UTICK_BASE_ADDRS { UTICK0_BASE } 11855 /** Array initializer of UTICK peripheral base pointers */ 11856 #define UTICK_BASE_PTRS { UTICK0 } 11857 /** Interrupt vectors for the UTICK peripheral type */ 11858 #define UTICK_IRQS { UTICK0_IRQn } 11859 11860 /*! 11861 * @} 11862 */ /* end of group UTICK_Peripheral_Access_Layer */ 11863 11864 11865 /* ---------------------------------------------------------------------------- 11866 -- WWDT Peripheral Access Layer 11867 ---------------------------------------------------------------------------- */ 11868 11869 /*! 11870 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer 11871 * @{ 11872 */ 11873 11874 /** WWDT - Register Layout Typedef */ 11875 typedef struct { 11876 __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ 11877 __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ 11878 __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ 11879 __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ 11880 uint8_t RESERVED_0[4]; 11881 __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ 11882 __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ 11883 } WWDT_Type; 11884 11885 /* ---------------------------------------------------------------------------- 11886 -- WWDT Register Masks 11887 ---------------------------------------------------------------------------- */ 11888 11889 /*! 11890 * @addtogroup WWDT_Register_Masks WWDT Register Masks 11891 * @{ 11892 */ 11893 11894 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ 11895 /*! @{ */ 11896 #define WWDT_MOD_WDEN_MASK (0x1U) 11897 #define WWDT_MOD_WDEN_SHIFT (0U) 11898 /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the 11899 * watchdog timer will run permanently. 11900 * 0b0..Stop. The watchdog timer is stopped. 11901 * 0b1..Run. The watchdog timer is running. 11902 */ 11903 #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) 11904 #define WWDT_MOD_WDRESET_MASK (0x2U) 11905 #define WWDT_MOD_WDRESET_SHIFT (1U) 11906 /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 11907 * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. 11908 * 0b1..Reset. A watchdog time-out will cause a chip reset. 11909 */ 11910 #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) 11911 #define WWDT_MOD_WDTOF_MASK (0x4U) 11912 #define WWDT_MOD_WDTOF_SHIFT (2U) 11913 /*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by 11914 * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a 11915 * chip reset if WDRESET = 1. 11916 */ 11917 #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) 11918 #define WWDT_MOD_WDINT_MASK (0x8U) 11919 #define WWDT_MOD_WDINT_SHIFT (3U) 11920 /*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. 11921 * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the 11922 * WARNINT value is equal to the value of the TV register. This can occur if the value of 11923 * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 11924 */ 11925 #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) 11926 #define WWDT_MOD_WDPROTECT_MASK (0x10U) 11927 #define WWDT_MOD_WDPROTECT_SHIFT (4U) 11928 /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 11929 * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. 11930 * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 11931 */ 11932 #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) 11933 #define WWDT_MOD_LOCK_MASK (0x20U) 11934 #define WWDT_MOD_LOCK_SHIFT (5U) 11935 /*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down 11936 * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is 11937 * only cleared by any reset. 11938 */ 11939 #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) 11940 /*! @} */ 11941 11942 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ 11943 /*! @{ */ 11944 #define WWDT_TC_COUNT_MASK (0xFFFFFFU) 11945 #define WWDT_TC_COUNT_SHIFT (0U) 11946 /*! COUNT - Watchdog time-out value. 11947 */ 11948 #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) 11949 /*! @} */ 11950 11951 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ 11952 /*! @{ */ 11953 #define WWDT_FEED_FEED_MASK (0xFFU) 11954 #define WWDT_FEED_FEED_SHIFT (0U) 11955 /*! FEED - Feed value should be 0xAA followed by 0x55. 11956 */ 11957 #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) 11958 /*! @} */ 11959 11960 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ 11961 /*! @{ */ 11962 #define WWDT_TV_COUNT_MASK (0xFFFFFFU) 11963 #define WWDT_TV_COUNT_SHIFT (0U) 11964 /*! COUNT - Counter timer value. 11965 */ 11966 #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) 11967 /*! @} */ 11968 11969 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ 11970 /*! @{ */ 11971 #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) 11972 #define WWDT_WARNINT_WARNINT_SHIFT (0U) 11973 /*! WARNINT - Watchdog warning interrupt compare value. 11974 */ 11975 #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) 11976 /*! @} */ 11977 11978 /*! @name WINDOW - Watchdog Window compare value. */ 11979 /*! @{ */ 11980 #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) 11981 #define WWDT_WINDOW_WINDOW_SHIFT (0U) 11982 /*! WINDOW - Watchdog window value. 11983 */ 11984 #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) 11985 /*! @} */ 11986 11987 11988 /*! 11989 * @} 11990 */ /* end of group WWDT_Register_Masks */ 11991 11992 11993 /* WWDT - Peripheral instance base addresses */ 11994 /** Peripheral WWDT base address */ 11995 #define WWDT_BASE (0x4000C000u) 11996 /** Peripheral WWDT base pointer */ 11997 #define WWDT ((WWDT_Type *)WWDT_BASE) 11998 /** Array initializer of WWDT peripheral base addresses */ 11999 #define WWDT_BASE_ADDRS { WWDT_BASE } 12000 /** Array initializer of WWDT peripheral base pointers */ 12001 #define WWDT_BASE_PTRS { WWDT } 12002 /** Interrupt vectors for the WWDT peripheral type */ 12003 #define WWDT_IRQS { WDT_BOD_IRQn } 12004 12005 /*! 12006 * @} 12007 */ /* end of group WWDT_Peripheral_Access_Layer */ 12008 12009 12010 /* 12011 ** End of section using anonymous unions 12012 */ 12013 12014 #if defined(__ARMCC_VERSION) 12015 #if (__ARMCC_VERSION >= 6010050) 12016 #pragma clang diagnostic pop 12017 #else 12018 #pragma pop 12019 #endif 12020 #elif defined(__GNUC__) 12021 /* leave anonymous unions enabled */ 12022 #elif defined(__IAR_SYSTEMS_ICC__) 12023 #pragma language=default 12024 #else 12025 #error Not supported compiler type 12026 #endif 12027 12028 /*! 12029 * @} 12030 */ /* end of group Peripheral_access_layer */ 12031 12032 12033 /* ---------------------------------------------------------------------------- 12034 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12035 ---------------------------------------------------------------------------- */ 12036 12037 /*! 12038 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12039 * @{ 12040 */ 12041 12042 #if defined(__ARMCC_VERSION) 12043 #if (__ARMCC_VERSION >= 6010050) 12044 #pragma clang system_header 12045 #endif 12046 #elif defined(__IAR_SYSTEMS_ICC__) 12047 #pragma system_include 12048 #endif 12049 12050 /** 12051 * @brief Mask and left-shift a bit field value for use in a register bit range. 12052 * @param field Name of the register bit field. 12053 * @param value Value of the bit field. 12054 * @return Masked and shifted value. 12055 */ 12056 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 12057 /** 12058 * @brief Mask and right-shift a register value to extract a bit field value. 12059 * @param field Name of the register bit field. 12060 * @param value Value of the register. 12061 * @return Masked and shifted bit field value. 12062 */ 12063 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 12064 12065 /*! 12066 * @} 12067 */ /* end of group Bit_Field_Generic_Macros */ 12068 12069 12070 /* ---------------------------------------------------------------------------- 12071 -- SDK Compatibility 12072 ---------------------------------------------------------------------------- */ 12073 12074 /*! 12075 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 12076 * @{ 12077 */ 12078 12079 /* No SDK compatibility issues. */ 12080 12081 /*! 12082 * @} 12083 */ /* end of group SDK_Compatibility_Symbols */ 12084 12085 12086 #endif /* _LPC54114_CM0PLUS_H_ */ 12087 12088
