1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, 2021 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #ifndef _FSL_CLOCK_H_
11 #define _FSL_CLOCK_H_
12
13 #include "fsl_common.h"
14
15 /*! @addtogroup clock */
16 /*! @{ */
17
18 /*! @file */
19
20 /*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief CLOCK driver version 2.3.2. */
27 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
28 /*@}*/
29
30 /*! @brief Configure whether driver controls clock
31 *
32 * When set to 0, peripheral drivers will enable clock in initialize function
33 * and disable clock in de-initialize function. When set to 1, peripheral
34 * driver will not control the clock, application could control the clock out of
35 * the driver.
36 *
37 * @note All drivers share this feature switcher. If it is set to 1, application
38 * should handle clock enable and disable for all drivers.
39 */
40 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
41 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
42 #endif
43
44 /*!
45 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
46 *
47 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
48 * would cache the recent calulation and accelerate the execution to get the
49 * right settings.
50 */
51 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
52 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
53 #endif
54
55 /* Definition for delay API in clock driver, users can redefine it to the real application. */
56 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
57 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
58 #endif
59
60 /*! @brief Clock ip name array for ADC. */
61 #define ADC_CLOCKS \
62 { \
63 kCLOCK_Adc0 \
64 }
65 /*! @brief Clock ip name array for ROM. */
66 #define ROM_CLOCKS \
67 { \
68 kCLOCK_Rom \
69 }
70 /*! @brief Clock ip name array for SRAM. */
71 #define SRAM_CLOCKS \
72 { \
73 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
74 }
75 /*! @brief Clock ip name array for FLASH. */
76 #define FLASH_CLOCKS \
77 { \
78 kCLOCK_Flash \
79 }
80 /*! @brief Clock ip name array for FMC. */
81 #define FMC_CLOCKS \
82 { \
83 kCLOCK_Fmc \
84 }
85 /*! @brief Clock ip name array for EEPROM. */
86 #define EEPROM_CLOCKS \
87 { \
88 kCLOCK_Eeprom \
89 }
90 /*! @brief Clock ip name array for SPIFI. */
91 #define SPIFI_CLOCKS \
92 { \
93 kCLOCK_Spifi \
94 }
95 /*! @brief Clock ip name array for INPUTMUX. */
96 #define INPUTMUX_CLOCKS \
97 { \
98 kCLOCK_InputMux \
99 }
100 /*! @brief Clock ip name array for IOCON. */
101 #define IOCON_CLOCKS \
102 { \
103 kCLOCK_Iocon \
104 }
105 /*! @brief Clock ip name array for GPIO. */
106 #define GPIO_CLOCKS \
107 { \
108 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
109 }
110 /*! @brief Clock ip name array for PINT. */
111 #define PINT_CLOCKS \
112 { \
113 kCLOCK_Pint \
114 }
115 /*! @brief Clock ip name array for GINT. */
116 #define GINT_CLOCKS \
117 { \
118 kCLOCK_Gint, kCLOCK_Gint \
119 }
120 /*! @brief Clock ip name array for DMA. */
121 #define DMA_CLOCKS \
122 { \
123 kCLOCK_Dma \
124 }
125 /*! @brief Clock ip name array for CRC. */
126 #define CRC_CLOCKS \
127 { \
128 kCLOCK_Crc \
129 }
130 /*! @brief Clock ip name array for WWDT. */
131 #define WWDT_CLOCKS \
132 { \
133 kCLOCK_Wwdt \
134 }
135 /*! @brief Clock ip name array for RTC. */
136 #define RTC_CLOCKS \
137 { \
138 kCLOCK_Rtc \
139 }
140 /*! @brief Clock ip name array for ADC0. */
141 #define ADC0_CLOCKS \
142 { \
143 kCLOCK_Adc0 \
144 }
145 /*! @brief Clock ip name array for MRT. */
146 #define MRT_CLOCKS \
147 { \
148 kCLOCK_Mrt \
149 }
150 /*! @brief Clock ip name array for RIT. */
151 #define RIT_CLOCKS \
152 { \
153 kCLOCK_Rit \
154 }
155 /*! @brief Clock ip name array for SCT0. */
156 #define SCT_CLOCKS \
157 { \
158 kCLOCK_Sct0 \
159 }
160 /*! @brief Clock ip name array for MCAN. */
161 #define MCAN_CLOCKS \
162 { \
163 kCLOCK_Mcan0, kCLOCK_Mcan1 \
164 }
165 /*! @brief Clock ip name array for UTICK. */
166 #define UTICK_CLOCKS \
167 { \
168 kCLOCK_Utick \
169 }
170 /*! @brief Clock ip name array for FLEXCOMM. */
171 #define FLEXCOMM_CLOCKS \
172 { \
173 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
174 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10 \
175 }
176 /*! @brief Clock ip name array for LPUART. */
177 #define LPUART_CLOCKS \
178 { \
179 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
180 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
181 }
182
183 /*! @brief Clock ip name array for BI2C. */
184 #define BI2C_CLOCKS \
185 { \
186 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
187 kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
188 }
189 /*! @brief Clock ip name array for LSPI. */
190 #define LPSI_CLOCKS \
191 { \
192 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
193 kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
194 }
195 /*! @brief Clock ip name array for FLEXI2S. */
196 #define FLEXI2S_CLOCKS \
197 { \
198 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
199 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
200 }
201 /*! @brief Clock ip name array for DMIC. */
202 #define DMIC_CLOCKS \
203 { \
204 kCLOCK_DMic \
205 }
206 /*! @brief Clock ip name array for CT32B. */
207 #define CTIMER_CLOCKS \
208 { \
209 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
210 }
211 /*! @brief Clock ip name array for LCD. */
212 #define LCD_CLOCKS \
213 { \
214 kCLOCK_Lcd \
215 }
216 /*! @brief Clock ip name array for SDIO. */
217 #define SDIO_CLOCKS \
218 { \
219 kCLOCK_Sdio \
220 }
221 /*! @brief Clock ip name array for USBRAM. */
222 #define USBRAM_CLOCKS \
223 { \
224 kCLOCK_UsbRam1 \
225 }
226 /*! @brief Clock ip name array for EMC. */
227 #define EMC_CLOCKS \
228 { \
229 kCLOCK_Emc \
230 }
231 /*! @brief Clock ip name array for ETH. */
232 #define ETH_CLOCKS \
233 { \
234 kCLOCK_Eth \
235 }
236 /*! @brief Clock ip name array for AES. */
237 #define AES_CLOCKS \
238 { \
239 kCLOCK_Aes \
240 }
241 /*! @brief Clock ip name array for OTP. */
242 #define OTP_CLOCKS \
243 { \
244 kCLOCK_Otp \
245 }
246 /*! @brief Clock ip name array for RNG. */
247 #define RNG_CLOCKS \
248 { \
249 kCLOCK_Rng \
250 }
251 /*! @brief Clock ip name array for USBHMR0. */
252 #define USBHMR0_CLOCKS \
253 { \
254 kCLOCK_Usbhmr0 \
255 }
256 /*! @brief Clock ip name array for USBHSL0. */
257 #define USBHSL0_CLOCKS \
258 { \
259 kCLOCK_Usbhsl0 \
260 }
261 /*! @brief Clock ip name array for SHA0. */
262 #define SHA0_CLOCKS \
263 { \
264 kCLOCK_Sha0 \
265 }
266 /*! @brief Clock ip name array for SMARTCARD. */
267 #define SMARTCARD_CLOCKS \
268 { \
269 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
270 }
271 /*! @brief Clock ip name array for USBD. */
272 #define USBD_CLOCKS \
273 { \
274 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
275 }
276 /*! @brief Clock ip name array for USBH. */
277 #define USBH_CLOCKS \
278 { \
279 kCLOCK_Usbh1 \
280 }
281 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
282 /*------------------------------------------------------------------------------
283 clock_ip_name_t definition:
284 ------------------------------------------------------------------------------*/
285
286 #define CLK_GATE_REG_OFFSET_SHIFT 8U
287 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
288 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
289 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
290
291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
292 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
293 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
294
295 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
296 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
297
298 #define AHB_CLK_CTRL0 0
299 #define AHB_CLK_CTRL1 1
300 #define AHB_CLK_CTRL2 2
301 #define ASYNC_CLK_CTRL0 3
302
303 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
304 typedef enum _clock_ip_name
305 {
306 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
308
309 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */
310
311 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */
312
313 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */
314
315 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Spifi. */
316
317 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
318
319 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
320
321 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
322
323 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
324
325 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */
326
327 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */
328
329 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
330
331 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */
332
333 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma. */
334
335 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
336
337 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
338
339 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
340
341 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
342
343 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
344
345 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: Rit. */
346
347 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
348
349 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan0. */
350
351 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), /*!< Clock gate name: Mcan1. */
352
353 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */
354
355 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
356
357 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
358
359 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
360
361 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
362
363 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
364
365 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
366
367 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
368
369 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */
370
371 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
372
373 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
374
375 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
376
377 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
378
379 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
380
381 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
382
383 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
384
385 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
386
387 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
388
389 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
390
391 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
392
393 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
394
395 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
396
397 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
398
399 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
400
401 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
402
403 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
404
405 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
406
407 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
408
409 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
410
411 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
412
413 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
414
415 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
416
417 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
418
419 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
420
421 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
422
423 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
424
425 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
426
427 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
428
429 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
430
431 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
432
433 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
434
435 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: DMic. */
436
437 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Ct32b2. */
438
439 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */
440
441 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Ct32b0. */
442
443 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Ct32b1. */
444
445 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: BodyBias0. */
446
447 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: EzhArchB0. */
448
449 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Lcd. */
450
451 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */
452
453 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */
454
455 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */
456
457 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */
458
459 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Emc. */
460
461 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Eth. */
462
463 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), /*!< Clock gate name: Gpio4. */
464
465 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), /*!< Clock gate name: Gpio5. */
466
467 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Aes. */
468
469 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), /*!< Clock gate name: Otp. */
470
471 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */
472
473 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: FlexComm8. */
474
475 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: FlexComm9. */
476
477 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: MinUart8. */
478
479 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: MinUart9. */
480
481 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: LSpi8. */
482
483 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: LSpi9. */
484
485 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: BI2c8. */
486
487 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: BI2c9. */
488
489 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: FlexI2s8. */
490
491 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: FlexI2s9. */
492
493 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */
494
495 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */
496
497 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Sha0. */
498
499 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: SmartCard0. */
500
501 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: SmartCard1. */
502
503 kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: FlexComm10. */
504
505 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), /*!< Clock gate name: Ct32b3. */
506
507 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) /*!< Clock gate name: Ct32b4. */
508 } clock_ip_name_t;
509
510 /*! @brief Clock name used to get clock frequency. */
511 typedef enum _clock_name
512 {
513 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
514 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
515 kCLOCK_ClockOut, /*!< CLOCKOUT */
516 kCLOCK_FroHf, /*!< FRO48/96 */
517 kCLOCK_UsbPll, /*!< USB1 PLL */
518 kCLOCK_Mclk, /*!< MCLK */
519 kCLOCK_Fro12M, /*!< FRO12M */
520 kCLOCK_ExtClk, /*!< External Clock */
521 kCLOCK_PllOut, /*!< PLL Output */
522 kCLOCK_UsbClk, /*!< USB input */
523 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
524 kCLOCK_Frg, /*!< Frg Clock */
525 kCLOCK_AsyncApbClk, /*!< Async APB clock */
526 } clock_name_t;
527
528 /**
529 * @brief Clock source selections for the asynchronous APB clock
530 */
531 typedef enum _async_clock_src
532 {
533 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
534 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
535 kCLOCK_AsyncAudioPllClk, /*!< Async Audio PLL clock. */
536 kCLOCK_AsyncI2cClkFc6, /*!< Async I2C Clock. */
537
538 } async_clock_src_t;
539
540 /*! @brief Clock Mux Switches
541 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
542 * starting from LSB upwards
543 *
544 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
545 *
546 */
547
548 #define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
549 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
550 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
551
552 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
553 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
554 #define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
555 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))
556 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
557
558 #define CM_STICKCLKSEL 0
559 #define CM_MAINCLKSELA 1
560 #define CM_MAINCLKSELB 2
561 #define CM_CLKOUTCLKSELA 3
562 #define CM_SYSPLLCLKSEL 5
563 #define CM_AUDPLLCLKSEL 7
564 #define CM_SPIFICLKSEL 9
565 #define CM_ADCASYNCCLKSEL 10
566 #define CM_USB0CLKSEL 11
567 #define CM_USB1CLKSEL 12
568 #define CM_FXCOMCLKSEL0 13
569 #define CM_FXCOMCLKSEL1 14
570 #define CM_FXCOMCLKSEL2 15
571 #define CM_FXCOMCLKSEL3 16
572 #define CM_FXCOMCLKSEL4 17
573 #define CM_FXCOMCLKSEL5 18
574 #define CM_FXCOMCLKSEL6 19
575 #define CM_FXCOMCLKSEL7 20
576 #define CM_FXCOMCLKSEL8 21
577 #define CM_FXCOMCLKSEL9 22
578 #define CM_FXCOMCLKSEL10 23
579 #define CM_MCLKCLKSEL 25
580 #define CM_FRGCLKSEL 27
581 #define CM_DMICCLKSEL 28
582 #define CM_SCTCLKSEL 29
583 #define CM_LCDCLKSEL 30
584 #define CM_SDIOCLKSEL 31
585
586 #define CM_ASYNCAPB 32U
587
588 /*!
589 * @brief The enumerator of clock attach Id.
590 */
591 typedef enum _clock_attach_id
592 {
593
594 kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0), /*!< Attach SYSTICK_DIV_CLK to SYSTICKCLK. */
595
596 kWDT_OSC_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 1), /*!< Attach WDT_OSC to SYSTICKCLK. */
597
598 kOSC32K_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 2), /*!< Attach OSC32K to SYSTICKCLK. */
599
600 kFRO12M_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 3), /*!< Attach FRO12M to SYSTICKCLK. */
601
602 kNONE_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 7), /*!< Attach NONE to SYSTICKCLK. */
603
604 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
605
606 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
607
608 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach WDT_OSC to MAIN_CLK. */
609
610 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
611
612 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach SYS_PLL to MAIN_CLK. */
613
614 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
615
616 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), /*!< Attach MAIN_CLK to CLKOUT. */
617
618 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), /*!< Attach EXT_CLK to CLKOUT. */
619
620 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), /*!< Attach WDT_OSC to CLKOUT. */
621
622 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), /*!< Attach FRO_HF to CLKOUT. */
623
624 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), /*!< Attach SYS_PLL to CLKOUT. */
625
626 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), /*!< Attach USB_PLL to CLKOUT. */
627
628 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), /*!< Attach AUDIO_PLL to CLKOUT. */
629
630 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), /*!< Attach OSC32K_OSC to CLKOUT. */
631
632 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), /*!< Attach FRO12M to SYS_PLL. */
633
634 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), /*!< Attach EXT_CLK to SYS_PLL. */
635
636 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), /*!< Attach WDT_OSC to SYS_PLL. */
637
638 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), /*!< Attach OSC32K to SYS_PLL. */
639
640 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), /*!< Attach NONE to SYS_PLL. */
641
642 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), /*!< Attach FRO12M to AUDIO_PLL. */
643
644 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1), /*!< Attach EXT_CLK to AUDIO_PLL. */
645
646 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), /*!< Attach NONE to AUDIO_PLL. */
647
648 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), /*!< Attach MAIN_CLK to SPIFI_CLK. */
649
650 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), /*!< Attach SYS_PLL to SPIFI_CLK. */
651
652 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), /*!< Attach USB_PLL to SPIFI_CLK. */
653
654 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), /*!< Attach FRO_HF to SPIFI_CLK. */
655
656 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4), /*!< Attach AUDIO_PLL to SPIFI_CLK. */
657
658 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), /*!< Attach NONE to SPIFI_CLK. */
659
660 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach FRO_HF to ADC_CLK. */
661
662 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach SYS_PLL to ADC_CLK. */
663
664 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach USB_PLL to ADC_CLK. */
665
666 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /*!< Attach AUDIO_PLL to ADC_CLK. */
667
668 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
669
670 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach FRO_HF to USB0_CLK. */
671
672 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach SYS_PLL to USB0_CLK. */
673
674 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2), /*!< Attach USB_PLL to USB0_CLK. */
675
676 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */
677
678 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), /*!< Attach FRO_HF to USB1_CLK. */
679
680 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1), /*!< Attach SYS_PLL to USB1_CLK. */
681
682 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2), /*!< Attach USB_PLL to USB1_CLK. */
683
684 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), /*!< Attach NONE to USB1_CLK. */
685
686 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach FRO12M to FLEXCOMM0. */
687
688 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach FRO_HF to FLEXCOMM0. */
689
690 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach AUDIO_PLL to FLEXCOMM0. */
691
692 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach MCLK to FLEXCOMM0. */
693
694 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRG to FLEXCOMM0. */
695
696 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
697
698 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach FRO12M to FLEXCOMM1. */
699
700 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach FRO_HF to FLEXCOMM1. */
701
702 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach AUDIO_PLL to FLEXCOMM1. */
703
704 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach MCLK to FLEXCOMM1. */
705
706 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRG to FLEXCOMM1. */
707
708 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
709
710 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach FRO12M to FLEXCOMM2. */
711
712 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach FRO_HF to FLEXCOMM2. */
713
714 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach AUDIO_PLL to FLEXCOMM2. */
715
716 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach MCLK to FLEXCOMM2. */
717
718 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRG to FLEXCOMM2. */
719
720 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
721
722 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach FRO12M to FLEXCOMM3. */
723
724 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach FRO_HF to FLEXCOMM3. */
725
726 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach AUDIO_PLL to FLEXCOMM3. */
727
728 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach MCLK to FLEXCOMM3. */
729
730 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRG to FLEXCOMM3. */
731
732 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
733
734 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach FRO12M to FLEXCOMM4. */
735
736 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach FRO_HF to FLEXCOMM4. */
737
738 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach AUDIO_PLL to FLEXCOMM4. */
739
740 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach MCLK to FLEXCOMM4. */
741
742 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRG to FLEXCOMM4. */
743
744 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
745
746 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach FRO12M to FLEXCOMM5. */
747
748 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach FRO_HF to FLEXCOMM5. */
749
750 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach AUDIO_PLL to FLEXCOMM5. */
751
752 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach MCLK to FLEXCOMM5. */
753
754 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRG to FLEXCOMM5. */
755
756 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
757
758 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach FRO12M to FLEXCOMM6. */
759
760 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach FRO_HF to FLEXCOMM6. */
761
762 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach AUDIO_PLL to FLEXCOMM6. */
763
764 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach MCLK to FLEXCOMM6. */
765
766 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRG to FLEXCOMM6. */
767
768 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
769
770 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach FRO12M to FLEXCOMM7. */
771
772 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach FRO_HF to FLEXCOMM7. */
773
774 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach AUDIO_PLL to FLEXCOMM7. */
775
776 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach MCLK to FLEXCOMM7. */
777
778 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRG to FLEXCOMM7. */
779
780 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
781
782 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), /*!< Attach FRO12M to FLEXCOMM8. */
783
784 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), /*!< Attach FRO_HF to FLEXCOMM8. */
785
786 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2), /*!< Attach AUDIO_PLL to FLEXCOMM8. */
787
788 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), /*!< Attach MCLK to FLEXCOMM8. */
789
790 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), /*!< Attach FRG to FLEXCOMM8. */
791
792 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), /*!< Attach NONE to FLEXCOMM8. */
793
794 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), /*!< Attach FRO12M to FLEXCOMM9. */
795
796 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), /*!< Attach FRO_HF to FLEXCOMM9. */
797
798 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2), /*!< Attach AUDIO_PLL to FLEXCOMM9. */
799
800 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), /*!< Attach MCLK to FLEXCOMM9. */
801
802 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), /*!< Attach FRG to FLEXCOMM9. */
803
804 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), /*!< Attach NONE to FLEXCOMM9. */
805
806 kMAIN_CLK_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 0), /*!< Attach MAIN_CLK to FLEXCOMM10. */
807
808 kSYS_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 1), /*!< Attach SYS_PLL to FLEXCOMM10. */
809
810 kUSB_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 2), /*!< Attach USB_PLL to FLEXCOMM10. */
811
812 kFRO_HF_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 3), /*!< Attach FRO_HF to FLEXCOMM10. */
813
814 kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4), /*!< Attach AUDIO_PLL to FLEXCOMM10. */
815
816 kNONE_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 7), /*!< Attach NONE to FLEXCOMM10. */
817
818 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
819
820 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach AUDIO_PLL to MCLK. */
821
822 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
823
824 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), /*!< Attach MAIN_CLK to FRG. */
825
826 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), /*!< Attach SYS_PLL to FRG. */
827
828 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), /*!< Attach FRO12M to FRG. */
829
830 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), /*!< Attach FRO_HF to FRG. */
831
832 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), /*!< Attach NONE to FRG. */
833
834 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), /*!< Attach FRO12M to DMIC. */
835
836 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), /*!< Attach FRO_HF_DIV to DMIC. */
837
838 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), /*!< Attach AUDIO_PLL to DMIC. */
839
840 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), /*!< Attach MCLK to DMIC. */
841
842 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4), /*!< Attach MAIN_CLK to DMIC. */
843
844 kWDT_OSC_to_DMIC = MUX_A(CM_DMICCLKSEL, 5), /*!< Attach WDT_OSC to DMIC. */
845
846 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), /*!< Attach NONE to DMIC. */
847
848 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
849
850 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach SYS_PLL to SCT_CLK. */
851
852 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach FRO_HF to SCT_CLK. */
853
854 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach AUDIO_PLL to SCT_CLK. */
855
856 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */
857
858 kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), /*!< Attach MAIN_CLK to LCD_CLK. */
859
860 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), /*!< Attach LCDCLKIN to LCD_CLK. */
861
862 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), /*!< Attach FRO_HF to LCD_CLK. */
863
864 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), /*!< Attach NONE to LCD_CLK. */
865
866 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */
867
868 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach SYS_PLL to SDIO_CLK. */
869
870 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), /*!< Attach USB_PLL to SDIO_CLK. */
871
872 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */
873
874 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), /*!< Attach AUDIO_PLL to SDIO_CLK. */
875
876 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */
877
878 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Attach MAIN_CLK to ASYNC_APB. */
879
880 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), /*!< Attach FRO12M to ASYNC_APB. */
881
882 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), /*!< Attach AUDIO_PLL to ASYNC_APB. */
883
884 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3), /*!< Attach I2C_CLK_FC6 to ASYNC_APB. */
885
886 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
887
888 } clock_attach_id_t;
889
890 /*! @brief Clock dividers */
891 typedef enum _clock_div_name
892 {
893 kCLOCK_DivSystickClk = 0, /*!< Systick Clock Divider. */
894
895 kCLOCK_DivArmTrClkDiv = 1, /*!< Arm Tr Clk Div Divider. */
896
897 kCLOCK_DivCan0Clk = 2, /*!< Can0 Clock Divider. */
898
899 kCLOCK_DivCan1Clk = 3, /*!< Can1 Clock Divider. */
900
901 kCLOCK_DivSmartCard0Clk = 4, /*!< Smart Card0 Clock Divider. */
902
903 kCLOCK_DivSmartCard1Clk = 5, /*!< Smart Card1 Clock Divider. */
904
905 kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */
906
907 kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */
908
909 kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */
910
911 kCLOCK_DivSpifiClk = 36, /*!< Spifi Clock Divider. */
912
913 kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */
914
915 kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */
916
917 kCLOCK_DivUsb1Clk = 39, /*!< Usb1 Clock Divider. */
918
919 kCLOCK_DivFrg = 40, /*!< Frg Divider. */
920
921 kCLOCK_DivDmicClk = 42, /*!< Dmic Clock Divider. */
922
923 kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */
924
925 kCLOCK_DivLcdClk = 44, /*!< Lcd Clock Divider. */
926
927 kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */
928
929 kCLOCK_DivEmcClk = 46, /*!< Emc Clock Divider. */
930
931 kCLOCK_DivSdioClk = 47 /*!< Sdio clock divider. */
932 } clock_div_name_t;
933
934 /*******************************************************************************
935 * API
936 ******************************************************************************/
937
938 #if defined(__cplusplus)
939 extern "C" {
940 #endif /* __cplusplus */
941
CLOCK_EnableClock(clock_ip_name_t clk)942 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
943 {
944 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
945 if (index < 3UL)
946 {
947 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
948 }
949 else
950 {
951 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
952 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
953 }
954 }
955
CLOCK_DisableClock(clock_ip_name_t clk)956 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
957 {
958 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
959 if (index < 3UL)
960 {
961 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
962 }
963 else
964 {
965 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
966 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
967 }
968 }
969
970 /**
971 * @brief
972 * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
973 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
974 * output is enabled.
975 * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
976 * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
977 * implemented in ROM code and the FROHF TRIM value is stored in OTP
978 *
979 * @param froFreq target fro frequency.
980 * @return Nothing
981 */
982
983 void CLOCK_SetupFROClocking(uint32_t froFreq);
984
985 /**
986 * @brief Configure the clock selection muxes.
987 * @param connection : Clock to be configured.
988 * @return Nothing
989 */
990 void CLOCK_AttachClk(clock_attach_id_t connection);
991 /**
992 * @brief Get the actual clock attach id.
993 * This fuction uses the offset in input attach id, then it reads the actual source value in
994 * the register and combine the offset to obtain an actual attach id.
995 * @param attachId : Clock attach id to get.
996 * @return Clock source value.
997 */
998 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
999 /**
1000 * @brief Setup peripheral clock dividers.
1001 * @param div_name : Clock divider name
1002 * @param divided_by_value: Value to be divided
1003 * @param reset : Whether to reset the divider counter.
1004 * @return Nothing
1005 */
1006 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
1007
1008 /*! @brief Return Frequency of selected clock
1009 * @return Frequency of selected clock
1010 */
1011 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1012 /*! @brief Return Frequency of FRO 12MHz
1013 * @return Frequency of FRO 12MHz
1014 */
1015 uint32_t CLOCK_GetFro12MFreq(void);
1016 /*! @brief Return Frequency of ClockOut
1017 * @return Frequency of ClockOut
1018 */
1019 uint32_t CLOCK_GetClockOutClkFreq(void);
1020 /*! @brief Return Frequency of Spifi Clock
1021 * @return Frequency of Spifi.
1022 */
1023 uint32_t CLOCK_GetSpifiClkFreq(void);
1024 /*! @brief Return Frequency of Adc Clock
1025 * @return Frequency of Adc Clock.
1026 */
1027 uint32_t CLOCK_GetAdcClkFreq(void);
1028 /*! brief Return Frequency of MCAN Clock
1029 * param MCanSel : 0U: MCAN0; 1U: MCAN1
1030 * return Frequency of MCAN Clock
1031 */
1032 uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
1033 /*! @brief Return Frequency of Usb0 Clock
1034 * @return Frequency of Usb0 Clock.
1035 */
1036 uint32_t CLOCK_GetUsb0ClkFreq(void);
1037 /*! @brief Return Frequency of Usb1 Clock
1038 * @return Frequency of Usb1 Clock.
1039 */
1040 uint32_t CLOCK_GetUsb1ClkFreq(void);
1041 /*! @brief Return Frequency of MClk Clock
1042 * @return Frequency of MClk Clock.
1043 */
1044 uint32_t CLOCK_GetMclkClkFreq(void);
1045 /*! @brief Return Frequency of SCTimer Clock
1046 * @return Frequency of SCTimer Clock.
1047 */
1048 uint32_t CLOCK_GetSctClkFreq(void);
1049 /*! @brief Return Frequency of SDIO Clock
1050 * @return Frequency of SDIO Clock.
1051 */
1052 uint32_t CLOCK_GetSdioClkFreq(void);
1053 /*! @brief Return Frequency of LCD Clock
1054 * @return Frequency of LCD Clock.
1055 */
1056 uint32_t CLOCK_GetLcdClkFreq(void);
1057 /*! @brief Return Frequency of LCD CLKIN Clock
1058 * @return Frequency of LCD CLKIN Clock.
1059 */
1060 uint32_t CLOCK_GetLcdClkIn(void);
1061 /*! @brief Return Frequency of External Clock
1062 * @return Frequency of External Clock. If no external clock is used returns 0.
1063 */
1064 uint32_t CLOCK_GetExtClkFreq(void);
1065 /*! @brief Return Frequency of Watchdog Oscillator
1066 * @return Frequency of Watchdog Oscillator
1067 */
1068 uint32_t CLOCK_GetWdtOscFreq(void);
1069 /*! @brief Return Frequency of High-Freq output of FRO
1070 * @return Frequency of High-Freq output of FRO
1071 */
1072 uint32_t CLOCK_GetFroHfFreq(void);
1073 /*! @brief Return Frequency of frg
1074 * @return Frequency of FRG
1075 */
1076 uint32_t CLOCK_GetFrgClkFreq(void);
1077 /*! @brief Return Frequency of dmic
1078 * @return Frequency of DMIC
1079 */
1080 uint32_t CLOCK_GetDmicClkFreq(void);
1081
1082 /*!
1083 * @brief Set FRG Clk
1084 * @return
1085 * 1: if set FRG CLK successfully.
1086 * 0: if set FRG CLK fail.
1087 */
1088 uint32_t CLOCK_SetFRGClock(uint32_t freq);
1089
1090 /*! @brief Return Frequency of PLL
1091 * @return Frequency of PLL
1092 */
1093 uint32_t CLOCK_GetPllOutFreq(void);
1094 /*! @brief Return Frequency of USB PLL
1095 * @return Frequency of PLL
1096 */
1097 uint32_t CLOCK_GetUsbPllOutFreq(void);
1098 /*! @brief Return Frequency of AUDIO PLL
1099 * @return Frequency of PLL
1100 */
1101 uint32_t CLOCK_GetAudioPllOutFreq(void);
1102 /*! @brief Return Frequency of 32kHz osc
1103 * @return Frequency of 32kHz osc
1104 */
1105 uint32_t CLOCK_GetOsc32KFreq(void);
1106 /*! @brief Return Frequency of Core System
1107 * @return Frequency of Core System
1108 */
1109 uint32_t CLOCK_GetCoreSysClkFreq(void);
1110 /*! @brief Return Frequency of I2S MCLK Clock
1111 * @return Frequency of I2S MCLK Clock
1112 */
1113 uint32_t CLOCK_GetI2SMClkFreq(void);
1114 /*! @brief Return Frequency of Flexcomm functional Clock
1115 * @return Frequency of Flexcomm functional Clock
1116 */
1117 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1118
1119 /*! @brief return FRG Clk
1120 * @return Frequency of FRG CLK.
1121 */
1122 uint32_t CLOCK_GetFRGInputClock(void);
1123 /*! @brief Return Asynchronous APB Clock source
1124 * @return Asynchronous APB CLock source
1125 */
CLOCK_GetAsyncApbClkSrc(void)1126 __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
1127 {
1128 return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
1129 }
1130 /*! @brief Return Frequency of Asynchronous APB Clock
1131 * @return Frequency of Asynchronous APB Clock Clock
1132 */
1133 uint32_t CLOCK_GetAsyncApbClkFreq(void);
1134 /*! @brief Return EMC source
1135 * @return EMC source
1136 */
CLOCK_GetEmcClkFreq(void)1137 __STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
1138 {
1139 uint32_t freqtmp;
1140
1141 freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
1142 return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
1143 }
1144 /*! @brief Return Audio PLL input clock rate
1145 * @return Audio PLL input clock rate
1146 */
1147 uint32_t CLOCK_GetAudioPLLInClockRate(void);
1148 /*! @brief Return System PLL input clock rate
1149 * @return System PLL input clock rate
1150 */
1151 uint32_t CLOCK_GetSystemPLLInClockRate(void);
1152
1153 /*! @brief Return System PLL output clock rate
1154 * @param recompute : Forces a PLL rate recomputation if true
1155 * @return System PLL output clock rate
1156 * @note The PLL rate is cached in the driver in a variable as
1157 * the rate computation function can take some time to perform. It
1158 * is recommended to use 'false' with the 'recompute' parameter.
1159 */
1160 uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
1161
1162 /*! @brief Return System AUDIO PLL output clock rate
1163 * @param recompute : Forces a AUDIO PLL rate recomputation if true
1164 * @return System AUDIO PLL output clock rate
1165 * @note The AUDIO PLL rate is cached in the driver in a variable as
1166 * the rate computation function can take some time to perform. It
1167 * is recommended to use 'false' with the 'recompute' parameter.
1168 */
1169 uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
1170
1171 /*! @brief Return System USB PLL output clock rate
1172 * @param recompute : Forces a USB PLL rate recomputation if true
1173 * @return System USB PLL output clock rate
1174 * @note The USB PLL rate is cached in the driver in a variable as
1175 * the rate computation function can take some time to perform. It
1176 * is recommended to use 'false' with the 'recompute' parameter.
1177 */
1178 uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
1179
1180 /*! @brief Enables and disables PLL bypass mode
1181 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
1182 * @return System PLL output clock rate
1183 */
CLOCK_SetBypassPLL(bool bypass)1184 __STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
1185 {
1186 if (bypass)
1187 {
1188 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
1189 }
1190 else
1191 {
1192 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
1193 }
1194 }
1195
1196 /*! @brief Check if PLL is locked or not
1197 * @return true if the PLL is locked, false if not locked
1198 */
CLOCK_IsSystemPLLLocked(void)1199 __STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
1200 {
1201 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
1202 }
1203
1204 /*! @brief Check if USB PLL is locked or not
1205 * @return true if the USB PLL is locked, false if not locked
1206 */
CLOCK_IsUsbPLLLocked(void)1207 __STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
1208 {
1209 return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
1210 }
1211
1212 /*! @brief Check if AUDIO PLL is locked or not
1213 * @return true if the AUDIO PLL is locked, false if not locked
1214 */
CLOCK_IsAudioPLLLocked(void)1215 __STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
1216 {
1217 return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
1218 }
1219
1220 /*! @brief Enables and disables SYS OSC
1221 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
1222 */
CLOCK_Enable_SysOsc(bool enable)1223 __STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
1224 {
1225 if (enable)
1226 {
1227 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
1228 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
1229 }
1230
1231 else
1232 {
1233 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
1234 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
1235 }
1236 }
1237
1238 /*! @brief Store the current PLL rate
1239 * @param rate: Current rate of the PLL
1240 * @return Nothing
1241 **/
1242 void CLOCK_SetStoredPLLClockRate(uint32_t rate);
1243
1244 /*! @brief Store the current AUDIO PLL rate
1245 * @param rate: Current rate of the PLL
1246 * @return Nothing
1247 **/
1248 void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
1249
1250 /*! @brief PLL configuration structure flags for 'flags' field
1251 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1252 *
1253 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1254 * configuration structure must be assigned with the expected PLL frequency. If the
1255 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1256 * function and the driver will determine the PLL rate from the currently selected
1257 * PLL source. This flag might be used to configure the PLL input clock more accurately
1258 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1259 *
1260 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1261 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1262 * are not used.<br>
1263 */
1264 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1265 #define PLL_CONFIGFLAG_FORCENOFRACT \
1266 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
1267 SS hardware */
1268
1269 /*! @brief PLL configuration structure
1270 *
1271 * This structure can be used to configure the settings for a PLL
1272 * setup structure. Fill in the desired configuration for the PLL
1273 * and call the PLL setup function to fill in a PLL setup structure.
1274 */
1275 typedef struct _pll_config
1276 {
1277 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1278 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1279 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1280 } pll_config_t;
1281
1282 /*! @brief PLL setup structure flags for 'flags' field
1283 * These flags control how the PLL setup function sets up the PLL
1284 */
1285 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1286 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1287 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1288
1289 /*! @brief PLL setup structure
1290 * This structure can be used to pre-build a PLL setup configuration
1291 * at run-time and quickly set the PLL to the configuration. It can be
1292 * populated with the PLL setup function. If powering up or waiting
1293 * for PLL lock, the PLL input clock source should be configured prior
1294 * to PLL setup.
1295 */
1296 typedef struct _pll_setup
1297 {
1298 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
1299 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
1300 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
1301 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
1302 uint32_t pllRate; /*!< Acutal PLL rate */
1303 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
1304 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1305 } pll_setup_t;
1306
1307 /*! @brief PLL status definitions
1308 */
1309 typedef enum _pll_error
1310 {
1311 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1312 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1313 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1314 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1315 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1316 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1317 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1318 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1319 } pll_error_t;
1320
1321 /*! @brief USB clock source definition. */
1322 typedef enum _clock_usb_src
1323 {
1324 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
1325 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
1326 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1327 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
1328
1329 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
1330 7U) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
1331 } clock_usb_src_t;
1332
1333 /*! @brief USB PDEL Divider. */
1334 typedef enum _usb_pll_psel
1335 {
1336 pSel_Divide_1 = 0U,
1337 pSel_Divide_2,
1338 pSel_Divide_4,
1339 pSel_Divide_8
1340 } usb_pll_psel;
1341
1342 /*! @brief PLL setup structure
1343 * This structure can be used to pre-build a USB PLL setup configuration
1344 * at run-time and quickly set the usb PLL to the configuration. It can be
1345 * populated with the USB PLL setup function. If powering up or waiting
1346 * for USB PLL lock, the PLL input clock source should be configured prior
1347 * to USB PLL setup.
1348 */
1349 typedef struct _usb_pll_setup
1350 {
1351 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
1352 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
1353 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
1354 bool direct; /*!< USB PLL CCO output control */
1355 bool bypass; /*!< USB PLL inout clock bypass control */
1356 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
1357 uint32_t inputRate; /*!< USB PLL input rate */
1358 } usb_pll_setup_t;
1359
1360 /*! @brief Return System PLL output clock rate from setup structure
1361 * @param pSetup : Pointer to a PLL setup structure
1362 * @return System PLL output clock rate the setup structure will generate
1363 */
1364 uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
1365
1366 /*! @brief Return System AUDIO PLL output clock rate from setup structure
1367 * @param pSetup : Pointer to a PLL setup structure
1368 * @return System PLL output clock rate the setup structure will generate
1369 */
1370 uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
1371
1372 /*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
1373 * @param pSetup : Pointer to a PLL setup structure
1374 * @return System PLL output clock rate the setup structure will generate
1375 */
1376 uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
1377
1378 /*! @brief Return System USB PLL output clock rate from setup structure
1379 * @param pSetup : Pointer to a PLL setup structure
1380 * @return System PLL output clock rate the setup structure will generate
1381 */
1382 uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
1383
1384 /*! @brief Set PLL output based on the passed PLL setup data
1385 * @param pControl : Pointer to populated PLL control structure to generate setup with
1386 * @param pSetup : Pointer to PLL setup structure to be filled
1387 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1388 * @note Actual frequency for setup may vary from the desired frequency based on the
1389 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1390 */
1391 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1392
1393 /*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
1394 * @param pControl : Pointer to populated PLL control structure to generate setup with
1395 * @param pSetup : Pointer to PLL setup structure to be filled
1396 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1397 * @note Actual frequency for setup may vary from the desired frequency based on the
1398 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1399 */
1400 pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1401
1402 /*! @brief Set PLL output from PLL setup structure (precise frequency)
1403 * @param pSetup : Pointer to populated PLL setup structure
1404 * @param flagcfg : Flag configuration for PLL config structure
1405 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1406 * @note This function will power off the PLL, setup the PLL with the
1407 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1408 * and adjust system voltages to the new PLL rate. The function will not
1409 * alter any source clocks (ie, main systen clock) that may use the PLL,
1410 * so these should be setup prior to and after exiting the function.
1411 */
1412 pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1413
1414 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
1415 * @param pSetup : Pointer to populated PLL setup structure
1416 * @param flagcfg : Flag configuration for PLL config structure
1417 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1418 * @note This function will power off the PLL, setup the PLL with the
1419 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1420 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1421 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1422 * so these should be setup prior to and after exiting the function.
1423 */
1424 pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1425
1426 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
1427 * frequency)
1428 * @param pSetup : Pointer to populated PLL setup structure
1429 * @param flagcfg : Flag configuration for PLL config structure
1430 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1431 * @note This function will power off the PLL, setup the PLL with the
1432 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1433 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1434 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1435 * so these should be setup prior to and after exiting the function.
1436 */
1437 pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
1438
1439 /**
1440 * @brief Set PLL output from PLL setup structure (precise frequency)
1441 * @param pSetup : Pointer to populated PLL setup structure
1442 * @return kStatus_PLL_Success on success, or PLL setup error code
1443 * @note This function will power off the PLL, setup the PLL with the
1444 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1445 * and adjust system voltages to the new PLL rate. The function will not
1446 * alter any source clocks (ie, main systen clock) that may use the PLL,
1447 * so these should be setup prior to and after exiting the function.
1448 */
1449 pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
1450
1451 /**
1452 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
1453 * @param pSetup : Pointer to populated PLL setup structure
1454 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
1455 * @note This function will power off the PLL, setup the Audio PLL with the
1456 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
1457 * and adjust system voltages to the new PLL rate. The function will not
1458 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
1459 * so these should be setup prior to and after exiting the function.
1460 */
1461 pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
1462
1463 /**
1464 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
1465 * @param pSetup : Pointer to populated USB PLL setup structure
1466 * @return kStatus_PLL_Success on success, or USB PLL setup error code
1467 * @note This function will power off the USB PLL, setup the PLL with the
1468 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
1469 * and adjust system voltages to the new USB PLL rate. The function will not
1470 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
1471 * so these should be setup prior to and after exiting the function.
1472 */
1473 pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
1474
1475 /*! @brief Set PLL output based on the multiplier and input frequency
1476 * @param multiply_by : multiplier
1477 * @param input_freq : Clock input frequency of the PLL
1478 * @return Nothing
1479 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1480 * function does not disable or enable PLL power, wait for PLL lock,
1481 * or adjust system voltages. These must be done in the application.
1482 * The function will not alter any source clocks (ie, main systen clock)
1483 * that may use the PLL, so these should be setup prior to and after
1484 * exiting the function.
1485 */
1486 void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
1487
1488 /*! @brief Disable USB clock.
1489 *
1490 * Disable USB clock.
1491 */
CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)1492 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1493 {
1494 CLOCK_DisableClock(clk);
1495 }
1496
1497 /*! @brief Enable USB Device FS clock.
1498 * @param src : clock source
1499 * @param freq: clock frequency
1500 * Enable USB Device Full Speed clock.
1501 */
1502 bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1503
1504 /*! @brief Enable USB HOST FS clock.
1505 * @param src : clock source
1506 * @param freq: clock frequency
1507 * Enable USB HOST Full Speed clock.
1508 */
1509 bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
1510
1511 /*! @brief Set the current Usb PLL Rate
1512 */
1513 void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
1514
1515 /*! @brief Enable USB Device HS clock.
1516 * @param src : clock source
1517 * @param freq: clock frequency
1518 * Enable USB Device High Speed clock.
1519 */
1520 bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1521
1522 /*! @brief Enable USB HOST HS clock.
1523 * @param src : clock source
1524 * @param freq: clock frequency
1525 * Enable USB HOST High Speed clock.
1526 */
1527 bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
1528
1529 #if defined(__cplusplus)
1530 }
1531 #endif /* __cplusplus */
1532
1533 /*! @} */
1534
1535 #endif /* _FSL_CLOCK_H_ */
1536
