1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _RTE_DEVICE_H 10 #define _RTE_DEVICE_H 11 12 #include "pin_mux.h" 13 14 /* UART Select. */ 15 /* Select LPUART0 - LPUART1. */ 16 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 17 * LPUART instance. */ 18 #define RTE_USART0 0 19 #define RTE_USART0_DMA_EN 0 20 #define RTE_USART1 0 21 #define RTE_USART1_DMA_EN 0 22 /* Select UART2. */ 23 #define RTE_USART2 0 24 #define RTE_USART2_DMA_EN 0 25 26 /* UART configuration. */ 27 #define USART_RX_BUFFER_LEN 64 28 #define USART0_RX_BUFFER_ENABLE 0 29 #define USART1_RX_BUFFER_ENABLE 0 30 #define USART2_RX_BUFFER_ENABLE 0 31 32 #define RTE_USART0_PIN_INIT LPUART0_InitPins 33 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 34 #define RTE_USART0_DMA_TX_CH 0 35 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 36 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 37 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 38 #define RTE_USART0_DMA_RX_CH 1 39 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 40 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 41 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 42 43 #define RTE_USART1_PIN_INIT LPUART1_InitPins 44 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 45 #define RTE_USART1_DMA_TX_CH 0 46 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx 47 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 48 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 49 #define RTE_USART1_DMA_RX_CH 1 50 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx 51 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 52 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 53 54 #define RTE_USART2_PIN_INIT LPUART2_InitPins 55 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 56 #define RTE_USART2_DMA_TX_CH 0 57 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 58 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 59 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 60 #define RTE_USART2_DMA_RX_CH 1 61 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 62 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 63 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 64 65 /* I2C Select, I2C0 - I2C1. */ 66 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 67 */ 68 #define RTE_I2C0 0 69 #define RTE_I2C0_DMA_EN 0 70 #define RTE_I2C1 0 71 #define RTE_I2C1_DMA_EN 0 72 73 /*I2C configuration*/ 74 #define RTE_I2C0_Master_DMA_BASE DMA0 75 #define RTE_I2C0_Master_DMA_CH 0 76 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 77 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 78 79 #define RTE_I2C1_Master_DMA_BASE DMA0 80 #define RTE_I2C1_Master_DMA_CH 1 81 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 82 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 83 84 /* SPI select, SPI0 - SPI1. */ 85 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 86 */ 87 #define RTE_SPI0 0 88 #define RTE_SPI0_DMA_EN 0 89 #define RTE_SPI1 0 90 #define RTE_SPI1_DMA_EN 0 91 92 /* SPI configuration. */ 93 #define RTE_SPI0_PIN_INIT SPI0_InitPins 94 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 95 #define RTE_SPI0_DMA_TX_CH 0 96 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 97 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 98 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 99 #define RTE_SPI0_DMA_RX_CH 1 100 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 101 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 102 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 103 104 #define RTE_SPI1_PIN_INIT SPI1_InitPins 105 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 106 #define RTE_SPI1_DMA_TX_CH 2 107 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx 108 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 109 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 110 #define RTE_SPI1_DMA_RX_CH 3 111 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx 112 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 113 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 114 115 #endif /* _RTE_DEVICE_H */ 116
