1 /*
2  * Copyright 2018-2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef __FSL_SEMC_NAND_FLASH_H__
9 #define __FSL_SEMC_NAND_FLASH_H__
10 
11 #include "fsl_common.h"
12 #include "fsl_semc.h"
13 
14 /*!
15  * @addtogroup semc_nand_flash
16  * @{
17  */
18 
19 /*******************************************************************************
20  * Definitions
21  ******************************************************************************/
22 
23 /*! @brief NAND Flash vendor type, _nand_vendor_type_index */
24 enum
25 {
26     kNandVendorType_Micron   = 0U,
27     kNandVendorType_Spansion = 1U,
28     kNandVendorType_Samsung  = 2U,
29     kNandVendorType_Winbond  = 3U,
30     kNandVendorType_Hynix    = 4U,
31     kNandVendorType_Toshiba  = 5U,
32     kNandVendorType_Macronix = 6U,
33     kNandVendorType_Unknown  = 7U,
34 };
35 
36 /*! @brief Parallel NAND Flash AC timing mode, _nand_ac_timing_table_index */
37 enum
38 {
39     kNandAcTimingTableIndex_ONFI_1p0_Mode0_10MHz = 0U,
40     kNandAcTimingTableIndex_ONFI_1p0_Mode1_20MHz = 1U,
41     kNandAcTimingTableIndex_ONFI_1p0_Mode2_28MHz = 2U,
42     kNandAcTimingTableIndex_ONFI_1p0_Mode3_33MHz = 3U,
43     kNandAcTimingTableIndex_ONFI_1p0_Mode4_40MHz = 4U,
44     kNandAcTimingTableIndex_ONFI_1p0_Mode5_50MHz = 5U,
45     kNandAcTimingTableIndex_ONFI_1p0_FastestMode = 6U,
46 };
47 
48 /*! @brief Parallel NAND Flash commands, _nand_onfi_command_set */
49 enum
50 {
51     /* Must-have command */
52     kNandDeviceCmd_ONFI_Reset                         = 0xFFU,
53     kNandDeviceCmd_ONFI_ReadMode                      = 0x00U,
54     kNandDeviceCmd_ONFI_ReadParameterPage             = 0xECU,
55     kNandDeviceCmd_ONFI_ReadStatus                    = 0x70U,
56     kNandDeviceCmd_ONFI_ReadPageSetup                 = 0x00U,
57     kNandDeviceCmd_ONFI_ReadPageConfirm               = 0x30U,
58     kNandDeviceCmd_ONFI_ChangeReadColumnSetup         = 0x05U,
59     kNandDeviceCmd_ONFI_ChangeReadColumnEnhancedSetup = 0x06U,
60     kNandDeviceCmd_ONFI_ChangeReadColumnConfirm       = 0xE0U,
61     kNandDeviceCmd_ONFI_EraseBlockSetup               = 0x60U,
62     kNandDeviceCmd_ONFI_EraseBlockConfirm             = 0xD0U,
63     kNandDeviceCmd_ONFI_ProgramPageSetup              = 0x80U,
64     kNandDeviceCmd_ONFI_ProgramPageConfirm            = 0x10U,
65     /* Optional command */
66     kNandDeviceCmd_ONFI_ReadStatusEnhanced = 0x78U,
67     kNandDeviceCmd_ONFI_SetFeatures        = 0xEFU,
68     kNandDeviceCmd_ONFI_GetFeatures        = 0xEEU,
69     kNandDeviceCmd_ONFI_GetManufacturerID  = 0x90U,
70 };
71 
72 /*! @brief Parallel NAND Flash feature set*/
73 enum
74 {
75     kNandDeviceFeature_ArrayOperationMode_Address    = 0x90U,
76     kNandDeviceFeature_ArrayOperationMode_DisableECC = 0x00U,
77     kNandDeviceFeature_ArrayOperationMode_EnableECC  = 0x08U,
78 };
79 
80 /*! @brief Parallel NAND Flash ONFI Version */
81 typedef enum _nand_onfi_version
82 {
83     kNandOnfiVersion_None = 0U,
84     kNandOnfiVersion_1p0  = 1U,
85     kNandOnfiVersion_2p0  = 2U,
86     kNandOnfiVersion_3p0  = 3U,
87     kNandOnfiVersion_4p0  = 4U,
88 } nand_onfi_version_t;
89 
90 /*! @brief Parallel NAND Flash Status Command Type */
91 typedef enum _nand_status_command_type
92 {
93     kNandStatusCommandType_Common   = 0U,
94     kNandStatusCommandType_Enhanced = 1U,
95 } nand_status_command_type_t;
96 
97 /*! @brief Parallel NAND Flash change read column Command Type */
98 typedef enum _nand_change_readcolumn_command_type
99 {
100     kNandChangeReadColumnCommandType_Common   = 0U,
101     kNandChangeReadColumnCommandType_Enhanced = 1U,
102 } nand_change_readcolumn_command_type_t;
103 
104 /*! @brief NAND Flash ecc check type */
105 typedef enum _nand_ecc_check_type
106 {
107     kNandEccCheckType_SoftwareECC = 0U,
108     kNandEccCheckType_DeviceECC   = 1U,
109 } nand_ecc_check_type_t;
110 
111 /*! @brief Parallel NAND Flash Ready check option */
112 typedef enum _nand_ready_check_option
113 {
114     kNandReadyCheckOption_SR = 0U, /*!< Via Status Register */
115     kNandReadyCheckOption_RB = 1U, /*!< Via R/B# signal */
116 } nand_ready_check_option_t;
117 
118 /*!@brief Parallel NAND ONFI parameter config */
119 typedef struct __nand_onfi_parameter_config
120 {
121     /* Revision information and features block */
122     uint32_t signature;      /*!< [0x000-0x003] */
123     uint16_t revisionNumber; /*!< [0x004-0x005] */
124     struct
125     {
126         uint16_t x16bitDataBusWidth : 1;
127         uint16_t multipleLUNoperations : 1;
128         uint16_t reserved : 14;
129     } supportedFeatures; /*!< [0x006-0x007] */
130     struct
131     {
132         uint16_t reserved0 : 2;
133         uint16_t setGetfeatures : 1;
134         uint16_t readStatusEnhanced : 1;
135         uint16_t reserved1 : 2;
136         uint16_t changeReadColumnEnhanced : 1;
137         uint16_t reserved2 : 9;
138     } optionalCommands;    /*!< [0x008-0x009] */
139     uint8_t reserved0[22]; /*!< [0x00a-0x01f] */
140     /* Manufacturer information block */
141     char deviceManufacturer[12]; /*!< [0x020-0x02b] */
142     uint8_t deviceModel[20];     /*!< [0x02c-0x03f] */
143     uint8_t JEDECid;             /*!< [0x040-0x040] */
144     uint8_t dataCode[2];         /*!< [0x041-0x042] */
145     uint8_t reserved1[13];       /*!< [0x043-0x04f] */
146     /* Memory organization block */
147     uint32_t dataBytesPerPage;  /*!< [0x050-0x053] */
148     uint16_t spareBytesPerPage; /*!< [0x054-0x055] */
149     uint8_t reserved2[6];       /*!< [0x056-0x05b] */
150     uint32_t pagesPerBlock;     /*!< [0x05c-0x05f] */
151     uint32_t blocksPerLUN;      /*!< [0x060-0x063] */
152     uint8_t LUNsPerDevice;      /*!< [0x064-0x064] */
153     union
154     {
155         uint8_t addressCycles;
156         struct
157         {
158             uint8_t rowAddressCycles : 4;
159             uint8_t columnAddressCycles : 4;
160         } addressCyclesStr;
161     };                     /*!< [0x065-0x065] */
162     uint8_t reserved3[26]; /*!< [0x066-0x07f] */
163     /* Electrical parameters block */
164     uint8_t reserved4; /*!< [0x080-0x080] */
165     struct
166     {
167         uint8_t mode0 : 1;
168         uint8_t mode1 : 1;
169         uint8_t mode2 : 1;
170         uint8_t mode3 : 1;
171         uint8_t mode4 : 1;
172         uint8_t mode5 : 1;
173         uint8_t reserved : 2;
174     } timingMode;                            /*!< [0x081-0x081] */
175     uint8_t reserved5[3];                    /*!< [0x082-0x084] */
176     uint8_t maxPageProgramTimeInUs[2];       /*!< [0x085-0x086] */
177     uint8_t maxBlockEraseTimeInUs[2];        /*!< [0x087-0x088] */
178     uint8_t maxPageReadTimeInUs[2];          /*!< [0x089-0x08a] */
179     uint8_t minChangeColunmSetupTimeInNs[2]; /*!< [0x08b-0x08c] */
180     uint8_t reserved6[23];                   /*!< [0x08d-0x0a3] */
181     /* Vendor block */
182     uint16_t vendorSpecificRevisionNumber; /*!< [0x0a4-0x0a5] */
183     uint8_t reserved7[88];                 /*!< [0x0a6-0x0fd] */
184     uint16_t integrityCRC;                 /*!< [0x0fe-0x0ff] */
185 } nand_onfi_parameter_config_t;
186 
187 /*! @brief Parallel NAND ONFI feature config */
188 typedef struct __nand_onfi_feature_config
189 {
190     uint8_t command;
191     uint8_t address;
192     uint8_t parameter[4];
193     uint8_t reserved[2];
194 } nand_onfi_feature_config_t;
195 
196 /*! @brief us delay function pointer */
197 typedef void (*delay_us)(uint32_t us);
198 
199 /*! @brief SEMC NAND Flash Config block structure */
200 typedef struct _semc_mem_nand_config
201 {
202     semc_nand_config_t *semcNandConfig; /*!< memory controller configuration, shoule bd configured with controller
203                                configure structure. */
204     uint32_t clkSrc_Hz;                 /*!< The async clock frequency */
205     delay_us delayUS;                /*!< delay function pointer, application should prepare a delay function for it */
206     nand_onfi_version_t onfiVersion; /*!< only onfi nand flash will be supported currently. */
207     uint8_t readyCheckOption;        /*!< Set with enum type defined in "nand_ready_check_option_t" */
208     nand_ecc_check_type_t eccCheckType; /*!< Soft/device ECC check. */
209 } semc_mem_nand_config_t;
210 
211 /*!@brief NAND Flash handle info*/
212 typedef struct _semc_mem_nand_handle
213 {
214     delay_us delayUS;           /*!< delay function pointer, application should prepare a delay function for it */
215     uint32_t ctlAccessMemAddr1; /*!< Nand memory address for memory controller access. */
216     uint32_t ctlAccessMemAddr2; /*!< Nand memory address for memory controller access. */
217     uint8_t readyCheckOption;   /*!< Set with enum type defined in "nand_ready_check_option_t" */
218     nand_ecc_check_type_t eccCheckType;      /*!< Soft/device ECC check. */
219     uint8_t statusCommandType;               /*!< the command enhanced mode or normal command mode */
220     uint8_t changeReadColumnType;            /*!< the change read column type. */
221     uint8_t columnWidth;                     /*!< the Colum width setting in the controller. */
222     bool isFeatureCommandSupport;            /*!< feature command support .*/
223     uint32_t rowAddressToGetSR;              /*!< Row address for read status enhanced command */
224     uint32_t pageReadTimeInUs_tR;            /*!< Page read time delay */
225     uint32_t PageProgramTimeInUs_tPROG;      /*!< Page program time delay */
226     uint32_t blockEraseTimeInUs_tBERS;       /*!< block erase time delay */
227     uint32_t changeColumnSetupTimeInNs_tCCS; /*!< Change column setup time delay */
228 } semc_mem_nand_handle_t;
229 /*! @} */
230 #endif /* __FSL_SEMC_NAND_FLASH_H__ */
231