1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2017,2020 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_dspi_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.dspi_cmsis"
26 #endif
27
28 #if ((defined(RTE_SPI0) && RTE_SPI0 && defined(DSPI0)) || (defined(RTE_SPI1) && RTE_SPI1 && defined(DSPI1)) || \
29 (defined(RTE_SPI2) && RTE_SPI2 && defined(DSPI2)))
30
31 #define ARM_DSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (3)) /* driver version */
32
33 /*
34 * ARMCC does not support split the data section automatically, so the driver
35 * needs to split the data to separate sections explicitly, to reduce codesize.
36 */
37 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
38 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
39 #endif
40
41 static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS;
42
43 typedef const struct _cmsis_dspi_resource
44 {
45 SPI_Type *base;
46 uint32_t instance;
47 uint32_t (*GetFreq)(void);
48 } cmsis_dspi_resource_t;
49
50 typedef union _cmsis_dspi_handle
51 {
52 dspi_master_handle_t masterHandle;
53 dspi_slave_handle_t slaveHandle;
54 } cmsis_dspi_handle_t;
55
56 typedef struct _cmsis_dspi_interrupt_driver_state
57 {
58 cmsis_dspi_resource_t *resource;
59 cmsis_dspi_handle_t *handle;
60 ARM_SPI_SignalEvent_t event;
61
62 uint32_t baudRate_Bps;
63 uint8_t flags; /*!< Control and state flags. */
64 } cmsis_dspi_interrupt_driver_state_t;
65
66 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
67 typedef union _cmsis_dspi_edma_handle
68 {
69 dspi_master_edma_handle_t masterHandle;
70 dspi_slave_edma_handle_t slaveHandle;
71 } cmsis_dspi_edma_handle_t;
72
73 typedef const struct _cmsis_dspi_edma_resource
74 {
75 DMA_Type *txEdmaBase;
76 uint32_t txEdmaChannel;
77 DMAMUX_Type *txDmamuxBase;
78 uint8_t txDmaRequest;
79
80 DMA_Type *rxEdmaBase;
81 uint32_t rxEdmaChannel;
82 DMAMUX_Type *rxDmamuxBase;
83 uint8_t rxDmaRequest;
84
85 DMA_Type *masterLinkEdmaBase;
86 uint32_t masterLinkChannel;
87 } cmsis_dspi_edma_resource_t;
88
89 typedef struct _cmsis_dspi_edma_driver_state
90 {
91 cmsis_dspi_resource_t *resource;
92 cmsis_dspi_edma_resource_t *dmaResource;
93 cmsis_dspi_edma_handle_t *handle;
94 edma_handle_t *edmaRxRegToRxDataHandle;
95 edma_handle_t *edmaTxDataToIntermediaryHandle;
96 edma_handle_t *edmaIntermediaryToTxRegHandle;
97 edma_handle_t *edmaTxDataToTxRegHandle;
98 ARM_SPI_SignalEvent_t event;
99
100 uint32_t baudRate_Bps;
101 uint8_t flags; /*!< Control and state flags. */
102 } cmsis_dspi_edma_driver_state_t;
103 #endif
104
105 /* Driver Version */
106 static const ARM_DRIVER_VERSION s_dspiDriverVersion = {ARM_SPI_API_VERSION, ARM_DSPI_DRV_VERSION};
107
108 /* Driver Capabilities */
109 static const ARM_SPI_CAPABILITIES s_dspiDriverCapabilities = {
110 1, /* Simplex Mode (Master and Slave) */
111 0, /* TI Synchronous Serial Interface */
112 0, /* Microwire Interface */
113 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
114 };
115
116 /*
117 *Common Control function used by DSPI_InterruptControl / DSPI_EdmaControl.
118 */
DSPI_CommonControl(uint32_t control,uint32_t arg,cmsis_dspi_resource_t * resource,uint8_t * isConfigured)119 static int32_t DSPI_CommonControl(uint32_t control,
120 uint32_t arg,
121 cmsis_dspi_resource_t *resource,
122 uint8_t *isConfigured)
123 {
124 dspi_master_config_t masterConfig;
125 DSPI_MasterGetDefaultConfig(&masterConfig);
126 dspi_slave_config_t slaveConfig;
127 DSPI_SlaveGetDefaultConfig(&slaveConfig);
128 masterConfig.ctarConfig.baudRate = arg;
129
130 #if (defined(RTE_SPI0_PCS_TO_SCK_DELAY) && defined(RTE_SPI0_SCK_TO_PSC_DELAY) && \
131 defined(RTE_SPI0_BETWEEN_TRANSFER_DELAY))
132 if (0U == resource->instance)
133 {
134 masterConfig.ctarConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI0_PCS_TO_SCK_DELAY;
135 masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI0_SCK_TO_PSC_DELAY;
136 masterConfig.ctarConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI0_BETWEEN_TRANSFER_DELAY;
137 }
138 #endif /*RTE DSPI0 trnafer delay time configure */
139
140 #if (defined(RTE_SPI1_PCS_TO_SCK_DELAY) && defined(RTE_SPI1_SCK_TO_PSC_DELAY) && \
141 defined(RTE_SPI1_BETWEEN_TRANSFER_DELAY))
142 if (1U == resource->instance)
143 {
144 masterConfig.ctarConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI1_PCS_TO_SCK_DELAY;
145 masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI1_SCK_TO_PSC_DELAY;
146 masterConfig.ctarConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI1_BETWEEN_TRANSFER_DELAY;
147 }
148 #endif /*RTE DSPI1 trnafer delay time configure */
149
150 #if (defined(RTE_SPI2_PCS_TO_SCK_DELAY) && defined(RTE_SPI2_SCK_TO_PSC_DELAY) && \
151 defined(RTE_SPI2_BETWEEN_TRANSFER_DELAY))
152 if (2U == resource->instance)
153 {
154 masterConfig.ctarConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI2_PCS_TO_SCK_DELAY;
155 masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI2_SCK_TO_PSC_DELAY;
156 masterConfig.ctarConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI2_BETWEEN_TRANSFER_DELAY;
157 }
158 #endif /*RTE DSPI2 trnafer delay time configure */
159
160 switch (control & ARM_SPI_FRAME_FORMAT_Msk)
161 {
162 case ARM_SPI_CPOL0_CPHA0: /* Clock Polarity 0, Clock Phase 0*/
163 if (DSPI_IsMaster(resource->base))
164 {
165 masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
166 masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
167 }
168 else
169 {
170 slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
171 slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
172 }
173 break;
174
175 case ARM_SPI_CPOL0_CPHA1: /* Clock Polarity 0, Clock Phase 1*/
176 if (DSPI_IsMaster(resource->base))
177 {
178 masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
179 masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge;
180 }
181 else
182 {
183 slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
184 slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge;
185 }
186 break;
187
188 case ARM_SPI_CPOL1_CPHA0: /* Clock Polarity 1, Clock Phase 0*/
189 if (DSPI_IsMaster(resource->base))
190 {
191 masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow;
192 masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
193 }
194 else
195 {
196 slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow;
197 slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
198 }
199 break;
200
201 case ARM_SPI_CPOL1_CPHA1: /* Clock Polarity 1, Clock Phase 1*/
202 if (DSPI_IsMaster(resource->base))
203 {
204 masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow;
205 masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge;
206 }
207 else
208 {
209 slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow;
210 slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge;
211 }
212 break;
213
214 default:
215 /* Avoid MISRA 16.4 violation */
216 break;
217 }
218
219 if ((control & ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */
220 {
221 if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) &&
222 (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U))
223 {
224 if (DSPI_IsMaster(resource->base))
225 {
226 masterConfig.ctarConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
227 }
228 else
229 {
230 slaveConfig.ctarConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
231 }
232 }
233 else
234 {
235 return ARM_SPI_ERROR_DATA_BITS;
236 }
237 }
238
239 switch (control & ARM_SPI_BIT_ORDER_Msk)
240 {
241 case ARM_SPI_LSB_MSB: /* SPI Bit order from LSB to MSB */
242 if (DSPI_IsMaster(resource->base))
243 {
244 masterConfig.ctarConfig.direction = kDSPI_LsbFirst;
245 }
246 break;
247
248 case ARM_SPI_MSB_LSB: /* SPI Bit order from MSB to LSB */
249 if (DSPI_IsMaster(resource->base))
250 {
251 masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
252 }
253 break;
254
255 default:
256 /* Avoid MISRA 16.4 violation */
257 break;
258 }
259
260 if (DSPI_IsMaster(resource->base))
261 {
262 /* The SPI slave select is controlled by hardware, the other mode is not supported by current driver. */
263 switch (control & ARM_SPI_SS_MASTER_MODE_Msk)
264 {
265 case ARM_SPI_SS_MASTER_UNUSED:
266 break;
267 case ARM_SPI_SS_MASTER_SW:
268 break;
269 case ARM_SPI_SS_MASTER_HW_OUTPUT:
270 break;
271 case ARM_SPI_SS_MASTER_HW_INPUT:
272 break;
273 default:
274 /* Avoid MISRA 16.4 violation */
275 break;
276 }
277 }
278 else
279 {
280 /* The SPI slave select is controlled by hardware, the other mode is not supported by current driver. */
281 switch (control & ARM_SPI_SS_SLAVE_MODE_Msk)
282 {
283 case ARM_SPI_SS_SLAVE_HW:
284 break;
285 case ARM_SPI_SS_SLAVE_SW:
286 break;
287 default:
288 /* Avoid MISRA 16.4 violation */
289 break;
290 }
291 }
292 if (DSPI_IsMaster(resource->base))
293 {
294 if (((*isConfigured) & SPI_FLAG_CONFIGURED) != 0U)
295 {
296 DSPI_Deinit(resource->base);
297 }
298 DSPI_MasterInit(resource->base, &masterConfig, resource->GetFreq());
299 *isConfigured |= (uint8_t)SPI_FLAG_CONFIGURED;
300 }
301 else
302 {
303 if (((*isConfigured) & SPI_FLAG_CONFIGURED) != 0U)
304 {
305 DSPI_Deinit(resource->base);
306 }
307 DSPI_SlaveInit(resource->base, &slaveConfig);
308 *isConfigured |= (uint8_t)SPI_FLAG_CONFIGURED;
309 }
310
311 return ARM_DRIVER_OK;
312 }
313
314 /*******************************************************************************
315 * Code
316 ******************************************************************************/
317
DSPIx_GetVersion(void)318 static ARM_DRIVER_VERSION DSPIx_GetVersion(void)
319 {
320 return s_dspiDriverVersion;
321 }
322
DSPIx_GetCapabilities(void)323 static ARM_SPI_CAPABILITIES DSPIx_GetCapabilities(void)
324 {
325 return s_dspiDriverCapabilities;
326 }
327
328 #endif
329
330 #if ((defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN) || (defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || \
331 (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN))
332
333 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
334
KSDK_DSPI_MasterEdmaCallback(SPI_Type * base,dspi_master_edma_handle_t * handle,status_t status,void * userData)335 static void KSDK_DSPI_MasterEdmaCallback(SPI_Type *base,
336 dspi_master_edma_handle_t *handle,
337 status_t status,
338 void *userData)
339 {
340 uint32_t event = 0U;
341
342 if (kStatus_Success == status)
343 {
344 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
345 }
346
347 if (kStatus_DSPI_OutOfRange == status)
348 {
349 event = ARM_SPI_EVENT_DATA_LOST;
350 }
351 /* User data is actually CMSIS driver callback. */
352 if ((0U != event) && (userData != NULL))
353 {
354 ((ARM_SPI_SignalEvent_t)userData)(event);
355 }
356 }
KSDK_DSPI_SlaveEdmaCallback(SPI_Type * base,dspi_slave_edma_handle_t * handle,status_t status,void * userData)357 static void KSDK_DSPI_SlaveEdmaCallback(SPI_Type *base,
358 dspi_slave_edma_handle_t *handle,
359 status_t status,
360 void *userData)
361 {
362 uint32_t event = 0U;
363
364 if (kStatus_Success == status)
365 {
366 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
367 }
368
369 if (kStatus_DSPI_OutOfRange == status)
370 {
371 event = ARM_SPI_EVENT_DATA_LOST;
372 }
373 /* User data is actually CMSIS driver callback. */
374 if ((0U != event) && (userData != NULL))
375 {
376 ((ARM_SPI_SignalEvent_t)userData)(event);
377 }
378 }
379
DSPI_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_dspi_edma_driver_state_t * dspi)380 static int32_t DSPI_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_dspi_edma_driver_state_t *dspi)
381 {
382 if (0U == (dspi->flags & (uint8_t)SPI_FLAG_INIT))
383 {
384 dspi->event = cb_event;
385 dspi->flags = (uint8_t)SPI_FLAG_INIT;
386 }
387 return ARM_DRIVER_OK;
388 }
389
DSPI_EdmaUninitialize(cmsis_dspi_edma_driver_state_t * dspi)390 static int32_t DSPI_EdmaUninitialize(cmsis_dspi_edma_driver_state_t *dspi)
391 {
392 dspi->flags = (uint8_t)SPI_FLAG_UNINIT;
393 return ARM_DRIVER_OK;
394 }
395
DSPI_EdmaPowerControl(ARM_POWER_STATE state,cmsis_dspi_edma_driver_state_t * dspi)396 static int32_t DSPI_EdmaPowerControl(ARM_POWER_STATE state, cmsis_dspi_edma_driver_state_t *dspi)
397 {
398 int32_t result = ARM_DRIVER_OK;
399 switch (state)
400 {
401 case ARM_POWER_OFF:
402 if ((dspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
403 {
404 DSPI_Deinit(dspi->resource->base);
405 DMAMUX_DisableChannel(dspi->dmaResource->rxDmamuxBase, dspi->dmaResource->rxEdmaChannel);
406 DMAMUX_DisableChannel(dspi->dmaResource->txDmamuxBase, dspi->dmaResource->txEdmaChannel);
407 dspi->flags = (uint8_t)SPI_FLAG_INIT;
408 }
409 break;
410 case ARM_POWER_LOW:
411 result = ARM_DRIVER_ERROR_UNSUPPORTED;
412 break;
413 case ARM_POWER_FULL:
414 if (dspi->flags == (uint8_t)SPI_FLAG_UNINIT)
415 {
416 result = ARM_DRIVER_ERROR;
417 break;
418 }
419
420 if ((dspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
421 {
422 /* Driver already powered */
423 break;
424 }
425 /* Enable Clock gate */
426 CLOCK_EnableClock(s_dspiClock[dspi->resource->instance]);
427 dspi->flags |= (uint8_t)SPI_FLAG_POWER;
428 break;
429 default:
430 result = ARM_DRIVER_ERROR_UNSUPPORTED;
431 break;
432 }
433 return result;
434 }
435
DSPI_EdmaSend(const void * data,uint32_t num,cmsis_dspi_edma_driver_state_t * dspi)436 static int32_t DSPI_EdmaSend(const void *data, uint32_t num, cmsis_dspi_edma_driver_state_t *dspi)
437 {
438 int32_t ret;
439 status_t status;
440 dspi_transfer_t xfer = {0};
441 uint32_t datawidth =
442 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
443
444 xfer.rxData = NULL;
445 xfer.txData = (uint8_t *)data;
446 xfer.dataSize = num * ((datawidth + 8U) / 8U);
447
448 if (DSPI_IsMaster(dspi->resource->base))
449 {
450 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
451 if (0U == dspi->resource->instance)
452 {
453 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL;
454 }
455 #endif /* DSPI0 PCS select configuration */
456 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
457 if (1U == dspi->resource->instance)
458 {
459 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL;
460 }
461 #endif /* DSPI1 PCS select configuration */
462 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
463 if (2U == dspi->resource->instance)
464 {
465 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL;
466 }
467 #endif /* DSPI2 PCS select configuration */
468 }
469 else
470 {
471 /* DSPI slave use Ctar0 setting and slave can only use PCS0. */
472 xfer.configFlags = (uint32_t)kDSPI_SlaveCtar0;
473 }
474
475 if (DSPI_IsMaster(dspi->resource->base))
476 {
477 status = DSPI_MasterTransferEDMA(dspi->resource->base, &dspi->handle->masterHandle, &xfer);
478 }
479 else
480 {
481 status = DSPI_SlaveTransferEDMA(dspi->resource->base, &dspi->handle->slaveHandle, &xfer);
482 }
483
484 switch (status)
485 {
486 case kStatus_Success:
487 ret = ARM_DRIVER_OK;
488 break;
489 case kStatus_InvalidArgument:
490 ret = ARM_DRIVER_ERROR_PARAMETER;
491 break;
492 case kStatus_DSPI_Busy:
493 ret = ARM_DRIVER_ERROR_BUSY;
494 break;
495 default:
496 ret = ARM_DRIVER_ERROR;
497 break;
498 }
499
500 return ret;
501 }
502
DSPI_EdmaReceive(void * data,uint32_t num,cmsis_dspi_edma_driver_state_t * dspi)503 static int32_t DSPI_EdmaReceive(void *data, uint32_t num, cmsis_dspi_edma_driver_state_t *dspi)
504 {
505 int32_t ret;
506 status_t status;
507 dspi_transfer_t xfer = {0};
508 uint32_t datawidth =
509 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
510
511 xfer.txData = NULL;
512 xfer.rxData = (uint8_t *)data;
513 xfer.dataSize = num * ((datawidth + 8U) / 8U);
514
515 if (DSPI_IsMaster(dspi->resource->base))
516 {
517 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
518 if (0U == dspi->resource->instance)
519 {
520 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL;
521 }
522 #endif /* DSPI0 PCS select configuration */
523 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
524 if (1U == dspi->resource->instance)
525 {
526 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL;
527 }
528 #endif /* DSPI1 PCS select configuration */
529 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
530 if (2U == dspi->resource->instance)
531 {
532 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL;
533 }
534 #endif /* DSPI2 PCS select configuration */
535 }
536 else
537 {
538 /* DSPI slave use Ctar0 setting and slave can only use PCS0. */
539 xfer.configFlags = (uint32_t)kDSPI_SlaveCtar0;
540 }
541
542 if (DSPI_IsMaster(dspi->resource->base))
543 {
544 status = DSPI_MasterTransferEDMA(dspi->resource->base, &dspi->handle->masterHandle, &xfer);
545 }
546 else
547 {
548 status = DSPI_SlaveTransferEDMA(dspi->resource->base, &dspi->handle->slaveHandle, &xfer);
549 }
550
551 switch (status)
552 {
553 case kStatus_Success:
554 ret = ARM_DRIVER_OK;
555 break;
556 case kStatus_InvalidArgument:
557 ret = ARM_DRIVER_ERROR_PARAMETER;
558 break;
559 case kStatus_DSPI_Busy:
560 ret = ARM_DRIVER_ERROR_BUSY;
561 break;
562 default:
563 ret = ARM_DRIVER_ERROR;
564 break;
565 }
566
567 return ret;
568 }
569
DSPI_EdmaTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_dspi_edma_driver_state_t * dspi)570 static int32_t DSPI_EdmaTransfer(const void *data_out,
571 void *data_in,
572 uint32_t num,
573 cmsis_dspi_edma_driver_state_t *dspi)
574 {
575 int32_t ret;
576 status_t status;
577 dspi_transfer_t xfer = {0};
578 uint32_t datawidth =
579 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
580
581 xfer.txData = (uint8_t *)data_out;
582 xfer.rxData = (uint8_t *)data_in;
583 xfer.dataSize = num * ((datawidth + 8U) / 8U);
584
585 if (DSPI_IsMaster(dspi->resource->base))
586 {
587 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
588 if (0U == dspi->resource->instance)
589 {
590 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL;
591 }
592 #endif /* DSPI0 PCS select configuration */
593 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
594 if (1U == dspi->resource->instance)
595 {
596 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL;
597 }
598 #endif /* DSPI1 PCS select configuration */
599 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
600 if (2U == dspi->resource->instance)
601 {
602 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL;
603 }
604 #endif /* DSPI2 PCS select configuration */
605 }
606 else
607 {
608 /* DSPI slave use Ctar0 setting and slave can only use PCS0. */
609 xfer.configFlags = (uint32_t)kDSPI_SlaveCtar0;
610 }
611
612 if (DSPI_IsMaster(dspi->resource->base))
613 {
614 status = DSPI_MasterTransferEDMA(dspi->resource->base, &dspi->handle->masterHandle, &xfer);
615 }
616 else
617 {
618 status = DSPI_SlaveTransferEDMA(dspi->resource->base, &dspi->handle->slaveHandle, &xfer);
619 }
620
621 switch (status)
622 {
623 case kStatus_Success:
624 ret = ARM_DRIVER_OK;
625 break;
626 case kStatus_InvalidArgument:
627 ret = ARM_DRIVER_ERROR_PARAMETER;
628 break;
629 case kStatus_DSPI_Busy:
630 ret = ARM_DRIVER_ERROR_BUSY;
631 break;
632 default:
633 ret = ARM_DRIVER_ERROR;
634 break;
635 }
636
637 return ret;
638 }
DSPI_EdmaGetCount(cmsis_dspi_edma_driver_state_t * dspi)639 static uint32_t DSPI_EdmaGetCount(cmsis_dspi_edma_driver_state_t *dspi)
640 {
641 uint32_t cnt;
642 size_t bytes;
643 uint32_t datawidth =
644 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
645
646 if (DSPI_IsMaster(dspi->resource->base))
647 {
648 if (dspi->handle->masterHandle.state != (uint8_t)kDSPI_Idle)
649 {
650 cnt = 0UL;
651 return cnt;
652 }
653 bytes = (uint32_t)dspi->handle->masterHandle.nbytes *
654 EDMA_GetRemainingMajorLoopCount(dspi->dmaResource->rxEdmaBase, dspi->dmaResource->rxEdmaChannel);
655 cnt = dspi->handle->masterHandle.totalByteCount - bytes;
656 }
657 else
658 {
659 if (dspi->handle->slaveHandle.state != (uint8_t)kDSPI_Idle)
660 {
661 cnt = 0UL;
662 return cnt;
663 }
664 bytes = (uint32_t)dspi->handle->slaveHandle.nbytes *
665 EDMA_GetRemainingMajorLoopCount(dspi->dmaResource->rxEdmaBase, dspi->dmaResource->rxEdmaChannel);
666 cnt = dspi->handle->slaveHandle.totalByteCount - bytes;
667 }
668 cnt /= ((datawidth + 8U) / 8U);
669
670 return cnt;
671 }
672
DSPI_EdmaControl(uint32_t control,uint32_t arg,cmsis_dspi_edma_driver_state_t * dspi)673 static int32_t DSPI_EdmaControl(uint32_t control, uint32_t arg, cmsis_dspi_edma_driver_state_t *dspi)
674 {
675 int32_t result = ARM_DRIVER_OK;
676 bool isContinue = false;
677 if (0U == (dspi->flags & (uint8_t)SPI_FLAG_POWER))
678 {
679 return ARM_DRIVER_ERROR;
680 }
681
682 cmsis_dspi_edma_resource_t *dmaResource = dspi->dmaResource;
683
684 switch (control & ARM_SPI_CONTROL_Msk)
685 {
686 case ARM_SPI_MODE_INACTIVE:
687 DSPI_Enable(dspi->resource->base, false);
688 result = ARM_DRIVER_OK;
689 break;
690
691 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */
692 DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Master);
693 (void)memset((dspi->edmaRxRegToRxDataHandle), 0, sizeof(edma_handle_t));
694 (void)memset((dspi->edmaTxDataToIntermediaryHandle), 0, sizeof(edma_handle_t));
695 (void)memset((dspi->edmaIntermediaryToTxRegHandle), 0, sizeof(edma_handle_t));
696
697 EDMA_CreateHandle(dspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel);
698 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest);
699 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel);
700
701 EDMA_CreateHandle(dspi->edmaTxDataToIntermediaryHandle, dmaResource->txEdmaBase,
702 dmaResource->txEdmaChannel);
703
704 EDMA_CreateHandle(dspi->edmaIntermediaryToTxRegHandle, dmaResource->masterLinkEdmaBase,
705 dmaResource->masterLinkChannel);
706
707 if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(dspi->resource->base))
708 {
709 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->masterLinkChannel, (int32_t)dmaResource->txDmaRequest);
710 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->masterLinkChannel);
711 }
712 DSPI_MasterTransferCreateHandleEDMA(dspi->resource->base, &(dspi->handle->masterHandle),
713 KSDK_DSPI_MasterEdmaCallback, (void *)dspi->event,
714 (dspi->edmaRxRegToRxDataHandle), (dspi->edmaTxDataToIntermediaryHandle),
715 (dspi->edmaIntermediaryToTxRegHandle));
716
717 dspi->baudRate_Bps = arg;
718 dspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
719 isContinue = true;
720 break;
721
722 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */
723 DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Slave);
724 (void)memset(dspi->edmaRxRegToRxDataHandle, 0, sizeof(edma_handle_t));
725 (void)memset(dspi->edmaTxDataToTxRegHandle, 0, sizeof(edma_handle_t));
726
727 EDMA_CreateHandle(dspi->edmaTxDataToTxRegHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel);
728 if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(dspi->resource->base))
729 {
730 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, (int32_t)dmaResource->txDmaRequest);
731 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel);
732 }
733
734 EDMA_CreateHandle(dspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel);
735 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest);
736 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel);
737
738 DSPI_SlaveTransferCreateHandleEDMA(dspi->resource->base, &(dspi->handle->slaveHandle),
739 KSDK_DSPI_SlaveEdmaCallback, (void *)dspi->event,
740 (dspi->edmaRxRegToRxDataHandle), (dspi->edmaTxDataToTxRegHandle));
741
742 dspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
743 isContinue = true;
744 break;
745
746 case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
747 if (!DSPI_IsMaster(dspi->resource->base))
748 {
749 result = ARM_DRIVER_ERROR_UNSUPPORTED;
750 break;
751 }
752
753 if (0U == DSPI_MasterSetBaudRate(dspi->resource->base, kDSPI_Ctar0, arg, dspi->resource->GetFreq()))
754 {
755 result = ARM_DRIVER_ERROR;
756 break;
757 }
758
759 dspi->baudRate_Bps = (uint32_t)arg;
760 result = ARM_DRIVER_OK;
761 break;
762
763 case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */
764 if (!DSPI_IsMaster(dspi->resource->base))
765 {
766 result = ARM_DRIVER_ERROR_UNSUPPORTED;
767 break;
768 }
769
770 result = (int32_t)dspi->baudRate_Bps;
771 break;
772
773 case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */
774 result = ARM_DRIVER_ERROR_UNSUPPORTED;
775 break;
776
777 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
778 if (DSPI_IsMaster(dspi->resource->base))
779 {
780 DSPI_MasterTransferAbortEDMA(dspi->resource->base, &dspi->handle->masterHandle);
781 }
782 else
783 {
784 DSPI_SlaveTransferAbortEDMA(dspi->resource->base, &dspi->handle->slaveHandle);
785 }
786 result = ARM_DRIVER_OK;
787 break;
788
789 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
790 DSPI_SetDummyData(dspi->resource->base, (uint8_t)arg);
791 result = ARM_DRIVER_OK;
792 break;
793
794 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
795 /* Mode is not supported by current driver. */
796 result = ARM_DRIVER_ERROR_UNSUPPORTED;
797 break;
798
799 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
800 /* Mode is not supported by current driver. */
801 result = ARM_DRIVER_ERROR_UNSUPPORTED;
802 break;
803
804 default:
805 isContinue = true;
806 break;
807 }
808
809 if (isContinue)
810 {
811 result = DSPI_CommonControl(control, dspi->baudRate_Bps, dspi->resource, &dspi->flags);
812 }
813 return result;
814 }
815
DSPI_EdmaGetStatus(cmsis_dspi_edma_driver_state_t * dspi)816 static ARM_SPI_STATUS DSPI_EdmaGetStatus(cmsis_dspi_edma_driver_state_t *dspi)
817 {
818 ARM_SPI_STATUS stat = {0};
819 uint32_t ksdk_dspi_status = DSPI_GetStatusFlags(dspi->resource->base);
820
821 if (DSPI_IsMaster(dspi->resource->base))
822 {
823 stat.busy = ((uint8_t)kDSPI_Busy == dspi->handle->masterHandle.state) ? (1U) : (0U);
824 }
825 else
826 {
827 stat.busy = ((uint8_t)kDSPI_Busy == dspi->handle->slaveHandle.state) ? (1U) : (0U);
828 }
829
830 stat.data_lost = (((ksdk_dspi_status & (uint32_t)kDSPI_TxFifoUnderflowFlag) != 0U) ||
831 ((ksdk_dspi_status & (uint32_t)kDSPI_RxFifoOverflowFlag) != 0U)) ?
832 (1U) :
833 (0U);
834 stat.mode_fault = 0U;
835 stat.reserved = 0U;
836
837 return stat;
838 }
839 #endif /* defined(FSL_FEATURE_SOC_EDMA_COUNT) */
840
841 #endif
842
843 #if ((defined(RTE_SPI0) && RTE_SPI0 && !(defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN)) || \
844 (defined(RTE_SPI1) && RTE_SPI1 && !(defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN)) || \
845 (defined(RTE_SPI2) && RTE_SPI2 && !(defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN)))
846
KSDK_DSPI_MasterInterruptCallback(SPI_Type * base,dspi_master_handle_t * handle,status_t status,void * userData)847 static void KSDK_DSPI_MasterInterruptCallback(SPI_Type *base,
848 dspi_master_handle_t *handle,
849 status_t status,
850 void *userData)
851 {
852 uint32_t event = 0U;
853
854 if (kStatus_Success == status)
855 {
856 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
857 }
858
859 if (kStatus_DSPI_Error == status)
860 {
861 event = ARM_SPI_EVENT_DATA_LOST;
862 }
863 /* User data is actually CMSIS driver callback. */
864 if ((0U != event) && (userData != NULL))
865 {
866 ((ARM_SPI_SignalEvent_t)userData)(event);
867 }
868 }
KSDK_DSPI_SlaveInterruptCallback(SPI_Type * base,dspi_slave_handle_t * handle,status_t status,void * userData)869 static void KSDK_DSPI_SlaveInterruptCallback(SPI_Type *base,
870 dspi_slave_handle_t *handle,
871 status_t status,
872 void *userData)
873 {
874 uint32_t event = 0U;
875
876 if (kStatus_Success == status)
877 {
878 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
879 }
880
881 if (kStatus_DSPI_Error == status)
882 {
883 event = ARM_SPI_EVENT_DATA_LOST;
884 }
885 /* User data is actually CMSIS driver callback. */
886 if ((0U != event) && (userData != NULL))
887 {
888 ((ARM_SPI_SignalEvent_t)userData)(event);
889 }
890 }
891
DSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_dspi_interrupt_driver_state_t * dspi)892 static int32_t DSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_dspi_interrupt_driver_state_t *dspi)
893 {
894 if (0U == (dspi->flags & (uint8_t)SPI_FLAG_INIT))
895 {
896 dspi->event = cb_event;
897 dspi->flags = (uint8_t)SPI_FLAG_INIT;
898 }
899 return ARM_DRIVER_OK;
900 }
901
DSPI_InterruptUninitialize(cmsis_dspi_interrupt_driver_state_t * dspi)902 static int32_t DSPI_InterruptUninitialize(cmsis_dspi_interrupt_driver_state_t *dspi)
903 {
904 dspi->flags = (uint8_t)SPI_FLAG_UNINIT;
905 return ARM_DRIVER_OK;
906 }
907
DSPI_InterruptPowerControl(ARM_POWER_STATE state,cmsis_dspi_interrupt_driver_state_t * dspi)908 static int32_t DSPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_dspi_interrupt_driver_state_t *dspi)
909 {
910 int32_t result = ARM_DRIVER_OK;
911 switch (state)
912 {
913 case ARM_POWER_OFF:
914 if ((dspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
915 {
916 DSPI_Deinit(dspi->resource->base);
917 dspi->flags = (uint8_t)SPI_FLAG_INIT;
918 }
919 break;
920
921 case ARM_POWER_LOW:
922 result = ARM_DRIVER_ERROR_UNSUPPORTED;
923 break;
924
925 case ARM_POWER_FULL:
926 if (dspi->flags == (uint8_t)SPI_FLAG_UNINIT)
927 {
928 result = ARM_DRIVER_ERROR;
929 break;
930 }
931
932 if ((dspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
933 {
934 /* Driver already powered */
935 break;
936 }
937
938 CLOCK_EnableClock(s_dspiClock[dspi->resource->instance]);
939 dspi->flags |= (uint8_t)SPI_FLAG_POWER;
940
941 break;
942 default:
943 result = ARM_DRIVER_ERROR_UNSUPPORTED;
944 break;
945 }
946 return result;
947 }
948
DSPI_InterruptSend(const void * data,uint32_t num,cmsis_dspi_interrupt_driver_state_t * dspi)949 static int32_t DSPI_InterruptSend(const void *data, uint32_t num, cmsis_dspi_interrupt_driver_state_t *dspi)
950 {
951 int32_t ret;
952 status_t status;
953 dspi_transfer_t xfer = {0};
954 uint32_t datawidth =
955 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
956
957 xfer.rxData = NULL;
958 xfer.txData = (uint8_t *)data;
959 xfer.dataSize = num * ((datawidth + 8U) / 8U);
960
961 if (DSPI_IsMaster(dspi->resource->base))
962 {
963 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
964 if (0U == dspi->resource->instance)
965 {
966 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL;
967 }
968 #endif /* DSPI0 PCS select configuration */
969 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
970 if (1U == dspi->resource->instance)
971 {
972 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL;
973 }
974 #endif /* DSPI1 PCS select configuration */
975 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
976 if (2U == dspi->resource->instance)
977 {
978 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL;
979 }
980 #endif /* DSPI2 PCS select configuration */
981 }
982 else
983 {
984 /* DSPI slave use Ctar0 setting and slave can only use PCS0. */
985 xfer.configFlags = (uint32_t)kDSPI_SlaveCtar0;
986 }
987
988 if (DSPI_IsMaster(dspi->resource->base))
989 {
990 status = DSPI_MasterTransferNonBlocking(dspi->resource->base, &dspi->handle->masterHandle, &xfer);
991 }
992 else
993 {
994 status = DSPI_SlaveTransferNonBlocking(dspi->resource->base, &dspi->handle->slaveHandle, &xfer);
995 }
996
997 switch (status)
998 {
999 case kStatus_Success:
1000 ret = ARM_DRIVER_OK;
1001 break;
1002 case kStatus_InvalidArgument:
1003 ret = ARM_DRIVER_ERROR_PARAMETER;
1004 break;
1005 case kStatus_DSPI_Busy:
1006 ret = ARM_DRIVER_ERROR_BUSY;
1007 break;
1008 default:
1009 ret = ARM_DRIVER_ERROR;
1010 break;
1011 }
1012
1013 return ret;
1014 }
1015
DSPI_InterruptReceive(void * data,uint32_t num,cmsis_dspi_interrupt_driver_state_t * dspi)1016 static int32_t DSPI_InterruptReceive(void *data, uint32_t num, cmsis_dspi_interrupt_driver_state_t *dspi)
1017 {
1018 int32_t ret;
1019 status_t status;
1020 dspi_transfer_t xfer = {0};
1021 uint32_t datawidth =
1022 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
1023
1024 xfer.txData = NULL;
1025 xfer.rxData = (uint8_t *)data;
1026 xfer.dataSize = num * ((datawidth + 8U) / 8U);
1027
1028 if (DSPI_IsMaster(dspi->resource->base))
1029 {
1030 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
1031 if (0U == dspi->resource->instance)
1032 {
1033 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL;
1034 }
1035 #endif /* DSPI0 PCS select configuration */
1036 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
1037 if (1U == dspi->resource->instance)
1038 {
1039 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL;
1040 }
1041 #endif /* DSPI1 PCS select configuration */
1042 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
1043 if (2U == dspi->resource->instance)
1044 {
1045 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL;
1046 }
1047 #endif /* DSPI2 PCS select configuration */
1048 }
1049 else
1050 {
1051 /* DSPI slave use Ctar0 setting and slave can only use PCS0. */
1052 xfer.configFlags = (uint32_t)kDSPI_SlaveCtar0;
1053 }
1054
1055 if (DSPI_IsMaster(dspi->resource->base))
1056 {
1057 status = DSPI_MasterTransferNonBlocking(dspi->resource->base, &dspi->handle->masterHandle, &xfer);
1058 }
1059 else
1060 {
1061 status = DSPI_SlaveTransferNonBlocking(dspi->resource->base, &dspi->handle->slaveHandle, &xfer);
1062 }
1063
1064 switch (status)
1065 {
1066 case kStatus_Success:
1067 ret = ARM_DRIVER_OK;
1068 break;
1069 case kStatus_InvalidArgument:
1070 ret = ARM_DRIVER_ERROR_PARAMETER;
1071 break;
1072 case kStatus_DSPI_Busy:
1073 ret = ARM_DRIVER_ERROR_BUSY;
1074 break;
1075 default:
1076 ret = ARM_DRIVER_ERROR;
1077 break;
1078 }
1079
1080 return ret;
1081 }
1082
DSPI_InterruptTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_dspi_interrupt_driver_state_t * dspi)1083 static int32_t DSPI_InterruptTransfer(const void *data_out,
1084 void *data_in,
1085 uint32_t num,
1086 cmsis_dspi_interrupt_driver_state_t *dspi)
1087 {
1088 int32_t ret;
1089 status_t status;
1090 dspi_transfer_t xfer = {0};
1091 uint32_t datawidth =
1092 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
1093
1094 xfer.txData = (uint8_t *)data_out;
1095 xfer.rxData = (uint8_t *)data_in;
1096 xfer.dataSize = num * ((datawidth + 8U) / 8U);
1097
1098 if (DSPI_IsMaster(dspi->resource->base))
1099 {
1100 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
1101 if (0U == dspi->resource->instance)
1102 {
1103 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL;
1104 }
1105 #endif /* DSPI0 PCS select configuration */
1106 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
1107 if (1U == dspi->resource->instance)
1108 {
1109 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL;
1110 }
1111 #endif /* DSPI1 PCS select configuration */
1112 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
1113 if (2U == dspi->resource->instance)
1114 {
1115 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL;
1116 }
1117 #endif /* DSPI2 PCS select configuration */
1118 }
1119 else
1120 {
1121 /* DSPI slave use Ctar0 setting and slave can only use PCS0. */
1122 xfer.configFlags = (uint32_t)kDSPI_SlaveCtar0;
1123 }
1124
1125 if (DSPI_IsMaster(dspi->resource->base))
1126 {
1127 status = DSPI_MasterTransferNonBlocking(dspi->resource->base, &dspi->handle->masterHandle, &xfer);
1128 }
1129 else
1130 {
1131 status = DSPI_SlaveTransferNonBlocking(dspi->resource->base, &dspi->handle->slaveHandle, &xfer);
1132 }
1133
1134 switch (status)
1135 {
1136 case kStatus_Success:
1137 ret = ARM_DRIVER_OK;
1138 break;
1139 case kStatus_InvalidArgument:
1140 ret = ARM_DRIVER_ERROR_PARAMETER;
1141 break;
1142 case kStatus_DSPI_Busy:
1143 ret = ARM_DRIVER_ERROR_BUSY;
1144 break;
1145 default:
1146 ret = ARM_DRIVER_ERROR;
1147 break;
1148 }
1149
1150 return ret;
1151 }
DSPI_InterruptGetCount(cmsis_dspi_interrupt_driver_state_t * dspi)1152 static uint32_t DSPI_InterruptGetCount(cmsis_dspi_interrupt_driver_state_t *dspi)
1153 {
1154 uint32_t cnt;
1155 uint32_t datawidth =
1156 (dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT;
1157
1158 if (DSPI_IsMaster(dspi->resource->base))
1159 {
1160 cnt = dspi->handle->masterHandle.totalByteCount - dspi->handle->masterHandle.remainingReceiveByteCount;
1161 }
1162 else
1163 {
1164 cnt = dspi->handle->slaveHandle.totalByteCount - dspi->handle->slaveHandle.remainingReceiveByteCount;
1165 }
1166 cnt /= ((datawidth + 8U) / 8U);
1167
1168 return cnt;
1169 }
1170
DSPI_InterruptControl(uint32_t control,uint32_t arg,cmsis_dspi_interrupt_driver_state_t * dspi)1171 static int32_t DSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_dspi_interrupt_driver_state_t *dspi)
1172 {
1173 int32_t result = ARM_DRIVER_OK;
1174 bool isContinue = false;
1175 if (0U == (dspi->flags & (uint8_t)SPI_FLAG_POWER))
1176 {
1177 return ARM_DRIVER_ERROR;
1178 }
1179
1180 switch (control & ARM_SPI_CONTROL_Msk)
1181 {
1182 case ARM_SPI_MODE_INACTIVE:
1183 DSPI_Enable(dspi->resource->base, false);
1184 result = ARM_DRIVER_OK;
1185 break;
1186
1187 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */
1188 DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Master);
1189 DSPI_MasterTransferCreateHandle(dspi->resource->base, &dspi->handle->masterHandle,
1190 KSDK_DSPI_MasterInterruptCallback, (void *)dspi->event);
1191 dspi->baudRate_Bps = arg;
1192 dspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1193 isContinue = true;
1194 break;
1195
1196 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */
1197 DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Slave);
1198 DSPI_SlaveTransferCreateHandle(dspi->resource->base, &dspi->handle->slaveHandle,
1199 KSDK_DSPI_SlaveInterruptCallback, (void *)dspi->event);
1200
1201 dspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1202 isContinue = true;
1203 break;
1204
1205 case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */
1206 if (!DSPI_IsMaster(dspi->resource->base))
1207 {
1208 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1209 break;
1210 }
1211
1212 result = (int32_t)dspi->baudRate_Bps;
1213 break;
1214
1215 case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
1216 if (!DSPI_IsMaster(dspi->resource->base))
1217 {
1218 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1219 break;
1220 }
1221 if (0U == DSPI_MasterSetBaudRate(dspi->resource->base, kDSPI_Ctar0, arg, dspi->resource->GetFreq()))
1222 {
1223 result = ARM_DRIVER_ERROR;
1224 break;
1225 }
1226
1227 dspi->baudRate_Bps = arg;
1228 break;
1229
1230 case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */
1231 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1232 break;
1233
1234 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
1235 if (DSPI_IsMaster(dspi->resource->base))
1236 {
1237 DSPI_MasterTransferAbort(dspi->resource->base, &dspi->handle->masterHandle);
1238 }
1239 else
1240 {
1241 DSPI_SlaveTransferAbort(dspi->resource->base, &dspi->handle->slaveHandle);
1242 }
1243 result = ARM_DRIVER_OK;
1244 break;
1245
1246 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
1247 DSPI_SetDummyData(dspi->resource->base, (uint8_t)arg);
1248 result = ARM_DRIVER_OK;
1249 break;
1250
1251 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
1252 /* Mode is not supported by current driver. */
1253 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1254 break;
1255
1256 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
1257 /* Mode is not supported by current driver. */
1258 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1259 break;
1260
1261 default:
1262 isContinue = true;
1263 break;
1264 }
1265
1266 if (isContinue)
1267 {
1268 result = DSPI_CommonControl(control, dspi->baudRate_Bps, dspi->resource, &dspi->flags);
1269 }
1270 return result;
1271 }
1272
DSPI_InterruptGetStatus(cmsis_dspi_interrupt_driver_state_t * dspi)1273 static ARM_SPI_STATUS DSPI_InterruptGetStatus(cmsis_dspi_interrupt_driver_state_t *dspi)
1274 {
1275 ARM_SPI_STATUS stat = {0};
1276 uint32_t ksdk_dspi_status = DSPI_GetStatusFlags(dspi->resource->base);
1277
1278 if (DSPI_IsMaster(dspi->resource->base))
1279 {
1280 stat.busy = ((dspi->handle->masterHandle.remainingSendByteCount > 0U) ||
1281 (dspi->handle->masterHandle.remainingReceiveByteCount > 0U)) ?
1282 (1U) :
1283 (0U);
1284 }
1285 else
1286 {
1287 stat.busy = ((dspi->handle->slaveHandle.remainingSendByteCount > 0U) ||
1288 (dspi->handle->slaveHandle.remainingReceiveByteCount > 0U)) ?
1289 (1U) :
1290 (0U);
1291 }
1292 stat.data_lost = (((ksdk_dspi_status & (uint32_t)kDSPI_TxFifoUnderflowFlag) != 0U) ||
1293 ((ksdk_dspi_status & (uint32_t)kDSPI_RxFifoOverflowFlag) != 0U)) ?
1294 (1U) :
1295 (0U);
1296 stat.mode_fault = 0U;
1297 stat.reserved = 0U;
1298
1299 return stat;
1300 }
1301
1302 #endif
1303
1304 #if defined(DSPI0) && defined(RTE_SPI0) && RTE_SPI0
1305
1306 /* User needs to provide the implementation for DSPI0_GetFreq/InitPins/DeinitPins
1307 in the application for enabling according instance. */
1308 extern uint32_t DSPI0_GetFreq(void);
1309
1310 static cmsis_dspi_resource_t DSPI0_Resource = {DSPI0, 0, DSPI0_GetFreq};
1311
1312 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1313
1314 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1315 static cmsis_dspi_edma_resource_t DSPI0_EdmaResource = {
1316 RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_TX_DMAMUX_BASE, RTE_SPI0_DMA_TX_PERI_SEL,
1317 RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH, RTE_SPI0_DMA_RX_DMAMUX_BASE, RTE_SPI0_DMA_RX_PERI_SEL,
1318 RTE_SPI0_DMA_LINK_DMA_BASE, RTE_SPI0_DMA_LINK_CH};
1319 static cmsis_dspi_edma_handle_t DSPI0_EdmaHandle;
1320
1321 static edma_handle_t DSPI0_EdmaRxRegToRxDataHandle;
1322 static edma_handle_t DSPI0_EedmaTxDataToIntermediaryHandle;
1323 static edma_handle_t DSPI0_EedmaIntermediaryToTxRegHandle;
1324 static edma_handle_t DSPI0_EedmaTxDataToTxRegHandle;
1325
1326 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1327 ARMCC_SECTION("dspi0_edma_driver_state")
1328 static cmsis_dspi_edma_driver_state_t DSPI0_EdmaDriverState = {
1329 #else
1330 static cmsis_dspi_edma_driver_state_t DSPI0_EdmaDriverState = {
1331 #endif
1332 &DSPI0_Resource,
1333 &DSPI0_EdmaResource,
1334 &DSPI0_EdmaHandle,
1335 &DSPI0_EdmaRxRegToRxDataHandle,
1336 &DSPI0_EedmaTxDataToIntermediaryHandle,
1337 &DSPI0_EedmaIntermediaryToTxRegHandle,
1338 &DSPI0_EedmaTxDataToTxRegHandle,
1339 };
1340
DSPI0_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1341 static int32_t DSPI0_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1342 {
1343 #ifdef RTE_SPI0_PIN_INIT
1344 RTE_SPI0_PIN_INIT();
1345 #endif
1346 return DSPI_EdmaInitialize(cb_event, &DSPI0_EdmaDriverState);
1347 }
1348
DSPI0_EdmaUninitialize(void)1349 static int32_t DSPI0_EdmaUninitialize(void)
1350 {
1351 #ifdef RTE_SPI0_PIN_DEINIT
1352 RTE_SPI0_PIN_DEINIT();
1353 #endif
1354 return DSPI_EdmaUninitialize(&DSPI0_EdmaDriverState);
1355 }
1356
DSPI0_EdmaPowerControl(ARM_POWER_STATE state)1357 static int32_t DSPI0_EdmaPowerControl(ARM_POWER_STATE state)
1358 {
1359 return DSPI_EdmaPowerControl(state, &DSPI0_EdmaDriverState);
1360 }
1361
DSPI0_EdmaSend(const void * data,uint32_t num)1362 static int32_t DSPI0_EdmaSend(const void *data, uint32_t num)
1363 {
1364 return DSPI_EdmaSend(data, num, &DSPI0_EdmaDriverState);
1365 }
1366
DSPI0_EdmaReceive(void * data,uint32_t num)1367 static int32_t DSPI0_EdmaReceive(void *data, uint32_t num)
1368 {
1369 return DSPI_EdmaReceive(data, num, &DSPI0_EdmaDriverState);
1370 }
1371
DSPI0_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1372 static int32_t DSPI0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1373 {
1374 return DSPI_EdmaTransfer(data_out, data_in, num, &DSPI0_EdmaDriverState);
1375 }
1376
DSPI0_EdmaGetCount(void)1377 static uint32_t DSPI0_EdmaGetCount(void)
1378 {
1379 return DSPI_EdmaGetCount(&DSPI0_EdmaDriverState);
1380 }
1381
DSPI0_EdmaControl(uint32_t control,uint32_t arg)1382 static int32_t DSPI0_EdmaControl(uint32_t control, uint32_t arg)
1383 {
1384 return DSPI_EdmaControl(control, arg, &DSPI0_EdmaDriverState);
1385 }
1386
DSPI0_EdmaGetStatus(void)1387 static ARM_SPI_STATUS DSPI0_EdmaGetStatus(void)
1388 {
1389 return DSPI_EdmaGetStatus(&DSPI0_EdmaDriverState);
1390 }
1391
1392 #endif
1393
1394 #else
1395 static cmsis_dspi_handle_t DSPI0_Handle;
1396
1397 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1398 ARMCC_SECTION("dspi0_interrupt_driver_state")
1399 static cmsis_dspi_interrupt_driver_state_t DSPI0_InterruptDriverState = {
1400 #else
1401 static cmsis_dspi_interrupt_driver_state_t DSPI0_InterruptDriverState = {
1402 #endif
1403 &DSPI0_Resource,
1404 &DSPI0_Handle,
1405 };
1406
DSPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1407 static int32_t DSPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1408 {
1409 #ifdef RTE_SPI0_PIN_INIT
1410 RTE_SPI0_PIN_INIT();
1411 #endif
1412 return DSPI_InterruptInitialize(cb_event, &DSPI0_InterruptDriverState);
1413 }
1414
DSPI0_InterruptUninitialize(void)1415 static int32_t DSPI0_InterruptUninitialize(void)
1416 {
1417 #ifdef RTE_SPI0_PIN_DEINIT
1418 RTE_SPI0_PIN_DEINIT();
1419 #endif
1420 return DSPI_InterruptUninitialize(&DSPI0_InterruptDriverState);
1421 }
1422
DSPI0_InterruptPowerControl(ARM_POWER_STATE state)1423 static int32_t DSPI0_InterruptPowerControl(ARM_POWER_STATE state)
1424 {
1425 return DSPI_InterruptPowerControl(state, &DSPI0_InterruptDriverState);
1426 }
1427
DSPI0_InterruptSend(const void * data,uint32_t num)1428 static int32_t DSPI0_InterruptSend(const void *data, uint32_t num)
1429 {
1430 return DSPI_InterruptSend(data, num, &DSPI0_InterruptDriverState);
1431 }
1432
DSPI0_InterruptReceive(void * data,uint32_t num)1433 static int32_t DSPI0_InterruptReceive(void *data, uint32_t num)
1434 {
1435 return DSPI_InterruptReceive(data, num, &DSPI0_InterruptDriverState);
1436 }
1437
DSPI0_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1438 static int32_t DSPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1439 {
1440 return DSPI_InterruptTransfer(data_out, data_in, num, &DSPI0_InterruptDriverState);
1441 }
1442
DSPI0_InterruptGetCount(void)1443 static uint32_t DSPI0_InterruptGetCount(void)
1444 {
1445 return DSPI_InterruptGetCount(&DSPI0_InterruptDriverState);
1446 }
1447
DSPI0_InterruptControl(uint32_t control,uint32_t arg)1448 static int32_t DSPI0_InterruptControl(uint32_t control, uint32_t arg)
1449 {
1450 return DSPI_InterruptControl(control, arg, &DSPI0_InterruptDriverState);
1451 }
1452
DSPI0_InterruptGetStatus(void)1453 static ARM_SPI_STATUS DSPI0_InterruptGetStatus(void)
1454 {
1455 return DSPI_InterruptGetStatus(&DSPI0_InterruptDriverState);
1456 }
1457
1458 #endif
1459
1460 ARM_DRIVER_SPI Driver_SPI0 = {DSPIx_GetVersion, DSPIx_GetCapabilities,
1461 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1462 DSPI0_EdmaInitialize, DSPI0_EdmaUninitialize, DSPI0_EdmaPowerControl, DSPI0_EdmaSend,
1463 DSPI0_EdmaReceive, DSPI0_EdmaTransfer, DSPI0_EdmaGetCount, DSPI0_EdmaControl,
1464 DSPI0_EdmaGetStatus
1465 #else
1466 DSPI0_InterruptInitialize,
1467 DSPI0_InterruptUninitialize,
1468 DSPI0_InterruptPowerControl,
1469 DSPI0_InterruptSend,
1470 DSPI0_InterruptReceive,
1471 DSPI0_InterruptTransfer,
1472 DSPI0_InterruptGetCount,
1473 DSPI0_InterruptControl,
1474 DSPI0_InterruptGetStatus
1475 #endif
1476 };
1477
1478 #endif /* DSPI0 */
1479
1480 #if defined(DSPI1) && defined(RTE_SPI1) && RTE_SPI1
1481
1482 /* User needs to provide the implementation for DSPI1_GetFreq/InitPins/DeinitPins
1483 in the application for enabling according instance. */
1484 extern uint32_t DSPI1_GetFreq(void);
1485
1486 static cmsis_dspi_resource_t DSPI1_Resource = {DSPI1, 1, DSPI1_GetFreq};
1487
1488 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1489
1490 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1491 static cmsis_dspi_edma_resource_t DSPI1_EdmaResource = {
1492 RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_DMAMUX_BASE, RTE_SPI1_DMA_TX_PERI_SEL,
1493 RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_DMAMUX_BASE, RTE_SPI1_DMA_RX_PERI_SEL,
1494 RTE_SPI1_DMA_LINK_DMA_BASE, RTE_SPI1_DMA_LINK_CH};
1495 static cmsis_dspi_edma_handle_t DSPI1_EdmaHandle;
1496
1497 static edma_handle_t DSPI1_EdmaRxRegToRxDataHandle;
1498 static edma_handle_t DSPI1_EedmaTxDataToIntermediaryHandle;
1499 static edma_handle_t DSPI1_EedmaIntermediaryToTxRegHandle;
1500 static edma_handle_t DSPI1_EedmaTxDataToTxRegHandle;
1501
1502 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1503 ARMCC_SECTION("dspi1_edma_driver_state")
1504 static cmsis_dspi_edma_driver_state_t DSPI1_EdmaDriverState = {
1505 #else
1506 static cmsis_dspi_edma_driver_state_t DSPI1_EdmaDriverState = {
1507 #endif
1508 &DSPI1_Resource,
1509 &DSPI1_EdmaResource,
1510 &DSPI1_EdmaHandle,
1511 &DSPI1_EdmaRxRegToRxDataHandle,
1512 &DSPI1_EedmaTxDataToIntermediaryHandle,
1513 &DSPI1_EedmaIntermediaryToTxRegHandle,
1514 &DSPI1_EedmaTxDataToTxRegHandle,
1515 };
1516
DSPI1_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1517 static int32_t DSPI1_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1518 {
1519 #ifdef RTE_SPI1_PIN_INIT
1520 RTE_SPI1_PIN_INIT();
1521 #endif
1522 return DSPI_EdmaInitialize(cb_event, &DSPI1_EdmaDriverState);
1523 }
1524
DSPI1_EdmaUninitialize(void)1525 static int32_t DSPI1_EdmaUninitialize(void)
1526 {
1527 #ifdef RTE_SPI1_PIN_DEINIT
1528 RTE_SPI1_PIN_DEINIT();
1529 #endif
1530 return DSPI_EdmaUninitialize(&DSPI1_EdmaDriverState);
1531 }
1532
DSPI1_EdmaPowerControl(ARM_POWER_STATE state)1533 static int32_t DSPI1_EdmaPowerControl(ARM_POWER_STATE state)
1534 {
1535 return DSPI_EdmaPowerControl(state, &DSPI1_EdmaDriverState);
1536 }
1537
DSPI1_EdmaSend(const void * data,uint32_t num)1538 static int32_t DSPI1_EdmaSend(const void *data, uint32_t num)
1539 {
1540 return DSPI_EdmaSend(data, num, &DSPI1_EdmaDriverState);
1541 }
1542
DSPI1_EdmaReceive(void * data,uint32_t num)1543 static int32_t DSPI1_EdmaReceive(void *data, uint32_t num)
1544 {
1545 return DSPI_EdmaReceive(data, num, &DSPI1_EdmaDriverState);
1546 }
1547
DSPI1_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1548 static int32_t DSPI1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1549 {
1550 return DSPI_EdmaTransfer(data_out, data_in, num, &DSPI1_EdmaDriverState);
1551 }
1552
DSPI1_EdmaGetCount(void)1553 static uint32_t DSPI1_EdmaGetCount(void)
1554 {
1555 return DSPI_EdmaGetCount(&DSPI1_EdmaDriverState);
1556 }
1557
DSPI1_EdmaControl(uint32_t control,uint32_t arg)1558 static int32_t DSPI1_EdmaControl(uint32_t control, uint32_t arg)
1559 {
1560 return DSPI_EdmaControl(control, arg, &DSPI1_EdmaDriverState);
1561 }
1562
DSPI1_EdmaGetStatus(void)1563 static ARM_SPI_STATUS DSPI1_EdmaGetStatus(void)
1564 {
1565 return DSPI_EdmaGetStatus(&DSPI1_EdmaDriverState);
1566 }
1567
1568 #endif
1569
1570 #else
1571
1572 static cmsis_dspi_handle_t DSPI1_Handle;
1573
1574 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1575 ARMCC_SECTION("dspi1_interrupt_driver_state")
1576 static cmsis_dspi_interrupt_driver_state_t DSPI1_InterruptDriverState = {
1577 #else
1578 static cmsis_dspi_interrupt_driver_state_t DSPI1_InterruptDriverState = {
1579 #endif
1580 &DSPI1_Resource,
1581 &DSPI1_Handle,
1582 };
1583
DSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1584 static int32_t DSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1585 {
1586 #ifdef RTE_SPI1_PIN_INIT
1587 RTE_SPI1_PIN_INIT();
1588 #endif
1589 return DSPI_InterruptInitialize(cb_event, &DSPI1_InterruptDriverState);
1590 }
1591
DSPI1_InterruptUninitialize(void)1592 static int32_t DSPI1_InterruptUninitialize(void)
1593 {
1594 #ifdef RTE_SPI1_PIN_DEINIT
1595 RTE_SPI1_PIN_DEINIT();
1596 #endif
1597 return DSPI_InterruptUninitialize(&DSPI1_InterruptDriverState);
1598 }
1599
DSPI1_InterruptPowerControl(ARM_POWER_STATE state)1600 static int32_t DSPI1_InterruptPowerControl(ARM_POWER_STATE state)
1601 {
1602 return DSPI_InterruptPowerControl(state, &DSPI1_InterruptDriverState);
1603 }
1604
DSPI1_InterruptSend(const void * data,uint32_t num)1605 static int32_t DSPI1_InterruptSend(const void *data, uint32_t num)
1606 {
1607 return DSPI_InterruptSend(data, num, &DSPI1_InterruptDriverState);
1608 }
1609
DSPI1_InterruptReceive(void * data,uint32_t num)1610 static int32_t DSPI1_InterruptReceive(void *data, uint32_t num)
1611 {
1612 return DSPI_InterruptReceive(data, num, &DSPI1_InterruptDriverState);
1613 }
1614
DSPI1_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1615 static int32_t DSPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1616 {
1617 return DSPI_InterruptTransfer(data_out, data_in, num, &DSPI1_InterruptDriverState);
1618 }
1619
DSPI1_InterruptGetCount(void)1620 static uint32_t DSPI1_InterruptGetCount(void)
1621 {
1622 return DSPI_InterruptGetCount(&DSPI1_InterruptDriverState);
1623 }
1624
DSPI1_InterruptControl(uint32_t control,uint32_t arg)1625 static int32_t DSPI1_InterruptControl(uint32_t control, uint32_t arg)
1626 {
1627 return DSPI_InterruptControl(control, arg, &DSPI1_InterruptDriverState);
1628 }
1629
DSPI1_InterruptGetStatus(void)1630 static ARM_SPI_STATUS DSPI1_InterruptGetStatus(void)
1631 {
1632 return DSPI_InterruptGetStatus(&DSPI1_InterruptDriverState);
1633 }
1634
1635 #endif
1636
1637 ARM_DRIVER_SPI Driver_SPI1 = {DSPIx_GetVersion, DSPIx_GetCapabilities,
1638 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1639 DSPI1_EdmaInitialize, DSPI1_EdmaUninitialize, DSPI1_EdmaPowerControl, DSPI1_EdmaSend,
1640 DSPI1_EdmaReceive, DSPI1_EdmaTransfer, DSPI1_EdmaGetCount, DSPI1_EdmaControl,
1641 DSPI1_EdmaGetStatus
1642 #else
1643 DSPI1_InterruptInitialize,
1644 DSPI1_InterruptUninitialize,
1645 DSPI1_InterruptPowerControl,
1646 DSPI1_InterruptSend,
1647 DSPI1_InterruptReceive,
1648 DSPI1_InterruptTransfer,
1649 DSPI1_InterruptGetCount,
1650 DSPI1_InterruptControl,
1651 DSPI1_InterruptGetStatus
1652 #endif
1653 };
1654
1655 #endif /* DSPI1 */
1656
1657 #if defined(DSPI2) && defined(RTE_SPI2) && RTE_SPI2
1658
1659 /* User needs to provide the implementation for DSPI2_GetFreq/InitPins/DeinitPins
1660 in the application for enabling according instance. */
1661 extern uint32_t DSPI2_GetFreq(void);
1662
1663 static cmsis_dspi_resource_t DSPI2_Resource = {DSPI2, 2, DSPI2_GetFreq};
1664
1665 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1666
1667 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1668 static cmsis_dspi_edma_resource_t DSPI2_EdmaResource = {
1669 RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_TX_DMAMUX_BASE, RTE_SPI2_DMA_TX_PERI_SEL,
1670
1671 RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, RTE_SPI2_DMA_RX_DMAMUX_BASE, RTE_SPI2_DMA_RX_PERI_SEL,
1672
1673 RTE_SPI2_DMA_LINK_DMA_BASE, RTE_SPI2_DMA_LINK_CH};
1674
1675 static cmsis_dspi_edma_handle_t DSPI2_EdmaHandle;
1676
1677 static edma_handle_t DSPI2_EdmaRxRegToRxDataHandle;
1678 static edma_handle_t DSPI2_EedmaTxDataToIntermediaryHandle;
1679 static edma_handle_t DSPI2_EedmaIntermediaryToTxRegHandle;
1680 static edma_handle_t DSPI2_EedmaTxDataToTxRegHandle;
1681
1682 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1683 ARMCC_SECTION("dspi2_edma_driver_state")
1684 static cmsis_dspi_edma_driver_state_t DSPI2_EdmaDriverState = {
1685 #else
1686 static cmsis_dspi_edma_driver_state_t DSPI2_EdmaDriverState = {
1687 #endif
1688 &DSPI2_Resource,
1689 &DSPI2_EdmaResource,
1690 &DSPI2_EdmaHandle,
1691 &DSPI2_EdmaRxRegToRxDataHandle,
1692 &DSPI2_EedmaTxDataToIntermediaryHandle,
1693 &DSPI2_EedmaIntermediaryToTxRegHandle,
1694 &DSPI2_EedmaTxDataToTxRegHandle,
1695 };
1696
DSPI2_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1697 static int32_t DSPI2_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1698 {
1699 #ifdef RTE_SPI2_PIN_INIT
1700 RTE_SPI2_PIN_INIT();
1701 #endif
1702 return DSPI_EdmaInitialize(cb_event, &DSPI2_EdmaDriverState);
1703 }
1704
DSPI2_EdmaUninitialize(void)1705 static int32_t DSPI2_EdmaUninitialize(void)
1706 {
1707 #ifdef RTE_SPI2_PIN_DEINIT
1708 RTE_SPI2_PIN_DEINIT();
1709 #endif
1710 return DSPI_EdmaUninitialize(&DSPI2_EdmaDriverState);
1711 }
1712
DSPI2_EdmaPowerControl(ARM_POWER_STATE state)1713 static int32_t DSPI2_EdmaPowerControl(ARM_POWER_STATE state)
1714 {
1715 return DSPI_EdmaPowerControl(state, &DSPI2_EdmaDriverState);
1716 }
1717
DSPI2_EdmaSend(const void * data,uint32_t num)1718 static int32_t DSPI2_EdmaSend(const void *data, uint32_t num)
1719 {
1720 return DSPI_EdmaSend(data, num, &DSPI2_EdmaDriverState);
1721 }
1722
DSPI2_EdmaReceive(void * data,uint32_t num)1723 static int32_t DSPI2_EdmaReceive(void *data, uint32_t num)
1724 {
1725 return DSPI_EdmaReceive(data, num, &DSPI2_EdmaDriverState);
1726 }
1727
DSPI2_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1728 static int32_t DSPI2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1729 {
1730 return DSPI_EdmaTransfer(data_out, data_in, num, &DSPI2_EdmaDriverState);
1731 }
1732
DSPI2_EdmaGetCount(void)1733 static uint32_t DSPI2_EdmaGetCount(void)
1734 {
1735 return DSPI_EdmaGetCount(&DSPI2_EdmaDriverState);
1736 }
1737
DSPI2_EdmaControl(uint32_t control,uint32_t arg)1738 static int32_t DSPI2_EdmaControl(uint32_t control, uint32_t arg)
1739 {
1740 return DSPI_EdmaControl(control, arg, &DSPI2_EdmaDriverState);
1741 }
1742
DSPI2_EdmaGetStatus(void)1743 static ARM_SPI_STATUS DSPI2_EdmaGetStatus(void)
1744 {
1745 return DSPI_EdmaGetStatus(&DSPI2_EdmaDriverState);
1746 }
1747
1748 #endif
1749
1750 #else
1751
1752 static cmsis_dspi_handle_t DSPI2_Handle;
1753
1754 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1755 ARMCC_SECTION("dspi2_interrupt_driver_state")
1756 static cmsis_dspi_interrupt_driver_state_t DSPI2_InterruptDriverState = {
1757 #else
1758 static cmsis_dspi_interrupt_driver_state_t DSPI2_InterruptDriverState = {
1759 #endif
1760 &DSPI2_Resource,
1761 &DSPI2_Handle,
1762 };
1763
DSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1764 static int32_t DSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1765 {
1766 #ifdef RTE_SPI2_PIN_INIT
1767 RTE_SPI2_PIN_INIT();
1768 #endif
1769 return DSPI_InterruptInitialize(cb_event, &DSPI2_InterruptDriverState);
1770 }
1771
DSPI2_InterruptUninitialize(void)1772 static int32_t DSPI2_InterruptUninitialize(void)
1773 {
1774 #ifdef RTE_SPI2_PIN_DEINIT
1775 RTE_SPI2_PIN_DEINIT();
1776 #endif
1777 return DSPI_InterruptUninitialize(&DSPI2_InterruptDriverState);
1778 }
1779
DSPI2_InterruptPowerControl(ARM_POWER_STATE state)1780 static int32_t DSPI2_InterruptPowerControl(ARM_POWER_STATE state)
1781 {
1782 return DSPI_InterruptPowerControl(state, &DSPI2_InterruptDriverState);
1783 }
1784
DSPI2_InterruptSend(const void * data,uint32_t num)1785 static int32_t DSPI2_InterruptSend(const void *data, uint32_t num)
1786 {
1787 return DSPI_InterruptSend(data, num, &DSPI2_InterruptDriverState);
1788 }
1789
DSPI2_InterruptReceive(void * data,uint32_t num)1790 static int32_t DSPI2_InterruptReceive(void *data, uint32_t num)
1791 {
1792 return DSPI_InterruptReceive(data, num, &DSPI2_InterruptDriverState);
1793 }
1794
DSPI2_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1795 static int32_t DSPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1796 {
1797 return DSPI_InterruptTransfer(data_out, data_in, num, &DSPI2_InterruptDriverState);
1798 }
1799
DSPI2_InterruptGetCount(void)1800 static uint32_t DSPI2_InterruptGetCount(void)
1801 {
1802 return DSPI_InterruptGetCount(&DSPI2_InterruptDriverState);
1803 }
1804
DSPI2_InterruptControl(uint32_t control,uint32_t arg)1805 static int32_t DSPI2_InterruptControl(uint32_t control, uint32_t arg)
1806 {
1807 return DSPI_InterruptControl(control, arg, &DSPI2_InterruptDriverState);
1808 }
1809
DSPI2_InterruptGetStatus(void)1810 static ARM_SPI_STATUS DSPI2_InterruptGetStatus(void)
1811 {
1812 return DSPI_InterruptGetStatus(&DSPI2_InterruptDriverState);
1813 }
1814 #endif
1815
1816 ARM_DRIVER_SPI Driver_SPI2 = {DSPIx_GetVersion, DSPIx_GetCapabilities,
1817 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1818 DSPI2_EdmaInitialize, DSPI2_EdmaUninitialize, DSPI2_EdmaPowerControl, DSPI2_EdmaSend,
1819 DSPI2_EdmaReceive, DSPI2_EdmaTransfer, DSPI2_EdmaGetCount, DSPI2_EdmaControl,
1820 DSPI2_EdmaGetStatus
1821 #else
1822 DSPI2_InterruptInitialize,
1823 DSPI2_InterruptUninitialize,
1824 DSPI2_InterruptPowerControl,
1825 DSPI2_InterruptSend,
1826 DSPI2_InterruptReceive,
1827 DSPI2_InterruptTransfer,
1828 DSPI2_InterruptGetCount,
1829 DSPI2_InterruptControl,
1830 DSPI2_InterruptGetStatus
1831 #endif
1832 };
1833
1834 #endif /* DSPI2 */
1835
