1 /*
2  * Copyright 2022-2023 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /***********************************************************************************************************************
9  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11  **********************************************************************************************************************/
12 /*
13  * How to setup clock using clock driver functions:
14  *
15  * 1. Setup clock sources.
16  *
17  * 2. Set up wait states of the flash.
18  *
19  * 3. Set up all dividers.
20  *
21  * 4. Set up all selectors to provide selected clocks.
22  *
23  */
24 
25 /* clang-format off */
26 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
27 !!GlobalInfo
28 product: Clocks v12.0
29 processor: MCXN947
30 package_id: MCXN947VDF
31 mcu_data: ksdk2_0
32 processor_version: 0.14.14
33 board: FRDM-MCXN947
34  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
35 /* clang-format on */
36 
37 #include "fsl_clock.h"
38 #include "clock_config.h"
39 #include "fsl_spc.h"
40 
41 /*******************************************************************************
42  * Definitions
43  ******************************************************************************/
44 
45 /*******************************************************************************
46  * Variables
47  ******************************************************************************/
48 /* System clock frequency. */
49 extern uint32_t SystemCoreClock;
50 
51 /*******************************************************************************
52  ************************ BOARD_InitBootClocks function ************************
53  ******************************************************************************/
BOARD_InitBootClocks(void)54 void BOARD_InitBootClocks(void)
55 {
56     BOARD_BootClockPLL150M();
57 }
58 
59 /*******************************************************************************
60  ******************** Configuration BOARD_BootClockFRO12M **********************
61  ******************************************************************************/
62 /* clang-format off */
63 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
64 !!Configuration
65 name: BOARD_BootClockFRO12M
66 outputs:
67 - {id: CLK_144M_clock.outFreq, value: 144 MHz}
68 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
69 - {id: FRO_12M_clock.outFreq, value: 12 MHz}
70 - {id: MAIN_clock.outFreq, value: 12 MHz}
71 - {id: Slow_clock.outFreq, value: 3 MHz}
72 - {id: System_clock.outFreq, value: 12 MHz}
73 - {id: gdet_clock.outFreq, value: 48 MHz}
74 - {id: trng_clock.outFreq, value: 48 MHz}
75 settings:
76 - {id: SCGMode, value: SIRC}
77 - {id: SCG.SCSSEL.sel, value: SCG.SIRC}
78 - {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
79 - {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
80 - {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
81  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
82 /* clang-format on */
83 
84 /*******************************************************************************
85  * Variables for BOARD_BootClockFRO12M configuration
86  ******************************************************************************/
87 /*******************************************************************************
88  * Code for BOARD_BootClockFRO12M configuration
89  ******************************************************************************/
BOARD_BootClockFRO12M(void)90 void BOARD_BootClockFRO12M(void)
91 {
92     CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
93 
94     /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
95     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
96 
97     /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */
98     spc_active_mode_core_ldo_option_t ldoOpt = {
99       .CoreLDOVoltage       = kSPC_CoreLDO_MidDriveVoltage,
100       .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
101     };
102     SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
103     /* Set the DCDC VDD regulator to 1.0 V voltage level */
104     spc_active_mode_dcdc_option_t dcdcOpt = {
105       .DCDCVoltage       = kSPC_DCDC_MidVoltage,
106       .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
107     };
108     SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
109     /* Configure Flash wait-states to support 1V voltage level and 12000000Hz frequency */;
110     FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
111     /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */
112     spc_sram_voltage_config_t sramCfg = {
113       .operateVoltage       = kSPC_sramOperateAt1P0V,
114       .requestVoltageUpdate = true,
115     };
116     SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
117 
118     /*!< Set up clock selectors  */
119 
120     /*!< Set up dividers */
121     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
122 
123     /* Set SystemCoreClock variable */
124     SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
125 }
126 
127 /*******************************************************************************
128  ******************* Configuration BOARD_BootClockFROHF48M *********************
129  ******************************************************************************/
130 /* clang-format off */
131 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
132 !!Configuration
133 name: BOARD_BootClockFROHF48M
134 outputs:
135 - {id: CLK_144M_clock.outFreq, value: 144 MHz}
136 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
137 - {id: FRO_12M_clock.outFreq, value: 12 MHz}
138 - {id: FRO_HF_clock.outFreq, value: 48 MHz}
139 - {id: MAIN_clock.outFreq, value: 48 MHz}
140 - {id: Slow_clock.outFreq, value: 12 MHz}
141 - {id: System_clock.outFreq, value: 48 MHz}
142 - {id: gdet_clock.outFreq, value: 48 MHz}
143 - {id: trng_clock.outFreq, value: 48 MHz}
144 settings:
145 - {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
146 - {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
147 - {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
148  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
149 /* clang-format on */
150 
151 /*******************************************************************************
152  * Variables for BOARD_BootClockFROHF48M configuration
153  ******************************************************************************/
154 /*******************************************************************************
155  * Code for BOARD_BootClockFROHF48M configuration
156  ******************************************************************************/
BOARD_BootClockFROHF48M(void)157 void BOARD_BootClockFROHF48M(void)
158 {
159     CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
160 
161     /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
162     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
163 
164     /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */
165     spc_active_mode_core_ldo_option_t ldoOpt = {
166       .CoreLDOVoltage       = kSPC_CoreLDO_MidDriveVoltage,
167       .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
168     };
169     SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
170     /* Set the DCDC VDD regulator to 1.0 V voltage level */
171     spc_active_mode_dcdc_option_t dcdcOpt = {
172       .DCDCVoltage       = kSPC_DCDC_MidVoltage,
173       .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
174     };
175     SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
176     /* Configure Flash wait-states to support 1V voltage level and 48000000Hz frequency */;
177     FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
178     /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */
179     spc_sram_voltage_config_t sramCfg = {
180       .operateVoltage       = kSPC_sramOperateAt1P0V,
181       .requestVoltageUpdate = true,
182     };
183     SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
184 
185     CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
186     /*!< Set up clock selectors  */
187     CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
188 
189     /*!< Set up dividers */
190     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
191 
192     /* Set SystemCoreClock variable */
193     SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
194 }
195 
196 /*******************************************************************************
197  ******************* Configuration BOARD_BootClockFROHF144M ********************
198  ******************************************************************************/
199 /* clang-format off */
200 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
201 !!Configuration
202 name: BOARD_BootClockFROHF144M
203 outputs:
204 - {id: CLK_144M_clock.outFreq, value: 144 MHz}
205 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
206 - {id: FRO_12M_clock.outFreq, value: 12 MHz}
207 - {id: FRO_HF_clock.outFreq, value: 144 MHz}
208 - {id: MAIN_clock.outFreq, value: 144 MHz}
209 - {id: Slow_clock.outFreq, value: 36 MHz}
210 - {id: System_clock.outFreq, value: 144 MHz}
211 - {id: gdet_clock.outFreq, value: 48 MHz}
212 - {id: trng_clock.outFreq, value: 48 MHz}
213 settings:
214 - {id: RunPowerMode, value: OD}
215 - {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
216 - {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
217 - {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
218 - {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
219 sources:
220 - {id: SCG.FIRC.outFreq, value: 144 MHz}
221  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
222 /* clang-format on */
223 
224 /*******************************************************************************
225  * Variables for BOARD_BootClockFROHF144M configuration
226  ******************************************************************************/
227 /*******************************************************************************
228  * Code for BOARD_BootClockFROHF144M configuration
229  ******************************************************************************/
BOARD_BootClockFROHF144M(void)230 void BOARD_BootClockFROHF144M(void)
231 {
232     CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
233 
234     /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
235     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
236 
237     /* Set the DCDC VDD regulator to 1.2 V voltage level */
238     spc_active_mode_dcdc_option_t dcdcOpt = {
239       .DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
240       .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
241     };
242     SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
243     /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
244     spc_active_mode_core_ldo_option_t ldoOpt = {
245       .CoreLDOVoltage       = kSPC_CoreLDO_OverDriveVoltage,
246       .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
247     };
248     SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
249     /* Configure Flash wait-states to support 1.2V voltage level and 144000000Hz frequency */;
250     FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
251     /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
252     spc_sram_voltage_config_t sramCfg = {
253       .operateVoltage       = kSPC_sramOperateAt1P2V,
254       .requestVoltageUpdate = true,
255     };
256     SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
257 
258     CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
259     /*!< Set up clock selectors  */
260     CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
261 
262     /*!< Set up dividers */
263     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
264 
265     /* Set SystemCoreClock variable */
266     SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
267 }
268 
269 /*******************************************************************************
270  ******************** Configuration BOARD_BootClockPLL150M *********************
271  ******************************************************************************/
272 /* clang-format off */
273 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
274 !!Configuration
275 name: BOARD_BootClockPLL150M
276 called_from_default_init: true
277 outputs:
278 - {id: CLK_144M_clock.outFreq, value: 144 MHz}
279 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
280 - {id: FRO_12M_clock.outFreq, value: 12 MHz}
281 - {id: FRO_HF_clock.outFreq, value: 48 MHz}
282 - {id: MAIN_clock.outFreq, value: 150 MHz}
283 - {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
284 - {id: Slow_clock.outFreq, value: 37.5 MHz}
285 - {id: System_clock.outFreq, value: 150 MHz}
286 - {id: gdet_clock.outFreq, value: 48 MHz}
287 - {id: trng_clock.outFreq, value: 48 MHz}
288 settings:
289 - {id: PLL0_Mode, value: Normal}
290 - {id: RunPowerMode, value: OD}
291 - {id: SCGMode, value: PLL0}
292 - {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
293 - {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
294 - {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
295 - {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
296 - {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
297 - {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
298 - {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
299  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
300 /* clang-format on */
301 
302 /*******************************************************************************
303  * Variables for BOARD_BootClockPLL150M configuration
304  ******************************************************************************/
305 /*******************************************************************************
306  * Code for BOARD_BootClockPLL150M configuration
307  ******************************************************************************/
BOARD_BootClockPLL150M(void)308 void BOARD_BootClockPLL150M(void)
309 {
310     CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
311 
312     /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
313     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
314 
315     /* Set the DCDC VDD regulator to 1.2 V voltage level */
316     spc_active_mode_dcdc_option_t dcdcOpt = {
317       .DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
318       .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
319     };
320     SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
321     /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
322     spc_active_mode_core_ldo_option_t ldoOpt = {
323       .CoreLDOVoltage       = kSPC_CoreLDO_OverDriveVoltage,
324       .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
325     };
326     SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
327     /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */;
328     FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
329     /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
330     spc_sram_voltage_config_t sramCfg = {
331       .operateVoltage       = kSPC_sramOperateAt1P2V,
332       .requestVoltageUpdate = true,
333     };
334     SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
335 
336     CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
337     /*!< Set up PLL0 */
338     const pll_setup_t pll0Setup = {
339         .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
340         .pllndiv = SCG_APLLNDIV_NDIV(8U),
341         .pllpdiv = SCG_APLLPDIV_PDIV(1U),
342         .pllmdiv = SCG_APLLMDIV_MDIV(50U),
343         .pllRate = 150000000U
344     };
345     CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
346     CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
347 
348     /*!< Set up clock selectors  */
349     CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
350 
351     /*!< Set up dividers */
352     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
353 
354     /* Set SystemCoreClock variable */
355     SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
356 }
357 
358 /*******************************************************************************
359  ******************** Configuration BOARD_BootClockPLL100M *********************
360  ******************************************************************************/
361 /* clang-format off */
362 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
363 !!Configuration
364 name: BOARD_BootClockPLL100M
365 outputs:
366 - {id: CLK_144M_clock.outFreq, value: 144 MHz}
367 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
368 - {id: CLK_IN_clock.outFreq, value: 24 MHz}
369 - {id: FRO_12M_clock.outFreq, value: 12 MHz}
370 - {id: MAIN_clock.outFreq, value: 100 MHz}
371 - {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
372 - {id: Slow_clock.outFreq, value: 25 MHz}
373 - {id: System_clock.outFreq, value: 100 MHz}
374 - {id: gdet_clock.outFreq, value: 48 MHz}
375 - {id: trng_clock.outFreq, value: 48 MHz}
376 settings:
377 - {id: PLL1_Mode, value: Normal}
378 - {id: RunPowerMode, value: SD}
379 - {id: SCGMode, value: PLL1}
380 - {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
381 - {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
382 - {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
383 - {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
384 - {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
385 - {id: SCG_SOSCCSR_ERFES_SEL, value: CryOsc}
386 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
387 - {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
388 - {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
389 sources:
390 - {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
391  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
392 /* clang-format on */
393 
394 /*******************************************************************************
395  * Variables for BOARD_BootClockPLL100M configuration
396  ******************************************************************************/
397 /*******************************************************************************
398  * Code for BOARD_BootClockPLL100M configuration
399  ******************************************************************************/
BOARD_BootClockPLL100M(void)400 void BOARD_BootClockPLL100M(void)
401 {
402     CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
403 
404     /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
405     CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
406 
407     /* Set the DCDC VDD regulator to 1.1 V voltage level */
408     spc_active_mode_dcdc_option_t dcdcOpt = {
409       .DCDCVoltage       = kSPC_DCDC_NormalVoltage,
410       .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
411     };
412     SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
413     /* Set the LDO_CORE VDD regulator to 1.1 V voltage level */
414     spc_active_mode_core_ldo_option_t ldoOpt = {
415       .CoreLDOVoltage       = kSPC_CoreLDO_NormalVoltage,
416       .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
417     };
418     SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
419     /* Configure Flash wait-states to support 1.1V voltage level and 100000000Hz frequency */;
420     FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
421     /* Specifies the 1.1V operating voltage for the SRAM's read/write timing margin */
422     spc_sram_voltage_config_t sramCfg = {
423       .operateVoltage       = kSPC_sramOperateAt1P1V,
424       .requestVoltageUpdate = true,
425     };
426     SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
427 
428     CLOCK_SetupExtClocking(24000000U);
429     CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
430 
431     /*!< Set up PLL1 */
432     const pll_setup_t pll1Setup = {
433         .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
434         .pllndiv = SCG_SPLLNDIV_NDIV(6U),
435         .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
436         .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
437         .pllRate = 100000000U
438     };
439     CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
440     CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
441 
442     /*!< Set up clock selectors  */
443     CLOCK_AttachClk(kPLL1_to_MAIN_CLK);
444 
445     /*!< Set up dividers */
446     CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
447 
448     /* Set SystemCoreClock variable */
449     SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
450 }
451 
452