1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24 !!GlobalInfo
25 product: Clocks v10.0
26 processor: MIMXRT1042xxxxB
27 package_id: MIMXRT1042XJM5B
28 mcu_data: ksdk2_0
29 processor_version: 0.12.13
30 board: MIMXRT1040-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33 #include "clock_config.h"
34 #include "fsl_iomuxc.h"
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*******************************************************************************
41 * Variables
42 ******************************************************************************/
43
44 /*******************************************************************************
45 ************************ BOARD_InitBootClocks function ************************
46 ******************************************************************************/
BOARD_InitBootClocks(void)47 void BOARD_InitBootClocks(void)
48 {
49 BOARD_BootClockRUN();
50 }
51
52 /*******************************************************************************
53 ********************** Configuration BOARD_BootClockRUN ***********************
54 ******************************************************************************/
55 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
56 !!Configuration
57 name: BOARD_BootClockRUN
58 called_from_default_init: true
59 outputs:
60 - {id: AHB_CLK_ROOT.outFreq, value: 528 MHz}
61 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
62 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
63 - {id: CLK_1M.outFreq, value: 1 MHz}
64 - {id: CLK_24M.outFreq, value: 24 MHz}
65 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
66 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
67 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
68 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
69 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
70 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
71 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz}
72 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz}
73 - {id: IPG_CLK_ROOT.outFreq, value: 132 MHz}
74 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
75 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
76 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
77 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
78 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
79 - {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz}
80 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
81 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
82 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
83 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
84 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
85 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
86 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
87 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
88 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
89 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
90 - {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz}
91 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
92 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
93 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
94 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
95 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
96 settings:
97 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
98 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
99 - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
100 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
101 - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
102 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
103 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
104 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
105 - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
106 - {id: CCM.SEMC_PODF.scale, value: '8', locked: true}
107 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
108 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
109 - {id: CCM.USDHC1_PODF.scale, value: '2', locked: true}
110 - {id: CCM.USDHC2_PODF.scale, value: '2', locked: true}
111 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
112 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
113 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
114 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
115 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
116 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
117 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
118 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
119 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
120 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
121 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
122 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
123 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
124 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
125 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
126 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
127 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
128 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
129 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
130 - {id: CCM_ANALOG.PLL5.num, value: '0'}
131 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
132 - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
133 - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
134 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
135 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
136 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
137 sources:
138 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
139 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
140
141 /*******************************************************************************
142 * Variables for BOARD_BootClockRUN configuration
143 ******************************************************************************/
144 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
145 {
146 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
147 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
148 };
149 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
150 {
151 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
152 .numerator = 0, /* 30 bit numerator of fractional loop divider */
153 .denominator = 1, /* 30 bit denominator of fractional loop divider */
154 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
155 };
156 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
157 {
158 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
159 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
160 };
161 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
162 {
163 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
164 .postDivider = 8, /* Divider after PLL */
165 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
166 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
167 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
168 };
169 /*******************************************************************************
170 * Code for BOARD_BootClockRUN configuration
171 ******************************************************************************/
BOARD_BootClockRUN(void)172 void BOARD_BootClockRUN(void)
173 {
174 /* Init RTC OSC clock frequency. */
175 CLOCK_SetRtcXtalFreq(32768U);
176 /* Enable 1MHz clock output. */
177 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
178 /* Use free 1MHz clock output. */
179 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
180 /* Set XTAL 24MHz clock frequency. */
181 CLOCK_SetXtalFreq(24000000U);
182 /* Enable XTAL 24MHz clock source. */
183 CLOCK_InitExternalClk(0);
184 /* Enable internal RC. */
185 CLOCK_InitRcOsc24M();
186 /* Switch clock source to external OSC. */
187 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
188 /* Set Oscillator ready counter value. */
189 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
190 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
191 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
192 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
193 /* Set AHB_PODF. */
194 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
195 /* Disable IPG clock gate. */
196 CLOCK_DisableClock(kCLOCK_Adc1);
197 CLOCK_DisableClock(kCLOCK_Adc2);
198 CLOCK_DisableClock(kCLOCK_Xbar1);
199 CLOCK_DisableClock(kCLOCK_Xbar2);
200 CLOCK_DisableClock(kCLOCK_Xbar3);
201 /* Set IPG_PODF. */
202 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
203 /* Set ARM_PODF. */
204 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
205 /* Set PERIPH_CLK2_PODF. */
206 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
207 /* Disable PERCLK clock gate. */
208 CLOCK_DisableClock(kCLOCK_Gpt1);
209 CLOCK_DisableClock(kCLOCK_Gpt1S);
210 CLOCK_DisableClock(kCLOCK_Gpt2);
211 CLOCK_DisableClock(kCLOCK_Gpt2S);
212 CLOCK_DisableClock(kCLOCK_Pit);
213 /* Set PERCLK_PODF. */
214 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
215 /* Disable USDHC1 clock gate. */
216 CLOCK_DisableClock(kCLOCK_Usdhc1);
217 /* Set USDHC1_PODF. */
218 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
219 /* Set Usdhc1 clock source. */
220 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
221 /* Disable USDHC2 clock gate. */
222 CLOCK_DisableClock(kCLOCK_Usdhc2);
223 /* Set USDHC2_PODF. */
224 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
225 /* Set Usdhc2 clock source. */
226 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
227 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
228 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
229 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
230 #ifndef SKIP_SYSCLK_INIT
231 /* Disable Semc clock gate. */
232 CLOCK_DisableClock(kCLOCK_Semc);
233 /* Set SEMC_PODF. */
234 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
235 /* Set Semc alt clock source. */
236 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
237 /* Set Semc clock source. */
238 CLOCK_SetMux(kCLOCK_SemcMux, 0);
239 #endif
240 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
241 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
242 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
243 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
244 /* Disable Flexspi clock gate. */
245 CLOCK_DisableClock(kCLOCK_FlexSpi);
246 /* Set FLEXSPI_PODF. */
247 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
248 /* Set Flexspi clock source. */
249 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
250 #endif
251 /* Disable Flexspi2 clock gate. */
252 CLOCK_DisableClock(kCLOCK_FlexSpi2);
253 /* Set FLEXSPI2_PODF. */
254 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
255 /* Set Flexspi2 clock source. */
256 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
257 /* Disable LPSPI clock gate. */
258 CLOCK_DisableClock(kCLOCK_Lpspi1);
259 CLOCK_DisableClock(kCLOCK_Lpspi2);
260 CLOCK_DisableClock(kCLOCK_Lpspi3);
261 /* Set LPSPI_PODF. */
262 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
263 /* Set Lpspi clock source. */
264 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
265 /* Disable TRACE clock gate. */
266 CLOCK_DisableClock(kCLOCK_Trace);
267 /* Set TRACE_PODF. */
268 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
269 /* Set Trace clock source. */
270 CLOCK_SetMux(kCLOCK_TraceMux, 0);
271 /* Disable SAI1 clock gate. */
272 CLOCK_DisableClock(kCLOCK_Sai1);
273 /* Set SAI1_CLK_PRED. */
274 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
275 /* Set SAI1_CLK_PODF. */
276 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
277 /* Set Sai1 clock source. */
278 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
279 /* Disable SAI2 clock gate. */
280 CLOCK_DisableClock(kCLOCK_Sai2);
281 /* Set SAI2_CLK_PRED. */
282 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
283 /* Set SAI2_CLK_PODF. */
284 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
285 /* Set Sai2 clock source. */
286 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
287 /* Disable SAI3 clock gate. */
288 CLOCK_DisableClock(kCLOCK_Sai3);
289 /* Set SAI3_CLK_PRED. */
290 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
291 /* Set SAI3_CLK_PODF. */
292 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
293 /* Set Sai3 clock source. */
294 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
295 /* Disable Lpi2c clock gate. */
296 CLOCK_DisableClock(kCLOCK_Lpi2c1);
297 CLOCK_DisableClock(kCLOCK_Lpi2c2);
298 CLOCK_DisableClock(kCLOCK_Lpi2c3);
299 /* Set LPI2C_CLK_PODF. */
300 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
301 /* Set Lpi2c clock source. */
302 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
303 /* Disable CAN clock gate. */
304 CLOCK_DisableClock(kCLOCK_Can1);
305 CLOCK_DisableClock(kCLOCK_Can2);
306 CLOCK_DisableClock(kCLOCK_Can1S);
307 CLOCK_DisableClock(kCLOCK_Can2S);
308 /* Set CAN_CLK_PODF. */
309 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
310 /* Set Can clock source. */
311 CLOCK_SetMux(kCLOCK_CanMux, 2);
312 /* Disable UART clock gate. */
313 CLOCK_DisableClock(kCLOCK_Lpuart1);
314 CLOCK_DisableClock(kCLOCK_Lpuart2);
315 CLOCK_DisableClock(kCLOCK_Lpuart3);
316 CLOCK_DisableClock(kCLOCK_Lpuart4);
317 CLOCK_DisableClock(kCLOCK_Lpuart5);
318 CLOCK_DisableClock(kCLOCK_Lpuart6);
319 CLOCK_DisableClock(kCLOCK_Lpuart7);
320 CLOCK_DisableClock(kCLOCK_Lpuart8);
321 /* Set UART_CLK_PODF. */
322 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
323 /* Set Uart clock source. */
324 CLOCK_SetMux(kCLOCK_UartMux, 0);
325 /* Disable LCDIF clock gate. */
326 CLOCK_DisableClock(kCLOCK_LcdPixel);
327 /* Set LCDIF_PRED. */
328 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
329 /* Set LCDIF_CLK_PODF. */
330 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
331 /* Set Lcdif pre clock source. */
332 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
333 /* Disable SPDIF clock gate. */
334 CLOCK_DisableClock(kCLOCK_Spdif);
335 /* Set SPDIF0_CLK_PRED. */
336 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
337 /* Set SPDIF0_CLK_PODF. */
338 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
339 /* Set Spdif clock source. */
340 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
341 /* Disable Flexio1 clock gate. */
342 CLOCK_DisableClock(kCLOCK_Flexio1);
343 /* Set FLEXIO1_CLK_PRED. */
344 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
345 /* Set FLEXIO1_CLK_PODF. */
346 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
347 /* Set Flexio1 clock source. */
348 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
349 /* Disable Flexio2 clock gate. */
350 CLOCK_DisableClock(kCLOCK_Flexio2);
351 /* Set FLEXIO2_CLK_PRED. */
352 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
353 /* Set FLEXIO2_CLK_PODF. */
354 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
355 /* Set Flexio2 clock source. */
356 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
357 /* Set Pll3 sw clock source. */
358 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
359 /* Init ARM PLL. */
360 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
361 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
362 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
363 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
364 #ifndef SKIP_SYSCLK_INIT
365 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
366 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
367 #endif
368 /* Init System PLL. */
369 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
370 /* Init System pfd0. */
371 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
372 /* Init System pfd1. */
373 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
374 /* Init System pfd2. */
375 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
376 /* Init System pfd3. */
377 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
378 #endif
379 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
380 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
381 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
382 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
383 /* Init Usb1 PLL. */
384 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
385 /* Init Usb1 pfd0. */
386 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
387 /* Init Usb1 pfd1. */
388 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
389 /* Init Usb1 pfd2. */
390 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
391 /* Init Usb1 pfd3. */
392 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
393 /* Disable Usb1 PLL output for USBPHY1. */
394 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
395 #endif
396 /* DeInit Audio PLL. */
397 CLOCK_DeinitAudioPll();
398 /* Bypass Audio PLL. */
399 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
400 /* Set divider for Audio PLL. */
401 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
402 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
403 /* Enable Audio PLL output. */
404 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
405 /* Init Video PLL. */
406 uint32_t pllVideo;
407 /* Disable Video PLL output before initial Video PLL. */
408 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
409 /* Bypass PLL first */
410 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
411 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
412 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
413 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
414 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
415 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
416 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
417 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
418 CCM_ANALOG->PLL_VIDEO = pllVideo;
419 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
420 {
421 }
422 /* Disable bypass for Video PLL. */
423 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
424 /* DeInit Enet PLL. */
425 CLOCK_DeinitEnetPll();
426 /* Bypass Enet PLL. */
427 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
428 /* Set Enet output divider. */
429 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
430 /* Enable Enet output. */
431 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
432 /* Enable Enet25M output. */
433 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
434 /* Set preperiph clock source. */
435 CLOCK_SetMux(kCLOCK_PrePeriphMux, 0);
436 /* Set periph clock source. */
437 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
438 /* Set periph clock2 clock source. */
439 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
440 /* Set per clock source. */
441 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
442 /* Set lvds1 clock source. */
443 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
444 /* Set clock out1 divider. */
445 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
446 /* Set clock out1 source. */
447 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
448 /* Set clock out2 divider. */
449 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
450 /* Set clock out2 source. */
451 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
452 /* Set clock out1 drives clock out1. */
453 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
454 /* Disable clock out1. */
455 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
456 /* Disable clock out2. */
457 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
458 /* Set SAI1 MCLK1 clock source. */
459 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
460 /* Set SAI1 MCLK2 clock source. */
461 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
462 /* Set SAI1 MCLK3 clock source. */
463 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
464 /* Set SAI2 MCLK3 clock source. */
465 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
466 /* Set SAI3 MCLK3 clock source. */
467 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
468 /* Set MQS configuration. */
469 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
470 /* Set ENET Ref clock source. */
471 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
472 /* Set GPT1 High frequency reference clock source. */
473 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
474 /* Set GPT2 High frequency reference clock source. */
475 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
476 /* Set SystemCoreClock variable. */
477 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
478 }
479
480 /*******************************************************************************
481 ******************* Configuration BOARD_BootClockRUN_600M *********************
482 ******************************************************************************/
483 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
484 !!Configuration
485 name: BOARD_BootClockRUN_600M
486 outputs:
487 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
488 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
489 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
490 - {id: CLK_1M.outFreq, value: 1 MHz}
491 - {id: CLK_24M.outFreq, value: 24 MHz}
492 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
493 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
494 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
495 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
496 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
497 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
498 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
499 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
500 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
501 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
502 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
503 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
504 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
505 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
506 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
507 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
508 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
509 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
510 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
511 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
512 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
513 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
514 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
515 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
516 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
517 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
518 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
519 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
520 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
521 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
522 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
523 settings:
524 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
525 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
526 - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
527 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
528 - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
529 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
530 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
531 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
532 - {id: CCM.SEMC_PODF.scale, value: '8', locked: true}
533 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
534 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
535 - {id: CCM.USDHC1_PODF.scale, value: '2', locked: true}
536 - {id: CCM.USDHC2_PODF.scale, value: '2', locked: true}
537 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
538 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
539 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
540 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
541 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
542 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
543 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
544 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
545 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
546 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
547 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
548 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
549 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
550 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
551 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
552 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
553 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
554 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
555 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
556 - {id: CCM_ANALOG.PLL5.num, value: '0'}
557 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
558 - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
559 - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
560 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
561 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
562 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
563 sources:
564 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
565 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
566
567 /*******************************************************************************
568 * Variables for BOARD_BootClockRUN_600M configuration
569 ******************************************************************************/
570 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_600M =
571 {
572 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
573 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
574 };
575 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_600M =
576 {
577 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
578 .numerator = 0, /* 30 bit numerator of fractional loop divider */
579 .denominator = 1, /* 30 bit denominator of fractional loop divider */
580 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
581 };
582 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_600M =
583 {
584 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
585 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
586 };
587 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_600M =
588 {
589 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
590 .postDivider = 8, /* Divider after PLL */
591 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
592 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
593 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
594 };
595 /*******************************************************************************
596 * Code for BOARD_BootClockRUN_600M configuration
597 ******************************************************************************/
BOARD_BootClockRUN_600M(void)598 void BOARD_BootClockRUN_600M(void)
599 {
600 /* Init RTC OSC clock frequency. */
601 CLOCK_SetRtcXtalFreq(32768U);
602 /* Enable 1MHz clock output. */
603 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
604 /* Use free 1MHz clock output. */
605 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
606 /* Set XTAL 24MHz clock frequency. */
607 CLOCK_SetXtalFreq(24000000U);
608 /* Enable XTAL 24MHz clock source. */
609 CLOCK_InitExternalClk(0);
610 /* Enable internal RC. */
611 CLOCK_InitRcOsc24M();
612 /* Switch clock source to external OSC. */
613 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
614 /* Set Oscillator ready counter value. */
615 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
616 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
617 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
618 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
619 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
620 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
621 /* Waiting for DCDC_STS_DC_OK bit is asserted */
622 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
623 {
624 }
625 /* Set AHB_PODF. */
626 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
627 /* Disable IPG clock gate. */
628 CLOCK_DisableClock(kCLOCK_Adc1);
629 CLOCK_DisableClock(kCLOCK_Adc2);
630 CLOCK_DisableClock(kCLOCK_Xbar1);
631 CLOCK_DisableClock(kCLOCK_Xbar2);
632 CLOCK_DisableClock(kCLOCK_Xbar3);
633 /* Set IPG_PODF. */
634 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
635 /* Set ARM_PODF. */
636 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
637 /* Set PERIPH_CLK2_PODF. */
638 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
639 /* Disable PERCLK clock gate. */
640 CLOCK_DisableClock(kCLOCK_Gpt1);
641 CLOCK_DisableClock(kCLOCK_Gpt1S);
642 CLOCK_DisableClock(kCLOCK_Gpt2);
643 CLOCK_DisableClock(kCLOCK_Gpt2S);
644 CLOCK_DisableClock(kCLOCK_Pit);
645 /* Set PERCLK_PODF. */
646 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
647 /* Disable USDHC1 clock gate. */
648 CLOCK_DisableClock(kCLOCK_Usdhc1);
649 /* Set USDHC1_PODF. */
650 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
651 /* Set Usdhc1 clock source. */
652 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
653 /* Disable USDHC2 clock gate. */
654 CLOCK_DisableClock(kCLOCK_Usdhc2);
655 /* Set USDHC2_PODF. */
656 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
657 /* Set Usdhc2 clock source. */
658 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
659 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
660 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
661 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
662 #ifndef SKIP_SYSCLK_INIT
663 /* Disable Semc clock gate. */
664 CLOCK_DisableClock(kCLOCK_Semc);
665 /* Set SEMC_PODF. */
666 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
667 /* Set Semc alt clock source. */
668 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
669 /* Set Semc clock source. */
670 CLOCK_SetMux(kCLOCK_SemcMux, 0);
671 #endif
672 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
673 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
674 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
675 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
676 /* Disable Flexspi clock gate. */
677 CLOCK_DisableClock(kCLOCK_FlexSpi);
678 /* Set FLEXSPI_PODF. */
679 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
680 /* Set Flexspi clock source. */
681 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
682 #endif
683 /* Disable Flexspi2 clock gate. */
684 CLOCK_DisableClock(kCLOCK_FlexSpi2);
685 /* Set FLEXSPI2_PODF. */
686 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
687 /* Set Flexspi2 clock source. */
688 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
689 /* Disable LPSPI clock gate. */
690 CLOCK_DisableClock(kCLOCK_Lpspi1);
691 CLOCK_DisableClock(kCLOCK_Lpspi2);
692 CLOCK_DisableClock(kCLOCK_Lpspi3);
693 /* Set LPSPI_PODF. */
694 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
695 /* Set Lpspi clock source. */
696 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
697 /* Disable TRACE clock gate. */
698 CLOCK_DisableClock(kCLOCK_Trace);
699 /* Set TRACE_PODF. */
700 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
701 /* Set Trace clock source. */
702 CLOCK_SetMux(kCLOCK_TraceMux, 0);
703 /* Disable SAI1 clock gate. */
704 CLOCK_DisableClock(kCLOCK_Sai1);
705 /* Set SAI1_CLK_PRED. */
706 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
707 /* Set SAI1_CLK_PODF. */
708 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
709 /* Set Sai1 clock source. */
710 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
711 /* Disable SAI2 clock gate. */
712 CLOCK_DisableClock(kCLOCK_Sai2);
713 /* Set SAI2_CLK_PRED. */
714 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
715 /* Set SAI2_CLK_PODF. */
716 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
717 /* Set Sai2 clock source. */
718 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
719 /* Disable SAI3 clock gate. */
720 CLOCK_DisableClock(kCLOCK_Sai3);
721 /* Set SAI3_CLK_PRED. */
722 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
723 /* Set SAI3_CLK_PODF. */
724 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
725 /* Set Sai3 clock source. */
726 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
727 /* Disable Lpi2c clock gate. */
728 CLOCK_DisableClock(kCLOCK_Lpi2c1);
729 CLOCK_DisableClock(kCLOCK_Lpi2c2);
730 CLOCK_DisableClock(kCLOCK_Lpi2c3);
731 /* Set LPI2C_CLK_PODF. */
732 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
733 /* Set Lpi2c clock source. */
734 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
735 /* Disable CAN clock gate. */
736 CLOCK_DisableClock(kCLOCK_Can1);
737 CLOCK_DisableClock(kCLOCK_Can2);
738 CLOCK_DisableClock(kCLOCK_Can3);
739 CLOCK_DisableClock(kCLOCK_Can1S);
740 CLOCK_DisableClock(kCLOCK_Can2S);
741 CLOCK_DisableClock(kCLOCK_Can3S);
742 /* Set CAN_CLK_PODF. */
743 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
744 /* Set Can clock source. */
745 CLOCK_SetMux(kCLOCK_CanMux, 2);
746 /* Disable UART clock gate. */
747 CLOCK_DisableClock(kCLOCK_Lpuart1);
748 CLOCK_DisableClock(kCLOCK_Lpuart2);
749 CLOCK_DisableClock(kCLOCK_Lpuart3);
750 CLOCK_DisableClock(kCLOCK_Lpuart4);
751 CLOCK_DisableClock(kCLOCK_Lpuart5);
752 CLOCK_DisableClock(kCLOCK_Lpuart6);
753 CLOCK_DisableClock(kCLOCK_Lpuart7);
754 CLOCK_DisableClock(kCLOCK_Lpuart8);
755 /* Set UART_CLK_PODF. */
756 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
757 /* Set Uart clock source. */
758 CLOCK_SetMux(kCLOCK_UartMux, 0);
759 /* Disable LCDIF clock gate. */
760 CLOCK_DisableClock(kCLOCK_LcdPixel);
761 /* Set LCDIF_PRED. */
762 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
763 /* Set LCDIF_CLK_PODF. */
764 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
765 /* Set Lcdif pre clock source. */
766 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
767 /* Disable SPDIF clock gate. */
768 CLOCK_DisableClock(kCLOCK_Spdif);
769 /* Set SPDIF0_CLK_PRED. */
770 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
771 /* Set SPDIF0_CLK_PODF. */
772 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
773 /* Set Spdif clock source. */
774 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
775 /* Disable Flexio1 clock gate. */
776 CLOCK_DisableClock(kCLOCK_Flexio1);
777 /* Set FLEXIO1_CLK_PRED. */
778 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
779 /* Set FLEXIO1_CLK_PODF. */
780 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
781 /* Set Flexio1 clock source. */
782 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
783 /* Disable Flexio2 clock gate. */
784 CLOCK_DisableClock(kCLOCK_Flexio2);
785 /* Set FLEXIO2_CLK_PRED. */
786 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
787 /* Set FLEXIO2_CLK_PODF. */
788 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
789 /* Set Flexio2 clock source. */
790 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
791 /* Set Pll3 sw clock source. */
792 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
793 /* Init ARM PLL. */
794 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_600M);
795 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
796 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
797 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
798 #ifndef SKIP_SYSCLK_INIT
799 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
800 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
801 #endif
802 /* Init System PLL. */
803 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_600M);
804 /* Init System pfd0. */
805 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
806 /* Init System pfd1. */
807 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
808 /* Init System pfd2. */
809 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
810 /* Init System pfd3. */
811 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
812 #endif
813 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
814 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
815 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
816 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
817 /* Init Usb1 PLL. */
818 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_600M);
819 /* Init Usb1 pfd0. */
820 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
821 /* Init Usb1 pfd1. */
822 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
823 /* Init Usb1 pfd2. */
824 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
825 /* Init Usb1 pfd3. */
826 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
827 /* Disable Usb1 PLL output for USBPHY1. */
828 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
829 #endif
830 /* DeInit Audio PLL. */
831 CLOCK_DeinitAudioPll();
832 /* Bypass Audio PLL. */
833 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
834 /* Set divider for Audio PLL. */
835 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
836 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
837 /* Enable Audio PLL output. */
838 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
839 /* Init Video PLL. */
840 uint32_t pllVideo;
841 /* Disable Video PLL output before initial Video PLL. */
842 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
843 /* Bypass PLL first */
844 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
845 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
846 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
847 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
848 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
849 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
850 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
851 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
852 CCM_ANALOG->PLL_VIDEO = pllVideo;
853 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
854 {
855 }
856 /* Disable bypass for Video PLL. */
857 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
858 /* DeInit Enet PLL. */
859 CLOCK_DeinitEnetPll();
860 /* Bypass Enet PLL. */
861 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
862 /* Set Enet output divider. */
863 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
864 /* Enable Enet output. */
865 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
866 /* Enable Enet25M output. */
867 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
868 /* Set preperiph clock source. */
869 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
870 /* Set periph clock source. */
871 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
872 /* Set periph clock2 clock source. */
873 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
874 /* Set per clock source. */
875 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
876 /* Set lvds1 clock source. */
877 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
878 /* Set clock out1 divider. */
879 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
880 /* Set clock out1 source. */
881 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
882 /* Set clock out2 divider. */
883 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
884 /* Set clock out2 source. */
885 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
886 /* Set clock out1 drives clock out1. */
887 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
888 /* Disable clock out1. */
889 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
890 /* Disable clock out2. */
891 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
892 /* Set SAI1 MCLK1 clock source. */
893 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
894 /* Set SAI1 MCLK2 clock source. */
895 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
896 /* Set SAI1 MCLK3 clock source. */
897 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
898 /* Set SAI2 MCLK3 clock source. */
899 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
900 /* Set SAI3 MCLK3 clock source. */
901 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
902 /* Set MQS configuration. */
903 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
904 /* Set ENET Ref clock source. */
905 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
906 /* Set GPT1 High frequency reference clock source. */
907 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
908 /* Set GPT2 High frequency reference clock source. */
909 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
910 /* Set SystemCoreClock variable. */
911 SystemCoreClock = BOARD_BOOTCLOCKRUN_600M_CORE_CLOCK;
912 }
913
914
