1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24 !!GlobalInfo
25 product: Clocks v10.0
26 processor: MIMXRT1011xxxxx
27 package_id: MIMXRT1011DAE5A
28 mcu_data: ksdk2_0
29 processor_version: 0.12.10
30 board: MIMXRT1010-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33 #include "clock_config.h"
34 #include "fsl_iomuxc.h"
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*******************************************************************************
41 * Variables
42 ******************************************************************************/
43
44 /*******************************************************************************
45 ************************ BOARD_InitBootClocks function ************************
46 ******************************************************************************/
BOARD_InitBootClocks(void)47 void BOARD_InitBootClocks(void)
48 {
49 BOARD_BootClockRUN();
50 }
51
52 /*******************************************************************************
53 ********************** Configuration BOARD_BootClockRUN ***********************
54 ******************************************************************************/
55 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
56 !!Configuration
57 name: BOARD_BootClockRUN
58 called_from_default_init: true
59 outputs:
60 - {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
61 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
62 - {id: CLK_1M.outFreq, value: 1 MHz}
63 - {id: CLK_24M.outFreq, value: 24 MHz}
64 - {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
65 - {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
66 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
67 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
68 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
69 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
70 - {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
71 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
72 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
73 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
74 - {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
75 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
76 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
77 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
78 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
79 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
80 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
81 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
82 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
83 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
84 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
85 settings:
86 - {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
87 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
88 - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
89 - {id: CCM.IPG_PODF.scale, value: '4'}
90 - {id: CCM.LPSPI_PODF.scale, value: '5'}
91 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
92 - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
93 - {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
94 - {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
95 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
96 - {id: CCM_ANALOG.PLL2.denom, value: '1'}
97 - {id: CCM_ANALOG.PLL2.num, value: '0'}
98 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
99 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
100 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
101 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
102 - {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
103 - {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
104 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
105 - {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
106 - {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
107 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
108 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
109 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
110 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
111 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
112 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
113 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
114 - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
115 - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
116 - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
117 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
118 sources:
119 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
120 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
121
122 /*******************************************************************************
123 * Variables for BOARD_BootClockRUN configuration
124 ******************************************************************************/
125 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
126 {
127 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
128 .numerator = 0, /* 30 bit numerator of fractional loop divider */
129 .denominator = 1, /* 30 bit denominator of fractional loop divider */
130 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
131 };
132 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
133 {
134 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
135 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
136 };
137 const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
138 {
139 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
140 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
141 };
142 /*******************************************************************************
143 * Code for BOARD_BootClockRUN configuration
144 ******************************************************************************/
BOARD_BootClockRUN(void)145 void BOARD_BootClockRUN(void)
146 {
147 /* Init RTC OSC clock frequency. */
148 CLOCK_SetRtcXtalFreq(32768U);
149 /* Enable 1MHz clock output. */
150 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
151 /* Use free 1MHz clock output. */
152 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
153 /* Set XTAL 24MHz clock frequency. */
154 CLOCK_SetXtalFreq(24000000U);
155 /* Enable XTAL 24MHz clock source. */
156 CLOCK_InitExternalClk(0);
157 /* Enable internal RC. */
158 CLOCK_InitRcOsc24M();
159 /* Switch clock source to external OSC. */
160 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
161 /* Set Oscillator ready counter value. */
162 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
163 /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
164 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
165 /* Waiting for DCDC_STS_DC_OK bit is asserted */
166 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
167 {
168 }
169 /* Disable IPG clock gate. */
170 CLOCK_DisableClock(kCLOCK_Adc1);
171 CLOCK_DisableClock(kCLOCK_Xbar1);
172 /* Set IPG_PODF. */
173 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
174 /* Init Enet PLL. */
175 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
176 /* Disable PERCLK clock gate. */
177 CLOCK_DisableClock(kCLOCK_Gpt1);
178 CLOCK_DisableClock(kCLOCK_Gpt1S);
179 CLOCK_DisableClock(kCLOCK_Gpt2);
180 CLOCK_DisableClock(kCLOCK_Gpt2S);
181 CLOCK_DisableClock(kCLOCK_Pit);
182 /* Set PERCLK_PODF. */
183 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
184 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
185 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
186 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
187 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
188 /* Disable Flexspi clock gate. */
189 CLOCK_DisableClock(kCLOCK_FlexSpi);
190 /* Set FLEXSPI_PODF. */
191 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
192 /* Set Flexspi clock source. */
193 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
194 CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
195 #endif
196 /* Disable ADC_ACLK_EN clock gate. */
197 CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
198 /* Set ADC_ACLK_PODF. */
199 CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
200 /* Disable LPSPI clock gate. */
201 CLOCK_DisableClock(kCLOCK_Lpspi1);
202 CLOCK_DisableClock(kCLOCK_Lpspi2);
203 /* Set LPSPI_PODF. */
204 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
205 /* Set Lpspi clock source. */
206 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
207 /* Disable TRACE clock gate. */
208 CLOCK_DisableClock(kCLOCK_Trace);
209 /* Set TRACE_PODF. */
210 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
211 /* Set Trace clock source. */
212 CLOCK_SetMux(kCLOCK_TraceMux, 0);
213 /* Disable SAI1 clock gate. */
214 CLOCK_DisableClock(kCLOCK_Sai1);
215 /* Set SAI1_CLK_PRED. */
216 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
217 /* Set SAI1_CLK_PODF. */
218 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
219 /* Set Sai1 clock source. */
220 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
221 /* Disable SAI3 clock gate. */
222 CLOCK_DisableClock(kCLOCK_Sai3);
223 /* Set SAI3_CLK_PRED. */
224 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
225 /* Set SAI3_CLK_PODF. */
226 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
227 /* Set Sai3 clock source. */
228 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
229 /* Disable Lpi2c clock gate. */
230 CLOCK_DisableClock(kCLOCK_Lpi2c1);
231 CLOCK_DisableClock(kCLOCK_Lpi2c2);
232 /* Set LPI2C_CLK_PODF. */
233 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
234 /* Set Lpi2c clock source. */
235 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
236 /* Disable UART clock gate. */
237 CLOCK_DisableClock(kCLOCK_Lpuart1);
238 CLOCK_DisableClock(kCLOCK_Lpuart2);
239 CLOCK_DisableClock(kCLOCK_Lpuart3);
240 CLOCK_DisableClock(kCLOCK_Lpuart4);
241 /* Set UART_CLK_PODF. */
242 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
243 /* Set Uart clock source. */
244 CLOCK_SetMux(kCLOCK_UartMux, 0);
245 /* Disable SPDIF clock gate. */
246 CLOCK_DisableClock(kCLOCK_Spdif);
247 /* Set SPDIF0_CLK_PRED. */
248 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
249 /* Set SPDIF0_CLK_PODF. */
250 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
251 /* Set Spdif clock source. */
252 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
253 /* Disable Flexio1 clock gate. */
254 CLOCK_DisableClock(kCLOCK_Flexio1);
255 /* Set FLEXIO1_CLK_PRED. */
256 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
257 /* Set FLEXIO1_CLK_PODF. */
258 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
259 /* Set Flexio1 clock source. */
260 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
261 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
262 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
263 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
264 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
265 /* Init Usb1 PLL. */
266 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
267 /* Init Usb1 pfd0. */
268 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
269 /* Init Usb1 pfd1. */
270 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
271 /* Init Usb1 pfd2. */
272 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
273 /* Init Usb1 pfd3. */
274 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
275 /* Disable Usb1 PLL output for USBPHY1. */
276 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
277 #endif
278 /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
279 /* Set Pll3 SW clock source to use the USB1 PLL output. */
280 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
281 /* Set safe value of the AHB_PODF. */
282 CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
283 /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
284 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
285 /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
286 CLOCK_SetMux(kCLOCK_PeriphMux, 1);
287 /* Set per clock source. */
288 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
289 /* Init System PLL. */
290 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
291 /* Init System pfd0. */
292 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
293 /* Init System pfd1. */
294 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
295 /* Init System pfd2. */
296 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
297 /* Init System pfd3. */
298 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
299 /* DeInit Audio PLL. */
300 CLOCK_DeinitAudioPll();
301 /* Bypass Audio PLL. */
302 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
303 /* Set divider for Audio PLL. */
304 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
305 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
306 /* Enable Audio PLL output. */
307 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
308 /* Set preperiph clock source. */
309 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
310 /* Set periph clock source. */
311 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
312 /* Set periph clock2 clock source. */
313 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
314 /* Set AHB_PODF. */
315 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
316 /* Set clock out1 divider. */
317 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
318 /* Set clock out1 source. */
319 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
320 /* Set clock out2 divider. */
321 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
322 /* Set clock out2 source. */
323 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
324 /* Set clock out1 drives clock out1. */
325 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
326 /* Disable clock out1. */
327 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
328 /* Disable clock out2. */
329 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
330 /* Set SAI1 MCLK1 clock source. */
331 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
332 /* Set SAI1 MCLK2 clock source. */
333 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
334 /* Set SAI1 MCLK3 clock source. */
335 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
336 /* Set SAI3 MCLK3 clock source. */
337 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
338 /* Set MQS configuration. */
339 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
340 /* Set GPT1 High frequency reference clock source. */
341 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
342 /* Set GPT2 High frequency reference clock source. */
343 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
344 /* Set SystemCoreClock variable. */
345 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
346 }
347
348 /*******************************************************************************
349 ******************* Configuration BOARD_BootClockRUN_400M *********************
350 ******************************************************************************/
351 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
352 !!Configuration
353 name: BOARD_BootClockRUN_400M
354 outputs:
355 - {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
356 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
357 - {id: CLK_1M.outFreq, value: 1 MHz}
358 - {id: CLK_24M.outFreq, value: 24 MHz}
359 - {id: CORE_CLK_ROOT.outFreq, value: 396 MHz}
360 - {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
361 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
362 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
363 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 49.5 MHz}
364 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 49.5 MHz}
365 - {id: IPG_CLK_ROOT.outFreq, value: 99 MHz}
366 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
367 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
368 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
369 - {id: PERCLK_CLK_ROOT.outFreq, value: 49.5 MHz}
370 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
371 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
372 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
373 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
374 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
375 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
376 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
377 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
378 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
379 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
380 settings:
381 - {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
382 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
383 - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
384 - {id: CCM.IPG_PODF.scale, value: '4'}
385 - {id: CCM.LPSPI_PODF.scale, value: '5'}
386 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
387 - {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
388 - {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
389 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
390 - {id: CCM_ANALOG.PLL2.denom, value: '1'}
391 - {id: CCM_ANALOG.PLL2.num, value: '0'}
392 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
393 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
394 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
395 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
396 - {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
397 - {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
398 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
399 - {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '24', locked: true}
400 - {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
401 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
402 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
403 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
404 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
405 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
406 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
407 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
408 - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
409 - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
410 - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
411 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
412 sources:
413 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
414 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
415
416 /*******************************************************************************
417 * Variables for BOARD_BootClockRUN_400M configuration
418 ******************************************************************************/
419 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_400M =
420 {
421 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
422 .numerator = 0, /* 30 bit numerator of fractional loop divider */
423 .denominator = 1, /* 30 bit denominator of fractional loop divider */
424 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
425 };
426 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_400M =
427 {
428 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
429 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
430 };
431 const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN_400M =
432 {
433 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
434 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
435 };
436 /*******************************************************************************
437 * Code for BOARD_BootClockRUN_400M configuration
438 ******************************************************************************/
BOARD_BootClockRUN_400M(void)439 void BOARD_BootClockRUN_400M(void)
440 {
441 /* Init RTC OSC clock frequency. */
442 CLOCK_SetRtcXtalFreq(32768U);
443 /* Enable 1MHz clock output. */
444 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
445 /* Use free 1MHz clock output. */
446 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
447 /* Set XTAL 24MHz clock frequency. */
448 CLOCK_SetXtalFreq(24000000U);
449 /* Enable XTAL 24MHz clock source. */
450 CLOCK_InitExternalClk(0);
451 /* Enable internal RC. */
452 CLOCK_InitRcOsc24M();
453 /* Switch clock source to external OSC. */
454 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
455 /* Set Oscillator ready counter value. */
456 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
457 /* Disable IPG clock gate. */
458 CLOCK_DisableClock(kCLOCK_Adc1);
459 CLOCK_DisableClock(kCLOCK_Xbar1);
460 /* Set IPG_PODF. */
461 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
462 /* Init Enet PLL. */
463 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN_400M);
464 /* Disable PERCLK clock gate. */
465 CLOCK_DisableClock(kCLOCK_Gpt1);
466 CLOCK_DisableClock(kCLOCK_Gpt1S);
467 CLOCK_DisableClock(kCLOCK_Gpt2);
468 CLOCK_DisableClock(kCLOCK_Gpt2S);
469 CLOCK_DisableClock(kCLOCK_Pit);
470 /* Set PERCLK_PODF. */
471 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
472 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
473 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
474 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
475 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
476 /* Disable Flexspi clock gate. */
477 CLOCK_DisableClock(kCLOCK_FlexSpi);
478 /* Set FLEXSPI_PODF. */
479 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
480 /* Set Flexspi clock source. */
481 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
482 CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
483 #endif
484 /* Disable ADC_ACLK_EN clock gate. */
485 CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
486 /* Set ADC_ACLK_PODF. */
487 CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
488 /* Disable LPSPI clock gate. */
489 CLOCK_DisableClock(kCLOCK_Lpspi1);
490 CLOCK_DisableClock(kCLOCK_Lpspi2);
491 /* Set LPSPI_PODF. */
492 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
493 /* Set Lpspi clock source. */
494 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
495 /* Disable TRACE clock gate. */
496 CLOCK_DisableClock(kCLOCK_Trace);
497 /* Set TRACE_PODF. */
498 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
499 /* Set Trace clock source. */
500 CLOCK_SetMux(kCLOCK_TraceMux, 0);
501 /* Disable SAI1 clock gate. */
502 CLOCK_DisableClock(kCLOCK_Sai1);
503 /* Set SAI1_CLK_PRED. */
504 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
505 /* Set SAI1_CLK_PODF. */
506 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
507 /* Set Sai1 clock source. */
508 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
509 /* Disable SAI3 clock gate. */
510 CLOCK_DisableClock(kCLOCK_Sai3);
511 /* Set SAI3_CLK_PRED. */
512 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
513 /* Set SAI3_CLK_PODF. */
514 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
515 /* Set Sai3 clock source. */
516 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
517 /* Disable Lpi2c clock gate. */
518 CLOCK_DisableClock(kCLOCK_Lpi2c1);
519 CLOCK_DisableClock(kCLOCK_Lpi2c2);
520 /* Set LPI2C_CLK_PODF. */
521 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
522 /* Set Lpi2c clock source. */
523 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
524 /* Disable UART clock gate. */
525 CLOCK_DisableClock(kCLOCK_Lpuart1);
526 CLOCK_DisableClock(kCLOCK_Lpuart2);
527 CLOCK_DisableClock(kCLOCK_Lpuart3);
528 CLOCK_DisableClock(kCLOCK_Lpuart4);
529 /* Set UART_CLK_PODF. */
530 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
531 /* Set Uart clock source. */
532 CLOCK_SetMux(kCLOCK_UartMux, 0);
533 /* Disable SPDIF clock gate. */
534 CLOCK_DisableClock(kCLOCK_Spdif);
535 /* Set SPDIF0_CLK_PRED. */
536 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
537 /* Set SPDIF0_CLK_PODF. */
538 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
539 /* Set Spdif clock source. */
540 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
541 /* Disable Flexio1 clock gate. */
542 CLOCK_DisableClock(kCLOCK_Flexio1);
543 /* Set FLEXIO1_CLK_PRED. */
544 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
545 /* Set FLEXIO1_CLK_PODF. */
546 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
547 /* Set Flexio1 clock source. */
548 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
549 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
550 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
551 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
552 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
553 /* Init Usb1 PLL. */
554 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_400M);
555 /* Init Usb1 pfd0. */
556 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
557 /* Init Usb1 pfd1. */
558 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
559 /* Init Usb1 pfd2. */
560 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
561 /* Init Usb1 pfd3. */
562 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
563 /* Disable Usb1 PLL output for USBPHY1. */
564 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
565 #endif
566 /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
567 /* Set Pll3 SW clock source to use the USB1 PLL output. */
568 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
569 /* Set safe value of the AHB_PODF. */
570 CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
571 /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
572 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
573 /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
574 CLOCK_SetMux(kCLOCK_PeriphMux, 1);
575 /* Set per clock source. */
576 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
577 /* Init System PLL. */
578 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_400M);
579 /* Init System pfd0. */
580 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
581 /* Init System pfd1. */
582 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
583 /* Init System pfd2. */
584 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
585 /* Init System pfd3. */
586 CLOCK_InitSysPfd(kCLOCK_Pfd3, 24);
587 /* DeInit Audio PLL. */
588 CLOCK_DeinitAudioPll();
589 /* Bypass Audio PLL. */
590 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
591 /* Set divider for Audio PLL. */
592 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
593 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
594 /* Enable Audio PLL output. */
595 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
596 /* Set preperiph clock source. */
597 CLOCK_SetMux(kCLOCK_PrePeriphMux, 2);
598 /* Set periph clock source. */
599 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
600 /* Set periph clock2 clock source. */
601 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
602 /* Set AHB_PODF. */
603 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
604 /* Set clock out1 divider. */
605 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
606 /* Set clock out1 source. */
607 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
608 /* Set clock out2 divider. */
609 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
610 /* Set clock out2 source. */
611 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
612 /* Set clock out1 drives clock out1. */
613 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
614 /* Disable clock out1. */
615 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
616 /* Disable clock out2. */
617 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
618 /* Set SAI1 MCLK1 clock source. */
619 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
620 /* Set SAI1 MCLK2 clock source. */
621 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
622 /* Set SAI1 MCLK3 clock source. */
623 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
624 /* Set SAI3 MCLK3 clock source. */
625 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
626 /* Set MQS configuration. */
627 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
628 /* Set GPT1 High frequency reference clock source. */
629 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
630 /* Set GPT2 High frequency reference clock source. */
631 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
632 /* Set SystemCoreClock variable. */
633 SystemCoreClock = BOARD_BOOTCLOCKRUN_400M_CORE_CLOCK;
634 }
635
636
