1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SW_PORT1.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_SW_PORT1 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SW_PORT1_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SW_PORT1_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SW_PORT1 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SW_PORT1_Peripheral_Access_Layer SW_PORT1 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SW_PORT1 - Size of Registers Arrays */ 72 #define SW_PORT1_TCT_NUM_COUNT 8u 73 74 /** SW_PORT1 - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t PCAPR; /**< Port capability register, offset: 0x0 */ 77 __I uint32_t PMCAPR; /**< Port MAC capability register, offset: 0x4 */ 78 __I uint32_t PIOCAPR; /**< Port I/O capability register, offset: 0x8 */ 79 uint8_t RESERVED_0[4]; 80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ 81 uint8_t RESERVED_1[12]; 82 __IO uint32_t PMAR0; /**< Port MAC address register 0, offset: 0x20 */ 83 __IO uint32_t PMAR1; /**< Port MAC address register 1, offset: 0x24 */ 84 uint8_t RESERVED_2[40]; 85 __IO uint32_t PTAR; /**< Port TPID acceptance register, offset: 0x50 */ 86 __IO uint32_t PQOSMR; /**< Port QoS mode register, offset: 0x54 */ 87 uint8_t RESERVED_3[8]; 88 __I uint32_t PQOR; /**< Port Queue Operational register, offset: 0x60 */ 89 uint8_t RESERVED_4[28]; 90 __IO uint32_t PPCR; /**< Port parser configuration register, offset: 0x80 */ 91 __IO uint32_t PIPFCR; /**< Port ingress port filter configuration register, offset: 0x84 */ 92 uint8_t RESERVED_5[24]; 93 __IO uint32_t PSGCR; /**< Port stream gate configuration register, offset: 0xA0 */ 94 uint8_t RESERVED_6[92]; 95 __IO uint32_t POR; /**< Port operational register, offset: 0x100 */ 96 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ 97 __IO uint32_t PRXSDUOR; /**< Port receive SDU overhead register, offset: 0x108 */ 98 __IO uint32_t PTXSDUOR; /**< Port transmit SDU overhead register, offset: 0x10C */ 99 __IO uint32_t PTGSCR; /**< Port time gate scheduling control register, offset: 0x110 */ 100 __I uint32_t PTGAGLSR; /**< Port time gate scheduling admin gate list status register, offset: 0x114 */ 101 __I uint32_t PTGAGLLR; /**< Port time gate scheduling admin gate list length register, offset: 0x118 */ 102 __I uint32_t PTGOGLLR; /**< Port time gating operational gate list length register, offset: 0x11C */ 103 uint8_t RESERVED_7[4]; 104 __I uint32_t PTGSHAR; /**< Port time gate scheduling hold advance register, offset: 0x124 */ 105 __I uint32_t PTGSRAR; /**< Port time gate scheduling release advance register, offset: 0x128 */ 106 __IO uint32_t PTGSHCR; /**< Port time gate scheduling hold configuration register, offset: 0x12C */ 107 uint8_t RESERVED_8[4]; 108 __IO uint32_t PFPCR; /**< Port frame preemption configuration register, offset: 0x134 */ 109 uint8_t RESERVED_9[136]; 110 __I uint32_t PRXDCR; /**< Port Rx discard count register, offset: 0x1C0 */ 111 uint8_t RESERVED_10[4]; 112 __IO uint32_t PRXDCRR0; /**< Port Rx discard count reason register 0, offset: 0x1C8 */ 113 __IO uint32_t PRXDCRR1; /**< Port Rx discard count reason register 1, offset: 0x1CC */ 114 uint8_t RESERVED_11[16]; 115 __I uint32_t PTXDCR; /**< Port Tx discard count register, offset: 0x1E0 */ 116 uint8_t RESERVED_12[4]; 117 __IO uint32_t PTXDCRR0; /**< Port Tx discard count reason register 0, offset: 0x1E8 */ 118 __IO uint32_t PTXDCRR1; /**< Port Tx discard count reason register 1, offset: 0x1EC */ 119 uint8_t RESERVED_13[16]; 120 struct { /* offset: 0x200, array step: 0x20 */ 121 __I uint32_t PTGSTCSR; /**< Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register, array offset: 0x200, array step: 0x20 */ 122 uint8_t RESERVED_0[4]; 123 __IO uint32_t PTCTMSDUR; /**< Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register, array offset: 0x208, array step: 0x20 */ 124 uint8_t RESERVED_1[4]; 125 __IO uint32_t PTCCBSR0; /**< Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0, array offset: 0x210, array step: 0x20 */ 126 __IO uint32_t PTCCBSR1; /**< Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1, array offset: 0x214, array step: 0x20 */ 127 uint8_t RESERVED_2[8]; 128 } TCT_NUM[SW_PORT1_TCT_NUM_COUNT]; 129 uint8_t RESERVED_14[256]; 130 __IO uint32_t PBPMCR0; /**< Port buffer pool mapping configuration register 0, offset: 0x400 */ 131 __IO uint32_t PBPMCR1; /**< Port buffer pool mapping configuration register 1, offset: 0x404 */ 132 uint8_t RESERVED_15[48]; 133 __IO uint32_t PPCPDEIMR; /**< Port PCP DEI mapping register, offset: 0x438 */ 134 uint8_t RESERVED_16[4]; 135 __IO uint32_t PMCR; /**< Port mirror configuration register, offset: 0x440 */ 136 uint8_t RESERVED_17[12]; 137 __IO uint32_t PCTFCR; /**< Port cut through forwarding configuration register, offset: 0x450 */ 138 uint8_t RESERVED_18[4]; 139 __IO uint32_t PLANIDCR; /**< Port LANID configuration register, offset: 0x458 */ 140 uint8_t RESERVED_19[4]; 141 __IO uint32_t PISIDCR; /**< Port ingress stream identification configuration register, offset: 0x460 */ 142 __IO uint32_t PFMCR; /**< Port frame modification configuration register, offset: 0x464 */ 143 uint8_t RESERVED_20[8]; 144 __IO uint32_t PIPV2QMR0; /**< Port IPV to queue mapping register 0, offset: 0x470 */ 145 uint8_t RESERVED_21[60]; 146 __I uint32_t PTCMINLR; /**< Port time capture minimum latency register, offset: 0x4B0 */ 147 __I uint32_t PTCMAXLR; /**< Port time capture maximum latency register, offset: 0x4B4 */ 148 uint8_t RESERVED_22[72]; 149 __IO uint32_t BPCR; /**< Bridge port configuration register, offset: 0x500 */ 150 uint8_t RESERVED_23[12]; 151 __IO uint32_t BPDVR; /**< Bridge port default VLAN register, offset: 0x510 */ 152 uint8_t RESERVED_24[12]; 153 __IO uint32_t BPSTGSR; /**< Bridge port spanning tree group state register, offset: 0x520 */ 154 uint8_t RESERVED_25[4]; 155 __IO uint32_t BPSCR0; /**< Bridge port storm control register 0, offset: 0x528 */ 156 __IO uint32_t BPSCR1; /**< Bridge port storm control register 1, offset: 0x52C */ 157 __I uint32_t BPOR; /**< Bridge port operational register, offset: 0x530 */ 158 uint8_t RESERVED_26[76]; 159 __I uint32_t BPDCR; /**< Bridge port discard count register, offset: 0x580 */ 160 uint8_t RESERVED_27[4]; 161 __IO uint32_t BPDCRR0; /**< Bridge port discard count reason register 0, offset: 0x588 */ 162 __IO uint32_t BPDCRR1; /**< Bridge port discard count reason register 1, offset: 0x58C */ 163 __IO uint32_t BPMLFSR; /**< Bridge port MAC learning failure status register, offset: 0x590 */ 164 } SW_PORT1_Type, *SW_PORT1_MemMapPtr; 165 166 /** Number of instances of the SW_PORT1 module. */ 167 #define SW_PORT1_INSTANCE_COUNT (1u) 168 169 /* SW_PORT1 - Peripheral instance base addresses */ 170 /** Peripheral NETC__SW0_PORT1 base address */ 171 #define IP_NETC__SW0_PORT1_BASE (0x74A08000u) 172 /** Peripheral NETC__SW0_PORT1 base pointer */ 173 #define IP_NETC__SW0_PORT1 ((SW_PORT1_Type *)IP_NETC__SW0_PORT1_BASE) 174 /** Array initializer of SW_PORT1 peripheral base addresses */ 175 #define IP_SW_PORT1_BASE_ADDRS { IP_NETC__SW0_PORT1_BASE } 176 /** Array initializer of SW_PORT1 peripheral base pointers */ 177 #define IP_SW_PORT1_BASE_PTRS { IP_NETC__SW0_PORT1 } 178 179 /* ---------------------------------------------------------------------------- 180 -- SW_PORT1 Register Masks 181 ---------------------------------------------------------------------------- */ 182 183 /*! 184 * @addtogroup SW_PORT1_Register_Masks SW_PORT1 Register Masks 185 * @{ 186 */ 187 188 /*! @name PCAPR - Port capability register */ 189 /*! @{ */ 190 191 #define SW_PORT1_PCAPR_LINK_TYPE_MASK (0x10U) 192 #define SW_PORT1_PCAPR_LINK_TYPE_SHIFT (4U) 193 #define SW_PORT1_PCAPR_LINK_TYPE_WIDTH (1U) 194 #define SW_PORT1_PCAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCAPR_LINK_TYPE_SHIFT)) & SW_PORT1_PCAPR_LINK_TYPE_MASK) 195 196 #define SW_PORT1_PCAPR_NUM_TC_MASK (0xF000U) 197 #define SW_PORT1_PCAPR_NUM_TC_SHIFT (12U) 198 #define SW_PORT1_PCAPR_NUM_TC_WIDTH (4U) 199 #define SW_PORT1_PCAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCAPR_NUM_TC_SHIFT)) & SW_PORT1_PCAPR_NUM_TC_MASK) 200 201 #define SW_PORT1_PCAPR_NUM_Q_MASK (0xF0000U) 202 #define SW_PORT1_PCAPR_NUM_Q_SHIFT (16U) 203 #define SW_PORT1_PCAPR_NUM_Q_WIDTH (4U) 204 #define SW_PORT1_PCAPR_NUM_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCAPR_NUM_Q_SHIFT)) & SW_PORT1_PCAPR_NUM_Q_MASK) 205 206 #define SW_PORT1_PCAPR_NUM_CG_MASK (0xF000000U) 207 #define SW_PORT1_PCAPR_NUM_CG_SHIFT (24U) 208 #define SW_PORT1_PCAPR_NUM_CG_WIDTH (4U) 209 #define SW_PORT1_PCAPR_NUM_CG(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCAPR_NUM_CG_SHIFT)) & SW_PORT1_PCAPR_NUM_CG_MASK) 210 211 #define SW_PORT1_PCAPR_TGS_MASK (0x10000000U) 212 #define SW_PORT1_PCAPR_TGS_SHIFT (28U) 213 #define SW_PORT1_PCAPR_TGS_WIDTH (1U) 214 #define SW_PORT1_PCAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCAPR_TGS_SHIFT)) & SW_PORT1_PCAPR_TGS_MASK) 215 216 #define SW_PORT1_PCAPR_CBS_MASK (0x20000000U) 217 #define SW_PORT1_PCAPR_CBS_SHIFT (29U) 218 #define SW_PORT1_PCAPR_CBS_WIDTH (1U) 219 #define SW_PORT1_PCAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCAPR_CBS_SHIFT)) & SW_PORT1_PCAPR_CBS_MASK) 220 /*! @} */ 221 222 /*! @name PMCAPR - Port MAC capability register */ 223 /*! @{ */ 224 225 #define SW_PORT1_PMCAPR_MAC_VAR_MASK (0x7U) 226 #define SW_PORT1_PMCAPR_MAC_VAR_SHIFT (0U) 227 #define SW_PORT1_PMCAPR_MAC_VAR_WIDTH (3U) 228 #define SW_PORT1_PMCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMCAPR_MAC_VAR_SHIFT)) & SW_PORT1_PMCAPR_MAC_VAR_MASK) 229 230 #define SW_PORT1_PMCAPR_EFPAD_MASK (0x30U) 231 #define SW_PORT1_PMCAPR_EFPAD_SHIFT (4U) 232 #define SW_PORT1_PMCAPR_EFPAD_WIDTH (2U) 233 #define SW_PORT1_PMCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMCAPR_EFPAD_SHIFT)) & SW_PORT1_PMCAPR_EFPAD_MASK) 234 235 #define SW_PORT1_PMCAPR_HD_MASK (0x100U) 236 #define SW_PORT1_PMCAPR_HD_SHIFT (8U) 237 #define SW_PORT1_PMCAPR_HD_WIDTH (1U) 238 #define SW_PORT1_PMCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMCAPR_HD_SHIFT)) & SW_PORT1_PMCAPR_HD_MASK) 239 240 #define SW_PORT1_PMCAPR_FP_MASK (0x600U) 241 #define SW_PORT1_PMCAPR_FP_SHIFT (9U) 242 #define SW_PORT1_PMCAPR_FP_WIDTH (2U) 243 #define SW_PORT1_PMCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMCAPR_FP_SHIFT)) & SW_PORT1_PMCAPR_FP_MASK) 244 245 #define SW_PORT1_PMCAPR_MII_PROT_MASK (0xF000000U) 246 #define SW_PORT1_PMCAPR_MII_PROT_SHIFT (24U) 247 #define SW_PORT1_PMCAPR_MII_PROT_WIDTH (4U) 248 #define SW_PORT1_PMCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMCAPR_MII_PROT_SHIFT)) & SW_PORT1_PMCAPR_MII_PROT_MASK) 249 /*! @} */ 250 251 /*! @name PIOCAPR - Port I/O capability register */ 252 /*! @{ */ 253 254 #define SW_PORT1_PIOCAPR_PCS_PROT_MASK (0xFFFFU) 255 #define SW_PORT1_PIOCAPR_PCS_PROT_SHIFT (0U) 256 #define SW_PORT1_PIOCAPR_PCS_PROT_WIDTH (16U) 257 #define SW_PORT1_PIOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIOCAPR_PCS_PROT_SHIFT)) & SW_PORT1_PIOCAPR_PCS_PROT_MASK) 258 259 #define SW_PORT1_PIOCAPR_IO_VAR_MASK (0xF000000U) 260 #define SW_PORT1_PIOCAPR_IO_VAR_SHIFT (24U) 261 #define SW_PORT1_PIOCAPR_IO_VAR_WIDTH (4U) 262 #define SW_PORT1_PIOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIOCAPR_IO_VAR_SHIFT)) & SW_PORT1_PIOCAPR_IO_VAR_MASK) 263 264 #define SW_PORT1_PIOCAPR_EMDIO_MASK (0x10000000U) 265 #define SW_PORT1_PIOCAPR_EMDIO_SHIFT (28U) 266 #define SW_PORT1_PIOCAPR_EMDIO_WIDTH (1U) 267 #define SW_PORT1_PIOCAPR_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIOCAPR_EMDIO_SHIFT)) & SW_PORT1_PIOCAPR_EMDIO_MASK) 268 269 #define SW_PORT1_PIOCAPR_REVMII_RATE_MASK (0x40000000U) 270 #define SW_PORT1_PIOCAPR_REVMII_RATE_SHIFT (30U) 271 #define SW_PORT1_PIOCAPR_REVMII_RATE_WIDTH (1U) 272 #define SW_PORT1_PIOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIOCAPR_REVMII_RATE_SHIFT)) & SW_PORT1_PIOCAPR_REVMII_RATE_MASK) 273 274 #define SW_PORT1_PIOCAPR_REVMII_MASK (0x80000000U) 275 #define SW_PORT1_PIOCAPR_REVMII_SHIFT (31U) 276 #define SW_PORT1_PIOCAPR_REVMII_WIDTH (1U) 277 #define SW_PORT1_PIOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIOCAPR_REVMII_SHIFT)) & SW_PORT1_PIOCAPR_REVMII_MASK) 278 /*! @} */ 279 280 /*! @name PCR - Port configuration register */ 281 /*! @{ */ 282 283 #define SW_PORT1_PCR_HDR_FMT_MASK (0x1U) 284 #define SW_PORT1_PCR_HDR_FMT_SHIFT (0U) 285 #define SW_PORT1_PCR_HDR_FMT_WIDTH (1U) 286 #define SW_PORT1_PCR_HDR_FMT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCR_HDR_FMT_SHIFT)) & SW_PORT1_PCR_HDR_FMT_MASK) 287 288 #define SW_PORT1_PCR_L2DOSE_MASK (0x10U) 289 #define SW_PORT1_PCR_L2DOSE_SHIFT (4U) 290 #define SW_PORT1_PCR_L2DOSE_WIDTH (1U) 291 #define SW_PORT1_PCR_L2DOSE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCR_L2DOSE_SHIFT)) & SW_PORT1_PCR_L2DOSE_MASK) 292 293 #define SW_PORT1_PCR_TIMER_CS_MASK (0x100U) 294 #define SW_PORT1_PCR_TIMER_CS_SHIFT (8U) 295 #define SW_PORT1_PCR_TIMER_CS_WIDTH (1U) 296 #define SW_PORT1_PCR_TIMER_CS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCR_TIMER_CS_SHIFT)) & SW_PORT1_PCR_TIMER_CS_MASK) 297 298 #define SW_PORT1_PCR_FCSEA_MASK (0x1000U) 299 #define SW_PORT1_PCR_FCSEA_SHIFT (12U) 300 #define SW_PORT1_PCR_FCSEA_WIDTH (1U) 301 #define SW_PORT1_PCR_FCSEA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCR_FCSEA_SHIFT)) & SW_PORT1_PCR_FCSEA_MASK) 302 303 #define SW_PORT1_PCR_PSPEED_MASK (0x3FFF0000U) 304 #define SW_PORT1_PCR_PSPEED_SHIFT (16U) 305 #define SW_PORT1_PCR_PSPEED_WIDTH (14U) 306 #define SW_PORT1_PCR_PSPEED(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCR_PSPEED_SHIFT)) & SW_PORT1_PCR_PSPEED_MASK) 307 /*! @} */ 308 309 /*! @name PMAR0 - Port MAC address register 0 */ 310 /*! @{ */ 311 312 #define SW_PORT1_PMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) 313 #define SW_PORT1_PMAR0_PRIM_MAC_ADDR_SHIFT (0U) 314 #define SW_PORT1_PMAR0_PRIM_MAC_ADDR_WIDTH (32U) 315 #define SW_PORT1_PMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMAR0_PRIM_MAC_ADDR_SHIFT)) & SW_PORT1_PMAR0_PRIM_MAC_ADDR_MASK) 316 /*! @} */ 317 318 /*! @name PMAR1 - Port MAC address register 1 */ 319 /*! @{ */ 320 321 #define SW_PORT1_PMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) 322 #define SW_PORT1_PMAR1_PRIM_MAC_ADDR_SHIFT (0U) 323 #define SW_PORT1_PMAR1_PRIM_MAC_ADDR_WIDTH (16U) 324 #define SW_PORT1_PMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMAR1_PRIM_MAC_ADDR_SHIFT)) & SW_PORT1_PMAR1_PRIM_MAC_ADDR_MASK) 325 /*! @} */ 326 327 /*! @name PTAR - Port TPID acceptance register */ 328 /*! @{ */ 329 330 #define SW_PORT1_PTAR_OVTPIDL_MASK (0xFU) 331 #define SW_PORT1_PTAR_OVTPIDL_SHIFT (0U) 332 #define SW_PORT1_PTAR_OVTPIDL_WIDTH (4U) 333 #define SW_PORT1_PTAR_OVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTAR_OVTPIDL_SHIFT)) & SW_PORT1_PTAR_OVTPIDL_MASK) 334 335 #define SW_PORT1_PTAR_IVTPIDL_MASK (0xF0U) 336 #define SW_PORT1_PTAR_IVTPIDL_SHIFT (4U) 337 #define SW_PORT1_PTAR_IVTPIDL_WIDTH (4U) 338 #define SW_PORT1_PTAR_IVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTAR_IVTPIDL_SHIFT)) & SW_PORT1_PTAR_IVTPIDL_MASK) 339 /*! @} */ 340 341 /*! @name PQOSMR - Port QoS mode register */ 342 /*! @{ */ 343 344 #define SW_PORT1_PQOSMR_VS_MASK (0x1U) 345 #define SW_PORT1_PQOSMR_VS_SHIFT (0U) 346 #define SW_PORT1_PQOSMR_VS_WIDTH (1U) 347 #define SW_PORT1_PQOSMR_VS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOSMR_VS_SHIFT)) & SW_PORT1_PQOSMR_VS_MASK) 348 349 #define SW_PORT1_PQOSMR_VE_MASK (0x2U) 350 #define SW_PORT1_PQOSMR_VE_SHIFT (1U) 351 #define SW_PORT1_PQOSMR_VE_WIDTH (1U) 352 #define SW_PORT1_PQOSMR_VE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOSMR_VE_SHIFT)) & SW_PORT1_PQOSMR_VE_MASK) 353 354 #define SW_PORT1_PQOSMR_DDR_MASK (0xCU) 355 #define SW_PORT1_PQOSMR_DDR_SHIFT (2U) 356 #define SW_PORT1_PQOSMR_DDR_WIDTH (2U) 357 #define SW_PORT1_PQOSMR_DDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOSMR_DDR_SHIFT)) & SW_PORT1_PQOSMR_DDR_MASK) 358 359 #define SW_PORT1_PQOSMR_DIPV_MASK (0x70U) 360 #define SW_PORT1_PQOSMR_DIPV_SHIFT (4U) 361 #define SW_PORT1_PQOSMR_DIPV_WIDTH (3U) 362 #define SW_PORT1_PQOSMR_DIPV(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOSMR_DIPV_SHIFT)) & SW_PORT1_PQOSMR_DIPV_MASK) 363 364 #define SW_PORT1_PQOSMR_VQMP_MASK (0xF0000U) 365 #define SW_PORT1_PQOSMR_VQMP_SHIFT (16U) 366 #define SW_PORT1_PQOSMR_VQMP_WIDTH (4U) 367 #define SW_PORT1_PQOSMR_VQMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOSMR_VQMP_SHIFT)) & SW_PORT1_PQOSMR_VQMP_MASK) 368 369 #define SW_PORT1_PQOSMR_QVMP_MASK (0xF00000U) 370 #define SW_PORT1_PQOSMR_QVMP_SHIFT (20U) 371 #define SW_PORT1_PQOSMR_QVMP_WIDTH (4U) 372 #define SW_PORT1_PQOSMR_QVMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOSMR_QVMP_SHIFT)) & SW_PORT1_PQOSMR_QVMP_MASK) 373 /*! @} */ 374 375 /*! @name PQOR - Port Queue Operational register */ 376 /*! @{ */ 377 378 #define SW_PORT1_PQOR_Q0S_MASK (0x1U) 379 #define SW_PORT1_PQOR_Q0S_SHIFT (0U) 380 #define SW_PORT1_PQOR_Q0S_WIDTH (1U) 381 #define SW_PORT1_PQOR_Q0S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q0S_SHIFT)) & SW_PORT1_PQOR_Q0S_MASK) 382 383 #define SW_PORT1_PQOR_Q1S_MASK (0x2U) 384 #define SW_PORT1_PQOR_Q1S_SHIFT (1U) 385 #define SW_PORT1_PQOR_Q1S_WIDTH (1U) 386 #define SW_PORT1_PQOR_Q1S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q1S_SHIFT)) & SW_PORT1_PQOR_Q1S_MASK) 387 388 #define SW_PORT1_PQOR_Q2S_MASK (0x4U) 389 #define SW_PORT1_PQOR_Q2S_SHIFT (2U) 390 #define SW_PORT1_PQOR_Q2S_WIDTH (1U) 391 #define SW_PORT1_PQOR_Q2S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q2S_SHIFT)) & SW_PORT1_PQOR_Q2S_MASK) 392 393 #define SW_PORT1_PQOR_Q3S_MASK (0x8U) 394 #define SW_PORT1_PQOR_Q3S_SHIFT (3U) 395 #define SW_PORT1_PQOR_Q3S_WIDTH (1U) 396 #define SW_PORT1_PQOR_Q3S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q3S_SHIFT)) & SW_PORT1_PQOR_Q3S_MASK) 397 398 #define SW_PORT1_PQOR_Q4S_MASK (0x10U) 399 #define SW_PORT1_PQOR_Q4S_SHIFT (4U) 400 #define SW_PORT1_PQOR_Q4S_WIDTH (1U) 401 #define SW_PORT1_PQOR_Q4S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q4S_SHIFT)) & SW_PORT1_PQOR_Q4S_MASK) 402 403 #define SW_PORT1_PQOR_Q5S_MASK (0x20U) 404 #define SW_PORT1_PQOR_Q5S_SHIFT (5U) 405 #define SW_PORT1_PQOR_Q5S_WIDTH (1U) 406 #define SW_PORT1_PQOR_Q5S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q5S_SHIFT)) & SW_PORT1_PQOR_Q5S_MASK) 407 408 #define SW_PORT1_PQOR_Q6S_MASK (0x40U) 409 #define SW_PORT1_PQOR_Q6S_SHIFT (6U) 410 #define SW_PORT1_PQOR_Q6S_WIDTH (1U) 411 #define SW_PORT1_PQOR_Q6S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q6S_SHIFT)) & SW_PORT1_PQOR_Q6S_MASK) 412 413 #define SW_PORT1_PQOR_Q7S_MASK (0x80U) 414 #define SW_PORT1_PQOR_Q7S_SHIFT (7U) 415 #define SW_PORT1_PQOR_Q7S_WIDTH (1U) 416 #define SW_PORT1_PQOR_Q7S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PQOR_Q7S_SHIFT)) & SW_PORT1_PQOR_Q7S_MASK) 417 /*! @} */ 418 419 /*! @name PPCR - Port parser configuration register */ 420 /*! @{ */ 421 422 #define SW_PORT1_PPCR_L1PFS_MASK (0x3EU) 423 #define SW_PORT1_PPCR_L1PFS_SHIFT (1U) 424 #define SW_PORT1_PPCR_L1PFS_WIDTH (5U) 425 #define SW_PORT1_PPCR_L1PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCR_L1PFS_SHIFT)) & SW_PORT1_PPCR_L1PFS_MASK) 426 427 #define SW_PORT1_PPCR_L2PFS_MASK (0x3E00U) 428 #define SW_PORT1_PPCR_L2PFS_SHIFT (9U) 429 #define SW_PORT1_PPCR_L2PFS_WIDTH (5U) 430 #define SW_PORT1_PPCR_L2PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCR_L2PFS_SHIFT)) & SW_PORT1_PPCR_L2PFS_MASK) 431 432 #define SW_PORT1_PPCR_L3HFP_MASK (0x10000U) 433 #define SW_PORT1_PPCR_L3HFP_SHIFT (16U) 434 #define SW_PORT1_PPCR_L3HFP_WIDTH (1U) 435 #define SW_PORT1_PPCR_L3HFP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCR_L3HFP_SHIFT)) & SW_PORT1_PPCR_L3HFP_MASK) 436 437 #define SW_PORT1_PPCR_L3PFS_MASK (0x3E0000U) 438 #define SW_PORT1_PPCR_L3PFS_SHIFT (17U) 439 #define SW_PORT1_PPCR_L3PFS_WIDTH (5U) 440 #define SW_PORT1_PPCR_L3PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCR_L3PFS_SHIFT)) & SW_PORT1_PPCR_L3PFS_MASK) 441 442 #define SW_PORT1_PPCR_L4HFP_MASK (0x1000000U) 443 #define SW_PORT1_PPCR_L4HFP_SHIFT (24U) 444 #define SW_PORT1_PPCR_L4HFP_WIDTH (1U) 445 #define SW_PORT1_PPCR_L4HFP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCR_L4HFP_SHIFT)) & SW_PORT1_PPCR_L4HFP_MASK) 446 447 #define SW_PORT1_PPCR_L4PFS_MASK (0x3E000000U) 448 #define SW_PORT1_PPCR_L4PFS_SHIFT (25U) 449 #define SW_PORT1_PPCR_L4PFS_WIDTH (5U) 450 #define SW_PORT1_PPCR_L4PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCR_L4PFS_SHIFT)) & SW_PORT1_PPCR_L4PFS_MASK) 451 /*! @} */ 452 453 /*! @name PIPFCR - Port ingress port filter configuration register */ 454 /*! @{ */ 455 456 #define SW_PORT1_PIPFCR_EN_MASK (0x1U) 457 #define SW_PORT1_PIPFCR_EN_SHIFT (0U) 458 #define SW_PORT1_PIPFCR_EN_WIDTH (1U) 459 #define SW_PORT1_PIPFCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPFCR_EN_SHIFT)) & SW_PORT1_PIPFCR_EN_MASK) 460 /*! @} */ 461 462 /*! @name PSGCR - Port stream gate configuration register */ 463 /*! @{ */ 464 465 #define SW_PORT1_PSGCR_PDELAY_MASK (0xFFFFFFU) 466 #define SW_PORT1_PSGCR_PDELAY_SHIFT (0U) 467 #define SW_PORT1_PSGCR_PDELAY_WIDTH (24U) 468 #define SW_PORT1_PSGCR_PDELAY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PSGCR_PDELAY_SHIFT)) & SW_PORT1_PSGCR_PDELAY_MASK) 469 470 #define SW_PORT1_PSGCR_OGC_MASK (0x80000000U) 471 #define SW_PORT1_PSGCR_OGC_SHIFT (31U) 472 #define SW_PORT1_PSGCR_OGC_WIDTH (1U) 473 #define SW_PORT1_PSGCR_OGC(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PSGCR_OGC_SHIFT)) & SW_PORT1_PSGCR_OGC_MASK) 474 /*! @} */ 475 476 /*! @name POR - Port operational register */ 477 /*! @{ */ 478 479 #define SW_PORT1_POR_TXDIS_MASK (0x1U) 480 #define SW_PORT1_POR_TXDIS_SHIFT (0U) 481 #define SW_PORT1_POR_TXDIS_WIDTH (1U) 482 #define SW_PORT1_POR_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_POR_TXDIS_SHIFT)) & SW_PORT1_POR_TXDIS_MASK) 483 484 #define SW_PORT1_POR_RXDIS_MASK (0x2U) 485 #define SW_PORT1_POR_RXDIS_SHIFT (1U) 486 #define SW_PORT1_POR_RXDIS_WIDTH (1U) 487 #define SW_PORT1_POR_RXDIS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_POR_RXDIS_SHIFT)) & SW_PORT1_POR_RXDIS_MASK) 488 /*! @} */ 489 490 /*! @name PSR - Port status register */ 491 /*! @{ */ 492 493 #define SW_PORT1_PSR_TX_BUSY_MASK (0x1U) 494 #define SW_PORT1_PSR_TX_BUSY_SHIFT (0U) 495 #define SW_PORT1_PSR_TX_BUSY_WIDTH (1U) 496 #define SW_PORT1_PSR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PSR_TX_BUSY_SHIFT)) & SW_PORT1_PSR_TX_BUSY_MASK) 497 498 #define SW_PORT1_PSR_RX_BUSY_MASK (0x2U) 499 #define SW_PORT1_PSR_RX_BUSY_SHIFT (1U) 500 #define SW_PORT1_PSR_RX_BUSY_WIDTH (1U) 501 #define SW_PORT1_PSR_RX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PSR_RX_BUSY_SHIFT)) & SW_PORT1_PSR_RX_BUSY_MASK) 502 /*! @} */ 503 504 /*! @name PRXSDUOR - Port receive SDU overhead register */ 505 /*! @{ */ 506 507 #define SW_PORT1_PRXSDUOR_PPDU_BCO_MASK (0x1FU) 508 #define SW_PORT1_PRXSDUOR_PPDU_BCO_SHIFT (0U) 509 #define SW_PORT1_PRXSDUOR_PPDU_BCO_WIDTH (5U) 510 #define SW_PORT1_PRXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXSDUOR_PPDU_BCO_SHIFT)) & SW_PORT1_PRXSDUOR_PPDU_BCO_MASK) 511 512 #define SW_PORT1_PRXSDUOR_MACSEC_BCO_MASK (0x1F00U) 513 #define SW_PORT1_PRXSDUOR_MACSEC_BCO_SHIFT (8U) 514 #define SW_PORT1_PRXSDUOR_MACSEC_BCO_WIDTH (5U) 515 #define SW_PORT1_PRXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXSDUOR_MACSEC_BCO_SHIFT)) & SW_PORT1_PRXSDUOR_MACSEC_BCO_MASK) 516 /*! @} */ 517 518 /*! @name PTXSDUOR - Port transmit SDU overhead register */ 519 /*! @{ */ 520 521 #define SW_PORT1_PTXSDUOR_PPDU_BCO_MASK (0x1FU) 522 #define SW_PORT1_PTXSDUOR_PPDU_BCO_SHIFT (0U) 523 #define SW_PORT1_PTXSDUOR_PPDU_BCO_WIDTH (5U) 524 #define SW_PORT1_PTXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXSDUOR_PPDU_BCO_SHIFT)) & SW_PORT1_PTXSDUOR_PPDU_BCO_MASK) 525 526 #define SW_PORT1_PTXSDUOR_MACSEC_BCO_MASK (0x1F00U) 527 #define SW_PORT1_PTXSDUOR_MACSEC_BCO_SHIFT (8U) 528 #define SW_PORT1_PTXSDUOR_MACSEC_BCO_WIDTH (5U) 529 #define SW_PORT1_PTXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXSDUOR_MACSEC_BCO_SHIFT)) & SW_PORT1_PTXSDUOR_MACSEC_BCO_MASK) 530 /*! @} */ 531 532 /*! @name PTGSCR - Port time gate scheduling control register */ 533 /*! @{ */ 534 535 #define SW_PORT1_PTGSCR_TGE_MASK (0x80000000U) 536 #define SW_PORT1_PTGSCR_TGE_SHIFT (31U) 537 #define SW_PORT1_PTGSCR_TGE_WIDTH (1U) 538 #define SW_PORT1_PTGSCR_TGE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGSCR_TGE_SHIFT)) & SW_PORT1_PTGSCR_TGE_MASK) 539 /*! @} */ 540 541 /*! @name PTGAGLSR - Port time gate scheduling admin gate list status register */ 542 /*! @{ */ 543 544 #define SW_PORT1_PTGAGLSR_TG_MASK (0x1U) 545 #define SW_PORT1_PTGAGLSR_TG_SHIFT (0U) 546 #define SW_PORT1_PTGAGLSR_TG_WIDTH (1U) 547 #define SW_PORT1_PTGAGLSR_TG(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGAGLSR_TG_SHIFT)) & SW_PORT1_PTGAGLSR_TG_MASK) 548 549 #define SW_PORT1_PTGAGLSR_CFG_PEND_MASK (0x2U) 550 #define SW_PORT1_PTGAGLSR_CFG_PEND_SHIFT (1U) 551 #define SW_PORT1_PTGAGLSR_CFG_PEND_WIDTH (1U) 552 #define SW_PORT1_PTGAGLSR_CFG_PEND(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGAGLSR_CFG_PEND_SHIFT)) & SW_PORT1_PTGAGLSR_CFG_PEND_MASK) 553 /*! @} */ 554 555 /*! @name PTGAGLLR - Port time gate scheduling admin gate list length register */ 556 /*! @{ */ 557 558 #define SW_PORT1_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK (0xFFFFU) 559 #define SW_PORT1_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT (0U) 560 #define SW_PORT1_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_WIDTH (16U) 561 #define SW_PORT1_PTGAGLLR_ADMIN_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT)) & SW_PORT1_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK) 562 /*! @} */ 563 564 /*! @name PTGOGLLR - Port time gating operational gate list length register */ 565 /*! @{ */ 566 567 #define SW_PORT1_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK (0xFFFFU) 568 #define SW_PORT1_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT (0U) 569 #define SW_PORT1_PTGOGLLR_OPER_GATE_LIST_LENGTH_WIDTH (16U) 570 #define SW_PORT1_PTGOGLLR_OPER_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT)) & SW_PORT1_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK) 571 /*! @} */ 572 573 /*! @name PTGSHAR - Port time gate scheduling hold advance register */ 574 /*! @{ */ 575 576 #define SW_PORT1_PTGSHAR_HOLDADVANCE_MASK (0xFFFFU) 577 #define SW_PORT1_PTGSHAR_HOLDADVANCE_SHIFT (0U) 578 #define SW_PORT1_PTGSHAR_HOLDADVANCE_WIDTH (16U) 579 #define SW_PORT1_PTGSHAR_HOLDADVANCE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGSHAR_HOLDADVANCE_SHIFT)) & SW_PORT1_PTGSHAR_HOLDADVANCE_MASK) 580 /*! @} */ 581 582 /*! @name PTGSRAR - Port time gate scheduling release advance register */ 583 /*! @{ */ 584 585 #define SW_PORT1_PTGSRAR_RELEASEADVANCE_MASK (0xFFFFU) 586 #define SW_PORT1_PTGSRAR_RELEASEADVANCE_SHIFT (0U) 587 #define SW_PORT1_PTGSRAR_RELEASEADVANCE_WIDTH (16U) 588 #define SW_PORT1_PTGSRAR_RELEASEADVANCE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGSRAR_RELEASEADVANCE_SHIFT)) & SW_PORT1_PTGSRAR_RELEASEADVANCE_MASK) 589 /*! @} */ 590 591 /*! @name PTGSHCR - Port time gate scheduling hold configuration register */ 592 /*! @{ */ 593 594 #define SW_PORT1_PTGSHCR_HOLD_SKEW_MASK (0xFFFFFU) 595 #define SW_PORT1_PTGSHCR_HOLD_SKEW_SHIFT (0U) 596 #define SW_PORT1_PTGSHCR_HOLD_SKEW_WIDTH (20U) 597 #define SW_PORT1_PTGSHCR_HOLD_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGSHCR_HOLD_SKEW_SHIFT)) & SW_PORT1_PTGSHCR_HOLD_SKEW_MASK) 598 /*! @} */ 599 600 /*! @name PFPCR - Port frame preemption configuration register */ 601 /*! @{ */ 602 603 #define SW_PORT1_PFPCR_FPE_TC0_MASK (0x1U) 604 #define SW_PORT1_PFPCR_FPE_TC0_SHIFT (0U) 605 #define SW_PORT1_PFPCR_FPE_TC0_WIDTH (1U) 606 #define SW_PORT1_PFPCR_FPE_TC0(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC0_SHIFT)) & SW_PORT1_PFPCR_FPE_TC0_MASK) 607 608 #define SW_PORT1_PFPCR_FPE_TC1_MASK (0x2U) 609 #define SW_PORT1_PFPCR_FPE_TC1_SHIFT (1U) 610 #define SW_PORT1_PFPCR_FPE_TC1_WIDTH (1U) 611 #define SW_PORT1_PFPCR_FPE_TC1(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC1_SHIFT)) & SW_PORT1_PFPCR_FPE_TC1_MASK) 612 613 #define SW_PORT1_PFPCR_FPE_TC2_MASK (0x4U) 614 #define SW_PORT1_PFPCR_FPE_TC2_SHIFT (2U) 615 #define SW_PORT1_PFPCR_FPE_TC2_WIDTH (1U) 616 #define SW_PORT1_PFPCR_FPE_TC2(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC2_SHIFT)) & SW_PORT1_PFPCR_FPE_TC2_MASK) 617 618 #define SW_PORT1_PFPCR_FPE_TC3_MASK (0x8U) 619 #define SW_PORT1_PFPCR_FPE_TC3_SHIFT (3U) 620 #define SW_PORT1_PFPCR_FPE_TC3_WIDTH (1U) 621 #define SW_PORT1_PFPCR_FPE_TC3(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC3_SHIFT)) & SW_PORT1_PFPCR_FPE_TC3_MASK) 622 623 #define SW_PORT1_PFPCR_FPE_TC4_MASK (0x10U) 624 #define SW_PORT1_PFPCR_FPE_TC4_SHIFT (4U) 625 #define SW_PORT1_PFPCR_FPE_TC4_WIDTH (1U) 626 #define SW_PORT1_PFPCR_FPE_TC4(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC4_SHIFT)) & SW_PORT1_PFPCR_FPE_TC4_MASK) 627 628 #define SW_PORT1_PFPCR_FPE_TC5_MASK (0x20U) 629 #define SW_PORT1_PFPCR_FPE_TC5_SHIFT (5U) 630 #define SW_PORT1_PFPCR_FPE_TC5_WIDTH (1U) 631 #define SW_PORT1_PFPCR_FPE_TC5(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC5_SHIFT)) & SW_PORT1_PFPCR_FPE_TC5_MASK) 632 633 #define SW_PORT1_PFPCR_FPE_TC6_MASK (0x40U) 634 #define SW_PORT1_PFPCR_FPE_TC6_SHIFT (6U) 635 #define SW_PORT1_PFPCR_FPE_TC6_WIDTH (1U) 636 #define SW_PORT1_PFPCR_FPE_TC6(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC6_SHIFT)) & SW_PORT1_PFPCR_FPE_TC6_MASK) 637 638 #define SW_PORT1_PFPCR_FPE_TC7_MASK (0x80U) 639 #define SW_PORT1_PFPCR_FPE_TC7_SHIFT (7U) 640 #define SW_PORT1_PFPCR_FPE_TC7_WIDTH (1U) 641 #define SW_PORT1_PFPCR_FPE_TC7(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFPCR_FPE_TC7_SHIFT)) & SW_PORT1_PFPCR_FPE_TC7_MASK) 642 /*! @} */ 643 644 /*! @name PRXDCR - Port Rx discard count register */ 645 /*! @{ */ 646 647 #define SW_PORT1_PRXDCR_COUNT_MASK (0xFFFFFFFFU) 648 #define SW_PORT1_PRXDCR_COUNT_SHIFT (0U) 649 #define SW_PORT1_PRXDCR_COUNT_WIDTH (32U) 650 #define SW_PORT1_PRXDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCR_COUNT_SHIFT)) & SW_PORT1_PRXDCR_COUNT_MASK) 651 /*! @} */ 652 653 /*! @name PRXDCRR0 - Port Rx discard count reason register 0 */ 654 /*! @{ */ 655 656 #define SW_PORT1_PRXDCRR0_PCDR_MASK (0x1U) 657 #define SW_PORT1_PRXDCRR0_PCDR_SHIFT (0U) 658 #define SW_PORT1_PRXDCRR0_PCDR_WIDTH (1U) 659 #define SW_PORT1_PRXDCRR0_PCDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_PCDR_SHIFT)) & SW_PORT1_PRXDCRR0_PCDR_MASK) 660 661 #define SW_PORT1_PRXDCRR0_SMREDR_MASK (0x2U) 662 #define SW_PORT1_PRXDCRR0_SMREDR_SHIFT (1U) 663 #define SW_PORT1_PRXDCRR0_SMREDR_WIDTH (1U) 664 #define SW_PORT1_PRXDCRR0_SMREDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_SMREDR_SHIFT)) & SW_PORT1_PRXDCRR0_SMREDR_MASK) 665 666 #define SW_PORT1_PRXDCRR0_RXDISDR_MASK (0x4U) 667 #define SW_PORT1_PRXDCRR0_RXDISDR_SHIFT (2U) 668 #define SW_PORT1_PRXDCRR0_RXDISDR_WIDTH (1U) 669 #define SW_PORT1_PRXDCRR0_RXDISDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_RXDISDR_SHIFT)) & SW_PORT1_PRXDCRR0_RXDISDR_MASK) 670 671 #define SW_PORT1_PRXDCRR0_IPFDR_MASK (0x8U) 672 #define SW_PORT1_PRXDCRR0_IPFDR_SHIFT (3U) 673 #define SW_PORT1_PRXDCRR0_IPFDR_WIDTH (1U) 674 #define SW_PORT1_PRXDCRR0_IPFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_IPFDR_SHIFT)) & SW_PORT1_PRXDCRR0_IPFDR_MASK) 675 676 #define SW_PORT1_PRXDCRR0_RPDR_MASK (0x10U) 677 #define SW_PORT1_PRXDCRR0_RPDR_SHIFT (4U) 678 #define SW_PORT1_PRXDCRR0_RPDR_WIDTH (1U) 679 #define SW_PORT1_PRXDCRR0_RPDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_RPDR_SHIFT)) & SW_PORT1_PRXDCRR0_RPDR_MASK) 680 681 #define SW_PORT1_PRXDCRR0_ISFDR_MASK (0x20U) 682 #define SW_PORT1_PRXDCRR0_ISFDR_SHIFT (5U) 683 #define SW_PORT1_PRXDCRR0_ISFDR_WIDTH (1U) 684 #define SW_PORT1_PRXDCRR0_ISFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_ISFDR_SHIFT)) & SW_PORT1_PRXDCRR0_ISFDR_MASK) 685 686 #define SW_PORT1_PRXDCRR0_SGCDR_MASK (0x40U) 687 #define SW_PORT1_PRXDCRR0_SGCDR_SHIFT (6U) 688 #define SW_PORT1_PRXDCRR0_SGCDR_WIDTH (1U) 689 #define SW_PORT1_PRXDCRR0_SGCDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_SGCDR_SHIFT)) & SW_PORT1_PRXDCRR0_SGCDR_MASK) 690 691 #define SW_PORT1_PRXDCRR0_SGOEDR_MASK (0x80U) 692 #define SW_PORT1_PRXDCRR0_SGOEDR_SHIFT (7U) 693 #define SW_PORT1_PRXDCRR0_SGOEDR_WIDTH (1U) 694 #define SW_PORT1_PRXDCRR0_SGOEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_SGOEDR_SHIFT)) & SW_PORT1_PRXDCRR0_SGOEDR_MASK) 695 696 #define SW_PORT1_PRXDCRR0_MSDUEDR_MASK (0x100U) 697 #define SW_PORT1_PRXDCRR0_MSDUEDR_SHIFT (8U) 698 #define SW_PORT1_PRXDCRR0_MSDUEDR_WIDTH (1U) 699 #define SW_PORT1_PRXDCRR0_MSDUEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_MSDUEDR_SHIFT)) & SW_PORT1_PRXDCRR0_MSDUEDR_MASK) 700 701 #define SW_PORT1_PRXDCRR0_FMMEDR_MASK (0x200U) 702 #define SW_PORT1_PRXDCRR0_FMMEDR_SHIFT (9U) 703 #define SW_PORT1_PRXDCRR0_FMMEDR_WIDTH (1U) 704 #define SW_PORT1_PRXDCRR0_FMMEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_FMMEDR_SHIFT)) & SW_PORT1_PRXDCRR0_FMMEDR_MASK) 705 706 #define SW_PORT1_PRXDCRR0_CMDR_MASK (0x400U) 707 #define SW_PORT1_PRXDCRR0_CMDR_SHIFT (10U) 708 #define SW_PORT1_PRXDCRR0_CMDR_WIDTH (1U) 709 #define SW_PORT1_PRXDCRR0_CMDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_CMDR_SHIFT)) & SW_PORT1_PRXDCRR0_CMDR_MASK) 710 711 #define SW_PORT1_PRXDCRR0_ITEDR_MASK (0x800U) 712 #define SW_PORT1_PRXDCRR0_ITEDR_SHIFT (11U) 713 #define SW_PORT1_PRXDCRR0_ITEDR_WIDTH (1U) 714 #define SW_PORT1_PRXDCRR0_ITEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_ITEDR_SHIFT)) & SW_PORT1_PRXDCRR0_ITEDR_MASK) 715 716 #define SW_PORT1_PRXDCRR0_ECCEDR_MASK (0x1000U) 717 #define SW_PORT1_PRXDCRR0_ECCEDR_SHIFT (12U) 718 #define SW_PORT1_PRXDCRR0_ECCEDR_WIDTH (1U) 719 #define SW_PORT1_PRXDCRR0_ECCEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_ECCEDR_SHIFT)) & SW_PORT1_PRXDCRR0_ECCEDR_MASK) 720 721 #define SW_PORT1_PRXDCRR0_L2DOSDR_MASK (0x4000U) 722 #define SW_PORT1_PRXDCRR0_L2DOSDR_SHIFT (14U) 723 #define SW_PORT1_PRXDCRR0_L2DOSDR_WIDTH (1U) 724 #define SW_PORT1_PRXDCRR0_L2DOSDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_L2DOSDR_SHIFT)) & SW_PORT1_PRXDCRR0_L2DOSDR_MASK) 725 726 #define SW_PORT1_PRXDCRR0_PEDR_MASK (0x10000U) 727 #define SW_PORT1_PRXDCRR0_PEDR_SHIFT (16U) 728 #define SW_PORT1_PRXDCRR0_PEDR_WIDTH (1U) 729 #define SW_PORT1_PRXDCRR0_PEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_PEDR_SHIFT)) & SW_PORT1_PRXDCRR0_PEDR_MASK) 730 731 #define SW_PORT1_PRXDCRR0_NODESTDR_MASK (0x20000U) 732 #define SW_PORT1_PRXDCRR0_NODESTDR_SHIFT (17U) 733 #define SW_PORT1_PRXDCRR0_NODESTDR_WIDTH (1U) 734 #define SW_PORT1_PRXDCRR0_NODESTDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR0_NODESTDR_SHIFT)) & SW_PORT1_PRXDCRR0_NODESTDR_MASK) 735 /*! @} */ 736 737 /*! @name PRXDCRR1 - Port Rx discard count reason register 1 */ 738 /*! @{ */ 739 740 #define SW_PORT1_PRXDCRR1_ENTRYID_MASK (0xFFFFU) 741 #define SW_PORT1_PRXDCRR1_ENTRYID_SHIFT (0U) 742 #define SW_PORT1_PRXDCRR1_ENTRYID_WIDTH (16U) 743 #define SW_PORT1_PRXDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR1_ENTRYID_SHIFT)) & SW_PORT1_PRXDCRR1_ENTRYID_MASK) 744 745 #define SW_PORT1_PRXDCRR1_TT_MASK (0xF0000000U) 746 #define SW_PORT1_PRXDCRR1_TT_SHIFT (28U) 747 #define SW_PORT1_PRXDCRR1_TT_WIDTH (4U) 748 #define SW_PORT1_PRXDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PRXDCRR1_TT_SHIFT)) & SW_PORT1_PRXDCRR1_TT_MASK) 749 /*! @} */ 750 751 /*! @name PTXDCR - Port Tx discard count register */ 752 /*! @{ */ 753 754 #define SW_PORT1_PTXDCR_COUNT_MASK (0xFFFFFFFFU) 755 #define SW_PORT1_PTXDCR_COUNT_SHIFT (0U) 756 #define SW_PORT1_PTXDCR_COUNT_WIDTH (32U) 757 #define SW_PORT1_PTXDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCR_COUNT_SHIFT)) & SW_PORT1_PTXDCR_COUNT_MASK) 758 /*! @} */ 759 760 /*! @name PTXDCRR0 - Port Tx discard count reason register 0 */ 761 /*! @{ */ 762 763 #define SW_PORT1_PTXDCRR0_TXDISDR_MASK (0x1U) 764 #define SW_PORT1_PTXDCRR0_TXDISDR_SHIFT (0U) 765 #define SW_PORT1_PTXDCRR0_TXDISDR_WIDTH (1U) 766 #define SW_PORT1_PTXDCRR0_TXDISDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_TXDISDR_SHIFT)) & SW_PORT1_PTXDCRR0_TXDISDR_MASK) 767 768 #define SW_PORT1_PTXDCRR0_ECCEDR_MASK (0x2U) 769 #define SW_PORT1_PTXDCRR0_ECCEDR_SHIFT (1U) 770 #define SW_PORT1_PTXDCRR0_ECCEDR_WIDTH (1U) 771 #define SW_PORT1_PTXDCRR0_ECCEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_ECCEDR_SHIFT)) & SW_PORT1_PTXDCRR0_ECCEDR_MASK) 772 773 #define SW_PORT1_PTXDCRR0_PEDR_MASK (0x4U) 774 #define SW_PORT1_PTXDCRR0_PEDR_SHIFT (2U) 775 #define SW_PORT1_PTXDCRR0_PEDR_WIDTH (1U) 776 #define SW_PORT1_PTXDCRR0_PEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_PEDR_SHIFT)) & SW_PORT1_PTXDCRR0_PEDR_MASK) 777 778 #define SW_PORT1_PTXDCRR0_TGSFTLDR_MASK (0x10U) 779 #define SW_PORT1_PTXDCRR0_TGSFTLDR_SHIFT (4U) 780 #define SW_PORT1_PTXDCRR0_TGSFTLDR_WIDTH (1U) 781 #define SW_PORT1_PTXDCRR0_TGSFTLDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_TGSFTLDR_SHIFT)) & SW_PORT1_PTXDCRR0_TGSFTLDR_MASK) 782 783 #define SW_PORT1_PTXDCRR0_FMMDR_MASK (0x20U) 784 #define SW_PORT1_PTXDCRR0_FMMDR_SHIFT (5U) 785 #define SW_PORT1_PTXDCRR0_FMMDR_WIDTH (1U) 786 #define SW_PORT1_PTXDCRR0_FMMDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_FMMDR_SHIFT)) & SW_PORT1_PTXDCRR0_FMMDR_MASK) 787 788 #define SW_PORT1_PTXDCRR0_TXDISEDR_MASK (0x40U) 789 #define SW_PORT1_PTXDCRR0_TXDISEDR_SHIFT (6U) 790 #define SW_PORT1_PTXDCRR0_TXDISEDR_WIDTH (1U) 791 #define SW_PORT1_PTXDCRR0_TXDISEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_TXDISEDR_SHIFT)) & SW_PORT1_PTXDCRR0_TXDISEDR_MASK) 792 793 #define SW_PORT1_PTXDCRR0_MSDUEDR_MASK (0x80U) 794 #define SW_PORT1_PTXDCRR0_MSDUEDR_SHIFT (7U) 795 #define SW_PORT1_PTXDCRR0_MSDUEDR_WIDTH (1U) 796 #define SW_PORT1_PTXDCRR0_MSDUEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_MSDUEDR_SHIFT)) & SW_PORT1_PTXDCRR0_MSDUEDR_MASK) 797 798 #define SW_PORT1_PTXDCRR0_QCONGDR_MASK (0x100U) 799 #define SW_PORT1_PTXDCRR0_QCONGDR_SHIFT (8U) 800 #define SW_PORT1_PTXDCRR0_QCONGDR_WIDTH (1U) 801 #define SW_PORT1_PTXDCRR0_QCONGDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_QCONGDR_SHIFT)) & SW_PORT1_PTXDCRR0_QCONGDR_MASK) 802 803 #define SW_PORT1_PTXDCRR0_ITEDR_MASK (0x200U) 804 #define SW_PORT1_PTXDCRR0_ITEDR_SHIFT (9U) 805 #define SW_PORT1_PTXDCRR0_ITEDR_WIDTH (1U) 806 #define SW_PORT1_PTXDCRR0_ITEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_ITEDR_SHIFT)) & SW_PORT1_PTXDCRR0_ITEDR_MASK) 807 808 #define SW_PORT1_PTXDCRR0_INVEQDR_MASK (0x400U) 809 #define SW_PORT1_PTXDCRR0_INVEQDR_SHIFT (10U) 810 #define SW_PORT1_PTXDCRR0_INVEQDR_WIDTH (1U) 811 #define SW_PORT1_PTXDCRR0_INVEQDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_INVEQDR_SHIFT)) & SW_PORT1_PTXDCRR0_INVEQDR_MASK) 812 813 #define SW_PORT1_PTXDCRR0_SQRTNSQDR_MASK (0x800U) 814 #define SW_PORT1_PTXDCRR0_SQRTNSQDR_SHIFT (11U) 815 #define SW_PORT1_PTXDCRR0_SQRTNSQDR_WIDTH (1U) 816 #define SW_PORT1_PTXDCRR0_SQRTNSQDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_SQRTNSQDR_SHIFT)) & SW_PORT1_PTXDCRR0_SQRTNSQDR_MASK) 817 818 #define SW_PORT1_PTXDCRR0_SQRRDR_MASK (0x2000U) 819 #define SW_PORT1_PTXDCRR0_SQRRDR_SHIFT (13U) 820 #define SW_PORT1_PTXDCRR0_SQRRDR_WIDTH (1U) 821 #define SW_PORT1_PTXDCRR0_SQRRDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_SQRRDR_SHIFT)) & SW_PORT1_PTXDCRR0_SQRRDR_MASK) 822 823 #define SW_PORT1_PTXDCRR0_SQRDDR_MASK (0x4000U) 824 #define SW_PORT1_PTXDCRR0_SQRDDR_SHIFT (14U) 825 #define SW_PORT1_PTXDCRR0_SQRDDR_WIDTH (1U) 826 #define SW_PORT1_PTXDCRR0_SQRDDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_SQRDDR_SHIFT)) & SW_PORT1_PTXDCRR0_SQRDDR_MASK) 827 828 #define SW_PORT1_PTXDCRR0_SMREDR_MASK (0x8000U) 829 #define SW_PORT1_PTXDCRR0_SMREDR_SHIFT (15U) 830 #define SW_PORT1_PTXDCRR0_SMREDR_WIDTH (1U) 831 #define SW_PORT1_PTXDCRR0_SMREDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR0_SMREDR_SHIFT)) & SW_PORT1_PTXDCRR0_SMREDR_MASK) 832 /*! @} */ 833 834 /*! @name PTXDCRR1 - Port Tx discard count reason register 1 */ 835 /*! @{ */ 836 837 #define SW_PORT1_PTXDCRR1_ENTRYID_MASK (0xFFFFU) 838 #define SW_PORT1_PTXDCRR1_ENTRYID_SHIFT (0U) 839 #define SW_PORT1_PTXDCRR1_ENTRYID_WIDTH (16U) 840 #define SW_PORT1_PTXDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR1_ENTRYID_SHIFT)) & SW_PORT1_PTXDCRR1_ENTRYID_MASK) 841 842 #define SW_PORT1_PTXDCRR1_TT_MASK (0xF0000000U) 843 #define SW_PORT1_PTXDCRR1_TT_SHIFT (28U) 844 #define SW_PORT1_PTXDCRR1_TT_WIDTH (4U) 845 #define SW_PORT1_PTXDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTXDCRR1_TT_SHIFT)) & SW_PORT1_PTXDCRR1_TT_MASK) 846 /*! @} */ 847 848 /*! @name PTGSTCSR - Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register */ 849 /*! @{ */ 850 851 #define SW_PORT1_PTGSTCSR_LH_STATE_MASK (0x10000U) 852 #define SW_PORT1_PTGSTCSR_LH_STATE_SHIFT (16U) 853 #define SW_PORT1_PTGSTCSR_LH_STATE_WIDTH (1U) 854 #define SW_PORT1_PTGSTCSR_LH_STATE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTGSTCSR_LH_STATE_SHIFT)) & SW_PORT1_PTGSTCSR_LH_STATE_MASK) 855 /*! @} */ 856 857 /*! @name PTCTMSDUR - Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register */ 858 /*! @{ */ 859 860 #define SW_PORT1_PTCTMSDUR_MAXSDU_MASK (0xFFFFU) 861 #define SW_PORT1_PTCTMSDUR_MAXSDU_SHIFT (0U) 862 #define SW_PORT1_PTCTMSDUR_MAXSDU_WIDTH (16U) 863 #define SW_PORT1_PTCTMSDUR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCTMSDUR_MAXSDU_SHIFT)) & SW_PORT1_PTCTMSDUR_MAXSDU_MASK) 864 865 #define SW_PORT1_PTCTMSDUR_SDU_TYPE_MASK (0x30000U) 866 #define SW_PORT1_PTCTMSDUR_SDU_TYPE_SHIFT (16U) 867 #define SW_PORT1_PTCTMSDUR_SDU_TYPE_WIDTH (2U) 868 #define SW_PORT1_PTCTMSDUR_SDU_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCTMSDUR_SDU_TYPE_SHIFT)) & SW_PORT1_PTCTMSDUR_SDU_TYPE_MASK) 869 870 #define SW_PORT1_PTCTMSDUR_SF_MAXSDU_DIS_MASK (0x1000000U) 871 #define SW_PORT1_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT (24U) 872 #define SW_PORT1_PTCTMSDUR_SF_MAXSDU_DIS_WIDTH (1U) 873 #define SW_PORT1_PTCTMSDUR_SF_MAXSDU_DIS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT)) & SW_PORT1_PTCTMSDUR_SF_MAXSDU_DIS_MASK) 874 /*! @} */ 875 876 /*! @name PTCCBSR0 - Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0 */ 877 /*! @{ */ 878 879 #define SW_PORT1_PTCCBSR0_BW_MASK (0x7FU) 880 #define SW_PORT1_PTCCBSR0_BW_SHIFT (0U) 881 #define SW_PORT1_PTCCBSR0_BW_WIDTH (7U) 882 #define SW_PORT1_PTCCBSR0_BW(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCCBSR0_BW_SHIFT)) & SW_PORT1_PTCCBSR0_BW_MASK) 883 884 #define SW_PORT1_PTCCBSR0_CBSE_MASK (0x80000000U) 885 #define SW_PORT1_PTCCBSR0_CBSE_SHIFT (31U) 886 #define SW_PORT1_PTCCBSR0_CBSE_WIDTH (1U) 887 #define SW_PORT1_PTCCBSR0_CBSE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCCBSR0_CBSE_SHIFT)) & SW_PORT1_PTCCBSR0_CBSE_MASK) 888 /*! @} */ 889 890 /*! @name PTCCBSR1 - Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1 */ 891 /*! @{ */ 892 893 #define SW_PORT1_PTCCBSR1_HI_CREDIT_MASK (0xFFFFFFFFU) 894 #define SW_PORT1_PTCCBSR1_HI_CREDIT_SHIFT (0U) 895 #define SW_PORT1_PTCCBSR1_HI_CREDIT_WIDTH (32U) 896 #define SW_PORT1_PTCCBSR1_HI_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCCBSR1_HI_CREDIT_SHIFT)) & SW_PORT1_PTCCBSR1_HI_CREDIT_MASK) 897 /*! @} */ 898 899 /*! @name PBPMCR0 - Port buffer pool mapping configuration register 0 */ 900 /*! @{ */ 901 902 #define SW_PORT1_PBPMCR0_IPV0_INDEX_MASK (0xFFU) 903 #define SW_PORT1_PBPMCR0_IPV0_INDEX_SHIFT (0U) 904 #define SW_PORT1_PBPMCR0_IPV0_INDEX_WIDTH (8U) 905 #define SW_PORT1_PBPMCR0_IPV0_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR0_IPV0_INDEX_SHIFT)) & SW_PORT1_PBPMCR0_IPV0_INDEX_MASK) 906 907 #define SW_PORT1_PBPMCR0_IPV1_INDEX_MASK (0xFF00U) 908 #define SW_PORT1_PBPMCR0_IPV1_INDEX_SHIFT (8U) 909 #define SW_PORT1_PBPMCR0_IPV1_INDEX_WIDTH (8U) 910 #define SW_PORT1_PBPMCR0_IPV1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR0_IPV1_INDEX_SHIFT)) & SW_PORT1_PBPMCR0_IPV1_INDEX_MASK) 911 912 #define SW_PORT1_PBPMCR0_IPV2_INDEX_MASK (0xFF0000U) 913 #define SW_PORT1_PBPMCR0_IPV2_INDEX_SHIFT (16U) 914 #define SW_PORT1_PBPMCR0_IPV2_INDEX_WIDTH (8U) 915 #define SW_PORT1_PBPMCR0_IPV2_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR0_IPV2_INDEX_SHIFT)) & SW_PORT1_PBPMCR0_IPV2_INDEX_MASK) 916 917 #define SW_PORT1_PBPMCR0_IPV3_INDEX_MASK (0xFF000000U) 918 #define SW_PORT1_PBPMCR0_IPV3_INDEX_SHIFT (24U) 919 #define SW_PORT1_PBPMCR0_IPV3_INDEX_WIDTH (8U) 920 #define SW_PORT1_PBPMCR0_IPV3_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR0_IPV3_INDEX_SHIFT)) & SW_PORT1_PBPMCR0_IPV3_INDEX_MASK) 921 /*! @} */ 922 923 /*! @name PBPMCR1 - Port buffer pool mapping configuration register 1 */ 924 /*! @{ */ 925 926 #define SW_PORT1_PBPMCR1_IPV4_INDEX_MASK (0xFFU) 927 #define SW_PORT1_PBPMCR1_IPV4_INDEX_SHIFT (0U) 928 #define SW_PORT1_PBPMCR1_IPV4_INDEX_WIDTH (8U) 929 #define SW_PORT1_PBPMCR1_IPV4_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR1_IPV4_INDEX_SHIFT)) & SW_PORT1_PBPMCR1_IPV4_INDEX_MASK) 930 931 #define SW_PORT1_PBPMCR1_IPV5_INDEX_MASK (0xFF00U) 932 #define SW_PORT1_PBPMCR1_IPV5_INDEX_SHIFT (8U) 933 #define SW_PORT1_PBPMCR1_IPV5_INDEX_WIDTH (8U) 934 #define SW_PORT1_PBPMCR1_IPV5_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR1_IPV5_INDEX_SHIFT)) & SW_PORT1_PBPMCR1_IPV5_INDEX_MASK) 935 936 #define SW_PORT1_PBPMCR1_IPV6_INDEX_MASK (0xFF0000U) 937 #define SW_PORT1_PBPMCR1_IPV6_INDEX_SHIFT (16U) 938 #define SW_PORT1_PBPMCR1_IPV6_INDEX_WIDTH (8U) 939 #define SW_PORT1_PBPMCR1_IPV6_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR1_IPV6_INDEX_SHIFT)) & SW_PORT1_PBPMCR1_IPV6_INDEX_MASK) 940 941 #define SW_PORT1_PBPMCR1_IPV7_INDEX_MASK (0xFF000000U) 942 #define SW_PORT1_PBPMCR1_IPV7_INDEX_SHIFT (24U) 943 #define SW_PORT1_PBPMCR1_IPV7_INDEX_WIDTH (8U) 944 #define SW_PORT1_PBPMCR1_IPV7_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PBPMCR1_IPV7_INDEX_SHIFT)) & SW_PORT1_PBPMCR1_IPV7_INDEX_MASK) 945 /*! @} */ 946 947 /*! @name PPCPDEIMR - Port PCP DEI mapping register */ 948 /*! @{ */ 949 950 #define SW_PORT1_PPCPDEIMR_IPCPMP_MASK (0xFU) 951 #define SW_PORT1_PPCPDEIMR_IPCPMP_SHIFT (0U) 952 #define SW_PORT1_PPCPDEIMR_IPCPMP_WIDTH (4U) 953 #define SW_PORT1_PPCPDEIMR_IPCPMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_IPCPMP_SHIFT)) & SW_PORT1_PPCPDEIMR_IPCPMP_MASK) 954 955 #define SW_PORT1_PPCPDEIMR_IPCPMPV_MASK (0x80U) 956 #define SW_PORT1_PPCPDEIMR_IPCPMPV_SHIFT (7U) 957 #define SW_PORT1_PPCPDEIMR_IPCPMPV_WIDTH (1U) 958 #define SW_PORT1_PPCPDEIMR_IPCPMPV(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_IPCPMPV_SHIFT)) & SW_PORT1_PPCPDEIMR_IPCPMPV_MASK) 959 960 #define SW_PORT1_PPCPDEIMR_EPCPMP_MASK (0xF00U) 961 #define SW_PORT1_PPCPDEIMR_EPCPMP_SHIFT (8U) 962 #define SW_PORT1_PPCPDEIMR_EPCPMP_WIDTH (4U) 963 #define SW_PORT1_PPCPDEIMR_EPCPMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_EPCPMP_SHIFT)) & SW_PORT1_PPCPDEIMR_EPCPMP_MASK) 964 965 #define SW_PORT1_PPCPDEIMR_EPCPMPV_MASK (0x8000U) 966 #define SW_PORT1_PPCPDEIMR_EPCPMPV_SHIFT (15U) 967 #define SW_PORT1_PPCPDEIMR_EPCPMPV_WIDTH (1U) 968 #define SW_PORT1_PPCPDEIMR_EPCPMPV(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_EPCPMPV_SHIFT)) & SW_PORT1_PPCPDEIMR_EPCPMPV_MASK) 969 970 #define SW_PORT1_PPCPDEIMR_DR0DEI_MASK (0x10000U) 971 #define SW_PORT1_PPCPDEIMR_DR0DEI_SHIFT (16U) 972 #define SW_PORT1_PPCPDEIMR_DR0DEI_WIDTH (1U) 973 #define SW_PORT1_PPCPDEIMR_DR0DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_DR0DEI_SHIFT)) & SW_PORT1_PPCPDEIMR_DR0DEI_MASK) 974 975 #define SW_PORT1_PPCPDEIMR_DR1DEI_MASK (0x20000U) 976 #define SW_PORT1_PPCPDEIMR_DR1DEI_SHIFT (17U) 977 #define SW_PORT1_PPCPDEIMR_DR1DEI_WIDTH (1U) 978 #define SW_PORT1_PPCPDEIMR_DR1DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_DR1DEI_SHIFT)) & SW_PORT1_PPCPDEIMR_DR1DEI_MASK) 979 980 #define SW_PORT1_PPCPDEIMR_DR2DEI_MASK (0x40000U) 981 #define SW_PORT1_PPCPDEIMR_DR2DEI_SHIFT (18U) 982 #define SW_PORT1_PPCPDEIMR_DR2DEI_WIDTH (1U) 983 #define SW_PORT1_PPCPDEIMR_DR2DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_DR2DEI_SHIFT)) & SW_PORT1_PPCPDEIMR_DR2DEI_MASK) 984 985 #define SW_PORT1_PPCPDEIMR_DR3DEI_MASK (0x80000U) 986 #define SW_PORT1_PPCPDEIMR_DR3DEI_SHIFT (19U) 987 #define SW_PORT1_PPCPDEIMR_DR3DEI_WIDTH (1U) 988 #define SW_PORT1_PPCPDEIMR_DR3DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_DR3DEI_SHIFT)) & SW_PORT1_PPCPDEIMR_DR3DEI_MASK) 989 990 #define SW_PORT1_PPCPDEIMR_DRME_MASK (0x100000U) 991 #define SW_PORT1_PPCPDEIMR_DRME_SHIFT (20U) 992 #define SW_PORT1_PPCPDEIMR_DRME_WIDTH (1U) 993 #define SW_PORT1_PPCPDEIMR_DRME(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PPCPDEIMR_DRME_SHIFT)) & SW_PORT1_PPCPDEIMR_DRME_MASK) 994 /*! @} */ 995 996 /*! @name PMCR - Port mirror configuration register */ 997 /*! @{ */ 998 999 #define SW_PORT1_PMCR_IMIRE_MASK (0x1U) 1000 #define SW_PORT1_PMCR_IMIRE_SHIFT (0U) 1001 #define SW_PORT1_PMCR_IMIRE_WIDTH (1U) 1002 #define SW_PORT1_PMCR_IMIRE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PMCR_IMIRE_SHIFT)) & SW_PORT1_PMCR_IMIRE_MASK) 1003 /*! @} */ 1004 1005 /*! @name PCTFCR - Port cut through forwarding configuration register */ 1006 /*! @{ */ 1007 1008 #define SW_PORT1_PCTFCR_ICTS_MASK (0x1U) 1009 #define SW_PORT1_PCTFCR_ICTS_SHIFT (0U) 1010 #define SW_PORT1_PCTFCR_ICTS_WIDTH (1U) 1011 #define SW_PORT1_PCTFCR_ICTS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCTFCR_ICTS_SHIFT)) & SW_PORT1_PCTFCR_ICTS_MASK) 1012 1013 #define SW_PORT1_PCTFCR_ECTS_MASK (0x2U) 1014 #define SW_PORT1_PCTFCR_ECTS_SHIFT (1U) 1015 #define SW_PORT1_PCTFCR_ECTS_WIDTH (1U) 1016 #define SW_PORT1_PCTFCR_ECTS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCTFCR_ECTS_SHIFT)) & SW_PORT1_PCTFCR_ECTS_MASK) 1017 1018 #define SW_PORT1_PCTFCR_BSQS_MASK (0x30U) 1019 #define SW_PORT1_PCTFCR_BSQS_SHIFT (4U) 1020 #define SW_PORT1_PCTFCR_BSQS_WIDTH (2U) 1021 #define SW_PORT1_PCTFCR_BSQS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PCTFCR_BSQS_SHIFT)) & SW_PORT1_PCTFCR_BSQS_MASK) 1022 /*! @} */ 1023 1024 /*! @name PLANIDCR - Port LANID configuration register */ 1025 /*! @{ */ 1026 1027 #define SW_PORT1_PLANIDCR_LANID_MASK (0xFU) 1028 #define SW_PORT1_PLANIDCR_LANID_SHIFT (0U) 1029 #define SW_PORT1_PLANIDCR_LANID_WIDTH (4U) 1030 #define SW_PORT1_PLANIDCR_LANID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PLANIDCR_LANID_SHIFT)) & SW_PORT1_PLANIDCR_LANID_MASK) 1031 /*! @} */ 1032 1033 /*! @name PISIDCR - Port ingress stream identification configuration register */ 1034 /*! @{ */ 1035 1036 #define SW_PORT1_PISIDCR_KCPAIR_MASK (0x1U) 1037 #define SW_PORT1_PISIDCR_KCPAIR_SHIFT (0U) 1038 #define SW_PORT1_PISIDCR_KCPAIR_WIDTH (1U) 1039 #define SW_PORT1_PISIDCR_KCPAIR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PISIDCR_KCPAIR_SHIFT)) & SW_PORT1_PISIDCR_KCPAIR_MASK) 1040 1041 #define SW_PORT1_PISIDCR_KC0EN_MASK (0x2U) 1042 #define SW_PORT1_PISIDCR_KC0EN_SHIFT (1U) 1043 #define SW_PORT1_PISIDCR_KC0EN_WIDTH (1U) 1044 #define SW_PORT1_PISIDCR_KC0EN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PISIDCR_KC0EN_SHIFT)) & SW_PORT1_PISIDCR_KC0EN_MASK) 1045 1046 #define SW_PORT1_PISIDCR_KC1EN_MASK (0x4U) 1047 #define SW_PORT1_PISIDCR_KC1EN_SHIFT (2U) 1048 #define SW_PORT1_PISIDCR_KC1EN_WIDTH (1U) 1049 #define SW_PORT1_PISIDCR_KC1EN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PISIDCR_KC1EN_SHIFT)) & SW_PORT1_PISIDCR_KC1EN_MASK) 1050 1051 #define SW_PORT1_PISIDCR_ISEID_MASK (0xFFFF0000U) 1052 #define SW_PORT1_PISIDCR_ISEID_SHIFT (16U) 1053 #define SW_PORT1_PISIDCR_ISEID_WIDTH (16U) 1054 #define SW_PORT1_PISIDCR_ISEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PISIDCR_ISEID_SHIFT)) & SW_PORT1_PISIDCR_ISEID_MASK) 1055 /*! @} */ 1056 1057 /*! @name PFMCR - Port frame modification configuration register */ 1058 /*! @{ */ 1059 1060 #define SW_PORT1_PFMCR_FMMA_MASK (0x1U) 1061 #define SW_PORT1_PFMCR_FMMA_SHIFT (0U) 1062 #define SW_PORT1_PFMCR_FMMA_WIDTH (1U) 1063 #define SW_PORT1_PFMCR_FMMA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PFMCR_FMMA_SHIFT)) & SW_PORT1_PFMCR_FMMA_MASK) 1064 /*! @} */ 1065 1066 /*! @name PIPV2QMR0 - Port IPV to queue mapping register 0 */ 1067 /*! @{ */ 1068 1069 #define SW_PORT1_PIPV2QMR0_IPV0_Q_MASK (0xFU) 1070 #define SW_PORT1_PIPV2QMR0_IPV0_Q_SHIFT (0U) 1071 #define SW_PORT1_PIPV2QMR0_IPV0_Q_WIDTH (4U) 1072 #define SW_PORT1_PIPV2QMR0_IPV0_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV0_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV0_Q_MASK) 1073 1074 #define SW_PORT1_PIPV2QMR0_IPV1_Q_MASK (0xF0U) 1075 #define SW_PORT1_PIPV2QMR0_IPV1_Q_SHIFT (4U) 1076 #define SW_PORT1_PIPV2QMR0_IPV1_Q_WIDTH (4U) 1077 #define SW_PORT1_PIPV2QMR0_IPV1_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV1_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV1_Q_MASK) 1078 1079 #define SW_PORT1_PIPV2QMR0_IPV2_Q_MASK (0xF00U) 1080 #define SW_PORT1_PIPV2QMR0_IPV2_Q_SHIFT (8U) 1081 #define SW_PORT1_PIPV2QMR0_IPV2_Q_WIDTH (4U) 1082 #define SW_PORT1_PIPV2QMR0_IPV2_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV2_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV2_Q_MASK) 1083 1084 #define SW_PORT1_PIPV2QMR0_IPV3_Q_MASK (0xF000U) 1085 #define SW_PORT1_PIPV2QMR0_IPV3_Q_SHIFT (12U) 1086 #define SW_PORT1_PIPV2QMR0_IPV3_Q_WIDTH (4U) 1087 #define SW_PORT1_PIPV2QMR0_IPV3_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV3_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV3_Q_MASK) 1088 1089 #define SW_PORT1_PIPV2QMR0_IPV4_Q_MASK (0xF0000U) 1090 #define SW_PORT1_PIPV2QMR0_IPV4_Q_SHIFT (16U) 1091 #define SW_PORT1_PIPV2QMR0_IPV4_Q_WIDTH (4U) 1092 #define SW_PORT1_PIPV2QMR0_IPV4_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV4_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV4_Q_MASK) 1093 1094 #define SW_PORT1_PIPV2QMR0_IPV5_Q_MASK (0xF00000U) 1095 #define SW_PORT1_PIPV2QMR0_IPV5_Q_SHIFT (20U) 1096 #define SW_PORT1_PIPV2QMR0_IPV5_Q_WIDTH (4U) 1097 #define SW_PORT1_PIPV2QMR0_IPV5_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV5_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV5_Q_MASK) 1098 1099 #define SW_PORT1_PIPV2QMR0_IPV6_Q_MASK (0xF000000U) 1100 #define SW_PORT1_PIPV2QMR0_IPV6_Q_SHIFT (24U) 1101 #define SW_PORT1_PIPV2QMR0_IPV6_Q_WIDTH (4U) 1102 #define SW_PORT1_PIPV2QMR0_IPV6_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV6_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV6_Q_MASK) 1103 1104 #define SW_PORT1_PIPV2QMR0_IPV7_Q_MASK (0xF0000000U) 1105 #define SW_PORT1_PIPV2QMR0_IPV7_Q_SHIFT (28U) 1106 #define SW_PORT1_PIPV2QMR0_IPV7_Q_WIDTH (4U) 1107 #define SW_PORT1_PIPV2QMR0_IPV7_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PIPV2QMR0_IPV7_Q_SHIFT)) & SW_PORT1_PIPV2QMR0_IPV7_Q_MASK) 1108 /*! @} */ 1109 1110 /*! @name PTCMINLR - Port time capture minimum latency register */ 1111 /*! @{ */ 1112 1113 #define SW_PORT1_PTCMINLR_LATENCY_MASK (0x3FFFFFFFU) 1114 #define SW_PORT1_PTCMINLR_LATENCY_SHIFT (0U) 1115 #define SW_PORT1_PTCMINLR_LATENCY_WIDTH (30U) 1116 #define SW_PORT1_PTCMINLR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCMINLR_LATENCY_SHIFT)) & SW_PORT1_PTCMINLR_LATENCY_MASK) 1117 1118 #define SW_PORT1_PTCMINLR_COUNT_MASK (0xC0000000U) 1119 #define SW_PORT1_PTCMINLR_COUNT_SHIFT (30U) 1120 #define SW_PORT1_PTCMINLR_COUNT_WIDTH (2U) 1121 #define SW_PORT1_PTCMINLR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCMINLR_COUNT_SHIFT)) & SW_PORT1_PTCMINLR_COUNT_MASK) 1122 /*! @} */ 1123 1124 /*! @name PTCMAXLR - Port time capture maximum latency register */ 1125 /*! @{ */ 1126 1127 #define SW_PORT1_PTCMAXLR_LATENCY_MASK (0x3FFFFFFFU) 1128 #define SW_PORT1_PTCMAXLR_LATENCY_SHIFT (0U) 1129 #define SW_PORT1_PTCMAXLR_LATENCY_WIDTH (30U) 1130 #define SW_PORT1_PTCMAXLR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_PTCMAXLR_LATENCY_SHIFT)) & SW_PORT1_PTCMAXLR_LATENCY_MASK) 1131 /*! @} */ 1132 1133 /*! @name BPCR - Bridge port configuration register */ 1134 /*! @{ */ 1135 1136 #define SW_PORT1_BPCR_DYN_LIMIT_MASK (0xFFFFU) 1137 #define SW_PORT1_BPCR_DYN_LIMIT_SHIFT (0U) 1138 #define SW_PORT1_BPCR_DYN_LIMIT_WIDTH (16U) 1139 #define SW_PORT1_BPCR_DYN_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_DYN_LIMIT_SHIFT)) & SW_PORT1_BPCR_DYN_LIMIT_MASK) 1140 1141 #define SW_PORT1_BPCR_UUCASTE_MASK (0x1000000U) 1142 #define SW_PORT1_BPCR_UUCASTE_SHIFT (24U) 1143 #define SW_PORT1_BPCR_UUCASTE_WIDTH (1U) 1144 #define SW_PORT1_BPCR_UUCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_UUCASTE_SHIFT)) & SW_PORT1_BPCR_UUCASTE_MASK) 1145 1146 #define SW_PORT1_BPCR_UMCASTE_MASK (0x2000000U) 1147 #define SW_PORT1_BPCR_UMCASTE_SHIFT (25U) 1148 #define SW_PORT1_BPCR_UMCASTE_WIDTH (1U) 1149 #define SW_PORT1_BPCR_UMCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_UMCASTE_SHIFT)) & SW_PORT1_BPCR_UMCASTE_MASK) 1150 1151 #define SW_PORT1_BPCR_MCASTE_MASK (0x4000000U) 1152 #define SW_PORT1_BPCR_MCASTE_SHIFT (26U) 1153 #define SW_PORT1_BPCR_MCASTE_WIDTH (1U) 1154 #define SW_PORT1_BPCR_MCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_MCASTE_SHIFT)) & SW_PORT1_BPCR_MCASTE_MASK) 1155 1156 #define SW_PORT1_BPCR_BCASTE_MASK (0x8000000U) 1157 #define SW_PORT1_BPCR_BCASTE_SHIFT (27U) 1158 #define SW_PORT1_BPCR_BCASTE_WIDTH (1U) 1159 #define SW_PORT1_BPCR_BCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_BCASTE_SHIFT)) & SW_PORT1_BPCR_BCASTE_MASK) 1160 1161 #define SW_PORT1_BPCR_STAMVD_MASK (0x10000000U) 1162 #define SW_PORT1_BPCR_STAMVD_SHIFT (28U) 1163 #define SW_PORT1_BPCR_STAMVD_WIDTH (1U) 1164 #define SW_PORT1_BPCR_STAMVD(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_STAMVD_SHIFT)) & SW_PORT1_BPCR_STAMVD_MASK) 1165 1166 #define SW_PORT1_BPCR_SRCPRND_MASK (0x20000000U) 1167 #define SW_PORT1_BPCR_SRCPRND_SHIFT (29U) 1168 #define SW_PORT1_BPCR_SRCPRND_WIDTH (1U) 1169 #define SW_PORT1_BPCR_SRCPRND(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPCR_SRCPRND_SHIFT)) & SW_PORT1_BPCR_SRCPRND_MASK) 1170 /*! @} */ 1171 1172 /*! @name BPDVR - Bridge port default VLAN register */ 1173 /*! @{ */ 1174 1175 #define SW_PORT1_BPDVR_VID_MASK (0xFFFU) 1176 #define SW_PORT1_BPDVR_VID_SHIFT (0U) 1177 #define SW_PORT1_BPDVR_VID_WIDTH (12U) 1178 #define SW_PORT1_BPDVR_VID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_VID_SHIFT)) & SW_PORT1_BPDVR_VID_MASK) 1179 1180 #define SW_PORT1_BPDVR_DEI_MASK (0x1000U) 1181 #define SW_PORT1_BPDVR_DEI_SHIFT (12U) 1182 #define SW_PORT1_BPDVR_DEI_WIDTH (1U) 1183 #define SW_PORT1_BPDVR_DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_DEI_SHIFT)) & SW_PORT1_BPDVR_DEI_MASK) 1184 1185 #define SW_PORT1_BPDVR_PCP_MASK (0xE000U) 1186 #define SW_PORT1_BPDVR_PCP_SHIFT (13U) 1187 #define SW_PORT1_BPDVR_PCP_WIDTH (3U) 1188 #define SW_PORT1_BPDVR_PCP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_PCP_SHIFT)) & SW_PORT1_BPDVR_PCP_MASK) 1189 1190 #define SW_PORT1_BPDVR_TPID_MASK (0x10000U) 1191 #define SW_PORT1_BPDVR_TPID_SHIFT (16U) 1192 #define SW_PORT1_BPDVR_TPID_WIDTH (1U) 1193 #define SW_PORT1_BPDVR_TPID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_TPID_SHIFT)) & SW_PORT1_BPDVR_TPID_MASK) 1194 1195 #define SW_PORT1_BPDVR_RXTAGA_MASK (0xF00000U) 1196 #define SW_PORT1_BPDVR_RXTAGA_SHIFT (20U) 1197 #define SW_PORT1_BPDVR_RXTAGA_WIDTH (4U) 1198 #define SW_PORT1_BPDVR_RXTAGA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_RXTAGA_SHIFT)) & SW_PORT1_BPDVR_RXTAGA_MASK) 1199 1200 #define SW_PORT1_BPDVR_RXVAM_MASK (0x1000000U) 1201 #define SW_PORT1_BPDVR_RXVAM_SHIFT (24U) 1202 #define SW_PORT1_BPDVR_RXVAM_WIDTH (1U) 1203 #define SW_PORT1_BPDVR_RXVAM(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_RXVAM_SHIFT)) & SW_PORT1_BPDVR_RXVAM_MASK) 1204 1205 #define SW_PORT1_BPDVR_TXTAGA_MASK (0x6000000U) 1206 #define SW_PORT1_BPDVR_TXTAGA_SHIFT (25U) 1207 #define SW_PORT1_BPDVR_TXTAGA_WIDTH (2U) 1208 #define SW_PORT1_BPDVR_TXTAGA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDVR_TXTAGA_SHIFT)) & SW_PORT1_BPDVR_TXTAGA_MASK) 1209 /*! @} */ 1210 1211 /*! @name BPSTGSR - Bridge port spanning tree group state register */ 1212 /*! @{ */ 1213 1214 #define SW_PORT1_BPSTGSR_STG_STATE0_MASK (0x3U) 1215 #define SW_PORT1_BPSTGSR_STG_STATE0_SHIFT (0U) 1216 #define SW_PORT1_BPSTGSR_STG_STATE0_WIDTH (2U) 1217 #define SW_PORT1_BPSTGSR_STG_STATE0(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE0_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE0_MASK) 1218 1219 #define SW_PORT1_BPSTGSR_STG_STATE1_MASK (0xCU) 1220 #define SW_PORT1_BPSTGSR_STG_STATE1_SHIFT (2U) 1221 #define SW_PORT1_BPSTGSR_STG_STATE1_WIDTH (2U) 1222 #define SW_PORT1_BPSTGSR_STG_STATE1(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE1_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE1_MASK) 1223 1224 #define SW_PORT1_BPSTGSR_STG_STATE2_MASK (0x30U) 1225 #define SW_PORT1_BPSTGSR_STG_STATE2_SHIFT (4U) 1226 #define SW_PORT1_BPSTGSR_STG_STATE2_WIDTH (2U) 1227 #define SW_PORT1_BPSTGSR_STG_STATE2(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE2_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE2_MASK) 1228 1229 #define SW_PORT1_BPSTGSR_STG_STATE3_MASK (0xC0U) 1230 #define SW_PORT1_BPSTGSR_STG_STATE3_SHIFT (6U) 1231 #define SW_PORT1_BPSTGSR_STG_STATE3_WIDTH (2U) 1232 #define SW_PORT1_BPSTGSR_STG_STATE3(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE3_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE3_MASK) 1233 1234 #define SW_PORT1_BPSTGSR_STG_STATE4_MASK (0x300U) 1235 #define SW_PORT1_BPSTGSR_STG_STATE4_SHIFT (8U) 1236 #define SW_PORT1_BPSTGSR_STG_STATE4_WIDTH (2U) 1237 #define SW_PORT1_BPSTGSR_STG_STATE4(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE4_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE4_MASK) 1238 1239 #define SW_PORT1_BPSTGSR_STG_STATE5_MASK (0xC00U) 1240 #define SW_PORT1_BPSTGSR_STG_STATE5_SHIFT (10U) 1241 #define SW_PORT1_BPSTGSR_STG_STATE5_WIDTH (2U) 1242 #define SW_PORT1_BPSTGSR_STG_STATE5(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE5_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE5_MASK) 1243 1244 #define SW_PORT1_BPSTGSR_STG_STATE6_MASK (0x3000U) 1245 #define SW_PORT1_BPSTGSR_STG_STATE6_SHIFT (12U) 1246 #define SW_PORT1_BPSTGSR_STG_STATE6_WIDTH (2U) 1247 #define SW_PORT1_BPSTGSR_STG_STATE6(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE6_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE6_MASK) 1248 1249 #define SW_PORT1_BPSTGSR_STG_STATE7_MASK (0xC000U) 1250 #define SW_PORT1_BPSTGSR_STG_STATE7_SHIFT (14U) 1251 #define SW_PORT1_BPSTGSR_STG_STATE7_WIDTH (2U) 1252 #define SW_PORT1_BPSTGSR_STG_STATE7(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE7_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE7_MASK) 1253 1254 #define SW_PORT1_BPSTGSR_STG_STATE8_MASK (0x30000U) 1255 #define SW_PORT1_BPSTGSR_STG_STATE8_SHIFT (16U) 1256 #define SW_PORT1_BPSTGSR_STG_STATE8_WIDTH (2U) 1257 #define SW_PORT1_BPSTGSR_STG_STATE8(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE8_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE8_MASK) 1258 1259 #define SW_PORT1_BPSTGSR_STG_STATE9_MASK (0xC0000U) 1260 #define SW_PORT1_BPSTGSR_STG_STATE9_SHIFT (18U) 1261 #define SW_PORT1_BPSTGSR_STG_STATE9_WIDTH (2U) 1262 #define SW_PORT1_BPSTGSR_STG_STATE9(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE9_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE9_MASK) 1263 1264 #define SW_PORT1_BPSTGSR_STG_STATE10_MASK (0x300000U) 1265 #define SW_PORT1_BPSTGSR_STG_STATE10_SHIFT (20U) 1266 #define SW_PORT1_BPSTGSR_STG_STATE10_WIDTH (2U) 1267 #define SW_PORT1_BPSTGSR_STG_STATE10(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE10_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE10_MASK) 1268 1269 #define SW_PORT1_BPSTGSR_STG_STATE11_MASK (0xC00000U) 1270 #define SW_PORT1_BPSTGSR_STG_STATE11_SHIFT (22U) 1271 #define SW_PORT1_BPSTGSR_STG_STATE11_WIDTH (2U) 1272 #define SW_PORT1_BPSTGSR_STG_STATE11(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE11_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE11_MASK) 1273 1274 #define SW_PORT1_BPSTGSR_STG_STATE12_MASK (0x3000000U) 1275 #define SW_PORT1_BPSTGSR_STG_STATE12_SHIFT (24U) 1276 #define SW_PORT1_BPSTGSR_STG_STATE12_WIDTH (2U) 1277 #define SW_PORT1_BPSTGSR_STG_STATE12(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE12_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE12_MASK) 1278 1279 #define SW_PORT1_BPSTGSR_STG_STATE13_MASK (0xC000000U) 1280 #define SW_PORT1_BPSTGSR_STG_STATE13_SHIFT (26U) 1281 #define SW_PORT1_BPSTGSR_STG_STATE13_WIDTH (2U) 1282 #define SW_PORT1_BPSTGSR_STG_STATE13(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE13_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE13_MASK) 1283 1284 #define SW_PORT1_BPSTGSR_STG_STATE14_MASK (0x30000000U) 1285 #define SW_PORT1_BPSTGSR_STG_STATE14_SHIFT (28U) 1286 #define SW_PORT1_BPSTGSR_STG_STATE14_WIDTH (2U) 1287 #define SW_PORT1_BPSTGSR_STG_STATE14(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE14_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE14_MASK) 1288 1289 #define SW_PORT1_BPSTGSR_STG_STATE15_MASK (0xC0000000U) 1290 #define SW_PORT1_BPSTGSR_STG_STATE15_SHIFT (30U) 1291 #define SW_PORT1_BPSTGSR_STG_STATE15_WIDTH (2U) 1292 #define SW_PORT1_BPSTGSR_STG_STATE15(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSTGSR_STG_STATE15_SHIFT)) & SW_PORT1_BPSTGSR_STG_STATE15_MASK) 1293 /*! @} */ 1294 1295 /*! @name BPSCR0 - Bridge port storm control register 0 */ 1296 /*! @{ */ 1297 1298 #define SW_PORT1_BPSCR0_UUCASTRPEID_MASK (0xFFFU) 1299 #define SW_PORT1_BPSCR0_UUCASTRPEID_SHIFT (0U) 1300 #define SW_PORT1_BPSCR0_UUCASTRPEID_WIDTH (12U) 1301 #define SW_PORT1_BPSCR0_UUCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSCR0_UUCASTRPEID_SHIFT)) & SW_PORT1_BPSCR0_UUCASTRPEID_MASK) 1302 1303 #define SW_PORT1_BPSCR0_BCASTRPEID_MASK (0xFFF0000U) 1304 #define SW_PORT1_BPSCR0_BCASTRPEID_SHIFT (16U) 1305 #define SW_PORT1_BPSCR0_BCASTRPEID_WIDTH (12U) 1306 #define SW_PORT1_BPSCR0_BCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSCR0_BCASTRPEID_SHIFT)) & SW_PORT1_BPSCR0_BCASTRPEID_MASK) 1307 /*! @} */ 1308 1309 /*! @name BPSCR1 - Bridge port storm control register 1 */ 1310 /*! @{ */ 1311 1312 #define SW_PORT1_BPSCR1_MCASTRPEID_MASK (0xFFFU) 1313 #define SW_PORT1_BPSCR1_MCASTRPEID_SHIFT (0U) 1314 #define SW_PORT1_BPSCR1_MCASTRPEID_WIDTH (12U) 1315 #define SW_PORT1_BPSCR1_MCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSCR1_MCASTRPEID_SHIFT)) & SW_PORT1_BPSCR1_MCASTRPEID_MASK) 1316 1317 #define SW_PORT1_BPSCR1_UMCASTRPEID_MASK (0xFFF0000U) 1318 #define SW_PORT1_BPSCR1_UMCASTRPEID_SHIFT (16U) 1319 #define SW_PORT1_BPSCR1_UMCASTRPEID_WIDTH (12U) 1320 #define SW_PORT1_BPSCR1_UMCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPSCR1_UMCASTRPEID_SHIFT)) & SW_PORT1_BPSCR1_UMCASTRPEID_MASK) 1321 /*! @} */ 1322 1323 /*! @name BPOR - Bridge port operational register */ 1324 /*! @{ */ 1325 1326 #define SW_PORT1_BPOR_NUM_DYN_MASK (0xFFFFU) 1327 #define SW_PORT1_BPOR_NUM_DYN_SHIFT (0U) 1328 #define SW_PORT1_BPOR_NUM_DYN_WIDTH (16U) 1329 #define SW_PORT1_BPOR_NUM_DYN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPOR_NUM_DYN_SHIFT)) & SW_PORT1_BPOR_NUM_DYN_MASK) 1330 /*! @} */ 1331 1332 /*! @name BPDCR - Bridge port discard count register */ 1333 /*! @{ */ 1334 1335 #define SW_PORT1_BPDCR_COUNT_MASK (0xFFFFFFFFU) 1336 #define SW_PORT1_BPDCR_COUNT_SHIFT (0U) 1337 #define SW_PORT1_BPDCR_COUNT_WIDTH (32U) 1338 #define SW_PORT1_BPDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCR_COUNT_SHIFT)) & SW_PORT1_BPDCR_COUNT_MASK) 1339 /*! @} */ 1340 1341 /*! @name BPDCRR0 - Bridge port discard count reason register 0 */ 1342 /*! @{ */ 1343 1344 #define SW_PORT1_BPDCRR0_BPACDR_MASK (0x1U) 1345 #define SW_PORT1_BPDCRR0_BPACDR_SHIFT (0U) 1346 #define SW_PORT1_BPDCRR0_BPACDR_WIDTH (1U) 1347 #define SW_PORT1_BPDCRR0_BPACDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_BPACDR_SHIFT)) & SW_PORT1_BPDCRR0_BPACDR_MASK) 1348 1349 #define SW_PORT1_BPDCRR0_ISTGSDR_MASK (0x2U) 1350 #define SW_PORT1_BPDCRR0_ISTGSDR_SHIFT (1U) 1351 #define SW_PORT1_BPDCRR0_ISTGSDR_WIDTH (1U) 1352 #define SW_PORT1_BPDCRR0_ISTGSDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_ISTGSDR_SHIFT)) & SW_PORT1_BPDCRR0_ISTGSDR_MASK) 1353 1354 #define SW_PORT1_BPDCRR0_BPVFLTDR_MASK (0x4U) 1355 #define SW_PORT1_BPDCRR0_BPVFLTDR_SHIFT (2U) 1356 #define SW_PORT1_BPDCRR0_BPVFLTDR_WIDTH (1U) 1357 #define SW_PORT1_BPDCRR0_BPVFLTDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_BPVFLTDR_SHIFT)) & SW_PORT1_BPDCRR0_BPVFLTDR_MASK) 1358 1359 #define SW_PORT1_BPDCRR0_MACLNFDR_MASK (0x8U) 1360 #define SW_PORT1_BPDCRR0_MACLNFDR_SHIFT (3U) 1361 #define SW_PORT1_BPDCRR0_MACLNFDR_WIDTH (1U) 1362 #define SW_PORT1_BPDCRR0_MACLNFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_MACLNFDR_SHIFT)) & SW_PORT1_BPDCRR0_MACLNFDR_MASK) 1363 1364 #define SW_PORT1_BPDCRR0_STAMVDDR_MASK (0x80U) 1365 #define SW_PORT1_BPDCRR0_STAMVDDR_SHIFT (7U) 1366 #define SW_PORT1_BPDCRR0_STAMVDDR_WIDTH (1U) 1367 #define SW_PORT1_BPDCRR0_STAMVDDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_STAMVDDR_SHIFT)) & SW_PORT1_BPDCRR0_STAMVDDR_MASK) 1368 1369 #define SW_PORT1_BPDCRR0_MACFDDDR_MASK (0x100U) 1370 #define SW_PORT1_BPDCRR0_MACFDDDR_SHIFT (8U) 1371 #define SW_PORT1_BPDCRR0_MACFDDDR_WIDTH (1U) 1372 #define SW_PORT1_BPDCRR0_MACFDDDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_MACFDDDR_SHIFT)) & SW_PORT1_BPDCRR0_MACFDDDR_MASK) 1373 1374 #define SW_PORT1_BPDCRR0_NODESTDR_MASK (0x200U) 1375 #define SW_PORT1_BPDCRR0_NODESTDR_SHIFT (9U) 1376 #define SW_PORT1_BPDCRR0_NODESTDR_WIDTH (1U) 1377 #define SW_PORT1_BPDCRR0_NODESTDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_NODESTDR_SHIFT)) & SW_PORT1_BPDCRR0_NODESTDR_MASK) 1378 1379 #define SW_PORT1_BPDCRR0_IPMFDR_MASK (0x400U) 1380 #define SW_PORT1_BPDCRR0_IPMFDR_SHIFT (10U) 1381 #define SW_PORT1_BPDCRR0_IPMFDR_WIDTH (1U) 1382 #define SW_PORT1_BPDCRR0_IPMFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_IPMFDR_SHIFT)) & SW_PORT1_BPDCRR0_IPMFDR_MASK) 1383 1384 #define SW_PORT1_BPDCRR0_UFMMDR_MASK (0x800U) 1385 #define SW_PORT1_BPDCRR0_UFMMDR_SHIFT (11U) 1386 #define SW_PORT1_BPDCRR0_UFMMDR_WIDTH (1U) 1387 #define SW_PORT1_BPDCRR0_UFMMDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_UFMMDR_SHIFT)) & SW_PORT1_BPDCRR0_UFMMDR_MASK) 1388 1389 #define SW_PORT1_BPDCRR0_MISCDR_MASK (0x1000U) 1390 #define SW_PORT1_BPDCRR0_MISCDR_SHIFT (12U) 1391 #define SW_PORT1_BPDCRR0_MISCDR_WIDTH (1U) 1392 #define SW_PORT1_BPDCRR0_MISCDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_MISCDR_SHIFT)) & SW_PORT1_BPDCRR0_MISCDR_MASK) 1393 1394 #define SW_PORT1_BPDCRR0_STRMCTRLDR_MASK (0x2000U) 1395 #define SW_PORT1_BPDCRR0_STRMCTRLDR_SHIFT (13U) 1396 #define SW_PORT1_BPDCRR0_STRMCTRLDR_WIDTH (1U) 1397 #define SW_PORT1_BPDCRR0_STRMCTRLDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR0_STRMCTRLDR_SHIFT)) & SW_PORT1_BPDCRR0_STRMCTRLDR_MASK) 1398 /*! @} */ 1399 1400 /*! @name BPDCRR1 - Bridge port discard count reason register 1 */ 1401 /*! @{ */ 1402 1403 #define SW_PORT1_BPDCRR1_ENTRYID_MASK (0x7FFFFFFU) 1404 #define SW_PORT1_BPDCRR1_ENTRYID_SHIFT (0U) 1405 #define SW_PORT1_BPDCRR1_ENTRYID_WIDTH (27U) 1406 #define SW_PORT1_BPDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR1_ENTRYID_SHIFT)) & SW_PORT1_BPDCRR1_ENTRYID_MASK) 1407 1408 #define SW_PORT1_BPDCRR1_TT_MASK (0xF0000000U) 1409 #define SW_PORT1_BPDCRR1_TT_SHIFT (28U) 1410 #define SW_PORT1_BPDCRR1_TT_WIDTH (4U) 1411 #define SW_PORT1_BPDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPDCRR1_TT_SHIFT)) & SW_PORT1_BPDCRR1_TT_MASK) 1412 /*! @} */ 1413 1414 /*! @name BPMLFSR - Bridge port MAC learning failure status register */ 1415 /*! @{ */ 1416 1417 #define SW_PORT1_BPMLFSR_BPMLLRFR_MASK (0x1U) 1418 #define SW_PORT1_BPMLFSR_BPMLLRFR_SHIFT (0U) 1419 #define SW_PORT1_BPMLFSR_BPMLLRFR_WIDTH (1U) 1420 #define SW_PORT1_BPMLFSR_BPMLLRFR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPMLFSR_BPMLLRFR_SHIFT)) & SW_PORT1_BPMLFSR_BPMLLRFR_MASK) 1421 1422 #define SW_PORT1_BPMLFSR_FFDBTRFR_MASK (0x2U) 1423 #define SW_PORT1_BPMLFSR_FFDBTRFR_SHIFT (1U) 1424 #define SW_PORT1_BPMLFSR_FFDBTRFR_WIDTH (1U) 1425 #define SW_PORT1_BPMLFSR_FFDBTRFR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPMLFSR_FFDBTRFR_SHIFT)) & SW_PORT1_BPMLFSR_FFDBTRFR_MASK) 1426 1427 #define SW_PORT1_BPMLFSR_HCCLRFR_MASK (0x4U) 1428 #define SW_PORT1_BPMLFSR_HCCLRFR_SHIFT (2U) 1429 #define SW_PORT1_BPMLFSR_HCCLRFR_WIDTH (1U) 1430 #define SW_PORT1_BPMLFSR_HCCLRFR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT1_BPMLFSR_HCCLRFR_SHIFT)) & SW_PORT1_BPMLFSR_HCCLRFR_MASK) 1431 /*! @} */ 1432 1433 /*! 1434 * @} 1435 */ /* end of group SW_PORT1_Register_Masks */ 1436 1437 /*! 1438 * @} 1439 */ /* end of group SW_PORT1_Peripheral_Access_Layer */ 1440 1441 #endif /* #if !defined(S32Z2_SW_PORT1_H_) */ 1442
