1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SWT.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_SWT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SWT_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SWT_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SWT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SWT_Peripheral_Access_Layer SWT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SWT - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR; /**< Control, offset: 0x0 */ 74 __IO uint32_t IR; /**< Interrupt, offset: 0x4 */ 75 __IO uint32_t TO; /**< Timeout, offset: 0x8 */ 76 __IO uint32_t WN; /**< Window, offset: 0xC */ 77 __O uint32_t SR; /**< Service, offset: 0x10 */ 78 __I uint32_t CO; /**< Counter Output, offset: 0x14 */ 79 __IO uint32_t SK; /**< Service Key, offset: 0x18 */ 80 __IO uint32_t RRR; /**< Event Request, offset: 0x1C */ 81 } SWT_Type, *SWT_MemMapPtr; 82 83 /** Number of instances of the SWT module. */ 84 #define SWT_INSTANCE_COUNT (13) 85 86 /* SWT - Peripheral instance base addresses */ 87 /** Peripheral CE_SWT_0 base address */ 88 #define IP_CE_SWT_0_BASE (0x44824000u) 89 /** Peripheral CE_SWT_0 base pointer */ 90 #define IP_CE_SWT_0 ((SWT_Type *)IP_CE_SWT_0_BASE) 91 /** Peripheral CE_SWT_1 base address */ 92 #define IP_CE_SWT_1_BASE (0x44A24000u) 93 /** Peripheral CE_SWT_1 base pointer */ 94 #define IP_CE_SWT_1 ((SWT_Type *)IP_CE_SWT_1_BASE) 95 /** Peripheral RTU0__SWT_0 base address */ 96 #define IP_RTU0__SWT_0_BASE (0x76000000u) 97 /** Peripheral RTU0__SWT_0 base pointer */ 98 #define IP_RTU0__SWT_0 ((SWT_Type *)IP_RTU0__SWT_0_BASE) 99 /** Peripheral RTU0__SWT_1 base address */ 100 #define IP_RTU0__SWT_1_BASE (0x76010000u) 101 /** Peripheral RTU0__SWT_1 base pointer */ 102 #define IP_RTU0__SWT_1 ((SWT_Type *)IP_RTU0__SWT_1_BASE) 103 /** Peripheral RTU0__SWT_2 base address */ 104 #define IP_RTU0__SWT_2_BASE (0x76220000u) 105 /** Peripheral RTU0__SWT_2 base pointer */ 106 #define IP_RTU0__SWT_2 ((SWT_Type *)IP_RTU0__SWT_2_BASE) 107 /** Peripheral RTU0__SWT_3 base address */ 108 #define IP_RTU0__SWT_3_BASE (0x76230000u) 109 /** Peripheral RTU0__SWT_3 base pointer */ 110 #define IP_RTU0__SWT_3 ((SWT_Type *)IP_RTU0__SWT_3_BASE) 111 /** Peripheral RTU0__SWT_4 base address */ 112 #define IP_RTU0__SWT_4_BASE (0x76140000u) 113 /** Peripheral RTU0__SWT_4 base pointer */ 114 #define IP_RTU0__SWT_4 ((SWT_Type *)IP_RTU0__SWT_4_BASE) 115 /** Peripheral RTU1__SWT_0 base address */ 116 #define IP_RTU1__SWT_0_BASE (0x76800000u) 117 /** Peripheral RTU1__SWT_0 base pointer */ 118 #define IP_RTU1__SWT_0 ((SWT_Type *)IP_RTU1__SWT_0_BASE) 119 /** Peripheral RTU1__SWT_1 base address */ 120 #define IP_RTU1__SWT_1_BASE (0x76810000u) 121 /** Peripheral RTU1__SWT_1 base pointer */ 122 #define IP_RTU1__SWT_1 ((SWT_Type *)IP_RTU1__SWT_1_BASE) 123 /** Peripheral RTU1__SWT_2 base address */ 124 #define IP_RTU1__SWT_2_BASE (0x76A20000u) 125 /** Peripheral RTU1__SWT_2 base pointer */ 126 #define IP_RTU1__SWT_2 ((SWT_Type *)IP_RTU1__SWT_2_BASE) 127 /** Peripheral RTU1__SWT_3 base address */ 128 #define IP_RTU1__SWT_3_BASE (0x76A30000u) 129 /** Peripheral RTU1__SWT_3 base pointer */ 130 #define IP_RTU1__SWT_3 ((SWT_Type *)IP_RTU1__SWT_3_BASE) 131 /** Peripheral RTU1__SWT_4 base address */ 132 #define IP_RTU1__SWT_4_BASE (0x76940000u) 133 /** Peripheral RTU1__SWT_4 base pointer */ 134 #define IP_RTU1__SWT_4 ((SWT_Type *)IP_RTU1__SWT_4_BASE) 135 /** Peripheral SMU__SWT base address */ 136 #define IP_SMU__SWT_BASE (0x45024000u) 137 /** Peripheral SMU__SWT base pointer */ 138 #define IP_SMU__SWT ((SWT_Type *)IP_SMU__SWT_BASE) 139 /** Array initializer of SWT peripheral base addresses */ 140 #define IP_SWT_BASE_ADDRS { IP_CE_SWT_0_BASE, IP_CE_SWT_1_BASE, IP_RTU0__SWT_0_BASE, IP_RTU0__SWT_1_BASE, IP_RTU0__SWT_2_BASE, IP_RTU0__SWT_3_BASE, IP_RTU0__SWT_4_BASE, IP_RTU1__SWT_0_BASE, IP_RTU1__SWT_1_BASE, IP_RTU1__SWT_2_BASE, IP_RTU1__SWT_3_BASE, IP_RTU1__SWT_4_BASE, IP_SMU__SWT_BASE } 141 /** Array initializer of SWT peripheral base pointers */ 142 #define IP_SWT_BASE_PTRS { IP_CE_SWT_0, IP_CE_SWT_1, IP_RTU0__SWT_0, IP_RTU0__SWT_1, IP_RTU0__SWT_2, IP_RTU0__SWT_3, IP_RTU0__SWT_4, IP_RTU1__SWT_0, IP_RTU1__SWT_1, IP_RTU1__SWT_2, IP_RTU1__SWT_3, IP_RTU1__SWT_4, IP_SMU__SWT } 143 144 /* ---------------------------------------------------------------------------- 145 -- SWT Register Masks 146 ---------------------------------------------------------------------------- */ 147 148 /*! 149 * @addtogroup SWT_Register_Masks SWT Register Masks 150 * @{ 151 */ 152 153 /*! @name CR - Control */ 154 /*! @{ */ 155 156 #define SWT_CR_WEN_MASK (0x1U) 157 #define SWT_CR_WEN_SHIFT (0U) 158 #define SWT_CR_WEN_WIDTH (1U) 159 #define SWT_CR_WEN(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_WEN_SHIFT)) & SWT_CR_WEN_MASK) 160 161 #define SWT_CR_FRZ_MASK (0x2U) 162 #define SWT_CR_FRZ_SHIFT (1U) 163 #define SWT_CR_FRZ_WIDTH (1U) 164 #define SWT_CR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_FRZ_SHIFT)) & SWT_CR_FRZ_MASK) 165 166 #define SWT_CR_STP_MASK (0x4U) 167 #define SWT_CR_STP_SHIFT (2U) 168 #define SWT_CR_STP_WIDTH (1U) 169 #define SWT_CR_STP(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_STP_SHIFT)) & SWT_CR_STP_MASK) 170 171 #define SWT_CR_SLK_MASK (0x10U) 172 #define SWT_CR_SLK_SHIFT (4U) 173 #define SWT_CR_SLK_WIDTH (1U) 174 #define SWT_CR_SLK(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_SLK_SHIFT)) & SWT_CR_SLK_MASK) 175 176 #define SWT_CR_HLK_MASK (0x20U) 177 #define SWT_CR_HLK_SHIFT (5U) 178 #define SWT_CR_HLK_WIDTH (1U) 179 #define SWT_CR_HLK(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_HLK_SHIFT)) & SWT_CR_HLK_MASK) 180 181 #define SWT_CR_ITR_MASK (0x40U) 182 #define SWT_CR_ITR_SHIFT (6U) 183 #define SWT_CR_ITR_WIDTH (1U) 184 #define SWT_CR_ITR(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_ITR_SHIFT)) & SWT_CR_ITR_MASK) 185 186 #define SWT_CR_WND_MASK (0x80U) 187 #define SWT_CR_WND_SHIFT (7U) 188 #define SWT_CR_WND_WIDTH (1U) 189 #define SWT_CR_WND(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_WND_SHIFT)) & SWT_CR_WND_MASK) 190 191 #define SWT_CR_RIA_MASK (0x100U) 192 #define SWT_CR_RIA_SHIFT (8U) 193 #define SWT_CR_RIA_WIDTH (1U) 194 #define SWT_CR_RIA(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_RIA_SHIFT)) & SWT_CR_RIA_MASK) 195 196 #define SWT_CR_SMD_MASK (0x600U) 197 #define SWT_CR_SMD_SHIFT (9U) 198 #define SWT_CR_SMD_WIDTH (2U) 199 #define SWT_CR_SMD(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_SMD_SHIFT)) & SWT_CR_SMD_MASK) 200 201 #define SWT_CR_MAP7_MASK (0x1000000U) 202 #define SWT_CR_MAP7_SHIFT (24U) 203 #define SWT_CR_MAP7_WIDTH (1U) 204 #define SWT_CR_MAP7(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP7_SHIFT)) & SWT_CR_MAP7_MASK) 205 206 #define SWT_CR_MAP6_MASK (0x2000000U) 207 #define SWT_CR_MAP6_SHIFT (25U) 208 #define SWT_CR_MAP6_WIDTH (1U) 209 #define SWT_CR_MAP6(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP6_SHIFT)) & SWT_CR_MAP6_MASK) 210 211 #define SWT_CR_MAP5_MASK (0x4000000U) 212 #define SWT_CR_MAP5_SHIFT (26U) 213 #define SWT_CR_MAP5_WIDTH (1U) 214 #define SWT_CR_MAP5(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP5_SHIFT)) & SWT_CR_MAP5_MASK) 215 216 #define SWT_CR_MAP4_MASK (0x8000000U) 217 #define SWT_CR_MAP4_SHIFT (27U) 218 #define SWT_CR_MAP4_WIDTH (1U) 219 #define SWT_CR_MAP4(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP4_SHIFT)) & SWT_CR_MAP4_MASK) 220 221 #define SWT_CR_MAP3_MASK (0x10000000U) 222 #define SWT_CR_MAP3_SHIFT (28U) 223 #define SWT_CR_MAP3_WIDTH (1U) 224 #define SWT_CR_MAP3(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP3_SHIFT)) & SWT_CR_MAP3_MASK) 225 226 #define SWT_CR_MAP2_MASK (0x20000000U) 227 #define SWT_CR_MAP2_SHIFT (29U) 228 #define SWT_CR_MAP2_WIDTH (1U) 229 #define SWT_CR_MAP2(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP2_SHIFT)) & SWT_CR_MAP2_MASK) 230 231 #define SWT_CR_MAP1_MASK (0x40000000U) 232 #define SWT_CR_MAP1_SHIFT (30U) 233 #define SWT_CR_MAP1_WIDTH (1U) 234 #define SWT_CR_MAP1(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP1_SHIFT)) & SWT_CR_MAP1_MASK) 235 236 #define SWT_CR_MAP0_MASK (0x80000000U) 237 #define SWT_CR_MAP0_SHIFT (31U) 238 #define SWT_CR_MAP0_WIDTH (1U) 239 #define SWT_CR_MAP0(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP0_SHIFT)) & SWT_CR_MAP0_MASK) 240 /*! @} */ 241 242 /*! @name IR - Interrupt */ 243 /*! @{ */ 244 245 #define SWT_IR_TIF_MASK (0x1U) 246 #define SWT_IR_TIF_SHIFT (0U) 247 #define SWT_IR_TIF_WIDTH (1U) 248 #define SWT_IR_TIF(x) (((uint32_t)(((uint32_t)(x)) << SWT_IR_TIF_SHIFT)) & SWT_IR_TIF_MASK) 249 /*! @} */ 250 251 /*! @name TO - Timeout */ 252 /*! @{ */ 253 254 #define SWT_TO_WTO_MASK (0xFFFFFFFFU) 255 #define SWT_TO_WTO_SHIFT (0U) 256 #define SWT_TO_WTO_WIDTH (32U) 257 #define SWT_TO_WTO(x) (((uint32_t)(((uint32_t)(x)) << SWT_TO_WTO_SHIFT)) & SWT_TO_WTO_MASK) 258 /*! @} */ 259 260 /*! @name WN - Window */ 261 /*! @{ */ 262 263 #define SWT_WN_WST_MASK (0xFFFFFFFFU) 264 #define SWT_WN_WST_SHIFT (0U) 265 #define SWT_WN_WST_WIDTH (32U) 266 #define SWT_WN_WST(x) (((uint32_t)(((uint32_t)(x)) << SWT_WN_WST_SHIFT)) & SWT_WN_WST_MASK) 267 /*! @} */ 268 269 /*! @name SR - Service */ 270 /*! @{ */ 271 272 #define SWT_SR_WSC_MASK (0xFFFFU) 273 #define SWT_SR_WSC_SHIFT (0U) 274 #define SWT_SR_WSC_WIDTH (16U) 275 #define SWT_SR_WSC(x) (((uint32_t)(((uint32_t)(x)) << SWT_SR_WSC_SHIFT)) & SWT_SR_WSC_MASK) 276 /*! @} */ 277 278 /*! @name CO - Counter Output */ 279 /*! @{ */ 280 281 #define SWT_CO_CNT_MASK (0xFFFFFFFFU) 282 #define SWT_CO_CNT_SHIFT (0U) 283 #define SWT_CO_CNT_WIDTH (32U) 284 #define SWT_CO_CNT(x) (((uint32_t)(((uint32_t)(x)) << SWT_CO_CNT_SHIFT)) & SWT_CO_CNT_MASK) 285 /*! @} */ 286 287 /*! @name SK - Service Key */ 288 /*! @{ */ 289 290 #define SWT_SK_SK_MASK (0xFFFFU) 291 #define SWT_SK_SK_SHIFT (0U) 292 #define SWT_SK_SK_WIDTH (16U) 293 #define SWT_SK_SK(x) (((uint32_t)(((uint32_t)(x)) << SWT_SK_SK_SHIFT)) & SWT_SK_SK_MASK) 294 /*! @} */ 295 296 /*! @name RRR - Event Request */ 297 /*! @{ */ 298 299 #define SWT_RRR_RRF_MASK (0x1U) 300 #define SWT_RRR_RRF_SHIFT (0U) 301 #define SWT_RRR_RRF_WIDTH (1U) 302 #define SWT_RRR_RRF(x) (((uint32_t)(((uint32_t)(x)) << SWT_RRR_RRF_SHIFT)) & SWT_RRR_RRF_MASK) 303 /*! @} */ 304 305 /*! 306 * @} 307 */ /* end of group SWT_Register_Masks */ 308 309 /*! 310 * @} 311 */ /* end of group SWT_Peripheral_Access_Layer */ 312 313 #endif /* #if !defined(S32Z2_SWT_H_) */ 314
