1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MC_ME.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_MC_ME 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MC_ME_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MC_ME_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MC_ME Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MC_ME_Peripheral_Access_Layer MC_ME Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MC_ME - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CTL_KEY; /**< Control Key Register, offset: 0x0 */ 74 __IO uint32_t MODE_CONF; /**< Mode Configuration Register, offset: 0x4 */ 75 __IO uint32_t MODE_UPD; /**< Mode Update Register, offset: 0x8 */ 76 uint8_t RESERVED_0[244]; 77 __IO uint32_t PRTN0_PCONF; /**< Partition 0 Process Configuration Register, offset: 0x100 */ 78 __IO uint32_t PRTN0_PUPD; /**< Partition 0 Process Update Register, offset: 0x104 */ 79 __I uint32_t PRTN0_STAT; /**< Partition 0 Status Register, offset: 0x108 */ 80 uint8_t RESERVED_1[52]; 81 __IO uint32_t PRTN0_CORE0_PCONF; /**< Partition 0 Core 0 Process Configuration Register, offset: 0x140 */ 82 __IO uint32_t PRTN0_CORE0_PUPD; /**< Partition 0 Core 0 Process Update Register, offset: 0x144 */ 83 __I uint32_t PRTN0_CORE0_STAT; /**< Partition 0 Core 0 Status Register, offset: 0x148 */ 84 __IO uint32_t PRTN0_CORE0_ADDR; /**< Partition 0 Core 0 Address Register, offset: 0x14C */ 85 uint8_t RESERVED_2[16]; 86 __IO uint32_t PRTN0_CORE1_PCONF; /**< Partition 0 Core 1 Process Configuration Register, offset: 0x160 */ 87 __IO uint32_t PRTN0_CORE1_PUPD; /**< Partition 0 Core 1 Process Update Register, offset: 0x164 */ 88 __I uint32_t PRTN0_CORE1_STAT; /**< Partition 0 Core 1 Status Register, offset: 0x168 */ 89 __IO uint32_t PRTN0_CORE1_ADDR; /**< Partition 0 Core 1 Address Register, offset: 0x16C */ 90 uint8_t RESERVED_3[16]; 91 __IO uint32_t PRTN0_CORE2_PCONF; /**< Partition 0 Core 2 Process Configuration Register, offset: 0x180 */ 92 __IO uint32_t PRTN0_CORE2_PUPD; /**< Partition 0 Core 2 Process Update Register, offset: 0x184 */ 93 __I uint32_t PRTN0_CORE2_STAT; /**< Partition 0 Core 2 Status Register, offset: 0x188 */ 94 __IO uint32_t PRTN0_CORE2_ADDR; /**< Partition 0 Core 2 Address Register, offset: 0x18C */ 95 uint8_t RESERVED_4[16]; 96 __IO uint32_t PRTN0_CORE3_PCONF; /**< Partition 0 Core 3 Process Configuration Register, offset: 0x1A0 */ 97 __IO uint32_t PRTN0_CORE3_PUPD; /**< Partition 0 Core 3 Process Update Register, offset: 0x1A4 */ 98 __I uint32_t PRTN0_CORE3_STAT; /**< Partition 0 Core 3 Status Register, offset: 0x1A8 */ 99 __IO uint32_t PRTN0_CORE3_ADDR; /**< Partition 0 Core 3 Address Register, offset: 0x1AC */ 100 uint8_t RESERVED_5[16]; 101 __IO uint32_t PRTN0_CORE4_PCONF; /**< Partition 0 Core 4 Process Configuration Register, offset: 0x1C0 */ 102 __IO uint32_t PRTN0_CORE4_PUPD; /**< Partition 0 Core 4 Process Update Register, offset: 0x1C4 */ 103 __I uint32_t PRTN0_CORE4_STAT; /**< Partition 0 Core 4 Status Register, offset: 0x1C8 */ 104 __IO uint32_t PRTN0_CORE4_ADDR; /**< Partition 0 Core 4 Address Register, offset: 0x1CC */ 105 uint8_t RESERVED_6[16]; 106 __IO uint32_t PRTN0_CORE5_PCONF; /**< Partition 0 Core 5 Process Configuration Register, offset: 0x1E0 */ 107 __IO uint32_t PRTN0_CORE5_PUPD; /**< Partition 0 Core 5 Process Update Register, offset: 0x1E4 */ 108 __I uint32_t PRTN0_CORE5_STAT; /**< Partition 0 Core 5 Status Register, offset: 0x1E8 */ 109 __IO uint32_t PRTN0_CORE5_ADDR; /**< Partition 0 Core 5 Address Register, offset: 0x1EC */ 110 uint8_t RESERVED_7[16]; 111 __IO uint32_t PRTN0_CORE6_PCONF; /**< Partition 0 Core 6 Process Configuration Register, offset: 0x200 */ 112 __IO uint32_t PRTN0_CORE6_PUPD; /**< Partition 0 Core 6 Process Update Register, offset: 0x204 */ 113 __I uint32_t PRTN0_CORE6_STAT; /**< Partition 0 Core 6 Status Register, offset: 0x208 */ 114 __IO uint32_t PRTN0_CORE6_ADDR; /**< Partition 0 Core 6 Address Register, offset: 0x20C */ 115 uint8_t RESERVED_8[16]; 116 __IO uint32_t PRTN0_CORE7_PCONF; /**< Partition 0 Core 7 Process Configuration Register, offset: 0x220 */ 117 __IO uint32_t PRTN0_CORE7_PUPD; /**< Partition 0 Core 7 Process Update Register, offset: 0x224 */ 118 __I uint32_t PRTN0_CORE7_STAT; /**< Partition 0 Core 7 Status Register, offset: 0x228 */ 119 __IO uint32_t PRTN0_CORE7_ADDR; /**< Partition 0 Core 7 Address Register, offset: 0x22C */ 120 uint8_t RESERVED_9[208]; 121 __IO uint32_t PRTN1_PCONF; /**< Partition 1 Process Configuration Register, offset: 0x300 */ 122 __IO uint32_t PRTN1_PUPD; /**< Partition 1 Process Update Register, offset: 0x304 */ 123 __I uint32_t PRTN1_STAT; /**< Partition 1 Status Register, offset: 0x308 */ 124 uint8_t RESERVED_10[52]; 125 __IO uint32_t PRTN1_CORE0_PCONF; /**< Partition 1 Core 0 Process Configuration Register, offset: 0x340 */ 126 __IO uint32_t PRTN1_CORE0_PUPD; /**< Partition 1 Core 0 Process Update Register, offset: 0x344 */ 127 __I uint32_t PRTN1_CORE0_STAT; /**< Partition 1 Core 0 Status Register, offset: 0x348 */ 128 __IO uint32_t PRTN1_CORE0_ADDR; /**< Partition 1 Core 0 Address Register, offset: 0x34C */ 129 uint8_t RESERVED_11[16]; 130 __IO uint32_t PRTN1_CORE1_PCONF; /**< Partition 1 Core 1 Process Configuration Register, offset: 0x360 */ 131 __IO uint32_t PRTN1_CORE1_PUPD; /**< Partition 1 Core 1 Process Update Register, offset: 0x364 */ 132 __I uint32_t PRTN1_CORE1_STAT; /**< Partition 1 Core 1 Status Register, offset: 0x368 */ 133 __IO uint32_t PRTN1_CORE1_ADDR; /**< Partition 1 Core 1 Address Register, offset: 0x36C */ 134 uint8_t RESERVED_12[16]; 135 __IO uint32_t PRTN1_CORE2_PCONF; /**< Partition 1 Core 2 Process Configuration Register, offset: 0x380 */ 136 __IO uint32_t PRTN1_CORE2_PUPD; /**< Partition 1 Core 2 Process Update Register, offset: 0x384 */ 137 __I uint32_t PRTN1_CORE2_STAT; /**< Partition 1 Core 2 Status Register, offset: 0x388 */ 138 __IO uint32_t PRTN1_CORE2_ADDR; /**< Partition 1 Core 2 Address Register, offset: 0x38C */ 139 uint8_t RESERVED_13[16]; 140 __IO uint32_t PRTN1_CORE3_PCONF; /**< Partition 1 Core 3 Process Configuration Register, offset: 0x3A0 */ 141 __IO uint32_t PRTN1_CORE3_PUPD; /**< Partition 1 Core 3 Process Update Register, offset: 0x3A4 */ 142 __I uint32_t PRTN1_CORE3_STAT; /**< Partition 1 Core 3 Status Register, offset: 0x3A8 */ 143 __IO uint32_t PRTN1_CORE3_ADDR; /**< Partition 1 Core 3 Address Register, offset: 0x3AC */ 144 uint8_t RESERVED_14[336]; 145 __IO uint32_t PRTN2_PCONF; /**< Partition 2 Process Configuration Register, offset: 0x500 */ 146 __IO uint32_t PRTN2_PUPD; /**< Partition 2 Process Update Register, offset: 0x504 */ 147 __I uint32_t PRTN2_STAT; /**< Partition 2 Status Register, offset: 0x508 */ 148 uint8_t RESERVED_15[52]; 149 __IO uint32_t PRTN2_CORE0_PCONF; /**< Partition 2 Core 0 Process Configuration Register, offset: 0x540 */ 150 __IO uint32_t PRTN2_CORE0_PUPD; /**< Partition 2 Core 0 Process Update Register, offset: 0x544 */ 151 __I uint32_t PRTN2_CORE0_STAT; /**< Partition 2 Core 0 Status Register, offset: 0x548 */ 152 __IO uint32_t PRTN2_CORE0_ADDR; /**< Partition 2 Core 0 Address Register, offset: 0x54C */ 153 uint8_t RESERVED_16[16]; 154 __IO uint32_t PRTN2_CORE1_PCONF; /**< Partition 2 Core 1 Process Configuration Register, offset: 0x560 */ 155 __IO uint32_t PRTN2_CORE1_PUPD; /**< Partition 2 Core 1 Process Update Register, offset: 0x564 */ 156 __I uint32_t PRTN2_CORE1_STAT; /**< Partition 2 Core 1 Status Register, offset: 0x568 */ 157 __IO uint32_t PRTN2_CORE1_ADDR; /**< Partition 2 Core 1 Address Register, offset: 0x56C */ 158 uint8_t RESERVED_17[16]; 159 __IO uint32_t PRTN2_CORE2_PCONF; /**< Partition 2 Core 2 Process Configuration Register, offset: 0x580 */ 160 __IO uint32_t PRTN2_CORE2_PUPD; /**< Partition 2 Core 2 Process Update Register, offset: 0x584 */ 161 __I uint32_t PRTN2_CORE2_STAT; /**< Partition 2 Core 2 Status Register, offset: 0x588 */ 162 __IO uint32_t PRTN2_CORE2_ADDR; /**< Partition 2 Core 2 Address Register, offset: 0x58C */ 163 uint8_t RESERVED_18[16]; 164 __IO uint32_t PRTN2_CORE3_PCONF; /**< Partition 2 Core 3 Process Configuration Register, offset: 0x5A0 */ 165 __IO uint32_t PRTN2_CORE3_PUPD; /**< Partition 2 Core 3 Process Update Register, offset: 0x5A4 */ 166 __I uint32_t PRTN2_CORE3_STAT; /**< Partition 2 Core 3 Status Register, offset: 0x5A8 */ 167 __IO uint32_t PRTN2_CORE3_ADDR; /**< Partition 2 Core 3 Address Register, offset: 0x5AC */ 168 } MC_ME_Type, *MC_ME_MemMapPtr; 169 170 /** Number of instances of the MC_ME module. */ 171 #define MC_ME_INSTANCE_COUNT (1u) 172 173 /* MC_ME - Peripheral instance base addresses */ 174 /** Peripheral MC_ME base address */ 175 #define IP_MC_ME_BASE (0x41900000u) 176 /** Peripheral MC_ME base pointer */ 177 #define IP_MC_ME ((MC_ME_Type *)IP_MC_ME_BASE) 178 /** Array initializer of MC_ME peripheral base addresses */ 179 #define IP_MC_ME_BASE_ADDRS { IP_MC_ME_BASE } 180 /** Array initializer of MC_ME peripheral base pointers */ 181 #define IP_MC_ME_BASE_PTRS { IP_MC_ME } 182 183 /* ---------------------------------------------------------------------------- 184 -- MC_ME Register Masks 185 ---------------------------------------------------------------------------- */ 186 187 /*! 188 * @addtogroup MC_ME_Register_Masks MC_ME Register Masks 189 * @{ 190 */ 191 192 /*! @name CTL_KEY - Control Key Register */ 193 /*! @{ */ 194 195 #define MC_ME_CTL_KEY_KEY_MASK (0xFFFFU) 196 #define MC_ME_CTL_KEY_KEY_SHIFT (0U) 197 #define MC_ME_CTL_KEY_KEY_WIDTH (16U) 198 #define MC_ME_CTL_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_CTL_KEY_KEY_SHIFT)) & MC_ME_CTL_KEY_KEY_MASK) 199 /*! @} */ 200 201 /*! @name MODE_CONF - Mode Configuration Register */ 202 /*! @{ */ 203 204 #define MC_ME_MODE_CONF_DEST_RST_MASK (0x1U) 205 #define MC_ME_MODE_CONF_DEST_RST_SHIFT (0U) 206 #define MC_ME_MODE_CONF_DEST_RST_WIDTH (1U) 207 #define MC_ME_MODE_CONF_DEST_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_CONF_DEST_RST_SHIFT)) & MC_ME_MODE_CONF_DEST_RST_MASK) 208 209 #define MC_ME_MODE_CONF_FUNC_RST_MASK (0x2U) 210 #define MC_ME_MODE_CONF_FUNC_RST_SHIFT (1U) 211 #define MC_ME_MODE_CONF_FUNC_RST_WIDTH (1U) 212 #define MC_ME_MODE_CONF_FUNC_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_CONF_FUNC_RST_SHIFT)) & MC_ME_MODE_CONF_FUNC_RST_MASK) 213 /*! @} */ 214 215 /*! @name MODE_UPD - Mode Update Register */ 216 /*! @{ */ 217 218 #define MC_ME_MODE_UPD_MODE_UPD_MASK (0x1U) 219 #define MC_ME_MODE_UPD_MODE_UPD_SHIFT (0U) 220 #define MC_ME_MODE_UPD_MODE_UPD_WIDTH (1U) 221 #define MC_ME_MODE_UPD_MODE_UPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_UPD_MODE_UPD_SHIFT)) & MC_ME_MODE_UPD_MODE_UPD_MASK) 222 /*! @} */ 223 224 /*! @name PRTN0_PCONF - Partition 0 Process Configuration Register */ 225 /*! @{ */ 226 227 #define MC_ME_PRTN0_PCONF_PCE_MASK (0x1U) 228 #define MC_ME_PRTN0_PCONF_PCE_SHIFT (0U) 229 #define MC_ME_PRTN0_PCONF_PCE_WIDTH (1U) 230 #define MC_ME_PRTN0_PCONF_PCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_PCONF_PCE_SHIFT)) & MC_ME_PRTN0_PCONF_PCE_MASK) 231 /*! @} */ 232 233 /*! @name PRTN0_PUPD - Partition 0 Process Update Register */ 234 /*! @{ */ 235 236 #define MC_ME_PRTN0_PUPD_PCUD_MASK (0x1U) 237 #define MC_ME_PRTN0_PUPD_PCUD_SHIFT (0U) 238 #define MC_ME_PRTN0_PUPD_PCUD_WIDTH (1U) 239 #define MC_ME_PRTN0_PUPD_PCUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_PUPD_PCUD_SHIFT)) & MC_ME_PRTN0_PUPD_PCUD_MASK) 240 /*! @} */ 241 242 /*! @name PRTN0_STAT - Partition 0 Status Register */ 243 /*! @{ */ 244 245 #define MC_ME_PRTN0_STAT_PCS_MASK (0x1U) 246 #define MC_ME_PRTN0_STAT_PCS_SHIFT (0U) 247 #define MC_ME_PRTN0_STAT_PCS_WIDTH (1U) 248 #define MC_ME_PRTN0_STAT_PCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_STAT_PCS_SHIFT)) & MC_ME_PRTN0_STAT_PCS_MASK) 249 /*! @} */ 250 251 /*! @name PRTN0_CORE0_PCONF - Partition 0 Core 0 Process Configuration Register */ 252 /*! @{ */ 253 254 #define MC_ME_PRTN0_CORE0_PCONF_CCE_MASK (0x1U) 255 #define MC_ME_PRTN0_CORE0_PCONF_CCE_SHIFT (0U) 256 #define MC_ME_PRTN0_CORE0_PCONF_CCE_WIDTH (1U) 257 #define MC_ME_PRTN0_CORE0_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE0_PCONF_CCE_MASK) 258 /*! @} */ 259 260 /*! @name PRTN0_CORE0_PUPD - Partition 0 Core 0 Process Update Register */ 261 /*! @{ */ 262 263 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD_MASK (0x1U) 264 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD_SHIFT (0U) 265 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD_WIDTH (1U) 266 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE0_PUPD_CCUPD_MASK) 267 /*! @} */ 268 269 /*! @name PRTN0_CORE0_STAT - Partition 0 Core 0 Status Register */ 270 /*! @{ */ 271 272 #define MC_ME_PRTN0_CORE0_STAT_CCS_MASK (0x1U) 273 #define MC_ME_PRTN0_CORE0_STAT_CCS_SHIFT (0U) 274 #define MC_ME_PRTN0_CORE0_STAT_CCS_WIDTH (1U) 275 #define MC_ME_PRTN0_CORE0_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE0_STAT_CCS_MASK) 276 277 #define MC_ME_PRTN0_CORE0_STAT_WFI_MASK (0x80000000U) 278 #define MC_ME_PRTN0_CORE0_STAT_WFI_SHIFT (31U) 279 #define MC_ME_PRTN0_CORE0_STAT_WFI_WIDTH (1U) 280 #define MC_ME_PRTN0_CORE0_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE0_STAT_WFI_MASK) 281 /*! @} */ 282 283 /*! @name PRTN0_CORE0_ADDR - Partition 0 Core 0 Address Register */ 284 /*! @{ */ 285 286 #define MC_ME_PRTN0_CORE0_ADDR_ADDR_MASK (0xFFFFFFFCU) 287 #define MC_ME_PRTN0_CORE0_ADDR_ADDR_SHIFT (2U) 288 #define MC_ME_PRTN0_CORE0_ADDR_ADDR_WIDTH (30U) 289 #define MC_ME_PRTN0_CORE0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE0_ADDR_ADDR_MASK) 290 /*! @} */ 291 292 /*! @name PRTN0_CORE1_PCONF - Partition 0 Core 1 Process Configuration Register */ 293 /*! @{ */ 294 295 #define MC_ME_PRTN0_CORE1_PCONF_CCE_MASK (0x1U) 296 #define MC_ME_PRTN0_CORE1_PCONF_CCE_SHIFT (0U) 297 #define MC_ME_PRTN0_CORE1_PCONF_CCE_WIDTH (1U) 298 #define MC_ME_PRTN0_CORE1_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE1_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE1_PCONF_CCE_MASK) 299 /*! @} */ 300 301 /*! @name PRTN0_CORE1_PUPD - Partition 0 Core 1 Process Update Register */ 302 /*! @{ */ 303 304 #define MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK (0x1U) 305 #define MC_ME_PRTN0_CORE1_PUPD_CCUPD_SHIFT (0U) 306 #define MC_ME_PRTN0_CORE1_PUPD_CCUPD_WIDTH (1U) 307 #define MC_ME_PRTN0_CORE1_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE1_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK) 308 /*! @} */ 309 310 /*! @name PRTN0_CORE1_STAT - Partition 0 Core 1 Status Register */ 311 /*! @{ */ 312 313 #define MC_ME_PRTN0_CORE1_STAT_CCS_MASK (0x1U) 314 #define MC_ME_PRTN0_CORE1_STAT_CCS_SHIFT (0U) 315 #define MC_ME_PRTN0_CORE1_STAT_CCS_WIDTH (1U) 316 #define MC_ME_PRTN0_CORE1_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE1_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE1_STAT_CCS_MASK) 317 318 #define MC_ME_PRTN0_CORE1_STAT_WFI_MASK (0x80000000U) 319 #define MC_ME_PRTN0_CORE1_STAT_WFI_SHIFT (31U) 320 #define MC_ME_PRTN0_CORE1_STAT_WFI_WIDTH (1U) 321 #define MC_ME_PRTN0_CORE1_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE1_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE1_STAT_WFI_MASK) 322 /*! @} */ 323 324 /*! @name PRTN0_CORE1_ADDR - Partition 0 Core 1 Address Register */ 325 /*! @{ */ 326 327 #define MC_ME_PRTN0_CORE1_ADDR_ADDR_MASK (0xFFFFFFFCU) 328 #define MC_ME_PRTN0_CORE1_ADDR_ADDR_SHIFT (2U) 329 #define MC_ME_PRTN0_CORE1_ADDR_ADDR_WIDTH (30U) 330 #define MC_ME_PRTN0_CORE1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE1_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE1_ADDR_ADDR_MASK) 331 /*! @} */ 332 333 /*! @name PRTN0_CORE2_PCONF - Partition 0 Core 2 Process Configuration Register */ 334 /*! @{ */ 335 336 #define MC_ME_PRTN0_CORE2_PCONF_CCE_MASK (0x1U) 337 #define MC_ME_PRTN0_CORE2_PCONF_CCE_SHIFT (0U) 338 #define MC_ME_PRTN0_CORE2_PCONF_CCE_WIDTH (1U) 339 #define MC_ME_PRTN0_CORE2_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE2_PCONF_CCE_MASK) 340 /*! @} */ 341 342 /*! @name PRTN0_CORE2_PUPD - Partition 0 Core 2 Process Update Register */ 343 /*! @{ */ 344 345 #define MC_ME_PRTN0_CORE2_PUPD_CCUPD_MASK (0x1U) 346 #define MC_ME_PRTN0_CORE2_PUPD_CCUPD_SHIFT (0U) 347 #define MC_ME_PRTN0_CORE2_PUPD_CCUPD_WIDTH (1U) 348 #define MC_ME_PRTN0_CORE2_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE2_PUPD_CCUPD_MASK) 349 /*! @} */ 350 351 /*! @name PRTN0_CORE2_STAT - Partition 0 Core 2 Status Register */ 352 /*! @{ */ 353 354 #define MC_ME_PRTN0_CORE2_STAT_CCS_MASK (0x1U) 355 #define MC_ME_PRTN0_CORE2_STAT_CCS_SHIFT (0U) 356 #define MC_ME_PRTN0_CORE2_STAT_CCS_WIDTH (1U) 357 #define MC_ME_PRTN0_CORE2_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE2_STAT_CCS_MASK) 358 359 #define MC_ME_PRTN0_CORE2_STAT_WFI_MASK (0x80000000U) 360 #define MC_ME_PRTN0_CORE2_STAT_WFI_SHIFT (31U) 361 #define MC_ME_PRTN0_CORE2_STAT_WFI_WIDTH (1U) 362 #define MC_ME_PRTN0_CORE2_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE2_STAT_WFI_MASK) 363 /*! @} */ 364 365 /*! @name PRTN0_CORE2_ADDR - Partition 0 Core 2 Address Register */ 366 /*! @{ */ 367 368 #define MC_ME_PRTN0_CORE2_ADDR_ADDR_MASK (0xFFFFFFFCU) 369 #define MC_ME_PRTN0_CORE2_ADDR_ADDR_SHIFT (2U) 370 #define MC_ME_PRTN0_CORE2_ADDR_ADDR_WIDTH (30U) 371 #define MC_ME_PRTN0_CORE2_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE2_ADDR_ADDR_MASK) 372 /*! @} */ 373 374 /*! @name PRTN0_CORE3_PCONF - Partition 0 Core 3 Process Configuration Register */ 375 /*! @{ */ 376 377 #define MC_ME_PRTN0_CORE3_PCONF_CCE_MASK (0x1U) 378 #define MC_ME_PRTN0_CORE3_PCONF_CCE_SHIFT (0U) 379 #define MC_ME_PRTN0_CORE3_PCONF_CCE_WIDTH (1U) 380 #define MC_ME_PRTN0_CORE3_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE3_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE3_PCONF_CCE_MASK) 381 /*! @} */ 382 383 /*! @name PRTN0_CORE3_PUPD - Partition 0 Core 3 Process Update Register */ 384 /*! @{ */ 385 386 #define MC_ME_PRTN0_CORE3_PUPD_CCUPD_MASK (0x1U) 387 #define MC_ME_PRTN0_CORE3_PUPD_CCUPD_SHIFT (0U) 388 #define MC_ME_PRTN0_CORE3_PUPD_CCUPD_WIDTH (1U) 389 #define MC_ME_PRTN0_CORE3_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE3_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE3_PUPD_CCUPD_MASK) 390 /*! @} */ 391 392 /*! @name PRTN0_CORE3_STAT - Partition 0 Core 3 Status Register */ 393 /*! @{ */ 394 395 #define MC_ME_PRTN0_CORE3_STAT_CCS_MASK (0x1U) 396 #define MC_ME_PRTN0_CORE3_STAT_CCS_SHIFT (0U) 397 #define MC_ME_PRTN0_CORE3_STAT_CCS_WIDTH (1U) 398 #define MC_ME_PRTN0_CORE3_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE3_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE3_STAT_CCS_MASK) 399 400 #define MC_ME_PRTN0_CORE3_STAT_WFI_MASK (0x80000000U) 401 #define MC_ME_PRTN0_CORE3_STAT_WFI_SHIFT (31U) 402 #define MC_ME_PRTN0_CORE3_STAT_WFI_WIDTH (1U) 403 #define MC_ME_PRTN0_CORE3_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE3_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE3_STAT_WFI_MASK) 404 /*! @} */ 405 406 /*! @name PRTN0_CORE3_ADDR - Partition 0 Core 3 Address Register */ 407 /*! @{ */ 408 409 #define MC_ME_PRTN0_CORE3_ADDR_ADDR_MASK (0xFFFFFFFCU) 410 #define MC_ME_PRTN0_CORE3_ADDR_ADDR_SHIFT (2U) 411 #define MC_ME_PRTN0_CORE3_ADDR_ADDR_WIDTH (30U) 412 #define MC_ME_PRTN0_CORE3_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE3_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE3_ADDR_ADDR_MASK) 413 /*! @} */ 414 415 /*! @name PRTN0_CORE4_PCONF - Partition 0 Core 4 Process Configuration Register */ 416 /*! @{ */ 417 418 #define MC_ME_PRTN0_CORE4_PCONF_CCE_MASK (0x1U) 419 #define MC_ME_PRTN0_CORE4_PCONF_CCE_SHIFT (0U) 420 #define MC_ME_PRTN0_CORE4_PCONF_CCE_WIDTH (1U) 421 #define MC_ME_PRTN0_CORE4_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE4_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE4_PCONF_CCE_MASK) 422 /*! @} */ 423 424 /*! @name PRTN0_CORE4_PUPD - Partition 0 Core 4 Process Update Register */ 425 /*! @{ */ 426 427 #define MC_ME_PRTN0_CORE4_PUPD_CCUPD_MASK (0x1U) 428 #define MC_ME_PRTN0_CORE4_PUPD_CCUPD_SHIFT (0U) 429 #define MC_ME_PRTN0_CORE4_PUPD_CCUPD_WIDTH (1U) 430 #define MC_ME_PRTN0_CORE4_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE4_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE4_PUPD_CCUPD_MASK) 431 /*! @} */ 432 433 /*! @name PRTN0_CORE4_STAT - Partition 0 Core 4 Status Register */ 434 /*! @{ */ 435 436 #define MC_ME_PRTN0_CORE4_STAT_CCS_MASK (0x1U) 437 #define MC_ME_PRTN0_CORE4_STAT_CCS_SHIFT (0U) 438 #define MC_ME_PRTN0_CORE4_STAT_CCS_WIDTH (1U) 439 #define MC_ME_PRTN0_CORE4_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE4_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE4_STAT_CCS_MASK) 440 441 #define MC_ME_PRTN0_CORE4_STAT_WFI_MASK (0x80000000U) 442 #define MC_ME_PRTN0_CORE4_STAT_WFI_SHIFT (31U) 443 #define MC_ME_PRTN0_CORE4_STAT_WFI_WIDTH (1U) 444 #define MC_ME_PRTN0_CORE4_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE4_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE4_STAT_WFI_MASK) 445 /*! @} */ 446 447 /*! @name PRTN0_CORE4_ADDR - Partition 0 Core 4 Address Register */ 448 /*! @{ */ 449 450 #define MC_ME_PRTN0_CORE4_ADDR_ADDR_MASK (0xFFFFFFFCU) 451 #define MC_ME_PRTN0_CORE4_ADDR_ADDR_SHIFT (2U) 452 #define MC_ME_PRTN0_CORE4_ADDR_ADDR_WIDTH (30U) 453 #define MC_ME_PRTN0_CORE4_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE4_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE4_ADDR_ADDR_MASK) 454 /*! @} */ 455 456 /*! @name PRTN0_CORE5_PCONF - Partition 0 Core 5 Process Configuration Register */ 457 /*! @{ */ 458 459 #define MC_ME_PRTN0_CORE5_PCONF_CCE_MASK (0x1U) 460 #define MC_ME_PRTN0_CORE5_PCONF_CCE_SHIFT (0U) 461 #define MC_ME_PRTN0_CORE5_PCONF_CCE_WIDTH (1U) 462 #define MC_ME_PRTN0_CORE5_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE5_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE5_PCONF_CCE_MASK) 463 /*! @} */ 464 465 /*! @name PRTN0_CORE5_PUPD - Partition 0 Core 5 Process Update Register */ 466 /*! @{ */ 467 468 #define MC_ME_PRTN0_CORE5_PUPD_CCUPD_MASK (0x1U) 469 #define MC_ME_PRTN0_CORE5_PUPD_CCUPD_SHIFT (0U) 470 #define MC_ME_PRTN0_CORE5_PUPD_CCUPD_WIDTH (1U) 471 #define MC_ME_PRTN0_CORE5_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE5_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE5_PUPD_CCUPD_MASK) 472 /*! @} */ 473 474 /*! @name PRTN0_CORE5_STAT - Partition 0 Core 5 Status Register */ 475 /*! @{ */ 476 477 #define MC_ME_PRTN0_CORE5_STAT_CCS_MASK (0x1U) 478 #define MC_ME_PRTN0_CORE5_STAT_CCS_SHIFT (0U) 479 #define MC_ME_PRTN0_CORE5_STAT_CCS_WIDTH (1U) 480 #define MC_ME_PRTN0_CORE5_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE5_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE5_STAT_CCS_MASK) 481 482 #define MC_ME_PRTN0_CORE5_STAT_WFI_MASK (0x80000000U) 483 #define MC_ME_PRTN0_CORE5_STAT_WFI_SHIFT (31U) 484 #define MC_ME_PRTN0_CORE5_STAT_WFI_WIDTH (1U) 485 #define MC_ME_PRTN0_CORE5_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE5_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE5_STAT_WFI_MASK) 486 /*! @} */ 487 488 /*! @name PRTN0_CORE5_ADDR - Partition 0 Core 5 Address Register */ 489 /*! @{ */ 490 491 #define MC_ME_PRTN0_CORE5_ADDR_ADDR_MASK (0xFFFFFFFCU) 492 #define MC_ME_PRTN0_CORE5_ADDR_ADDR_SHIFT (2U) 493 #define MC_ME_PRTN0_CORE5_ADDR_ADDR_WIDTH (30U) 494 #define MC_ME_PRTN0_CORE5_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE5_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE5_ADDR_ADDR_MASK) 495 /*! @} */ 496 497 /*! @name PRTN0_CORE6_PCONF - Partition 0 Core 6 Process Configuration Register */ 498 /*! @{ */ 499 500 #define MC_ME_PRTN0_CORE6_PCONF_CCE_MASK (0x1U) 501 #define MC_ME_PRTN0_CORE6_PCONF_CCE_SHIFT (0U) 502 #define MC_ME_PRTN0_CORE6_PCONF_CCE_WIDTH (1U) 503 #define MC_ME_PRTN0_CORE6_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE6_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE6_PCONF_CCE_MASK) 504 /*! @} */ 505 506 /*! @name PRTN0_CORE6_PUPD - Partition 0 Core 6 Process Update Register */ 507 /*! @{ */ 508 509 #define MC_ME_PRTN0_CORE6_PUPD_CCUPD_MASK (0x1U) 510 #define MC_ME_PRTN0_CORE6_PUPD_CCUPD_SHIFT (0U) 511 #define MC_ME_PRTN0_CORE6_PUPD_CCUPD_WIDTH (1U) 512 #define MC_ME_PRTN0_CORE6_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE6_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE6_PUPD_CCUPD_MASK) 513 /*! @} */ 514 515 /*! @name PRTN0_CORE6_STAT - Partition 0 Core 6 Status Register */ 516 /*! @{ */ 517 518 #define MC_ME_PRTN0_CORE6_STAT_CCS_MASK (0x1U) 519 #define MC_ME_PRTN0_CORE6_STAT_CCS_SHIFT (0U) 520 #define MC_ME_PRTN0_CORE6_STAT_CCS_WIDTH (1U) 521 #define MC_ME_PRTN0_CORE6_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE6_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE6_STAT_CCS_MASK) 522 523 #define MC_ME_PRTN0_CORE6_STAT_WFI_MASK (0x80000000U) 524 #define MC_ME_PRTN0_CORE6_STAT_WFI_SHIFT (31U) 525 #define MC_ME_PRTN0_CORE6_STAT_WFI_WIDTH (1U) 526 #define MC_ME_PRTN0_CORE6_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE6_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE6_STAT_WFI_MASK) 527 /*! @} */ 528 529 /*! @name PRTN0_CORE6_ADDR - Partition 0 Core 6 Address Register */ 530 /*! @{ */ 531 532 #define MC_ME_PRTN0_CORE6_ADDR_ADDR_MASK (0xFFFFFFFCU) 533 #define MC_ME_PRTN0_CORE6_ADDR_ADDR_SHIFT (2U) 534 #define MC_ME_PRTN0_CORE6_ADDR_ADDR_WIDTH (30U) 535 #define MC_ME_PRTN0_CORE6_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE6_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE6_ADDR_ADDR_MASK) 536 /*! @} */ 537 538 /*! @name PRTN0_CORE7_PCONF - Partition 0 Core 7 Process Configuration Register */ 539 /*! @{ */ 540 541 #define MC_ME_PRTN0_CORE7_PCONF_CCE_MASK (0x1U) 542 #define MC_ME_PRTN0_CORE7_PCONF_CCE_SHIFT (0U) 543 #define MC_ME_PRTN0_CORE7_PCONF_CCE_WIDTH (1U) 544 #define MC_ME_PRTN0_CORE7_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE7_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE7_PCONF_CCE_MASK) 545 /*! @} */ 546 547 /*! @name PRTN0_CORE7_PUPD - Partition 0 Core 7 Process Update Register */ 548 /*! @{ */ 549 550 #define MC_ME_PRTN0_CORE7_PUPD_CCUPD_MASK (0x1U) 551 #define MC_ME_PRTN0_CORE7_PUPD_CCUPD_SHIFT (0U) 552 #define MC_ME_PRTN0_CORE7_PUPD_CCUPD_WIDTH (1U) 553 #define MC_ME_PRTN0_CORE7_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE7_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE7_PUPD_CCUPD_MASK) 554 /*! @} */ 555 556 /*! @name PRTN0_CORE7_STAT - Partition 0 Core 7 Status Register */ 557 /*! @{ */ 558 559 #define MC_ME_PRTN0_CORE7_STAT_CCS_MASK (0x1U) 560 #define MC_ME_PRTN0_CORE7_STAT_CCS_SHIFT (0U) 561 #define MC_ME_PRTN0_CORE7_STAT_CCS_WIDTH (1U) 562 #define MC_ME_PRTN0_CORE7_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE7_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE7_STAT_CCS_MASK) 563 564 #define MC_ME_PRTN0_CORE7_STAT_WFI_MASK (0x80000000U) 565 #define MC_ME_PRTN0_CORE7_STAT_WFI_SHIFT (31U) 566 #define MC_ME_PRTN0_CORE7_STAT_WFI_WIDTH (1U) 567 #define MC_ME_PRTN0_CORE7_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE7_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE7_STAT_WFI_MASK) 568 /*! @} */ 569 570 /*! @name PRTN0_CORE7_ADDR - Partition 0 Core 7 Address Register */ 571 /*! @{ */ 572 573 #define MC_ME_PRTN0_CORE7_ADDR_ADDR_MASK (0xFFFFFFFCU) 574 #define MC_ME_PRTN0_CORE7_ADDR_ADDR_SHIFT (2U) 575 #define MC_ME_PRTN0_CORE7_ADDR_ADDR_WIDTH (30U) 576 #define MC_ME_PRTN0_CORE7_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE7_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE7_ADDR_ADDR_MASK) 577 /*! @} */ 578 579 /*! @name PRTN1_PCONF - Partition 1 Process Configuration Register */ 580 /*! @{ */ 581 582 #define MC_ME_PRTN1_PCONF_PCE_MASK (0x1U) 583 #define MC_ME_PRTN1_PCONF_PCE_SHIFT (0U) 584 #define MC_ME_PRTN1_PCONF_PCE_WIDTH (1U) 585 #define MC_ME_PRTN1_PCONF_PCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_PCONF_PCE_SHIFT)) & MC_ME_PRTN1_PCONF_PCE_MASK) 586 587 #define MC_ME_PRTN1_PCONF_OSSE_MASK (0x4U) 588 #define MC_ME_PRTN1_PCONF_OSSE_SHIFT (2U) 589 #define MC_ME_PRTN1_PCONF_OSSE_WIDTH (1U) 590 #define MC_ME_PRTN1_PCONF_OSSE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_PCONF_OSSE_SHIFT)) & MC_ME_PRTN1_PCONF_OSSE_MASK) 591 /*! @} */ 592 593 /*! @name PRTN1_PUPD - Partition 1 Process Update Register */ 594 /*! @{ */ 595 596 #define MC_ME_PRTN1_PUPD_PCUD_MASK (0x1U) 597 #define MC_ME_PRTN1_PUPD_PCUD_SHIFT (0U) 598 #define MC_ME_PRTN1_PUPD_PCUD_WIDTH (1U) 599 #define MC_ME_PRTN1_PUPD_PCUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_PUPD_PCUD_SHIFT)) & MC_ME_PRTN1_PUPD_PCUD_MASK) 600 601 #define MC_ME_PRTN1_PUPD_OSSUD_MASK (0x4U) 602 #define MC_ME_PRTN1_PUPD_OSSUD_SHIFT (2U) 603 #define MC_ME_PRTN1_PUPD_OSSUD_WIDTH (1U) 604 #define MC_ME_PRTN1_PUPD_OSSUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_PUPD_OSSUD_SHIFT)) & MC_ME_PRTN1_PUPD_OSSUD_MASK) 605 /*! @} */ 606 607 /*! @name PRTN1_STAT - Partition 1 Status Register */ 608 /*! @{ */ 609 610 #define MC_ME_PRTN1_STAT_PCS_MASK (0x1U) 611 #define MC_ME_PRTN1_STAT_PCS_SHIFT (0U) 612 #define MC_ME_PRTN1_STAT_PCS_WIDTH (1U) 613 #define MC_ME_PRTN1_STAT_PCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_STAT_PCS_SHIFT)) & MC_ME_PRTN1_STAT_PCS_MASK) 614 615 #define MC_ME_PRTN1_STAT_OSSS_MASK (0x4U) 616 #define MC_ME_PRTN1_STAT_OSSS_SHIFT (2U) 617 #define MC_ME_PRTN1_STAT_OSSS_WIDTH (1U) 618 #define MC_ME_PRTN1_STAT_OSSS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_STAT_OSSS_SHIFT)) & MC_ME_PRTN1_STAT_OSSS_MASK) 619 /*! @} */ 620 621 /*! @name PRTN1_CORE0_PCONF - Partition 1 Core 0 Process Configuration Register */ 622 /*! @{ */ 623 624 #define MC_ME_PRTN1_CORE0_PCONF_CCE_MASK (0x1U) 625 #define MC_ME_PRTN1_CORE0_PCONF_CCE_SHIFT (0U) 626 #define MC_ME_PRTN1_CORE0_PCONF_CCE_WIDTH (1U) 627 #define MC_ME_PRTN1_CORE0_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE0_PCONF_CCE_SHIFT)) & MC_ME_PRTN1_CORE0_PCONF_CCE_MASK) 628 /*! @} */ 629 630 /*! @name PRTN1_CORE0_PUPD - Partition 1 Core 0 Process Update Register */ 631 /*! @{ */ 632 633 #define MC_ME_PRTN1_CORE0_PUPD_CCUPD_MASK (0x1U) 634 #define MC_ME_PRTN1_CORE0_PUPD_CCUPD_SHIFT (0U) 635 #define MC_ME_PRTN1_CORE0_PUPD_CCUPD_WIDTH (1U) 636 #define MC_ME_PRTN1_CORE0_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE0_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN1_CORE0_PUPD_CCUPD_MASK) 637 /*! @} */ 638 639 /*! @name PRTN1_CORE0_STAT - Partition 1 Core 0 Status Register */ 640 /*! @{ */ 641 642 #define MC_ME_PRTN1_CORE0_STAT_CCS_MASK (0x1U) 643 #define MC_ME_PRTN1_CORE0_STAT_CCS_SHIFT (0U) 644 #define MC_ME_PRTN1_CORE0_STAT_CCS_WIDTH (1U) 645 #define MC_ME_PRTN1_CORE0_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE0_STAT_CCS_SHIFT)) & MC_ME_PRTN1_CORE0_STAT_CCS_MASK) 646 647 #define MC_ME_PRTN1_CORE0_STAT_WFI_MASK (0x80000000U) 648 #define MC_ME_PRTN1_CORE0_STAT_WFI_SHIFT (31U) 649 #define MC_ME_PRTN1_CORE0_STAT_WFI_WIDTH (1U) 650 #define MC_ME_PRTN1_CORE0_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE0_STAT_WFI_SHIFT)) & MC_ME_PRTN1_CORE0_STAT_WFI_MASK) 651 /*! @} */ 652 653 /*! @name PRTN1_CORE0_ADDR - Partition 1 Core 0 Address Register */ 654 /*! @{ */ 655 656 #define MC_ME_PRTN1_CORE0_ADDR_ADDR_MASK (0xFFFFFFFCU) 657 #define MC_ME_PRTN1_CORE0_ADDR_ADDR_SHIFT (2U) 658 #define MC_ME_PRTN1_CORE0_ADDR_ADDR_WIDTH (30U) 659 #define MC_ME_PRTN1_CORE0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE0_ADDR_ADDR_SHIFT)) & MC_ME_PRTN1_CORE0_ADDR_ADDR_MASK) 660 /*! @} */ 661 662 /*! @name PRTN1_CORE1_PCONF - Partition 1 Core 1 Process Configuration Register */ 663 /*! @{ */ 664 665 #define MC_ME_PRTN1_CORE1_PCONF_CCE_MASK (0x1U) 666 #define MC_ME_PRTN1_CORE1_PCONF_CCE_SHIFT (0U) 667 #define MC_ME_PRTN1_CORE1_PCONF_CCE_WIDTH (1U) 668 #define MC_ME_PRTN1_CORE1_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE1_PCONF_CCE_SHIFT)) & MC_ME_PRTN1_CORE1_PCONF_CCE_MASK) 669 /*! @} */ 670 671 /*! @name PRTN1_CORE1_PUPD - Partition 1 Core 1 Process Update Register */ 672 /*! @{ */ 673 674 #define MC_ME_PRTN1_CORE1_PUPD_CCUPD_MASK (0x1U) 675 #define MC_ME_PRTN1_CORE1_PUPD_CCUPD_SHIFT (0U) 676 #define MC_ME_PRTN1_CORE1_PUPD_CCUPD_WIDTH (1U) 677 #define MC_ME_PRTN1_CORE1_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE1_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN1_CORE1_PUPD_CCUPD_MASK) 678 /*! @} */ 679 680 /*! @name PRTN1_CORE1_STAT - Partition 1 Core 1 Status Register */ 681 /*! @{ */ 682 683 #define MC_ME_PRTN1_CORE1_STAT_CCS_MASK (0x1U) 684 #define MC_ME_PRTN1_CORE1_STAT_CCS_SHIFT (0U) 685 #define MC_ME_PRTN1_CORE1_STAT_CCS_WIDTH (1U) 686 #define MC_ME_PRTN1_CORE1_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE1_STAT_CCS_SHIFT)) & MC_ME_PRTN1_CORE1_STAT_CCS_MASK) 687 688 #define MC_ME_PRTN1_CORE1_STAT_WFI_MASK (0x80000000U) 689 #define MC_ME_PRTN1_CORE1_STAT_WFI_SHIFT (31U) 690 #define MC_ME_PRTN1_CORE1_STAT_WFI_WIDTH (1U) 691 #define MC_ME_PRTN1_CORE1_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE1_STAT_WFI_SHIFT)) & MC_ME_PRTN1_CORE1_STAT_WFI_MASK) 692 /*! @} */ 693 694 /*! @name PRTN1_CORE1_ADDR - Partition 1 Core 1 Address Register */ 695 /*! @{ */ 696 697 #define MC_ME_PRTN1_CORE1_ADDR_ADDR_MASK (0xFFFFFFFCU) 698 #define MC_ME_PRTN1_CORE1_ADDR_ADDR_SHIFT (2U) 699 #define MC_ME_PRTN1_CORE1_ADDR_ADDR_WIDTH (30U) 700 #define MC_ME_PRTN1_CORE1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE1_ADDR_ADDR_SHIFT)) & MC_ME_PRTN1_CORE1_ADDR_ADDR_MASK) 701 /*! @} */ 702 703 /*! @name PRTN1_CORE2_PCONF - Partition 1 Core 2 Process Configuration Register */ 704 /*! @{ */ 705 706 #define MC_ME_PRTN1_CORE2_PCONF_CCE_MASK (0x1U) 707 #define MC_ME_PRTN1_CORE2_PCONF_CCE_SHIFT (0U) 708 #define MC_ME_PRTN1_CORE2_PCONF_CCE_WIDTH (1U) 709 #define MC_ME_PRTN1_CORE2_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE2_PCONF_CCE_SHIFT)) & MC_ME_PRTN1_CORE2_PCONF_CCE_MASK) 710 /*! @} */ 711 712 /*! @name PRTN1_CORE2_PUPD - Partition 1 Core 2 Process Update Register */ 713 /*! @{ */ 714 715 #define MC_ME_PRTN1_CORE2_PUPD_CCUPD_MASK (0x1U) 716 #define MC_ME_PRTN1_CORE2_PUPD_CCUPD_SHIFT (0U) 717 #define MC_ME_PRTN1_CORE2_PUPD_CCUPD_WIDTH (1U) 718 #define MC_ME_PRTN1_CORE2_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE2_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN1_CORE2_PUPD_CCUPD_MASK) 719 /*! @} */ 720 721 /*! @name PRTN1_CORE2_STAT - Partition 1 Core 2 Status Register */ 722 /*! @{ */ 723 724 #define MC_ME_PRTN1_CORE2_STAT_CCS_MASK (0x1U) 725 #define MC_ME_PRTN1_CORE2_STAT_CCS_SHIFT (0U) 726 #define MC_ME_PRTN1_CORE2_STAT_CCS_WIDTH (1U) 727 #define MC_ME_PRTN1_CORE2_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE2_STAT_CCS_SHIFT)) & MC_ME_PRTN1_CORE2_STAT_CCS_MASK) 728 729 #define MC_ME_PRTN1_CORE2_STAT_WFI_MASK (0x80000000U) 730 #define MC_ME_PRTN1_CORE2_STAT_WFI_SHIFT (31U) 731 #define MC_ME_PRTN1_CORE2_STAT_WFI_WIDTH (1U) 732 #define MC_ME_PRTN1_CORE2_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE2_STAT_WFI_SHIFT)) & MC_ME_PRTN1_CORE2_STAT_WFI_MASK) 733 /*! @} */ 734 735 /*! @name PRTN1_CORE2_ADDR - Partition 1 Core 2 Address Register */ 736 /*! @{ */ 737 738 #define MC_ME_PRTN1_CORE2_ADDR_ADDR_MASK (0xFFFFFFFCU) 739 #define MC_ME_PRTN1_CORE2_ADDR_ADDR_SHIFT (2U) 740 #define MC_ME_PRTN1_CORE2_ADDR_ADDR_WIDTH (30U) 741 #define MC_ME_PRTN1_CORE2_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE2_ADDR_ADDR_SHIFT)) & MC_ME_PRTN1_CORE2_ADDR_ADDR_MASK) 742 /*! @} */ 743 744 /*! @name PRTN1_CORE3_PCONF - Partition 1 Core 3 Process Configuration Register */ 745 /*! @{ */ 746 747 #define MC_ME_PRTN1_CORE3_PCONF_CCE_MASK (0x1U) 748 #define MC_ME_PRTN1_CORE3_PCONF_CCE_SHIFT (0U) 749 #define MC_ME_PRTN1_CORE3_PCONF_CCE_WIDTH (1U) 750 #define MC_ME_PRTN1_CORE3_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE3_PCONF_CCE_SHIFT)) & MC_ME_PRTN1_CORE3_PCONF_CCE_MASK) 751 /*! @} */ 752 753 /*! @name PRTN1_CORE3_PUPD - Partition 1 Core 3 Process Update Register */ 754 /*! @{ */ 755 756 #define MC_ME_PRTN1_CORE3_PUPD_CCUPD_MASK (0x1U) 757 #define MC_ME_PRTN1_CORE3_PUPD_CCUPD_SHIFT (0U) 758 #define MC_ME_PRTN1_CORE3_PUPD_CCUPD_WIDTH (1U) 759 #define MC_ME_PRTN1_CORE3_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE3_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN1_CORE3_PUPD_CCUPD_MASK) 760 /*! @} */ 761 762 /*! @name PRTN1_CORE3_STAT - Partition 1 Core 3 Status Register */ 763 /*! @{ */ 764 765 #define MC_ME_PRTN1_CORE3_STAT_CCS_MASK (0x1U) 766 #define MC_ME_PRTN1_CORE3_STAT_CCS_SHIFT (0U) 767 #define MC_ME_PRTN1_CORE3_STAT_CCS_WIDTH (1U) 768 #define MC_ME_PRTN1_CORE3_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE3_STAT_CCS_SHIFT)) & MC_ME_PRTN1_CORE3_STAT_CCS_MASK) 769 770 #define MC_ME_PRTN1_CORE3_STAT_WFI_MASK (0x80000000U) 771 #define MC_ME_PRTN1_CORE3_STAT_WFI_SHIFT (31U) 772 #define MC_ME_PRTN1_CORE3_STAT_WFI_WIDTH (1U) 773 #define MC_ME_PRTN1_CORE3_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE3_STAT_WFI_SHIFT)) & MC_ME_PRTN1_CORE3_STAT_WFI_MASK) 774 /*! @} */ 775 776 /*! @name PRTN1_CORE3_ADDR - Partition 1 Core 3 Address Register */ 777 /*! @{ */ 778 779 #define MC_ME_PRTN1_CORE3_ADDR_ADDR_MASK (0xFFFFFFFCU) 780 #define MC_ME_PRTN1_CORE3_ADDR_ADDR_SHIFT (2U) 781 #define MC_ME_PRTN1_CORE3_ADDR_ADDR_WIDTH (30U) 782 #define MC_ME_PRTN1_CORE3_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_CORE3_ADDR_ADDR_SHIFT)) & MC_ME_PRTN1_CORE3_ADDR_ADDR_MASK) 783 /*! @} */ 784 785 /*! @name PRTN2_PCONF - Partition 2 Process Configuration Register */ 786 /*! @{ */ 787 788 #define MC_ME_PRTN2_PCONF_PCE_MASK (0x1U) 789 #define MC_ME_PRTN2_PCONF_PCE_SHIFT (0U) 790 #define MC_ME_PRTN2_PCONF_PCE_WIDTH (1U) 791 #define MC_ME_PRTN2_PCONF_PCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_PCONF_PCE_SHIFT)) & MC_ME_PRTN2_PCONF_PCE_MASK) 792 793 #define MC_ME_PRTN2_PCONF_OSSE_MASK (0x4U) 794 #define MC_ME_PRTN2_PCONF_OSSE_SHIFT (2U) 795 #define MC_ME_PRTN2_PCONF_OSSE_WIDTH (1U) 796 #define MC_ME_PRTN2_PCONF_OSSE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_PCONF_OSSE_SHIFT)) & MC_ME_PRTN2_PCONF_OSSE_MASK) 797 /*! @} */ 798 799 /*! @name PRTN2_PUPD - Partition 2 Process Update Register */ 800 /*! @{ */ 801 802 #define MC_ME_PRTN2_PUPD_PCUD_MASK (0x1U) 803 #define MC_ME_PRTN2_PUPD_PCUD_SHIFT (0U) 804 #define MC_ME_PRTN2_PUPD_PCUD_WIDTH (1U) 805 #define MC_ME_PRTN2_PUPD_PCUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_PUPD_PCUD_SHIFT)) & MC_ME_PRTN2_PUPD_PCUD_MASK) 806 807 #define MC_ME_PRTN2_PUPD_OSSUD_MASK (0x4U) 808 #define MC_ME_PRTN2_PUPD_OSSUD_SHIFT (2U) 809 #define MC_ME_PRTN2_PUPD_OSSUD_WIDTH (1U) 810 #define MC_ME_PRTN2_PUPD_OSSUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_PUPD_OSSUD_SHIFT)) & MC_ME_PRTN2_PUPD_OSSUD_MASK) 811 /*! @} */ 812 813 /*! @name PRTN2_STAT - Partition 2 Status Register */ 814 /*! @{ */ 815 816 #define MC_ME_PRTN2_STAT_PCS_MASK (0x1U) 817 #define MC_ME_PRTN2_STAT_PCS_SHIFT (0U) 818 #define MC_ME_PRTN2_STAT_PCS_WIDTH (1U) 819 #define MC_ME_PRTN2_STAT_PCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_STAT_PCS_SHIFT)) & MC_ME_PRTN2_STAT_PCS_MASK) 820 821 #define MC_ME_PRTN2_STAT_OSSS_MASK (0x4U) 822 #define MC_ME_PRTN2_STAT_OSSS_SHIFT (2U) 823 #define MC_ME_PRTN2_STAT_OSSS_WIDTH (1U) 824 #define MC_ME_PRTN2_STAT_OSSS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_STAT_OSSS_SHIFT)) & MC_ME_PRTN2_STAT_OSSS_MASK) 825 /*! @} */ 826 827 /*! @name PRTN2_CORE0_PCONF - Partition 2 Core 0 Process Configuration Register */ 828 /*! @{ */ 829 830 #define MC_ME_PRTN2_CORE0_PCONF_CCE_MASK (0x1U) 831 #define MC_ME_PRTN2_CORE0_PCONF_CCE_SHIFT (0U) 832 #define MC_ME_PRTN2_CORE0_PCONF_CCE_WIDTH (1U) 833 #define MC_ME_PRTN2_CORE0_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE0_PCONF_CCE_SHIFT)) & MC_ME_PRTN2_CORE0_PCONF_CCE_MASK) 834 /*! @} */ 835 836 /*! @name PRTN2_CORE0_PUPD - Partition 2 Core 0 Process Update Register */ 837 /*! @{ */ 838 839 #define MC_ME_PRTN2_CORE0_PUPD_CCUPD_MASK (0x1U) 840 #define MC_ME_PRTN2_CORE0_PUPD_CCUPD_SHIFT (0U) 841 #define MC_ME_PRTN2_CORE0_PUPD_CCUPD_WIDTH (1U) 842 #define MC_ME_PRTN2_CORE0_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE0_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN2_CORE0_PUPD_CCUPD_MASK) 843 /*! @} */ 844 845 /*! @name PRTN2_CORE0_STAT - Partition 2 Core 0 Status Register */ 846 /*! @{ */ 847 848 #define MC_ME_PRTN2_CORE0_STAT_CCS_MASK (0x1U) 849 #define MC_ME_PRTN2_CORE0_STAT_CCS_SHIFT (0U) 850 #define MC_ME_PRTN2_CORE0_STAT_CCS_WIDTH (1U) 851 #define MC_ME_PRTN2_CORE0_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE0_STAT_CCS_SHIFT)) & MC_ME_PRTN2_CORE0_STAT_CCS_MASK) 852 853 #define MC_ME_PRTN2_CORE0_STAT_WFI_MASK (0x80000000U) 854 #define MC_ME_PRTN2_CORE0_STAT_WFI_SHIFT (31U) 855 #define MC_ME_PRTN2_CORE0_STAT_WFI_WIDTH (1U) 856 #define MC_ME_PRTN2_CORE0_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE0_STAT_WFI_SHIFT)) & MC_ME_PRTN2_CORE0_STAT_WFI_MASK) 857 /*! @} */ 858 859 /*! @name PRTN2_CORE0_ADDR - Partition 2 Core 0 Address Register */ 860 /*! @{ */ 861 862 #define MC_ME_PRTN2_CORE0_ADDR_ADDR_MASK (0xFFFFFFFCU) 863 #define MC_ME_PRTN2_CORE0_ADDR_ADDR_SHIFT (2U) 864 #define MC_ME_PRTN2_CORE0_ADDR_ADDR_WIDTH (30U) 865 #define MC_ME_PRTN2_CORE0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE0_ADDR_ADDR_SHIFT)) & MC_ME_PRTN2_CORE0_ADDR_ADDR_MASK) 866 /*! @} */ 867 868 /*! @name PRTN2_CORE1_PCONF - Partition 2 Core 1 Process Configuration Register */ 869 /*! @{ */ 870 871 #define MC_ME_PRTN2_CORE1_PCONF_CCE_MASK (0x1U) 872 #define MC_ME_PRTN2_CORE1_PCONF_CCE_SHIFT (0U) 873 #define MC_ME_PRTN2_CORE1_PCONF_CCE_WIDTH (1U) 874 #define MC_ME_PRTN2_CORE1_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE1_PCONF_CCE_SHIFT)) & MC_ME_PRTN2_CORE1_PCONF_CCE_MASK) 875 /*! @} */ 876 877 /*! @name PRTN2_CORE1_PUPD - Partition 2 Core 1 Process Update Register */ 878 /*! @{ */ 879 880 #define MC_ME_PRTN2_CORE1_PUPD_CCUPD_MASK (0x1U) 881 #define MC_ME_PRTN2_CORE1_PUPD_CCUPD_SHIFT (0U) 882 #define MC_ME_PRTN2_CORE1_PUPD_CCUPD_WIDTH (1U) 883 #define MC_ME_PRTN2_CORE1_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE1_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN2_CORE1_PUPD_CCUPD_MASK) 884 /*! @} */ 885 886 /*! @name PRTN2_CORE1_STAT - Partition 2 Core 1 Status Register */ 887 /*! @{ */ 888 889 #define MC_ME_PRTN2_CORE1_STAT_CCS_MASK (0x1U) 890 #define MC_ME_PRTN2_CORE1_STAT_CCS_SHIFT (0U) 891 #define MC_ME_PRTN2_CORE1_STAT_CCS_WIDTH (1U) 892 #define MC_ME_PRTN2_CORE1_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE1_STAT_CCS_SHIFT)) & MC_ME_PRTN2_CORE1_STAT_CCS_MASK) 893 894 #define MC_ME_PRTN2_CORE1_STAT_WFI_MASK (0x80000000U) 895 #define MC_ME_PRTN2_CORE1_STAT_WFI_SHIFT (31U) 896 #define MC_ME_PRTN2_CORE1_STAT_WFI_WIDTH (1U) 897 #define MC_ME_PRTN2_CORE1_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE1_STAT_WFI_SHIFT)) & MC_ME_PRTN2_CORE1_STAT_WFI_MASK) 898 /*! @} */ 899 900 /*! @name PRTN2_CORE1_ADDR - Partition 2 Core 1 Address Register */ 901 /*! @{ */ 902 903 #define MC_ME_PRTN2_CORE1_ADDR_ADDR_MASK (0xFFFFFFFCU) 904 #define MC_ME_PRTN2_CORE1_ADDR_ADDR_SHIFT (2U) 905 #define MC_ME_PRTN2_CORE1_ADDR_ADDR_WIDTH (30U) 906 #define MC_ME_PRTN2_CORE1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE1_ADDR_ADDR_SHIFT)) & MC_ME_PRTN2_CORE1_ADDR_ADDR_MASK) 907 /*! @} */ 908 909 /*! @name PRTN2_CORE2_PCONF - Partition 2 Core 2 Process Configuration Register */ 910 /*! @{ */ 911 912 #define MC_ME_PRTN2_CORE2_PCONF_CCE_MASK (0x1U) 913 #define MC_ME_PRTN2_CORE2_PCONF_CCE_SHIFT (0U) 914 #define MC_ME_PRTN2_CORE2_PCONF_CCE_WIDTH (1U) 915 #define MC_ME_PRTN2_CORE2_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE2_PCONF_CCE_SHIFT)) & MC_ME_PRTN2_CORE2_PCONF_CCE_MASK) 916 /*! @} */ 917 918 /*! @name PRTN2_CORE2_PUPD - Partition 2 Core 2 Process Update Register */ 919 /*! @{ */ 920 921 #define MC_ME_PRTN2_CORE2_PUPD_CCUPD_MASK (0x1U) 922 #define MC_ME_PRTN2_CORE2_PUPD_CCUPD_SHIFT (0U) 923 #define MC_ME_PRTN2_CORE2_PUPD_CCUPD_WIDTH (1U) 924 #define MC_ME_PRTN2_CORE2_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE2_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN2_CORE2_PUPD_CCUPD_MASK) 925 /*! @} */ 926 927 /*! @name PRTN2_CORE2_STAT - Partition 2 Core 2 Status Register */ 928 /*! @{ */ 929 930 #define MC_ME_PRTN2_CORE2_STAT_CCS_MASK (0x1U) 931 #define MC_ME_PRTN2_CORE2_STAT_CCS_SHIFT (0U) 932 #define MC_ME_PRTN2_CORE2_STAT_CCS_WIDTH (1U) 933 #define MC_ME_PRTN2_CORE2_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE2_STAT_CCS_SHIFT)) & MC_ME_PRTN2_CORE2_STAT_CCS_MASK) 934 935 #define MC_ME_PRTN2_CORE2_STAT_WFI_MASK (0x80000000U) 936 #define MC_ME_PRTN2_CORE2_STAT_WFI_SHIFT (31U) 937 #define MC_ME_PRTN2_CORE2_STAT_WFI_WIDTH (1U) 938 #define MC_ME_PRTN2_CORE2_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE2_STAT_WFI_SHIFT)) & MC_ME_PRTN2_CORE2_STAT_WFI_MASK) 939 /*! @} */ 940 941 /*! @name PRTN2_CORE2_ADDR - Partition 2 Core 2 Address Register */ 942 /*! @{ */ 943 944 #define MC_ME_PRTN2_CORE2_ADDR_ADDR_MASK (0xFFFFFFFCU) 945 #define MC_ME_PRTN2_CORE2_ADDR_ADDR_SHIFT (2U) 946 #define MC_ME_PRTN2_CORE2_ADDR_ADDR_WIDTH (30U) 947 #define MC_ME_PRTN2_CORE2_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE2_ADDR_ADDR_SHIFT)) & MC_ME_PRTN2_CORE2_ADDR_ADDR_MASK) 948 /*! @} */ 949 950 /*! @name PRTN2_CORE3_PCONF - Partition 2 Core 3 Process Configuration Register */ 951 /*! @{ */ 952 953 #define MC_ME_PRTN2_CORE3_PCONF_CCE_MASK (0x1U) 954 #define MC_ME_PRTN2_CORE3_PCONF_CCE_SHIFT (0U) 955 #define MC_ME_PRTN2_CORE3_PCONF_CCE_WIDTH (1U) 956 #define MC_ME_PRTN2_CORE3_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE3_PCONF_CCE_SHIFT)) & MC_ME_PRTN2_CORE3_PCONF_CCE_MASK) 957 /*! @} */ 958 959 /*! @name PRTN2_CORE3_PUPD - Partition 2 Core 3 Process Update Register */ 960 /*! @{ */ 961 962 #define MC_ME_PRTN2_CORE3_PUPD_CCUPD_MASK (0x1U) 963 #define MC_ME_PRTN2_CORE3_PUPD_CCUPD_SHIFT (0U) 964 #define MC_ME_PRTN2_CORE3_PUPD_CCUPD_WIDTH (1U) 965 #define MC_ME_PRTN2_CORE3_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE3_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN2_CORE3_PUPD_CCUPD_MASK) 966 /*! @} */ 967 968 /*! @name PRTN2_CORE3_STAT - Partition 2 Core 3 Status Register */ 969 /*! @{ */ 970 971 #define MC_ME_PRTN2_CORE3_STAT_CCS_MASK (0x1U) 972 #define MC_ME_PRTN2_CORE3_STAT_CCS_SHIFT (0U) 973 #define MC_ME_PRTN2_CORE3_STAT_CCS_WIDTH (1U) 974 #define MC_ME_PRTN2_CORE3_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE3_STAT_CCS_SHIFT)) & MC_ME_PRTN2_CORE3_STAT_CCS_MASK) 975 976 #define MC_ME_PRTN2_CORE3_STAT_WFI_MASK (0x80000000U) 977 #define MC_ME_PRTN2_CORE3_STAT_WFI_SHIFT (31U) 978 #define MC_ME_PRTN2_CORE3_STAT_WFI_WIDTH (1U) 979 #define MC_ME_PRTN2_CORE3_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE3_STAT_WFI_SHIFT)) & MC_ME_PRTN2_CORE3_STAT_WFI_MASK) 980 /*! @} */ 981 982 /*! @name PRTN2_CORE3_ADDR - Partition 2 Core 3 Address Register */ 983 /*! @{ */ 984 985 #define MC_ME_PRTN2_CORE3_ADDR_ADDR_MASK (0xFFFFFFFCU) 986 #define MC_ME_PRTN2_CORE3_ADDR_ADDR_SHIFT (2U) 987 #define MC_ME_PRTN2_CORE3_ADDR_ADDR_WIDTH (30U) 988 #define MC_ME_PRTN2_CORE3_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_CORE3_ADDR_ADDR_SHIFT)) & MC_ME_PRTN2_CORE3_ADDR_ADDR_MASK) 989 /*! @} */ 990 991 /*! 992 * @} 993 */ /* end of group MC_ME_Register_Masks */ 994 995 /*! 996 * @} 997 */ /* end of group MC_ME_Peripheral_Access_Layer */ 998 999 #endif /* #if !defined(S32Z2_MC_ME_H_) */ 1000
