1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_ERM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_ERM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_ERM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_ERM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ERM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ERM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ 74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ 75 __IO uint32_t CR2; /**< ERM Configuration Register 2, offset: 0x8 */ 76 uint8_t RESERVED_0[4]; 77 __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ 78 __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14 */ 79 __IO uint32_t SR2; /**< ERM Status Register 2, offset: 0x18 */ 80 uint8_t RESERVED_1[228]; 81 __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ 82 __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ 83 __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ 84 uint8_t RESERVED_2[4]; 85 __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110 */ 86 __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114 */ 87 __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ 88 uint8_t RESERVED_3[12]; 89 __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ 90 uint8_t RESERVED_4[12]; 91 __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ 92 uint8_t RESERVED_5[12]; 93 __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */ 94 uint8_t RESERVED_6[12]; 95 __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ 96 uint8_t RESERVED_7[12]; 97 __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ 98 uint8_t RESERVED_8[12]; 99 __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ 100 uint8_t RESERVED_9[12]; 101 __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */ 102 uint8_t RESERVED_10[12]; 103 __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */ 104 uint8_t RESERVED_11[4]; 105 __I uint32_t EAR10; /**< ERM Memory 10 Error Address Register, offset: 0x1A0 */ 106 __I uint32_t SYN10; /**< ERM Memory 10 Syndrome Register, offset: 0x1A4 */ 107 __IO uint32_t CORR_ERR_CNT10; /**< ERM Memory 10 Correctable Error Count Register, offset: 0x1A8 */ 108 uint8_t RESERVED_12[4]; 109 __I uint32_t EAR11; /**< ERM Memory 11 Error Address Register, offset: 0x1B0 */ 110 __I uint32_t SYN11; /**< ERM Memory 11 Syndrome Register, offset: 0x1B4 */ 111 __IO uint32_t CORR_ERR_CNT11; /**< ERM Memory 11 Correctable Error Count Register, offset: 0x1B8 */ 112 uint8_t RESERVED_13[4]; 113 __I uint32_t EAR12; /**< ERM Memory 12 Error Address Register, offset: 0x1C0 */ 114 __I uint32_t SYN12; /**< ERM Memory 12 Syndrome Register, offset: 0x1C4 */ 115 __IO uint32_t CORR_ERR_CNT12; /**< ERM Memory 12 Correctable Error Count Register, offset: 0x1C8 */ 116 uint8_t RESERVED_14[4]; 117 __I uint32_t EAR13; /**< ERM Memory 13 Error Address Register, offset: 0x1D0 */ 118 __I uint32_t SYN13; /**< ERM Memory 13 Syndrome Register, offset: 0x1D4 */ 119 __IO uint32_t CORR_ERR_CNT13; /**< ERM Memory 13 Correctable Error Count Register, offset: 0x1D8 */ 120 uint8_t RESERVED_15[4]; 121 __I uint32_t EAR14; /**< ERM Memory 14 Error Address Register, offset: 0x1E0 */ 122 __I uint32_t SYN14; /**< ERM Memory 14 Syndrome Register, offset: 0x1E4 */ 123 __IO uint32_t CORR_ERR_CNT14; /**< ERM Memory 14 Correctable Error Count Register, offset: 0x1E8 */ 124 uint8_t RESERVED_16[4]; 125 __I uint32_t EAR15; /**< ERM Memory 15 Error Address Register, offset: 0x1F0 */ 126 __I uint32_t SYN15; /**< ERM Memory 15 Syndrome Register, offset: 0x1F4 */ 127 __IO uint32_t CORR_ERR_CNT15; /**< ERM Memory 15 Correctable Error Count Register, offset: 0x1F8 */ 128 uint8_t RESERVED_17[4]; 129 __I uint32_t EAR16; /**< ERM Memory 16 Error Address Register, offset: 0x200 */ 130 __I uint32_t SYN16; /**< ERM Memory 16 Syndrome Register, offset: 0x204 */ 131 __IO uint32_t CORR_ERR_CNT16; /**< ERM Memory 16 Correctable Error Count Register, offset: 0x208 */ 132 uint8_t RESERVED_18[4]; 133 __I uint32_t EAR17; /**< ERM Memory 17 Error Address Register, offset: 0x210 */ 134 uint8_t RESERVED_19[4]; 135 __IO uint32_t CORR_ERR_CNT17; /**< ERM Memory 17 Correctable Error Count Register, offset: 0x218 */ 136 uint8_t RESERVED_20[4]; 137 __I uint32_t EAR18; /**< ERM Memory 18 Error Address Register, offset: 0x220 */ 138 uint8_t RESERVED_21[4]; 139 __IO uint32_t CORR_ERR_CNT18; /**< ERM Memory 18 Correctable Error Count Register, offset: 0x228 */ 140 uint8_t RESERVED_22[4]; 141 __I uint32_t EAR19; /**< ERM Memory 19 Error Address Register, offset: 0x230 */ 142 uint8_t RESERVED_23[4]; 143 __IO uint32_t CORR_ERR_CNT19; /**< ERM Memory 19 Correctable Error Count Register, offset: 0x238 */ 144 } ERM_Type, *ERM_MemMapPtr; 145 146 /** Number of instances of the ERM module. */ 147 #define ERM_INSTANCE_COUNT (1u) 148 149 /* ERM - Peripheral instance base addresses */ 150 /** Peripheral ERM base address */ 151 #define IP_ERM_BASE (0x4025C000u) 152 /** Peripheral ERM base pointer */ 153 #define IP_ERM ((ERM_Type *)IP_ERM_BASE) 154 /** Array initializer of ERM peripheral base addresses */ 155 #define IP_ERM_BASE_ADDRS { IP_ERM_BASE } 156 /** Array initializer of ERM peripheral base pointers */ 157 #define IP_ERM_BASE_PTRS { IP_ERM } 158 159 /* ---------------------------------------------------------------------------- 160 -- ERM Register Masks 161 ---------------------------------------------------------------------------- */ 162 163 /*! 164 * @addtogroup ERM_Register_Masks ERM Register Masks 165 * @{ 166 */ 167 168 /*! @name CR0 - ERM Configuration Register 0 */ 169 /*! @{ */ 170 171 #define ERM_CR0_ENCIE7_MASK (0x4U) 172 #define ERM_CR0_ENCIE7_SHIFT (2U) 173 #define ERM_CR0_ENCIE7_WIDTH (1U) 174 #define ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK) 175 176 #define ERM_CR0_ESCIE7_MASK (0x8U) 177 #define ERM_CR0_ESCIE7_SHIFT (3U) 178 #define ERM_CR0_ESCIE7_WIDTH (1U) 179 #define ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK) 180 181 #define ERM_CR0_ENCIE6_MASK (0x40U) 182 #define ERM_CR0_ENCIE6_SHIFT (6U) 183 #define ERM_CR0_ENCIE6_WIDTH (1U) 184 #define ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK) 185 186 #define ERM_CR0_ESCIE6_MASK (0x80U) 187 #define ERM_CR0_ESCIE6_SHIFT (7U) 188 #define ERM_CR0_ESCIE6_WIDTH (1U) 189 #define ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK) 190 191 #define ERM_CR0_ENCIE5_MASK (0x400U) 192 #define ERM_CR0_ENCIE5_SHIFT (10U) 193 #define ERM_CR0_ENCIE5_WIDTH (1U) 194 #define ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK) 195 196 #define ERM_CR0_ESCIE5_MASK (0x800U) 197 #define ERM_CR0_ESCIE5_SHIFT (11U) 198 #define ERM_CR0_ESCIE5_WIDTH (1U) 199 #define ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK) 200 201 #define ERM_CR0_ENCIE4_MASK (0x4000U) 202 #define ERM_CR0_ENCIE4_SHIFT (14U) 203 #define ERM_CR0_ENCIE4_WIDTH (1U) 204 #define ERM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK) 205 206 #define ERM_CR0_ESCIE4_MASK (0x8000U) 207 #define ERM_CR0_ESCIE4_SHIFT (15U) 208 #define ERM_CR0_ESCIE4_WIDTH (1U) 209 #define ERM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK) 210 211 #define ERM_CR0_ENCIE3_MASK (0x40000U) 212 #define ERM_CR0_ENCIE3_SHIFT (18U) 213 #define ERM_CR0_ENCIE3_WIDTH (1U) 214 #define ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK) 215 216 #define ERM_CR0_ESCIE3_MASK (0x80000U) 217 #define ERM_CR0_ESCIE3_SHIFT (19U) 218 #define ERM_CR0_ESCIE3_WIDTH (1U) 219 #define ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK) 220 221 #define ERM_CR0_ENCIE2_MASK (0x400000U) 222 #define ERM_CR0_ENCIE2_SHIFT (22U) 223 #define ERM_CR0_ENCIE2_WIDTH (1U) 224 #define ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK) 225 226 #define ERM_CR0_ESCIE2_MASK (0x800000U) 227 #define ERM_CR0_ESCIE2_SHIFT (23U) 228 #define ERM_CR0_ESCIE2_WIDTH (1U) 229 #define ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK) 230 231 #define ERM_CR0_ENCIE1_MASK (0x4000000U) 232 #define ERM_CR0_ENCIE1_SHIFT (26U) 233 #define ERM_CR0_ENCIE1_WIDTH (1U) 234 #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) 235 236 #define ERM_CR0_ESCIE1_MASK (0x8000000U) 237 #define ERM_CR0_ESCIE1_SHIFT (27U) 238 #define ERM_CR0_ESCIE1_WIDTH (1U) 239 #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) 240 241 #define ERM_CR0_ENCIE0_MASK (0x40000000U) 242 #define ERM_CR0_ENCIE0_SHIFT (30U) 243 #define ERM_CR0_ENCIE0_WIDTH (1U) 244 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) 245 246 #define ERM_CR0_ESCIE0_MASK (0x80000000U) 247 #define ERM_CR0_ESCIE0_SHIFT (31U) 248 #define ERM_CR0_ESCIE0_WIDTH (1U) 249 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) 250 /*! @} */ 251 252 /*! @name CR1 - ERM Configuration Register 1 */ 253 /*! @{ */ 254 255 #define ERM_CR1_ENCIE15_MASK (0x4U) 256 #define ERM_CR1_ENCIE15_SHIFT (2U) 257 #define ERM_CR1_ENCIE15_WIDTH (1U) 258 #define ERM_CR1_ENCIE15(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE15_SHIFT)) & ERM_CR1_ENCIE15_MASK) 259 260 #define ERM_CR1_ESCIE15_MASK (0x8U) 261 #define ERM_CR1_ESCIE15_SHIFT (3U) 262 #define ERM_CR1_ESCIE15_WIDTH (1U) 263 #define ERM_CR1_ESCIE15(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE15_SHIFT)) & ERM_CR1_ESCIE15_MASK) 264 265 #define ERM_CR1_ENCIE14_MASK (0x40U) 266 #define ERM_CR1_ENCIE14_SHIFT (6U) 267 #define ERM_CR1_ENCIE14_WIDTH (1U) 268 #define ERM_CR1_ENCIE14(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE14_SHIFT)) & ERM_CR1_ENCIE14_MASK) 269 270 #define ERM_CR1_ESCIE14_MASK (0x80U) 271 #define ERM_CR1_ESCIE14_SHIFT (7U) 272 #define ERM_CR1_ESCIE14_WIDTH (1U) 273 #define ERM_CR1_ESCIE14(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE14_SHIFT)) & ERM_CR1_ESCIE14_MASK) 274 275 #define ERM_CR1_ENCIE13_MASK (0x400U) 276 #define ERM_CR1_ENCIE13_SHIFT (10U) 277 #define ERM_CR1_ENCIE13_WIDTH (1U) 278 #define ERM_CR1_ENCIE13(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE13_SHIFT)) & ERM_CR1_ENCIE13_MASK) 279 280 #define ERM_CR1_ESCIE13_MASK (0x800U) 281 #define ERM_CR1_ESCIE13_SHIFT (11U) 282 #define ERM_CR1_ESCIE13_WIDTH (1U) 283 #define ERM_CR1_ESCIE13(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE13_SHIFT)) & ERM_CR1_ESCIE13_MASK) 284 285 #define ERM_CR1_ENCIE12_MASK (0x4000U) 286 #define ERM_CR1_ENCIE12_SHIFT (14U) 287 #define ERM_CR1_ENCIE12_WIDTH (1U) 288 #define ERM_CR1_ENCIE12(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE12_SHIFT)) & ERM_CR1_ENCIE12_MASK) 289 290 #define ERM_CR1_ESCIE12_MASK (0x8000U) 291 #define ERM_CR1_ESCIE12_SHIFT (15U) 292 #define ERM_CR1_ESCIE12_WIDTH (1U) 293 #define ERM_CR1_ESCIE12(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE12_SHIFT)) & ERM_CR1_ESCIE12_MASK) 294 295 #define ERM_CR1_ENCIE11_MASK (0x40000U) 296 #define ERM_CR1_ENCIE11_SHIFT (18U) 297 #define ERM_CR1_ENCIE11_WIDTH (1U) 298 #define ERM_CR1_ENCIE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE11_SHIFT)) & ERM_CR1_ENCIE11_MASK) 299 300 #define ERM_CR1_ESCIE11_MASK (0x80000U) 301 #define ERM_CR1_ESCIE11_SHIFT (19U) 302 #define ERM_CR1_ESCIE11_WIDTH (1U) 303 #define ERM_CR1_ESCIE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE11_SHIFT)) & ERM_CR1_ESCIE11_MASK) 304 305 #define ERM_CR1_ENCIE10_MASK (0x400000U) 306 #define ERM_CR1_ENCIE10_SHIFT (22U) 307 #define ERM_CR1_ENCIE10_WIDTH (1U) 308 #define ERM_CR1_ENCIE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE10_SHIFT)) & ERM_CR1_ENCIE10_MASK) 309 310 #define ERM_CR1_ESCIE10_MASK (0x800000U) 311 #define ERM_CR1_ESCIE10_SHIFT (23U) 312 #define ERM_CR1_ESCIE10_WIDTH (1U) 313 #define ERM_CR1_ESCIE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE10_SHIFT)) & ERM_CR1_ESCIE10_MASK) 314 315 #define ERM_CR1_ENCIE9_MASK (0x4000000U) 316 #define ERM_CR1_ENCIE9_SHIFT (26U) 317 #define ERM_CR1_ENCIE9_WIDTH (1U) 318 #define ERM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK) 319 320 #define ERM_CR1_ESCIE9_MASK (0x8000000U) 321 #define ERM_CR1_ESCIE9_SHIFT (27U) 322 #define ERM_CR1_ESCIE9_WIDTH (1U) 323 #define ERM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK) 324 325 #define ERM_CR1_ENCIE8_MASK (0x40000000U) 326 #define ERM_CR1_ENCIE8_SHIFT (30U) 327 #define ERM_CR1_ENCIE8_WIDTH (1U) 328 #define ERM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK) 329 330 #define ERM_CR1_ESCIE8_MASK (0x80000000U) 331 #define ERM_CR1_ESCIE8_SHIFT (31U) 332 #define ERM_CR1_ESCIE8_WIDTH (1U) 333 #define ERM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK) 334 /*! @} */ 335 336 /*! @name CR2 - ERM Configuration Register 2 */ 337 /*! @{ */ 338 339 #define ERM_CR2_ENCIE19_MASK (0x40000U) 340 #define ERM_CR2_ENCIE19_SHIFT (18U) 341 #define ERM_CR2_ENCIE19_WIDTH (1U) 342 #define ERM_CR2_ENCIE19(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE19_SHIFT)) & ERM_CR2_ENCIE19_MASK) 343 344 #define ERM_CR2_ESCIE19_MASK (0x80000U) 345 #define ERM_CR2_ESCIE19_SHIFT (19U) 346 #define ERM_CR2_ESCIE19_WIDTH (1U) 347 #define ERM_CR2_ESCIE19(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE19_SHIFT)) & ERM_CR2_ESCIE19_MASK) 348 349 #define ERM_CR2_ENCIE18_MASK (0x400000U) 350 #define ERM_CR2_ENCIE18_SHIFT (22U) 351 #define ERM_CR2_ENCIE18_WIDTH (1U) 352 #define ERM_CR2_ENCIE18(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE18_SHIFT)) & ERM_CR2_ENCIE18_MASK) 353 354 #define ERM_CR2_ESCIE18_MASK (0x800000U) 355 #define ERM_CR2_ESCIE18_SHIFT (23U) 356 #define ERM_CR2_ESCIE18_WIDTH (1U) 357 #define ERM_CR2_ESCIE18(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE18_SHIFT)) & ERM_CR2_ESCIE18_MASK) 358 359 #define ERM_CR2_ENCIE17_MASK (0x4000000U) 360 #define ERM_CR2_ENCIE17_SHIFT (26U) 361 #define ERM_CR2_ENCIE17_WIDTH (1U) 362 #define ERM_CR2_ENCIE17(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE17_SHIFT)) & ERM_CR2_ENCIE17_MASK) 363 364 #define ERM_CR2_ESCIE17_MASK (0x8000000U) 365 #define ERM_CR2_ESCIE17_SHIFT (27U) 366 #define ERM_CR2_ESCIE17_WIDTH (1U) 367 #define ERM_CR2_ESCIE17(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE17_SHIFT)) & ERM_CR2_ESCIE17_MASK) 368 369 #define ERM_CR2_ENCIE16_MASK (0x40000000U) 370 #define ERM_CR2_ENCIE16_SHIFT (30U) 371 #define ERM_CR2_ENCIE16_WIDTH (1U) 372 #define ERM_CR2_ENCIE16(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE16_SHIFT)) & ERM_CR2_ENCIE16_MASK) 373 374 #define ERM_CR2_ESCIE16_MASK (0x80000000U) 375 #define ERM_CR2_ESCIE16_SHIFT (31U) 376 #define ERM_CR2_ESCIE16_WIDTH (1U) 377 #define ERM_CR2_ESCIE16(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE16_SHIFT)) & ERM_CR2_ESCIE16_MASK) 378 /*! @} */ 379 380 /*! @name SR0 - ERM Status Register 0 */ 381 /*! @{ */ 382 383 #define ERM_SR0_NCE7_MASK (0x4U) 384 #define ERM_SR0_NCE7_SHIFT (2U) 385 #define ERM_SR0_NCE7_WIDTH (1U) 386 #define ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK) 387 388 #define ERM_SR0_SBC7_MASK (0x8U) 389 #define ERM_SR0_SBC7_SHIFT (3U) 390 #define ERM_SR0_SBC7_WIDTH (1U) 391 #define ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK) 392 393 #define ERM_SR0_NCE6_MASK (0x40U) 394 #define ERM_SR0_NCE6_SHIFT (6U) 395 #define ERM_SR0_NCE6_WIDTH (1U) 396 #define ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK) 397 398 #define ERM_SR0_SBC6_MASK (0x80U) 399 #define ERM_SR0_SBC6_SHIFT (7U) 400 #define ERM_SR0_SBC6_WIDTH (1U) 401 #define ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK) 402 403 #define ERM_SR0_NCE5_MASK (0x400U) 404 #define ERM_SR0_NCE5_SHIFT (10U) 405 #define ERM_SR0_NCE5_WIDTH (1U) 406 #define ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK) 407 408 #define ERM_SR0_SBC5_MASK (0x800U) 409 #define ERM_SR0_SBC5_SHIFT (11U) 410 #define ERM_SR0_SBC5_WIDTH (1U) 411 #define ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK) 412 413 #define ERM_SR0_NCE4_MASK (0x4000U) 414 #define ERM_SR0_NCE4_SHIFT (14U) 415 #define ERM_SR0_NCE4_WIDTH (1U) 416 #define ERM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK) 417 418 #define ERM_SR0_SBC4_MASK (0x8000U) 419 #define ERM_SR0_SBC4_SHIFT (15U) 420 #define ERM_SR0_SBC4_WIDTH (1U) 421 #define ERM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK) 422 423 #define ERM_SR0_NCE3_MASK (0x40000U) 424 #define ERM_SR0_NCE3_SHIFT (18U) 425 #define ERM_SR0_NCE3_WIDTH (1U) 426 #define ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK) 427 428 #define ERM_SR0_SBC3_MASK (0x80000U) 429 #define ERM_SR0_SBC3_SHIFT (19U) 430 #define ERM_SR0_SBC3_WIDTH (1U) 431 #define ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK) 432 433 #define ERM_SR0_NCE2_MASK (0x400000U) 434 #define ERM_SR0_NCE2_SHIFT (22U) 435 #define ERM_SR0_NCE2_WIDTH (1U) 436 #define ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK) 437 438 #define ERM_SR0_SBC2_MASK (0x800000U) 439 #define ERM_SR0_SBC2_SHIFT (23U) 440 #define ERM_SR0_SBC2_WIDTH (1U) 441 #define ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK) 442 443 #define ERM_SR0_NCE1_MASK (0x4000000U) 444 #define ERM_SR0_NCE1_SHIFT (26U) 445 #define ERM_SR0_NCE1_WIDTH (1U) 446 #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) 447 448 #define ERM_SR0_SBC1_MASK (0x8000000U) 449 #define ERM_SR0_SBC1_SHIFT (27U) 450 #define ERM_SR0_SBC1_WIDTH (1U) 451 #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) 452 453 #define ERM_SR0_NCE0_MASK (0x40000000U) 454 #define ERM_SR0_NCE0_SHIFT (30U) 455 #define ERM_SR0_NCE0_WIDTH (1U) 456 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) 457 458 #define ERM_SR0_SBC0_MASK (0x80000000U) 459 #define ERM_SR0_SBC0_SHIFT (31U) 460 #define ERM_SR0_SBC0_WIDTH (1U) 461 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) 462 /*! @} */ 463 464 /*! @name SR1 - ERM Status Register 1 */ 465 /*! @{ */ 466 467 #define ERM_SR1_NCE15_MASK (0x4U) 468 #define ERM_SR1_NCE15_SHIFT (2U) 469 #define ERM_SR1_NCE15_WIDTH (1U) 470 #define ERM_SR1_NCE15(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE15_SHIFT)) & ERM_SR1_NCE15_MASK) 471 472 #define ERM_SR1_SBC15_MASK (0x8U) 473 #define ERM_SR1_SBC15_SHIFT (3U) 474 #define ERM_SR1_SBC15_WIDTH (1U) 475 #define ERM_SR1_SBC15(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC15_SHIFT)) & ERM_SR1_SBC15_MASK) 476 477 #define ERM_SR1_NCE14_MASK (0x40U) 478 #define ERM_SR1_NCE14_SHIFT (6U) 479 #define ERM_SR1_NCE14_WIDTH (1U) 480 #define ERM_SR1_NCE14(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE14_SHIFT)) & ERM_SR1_NCE14_MASK) 481 482 #define ERM_SR1_SBC14_MASK (0x80U) 483 #define ERM_SR1_SBC14_SHIFT (7U) 484 #define ERM_SR1_SBC14_WIDTH (1U) 485 #define ERM_SR1_SBC14(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC14_SHIFT)) & ERM_SR1_SBC14_MASK) 486 487 #define ERM_SR1_NCE13_MASK (0x400U) 488 #define ERM_SR1_NCE13_SHIFT (10U) 489 #define ERM_SR1_NCE13_WIDTH (1U) 490 #define ERM_SR1_NCE13(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE13_SHIFT)) & ERM_SR1_NCE13_MASK) 491 492 #define ERM_SR1_SBC13_MASK (0x800U) 493 #define ERM_SR1_SBC13_SHIFT (11U) 494 #define ERM_SR1_SBC13_WIDTH (1U) 495 #define ERM_SR1_SBC13(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC13_SHIFT)) & ERM_SR1_SBC13_MASK) 496 497 #define ERM_SR1_NCE12_MASK (0x4000U) 498 #define ERM_SR1_NCE12_SHIFT (14U) 499 #define ERM_SR1_NCE12_WIDTH (1U) 500 #define ERM_SR1_NCE12(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE12_SHIFT)) & ERM_SR1_NCE12_MASK) 501 502 #define ERM_SR1_SBC12_MASK (0x8000U) 503 #define ERM_SR1_SBC12_SHIFT (15U) 504 #define ERM_SR1_SBC12_WIDTH (1U) 505 #define ERM_SR1_SBC12(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC12_SHIFT)) & ERM_SR1_SBC12_MASK) 506 507 #define ERM_SR1_NCE11_MASK (0x40000U) 508 #define ERM_SR1_NCE11_SHIFT (18U) 509 #define ERM_SR1_NCE11_WIDTH (1U) 510 #define ERM_SR1_NCE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE11_SHIFT)) & ERM_SR1_NCE11_MASK) 511 512 #define ERM_SR1_SBC11_MASK (0x80000U) 513 #define ERM_SR1_SBC11_SHIFT (19U) 514 #define ERM_SR1_SBC11_WIDTH (1U) 515 #define ERM_SR1_SBC11(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC11_SHIFT)) & ERM_SR1_SBC11_MASK) 516 517 #define ERM_SR1_NCE10_MASK (0x400000U) 518 #define ERM_SR1_NCE10_SHIFT (22U) 519 #define ERM_SR1_NCE10_WIDTH (1U) 520 #define ERM_SR1_NCE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE10_SHIFT)) & ERM_SR1_NCE10_MASK) 521 522 #define ERM_SR1_SBC10_MASK (0x800000U) 523 #define ERM_SR1_SBC10_SHIFT (23U) 524 #define ERM_SR1_SBC10_WIDTH (1U) 525 #define ERM_SR1_SBC10(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC10_SHIFT)) & ERM_SR1_SBC10_MASK) 526 527 #define ERM_SR1_NCE9_MASK (0x4000000U) 528 #define ERM_SR1_NCE9_SHIFT (26U) 529 #define ERM_SR1_NCE9_WIDTH (1U) 530 #define ERM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK) 531 532 #define ERM_SR1_SBC9_MASK (0x8000000U) 533 #define ERM_SR1_SBC9_SHIFT (27U) 534 #define ERM_SR1_SBC9_WIDTH (1U) 535 #define ERM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK) 536 537 #define ERM_SR1_NCE8_MASK (0x40000000U) 538 #define ERM_SR1_NCE8_SHIFT (30U) 539 #define ERM_SR1_NCE8_WIDTH (1U) 540 #define ERM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK) 541 542 #define ERM_SR1_SBC8_MASK (0x80000000U) 543 #define ERM_SR1_SBC8_SHIFT (31U) 544 #define ERM_SR1_SBC8_WIDTH (1U) 545 #define ERM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK) 546 /*! @} */ 547 548 /*! @name SR2 - ERM Status Register 2 */ 549 /*! @{ */ 550 551 #define ERM_SR2_NCE19_MASK (0x40000U) 552 #define ERM_SR2_NCE19_SHIFT (18U) 553 #define ERM_SR2_NCE19_WIDTH (1U) 554 #define ERM_SR2_NCE19(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE19_SHIFT)) & ERM_SR2_NCE19_MASK) 555 556 #define ERM_SR2_SBC19_MASK (0x80000U) 557 #define ERM_SR2_SBC19_SHIFT (19U) 558 #define ERM_SR2_SBC19_WIDTH (1U) 559 #define ERM_SR2_SBC19(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC19_SHIFT)) & ERM_SR2_SBC19_MASK) 560 561 #define ERM_SR2_NCE18_MASK (0x400000U) 562 #define ERM_SR2_NCE18_SHIFT (22U) 563 #define ERM_SR2_NCE18_WIDTH (1U) 564 #define ERM_SR2_NCE18(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE18_SHIFT)) & ERM_SR2_NCE18_MASK) 565 566 #define ERM_SR2_SBC18_MASK (0x800000U) 567 #define ERM_SR2_SBC18_SHIFT (23U) 568 #define ERM_SR2_SBC18_WIDTH (1U) 569 #define ERM_SR2_SBC18(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC18_SHIFT)) & ERM_SR2_SBC18_MASK) 570 571 #define ERM_SR2_NCE17_MASK (0x4000000U) 572 #define ERM_SR2_NCE17_SHIFT (26U) 573 #define ERM_SR2_NCE17_WIDTH (1U) 574 #define ERM_SR2_NCE17(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE17_SHIFT)) & ERM_SR2_NCE17_MASK) 575 576 #define ERM_SR2_SBC17_MASK (0x8000000U) 577 #define ERM_SR2_SBC17_SHIFT (27U) 578 #define ERM_SR2_SBC17_WIDTH (1U) 579 #define ERM_SR2_SBC17(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC17_SHIFT)) & ERM_SR2_SBC17_MASK) 580 581 #define ERM_SR2_NCE16_MASK (0x40000000U) 582 #define ERM_SR2_NCE16_SHIFT (30U) 583 #define ERM_SR2_NCE16_WIDTH (1U) 584 #define ERM_SR2_NCE16(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE16_SHIFT)) & ERM_SR2_NCE16_MASK) 585 586 #define ERM_SR2_SBC16_MASK (0x80000000U) 587 #define ERM_SR2_SBC16_SHIFT (31U) 588 #define ERM_SR2_SBC16_WIDTH (1U) 589 #define ERM_SR2_SBC16(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC16_SHIFT)) & ERM_SR2_SBC16_MASK) 590 /*! @} */ 591 592 /*! @name EAR0 - ERM Memory 0 Error Address Register */ 593 /*! @{ */ 594 595 #define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) 596 #define ERM_EAR0_EAR_SHIFT (0U) 597 #define ERM_EAR0_EAR_WIDTH (32U) 598 #define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) 599 /*! @} */ 600 601 /*! @name SYN0 - ERM Memory 0 Syndrome Register */ 602 /*! @{ */ 603 604 #define ERM_SYN0_SYNDROME_MASK (0xFF000000U) 605 #define ERM_SYN0_SYNDROME_SHIFT (24U) 606 #define ERM_SYN0_SYNDROME_WIDTH (8U) 607 #define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) 608 /*! @} */ 609 610 /*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ 611 /*! @{ */ 612 613 #define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) 614 #define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) 615 #define ERM_CORR_ERR_CNT0_COUNT_WIDTH (8U) 616 #define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) 617 /*! @} */ 618 619 /*! @name EAR1 - ERM Memory 1 Error Address Register */ 620 /*! @{ */ 621 622 #define ERM_EAR1_EAR_MASK (0xFFFFFFFFU) 623 #define ERM_EAR1_EAR_SHIFT (0U) 624 #define ERM_EAR1_EAR_WIDTH (32U) 625 #define ERM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK) 626 /*! @} */ 627 628 /*! @name SYN1 - ERM Memory 1 Syndrome Register */ 629 /*! @{ */ 630 631 #define ERM_SYN1_SYNDROME_MASK (0xFF000000U) 632 #define ERM_SYN1_SYNDROME_SHIFT (24U) 633 #define ERM_SYN1_SYNDROME_WIDTH (8U) 634 #define ERM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK) 635 /*! @} */ 636 637 /*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ 638 /*! @{ */ 639 640 #define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) 641 #define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) 642 #define ERM_CORR_ERR_CNT1_COUNT_WIDTH (8U) 643 #define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) 644 /*! @} */ 645 646 /*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ 647 /*! @{ */ 648 649 #define ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) 650 #define ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) 651 #define ERM_CORR_ERR_CNT2_COUNT_WIDTH (8U) 652 #define ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK) 653 /*! @} */ 654 655 /*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ 656 /*! @{ */ 657 658 #define ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) 659 #define ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) 660 #define ERM_CORR_ERR_CNT3_COUNT_WIDTH (8U) 661 #define ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK) 662 /*! @} */ 663 664 /*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ 665 /*! @{ */ 666 667 #define ERM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) 668 #define ERM_CORR_ERR_CNT4_COUNT_SHIFT (0U) 669 #define ERM_CORR_ERR_CNT4_COUNT_WIDTH (8U) 670 #define ERM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK) 671 /*! @} */ 672 673 /*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ 674 /*! @{ */ 675 676 #define ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) 677 #define ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) 678 #define ERM_CORR_ERR_CNT5_COUNT_WIDTH (8U) 679 #define ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK) 680 /*! @} */ 681 682 /*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ 683 /*! @{ */ 684 685 #define ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) 686 #define ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) 687 #define ERM_CORR_ERR_CNT6_COUNT_WIDTH (8U) 688 #define ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK) 689 /*! @} */ 690 691 /*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ 692 /*! @{ */ 693 694 #define ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) 695 #define ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) 696 #define ERM_CORR_ERR_CNT7_COUNT_WIDTH (8U) 697 #define ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK) 698 /*! @} */ 699 700 /*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ 701 /*! @{ */ 702 703 #define ERM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) 704 #define ERM_CORR_ERR_CNT8_COUNT_SHIFT (0U) 705 #define ERM_CORR_ERR_CNT8_COUNT_WIDTH (8U) 706 #define ERM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK) 707 /*! @} */ 708 709 /*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ 710 /*! @{ */ 711 712 #define ERM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) 713 #define ERM_CORR_ERR_CNT9_COUNT_SHIFT (0U) 714 #define ERM_CORR_ERR_CNT9_COUNT_WIDTH (8U) 715 #define ERM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK) 716 /*! @} */ 717 718 /*! @name EAR10 - ERM Memory 10 Error Address Register */ 719 /*! @{ */ 720 721 #define ERM_EAR10_EAR_MASK (0xFFFFFFFFU) 722 #define ERM_EAR10_EAR_SHIFT (0U) 723 #define ERM_EAR10_EAR_WIDTH (32U) 724 #define ERM_EAR10_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR10_EAR_SHIFT)) & ERM_EAR10_EAR_MASK) 725 /*! @} */ 726 727 /*! @name SYN10 - ERM Memory 10 Syndrome Register */ 728 /*! @{ */ 729 730 #define ERM_SYN10_SYNDROME_MASK (0xFF000000U) 731 #define ERM_SYN10_SYNDROME_SHIFT (24U) 732 #define ERM_SYN10_SYNDROME_WIDTH (8U) 733 #define ERM_SYN10_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN10_SYNDROME_SHIFT)) & ERM_SYN10_SYNDROME_MASK) 734 /*! @} */ 735 736 /*! @name CORR_ERR_CNT10 - ERM Memory 10 Correctable Error Count Register */ 737 /*! @{ */ 738 739 #define ERM_CORR_ERR_CNT10_COUNT_MASK (0xFFU) 740 #define ERM_CORR_ERR_CNT10_COUNT_SHIFT (0U) 741 #define ERM_CORR_ERR_CNT10_COUNT_WIDTH (8U) 742 #define ERM_CORR_ERR_CNT10_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT10_COUNT_SHIFT)) & ERM_CORR_ERR_CNT10_COUNT_MASK) 743 /*! @} */ 744 745 /*! @name EAR11 - ERM Memory 11 Error Address Register */ 746 /*! @{ */ 747 748 #define ERM_EAR11_EAR_MASK (0xFFFFFFFFU) 749 #define ERM_EAR11_EAR_SHIFT (0U) 750 #define ERM_EAR11_EAR_WIDTH (32U) 751 #define ERM_EAR11_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR11_EAR_SHIFT)) & ERM_EAR11_EAR_MASK) 752 /*! @} */ 753 754 /*! @name SYN11 - ERM Memory 11 Syndrome Register */ 755 /*! @{ */ 756 757 #define ERM_SYN11_SYNDROME_MASK (0xFF000000U) 758 #define ERM_SYN11_SYNDROME_SHIFT (24U) 759 #define ERM_SYN11_SYNDROME_WIDTH (8U) 760 #define ERM_SYN11_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN11_SYNDROME_SHIFT)) & ERM_SYN11_SYNDROME_MASK) 761 /*! @} */ 762 763 /*! @name CORR_ERR_CNT11 - ERM Memory 11 Correctable Error Count Register */ 764 /*! @{ */ 765 766 #define ERM_CORR_ERR_CNT11_COUNT_MASK (0xFFU) 767 #define ERM_CORR_ERR_CNT11_COUNT_SHIFT (0U) 768 #define ERM_CORR_ERR_CNT11_COUNT_WIDTH (8U) 769 #define ERM_CORR_ERR_CNT11_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT11_COUNT_SHIFT)) & ERM_CORR_ERR_CNT11_COUNT_MASK) 770 /*! @} */ 771 772 /*! @name EAR12 - ERM Memory 12 Error Address Register */ 773 /*! @{ */ 774 775 #define ERM_EAR12_EAR_MASK (0xFFFFFFFFU) 776 #define ERM_EAR12_EAR_SHIFT (0U) 777 #define ERM_EAR12_EAR_WIDTH (32U) 778 #define ERM_EAR12_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR12_EAR_SHIFT)) & ERM_EAR12_EAR_MASK) 779 /*! @} */ 780 781 /*! @name SYN12 - ERM Memory 12 Syndrome Register */ 782 /*! @{ */ 783 784 #define ERM_SYN12_SYNDROME_MASK (0xFF000000U) 785 #define ERM_SYN12_SYNDROME_SHIFT (24U) 786 #define ERM_SYN12_SYNDROME_WIDTH (8U) 787 #define ERM_SYN12_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN12_SYNDROME_SHIFT)) & ERM_SYN12_SYNDROME_MASK) 788 /*! @} */ 789 790 /*! @name CORR_ERR_CNT12 - ERM Memory 12 Correctable Error Count Register */ 791 /*! @{ */ 792 793 #define ERM_CORR_ERR_CNT12_COUNT_MASK (0xFFU) 794 #define ERM_CORR_ERR_CNT12_COUNT_SHIFT (0U) 795 #define ERM_CORR_ERR_CNT12_COUNT_WIDTH (8U) 796 #define ERM_CORR_ERR_CNT12_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT12_COUNT_SHIFT)) & ERM_CORR_ERR_CNT12_COUNT_MASK) 797 /*! @} */ 798 799 /*! @name EAR13 - ERM Memory 13 Error Address Register */ 800 /*! @{ */ 801 802 #define ERM_EAR13_EAR_MASK (0xFFFFFFFFU) 803 #define ERM_EAR13_EAR_SHIFT (0U) 804 #define ERM_EAR13_EAR_WIDTH (32U) 805 #define ERM_EAR13_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR13_EAR_SHIFT)) & ERM_EAR13_EAR_MASK) 806 /*! @} */ 807 808 /*! @name SYN13 - ERM Memory 13 Syndrome Register */ 809 /*! @{ */ 810 811 #define ERM_SYN13_SYNDROME_MASK (0xFF000000U) 812 #define ERM_SYN13_SYNDROME_SHIFT (24U) 813 #define ERM_SYN13_SYNDROME_WIDTH (8U) 814 #define ERM_SYN13_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN13_SYNDROME_SHIFT)) & ERM_SYN13_SYNDROME_MASK) 815 /*! @} */ 816 817 /*! @name CORR_ERR_CNT13 - ERM Memory 13 Correctable Error Count Register */ 818 /*! @{ */ 819 820 #define ERM_CORR_ERR_CNT13_COUNT_MASK (0xFFU) 821 #define ERM_CORR_ERR_CNT13_COUNT_SHIFT (0U) 822 #define ERM_CORR_ERR_CNT13_COUNT_WIDTH (8U) 823 #define ERM_CORR_ERR_CNT13_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT13_COUNT_SHIFT)) & ERM_CORR_ERR_CNT13_COUNT_MASK) 824 /*! @} */ 825 826 /*! @name EAR14 - ERM Memory 14 Error Address Register */ 827 /*! @{ */ 828 829 #define ERM_EAR14_EAR_MASK (0xFFFFFFFFU) 830 #define ERM_EAR14_EAR_SHIFT (0U) 831 #define ERM_EAR14_EAR_WIDTH (32U) 832 #define ERM_EAR14_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR14_EAR_SHIFT)) & ERM_EAR14_EAR_MASK) 833 /*! @} */ 834 835 /*! @name SYN14 - ERM Memory 14 Syndrome Register */ 836 /*! @{ */ 837 838 #define ERM_SYN14_SYNDROME_MASK (0xFF000000U) 839 #define ERM_SYN14_SYNDROME_SHIFT (24U) 840 #define ERM_SYN14_SYNDROME_WIDTH (8U) 841 #define ERM_SYN14_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN14_SYNDROME_SHIFT)) & ERM_SYN14_SYNDROME_MASK) 842 /*! @} */ 843 844 /*! @name CORR_ERR_CNT14 - ERM Memory 14 Correctable Error Count Register */ 845 /*! @{ */ 846 847 #define ERM_CORR_ERR_CNT14_COUNT_MASK (0xFFU) 848 #define ERM_CORR_ERR_CNT14_COUNT_SHIFT (0U) 849 #define ERM_CORR_ERR_CNT14_COUNT_WIDTH (8U) 850 #define ERM_CORR_ERR_CNT14_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT14_COUNT_SHIFT)) & ERM_CORR_ERR_CNT14_COUNT_MASK) 851 /*! @} */ 852 853 /*! @name EAR15 - ERM Memory 15 Error Address Register */ 854 /*! @{ */ 855 856 #define ERM_EAR15_EAR_MASK (0xFFFFFFFFU) 857 #define ERM_EAR15_EAR_SHIFT (0U) 858 #define ERM_EAR15_EAR_WIDTH (32U) 859 #define ERM_EAR15_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR15_EAR_SHIFT)) & ERM_EAR15_EAR_MASK) 860 /*! @} */ 861 862 /*! @name SYN15 - ERM Memory 15 Syndrome Register */ 863 /*! @{ */ 864 865 #define ERM_SYN15_SYNDROME_MASK (0xFF000000U) 866 #define ERM_SYN15_SYNDROME_SHIFT (24U) 867 #define ERM_SYN15_SYNDROME_WIDTH (8U) 868 #define ERM_SYN15_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN15_SYNDROME_SHIFT)) & ERM_SYN15_SYNDROME_MASK) 869 /*! @} */ 870 871 /*! @name CORR_ERR_CNT15 - ERM Memory 15 Correctable Error Count Register */ 872 /*! @{ */ 873 874 #define ERM_CORR_ERR_CNT15_COUNT_MASK (0xFFU) 875 #define ERM_CORR_ERR_CNT15_COUNT_SHIFT (0U) 876 #define ERM_CORR_ERR_CNT15_COUNT_WIDTH (8U) 877 #define ERM_CORR_ERR_CNT15_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT15_COUNT_SHIFT)) & ERM_CORR_ERR_CNT15_COUNT_MASK) 878 /*! @} */ 879 880 /*! @name EAR16 - ERM Memory 16 Error Address Register */ 881 /*! @{ */ 882 883 #define ERM_EAR16_EAR_MASK (0xFFFFFFFFU) 884 #define ERM_EAR16_EAR_SHIFT (0U) 885 #define ERM_EAR16_EAR_WIDTH (32U) 886 #define ERM_EAR16_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR16_EAR_SHIFT)) & ERM_EAR16_EAR_MASK) 887 /*! @} */ 888 889 /*! @name SYN16 - ERM Memory 16 Syndrome Register */ 890 /*! @{ */ 891 892 #define ERM_SYN16_SYNDROME_MASK (0xFF000000U) 893 #define ERM_SYN16_SYNDROME_SHIFT (24U) 894 #define ERM_SYN16_SYNDROME_WIDTH (8U) 895 #define ERM_SYN16_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN16_SYNDROME_SHIFT)) & ERM_SYN16_SYNDROME_MASK) 896 /*! @} */ 897 898 /*! @name CORR_ERR_CNT16 - ERM Memory 16 Correctable Error Count Register */ 899 /*! @{ */ 900 901 #define ERM_CORR_ERR_CNT16_COUNT_MASK (0xFFU) 902 #define ERM_CORR_ERR_CNT16_COUNT_SHIFT (0U) 903 #define ERM_CORR_ERR_CNT16_COUNT_WIDTH (8U) 904 #define ERM_CORR_ERR_CNT16_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT16_COUNT_SHIFT)) & ERM_CORR_ERR_CNT16_COUNT_MASK) 905 /*! @} */ 906 907 /*! @name EAR17 - ERM Memory 17 Error Address Register */ 908 /*! @{ */ 909 910 #define ERM_EAR17_EAR_MASK (0xFFFFFFFFU) 911 #define ERM_EAR17_EAR_SHIFT (0U) 912 #define ERM_EAR17_EAR_WIDTH (32U) 913 #define ERM_EAR17_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR17_EAR_SHIFT)) & ERM_EAR17_EAR_MASK) 914 /*! @} */ 915 916 /*! @name CORR_ERR_CNT17 - ERM Memory 17 Correctable Error Count Register */ 917 /*! @{ */ 918 919 #define ERM_CORR_ERR_CNT17_COUNT_MASK (0xFFU) 920 #define ERM_CORR_ERR_CNT17_COUNT_SHIFT (0U) 921 #define ERM_CORR_ERR_CNT17_COUNT_WIDTH (8U) 922 #define ERM_CORR_ERR_CNT17_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT17_COUNT_SHIFT)) & ERM_CORR_ERR_CNT17_COUNT_MASK) 923 /*! @} */ 924 925 /*! @name EAR18 - ERM Memory 18 Error Address Register */ 926 /*! @{ */ 927 928 #define ERM_EAR18_EAR_MASK (0xFFFFFFFFU) 929 #define ERM_EAR18_EAR_SHIFT (0U) 930 #define ERM_EAR18_EAR_WIDTH (32U) 931 #define ERM_EAR18_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR18_EAR_SHIFT)) & ERM_EAR18_EAR_MASK) 932 /*! @} */ 933 934 /*! @name CORR_ERR_CNT18 - ERM Memory 18 Correctable Error Count Register */ 935 /*! @{ */ 936 937 #define ERM_CORR_ERR_CNT18_COUNT_MASK (0xFFU) 938 #define ERM_CORR_ERR_CNT18_COUNT_SHIFT (0U) 939 #define ERM_CORR_ERR_CNT18_COUNT_WIDTH (8U) 940 #define ERM_CORR_ERR_CNT18_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT18_COUNT_SHIFT)) & ERM_CORR_ERR_CNT18_COUNT_MASK) 941 /*! @} */ 942 943 /*! @name EAR19 - ERM Memory 19 Error Address Register */ 944 /*! @{ */ 945 946 #define ERM_EAR19_EAR_MASK (0xFFFFFFFFU) 947 #define ERM_EAR19_EAR_SHIFT (0U) 948 #define ERM_EAR19_EAR_WIDTH (32U) 949 #define ERM_EAR19_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR19_EAR_SHIFT)) & ERM_EAR19_EAR_MASK) 950 /*! @} */ 951 952 /*! @name CORR_ERR_CNT19 - ERM Memory 19 Correctable Error Count Register */ 953 /*! @{ */ 954 955 #define ERM_CORR_ERR_CNT19_COUNT_MASK (0xFFU) 956 #define ERM_CORR_ERR_CNT19_COUNT_SHIFT (0U) 957 #define ERM_CORR_ERR_CNT19_COUNT_WIDTH (8U) 958 #define ERM_CORR_ERR_CNT19_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT19_COUNT_SHIFT)) & ERM_CORR_ERR_CNT19_COUNT_MASK) 959 /*! @} */ 960 961 /*! 962 * @} 963 */ /* end of group ERM_Register_Masks */ 964 965 /*! 966 * @} 967 */ /* end of group ERM_Peripheral_Access_Layer */ 968 969 #endif /* #if !defined(S32K344_ERM_H_) */ 970
