1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144_SIM.h 10 * @version 1.1 11 * @date 2022-02-07 12 * @brief Peripheral Access Layer for S32K144_SIM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144_SIM_H_) /* Check if memory map has not been already included */ 58 #define S32K144_SIM_H_ 59 60 #include "S32K144_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SIM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SIM - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[4]; 74 __IO uint32_t CHIPCTL; /**< Chip Control register, offset: 0x4 */ 75 uint8_t RESERVED_1[4]; 76 __IO uint32_t FTMOPT0; /**< FTM Option Register 0, offset: 0xC */ 77 __IO uint32_t LPOCLKS; /**< LPO Clock Select Register, offset: 0x10 */ 78 uint8_t RESERVED_2[4]; 79 __IO uint32_t ADCOPT; /**< ADC Options Register, offset: 0x18 */ 80 __IO uint32_t FTMOPT1; /**< FTM Option Register 1, offset: 0x1C */ 81 __IO uint32_t MISCTRL0; /**< Miscellaneous control register 0, offset: 0x20 */ 82 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x24 */ 83 uint8_t RESERVED_3[24]; 84 __IO uint32_t PLATCGC; /**< Platform Clock Gating Control Register, offset: 0x40 */ 85 uint8_t RESERVED_4[8]; 86 __I uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x4C */ 87 uint8_t RESERVED_5[4]; 88 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x54 */ 89 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x58 */ 90 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x5C */ 91 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x60 */ 92 uint8_t RESERVED_6[4]; 93 __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x68 */ 94 __IO uint32_t MISCTRL1; /**< Miscellaneous Control register 1, offset: 0x6C */ 95 } SIM_Type, *SIM_MemMapPtr; 96 97 /** Number of instances of the SIM module. */ 98 #define SIM_INSTANCE_COUNT (1u) 99 100 /* SIM - Peripheral instance base addresses */ 101 /** Peripheral SIM base address */ 102 #define IP_SIM_BASE (0x40048000u) 103 /** Peripheral SIM base pointer */ 104 #define IP_SIM ((SIM_Type *)IP_SIM_BASE) 105 /** Array initializer of SIM peripheral base addresses */ 106 #define IP_SIM_BASE_ADDRS { IP_SIM_BASE } 107 /** Array initializer of SIM peripheral base pointers */ 108 #define IP_SIM_BASE_PTRS { IP_SIM } 109 110 /* ---------------------------------------------------------------------------- 111 -- SIM Register Masks 112 ---------------------------------------------------------------------------- */ 113 114 /*! 115 * @addtogroup SIM_Register_Masks SIM Register Masks 116 * @{ 117 */ 118 119 /*! @name CHIPCTL - Chip Control register */ 120 /*! @{ */ 121 122 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK (0xFU) 123 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT (0U) 124 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH (4U) 125 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT)) & SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK) 126 127 #define SIM_CHIPCTL_CLKOUTSEL_MASK (0xF0U) 128 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT (4U) 129 #define SIM_CHIPCTL_CLKOUTSEL_WIDTH (4U) 130 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTSEL_SHIFT)) & SIM_CHIPCTL_CLKOUTSEL_MASK) 131 132 #define SIM_CHIPCTL_CLKOUTDIV_MASK (0x700U) 133 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT (8U) 134 #define SIM_CHIPCTL_CLKOUTDIV_WIDTH (3U) 135 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTDIV_SHIFT)) & SIM_CHIPCTL_CLKOUTDIV_MASK) 136 137 #define SIM_CHIPCTL_CLKOUTEN_MASK (0x800U) 138 #define SIM_CHIPCTL_CLKOUTEN_SHIFT (11U) 139 #define SIM_CHIPCTL_CLKOUTEN_WIDTH (1U) 140 #define SIM_CHIPCTL_CLKOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTEN_SHIFT)) & SIM_CHIPCTL_CLKOUTEN_MASK) 141 142 #define SIM_CHIPCTL_TRACECLK_SEL_MASK (0x1000U) 143 #define SIM_CHIPCTL_TRACECLK_SEL_SHIFT (12U) 144 #define SIM_CHIPCTL_TRACECLK_SEL_WIDTH (1U) 145 #define SIM_CHIPCTL_TRACECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_TRACECLK_SEL_SHIFT)) & SIM_CHIPCTL_TRACECLK_SEL_MASK) 146 147 #define SIM_CHIPCTL_PDB_BB_SEL_MASK (0x2000U) 148 #define SIM_CHIPCTL_PDB_BB_SEL_SHIFT (13U) 149 #define SIM_CHIPCTL_PDB_BB_SEL_WIDTH (1U) 150 #define SIM_CHIPCTL_PDB_BB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_PDB_BB_SEL_SHIFT)) & SIM_CHIPCTL_PDB_BB_SEL_MASK) 151 152 #define SIM_CHIPCTL_ADC_SUPPLY_MASK (0x70000U) 153 #define SIM_CHIPCTL_ADC_SUPPLY_SHIFT (16U) 154 #define SIM_CHIPCTL_ADC_SUPPLY_WIDTH (3U) 155 #define SIM_CHIPCTL_ADC_SUPPLY(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_ADC_SUPPLY_SHIFT)) & SIM_CHIPCTL_ADC_SUPPLY_MASK) 156 157 #define SIM_CHIPCTL_ADC_SUPPLYEN_MASK (0x80000U) 158 #define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT (19U) 159 #define SIM_CHIPCTL_ADC_SUPPLYEN_WIDTH (1U) 160 #define SIM_CHIPCTL_ADC_SUPPLYEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT)) & SIM_CHIPCTL_ADC_SUPPLYEN_MASK) 161 162 #define SIM_CHIPCTL_SRAMU_RETEN_MASK (0x100000U) 163 #define SIM_CHIPCTL_SRAMU_RETEN_SHIFT (20U) 164 #define SIM_CHIPCTL_SRAMU_RETEN_WIDTH (1U) 165 #define SIM_CHIPCTL_SRAMU_RETEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_SRAMU_RETEN_SHIFT)) & SIM_CHIPCTL_SRAMU_RETEN_MASK) 166 167 #define SIM_CHIPCTL_SRAML_RETEN_MASK (0x200000U) 168 #define SIM_CHIPCTL_SRAML_RETEN_SHIFT (21U) 169 #define SIM_CHIPCTL_SRAML_RETEN_WIDTH (1U) 170 #define SIM_CHIPCTL_SRAML_RETEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_SRAML_RETEN_SHIFT)) & SIM_CHIPCTL_SRAML_RETEN_MASK) 171 /*! @} */ 172 173 /*! @name FTMOPT0 - FTM Option Register 0 */ 174 /*! @{ */ 175 176 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK (0x7U) 177 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT (0U) 178 #define SIM_FTMOPT0_FTM0FLTxSEL_WIDTH (3U) 179 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM0FLTxSEL_MASK) 180 181 #define SIM_FTMOPT0_FTM1FLTxSEL_MASK (0x70U) 182 #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT (4U) 183 #define SIM_FTMOPT0_FTM1FLTxSEL_WIDTH (3U) 184 #define SIM_FTMOPT0_FTM1FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM1FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM1FLTxSEL_MASK) 185 186 #define SIM_FTMOPT0_FTM2FLTxSEL_MASK (0x700U) 187 #define SIM_FTMOPT0_FTM2FLTxSEL_SHIFT (8U) 188 #define SIM_FTMOPT0_FTM2FLTxSEL_WIDTH (3U) 189 #define SIM_FTMOPT0_FTM2FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM2FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM2FLTxSEL_MASK) 190 191 #define SIM_FTMOPT0_FTM3FLTxSEL_MASK (0x7000U) 192 #define SIM_FTMOPT0_FTM3FLTxSEL_SHIFT (12U) 193 #define SIM_FTMOPT0_FTM3FLTxSEL_WIDTH (3U) 194 #define SIM_FTMOPT0_FTM3FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM3FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM3FLTxSEL_MASK) 195 196 #define SIM_FTMOPT0_FTM0CLKSEL_MASK (0x3000000U) 197 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT (24U) 198 #define SIM_FTMOPT0_FTM0CLKSEL_WIDTH (2U) 199 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM0CLKSEL_MASK) 200 201 #define SIM_FTMOPT0_FTM1CLKSEL_MASK (0xC000000U) 202 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT (26U) 203 #define SIM_FTMOPT0_FTM1CLKSEL_WIDTH (2U) 204 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM1CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM1CLKSEL_MASK) 205 206 #define SIM_FTMOPT0_FTM2CLKSEL_MASK (0x30000000U) 207 #define SIM_FTMOPT0_FTM2CLKSEL_SHIFT (28U) 208 #define SIM_FTMOPT0_FTM2CLKSEL_WIDTH (2U) 209 #define SIM_FTMOPT0_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM2CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM2CLKSEL_MASK) 210 211 #define SIM_FTMOPT0_FTM3CLKSEL_MASK (0xC0000000U) 212 #define SIM_FTMOPT0_FTM3CLKSEL_SHIFT (30U) 213 #define SIM_FTMOPT0_FTM3CLKSEL_WIDTH (2U) 214 #define SIM_FTMOPT0_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM3CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM3CLKSEL_MASK) 215 /*! @} */ 216 217 /*! @name LPOCLKS - LPO Clock Select Register */ 218 /*! @{ */ 219 220 #define SIM_LPOCLKS_LPO1KCLKEN_MASK (0x1U) 221 #define SIM_LPOCLKS_LPO1KCLKEN_SHIFT (0U) 222 #define SIM_LPOCLKS_LPO1KCLKEN_WIDTH (1U) 223 #define SIM_LPOCLKS_LPO1KCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_LPO1KCLKEN_SHIFT)) & SIM_LPOCLKS_LPO1KCLKEN_MASK) 224 225 #define SIM_LPOCLKS_LPO32KCLKEN_MASK (0x2U) 226 #define SIM_LPOCLKS_LPO32KCLKEN_SHIFT (1U) 227 #define SIM_LPOCLKS_LPO32KCLKEN_WIDTH (1U) 228 #define SIM_LPOCLKS_LPO32KCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_LPO32KCLKEN_SHIFT)) & SIM_LPOCLKS_LPO32KCLKEN_MASK) 229 230 #define SIM_LPOCLKS_LPOCLKSEL_MASK (0xCU) 231 #define SIM_LPOCLKS_LPOCLKSEL_SHIFT (2U) 232 #define SIM_LPOCLKS_LPOCLKSEL_WIDTH (2U) 233 #define SIM_LPOCLKS_LPOCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_LPOCLKSEL_SHIFT)) & SIM_LPOCLKS_LPOCLKSEL_MASK) 234 235 #define SIM_LPOCLKS_RTCCLKSEL_MASK (0x30U) 236 #define SIM_LPOCLKS_RTCCLKSEL_SHIFT (4U) 237 #define SIM_LPOCLKS_RTCCLKSEL_WIDTH (2U) 238 #define SIM_LPOCLKS_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_LPOCLKS_RTCCLKSEL_SHIFT)) & SIM_LPOCLKS_RTCCLKSEL_MASK) 239 /*! @} */ 240 241 /*! @name ADCOPT - ADC Options Register */ 242 /*! @{ */ 243 244 #define SIM_ADCOPT_ADC0TRGSEL_MASK (0x1U) 245 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT (0U) 246 #define SIM_ADCOPT_ADC0TRGSEL_WIDTH (1U) 247 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK) 248 249 #define SIM_ADCOPT_ADC0SWPRETRG_MASK (0xEU) 250 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT (1U) 251 #define SIM_ADCOPT_ADC0SWPRETRG_WIDTH (3U) 252 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0SWPRETRG_SHIFT)) & SIM_ADCOPT_ADC0SWPRETRG_MASK) 253 254 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK (0x30U) 255 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT (4U) 256 #define SIM_ADCOPT_ADC0PRETRGSEL_WIDTH (2U) 257 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK) 258 259 #define SIM_ADCOPT_ADC1TRGSEL_MASK (0x100U) 260 #define SIM_ADCOPT_ADC1TRGSEL_SHIFT (8U) 261 #define SIM_ADCOPT_ADC1TRGSEL_WIDTH (1U) 262 #define SIM_ADCOPT_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC1TRGSEL_SHIFT)) & SIM_ADCOPT_ADC1TRGSEL_MASK) 263 264 #define SIM_ADCOPT_ADC1SWPRETRG_MASK (0xE00U) 265 #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT (9U) 266 #define SIM_ADCOPT_ADC1SWPRETRG_WIDTH (3U) 267 #define SIM_ADCOPT_ADC1SWPRETRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC1SWPRETRG_SHIFT)) & SIM_ADCOPT_ADC1SWPRETRG_MASK) 268 269 #define SIM_ADCOPT_ADC1PRETRGSEL_MASK (0x3000U) 270 #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT (12U) 271 #define SIM_ADCOPT_ADC1PRETRGSEL_WIDTH (2U) 272 #define SIM_ADCOPT_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC1PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC1PRETRGSEL_MASK) 273 /*! @} */ 274 275 /*! @name FTMOPT1 - FTM Option Register 1 */ 276 /*! @{ */ 277 278 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK (0x1U) 279 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT (0U) 280 #define SIM_FTMOPT1_FTM0SYNCBIT_WIDTH (1U) 281 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM0SYNCBIT_MASK) 282 283 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK (0x2U) 284 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT (1U) 285 #define SIM_FTMOPT1_FTM1SYNCBIT_WIDTH (1U) 286 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM1SYNCBIT_MASK) 287 288 #define SIM_FTMOPT1_FTM2SYNCBIT_MASK (0x4U) 289 #define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT (2U) 290 #define SIM_FTMOPT1_FTM2SYNCBIT_WIDTH (1U) 291 #define SIM_FTMOPT1_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM2SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM2SYNCBIT_MASK) 292 293 #define SIM_FTMOPT1_FTM3SYNCBIT_MASK (0x8U) 294 #define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT (3U) 295 #define SIM_FTMOPT1_FTM3SYNCBIT_WIDTH (1U) 296 #define SIM_FTMOPT1_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM3SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM3SYNCBIT_MASK) 297 298 #define SIM_FTMOPT1_FTM1CH0SEL_MASK (0x30U) 299 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT (4U) 300 #define SIM_FTMOPT1_FTM1CH0SEL_WIDTH (2U) 301 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1CH0SEL_SHIFT)) & SIM_FTMOPT1_FTM1CH0SEL_MASK) 302 303 #define SIM_FTMOPT1_FTM2CH0SEL_MASK (0xC0U) 304 #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT (6U) 305 #define SIM_FTMOPT1_FTM2CH0SEL_WIDTH (2U) 306 #define SIM_FTMOPT1_FTM2CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM2CH0SEL_SHIFT)) & SIM_FTMOPT1_FTM2CH0SEL_MASK) 307 308 #define SIM_FTMOPT1_FTM2CH1SEL_MASK (0x100U) 309 #define SIM_FTMOPT1_FTM2CH1SEL_SHIFT (8U) 310 #define SIM_FTMOPT1_FTM2CH1SEL_WIDTH (1U) 311 #define SIM_FTMOPT1_FTM2CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM2CH1SEL_SHIFT)) & SIM_FTMOPT1_FTM2CH1SEL_MASK) 312 313 #define SIM_FTMOPT1_FTMGLDOK_MASK (0x8000U) 314 #define SIM_FTMOPT1_FTMGLDOK_SHIFT (15U) 315 #define SIM_FTMOPT1_FTMGLDOK_WIDTH (1U) 316 #define SIM_FTMOPT1_FTMGLDOK(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTMGLDOK_SHIFT)) & SIM_FTMOPT1_FTMGLDOK_MASK) 317 318 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK (0xFF0000U) 319 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT (16U) 320 #define SIM_FTMOPT1_FTM0_OUTSEL_WIDTH (8U) 321 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT)) & SIM_FTMOPT1_FTM0_OUTSEL_MASK) 322 323 #define SIM_FTMOPT1_FTM3_OUTSEL_MASK (0xFF000000U) 324 #define SIM_FTMOPT1_FTM3_OUTSEL_SHIFT (24U) 325 #define SIM_FTMOPT1_FTM3_OUTSEL_WIDTH (8U) 326 #define SIM_FTMOPT1_FTM3_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM3_OUTSEL_SHIFT)) & SIM_FTMOPT1_FTM3_OUTSEL_MASK) 327 /*! @} */ 328 329 /*! @name MISCTRL0 - Miscellaneous control register 0 */ 330 /*! @{ */ 331 332 #define SIM_MISCTRL0_STOP1_MONITOR_MASK (0x200U) 333 #define SIM_MISCTRL0_STOP1_MONITOR_SHIFT (9U) 334 #define SIM_MISCTRL0_STOP1_MONITOR_WIDTH (1U) 335 #define SIM_MISCTRL0_STOP1_MONITOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_STOP1_MONITOR_SHIFT)) & SIM_MISCTRL0_STOP1_MONITOR_MASK) 336 337 #define SIM_MISCTRL0_STOP2_MONITOR_MASK (0x400U) 338 #define SIM_MISCTRL0_STOP2_MONITOR_SHIFT (10U) 339 #define SIM_MISCTRL0_STOP2_MONITOR_WIDTH (1U) 340 #define SIM_MISCTRL0_STOP2_MONITOR(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_STOP2_MONITOR_SHIFT)) & SIM_MISCTRL0_STOP2_MONITOR_MASK) 341 342 #define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK (0x10000U) 343 #define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT (16U) 344 #define SIM_MISCTRL0_FTM0_OBE_CTRL_WIDTH (1U) 345 #define SIM_MISCTRL0_FTM0_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM0_OBE_CTRL_MASK) 346 347 #define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK (0x20000U) 348 #define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT (17U) 349 #define SIM_MISCTRL0_FTM1_OBE_CTRL_WIDTH (1U) 350 #define SIM_MISCTRL0_FTM1_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM1_OBE_CTRL_MASK) 351 352 #define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK (0x40000U) 353 #define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT (18U) 354 #define SIM_MISCTRL0_FTM2_OBE_CTRL_WIDTH (1U) 355 #define SIM_MISCTRL0_FTM2_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM2_OBE_CTRL_MASK) 356 357 #define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK (0x80000U) 358 #define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT (19U) 359 #define SIM_MISCTRL0_FTM3_OBE_CTRL_WIDTH (1U) 360 #define SIM_MISCTRL0_FTM3_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT)) & SIM_MISCTRL0_FTM3_OBE_CTRL_MASK) 361 /*! @} */ 362 363 /*! @name SDID - System Device Identification Register */ 364 /*! @{ */ 365 366 #define SIM_SDID_FEATURES_MASK (0xFFU) 367 #define SIM_SDID_FEATURES_SHIFT (0U) 368 #define SIM_SDID_FEATURES_WIDTH (8U) 369 #define SIM_SDID_FEATURES(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FEATURES_SHIFT)) & SIM_SDID_FEATURES_MASK) 370 371 #define SIM_SDID_PACKAGE_MASK (0xF00U) 372 #define SIM_SDID_PACKAGE_SHIFT (8U) 373 #define SIM_SDID_PACKAGE_WIDTH (4U) 374 #define SIM_SDID_PACKAGE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PACKAGE_SHIFT)) & SIM_SDID_PACKAGE_MASK) 375 376 #define SIM_SDID_REVID_MASK (0xF000U) 377 #define SIM_SDID_REVID_SHIFT (12U) 378 #define SIM_SDID_REVID_WIDTH (4U) 379 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 380 381 #define SIM_SDID_RAMSIZE_MASK (0xF0000U) 382 #define SIM_SDID_RAMSIZE_SHIFT (16U) 383 #define SIM_SDID_RAMSIZE_WIDTH (4U) 384 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_RAMSIZE_SHIFT)) & SIM_SDID_RAMSIZE_MASK) 385 386 #define SIM_SDID_DERIVATE_MASK (0xF00000U) 387 #define SIM_SDID_DERIVATE_SHIFT (20U) 388 #define SIM_SDID_DERIVATE_WIDTH (4U) 389 #define SIM_SDID_DERIVATE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DERIVATE_SHIFT)) & SIM_SDID_DERIVATE_MASK) 390 391 #define SIM_SDID_SUBSERIES_MASK (0xF000000U) 392 #define SIM_SDID_SUBSERIES_SHIFT (24U) 393 #define SIM_SDID_SUBSERIES_WIDTH (4U) 394 #define SIM_SDID_SUBSERIES(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBSERIES_SHIFT)) & SIM_SDID_SUBSERIES_MASK) 395 396 #define SIM_SDID_GENERATION_MASK (0xF0000000U) 397 #define SIM_SDID_GENERATION_SHIFT (28U) 398 #define SIM_SDID_GENERATION_WIDTH (4U) 399 #define SIM_SDID_GENERATION(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_GENERATION_SHIFT)) & SIM_SDID_GENERATION_MASK) 400 /*! @} */ 401 402 /*! @name PLATCGC - Platform Clock Gating Control Register */ 403 /*! @{ */ 404 405 #define SIM_PLATCGC_CGCMSCM_MASK (0x1U) 406 #define SIM_PLATCGC_CGCMSCM_SHIFT (0U) 407 #define SIM_PLATCGC_CGCMSCM_WIDTH (1U) 408 #define SIM_PLATCGC_CGCMSCM(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCMSCM_SHIFT)) & SIM_PLATCGC_CGCMSCM_MASK) 409 410 #define SIM_PLATCGC_CGCMPU_MASK (0x2U) 411 #define SIM_PLATCGC_CGCMPU_SHIFT (1U) 412 #define SIM_PLATCGC_CGCMPU_WIDTH (1U) 413 #define SIM_PLATCGC_CGCMPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCMPU_SHIFT)) & SIM_PLATCGC_CGCMPU_MASK) 414 415 #define SIM_PLATCGC_CGCDMA_MASK (0x4U) 416 #define SIM_PLATCGC_CGCDMA_SHIFT (2U) 417 #define SIM_PLATCGC_CGCDMA_WIDTH (1U) 418 #define SIM_PLATCGC_CGCDMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCDMA_SHIFT)) & SIM_PLATCGC_CGCDMA_MASK) 419 420 #define SIM_PLATCGC_CGCERM_MASK (0x8U) 421 #define SIM_PLATCGC_CGCERM_SHIFT (3U) 422 #define SIM_PLATCGC_CGCERM_WIDTH (1U) 423 #define SIM_PLATCGC_CGCERM(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCERM_SHIFT)) & SIM_PLATCGC_CGCERM_MASK) 424 425 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) 426 #define SIM_PLATCGC_CGCEIM_SHIFT (4U) 427 #define SIM_PLATCGC_CGCEIM_WIDTH (1U) 428 #define SIM_PLATCGC_CGCEIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK) 429 /*! @} */ 430 431 /*! @name FCFG1 - Flash Configuration Register 1 */ 432 /*! @{ */ 433 434 #define SIM_FCFG1_DEPART_MASK (0xF000U) 435 #define SIM_FCFG1_DEPART_SHIFT (12U) 436 #define SIM_FCFG1_DEPART_WIDTH (4U) 437 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) 438 439 #define SIM_FCFG1_EEERAMSIZE_MASK (0xF0000U) 440 #define SIM_FCFG1_EEERAMSIZE_SHIFT (16U) 441 #define SIM_FCFG1_EEERAMSIZE_WIDTH (4U) 442 #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EEERAMSIZE_SHIFT)) & SIM_FCFG1_EEERAMSIZE_MASK) 443 /*! @} */ 444 445 /*! @name UIDH - Unique Identification Register High */ 446 /*! @{ */ 447 448 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) 449 #define SIM_UIDH_UID127_96_SHIFT (0U) 450 #define SIM_UIDH_UID127_96_WIDTH (32U) 451 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK) 452 /*! @} */ 453 454 /*! @name UIDMH - Unique Identification Register Mid-High */ 455 /*! @{ */ 456 457 #define SIM_UIDMH_UID95_64_MASK (0xFFFFFFFFU) 458 #define SIM_UIDMH_UID95_64_SHIFT (0U) 459 #define SIM_UIDMH_UID95_64_WIDTH (32U) 460 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID95_64_SHIFT)) & SIM_UIDMH_UID95_64_MASK) 461 /*! @} */ 462 463 /*! @name UIDML - Unique Identification Register Mid Low */ 464 /*! @{ */ 465 466 #define SIM_UIDML_UID63_32_MASK (0xFFFFFFFFU) 467 #define SIM_UIDML_UID63_32_SHIFT (0U) 468 #define SIM_UIDML_UID63_32_WIDTH (32U) 469 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID63_32_SHIFT)) & SIM_UIDML_UID63_32_MASK) 470 /*! @} */ 471 472 /*! @name UIDL - Unique Identification Register Low */ 473 /*! @{ */ 474 475 #define SIM_UIDL_UID31_0_MASK (0xFFFFFFFFU) 476 #define SIM_UIDL_UID31_0_SHIFT (0U) 477 #define SIM_UIDL_UID31_0_WIDTH (32U) 478 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID31_0_SHIFT)) & SIM_UIDL_UID31_0_MASK) 479 /*! @} */ 480 481 /*! @name CLKDIV4 - System Clock Divider Register 4 */ 482 /*! @{ */ 483 484 #define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U) 485 #define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U) 486 #define SIM_CLKDIV4_TRACEFRAC_WIDTH (1U) 487 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK) 488 489 #define SIM_CLKDIV4_TRACEDIV_MASK (0xEU) 490 #define SIM_CLKDIV4_TRACEDIV_SHIFT (1U) 491 #define SIM_CLKDIV4_TRACEDIV_WIDTH (3U) 492 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK) 493 494 #define SIM_CLKDIV4_TRACEDIVEN_MASK (0x10000000U) 495 #define SIM_CLKDIV4_TRACEDIVEN_SHIFT (28U) 496 #define SIM_CLKDIV4_TRACEDIVEN_WIDTH (1U) 497 #define SIM_CLKDIV4_TRACEDIVEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIVEN_SHIFT)) & SIM_CLKDIV4_TRACEDIVEN_MASK) 498 /*! @} */ 499 500 /*! @name MISCTRL1 - Miscellaneous Control register 1 */ 501 /*! @{ */ 502 503 #define SIM_MISCTRL1_SW_TRG_MASK (0x1U) 504 #define SIM_MISCTRL1_SW_TRG_SHIFT (0U) 505 #define SIM_MISCTRL1_SW_TRG_WIDTH (1U) 506 #define SIM_MISCTRL1_SW_TRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SW_TRG_SHIFT)) & SIM_MISCTRL1_SW_TRG_MASK) 507 /*! @} */ 508 509 /*! 510 * @} 511 */ /* end of group SIM_Register_Masks */ 512 513 /*! 514 * @} 515 */ /* end of group SIM_Peripheral_Access_Layer */ 516 517 #endif /* #if !defined(S32K144_SIM_H_) */ 518
