1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144W_EWM.h 10 * @version 1.4 11 * @date 2022-02-09 12 * @brief Peripheral Access Layer for S32K144W_EWM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144W_EWM_H_) /* Check if memory map has not been already included */ 58 #define S32K144W_EWM_H_ 59 60 #include "S32K144W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EWM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EWM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ 74 __O uint8_t SERV; /**< Service Register, offset: 0x1 */ 75 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ 76 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ 77 uint8_t RESERVED_0[1]; 78 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ 79 } EWM_Type, *EWM_MemMapPtr; 80 81 /** Number of instances of the EWM module. */ 82 #define EWM_INSTANCE_COUNT (1u) 83 84 /* EWM - Peripheral instance base addresses */ 85 /** Peripheral EWM base address */ 86 #define IP_EWM_BASE (0x40061000u) 87 /** Peripheral EWM base pointer */ 88 #define IP_EWM ((EWM_Type *)IP_EWM_BASE) 89 /** Array initializer of EWM peripheral base addresses */ 90 #define IP_EWM_BASE_ADDRS { IP_EWM_BASE } 91 /** Array initializer of EWM peripheral base pointers */ 92 #define IP_EWM_BASE_PTRS { IP_EWM } 93 94 /* ---------------------------------------------------------------------------- 95 -- EWM Register Masks 96 ---------------------------------------------------------------------------- */ 97 98 /*! 99 * @addtogroup EWM_Register_Masks EWM Register Masks 100 * @{ 101 */ 102 103 /*! @name CTRL - Control Register */ 104 /*! @{ */ 105 106 #define EWM_CTRL_EWMEN_MASK (0x1U) 107 #define EWM_CTRL_EWMEN_SHIFT (0U) 108 #define EWM_CTRL_EWMEN_WIDTH (1U) 109 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) 110 111 #define EWM_CTRL_ASSIN_MASK (0x2U) 112 #define EWM_CTRL_ASSIN_SHIFT (1U) 113 #define EWM_CTRL_ASSIN_WIDTH (1U) 114 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) 115 116 #define EWM_CTRL_INEN_MASK (0x4U) 117 #define EWM_CTRL_INEN_SHIFT (2U) 118 #define EWM_CTRL_INEN_WIDTH (1U) 119 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) 120 121 #define EWM_CTRL_INTEN_MASK (0x8U) 122 #define EWM_CTRL_INTEN_SHIFT (3U) 123 #define EWM_CTRL_INTEN_WIDTH (1U) 124 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) 125 /*! @} */ 126 127 /*! @name SERV - Service Register */ 128 /*! @{ */ 129 130 #define EWM_SERV_SERVICE_MASK (0xFFU) 131 #define EWM_SERV_SERVICE_SHIFT (0U) 132 #define EWM_SERV_SERVICE_WIDTH (8U) 133 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) 134 /*! @} */ 135 136 /*! @name CMPL - Compare Low Register */ 137 /*! @{ */ 138 139 #define EWM_CMPL_COMPAREL_MASK (0xFFU) 140 #define EWM_CMPL_COMPAREL_SHIFT (0U) 141 #define EWM_CMPL_COMPAREL_WIDTH (8U) 142 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) 143 /*! @} */ 144 145 /*! @name CMPH - Compare High Register */ 146 /*! @{ */ 147 148 #define EWM_CMPH_COMPAREH_MASK (0xFFU) 149 #define EWM_CMPH_COMPAREH_SHIFT (0U) 150 #define EWM_CMPH_COMPAREH_WIDTH (8U) 151 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) 152 /*! @} */ 153 154 /*! @name CLKPRESCALER - Clock Prescaler Register */ 155 /*! @{ */ 156 157 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) 158 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) 159 #define EWM_CLKPRESCALER_CLK_DIV_WIDTH (8U) 160 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) 161 /*! @} */ 162 163 /*! 164 * @} 165 */ /* end of group EWM_Register_Masks */ 166 167 /*! 168 * @} 169 */ /* end of group EWM_Peripheral_Access_Layer */ 170 171 #endif /* #if !defined(S32K144W_EWM_H_) */ 172
