1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142_CRC.h 10 * @version 1.1 11 * @date 2022-02-01 12 * @brief Peripheral Access Layer for S32K142_CRC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142_CRC_H_) /* Check if memory map has not been already included */ 58 #define S32K142_CRC_H_ 59 60 #include "S32K142_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CRC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CRC - Register Layout Typedef */ 72 typedef struct { 73 union { /* offset: 0x0 */ 74 struct { /* offset: 0x0 */ 75 __IO uint8_t LL; /**< CRC_LL register, offset: 0x0 */ 76 __IO uint8_t LU; /**< CRC_LU register, offset: 0x1 */ 77 __IO uint8_t HL; /**< CRC_HL register, offset: 0x2 */ 78 __IO uint8_t HU; /**< CRC_HU register, offset: 0x3 */ 79 } DATA_8; 80 struct { /* offset: 0x0 */ 81 __IO uint16_t L; /**< CRC_L register, offset: 0x0 */ 82 __IO uint16_t H; /**< CRC_H register, offset: 0x2 */ 83 } DATA_16; 84 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 85 } DATAu; 86 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 87 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 88 } CRC_Type, *CRC_MemMapPtr; 89 90 /** Number of instances of the CRC module. */ 91 #define CRC_INSTANCE_COUNT (1u) 92 93 /* CRC - Peripheral instance base addresses */ 94 /** Peripheral CRC base address */ 95 #define IP_CRC_BASE (0x40032000u) 96 /** Peripheral CRC base pointer */ 97 #define IP_CRC ((CRC_Type *)IP_CRC_BASE) 98 /** Array initializer of CRC peripheral base addresses */ 99 #define IP_CRC_BASE_ADDRS { IP_CRC_BASE } 100 /** Array initializer of CRC peripheral base pointers */ 101 #define IP_CRC_BASE_PTRS { IP_CRC } 102 103 /* ---------------------------------------------------------------------------- 104 -- CRC Register Masks 105 ---------------------------------------------------------------------------- */ 106 107 /*! 108 * @addtogroup CRC_Register_Masks CRC Register Masks 109 * @{ 110 */ 111 112 /*! @name DATA_8_LL - CRC_LL register */ 113 /*! @{ */ 114 #define CRC_DATAu_DATA_8_LL_DATALL_MASK (0xFFU) 115 #define CRC_DATAu_DATA_8_LL_DATALL_SHIFT (0U) 116 #define CRC_DATAu_DATA_8_LL_DATALL_WIDTH (8U) 117 #define CRC_DATAu_DATA_8_LL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAu_DATA_8_LL_DATALL_SHIFT)) & CRC_DATAu_DATA_8_LL_DATALL_MASK) 118 /*! @} */ 119 120 /*! @name DATA_8_LU - CRC_LU register */ 121 /*! @{ */ 122 #define CRC_DATAu_DATA_8_LU_DATALU_MASK (0xFFU) 123 #define CRC_DATAu_DATA_8_LU_DATALU_SHIFT (0U) 124 #define CRC_DATAu_DATA_8_LU_DATALU_WIDTH (8U) 125 #define CRC_DATAu_DATA_8_LU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAu_DATA_8_LU_DATALU_SHIFT)) & CRC_DATAu_DATA_8_LU_DATALU_MASK) 126 /*! @} */ 127 128 /*! @name DATA_8_HL - CRC_HL register */ 129 /*! @{ */ 130 #define CRC_DATAu_DATA_8_HL_DATAHL_MASK (0xFFU) 131 #define CRC_DATAu_DATA_8_HL_DATAHL_SHIFT (0U) 132 #define CRC_DATAu_DATA_8_HL_DATAHL_WIDTH (8U) 133 #define CRC_DATAu_DATA_8_HL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAu_DATA_8_HL_DATAHL_SHIFT)) & CRC_DATAu_DATA_8_HL_DATAHL_MASK) 134 /*! @} */ 135 136 /*! @name DATA_8_HU - CRC_HU register */ 137 /*! @{ */ 138 #define CRC_DATAu_DATA_8_HU_DATAHU_MASK (0xFFU) 139 #define CRC_DATAu_DATA_8_HU_DATAHU_SHIFT (0U) 140 #define CRC_DATAu_DATA_8_HU_DATAHU_WIDTH (8U) 141 #define CRC_DATAu_DATA_8_HU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAu_DATA_8_HU_DATAHU_SHIFT)) & CRC_DATAu_DATA_8_HU_DATAHU_MASK) 142 /*! @} */ 143 144 /*! @name DATA_16_L - CRC_L register */ 145 /*! @{ */ 146 #define CRC_DATAu_DATA_16_L_DATAL_MASK (0xFFFFU) 147 #define CRC_DATAu_DATA_16_L_DATAL_SHIFT (0U) 148 #define CRC_DATAu_DATA_16_L_DATAL_WIDTH (16U) 149 #define CRC_DATAu_DATA_16_L_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAu_DATA_16_L_DATAL_SHIFT)) & CRC_DATAu_DATA_16_L_DATAL_MASK) 150 /*! @} */ 151 152 /*! @name DATA_16_H - CRC_H register */ 153 /*! @{ */ 154 #define CRC_DATAu_DATA_16_H_DATAH_MASK (0xFFFFU) 155 #define CRC_DATAu_DATA_16_H_DATAH_SHIFT (0U) 156 #define CRC_DATAu_DATA_16_H_DATAH_WIDTH (16U) 157 #define CRC_DATAu_DATA_16_H_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAu_DATA_16_H_DATAH_SHIFT)) & CRC_DATAu_DATA_16_H_DATAH_MASK) 158 /*! @} */ 159 160 /*! @name DATA - CRC Data register */ 161 /*! @{ */ 162 163 #define CRC_DATAu_DATA_LL_MASK (0xFFU) 164 #define CRC_DATAu_DATA_LL_SHIFT (0U) 165 #define CRC_DATAu_DATA_LL_WIDTH (8U) 166 #define CRC_DATAu_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATAu_DATA_LL_SHIFT)) & CRC_DATAu_DATA_LL_MASK) 167 168 #define CRC_DATAu_DATA_LU_MASK (0xFF00U) 169 #define CRC_DATAu_DATA_LU_SHIFT (8U) 170 #define CRC_DATAu_DATA_LU_WIDTH (8U) 171 #define CRC_DATAu_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATAu_DATA_LU_SHIFT)) & CRC_DATAu_DATA_LU_MASK) 172 173 #define CRC_DATAu_DATA_HL_MASK (0xFF0000U) 174 #define CRC_DATAu_DATA_HL_SHIFT (16U) 175 #define CRC_DATAu_DATA_HL_WIDTH (8U) 176 #define CRC_DATAu_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATAu_DATA_HL_SHIFT)) & CRC_DATAu_DATA_HL_MASK) 177 178 #define CRC_DATAu_DATA_HU_MASK (0xFF000000U) 179 #define CRC_DATAu_DATA_HU_SHIFT (24U) 180 #define CRC_DATAu_DATA_HU_WIDTH (8U) 181 #define CRC_DATAu_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATAu_DATA_HU_SHIFT)) & CRC_DATAu_DATA_HU_MASK) 182 /*! @} */ 183 184 /*! @name GPOLY - CRC Polynomial register */ 185 /*! @{ */ 186 187 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 188 #define CRC_GPOLY_LOW_SHIFT (0U) 189 #define CRC_GPOLY_LOW_WIDTH (16U) 190 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 191 192 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 193 #define CRC_GPOLY_HIGH_SHIFT (16U) 194 #define CRC_GPOLY_HIGH_WIDTH (16U) 195 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 196 /*! @} */ 197 198 /*! @name CTRL - CRC Control register */ 199 /*! @{ */ 200 201 #define CRC_CTRL_TCRC_MASK (0x1000000U) 202 #define CRC_CTRL_TCRC_SHIFT (24U) 203 #define CRC_CTRL_TCRC_WIDTH (1U) 204 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 205 206 #define CRC_CTRL_WAS_MASK (0x2000000U) 207 #define CRC_CTRL_WAS_SHIFT (25U) 208 #define CRC_CTRL_WAS_WIDTH (1U) 209 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 210 211 #define CRC_CTRL_FXOR_MASK (0x4000000U) 212 #define CRC_CTRL_FXOR_SHIFT (26U) 213 #define CRC_CTRL_FXOR_WIDTH (1U) 214 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 215 216 #define CRC_CTRL_TOTR_MASK (0x30000000U) 217 #define CRC_CTRL_TOTR_SHIFT (28U) 218 #define CRC_CTRL_TOTR_WIDTH (2U) 219 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 220 221 #define CRC_CTRL_TOT_MASK (0xC0000000U) 222 #define CRC_CTRL_TOT_SHIFT (30U) 223 #define CRC_CTRL_TOT_WIDTH (2U) 224 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 225 /*! @} */ 226 227 /*! 228 * @} 229 */ /* end of group CRC_Register_Masks */ 230 231 /*! 232 * @} 233 */ /* end of group CRC_Peripheral_Access_Layer */ 234 235 #endif /* #if !defined(S32K142_CRC_H_) */ 236
