1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_PDB.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_PDB 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_PDB_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_PDB_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PDB Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PDB - Size of Registers Arrays */ 72 #define PDB_DLY_COUNT 8u 73 #define PDB_CH_COUNT 2u 74 #define PDB_POnDLY_COUNT 1u 75 76 /** PDB - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ 79 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ 80 __I uint32_t CNT; /**< Counter register, offset: 0x8 */ 81 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ 82 struct { /* offset: 0x10, array step: 0x28 */ 83 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ 84 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ 85 __IO uint32_t DLY[PDB_DLY_COUNT]; /**< Channel n Delay 0 register..Channel n Delay 7 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ 86 } CH[PDB_CH_COUNT]; 87 uint8_t RESERVED_0[304]; 88 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ 89 union { /* offset: 0x194 */ 90 struct { /* offset: 0x194 */ 91 __IO uint16_t DLY2; /**< PDB_DLY2 register, offset: 0x194 */ 92 __IO uint16_t DLY1; /**< PDB_DLY1 register, offset: 0x196 */ 93 } ACCESS16BIT; 94 __IO uint32_t PODLY; /**< Pulse-Out n Delay register, offset: 0x194 */ 95 } POnDLY[PDB_POnDLY_COUNT]; 96 } PDB_Type, *PDB_MemMapPtr; 97 98 /** Number of instances of the PDB module. */ 99 #define PDB_INSTANCE_COUNT (2u) 100 101 /* PDB - Peripheral instance base addresses */ 102 /** Peripheral PDB0 base address */ 103 #define IP_PDB0_BASE (0x40036000u) 104 /** Peripheral PDB0 base pointer */ 105 #define IP_PDB0 ((PDB_Type *)IP_PDB0_BASE) 106 /** Peripheral PDB1 base address */ 107 #define IP_PDB1_BASE (0x40031000u) 108 /** Peripheral PDB1 base pointer */ 109 #define IP_PDB1 ((PDB_Type *)IP_PDB1_BASE) 110 /** Array initializer of PDB peripheral base addresses */ 111 #define IP_PDB_BASE_ADDRS { IP_PDB0_BASE, IP_PDB1_BASE } 112 /** Array initializer of PDB peripheral base pointers */ 113 #define IP_PDB_BASE_PTRS { IP_PDB0, IP_PDB1 } 114 115 /* ---------------------------------------------------------------------------- 116 -- PDB Register Masks 117 ---------------------------------------------------------------------------- */ 118 119 /*! 120 * @addtogroup PDB_Register_Masks PDB Register Masks 121 * @{ 122 */ 123 124 /*! @name SC - Status and Control register */ 125 /*! @{ */ 126 127 #define PDB_SC_LDOK_MASK (0x1U) 128 #define PDB_SC_LDOK_SHIFT (0U) 129 #define PDB_SC_LDOK_WIDTH (1U) 130 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) 131 132 #define PDB_SC_CONT_MASK (0x2U) 133 #define PDB_SC_CONT_SHIFT (1U) 134 #define PDB_SC_CONT_WIDTH (1U) 135 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) 136 137 #define PDB_SC_MULT_MASK (0xCU) 138 #define PDB_SC_MULT_SHIFT (2U) 139 #define PDB_SC_MULT_WIDTH (2U) 140 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) 141 142 #define PDB_SC_PDBIE_MASK (0x20U) 143 #define PDB_SC_PDBIE_SHIFT (5U) 144 #define PDB_SC_PDBIE_WIDTH (1U) 145 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) 146 147 #define PDB_SC_PDBIF_MASK (0x40U) 148 #define PDB_SC_PDBIF_SHIFT (6U) 149 #define PDB_SC_PDBIF_WIDTH (1U) 150 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) 151 152 #define PDB_SC_PDBEN_MASK (0x80U) 153 #define PDB_SC_PDBEN_SHIFT (7U) 154 #define PDB_SC_PDBEN_WIDTH (1U) 155 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) 156 157 #define PDB_SC_TRGSEL_MASK (0xF00U) 158 #define PDB_SC_TRGSEL_SHIFT (8U) 159 #define PDB_SC_TRGSEL_WIDTH (4U) 160 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) 161 162 #define PDB_SC_PRESCALER_MASK (0x7000U) 163 #define PDB_SC_PRESCALER_SHIFT (12U) 164 #define PDB_SC_PRESCALER_WIDTH (3U) 165 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) 166 167 #define PDB_SC_DMAEN_MASK (0x8000U) 168 #define PDB_SC_DMAEN_SHIFT (15U) 169 #define PDB_SC_DMAEN_WIDTH (1U) 170 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) 171 172 #define PDB_SC_SWTRIG_MASK (0x10000U) 173 #define PDB_SC_SWTRIG_SHIFT (16U) 174 #define PDB_SC_SWTRIG_WIDTH (1U) 175 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) 176 177 #define PDB_SC_PDBEIE_MASK (0x20000U) 178 #define PDB_SC_PDBEIE_SHIFT (17U) 179 #define PDB_SC_PDBEIE_WIDTH (1U) 180 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) 181 182 #define PDB_SC_LDMOD_MASK (0xC0000U) 183 #define PDB_SC_LDMOD_SHIFT (18U) 184 #define PDB_SC_LDMOD_WIDTH (2U) 185 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) 186 /*! @} */ 187 188 /*! @name MOD - Modulus register */ 189 /*! @{ */ 190 191 #define PDB_MOD_MOD_MASK (0xFFFFU) 192 #define PDB_MOD_MOD_SHIFT (0U) 193 #define PDB_MOD_MOD_WIDTH (16U) 194 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) 195 /*! @} */ 196 197 /*! @name CNT - Counter register */ 198 /*! @{ */ 199 200 #define PDB_CNT_CNT_MASK (0xFFFFU) 201 #define PDB_CNT_CNT_SHIFT (0U) 202 #define PDB_CNT_CNT_WIDTH (16U) 203 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) 204 /*! @} */ 205 206 /*! @name IDLY - Interrupt Delay register */ 207 /*! @{ */ 208 209 #define PDB_IDLY_IDLY_MASK (0xFFFFU) 210 #define PDB_IDLY_IDLY_SHIFT (0U) 211 #define PDB_IDLY_IDLY_WIDTH (16U) 212 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) 213 /*! @} */ 214 215 /*! @name C1 - Channel n Control register 1 */ 216 /*! @{ */ 217 218 #define PDB_C1_EN_MASK (0xFFU) 219 #define PDB_C1_EN_SHIFT (0U) 220 #define PDB_C1_EN_WIDTH (8U) 221 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) 222 223 #define PDB_C1_TOS_MASK (0xFF00U) 224 #define PDB_C1_TOS_SHIFT (8U) 225 #define PDB_C1_TOS_WIDTH (8U) 226 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) 227 228 #define PDB_C1_BB_MASK (0xFF0000U) 229 #define PDB_C1_BB_SHIFT (16U) 230 #define PDB_C1_BB_WIDTH (8U) 231 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) 232 /*! @} */ 233 234 /*! @name S - Channel n Status register */ 235 /*! @{ */ 236 237 #define PDB_S_ERR_MASK (0xFFU) 238 #define PDB_S_ERR_SHIFT (0U) 239 #define PDB_S_ERR_WIDTH (8U) 240 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) 241 242 #define PDB_S_CF_MASK (0xFF0000U) 243 #define PDB_S_CF_SHIFT (16U) 244 #define PDB_S_CF_WIDTH (8U) 245 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) 246 /*! @} */ 247 248 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 7 register */ 249 /*! @{ */ 250 251 #define PDB_DLY_DLY_MASK (0xFFFFU) 252 #define PDB_DLY_DLY_SHIFT (0U) 253 #define PDB_DLY_DLY_WIDTH (16U) 254 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) 255 /*! @} */ 256 257 /*! @name POEN - Pulse-Out n Enable register */ 258 /*! @{ */ 259 260 #define PDB_POEN_POEN_MASK (0xFFU) 261 #define PDB_POEN_POEN_SHIFT (0U) 262 #define PDB_POEN_POEN_WIDTH (8U) 263 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) 264 /*! @} */ 265 266 /*! @name POnDLY_PODLY - Pulse-Out n Delay register */ 267 /*! @{ */ 268 269 #define PDB_POnDLY_PODLY_DLY2_MASK (0xFFFFU) 270 #define PDB_POnDLY_PODLY_DLY2_SHIFT (0U) 271 #define PDB_POnDLY_PODLY_DLY2_WIDTH (16U) 272 #define PDB_POnDLY_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_POnDLY_PODLY_DLY2_SHIFT)) & PDB_POnDLY_PODLY_DLY2_MASK) 273 274 #define PDB_POnDLY_PODLY_DLY1_MASK (0xFFFF0000U) 275 #define PDB_POnDLY_PODLY_DLY1_SHIFT (16U) 276 #define PDB_POnDLY_PODLY_DLY1_WIDTH (16U) 277 #define PDB_POnDLY_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_POnDLY_PODLY_DLY1_SHIFT)) & PDB_POnDLY_PODLY_DLY1_MASK) 278 /*! @} */ 279 280 /*! @name POnDLY_ACCESS16BIT_DLY2 - PDB_DLY2 register */ 281 /*! @{ */ 282 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK (0xFFFFU) 283 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT (0U) 284 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_WIDTH (16U) 285 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2(x) (((uint16_t)(((uint16_t)(x)) << PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT)) & PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK) 286 /*! @} */ 287 288 /*! @name POnDLY_ACCESS16BIT_DLY1 - PDB_DLY1 register */ 289 /*! @{ */ 290 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK (0xFFFFU) 291 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT (0U) 292 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_WIDTH (16U) 293 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1(x) (((uint16_t)(((uint16_t)(x)) << PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT)) & PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK) 294 /*! @} */ 295 296 297 298 /*! 299 * @} 300 */ /* end of group PDB_Register_Masks */ 301 302 /*! 303 * @} 304 */ /* end of group PDB_Peripheral_Access_Layer */ 305 306 #endif /* #if !defined(S32K142W_PDB_H_) */ 307
