1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_GPIO.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_GPIO 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_GPIO_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_GPIO_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPIO Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPIO - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 77 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 78 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 79 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 80 } GPIO_Type, *GPIO_MemMapPtr; 81 82 /** Number of instances of the GPIO module. */ 83 #define GPIO_INSTANCE_COUNT (5u) 84 85 /* GPIO - Peripheral instance base addresses */ 86 /** Peripheral PTA base address */ 87 #define IP_PTA_BASE (0x400FF000u) 88 /** Peripheral PTA base pointer */ 89 #define IP_PTA ((GPIO_Type *)IP_PTA_BASE) 90 /** Peripheral PTB base address */ 91 #define IP_PTB_BASE (0x400FF040u) 92 /** Peripheral PTB base pointer */ 93 #define IP_PTB ((GPIO_Type *)IP_PTB_BASE) 94 /** Peripheral PTC base address */ 95 #define IP_PTC_BASE (0x400FF080u) 96 /** Peripheral PTC base pointer */ 97 #define IP_PTC ((GPIO_Type *)IP_PTC_BASE) 98 /** Peripheral PTD base address */ 99 #define IP_PTD_BASE (0x400FF0C0u) 100 /** Peripheral PTD base pointer */ 101 #define IP_PTD ((GPIO_Type *)IP_PTD_BASE) 102 /** Peripheral PTE base address */ 103 #define IP_PTE_BASE (0x400FF100u) 104 /** Peripheral PTE base pointer */ 105 #define IP_PTE ((GPIO_Type *)IP_PTE_BASE) 106 /** Array initializer of GPIO peripheral base addresses */ 107 #define IP_GPIO_BASE_ADDRS { IP_PTA_BASE, IP_PTB_BASE, IP_PTC_BASE, IP_PTD_BASE, IP_PTE_BASE } 108 /** Array initializer of GPIO peripheral base pointers */ 109 #define IP_GPIO_BASE_PTRS { IP_PTA, IP_PTB, IP_PTC, IP_PTD, IP_PTE } 110 111 /* ---------------------------------------------------------------------------- 112 -- GPIO Register Masks 113 ---------------------------------------------------------------------------- */ 114 115 /*! 116 * @addtogroup GPIO_Register_Masks GPIO Register Masks 117 * @{ 118 */ 119 120 /*! @name PDOR - Port Data Output Register */ 121 /*! @{ */ 122 123 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 124 #define GPIO_PDOR_PDO_SHIFT (0U) 125 #define GPIO_PDOR_PDO_WIDTH (32U) 126 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 127 /*! @} */ 128 129 /*! @name PSOR - Port Set Output Register */ 130 /*! @{ */ 131 132 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 133 #define GPIO_PSOR_PTSO_SHIFT (0U) 134 #define GPIO_PSOR_PTSO_WIDTH (32U) 135 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 136 /*! @} */ 137 138 /*! @name PCOR - Port Clear Output Register */ 139 /*! @{ */ 140 141 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 142 #define GPIO_PCOR_PTCO_SHIFT (0U) 143 #define GPIO_PCOR_PTCO_WIDTH (32U) 144 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 145 /*! @} */ 146 147 /*! @name PTOR - Port Toggle Output Register */ 148 /*! @{ */ 149 150 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 151 #define GPIO_PTOR_PTTO_SHIFT (0U) 152 #define GPIO_PTOR_PTTO_WIDTH (32U) 153 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 154 /*! @} */ 155 156 /*! @name PDIR - Port Data Input Register */ 157 /*! @{ */ 158 159 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 160 #define GPIO_PDIR_PDI_SHIFT (0U) 161 #define GPIO_PDIR_PDI_WIDTH (32U) 162 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 163 /*! @} */ 164 165 /*! @name PDDR - Port Data Direction Register */ 166 /*! @{ */ 167 168 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 169 #define GPIO_PDDR_PDD_SHIFT (0U) 170 #define GPIO_PDDR_PDD_WIDTH (32U) 171 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 172 /*! @} */ 173 174 /*! @name PIDR - Port Input Disable Register */ 175 /*! @{ */ 176 177 #define GPIO_PIDR_PID_MASK (0xFFFFFFFFU) 178 #define GPIO_PIDR_PID_SHIFT (0U) 179 #define GPIO_PIDR_PID_WIDTH (32U) 180 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID_SHIFT)) & GPIO_PIDR_PID_MASK) 181 /*! @} */ 182 183 /*! 184 * @} 185 */ /* end of group GPIO_Register_Masks */ 186 187 /*! 188 * @} 189 */ /* end of group GPIO_Peripheral_Access_Layer */ 190 191 #endif /* #if !defined(S32K142W_GPIO_H_) */ 192
