1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_DMA.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_DMA 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_DMA_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_DMA_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMA Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMA - Size of Registers Arrays */ 72 #define DMA_DCHPRI_COUNT 16u 73 #define DMA_TCD_COUNT 16u 74 75 /** DMA - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t CR; /**< Control, offset: 0x0 */ 78 __I uint32_t ES; /**< Error Status, offset: 0x4 */ 79 uint8_t RESERVED_0[4]; 80 __IO uint32_t ERQ; /**< Enable Request, offset: 0xC */ 81 uint8_t RESERVED_1[4]; 82 __IO uint32_t EEI; /**< Enable Error Interrupt, offset: 0x14 */ 83 __O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */ 84 __O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */ 85 __O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */ 86 __O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */ 87 __O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */ 88 __O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */ 89 __O uint8_t CERR; /**< Clear Error, offset: 0x1E */ 90 __O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */ 91 uint8_t RESERVED_2[4]; 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ 93 uint8_t RESERVED_3[4]; 94 __IO uint32_t ERR; /**< Error, offset: 0x2C */ 95 uint8_t RESERVED_4[4]; 96 __I uint32_t HRS; /**< Hardware Request Status, offset: 0x34 */ 97 uint8_t RESERVED_5[12]; 98 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop, offset: 0x44 */ 99 uint8_t RESERVED_6[184]; 100 __IO uint8_t DCHPRI[DMA_DCHPRI_COUNT]; /**< Channel Priority, array offset: 0x100, array step: 0x1 */ 101 uint8_t RESERVED_7[3824]; 102 struct { /* offset: 0x1000, array step: 0x20 */ 103 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ 104 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ 105 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ 106 union { /* offset: 0x1008, array step: 0x20 */ 107 __IO uint32_t MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ 108 __IO uint32_t MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ 109 __IO uint32_t MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ 110 } NBYTES; 111 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ 112 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ 113 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ 114 union { /* offset: 0x1016, array step: 0x20 */ 115 __IO uint16_t ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ 116 __IO uint16_t ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ 117 } CITER; 118 __IO uint32_t DLASTSGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ 119 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ 120 union { /* offset: 0x101E, array step: 0x20 */ 121 __IO uint16_t ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ 122 __IO uint16_t ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ 123 } BITER; 124 } TCD[DMA_TCD_COUNT]; 125 } DMA_Type, *DMA_MemMapPtr; 126 127 /** Number of instances of the DMA module. */ 128 #define DMA_INSTANCE_COUNT (1u) 129 130 /* DMA - Peripheral instance base addresses */ 131 /** Peripheral DMA base address */ 132 #define IP_DMA_BASE (0x40008000u) 133 /** Peripheral DMA base pointer */ 134 #define IP_DMA ((DMA_Type *)IP_DMA_BASE) 135 /** Array initializer of DMA peripheral base addresses */ 136 #define IP_DMA_BASE_ADDRS { IP_DMA_BASE } 137 /** Array initializer of DMA peripheral base pointers */ 138 #define IP_DMA_BASE_PTRS { IP_DMA } 139 140 /* ---------------------------------------------------------------------------- 141 -- DMA Register Masks 142 ---------------------------------------------------------------------------- */ 143 144 /*! 145 * @addtogroup DMA_Register_Masks DMA Register Masks 146 * @{ 147 */ 148 149 /*! @name CR - Control */ 150 /*! @{ */ 151 152 #define DMA_CR_EDBG_MASK (0x2U) 153 #define DMA_CR_EDBG_SHIFT (1U) 154 #define DMA_CR_EDBG_WIDTH (1U) 155 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) 156 157 #define DMA_CR_ERCA_MASK (0x4U) 158 #define DMA_CR_ERCA_SHIFT (2U) 159 #define DMA_CR_ERCA_WIDTH (1U) 160 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) 161 162 #define DMA_CR_HOE_MASK (0x10U) 163 #define DMA_CR_HOE_SHIFT (4U) 164 #define DMA_CR_HOE_WIDTH (1U) 165 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) 166 167 #define DMA_CR_HALT_MASK (0x20U) 168 #define DMA_CR_HALT_SHIFT (5U) 169 #define DMA_CR_HALT_WIDTH (1U) 170 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) 171 172 #define DMA_CR_CLM_MASK (0x40U) 173 #define DMA_CR_CLM_SHIFT (6U) 174 #define DMA_CR_CLM_WIDTH (1U) 175 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) 176 177 #define DMA_CR_EMLM_MASK (0x80U) 178 #define DMA_CR_EMLM_SHIFT (7U) 179 #define DMA_CR_EMLM_WIDTH (1U) 180 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) 181 182 #define DMA_CR_ECX_MASK (0x10000U) 183 #define DMA_CR_ECX_SHIFT (16U) 184 #define DMA_CR_ECX_WIDTH (1U) 185 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) 186 187 #define DMA_CR_CX_MASK (0x20000U) 188 #define DMA_CR_CX_SHIFT (17U) 189 #define DMA_CR_CX_WIDTH (1U) 190 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) 191 192 #define DMA_CR_ACTIVE_MASK (0x80000000U) 193 #define DMA_CR_ACTIVE_SHIFT (31U) 194 #define DMA_CR_ACTIVE_WIDTH (1U) 195 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) 196 /*! @} */ 197 198 /*! @name ES - Error Status */ 199 /*! @{ */ 200 201 #define DMA_ES_DBE_MASK (0x1U) 202 #define DMA_ES_DBE_SHIFT (0U) 203 #define DMA_ES_DBE_WIDTH (1U) 204 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) 205 206 #define DMA_ES_SBE_MASK (0x2U) 207 #define DMA_ES_SBE_SHIFT (1U) 208 #define DMA_ES_SBE_WIDTH (1U) 209 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) 210 211 #define DMA_ES_SGE_MASK (0x4U) 212 #define DMA_ES_SGE_SHIFT (2U) 213 #define DMA_ES_SGE_WIDTH (1U) 214 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) 215 216 #define DMA_ES_NCE_MASK (0x8U) 217 #define DMA_ES_NCE_SHIFT (3U) 218 #define DMA_ES_NCE_WIDTH (1U) 219 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) 220 221 #define DMA_ES_DOE_MASK (0x10U) 222 #define DMA_ES_DOE_SHIFT (4U) 223 #define DMA_ES_DOE_WIDTH (1U) 224 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) 225 226 #define DMA_ES_DAE_MASK (0x20U) 227 #define DMA_ES_DAE_SHIFT (5U) 228 #define DMA_ES_DAE_WIDTH (1U) 229 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) 230 231 #define DMA_ES_SOE_MASK (0x40U) 232 #define DMA_ES_SOE_SHIFT (6U) 233 #define DMA_ES_SOE_WIDTH (1U) 234 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) 235 236 #define DMA_ES_SAE_MASK (0x80U) 237 #define DMA_ES_SAE_SHIFT (7U) 238 #define DMA_ES_SAE_WIDTH (1U) 239 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) 240 241 #define DMA_ES_ERRCHN_MASK (0xF00U) 242 #define DMA_ES_ERRCHN_SHIFT (8U) 243 #define DMA_ES_ERRCHN_WIDTH (4U) 244 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) 245 246 #define DMA_ES_CPE_MASK (0x4000U) 247 #define DMA_ES_CPE_SHIFT (14U) 248 #define DMA_ES_CPE_WIDTH (1U) 249 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) 250 251 #define DMA_ES_ECX_MASK (0x10000U) 252 #define DMA_ES_ECX_SHIFT (16U) 253 #define DMA_ES_ECX_WIDTH (1U) 254 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) 255 256 #define DMA_ES_VLD_MASK (0x80000000U) 257 #define DMA_ES_VLD_SHIFT (31U) 258 #define DMA_ES_VLD_WIDTH (1U) 259 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) 260 /*! @} */ 261 262 /*! @name ERQ - Enable Request */ 263 /*! @{ */ 264 265 #define DMA_ERQ_ERQ0_MASK (0x1U) 266 #define DMA_ERQ_ERQ0_SHIFT (0U) 267 #define DMA_ERQ_ERQ0_WIDTH (1U) 268 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) 269 270 #define DMA_ERQ_ERQ1_MASK (0x2U) 271 #define DMA_ERQ_ERQ1_SHIFT (1U) 272 #define DMA_ERQ_ERQ1_WIDTH (1U) 273 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) 274 275 #define DMA_ERQ_ERQ2_MASK (0x4U) 276 #define DMA_ERQ_ERQ2_SHIFT (2U) 277 #define DMA_ERQ_ERQ2_WIDTH (1U) 278 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) 279 280 #define DMA_ERQ_ERQ3_MASK (0x8U) 281 #define DMA_ERQ_ERQ3_SHIFT (3U) 282 #define DMA_ERQ_ERQ3_WIDTH (1U) 283 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) 284 285 #define DMA_ERQ_ERQ4_MASK (0x10U) 286 #define DMA_ERQ_ERQ4_SHIFT (4U) 287 #define DMA_ERQ_ERQ4_WIDTH (1U) 288 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) 289 290 #define DMA_ERQ_ERQ5_MASK (0x20U) 291 #define DMA_ERQ_ERQ5_SHIFT (5U) 292 #define DMA_ERQ_ERQ5_WIDTH (1U) 293 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) 294 295 #define DMA_ERQ_ERQ6_MASK (0x40U) 296 #define DMA_ERQ_ERQ6_SHIFT (6U) 297 #define DMA_ERQ_ERQ6_WIDTH (1U) 298 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) 299 300 #define DMA_ERQ_ERQ7_MASK (0x80U) 301 #define DMA_ERQ_ERQ7_SHIFT (7U) 302 #define DMA_ERQ_ERQ7_WIDTH (1U) 303 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) 304 305 #define DMA_ERQ_ERQ8_MASK (0x100U) 306 #define DMA_ERQ_ERQ8_SHIFT (8U) 307 #define DMA_ERQ_ERQ8_WIDTH (1U) 308 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) 309 310 #define DMA_ERQ_ERQ9_MASK (0x200U) 311 #define DMA_ERQ_ERQ9_SHIFT (9U) 312 #define DMA_ERQ_ERQ9_WIDTH (1U) 313 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) 314 315 #define DMA_ERQ_ERQ10_MASK (0x400U) 316 #define DMA_ERQ_ERQ10_SHIFT (10U) 317 #define DMA_ERQ_ERQ10_WIDTH (1U) 318 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) 319 320 #define DMA_ERQ_ERQ11_MASK (0x800U) 321 #define DMA_ERQ_ERQ11_SHIFT (11U) 322 #define DMA_ERQ_ERQ11_WIDTH (1U) 323 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) 324 325 #define DMA_ERQ_ERQ12_MASK (0x1000U) 326 #define DMA_ERQ_ERQ12_SHIFT (12U) 327 #define DMA_ERQ_ERQ12_WIDTH (1U) 328 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) 329 330 #define DMA_ERQ_ERQ13_MASK (0x2000U) 331 #define DMA_ERQ_ERQ13_SHIFT (13U) 332 #define DMA_ERQ_ERQ13_WIDTH (1U) 333 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) 334 335 #define DMA_ERQ_ERQ14_MASK (0x4000U) 336 #define DMA_ERQ_ERQ14_SHIFT (14U) 337 #define DMA_ERQ_ERQ14_WIDTH (1U) 338 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) 339 340 #define DMA_ERQ_ERQ15_MASK (0x8000U) 341 #define DMA_ERQ_ERQ15_SHIFT (15U) 342 #define DMA_ERQ_ERQ15_WIDTH (1U) 343 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) 344 /*! @} */ 345 346 /*! @name EEI - Enable Error Interrupt */ 347 /*! @{ */ 348 349 #define DMA_EEI_EEI0_MASK (0x1U) 350 #define DMA_EEI_EEI0_SHIFT (0U) 351 #define DMA_EEI_EEI0_WIDTH (1U) 352 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) 353 354 #define DMA_EEI_EEI1_MASK (0x2U) 355 #define DMA_EEI_EEI1_SHIFT (1U) 356 #define DMA_EEI_EEI1_WIDTH (1U) 357 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) 358 359 #define DMA_EEI_EEI2_MASK (0x4U) 360 #define DMA_EEI_EEI2_SHIFT (2U) 361 #define DMA_EEI_EEI2_WIDTH (1U) 362 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) 363 364 #define DMA_EEI_EEI3_MASK (0x8U) 365 #define DMA_EEI_EEI3_SHIFT (3U) 366 #define DMA_EEI_EEI3_WIDTH (1U) 367 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) 368 369 #define DMA_EEI_EEI4_MASK (0x10U) 370 #define DMA_EEI_EEI4_SHIFT (4U) 371 #define DMA_EEI_EEI4_WIDTH (1U) 372 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) 373 374 #define DMA_EEI_EEI5_MASK (0x20U) 375 #define DMA_EEI_EEI5_SHIFT (5U) 376 #define DMA_EEI_EEI5_WIDTH (1U) 377 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) 378 379 #define DMA_EEI_EEI6_MASK (0x40U) 380 #define DMA_EEI_EEI6_SHIFT (6U) 381 #define DMA_EEI_EEI6_WIDTH (1U) 382 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) 383 384 #define DMA_EEI_EEI7_MASK (0x80U) 385 #define DMA_EEI_EEI7_SHIFT (7U) 386 #define DMA_EEI_EEI7_WIDTH (1U) 387 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) 388 389 #define DMA_EEI_EEI8_MASK (0x100U) 390 #define DMA_EEI_EEI8_SHIFT (8U) 391 #define DMA_EEI_EEI8_WIDTH (1U) 392 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) 393 394 #define DMA_EEI_EEI9_MASK (0x200U) 395 #define DMA_EEI_EEI9_SHIFT (9U) 396 #define DMA_EEI_EEI9_WIDTH (1U) 397 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) 398 399 #define DMA_EEI_EEI10_MASK (0x400U) 400 #define DMA_EEI_EEI10_SHIFT (10U) 401 #define DMA_EEI_EEI10_WIDTH (1U) 402 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) 403 404 #define DMA_EEI_EEI11_MASK (0x800U) 405 #define DMA_EEI_EEI11_SHIFT (11U) 406 #define DMA_EEI_EEI11_WIDTH (1U) 407 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) 408 409 #define DMA_EEI_EEI12_MASK (0x1000U) 410 #define DMA_EEI_EEI12_SHIFT (12U) 411 #define DMA_EEI_EEI12_WIDTH (1U) 412 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) 413 414 #define DMA_EEI_EEI13_MASK (0x2000U) 415 #define DMA_EEI_EEI13_SHIFT (13U) 416 #define DMA_EEI_EEI13_WIDTH (1U) 417 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) 418 419 #define DMA_EEI_EEI14_MASK (0x4000U) 420 #define DMA_EEI_EEI14_SHIFT (14U) 421 #define DMA_EEI_EEI14_WIDTH (1U) 422 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) 423 424 #define DMA_EEI_EEI15_MASK (0x8000U) 425 #define DMA_EEI_EEI15_SHIFT (15U) 426 #define DMA_EEI_EEI15_WIDTH (1U) 427 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) 428 /*! @} */ 429 430 /*! @name CEEI - Clear Enable Error Interrupt */ 431 /*! @{ */ 432 433 #define DMA_CEEI_CEEI_MASK (0xFU) 434 #define DMA_CEEI_CEEI_SHIFT (0U) 435 #define DMA_CEEI_CEEI_WIDTH (4U) 436 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) 437 438 #define DMA_CEEI_CAEE_MASK (0x40U) 439 #define DMA_CEEI_CAEE_SHIFT (6U) 440 #define DMA_CEEI_CAEE_WIDTH (1U) 441 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) 442 443 #define DMA_CEEI_NOP_MASK (0x80U) 444 #define DMA_CEEI_NOP_SHIFT (7U) 445 #define DMA_CEEI_NOP_WIDTH (1U) 446 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) 447 /*! @} */ 448 449 /*! @name SEEI - Set Enable Error Interrupt */ 450 /*! @{ */ 451 452 #define DMA_SEEI_SEEI_MASK (0xFU) 453 #define DMA_SEEI_SEEI_SHIFT (0U) 454 #define DMA_SEEI_SEEI_WIDTH (4U) 455 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) 456 457 #define DMA_SEEI_SAEE_MASK (0x40U) 458 #define DMA_SEEI_SAEE_SHIFT (6U) 459 #define DMA_SEEI_SAEE_WIDTH (1U) 460 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) 461 462 #define DMA_SEEI_NOP_MASK (0x80U) 463 #define DMA_SEEI_NOP_SHIFT (7U) 464 #define DMA_SEEI_NOP_WIDTH (1U) 465 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) 466 /*! @} */ 467 468 /*! @name CERQ - Clear Enable Request */ 469 /*! @{ */ 470 471 #define DMA_CERQ_CERQ_MASK (0xFU) 472 #define DMA_CERQ_CERQ_SHIFT (0U) 473 #define DMA_CERQ_CERQ_WIDTH (4U) 474 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) 475 476 #define DMA_CERQ_CAER_MASK (0x40U) 477 #define DMA_CERQ_CAER_SHIFT (6U) 478 #define DMA_CERQ_CAER_WIDTH (1U) 479 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) 480 481 #define DMA_CERQ_NOP_MASK (0x80U) 482 #define DMA_CERQ_NOP_SHIFT (7U) 483 #define DMA_CERQ_NOP_WIDTH (1U) 484 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) 485 /*! @} */ 486 487 /*! @name SERQ - Set Enable Request */ 488 /*! @{ */ 489 490 #define DMA_SERQ_SERQ_MASK (0xFU) 491 #define DMA_SERQ_SERQ_SHIFT (0U) 492 #define DMA_SERQ_SERQ_WIDTH (4U) 493 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) 494 495 #define DMA_SERQ_SAER_MASK (0x40U) 496 #define DMA_SERQ_SAER_SHIFT (6U) 497 #define DMA_SERQ_SAER_WIDTH (1U) 498 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) 499 500 #define DMA_SERQ_NOP_MASK (0x80U) 501 #define DMA_SERQ_NOP_SHIFT (7U) 502 #define DMA_SERQ_NOP_WIDTH (1U) 503 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) 504 /*! @} */ 505 506 /*! @name CDNE - Clear DONE Status Bit */ 507 /*! @{ */ 508 509 #define DMA_CDNE_CDNE_MASK (0xFU) 510 #define DMA_CDNE_CDNE_SHIFT (0U) 511 #define DMA_CDNE_CDNE_WIDTH (4U) 512 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) 513 514 #define DMA_CDNE_CADN_MASK (0x40U) 515 #define DMA_CDNE_CADN_SHIFT (6U) 516 #define DMA_CDNE_CADN_WIDTH (1U) 517 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) 518 519 #define DMA_CDNE_NOP_MASK (0x80U) 520 #define DMA_CDNE_NOP_SHIFT (7U) 521 #define DMA_CDNE_NOP_WIDTH (1U) 522 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) 523 /*! @} */ 524 525 /*! @name SSRT - Set START Bit */ 526 /*! @{ */ 527 528 #define DMA_SSRT_SSRT_MASK (0xFU) 529 #define DMA_SSRT_SSRT_SHIFT (0U) 530 #define DMA_SSRT_SSRT_WIDTH (4U) 531 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) 532 533 #define DMA_SSRT_SAST_MASK (0x40U) 534 #define DMA_SSRT_SAST_SHIFT (6U) 535 #define DMA_SSRT_SAST_WIDTH (1U) 536 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) 537 538 #define DMA_SSRT_NOP_MASK (0x80U) 539 #define DMA_SSRT_NOP_SHIFT (7U) 540 #define DMA_SSRT_NOP_WIDTH (1U) 541 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) 542 /*! @} */ 543 544 /*! @name CERR - Clear Error */ 545 /*! @{ */ 546 547 #define DMA_CERR_CERR_MASK (0xFU) 548 #define DMA_CERR_CERR_SHIFT (0U) 549 #define DMA_CERR_CERR_WIDTH (4U) 550 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) 551 552 #define DMA_CERR_CAEI_MASK (0x40U) 553 #define DMA_CERR_CAEI_SHIFT (6U) 554 #define DMA_CERR_CAEI_WIDTH (1U) 555 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) 556 557 #define DMA_CERR_NOP_MASK (0x80U) 558 #define DMA_CERR_NOP_SHIFT (7U) 559 #define DMA_CERR_NOP_WIDTH (1U) 560 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) 561 /*! @} */ 562 563 /*! @name CINT - Clear Interrupt Request */ 564 /*! @{ */ 565 566 #define DMA_CINT_CINT_MASK (0xFU) 567 #define DMA_CINT_CINT_SHIFT (0U) 568 #define DMA_CINT_CINT_WIDTH (4U) 569 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) 570 571 #define DMA_CINT_CAIR_MASK (0x40U) 572 #define DMA_CINT_CAIR_SHIFT (6U) 573 #define DMA_CINT_CAIR_WIDTH (1U) 574 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) 575 576 #define DMA_CINT_NOP_MASK (0x80U) 577 #define DMA_CINT_NOP_SHIFT (7U) 578 #define DMA_CINT_NOP_WIDTH (1U) 579 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) 580 /*! @} */ 581 582 /*! @name INT - Interrupt Request */ 583 /*! @{ */ 584 585 #define DMA_INT_INT0_MASK (0x1U) 586 #define DMA_INT_INT0_SHIFT (0U) 587 #define DMA_INT_INT0_WIDTH (1U) 588 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) 589 590 #define DMA_INT_INT1_MASK (0x2U) 591 #define DMA_INT_INT1_SHIFT (1U) 592 #define DMA_INT_INT1_WIDTH (1U) 593 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) 594 595 #define DMA_INT_INT2_MASK (0x4U) 596 #define DMA_INT_INT2_SHIFT (2U) 597 #define DMA_INT_INT2_WIDTH (1U) 598 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) 599 600 #define DMA_INT_INT3_MASK (0x8U) 601 #define DMA_INT_INT3_SHIFT (3U) 602 #define DMA_INT_INT3_WIDTH (1U) 603 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) 604 605 #define DMA_INT_INT4_MASK (0x10U) 606 #define DMA_INT_INT4_SHIFT (4U) 607 #define DMA_INT_INT4_WIDTH (1U) 608 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) 609 610 #define DMA_INT_INT5_MASK (0x20U) 611 #define DMA_INT_INT5_SHIFT (5U) 612 #define DMA_INT_INT5_WIDTH (1U) 613 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) 614 615 #define DMA_INT_INT6_MASK (0x40U) 616 #define DMA_INT_INT6_SHIFT (6U) 617 #define DMA_INT_INT6_WIDTH (1U) 618 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) 619 620 #define DMA_INT_INT7_MASK (0x80U) 621 #define DMA_INT_INT7_SHIFT (7U) 622 #define DMA_INT_INT7_WIDTH (1U) 623 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) 624 625 #define DMA_INT_INT8_MASK (0x100U) 626 #define DMA_INT_INT8_SHIFT (8U) 627 #define DMA_INT_INT8_WIDTH (1U) 628 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) 629 630 #define DMA_INT_INT9_MASK (0x200U) 631 #define DMA_INT_INT9_SHIFT (9U) 632 #define DMA_INT_INT9_WIDTH (1U) 633 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) 634 635 #define DMA_INT_INT10_MASK (0x400U) 636 #define DMA_INT_INT10_SHIFT (10U) 637 #define DMA_INT_INT10_WIDTH (1U) 638 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) 639 640 #define DMA_INT_INT11_MASK (0x800U) 641 #define DMA_INT_INT11_SHIFT (11U) 642 #define DMA_INT_INT11_WIDTH (1U) 643 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) 644 645 #define DMA_INT_INT12_MASK (0x1000U) 646 #define DMA_INT_INT12_SHIFT (12U) 647 #define DMA_INT_INT12_WIDTH (1U) 648 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) 649 650 #define DMA_INT_INT13_MASK (0x2000U) 651 #define DMA_INT_INT13_SHIFT (13U) 652 #define DMA_INT_INT13_WIDTH (1U) 653 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) 654 655 #define DMA_INT_INT14_MASK (0x4000U) 656 #define DMA_INT_INT14_SHIFT (14U) 657 #define DMA_INT_INT14_WIDTH (1U) 658 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) 659 660 #define DMA_INT_INT15_MASK (0x8000U) 661 #define DMA_INT_INT15_SHIFT (15U) 662 #define DMA_INT_INT15_WIDTH (1U) 663 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) 664 /*! @} */ 665 666 /*! @name ERR - Error */ 667 /*! @{ */ 668 669 #define DMA_ERR_ERR0_MASK (0x1U) 670 #define DMA_ERR_ERR0_SHIFT (0U) 671 #define DMA_ERR_ERR0_WIDTH (1U) 672 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) 673 674 #define DMA_ERR_ERR1_MASK (0x2U) 675 #define DMA_ERR_ERR1_SHIFT (1U) 676 #define DMA_ERR_ERR1_WIDTH (1U) 677 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) 678 679 #define DMA_ERR_ERR2_MASK (0x4U) 680 #define DMA_ERR_ERR2_SHIFT (2U) 681 #define DMA_ERR_ERR2_WIDTH (1U) 682 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) 683 684 #define DMA_ERR_ERR3_MASK (0x8U) 685 #define DMA_ERR_ERR3_SHIFT (3U) 686 #define DMA_ERR_ERR3_WIDTH (1U) 687 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) 688 689 #define DMA_ERR_ERR4_MASK (0x10U) 690 #define DMA_ERR_ERR4_SHIFT (4U) 691 #define DMA_ERR_ERR4_WIDTH (1U) 692 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) 693 694 #define DMA_ERR_ERR5_MASK (0x20U) 695 #define DMA_ERR_ERR5_SHIFT (5U) 696 #define DMA_ERR_ERR5_WIDTH (1U) 697 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) 698 699 #define DMA_ERR_ERR6_MASK (0x40U) 700 #define DMA_ERR_ERR6_SHIFT (6U) 701 #define DMA_ERR_ERR6_WIDTH (1U) 702 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) 703 704 #define DMA_ERR_ERR7_MASK (0x80U) 705 #define DMA_ERR_ERR7_SHIFT (7U) 706 #define DMA_ERR_ERR7_WIDTH (1U) 707 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) 708 709 #define DMA_ERR_ERR8_MASK (0x100U) 710 #define DMA_ERR_ERR8_SHIFT (8U) 711 #define DMA_ERR_ERR8_WIDTH (1U) 712 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) 713 714 #define DMA_ERR_ERR9_MASK (0x200U) 715 #define DMA_ERR_ERR9_SHIFT (9U) 716 #define DMA_ERR_ERR9_WIDTH (1U) 717 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) 718 719 #define DMA_ERR_ERR10_MASK (0x400U) 720 #define DMA_ERR_ERR10_SHIFT (10U) 721 #define DMA_ERR_ERR10_WIDTH (1U) 722 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) 723 724 #define DMA_ERR_ERR11_MASK (0x800U) 725 #define DMA_ERR_ERR11_SHIFT (11U) 726 #define DMA_ERR_ERR11_WIDTH (1U) 727 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) 728 729 #define DMA_ERR_ERR12_MASK (0x1000U) 730 #define DMA_ERR_ERR12_SHIFT (12U) 731 #define DMA_ERR_ERR12_WIDTH (1U) 732 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) 733 734 #define DMA_ERR_ERR13_MASK (0x2000U) 735 #define DMA_ERR_ERR13_SHIFT (13U) 736 #define DMA_ERR_ERR13_WIDTH (1U) 737 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) 738 739 #define DMA_ERR_ERR14_MASK (0x4000U) 740 #define DMA_ERR_ERR14_SHIFT (14U) 741 #define DMA_ERR_ERR14_WIDTH (1U) 742 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) 743 744 #define DMA_ERR_ERR15_MASK (0x8000U) 745 #define DMA_ERR_ERR15_SHIFT (15U) 746 #define DMA_ERR_ERR15_WIDTH (1U) 747 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) 748 /*! @} */ 749 750 /*! @name HRS - Hardware Request Status */ 751 /*! @{ */ 752 753 #define DMA_HRS_HRS0_MASK (0x1U) 754 #define DMA_HRS_HRS0_SHIFT (0U) 755 #define DMA_HRS_HRS0_WIDTH (1U) 756 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) 757 758 #define DMA_HRS_HRS1_MASK (0x2U) 759 #define DMA_HRS_HRS1_SHIFT (1U) 760 #define DMA_HRS_HRS1_WIDTH (1U) 761 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) 762 763 #define DMA_HRS_HRS2_MASK (0x4U) 764 #define DMA_HRS_HRS2_SHIFT (2U) 765 #define DMA_HRS_HRS2_WIDTH (1U) 766 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) 767 768 #define DMA_HRS_HRS3_MASK (0x8U) 769 #define DMA_HRS_HRS3_SHIFT (3U) 770 #define DMA_HRS_HRS3_WIDTH (1U) 771 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) 772 773 #define DMA_HRS_HRS4_MASK (0x10U) 774 #define DMA_HRS_HRS4_SHIFT (4U) 775 #define DMA_HRS_HRS4_WIDTH (1U) 776 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) 777 778 #define DMA_HRS_HRS5_MASK (0x20U) 779 #define DMA_HRS_HRS5_SHIFT (5U) 780 #define DMA_HRS_HRS5_WIDTH (1U) 781 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) 782 783 #define DMA_HRS_HRS6_MASK (0x40U) 784 #define DMA_HRS_HRS6_SHIFT (6U) 785 #define DMA_HRS_HRS6_WIDTH (1U) 786 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) 787 788 #define DMA_HRS_HRS7_MASK (0x80U) 789 #define DMA_HRS_HRS7_SHIFT (7U) 790 #define DMA_HRS_HRS7_WIDTH (1U) 791 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) 792 793 #define DMA_HRS_HRS8_MASK (0x100U) 794 #define DMA_HRS_HRS8_SHIFT (8U) 795 #define DMA_HRS_HRS8_WIDTH (1U) 796 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) 797 798 #define DMA_HRS_HRS9_MASK (0x200U) 799 #define DMA_HRS_HRS9_SHIFT (9U) 800 #define DMA_HRS_HRS9_WIDTH (1U) 801 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) 802 803 #define DMA_HRS_HRS10_MASK (0x400U) 804 #define DMA_HRS_HRS10_SHIFT (10U) 805 #define DMA_HRS_HRS10_WIDTH (1U) 806 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) 807 808 #define DMA_HRS_HRS11_MASK (0x800U) 809 #define DMA_HRS_HRS11_SHIFT (11U) 810 #define DMA_HRS_HRS11_WIDTH (1U) 811 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) 812 813 #define DMA_HRS_HRS12_MASK (0x1000U) 814 #define DMA_HRS_HRS12_SHIFT (12U) 815 #define DMA_HRS_HRS12_WIDTH (1U) 816 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) 817 818 #define DMA_HRS_HRS13_MASK (0x2000U) 819 #define DMA_HRS_HRS13_SHIFT (13U) 820 #define DMA_HRS_HRS13_WIDTH (1U) 821 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) 822 823 #define DMA_HRS_HRS14_MASK (0x4000U) 824 #define DMA_HRS_HRS14_SHIFT (14U) 825 #define DMA_HRS_HRS14_WIDTH (1U) 826 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) 827 828 #define DMA_HRS_HRS15_MASK (0x8000U) 829 #define DMA_HRS_HRS15_SHIFT (15U) 830 #define DMA_HRS_HRS15_WIDTH (1U) 831 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) 832 /*! @} */ 833 834 /*! @name EARS - Enable Asynchronous Request in Stop */ 835 /*! @{ */ 836 837 #define DMA_EARS_EDREQ_0_MASK (0x1U) 838 #define DMA_EARS_EDREQ_0_SHIFT (0U) 839 #define DMA_EARS_EDREQ_0_WIDTH (1U) 840 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) 841 842 #define DMA_EARS_EDREQ_1_MASK (0x2U) 843 #define DMA_EARS_EDREQ_1_SHIFT (1U) 844 #define DMA_EARS_EDREQ_1_WIDTH (1U) 845 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) 846 847 #define DMA_EARS_EDREQ_2_MASK (0x4U) 848 #define DMA_EARS_EDREQ_2_SHIFT (2U) 849 #define DMA_EARS_EDREQ_2_WIDTH (1U) 850 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) 851 852 #define DMA_EARS_EDREQ_3_MASK (0x8U) 853 #define DMA_EARS_EDREQ_3_SHIFT (3U) 854 #define DMA_EARS_EDREQ_3_WIDTH (1U) 855 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) 856 857 #define DMA_EARS_EDREQ_4_MASK (0x10U) 858 #define DMA_EARS_EDREQ_4_SHIFT (4U) 859 #define DMA_EARS_EDREQ_4_WIDTH (1U) 860 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) 861 862 #define DMA_EARS_EDREQ_5_MASK (0x20U) 863 #define DMA_EARS_EDREQ_5_SHIFT (5U) 864 #define DMA_EARS_EDREQ_5_WIDTH (1U) 865 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) 866 867 #define DMA_EARS_EDREQ_6_MASK (0x40U) 868 #define DMA_EARS_EDREQ_6_SHIFT (6U) 869 #define DMA_EARS_EDREQ_6_WIDTH (1U) 870 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) 871 872 #define DMA_EARS_EDREQ_7_MASK (0x80U) 873 #define DMA_EARS_EDREQ_7_SHIFT (7U) 874 #define DMA_EARS_EDREQ_7_WIDTH (1U) 875 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) 876 877 #define DMA_EARS_EDREQ_8_MASK (0x100U) 878 #define DMA_EARS_EDREQ_8_SHIFT (8U) 879 #define DMA_EARS_EDREQ_8_WIDTH (1U) 880 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) 881 882 #define DMA_EARS_EDREQ_9_MASK (0x200U) 883 #define DMA_EARS_EDREQ_9_SHIFT (9U) 884 #define DMA_EARS_EDREQ_9_WIDTH (1U) 885 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) 886 887 #define DMA_EARS_EDREQ_10_MASK (0x400U) 888 #define DMA_EARS_EDREQ_10_SHIFT (10U) 889 #define DMA_EARS_EDREQ_10_WIDTH (1U) 890 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) 891 892 #define DMA_EARS_EDREQ_11_MASK (0x800U) 893 #define DMA_EARS_EDREQ_11_SHIFT (11U) 894 #define DMA_EARS_EDREQ_11_WIDTH (1U) 895 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) 896 897 #define DMA_EARS_EDREQ_12_MASK (0x1000U) 898 #define DMA_EARS_EDREQ_12_SHIFT (12U) 899 #define DMA_EARS_EDREQ_12_WIDTH (1U) 900 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) 901 902 #define DMA_EARS_EDREQ_13_MASK (0x2000U) 903 #define DMA_EARS_EDREQ_13_SHIFT (13U) 904 #define DMA_EARS_EDREQ_13_WIDTH (1U) 905 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) 906 907 #define DMA_EARS_EDREQ_14_MASK (0x4000U) 908 #define DMA_EARS_EDREQ_14_SHIFT (14U) 909 #define DMA_EARS_EDREQ_14_WIDTH (1U) 910 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) 911 912 #define DMA_EARS_EDREQ_15_MASK (0x8000U) 913 #define DMA_EARS_EDREQ_15_SHIFT (15U) 914 #define DMA_EARS_EDREQ_15_WIDTH (1U) 915 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) 916 /*! @} */ 917 918 /*! @name DCHPRI - Channel Priority */ 919 /*! @{ */ 920 921 #define DMA_DCHPRI_CHPRI_MASK (0xFU) 922 #define DMA_DCHPRI_CHPRI_SHIFT (0U) 923 #define DMA_DCHPRI_CHPRI_WIDTH (4U) 924 #define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI_CHPRI_SHIFT)) & DMA_DCHPRI_CHPRI_MASK) 925 926 #define DMA_DCHPRI_DPA_MASK (0x40U) 927 #define DMA_DCHPRI_DPA_SHIFT (6U) 928 #define DMA_DCHPRI_DPA_WIDTH (1U) 929 #define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI_DPA_SHIFT)) & DMA_DCHPRI_DPA_MASK) 930 931 #define DMA_DCHPRI_ECP_MASK (0x80U) 932 #define DMA_DCHPRI_ECP_SHIFT (7U) 933 #define DMA_DCHPRI_ECP_WIDTH (1U) 934 #define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI_ECP_SHIFT)) & DMA_DCHPRI_ECP_MASK) 935 /*! @} */ 936 937 /*! @name TCD_SADDR - TCD Source Address */ 938 /*! @{ */ 939 940 #define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) 941 #define DMA_TCD_SADDR_SADDR_SHIFT (0U) 942 #define DMA_TCD_SADDR_SADDR_WIDTH (32U) 943 #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) 944 /*! @} */ 945 946 /*! @name TCD_SOFF - TCD Signed Source Address Offset */ 947 /*! @{ */ 948 949 #define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) 950 #define DMA_TCD_SOFF_SOFF_SHIFT (0U) 951 #define DMA_TCD_SOFF_SOFF_WIDTH (16U) 952 #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) 953 /*! @} */ 954 955 /*! @name TCD_ATTR - TCD Transfer Attributes */ 956 /*! @{ */ 957 958 #define DMA_TCD_ATTR_DSIZE_MASK (0x7U) 959 #define DMA_TCD_ATTR_DSIZE_SHIFT (0U) 960 #define DMA_TCD_ATTR_DSIZE_WIDTH (3U) 961 #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) 962 963 #define DMA_TCD_ATTR_DMOD_MASK (0xF8U) 964 #define DMA_TCD_ATTR_DMOD_SHIFT (3U) 965 #define DMA_TCD_ATTR_DMOD_WIDTH (5U) 966 #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) 967 968 #define DMA_TCD_ATTR_SSIZE_MASK (0x700U) 969 #define DMA_TCD_ATTR_SSIZE_SHIFT (8U) 970 #define DMA_TCD_ATTR_SSIZE_WIDTH (3U) 971 #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) 972 973 #define DMA_TCD_ATTR_SMOD_MASK (0xF800U) 974 #define DMA_TCD_ATTR_SMOD_SHIFT (11U) 975 #define DMA_TCD_ATTR_SMOD_WIDTH (5U) 976 #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) 977 /*! @} */ 978 979 /*! @name TCD_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ 980 /*! @{ */ 981 982 #define DMA_TCD_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) 983 #define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT (0U) 984 #define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH (32U) 985 #define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLNO_NBYTES_MASK) 986 /*! @} */ 987 988 /*! @name TCD_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ 989 /*! @{ */ 990 991 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 992 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 993 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 994 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) 995 996 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 997 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 998 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 999 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) 1000 1001 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 1002 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 1003 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 1004 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) 1005 /*! @} */ 1006 1007 /*! @name TCD_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ 1008 /*! @{ */ 1009 1010 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 1011 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 1012 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 1013 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) 1014 1015 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 1016 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 1017 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 1018 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) 1019 1020 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 1021 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 1022 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 1023 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) 1024 1025 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 1026 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 1027 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 1028 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) 1029 /*! @} */ 1030 1031 /*! @name TCD_SLAST - TCD Last Source Address Adjustment */ 1032 /*! @{ */ 1033 1034 #define DMA_TCD_SLAST_SLAST_MASK (0xFFFFFFFFU) 1035 #define DMA_TCD_SLAST_SLAST_SHIFT (0U) 1036 #define DMA_TCD_SLAST_SLAST_WIDTH (32U) 1037 #define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SLAST_SHIFT)) & DMA_TCD_SLAST_SLAST_MASK) 1038 /*! @} */ 1039 1040 /*! @name TCD_DADDR - TCD Destination Address */ 1041 /*! @{ */ 1042 1043 #define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) 1044 #define DMA_TCD_DADDR_DADDR_SHIFT (0U) 1045 #define DMA_TCD_DADDR_DADDR_WIDTH (32U) 1046 #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) 1047 /*! @} */ 1048 1049 /*! @name TCD_DOFF - TCD Signed Destination Address Offset */ 1050 /*! @{ */ 1051 1052 #define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) 1053 #define DMA_TCD_DOFF_DOFF_SHIFT (0U) 1054 #define DMA_TCD_DOFF_DOFF_WIDTH (16U) 1055 #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) 1056 /*! @} */ 1057 1058 /*! @name TCD_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 1059 /*! @{ */ 1060 1061 #define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) 1062 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) 1063 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH (15U) 1064 #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) 1065 1066 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) 1067 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) 1068 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH (1U) 1069 #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) 1070 /*! @} */ 1071 1072 /*! @name TCD_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 1073 /*! @{ */ 1074 1075 #define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) 1076 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) 1077 #define DMA_TCD_CITER_ELINKYES_CITER_WIDTH (9U) 1078 #define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) 1079 1080 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x1E00U) 1081 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) 1082 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH (4U) 1083 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) 1084 1085 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) 1086 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) 1087 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH (1U) 1088 #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) 1089 /*! @} */ 1090 1091 /*! @name TCD_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ 1092 /*! @{ */ 1093 1094 #define DMA_TCD_DLASTSGA_DLASTSGA_MASK (0xFFFFFFFFU) 1095 #define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT (0U) 1096 #define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH (32U) 1097 #define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLASTSGA_DLASTSGA_SHIFT)) & DMA_TCD_DLASTSGA_DLASTSGA_MASK) 1098 /*! @} */ 1099 1100 /*! @name TCD_CSR - TCD Control and Status */ 1101 /*! @{ */ 1102 1103 #define DMA_TCD_CSR_START_MASK (0x1U) 1104 #define DMA_TCD_CSR_START_SHIFT (0U) 1105 #define DMA_TCD_CSR_START_WIDTH (1U) 1106 #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) 1107 1108 #define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) 1109 #define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) 1110 #define DMA_TCD_CSR_INTMAJOR_WIDTH (1U) 1111 #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) 1112 1113 #define DMA_TCD_CSR_INTHALF_MASK (0x4U) 1114 #define DMA_TCD_CSR_INTHALF_SHIFT (2U) 1115 #define DMA_TCD_CSR_INTHALF_WIDTH (1U) 1116 #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) 1117 1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) 1119 #define DMA_TCD_CSR_DREQ_SHIFT (3U) 1120 #define DMA_TCD_CSR_DREQ_WIDTH (1U) 1121 #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) 1122 1123 #define DMA_TCD_CSR_ESG_MASK (0x10U) 1124 #define DMA_TCD_CSR_ESG_SHIFT (4U) 1125 #define DMA_TCD_CSR_ESG_WIDTH (1U) 1126 #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) 1127 1128 #define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) 1129 #define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) 1130 #define DMA_TCD_CSR_MAJORELINK_WIDTH (1U) 1131 #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) 1132 1133 #define DMA_TCD_CSR_ACTIVE_MASK (0x40U) 1134 #define DMA_TCD_CSR_ACTIVE_SHIFT (6U) 1135 #define DMA_TCD_CSR_ACTIVE_WIDTH (1U) 1136 #define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ACTIVE_SHIFT)) & DMA_TCD_CSR_ACTIVE_MASK) 1137 1138 #define DMA_TCD_CSR_DONE_MASK (0x80U) 1139 #define DMA_TCD_CSR_DONE_SHIFT (7U) 1140 #define DMA_TCD_CSR_DONE_WIDTH (1U) 1141 #define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DONE_SHIFT)) & DMA_TCD_CSR_DONE_MASK) 1142 1143 #define DMA_TCD_CSR_MAJORLINKCH_MASK (0xF00U) 1144 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) 1145 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH (4U) 1146 #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) 1147 1148 #define DMA_TCD_CSR_BWC_MASK (0xC000U) 1149 #define DMA_TCD_CSR_BWC_SHIFT (14U) 1150 #define DMA_TCD_CSR_BWC_WIDTH (2U) 1151 #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) 1152 /*! @} */ 1153 1154 /*! @name TCD_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 1155 /*! @{ */ 1156 1157 #define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) 1158 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) 1159 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH (15U) 1160 #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) 1161 1162 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) 1163 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) 1164 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH (1U) 1165 #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) 1166 /*! @} */ 1167 1168 /*! @name TCD_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 1169 /*! @{ */ 1170 1171 #define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) 1172 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) 1173 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH (9U) 1174 #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) 1175 1176 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x1E00U) 1177 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) 1178 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH (4U) 1179 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) 1180 1181 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) 1182 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) 1183 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH (1U) 1184 #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) 1185 /*! @} */ 1186 1187 /*! 1188 * @} 1189 */ /* end of group DMA_Register_Masks */ 1190 1191 /*! 1192 * @} 1193 */ /* end of group DMA_Peripheral_Access_Layer */ 1194 1195 #endif /* #if !defined(S32K142W_DMA_H_) */ 1196
