1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_LPTMR.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_LPTMR 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_LPTMR_H_) /* Check if memory map has not been already included */ 58 #define S32K118_LPTMR_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPTMR Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPTMR - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 74 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 75 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 76 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 77 } LPTMR_Type, *LPTMR_MemMapPtr; 78 79 /** Number of instances of the LPTMR module. */ 80 #define LPTMR_INSTANCE_COUNT (1u) 81 82 /* LPTMR - Peripheral instance base addresses */ 83 /** Peripheral LPTMR0 base address */ 84 #define IP_LPTMR0_BASE (0x40040000u) 85 /** Peripheral LPTMR0 base pointer */ 86 #define IP_LPTMR0 ((LPTMR_Type *)IP_LPTMR0_BASE) 87 /** Array initializer of LPTMR peripheral base addresses */ 88 #define IP_LPTMR_BASE_ADDRS { IP_LPTMR0_BASE } 89 /** Array initializer of LPTMR peripheral base pointers */ 90 #define IP_LPTMR_BASE_PTRS { IP_LPTMR0 } 91 92 /* ---------------------------------------------------------------------------- 93 -- LPTMR Register Masks 94 ---------------------------------------------------------------------------- */ 95 96 /*! 97 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 98 * @{ 99 */ 100 101 /*! @name CSR - Low Power Timer Control Status Register */ 102 /*! @{ */ 103 104 #define LPTMR_CSR_TEN_MASK (0x1U) 105 #define LPTMR_CSR_TEN_SHIFT (0U) 106 #define LPTMR_CSR_TEN_WIDTH (1U) 107 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 108 109 #define LPTMR_CSR_TMS_MASK (0x2U) 110 #define LPTMR_CSR_TMS_SHIFT (1U) 111 #define LPTMR_CSR_TMS_WIDTH (1U) 112 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 113 114 #define LPTMR_CSR_TFC_MASK (0x4U) 115 #define LPTMR_CSR_TFC_SHIFT (2U) 116 #define LPTMR_CSR_TFC_WIDTH (1U) 117 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 118 119 #define LPTMR_CSR_TPP_MASK (0x8U) 120 #define LPTMR_CSR_TPP_SHIFT (3U) 121 #define LPTMR_CSR_TPP_WIDTH (1U) 122 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 123 124 #define LPTMR_CSR_TPS_MASK (0x30U) 125 #define LPTMR_CSR_TPS_SHIFT (4U) 126 #define LPTMR_CSR_TPS_WIDTH (2U) 127 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 128 129 #define LPTMR_CSR_TIE_MASK (0x40U) 130 #define LPTMR_CSR_TIE_SHIFT (6U) 131 #define LPTMR_CSR_TIE_WIDTH (1U) 132 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 133 134 #define LPTMR_CSR_TCF_MASK (0x80U) 135 #define LPTMR_CSR_TCF_SHIFT (7U) 136 #define LPTMR_CSR_TCF_WIDTH (1U) 137 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 138 139 #define LPTMR_CSR_TDRE_MASK (0x100U) 140 #define LPTMR_CSR_TDRE_SHIFT (8U) 141 #define LPTMR_CSR_TDRE_WIDTH (1U) 142 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) 143 /*! @} */ 144 145 /*! @name PSR - Low Power Timer Prescale Register */ 146 /*! @{ */ 147 148 #define LPTMR_PSR_PCS_MASK (0x3U) 149 #define LPTMR_PSR_PCS_SHIFT (0U) 150 #define LPTMR_PSR_PCS_WIDTH (2U) 151 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 152 153 #define LPTMR_PSR_PBYP_MASK (0x4U) 154 #define LPTMR_PSR_PBYP_SHIFT (2U) 155 #define LPTMR_PSR_PBYP_WIDTH (1U) 156 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 157 158 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 159 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 160 #define LPTMR_PSR_PRESCALE_WIDTH (4U) 161 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 162 /*! @} */ 163 164 /*! @name CMR - Low Power Timer Compare Register */ 165 /*! @{ */ 166 167 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 168 #define LPTMR_CMR_COMPARE_SHIFT (0U) 169 #define LPTMR_CMR_COMPARE_WIDTH (16U) 170 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 171 /*! @} */ 172 173 /*! @name CNR - Low Power Timer Counter Register */ 174 /*! @{ */ 175 176 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 177 #define LPTMR_CNR_COUNTER_SHIFT (0U) 178 #define LPTMR_CNR_COUNTER_WIDTH (16U) 179 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 180 /*! @} */ 181 182 /*! 183 * @} 184 */ /* end of group LPTMR_Register_Masks */ 185 186 /*! 187 * @} 188 */ /* end of group LPTMR_Peripheral_Access_Layer */ 189 190 #endif /* #if !defined(S32K118_LPTMR_H_) */ 191
