1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118_GPIO.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118_GPIO 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K118_GPIO_H_) /* Check if memory map has not been already included */ 58 #define S32K118_GPIO_H_ 59 60 #include "S32K118_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPIO Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPIO - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 74 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 75 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 76 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 77 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 78 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 79 } GPIO_Type, *GPIO_MemMapPtr; 80 81 /** Number of instances of the GPIO module. */ 82 #define GPIO_INSTANCE_COUNT (5u) 83 84 /* GPIO - Peripheral instance base addresses */ 85 /** Peripheral PTA base address */ 86 #define IP_PTA_BASE (0x400FF000u) 87 /** Peripheral PTA base pointer */ 88 #define IP_PTA ((GPIO_Type *)IP_PTA_BASE) 89 /** Peripheral PTB base address */ 90 #define IP_PTB_BASE (0x400FF040u) 91 /** Peripheral PTB base pointer */ 92 #define IP_PTB ((GPIO_Type *)IP_PTB_BASE) 93 /** Peripheral PTC base address */ 94 #define IP_PTC_BASE (0x400FF080u) 95 /** Peripheral PTC base pointer */ 96 #define IP_PTC ((GPIO_Type *)IP_PTC_BASE) 97 /** Peripheral PTD base address */ 98 #define IP_PTD_BASE (0x400FF0C0u) 99 /** Peripheral PTD base pointer */ 100 #define IP_PTD ((GPIO_Type *)IP_PTD_BASE) 101 /** Peripheral PTE base address */ 102 #define IP_PTE_BASE (0x400FF100u) 103 /** Peripheral PTE base pointer */ 104 #define IP_PTE ((GPIO_Type *)IP_PTE_BASE) 105 /** Array initializer of GPIO peripheral base addresses */ 106 #define IP_GPIO_BASE_ADDRS { IP_PTA_BASE, IP_PTB_BASE, IP_PTC_BASE, IP_PTD_BASE, IP_PTE_BASE } 107 /** Array initializer of GPIO peripheral base pointers */ 108 #define IP_GPIO_BASE_PTRS { IP_PTA, IP_PTB, IP_PTC, IP_PTD, IP_PTE } 109 110 /* ---------------------------------------------------------------------------- 111 -- GPIO Register Masks 112 ---------------------------------------------------------------------------- */ 113 114 /*! 115 * @addtogroup GPIO_Register_Masks GPIO Register Masks 116 * @{ 117 */ 118 119 /*! @name PDOR - Port Data Output Register */ 120 /*! @{ */ 121 122 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 123 #define GPIO_PDOR_PDO_SHIFT (0U) 124 #define GPIO_PDOR_PDO_WIDTH (32U) 125 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 126 /*! @} */ 127 128 /*! @name PSOR - Port Set Output Register */ 129 /*! @{ */ 130 131 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 132 #define GPIO_PSOR_PTSO_SHIFT (0U) 133 #define GPIO_PSOR_PTSO_WIDTH (32U) 134 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 135 /*! @} */ 136 137 /*! @name PCOR - Port Clear Output Register */ 138 /*! @{ */ 139 140 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 141 #define GPIO_PCOR_PTCO_SHIFT (0U) 142 #define GPIO_PCOR_PTCO_WIDTH (32U) 143 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 144 /*! @} */ 145 146 /*! @name PTOR - Port Toggle Output Register */ 147 /*! @{ */ 148 149 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 150 #define GPIO_PTOR_PTTO_SHIFT (0U) 151 #define GPIO_PTOR_PTTO_WIDTH (32U) 152 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 153 /*! @} */ 154 155 /*! @name PDIR - Port Data Input Register */ 156 /*! @{ */ 157 158 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 159 #define GPIO_PDIR_PDI_SHIFT (0U) 160 #define GPIO_PDIR_PDI_WIDTH (32U) 161 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 162 /*! @} */ 163 164 /*! @name PDDR - Port Data Direction Register */ 165 /*! @{ */ 166 167 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 168 #define GPIO_PDDR_PDD_SHIFT (0U) 169 #define GPIO_PDDR_PDD_WIDTH (32U) 170 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 171 /*! @} */ 172 173 /*! 174 * @} 175 */ /* end of group GPIO_Register_Masks */ 176 177 /*! 178 * @} 179 */ /* end of group GPIO_Peripheral_Access_Layer */ 180 181 #endif /* #if !defined(S32K118_GPIO_H_) */ 182
