1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_PORT.h 10 * @version 1.1 11 * @date 2022-01-21 12 * @brief Peripheral Access Layer for S32K116_PORT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_PORT_H_) /* Check if memory map has not been already included */ 58 #define S32K116_PORT_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PORT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PORT - Size of Registers Arrays */ 72 #define PORT_PCR_COUNT 32u 73 74 /** PORT - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 77 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 78 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 79 __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */ 80 __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */ 81 uint8_t RESERVED_0[16]; 82 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 83 uint8_t RESERVED_1[28]; 84 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ 85 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ 86 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ 87 } PORT_Type, *PORT_MemMapPtr; 88 89 /** Number of instances of the PORT module. */ 90 #define PORT_INSTANCE_COUNT (5u) 91 92 /* PORT - Peripheral instance base addresses */ 93 /** Peripheral PORTA base address */ 94 #define IP_PORTA_BASE (0x40049000u) 95 /** Peripheral PORTA base pointer */ 96 #define IP_PORTA ((PORT_Type *)IP_PORTA_BASE) 97 /** Peripheral PORTB base address */ 98 #define IP_PORTB_BASE (0x4004A000u) 99 /** Peripheral PORTB base pointer */ 100 #define IP_PORTB ((PORT_Type *)IP_PORTB_BASE) 101 /** Peripheral PORTC base address */ 102 #define IP_PORTC_BASE (0x4004B000u) 103 /** Peripheral PORTC base pointer */ 104 #define IP_PORTC ((PORT_Type *)IP_PORTC_BASE) 105 /** Peripheral PORTD base address */ 106 #define IP_PORTD_BASE (0x4004C000u) 107 /** Peripheral PORTD base pointer */ 108 #define IP_PORTD ((PORT_Type *)IP_PORTD_BASE) 109 /** Peripheral PORTE base address */ 110 #define IP_PORTE_BASE (0x4004D000u) 111 /** Peripheral PORTE base pointer */ 112 #define IP_PORTE ((PORT_Type *)IP_PORTE_BASE) 113 /** Array initializer of PORT peripheral base addresses */ 114 #define IP_PORT_BASE_ADDRS { IP_PORTA_BASE, IP_PORTB_BASE, IP_PORTC_BASE, IP_PORTD_BASE, IP_PORTE_BASE } 115 /** Array initializer of PORT peripheral base pointers */ 116 #define IP_PORT_BASE_PTRS { IP_PORTA, IP_PORTB, IP_PORTC, IP_PORTD, IP_PORTE } 117 118 /* ---------------------------------------------------------------------------- 119 -- PORT Register Masks 120 ---------------------------------------------------------------------------- */ 121 122 /*! 123 * @addtogroup PORT_Register_Masks PORT Register Masks 124 * @{ 125 */ 126 127 /*! @name PCR - Pin Control Register n */ 128 /*! @{ */ 129 130 #define PORT_PCR_PS_MASK (0x1U) 131 #define PORT_PCR_PS_SHIFT (0U) 132 #define PORT_PCR_PS_WIDTH (1U) 133 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 134 135 #define PORT_PCR_PE_MASK (0x2U) 136 #define PORT_PCR_PE_SHIFT (1U) 137 #define PORT_PCR_PE_WIDTH (1U) 138 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 139 140 #define PORT_PCR_PFE_MASK (0x10U) 141 #define PORT_PCR_PFE_SHIFT (4U) 142 #define PORT_PCR_PFE_WIDTH (1U) 143 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 144 145 #define PORT_PCR_DSE_MASK (0x40U) 146 #define PORT_PCR_DSE_SHIFT (6U) 147 #define PORT_PCR_DSE_WIDTH (1U) 148 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 149 150 #define PORT_PCR_MUX_MASK (0x700U) 151 #define PORT_PCR_MUX_SHIFT (8U) 152 #define PORT_PCR_MUX_WIDTH (3U) 153 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 154 155 #define PORT_PCR_LK_MASK (0x8000U) 156 #define PORT_PCR_LK_SHIFT (15U) 157 #define PORT_PCR_LK_WIDTH (1U) 158 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) 159 160 #define PORT_PCR_IRQC_MASK (0xF0000U) 161 #define PORT_PCR_IRQC_SHIFT (16U) 162 #define PORT_PCR_IRQC_WIDTH (4U) 163 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 164 165 #define PORT_PCR_ISF_MASK (0x1000000U) 166 #define PORT_PCR_ISF_SHIFT (24U) 167 #define PORT_PCR_ISF_WIDTH (1U) 168 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 169 /*! @} */ 170 171 /*! @name GPCLR - Global Pin Control Low Register */ 172 /*! @{ */ 173 174 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 175 #define PORT_GPCLR_GPWD_SHIFT (0U) 176 #define PORT_GPCLR_GPWD_WIDTH (16U) 177 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 178 179 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 180 #define PORT_GPCLR_GPWE_SHIFT (16U) 181 #define PORT_GPCLR_GPWE_WIDTH (16U) 182 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 183 /*! @} */ 184 185 /*! @name GPCHR - Global Pin Control High Register */ 186 /*! @{ */ 187 188 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 189 #define PORT_GPCHR_GPWD_SHIFT (0U) 190 #define PORT_GPCHR_GPWD_WIDTH (16U) 191 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 192 193 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 194 #define PORT_GPCHR_GPWE_SHIFT (16U) 195 #define PORT_GPCHR_GPWE_WIDTH (16U) 196 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 197 /*! @} */ 198 199 /*! @name GICLR - Global Interrupt Control Low Register */ 200 /*! @{ */ 201 202 #define PORT_GICLR_GIWE_MASK (0xFFFFU) 203 #define PORT_GICLR_GIWE_SHIFT (0U) 204 #define PORT_GICLR_GIWE_WIDTH (16U) 205 #define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK) 206 207 #define PORT_GICLR_GIWD_MASK (0xFFFF0000U) 208 #define PORT_GICLR_GIWD_SHIFT (16U) 209 #define PORT_GICLR_GIWD_WIDTH (16U) 210 #define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK) 211 /*! @} */ 212 213 /*! @name GICHR - Global Interrupt Control High Register */ 214 /*! @{ */ 215 216 #define PORT_GICHR_GIWE_MASK (0xFFFFU) 217 #define PORT_GICHR_GIWE_SHIFT (0U) 218 #define PORT_GICHR_GIWE_WIDTH (16U) 219 #define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK) 220 221 #define PORT_GICHR_GIWD_MASK (0xFFFF0000U) 222 #define PORT_GICHR_GIWD_SHIFT (16U) 223 #define PORT_GICHR_GIWD_WIDTH (16U) 224 #define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK) 225 /*! @} */ 226 227 /*! @name ISFR - Interrupt Status Flag Register */ 228 /*! @{ */ 229 230 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 231 #define PORT_ISFR_ISF_SHIFT (0U) 232 #define PORT_ISFR_ISF_WIDTH (32U) 233 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 234 /*! @} */ 235 236 /*! @name DFER - Digital Filter Enable Register */ 237 /*! @{ */ 238 239 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) 240 #define PORT_DFER_DFE_SHIFT (0U) 241 #define PORT_DFER_DFE_WIDTH (32U) 242 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) 243 /*! @} */ 244 245 /*! @name DFCR - Digital Filter Clock Register */ 246 /*! @{ */ 247 248 #define PORT_DFCR_CS_MASK (0x1U) 249 #define PORT_DFCR_CS_SHIFT (0U) 250 #define PORT_DFCR_CS_WIDTH (1U) 251 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) 252 /*! @} */ 253 254 /*! @name DFWR - Digital Filter Width Register */ 255 /*! @{ */ 256 257 #define PORT_DFWR_FILT_MASK (0x1FU) 258 #define PORT_DFWR_FILT_SHIFT (0U) 259 #define PORT_DFWR_FILT_WIDTH (5U) 260 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) 261 /*! @} */ 262 263 /*! 264 * @} 265 */ /* end of group PORT_Register_Masks */ 266 267 /*! 268 * @} 269 */ /* end of group PORT_Peripheral_Access_Layer */ 270 271 #endif /* #if !defined(S32K116_PORT_H_) */ 272
