1 /*!
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * \file KW4xXcvrDrv.c
6 * This is a source file for the transceiver driver.
7 *
8 * Redistribution and use in source and binary forms, with or without modification,
9 * are permitted provided that the following conditions are met:
10 *
11 * o Redistributions of source code must retain the above copyright notice, this list
12 * of conditions and the following disclaimer.
13 *
14 * o Redistributions in binary form must reproduce the above copyright notice, this
15 * list of conditions and the following disclaimer in the documentation and/or
16 * other materials provided with the distribution.
17 *
18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
19 * contributors may be used to endorse or promote products derived from this
20 * software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*! *********************************************************************************
35 *************************************************************************************
36 * Include
37 *************************************************************************************
38 ********************************************************************************** */
39 #include "BLEDefaults.h"
40 #include "ZigbeeDefaults.h"
41 #include "KW4xXcvrDrv.h"
42 #include "fsl_os_abstraction.h"
43 #include "fsl_device_registers.h"
44
45 #include "tsm_ll_timing.h"
46 #include "ifr_mkw40z4_radio.h"
47
48 #if !USE_DCOC_MAGIC_NUMBERS
49 #include <math.h>
50 #endif
51
52 #ifdef gXcvrXtalTrimEnabled_d
53 #include "Flash_Adapter.h"
54 #endif
55
56 #define INCLUDE_OLD_DRV_CODE (0)
57 #define wait(param) while(param)
58 #define ASSERT(condition) if(condition) while(1);
59
60 /*! *********************************************************************************
61 *************************************************************************************
62 * Private type definitions
63 *************************************************************************************
64 ********************************************************************************** */
65 typedef enum
66 {
67 FIRST_INIT = 0,
68 MODE_CHANGE = 1
69 } MODE_CHG_SEL_T;
70
71 /*! *********************************************************************************
72 *************************************************************************************
73 * Private memory declarations
74 *************************************************************************************
75 ********************************************************************************** */
76 /* Channel Filter coeff for BLE */
77 const uint8_t gBLERxChfCoeff[8] = {
78 RX_CHF_COEF0_def_c,
79 RX_CHF_COEF1_def_c,
80 RX_CHF_COEF2_def_c,
81 RX_CHF_COEF3_def_c,
82 RX_CHF_COEF4_def_c,
83 RX_CHF_COEF5_def_c,
84 RX_CHF_COEF6_def_c,
85 RX_CHF_COEF7_def_c
86 };
87
88 /* Channel Filter coeff for Zigbee */
89 const uint8_t gZigbeeRxChfCoeff[8] = {
90 RX_CHF_COEF0_Zigbee_def_c,
91 RX_CHF_COEF1_Zigbee_def_c,
92 RX_CHF_COEF2_Zigbee_def_c,
93 RX_CHF_COEF3_Zigbee_def_c,
94 RX_CHF_COEF4_Zigbee_def_c,
95 RX_CHF_COEF5_Zigbee_def_c,
96 RX_CHF_COEF6_Zigbee_def_c,
97 RX_CHF_COEF7_Zigbee_def_c,
98 };
99
100 const uint8_t gPABiasTbl[8] = PA_BIAS_ENTRIES; /* See tsm_timing_ble.h for PA_BIAS_ENTRIES */
101 panic_fptr panic_function_ptr = NULL;
102 uint8_t panic_fptr_is_valid = 0; /* Flag to store validity of the panic function pointer */
103 static uint8_t gen1_dcgain_trims_enabled = 0;
104 static uint8_t HWDCoffsetCal = 0;
105 static uint32_t trim_status = 0xFFFF; /* Status of trims from IFR, default to all failed */
106 static uint16_t ifr_version = 0xFFFF; /* IFR data format version number, default to maxint. */
107
108 /*! *********************************************************************************
109 *************************************************************************************
110 * Public memory declarations
111 *************************************************************************************
112 ********************************************************************************** */
113 const pllChannel_t mapTable [channelMapTableSize] =
114 {
115 {0x00000025, 0x07C00000}, /* 0 */
116 {0x00000025, 0x07C80000}, /* 1 */
117 {0x00000025, 0x07D00000}, /* 2 */
118 {0x00000025, 0x07D80000}, /* 3 */
119 {0x00000025, 0x07E00000}, /* 4 */
120 {0x00000025, 0x07E80000}, /* 5 */
121 {0x00000025, 0x07F00000}, /* 6 */
122 {0x00000025, 0x07F80000}, /* 7 */
123 {0x00000025, 0x00000000}, /* 8 */
124 {0x00000025, 0x00080000}, /* 9 */
125 {0x00000025, 0x00100000}, /* 10 */
126 {0x00000025, 0x00180000}, /* 11 */
127 {0x00000025, 0x00200000}, /* 12 */
128 {0x00000025, 0x00280000}, /* 13 */
129 {0x00000025, 0x00300000}, /* 14 */
130 {0x00000025, 0x00380000}, /* 15 */
131 {0x00000025, 0x00400000}, /* 16 */
132 {0x00000025, 0x00480000}, /* 17 */
133 {0x00000025, 0x00500000}, /* 18 */
134 {0x00000025, 0x00580000}, /* 19 */
135 {0x00000025, 0x00600000}, /* 20 */
136 {0x00000025, 0x00680000}, /* 21 */
137 {0x00000025, 0x00700000}, /* 22 */
138 {0x00000025, 0x00780000}, /* 23 */
139 {0x00000025, 0x00800000}, /* 24 */
140 {0x00000025, 0x00880000}, /* 25 */
141 {0x00000025, 0x00900000}, /* 26 */
142 {0x00000025, 0x00980000}, /* 27 */
143 {0x00000025, 0x00A00000}, /* 28 */
144 {0x00000025, 0x00A80000}, /* 29 */
145 {0x00000025, 0x00B00000}, /* 30 */
146 {0x00000025, 0x00B80000}, /* 31 */
147 {0x00000025, 0x00C00000}, /* 32 */
148 {0x00000025, 0x00C80000}, /* 33 */
149 {0x00000025, 0x00D00000}, /* 34 */
150 {0x00000025, 0x00D80000}, /* 35 */
151 {0x00000025, 0x00E00000}, /* 36 */
152 {0x00000025, 0x00E80000}, /* 37 */
153 {0x00000025, 0x00F00000}, /* 38 */
154 {0x00000025, 0x00F80000}, /* 39 */
155 {0x00000025, 0x01000000}, /* 40 */
156 {0x00000026, 0x07080000}, /* 41 */
157 {0x00000026, 0x07100000}, /* 42 */
158 {0x00000026, 0x07180000}, /* 43 */
159 {0x00000026, 0x07200000}, /* 44 */
160 {0x00000026, 0x07280000}, /* 45 */
161 {0x00000026, 0x07300000}, /* 46 */
162 {0x00000026, 0x07380000}, /* 47 */
163 {0x00000026, 0x07400000}, /* 48 */
164 {0x00000026, 0x07480000}, /* 49 */
165 {0x00000026, 0x07500000}, /* 50 */
166 {0x00000026, 0x07580000}, /* 51 */
167 {0x00000026, 0x07600000}, /* 52 */
168 {0x00000026, 0x07680000}, /* 53 */
169 {0x00000026, 0x07700000}, /* 54 */
170 {0x00000026, 0x07780000}, /* 55 */
171 {0x00000026, 0x07800000}, /* 56 */
172 {0x00000026, 0x07880000}, /* 57 */
173 {0x00000026, 0x07900000}, /* 58 */
174 {0x00000026, 0x07980000}, /* 59 */
175 {0x00000026, 0x07A00000}, /* 60 */
176 {0x00000026, 0x07A80000}, /* 61 */
177 {0x00000026, 0x07B00000}, /* 62 */
178 {0x00000026, 0x07B80000}, /* 63 */
179 {0x00000026, 0x07C00000}, /* 64 */
180 {0x00000026, 0x07C80000}, /* 65 */
181 {0x00000026, 0x07D00000}, /* 66 */
182 {0x00000026, 0x07D80000}, /* 67 */
183 {0x00000026, 0x07E00000}, /* 68 */
184 {0x00000026, 0x07E80000}, /* 69 */
185 {0x00000026, 0x07F00000}, /* 70 */
186 {0x00000026, 0x07F80000}, /* 71 */
187 {0x00000026, 0x00000000}, /* 72 */
188 {0x00000026, 0x00080000}, /* 73 */
189 {0x00000026, 0x00100000}, /* 74 */
190 {0x00000026, 0x00180000}, /* 75 */
191 {0x00000026, 0x00200000}, /* 76 */
192 {0x00000026, 0x00280000}, /* 77 */
193 {0x00000026, 0x00300000}, /* 78 */
194 {0x00000026, 0x00380000}, /* 79 */
195 {0x00000026, 0x00400000}, /* 80 */
196 {0x00000026, 0x00480000}, /* 81 */
197 {0x00000026, 0x00500000}, /* 82 */
198 {0x00000026, 0x00580000}, /* 83 */
199 {0x00000026, 0x00600000}, /* 84 */
200 {0x00000026, 0x00680000}, /* 85 */
201 {0x00000026, 0x00700000}, /* 86 */
202 {0x00000026, 0x00780000}, /* 87 */
203 {0x00000026, 0x00800000}, /* 88 */
204 {0x00000026, 0x00880000}, /* 89 */
205 {0x00000026, 0x00900000}, /* 90 */
206 {0x00000026, 0x00980000}, /* 91 */
207 {0x00000026, 0x00A00000}, /* 92 */
208 {0x00000026, 0x00A80000}, /* 93 */
209 {0x00000026, 0x00B00000}, /* 94 */
210 {0x00000026, 0x00B80000}, /* 95 */
211 {0x00000026, 0x00C00000}, /* 96 */
212 {0x00000026, 0x00C80000}, /* 97 */
213 {0x00000026, 0x00D00000}, /* 98 */
214 {0x00000026, 0x00D80000}, /* 99 */
215 {0x00000026, 0x00E00000}, /* 100 */
216 {0x00000026, 0x00E80000}, /* 101 */
217 {0x00000026, 0x00F00000}, /* 102 */
218 {0x00000026, 0x00F80000}, /* 103 */
219 {0x00000026, 0x01000000}, /* 104 */
220 {0x00000027, 0x07080000}, /* 105 */
221 {0x00000027, 0x07100000}, /* 106 */
222 {0x00000027, 0x07180000}, /* 107 */
223 {0x00000027, 0x07200000}, /* 108 */
224 {0x00000027, 0x07280000}, /* 109 */
225 {0x00000027, 0x07300000}, /* 110 */
226 {0x00000027, 0x07380000}, /* 111 */
227 {0x00000027, 0x07400000}, /* 112 */
228 {0x00000027, 0x07480000}, /* 113 */
229 {0x00000027, 0x07500000}, /* 114 */
230 {0x00000027, 0x07580000}, /* 115 */
231 {0x00000027, 0x07600000}, /* 116 */
232 {0x00000027, 0x07680000}, /* 117 */
233 {0x00000027, 0x07700000}, /* 118 */
234 {0x00000027, 0x07780000}, /* 119 */
235 {0x00000027, 0x07800000}, /* 120 */
236 {0x00000027, 0x07880000}, /* 121 */
237 {0x00000027, 0x07900000}, /* 122 */
238 {0x00000027, 0x07980000}, /* 123 */
239 {0x00000027, 0x07A00000}, /* 124 */
240 {0x00000027, 0x07A80000}, /* 125 */
241 {0x00000027, 0x07B00000}, /* 126 */
242 {0x00000027, 0x07B80000} /* 127 */
243 };
244
245 /* Following are software trimmed values. They are initialized to potential
246 * blind trim values with the intent that IFR trims overwrite these blind
247 * trim values
248 */
249 float adc_gain_trimmed = ADC_SCALE_FACTOR;
250 uint8_t zb_tza_cap_tune = ZGBE_TZA_CAP_TUNE_def_c;
251 uint8_t zb_bbf_cap_tune = ZGBE_BBF_CAP_TUNE_def_c;
252 uint8_t zb_bbf_res_tune2 = ZGBE_BBF_RES_TUNE2_def_c;
253 uint8_t ble_tza_cap_tune = BLE_TZA_CAP_TUNE_def_c;
254 uint8_t ble_bbf_cap_tune = BLE_BBF_CAP_TUNE_def_c;
255 uint8_t ble_bbf_res_tune2 = BLE_BBF_RES_TUNE2_def_c;
256
257 /*! *********************************************************************************
258 *************************************************************************************
259 * Private prototypes
260 *************************************************************************************
261 ********************************************************************************** */
262 /* Common initialization and mode change routine, called by XcvrInit() and XcvRModeChange() */
263 void XcvrInit_ModeChg_Common ( radio_mode_t radioMode, MODE_CHG_SEL_T mode_change );
264
265 xcvrStatus_t XcvrCalcSetupDcoc ( void );
266 void XcvrManualDCOCCal (uint8_t chnum);
267
268 void XcvrSetTsmDefaults ( radio_mode_t radioMode );
269 void XcvrSetRxDigDefaults ( const uint8_t * filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src );
270 void XcvrSetTxDigPLLDefaults( radio_mode_t radioMode );
271 void XcvrSetAnalogDefaults ( radio_mode_t radioMode );
272
273 /* Separate out Mode Switch portion of init routines
274 * call these routines with the target mode during a mode switch
275 */
276 void XcvrSetTsmDef_ModeSwitch ( radio_mode_t radioMode );
277 void XcvrSetRxDigDef_ModeSwitch ( const uint8_t * filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src );
278 void XcvrSetTxDigPLLDef_ModeSwitch( radio_mode_t radioMode );
279 void XcvrSetAnalogDef_ModeSwitch ( radio_mode_t radioMode );
280
281 void XcvrPanic (uint32_t panic_id, uint32_t location);
282 void XcvrDelay(uint32_t time);
283
284 /*! *********************************************************************************
285 *************************************************************************************
286 * Public functions
287 *************************************************************************************
288 ********************************************************************************** */
289
290 /*! *********************************************************************************
291 * \brief This function initializes the transceiver for operation in a particular
292 * radioMode (BLE or Zigbee)
293 *
294 * \param[in] radioMode - the operating mode to which the radio should be initialized.
295 *
296 * \ingroup PublicAPIs
297 *
298 * \details
299 *
300 ***********************************************************************************/
XcvrInit(radio_mode_t radioMode)301 void XcvrInit ( radio_mode_t radioMode )
302 {
303 XcvrInit_ModeChg_Common(radioMode,FIRST_INIT);
304 #ifdef gXcvrXtalTrimEnabled_d
305 if( 0xFFFFFFFF != gHardwareParameters.xtalTrim )
306 {
307 XcvrSetXtalTrim( (uint8_t)gHardwareParameters.xtalTrim );
308 }
309 #endif
310 }
311
312 /*! *********************************************************************************
313 * \brief This function changes the radio operating mode between BLE and Zigbee
314 *
315 * \param[in] radioMode - the new operating mode for the radio
316 *
317 * \ingroup PublicAPIs
318 *
319 * \details
320 *
321 ***********************************************************************************/
XcvrChangeMode(radio_mode_t radioMode)322 xcvrStatus_t XcvrChangeMode ( radio_mode_t radioMode )
323 {
324 XcvrInit_ModeChg_Common(radioMode, MODE_CHANGE);
325 return gXcvrSuccess_c;
326 }
327
328 /*! *********************************************************************************
329 * \brief This function allows a callback function to be registered allowing the
330 * transceiver software to call a PANIC function in case of software error
331 *
332 * \param[in] fptr - a pointer to a function which implements system PANIC
333 *
334 * \ingroup PublicAPIs
335 *
336 * \details
337 *
338 ***********************************************************************************/
XcvrRegisterPanicCb(panic_fptr fptr)339 void XcvrRegisterPanicCb ( panic_fptr fptr )
340 {
341 panic_function_ptr = fptr;
342 panic_fptr_is_valid = 1;
343 }
344
345 /*! *********************************************************************************
346 * \brief This function allows a upper layer software to poll the health of the
347 * transceiver to detect problems in the radio operation.
348 *
349 * \return radio_status - current status of the radio, 0 = no failures. Any other
350 * value indicates a failure, see ::healthStatus_t for the possible values
351 * which may all be OR'd together as needed.
352 *
353 * \ingroup PublicAPIs
354 *
355 * \details
356 *
357 ***********************************************************************************/
XcvrHealthCheck(void)358 healthStatus_t XcvrHealthCheck ( void )
359 {
360 healthStatus_t retval = NO_ERRORS;
361 /* Read PLL status bits and set return values */
362 if (XCVR_BRD_PLL_LOCK_DETECT_CTFF(XCVR) == 1)
363 {
364 retval |= PLL_CTUNE_FAIL;
365 }
366 if (XCVR_BRD_PLL_LOCK_DETECT_CSFF(XCVR) == 1)
367 {
368 retval |= PLL_CYCLE_SLIP_FAIL;
369 }
370 if (XCVR_BRD_PLL_LOCK_DETECT_FTFF(XCVR) == 1)
371 {
372 retval |= PLL_FREQ_TARG_FAIL;
373 }
374 if (XCVR_BRD_PLL_LOCK_DETECT_TAFF(XCVR) == 1)
375 {
376 retval |= PLL_TSM_ABORT_FAIL;
377 }
378 /* Once errors have been captured, clear the sticky flags.
379 * Sticky bits are W1C so this clears them.
380 */
381 XCVR_PLL_LOCK_DETECT = (uint32_t)(XCVR_PLL_LOCK_DETECT);
382 return retval;
383 }
384
385 /*! *********************************************************************************
386 * \brief This function allows a upper layer software to control the state of the
387 * Fast Antenna Diversity (FAD) and Low Power Preamble Search (LPPS) features for
388 * the Zigbee radio.
389 *
390 * \param control - desired setting for combined FAD/LPPS feature.
391 *
392 * \ingroup PublicAPIs
393 *
394 * \details
395 * FAD and LPPS are mutually exclusive features, they cannot be enabled at
396 * the same time so this API enforces that restriction.
397 * This API only controls the transceiver functionality related to FAD and
398 * LPPS, it does not affect any link layer functionality that may be required.
399 * \note
400 * This code does NOT set the pin muxing for the GPIO pins required for this
401 * feature. TSM_GPIO2 and TSM_GPIO3 pins are used for TX and RX respectively.
402 ***********************************************************************************/
XcvrFadLppsControl(FAD_LPPS_CTRL_T control)403 void XcvrFadLppsControl(FAD_LPPS_CTRL_T control)
404 {
405 switch (control)
406 {
407 case NONE:
408 /* Disable FAD */
409 XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */
410 XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */
411 /* Disable LPPS */
412 XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(XCVR, 0);
413 break;
414 case FAD_ENABLED:
415 /* Enable FAD */
416 XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, END_OF_TX_WU_BLE));
417 XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, END_OF_RX_WU_BLE, 0xFF, 0xFF));
418 /* Disable LPPS */
419 XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(XCVR, 0);
420 break;
421 case LPPS_ENABLED:
422 /* Disable FAD */
423 XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */
424 XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */
425 /* Enable LPPS */
426 XCVR_LPPS_CTRL = (uint32_t)(XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_MASK |
427 XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_MASK |
428 XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_MASK |
429 XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_MASK |
430 XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_MASK |
431 XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_MASK |
432 XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_MASK
433 );
434 XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(XCVR, 1);
435 break;
436 default:
437 /* PANIC? */
438 break;
439 }
440 }
441
442 /*! *********************************************************************************
443 * \brief This function calls the system panic function for radio errors.
444 *
445 * \param[in] panic_id The identifier for the radio error.
446 * \param[in] location The location (address) in the code where the error happened.
447 *
448 *
449 * \ingroup PrivateAPIs
450 *
451 * \details This function is a common flow for both first init of the radio as well as
452 * mode change of the radio.
453 *
454 ***********************************************************************************/
XcvrPanic(uint32_t panic_id,uint32_t location)455 void XcvrPanic (uint32_t panic_id, uint32_t location)
456 {
457 if (panic_fptr_is_valid)
458 {
459 (*panic_function_ptr)(panic_id, location, (uint32_t)0, (uint32_t)0);
460 }
461 else
462 {
463 while(1); /* No panic function registered. */
464 }
465 }
466
467 /*! *********************************************************************************
468 * \brief This function initializes or changes the mode of the transceiver.
469 *
470 * \param[in] radioMode The target operating mode of the radio.
471 * \param[in] mode_change Whether this is an initialization or a mode change (FIRST_INIT == Init, MODE_CHANGE==mode change).
472 *
473 *
474 * \ingroup PrivateAPIs
475 *
476 * \details This function is a common flow for both first init of the radio as well as
477 * mode change of the radio.
478 *
479 ***********************************************************************************/
XcvrInit_ModeChg_Common(radio_mode_t radioMode,MODE_CHG_SEL_T mode_change)480 void XcvrInit_ModeChg_Common ( radio_mode_t radioMode, MODE_CHG_SEL_T mode_change )
481 {
482 static radio_mode_t last_mode = INVALID_MODE;
483
484 uint8_t osr;
485 uint8_t norm_en;
486 uint8_t chf_bypass;
487 IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] =
488 {
489 {ADC_GAIN, 0, FALSE}, /* Fetch the ADC GAIN parameter if available. */
490 {ZB_FILT_TRIM, 0, FALSE}, /* Fetch the Zigbee BBW filter trim if available. */
491 {BLE_FILT_TRIM, 0, FALSE}, /* Fetch the BLE BBW filter trim if available. */
492 {TRIM_STATUS, 0, FALSE}, /* Fetch the trim status word if available. */
493 {TRIM_VERSION, 0, FALSE} /* Fetch the trim version number if available. */
494 };
495
496 #define NUM_TRIM_TBL_ENTRIES sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T)
497
498 if( radioMode == last_mode )
499 {
500 return;
501 }
502 else
503 {
504 last_mode = radioMode;
505 }
506
507 /* Check that this is the proper chip version */
508 if ((RSIM_ANA_TEST >> 24) & 0xF != 0x2)
509 {
510 XcvrPanic(WRONG_RADIO_ID_DETECTED,(uint32_t)&XcvrInit_ModeChg_Common);
511 }
512
513
514 /* Enable XCVR_DIG, LTC and DCDC clock always, independent of radio mode.
515 * Only enable one of BTLL or Zigbee.
516 */
517 switch (radioMode)
518 {
519 case BLE:
520 SIM_SCGC5 |= SIM_SCGC5_BTLL_MASK | SIM_SCGC5_PHYDIG_MASK;
521 break;
522 case ZIGBEE:
523 SIM_SCGC5 |= SIM_SCGC5_ZigBee_MASK | SIM_SCGC5_PHYDIG_MASK;
524 break;
525 default:
526 break;
527 }
528
529 HWDCoffsetCal = 0; /* Default to using SW DCOC calibration */
530
531 gen1_dcgain_trims_enabled = 0;
532 handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES);
533
534 /* Transfer values from sw_trim_tbl[] to static variables used in radio operation */
535 {
536 uint16_t i;
537 for (i=0;i<NUM_TRIM_TBL_ENTRIES;i++)
538 {
539 if (sw_trim_tbl[i].valid == TRUE)
540 {
541 switch (sw_trim_tbl[i].trim_id)
542 {
543 /* ADC_GAIN */
544 case ADC_GAIN:
545 adc_gain_trimmed = (float)sw_trim_tbl[i].trim_value/(float)(0x400);
546 gen1_dcgain_trims_enabled = 1; /* Only enable code that handles these trims if the ADC_GAIN is present. */
547 break;
548 /* ZB_FILT_TRIM */
549 case ZB_FILT_TRIM:
550 zb_tza_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_TZA_CAP_TUNE_MASK)>>IFR_TZA_CAP_TUNE_SHIFT);
551 zb_bbf_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_BBF_CAP_TUNE_MASK)>>IFR_BBF_CAP_TUNE_SHIFT);
552 zb_bbf_res_tune2 = ((sw_trim_tbl[i].trim_value & IFR_RES_TUNE2_MASK)>>IFR_RES_TUNE2_SHIFT);
553 break;
554 /* BLE_FILT_TRIM */
555 case BLE_FILT_TRIM:
556 ble_tza_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_TZA_CAP_TUNE_MASK)>>IFR_TZA_CAP_TUNE_SHIFT);
557 ble_bbf_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_BBF_CAP_TUNE_MASK)>>IFR_BBF_CAP_TUNE_SHIFT);
558 ble_bbf_res_tune2 = ((sw_trim_tbl[i].trim_value & IFR_RES_TUNE2_MASK)>>IFR_RES_TUNE2_SHIFT);
559 break;
560 case TRIM_STATUS:
561 trim_status = sw_trim_tbl[i].trim_value;
562 break;
563 case TRIM_VERSION:
564 ifr_version = sw_trim_tbl[i].trim_value & 0xFFFF;
565 break;
566 default:
567 break;
568 }
569 }
570 }
571 }
572
573 {
574 static uint32_t tempstatus = 0;
575 tempstatus = (trim_status & (BGAP_VOLTAGE_TRIM_FAILED | IQMC_GAIN_ADJ_FAILED | IQMC_GAIN_ADJ_FAILED | IQMC_DC_GAIN_ADJ_FAILED));
576 /* Determine whether this IC can support HW DC Offset Calibration.
577 * Must be v3 or greater trim version and != 0xFFFF
578 * Must have BGAP, IQMC and IQ DC GAIN calibration SUCCESS
579 * OR - may be over-ridden by a compile time flag to force HW DCOC cal
580 */
581 if (((ifr_version >= 3) &&
582 (ifr_version != 0xFFFF) &&
583 (ifr_version != 0xFFFE) && /* Special version number indicating fallback IFR table used due to untrimmed part. */
584 (tempstatus == 0)) ||
585 (ENGINEERING_TRIM_BYPASS))
586 {
587 HWDCoffsetCal = 1;
588 }
589 }
590
591 XCVR_BWR_BGAP_CTRL_BGAP_ATST_ON(XCVR, 0);
592
593 if (mode_change == MODE_CHANGE)
594 {
595 /* Change only mode dependent analog & TSM settings */
596 XcvrSetAnalogDef_ModeSwitch(radioMode);
597 XcvrSetTsmDef_ModeSwitch(radioMode);
598 }
599 else
600 {
601 /* Setup initial analog & TSM settings */
602 XcvrSetAnalogDefaults(radioMode);
603 XcvrSetTsmDefaults(radioMode);
604 }
605
606 /* RX Channel filter coeffs and TSM settings are specific to modes */
607 switch (radioMode)
608 {
609 case BLE:
610 if (mode_change == MODE_CHANGE)
611 {
612 XcvrSetRxDigDef_ModeSwitch(&gBLERxChfCoeff[0], DCOC_CAL_IIR3A_IDX_def_c, DCOC_CAL_IIR2A_IDX_def_c, DCOC_CAL_IIR1A_IDX_def_c, RSSI_HOLD_SRC_def_c);
613 }
614 else
615 {
616 XcvrSetRxDigDefaults(&gBLERxChfCoeff[0], DCOC_CAL_IIR3A_IDX_def_c, DCOC_CAL_IIR2A_IDX_def_c, DCOC_CAL_IIR1A_IDX_def_c, RSSI_HOLD_SRC_def_c);
617 }
618 XCVR_BWR_CTRL_PROTOCOL(XCVR, BLE_PROTOCOL_def_c); /* BLE protocol selection */
619 XCVR_BWR_CTRL_TGT_PWR_SRC(XCVR, BLE_TGT_PWR_SRC_def_c);
620 XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(XCVR, FREEZE_AGC_SRC_def_c); /* Freeze AGC */
621 osr = RX_DEC_FILT_OSR_BLE_def_c; /* OSR 4 */
622 norm_en = RX_NORM_EN_BLE_def_c; /* Normalizer OFF */
623 chf_bypass = RX_CH_FILT_BYPASS_def_c; /* BLE Channel filter setting */
624
625 /* DCOC_CTRL_0 & RX_DIG_CTRL settings done separately from other RX_DIG*/
626 /* DCOC_CTRL_0 */
627 XCVR_DCOC_CTRL_0 = (uint32_t)(
628 (ALPHAC_SCALE_IDX_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT) |
629 (ALPHA_RADIUS_IDX_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT) |
630 (SIGN_SCALE_IDX_def_c << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT) |
631 (DCOC_CAL_DURATION_def_c << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT) |
632 (DCOC_CORR_DLY_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT) |
633 (DCOC_CORR_HOLD_TIME_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT) |
634 (DCOC_MAN_def_c << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) |
635 (DCOC_TRACK_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) |
636 (DCOC_CORRECT_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)
637 );
638 break;
639 case ZIGBEE:
640 if (mode_change == MODE_CHANGE)
641 {
642 XcvrSetRxDigDef_ModeSwitch(&gZigbeeRxChfCoeff[0], IIR3A_IDX_Zigbee_def_c, IIR2A_IDX_Zigbee_def_c, IIR1A_IDX_Zigbee_def_c, RSSI_HOLD_SRC_Zigbee_def_c);
643 }
644 else
645 {
646 XcvrSetRxDigDefaults(&gZigbeeRxChfCoeff[0], IIR3A_IDX_Zigbee_def_c, IIR2A_IDX_Zigbee_def_c, IIR1A_IDX_Zigbee_def_c, RSSI_HOLD_SRC_Zigbee_def_c);
647 }
648 XCVR_BWR_CTRL_PROTOCOL(XCVR, Zigbee_PROTOCOL_def_c); /* Zigbee protocol selection */
649 XCVR_BWR_CTRL_TGT_PWR_SRC(XCVR, Zigbee_TGT_PWR_SRC_def_c);
650 XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(XCVR, FREEZE_AGC_SRC_Zigbee_def_c); /* Freeze AGC */
651 /* Correlation zero count for Zigbee preamble detection */
652 XCVR_BWR_CORR_CTRL_CORR_NVAL(XCVR, CORR_NVAL_Zigbee_def_c);
653 /* Correlation threshold */
654 XCVR_BWR_CORR_CTRL_CORR_VT(XCVR, CORR_VT_Zigbee_def_c);
655 osr = RX_DEC_FILT_OSR_Zigbee_def_c; /* OSR 8 */
656 norm_en = RX_NORM_EN_Zigbee_def_c; /* Normalizer On */
657 chf_bypass = RX_CH_FILT_BYPASS_Zigbee_def_c; /* Zigbee Channel filter setting */
658
659 /* DCOC_CTRL_0 & RX_DIG_CTRL settings done separately from other RX_DIG*/
660 /* DCOC_CTRL_0 */
661 XCVR_DCOC_CTRL_0 = (uint32_t)(
662 (ALPHAC_SCALE_IDX_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT) |
663 (ALPHA_RADIUS_IDX_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT) |
664 (SIGN_SCALE_IDX_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT) |
665 (DCOC_CAL_DURATION_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT) |
666 (DCOC_CORR_DLY_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT) |
667 (DCOC_CORR_HOLD_TIME_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT) |
668 (DCOC_MAN_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) |
669 (DCOC_TRACK_EN_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) |
670 (DCOC_CORRECT_EN_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)
671 );
672 break;
673 default:
674 break;
675 }
676
677 if (mode_change == MODE_CHANGE)
678 {
679 XcvrSetTxDigPLLDef_ModeSwitch(radioMode);
680 }
681 else
682 {
683 XcvrSetTxDigPLLDefaults(radioMode);
684 }
685
686 XCVR_DCOC_CTRL_0 = (uint32_t)((XCVR_DCOC_CTRL_0 & (uint32_t)~(uint32_t)(
687 XCVR_DCOC_CTRL_0_DCOC_MAN_MASK |
688 XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_MASK |
689 XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK
690 )) | (uint32_t)(
691 (DCOC_MAN_def_c << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) |
692 (DCOC_TRACK_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) |
693 (DCOC_CORRECT_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)
694 ));
695
696 /* DCOC_CTRL_0 & RX_DIG_CTRL settings done separately from other RX_DIG*/
697 /* RX_DIG_CTRL */
698 XCVR_RX_DIG_CTRL = (uint32_t)((XCVR_RX_DIG_CTRL & (uint32_t)~(uint32_t)(
699 XCVR_RX_DIG_CTRL_RX_RSSI_EN_MASK |
700 XCVR_RX_DIG_CTRL_RX_AGC_EN_MASK |
701 XCVR_RX_DIG_CTRL_RX_DCOC_EN_MASK |
702 XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK |
703 XCVR_RX_DIG_CTRL_RX_NORM_EN_MASK |
704 XCVR_RX_DIG_CTRL_RX_INTERP_EN_MASK |
705 XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK |
706 XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK
707 )) | (uint32_t)(
708 (RX_RSSI_EN_def_c << XCVR_RX_DIG_CTRL_RX_RSSI_EN_SHIFT) |
709 (RX_AGC_EN_def_c << XCVR_RX_DIG_CTRL_RX_AGC_EN_SHIFT) |
710 (RX_DCOC_EN_def_c << XCVR_RX_DIG_CTRL_RX_DCOC_EN_SHIFT) |
711 (osr << XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT) |
712 (norm_en << XCVR_RX_DIG_CTRL_RX_NORM_EN_SHIFT) |
713 (RX_INTERP_EN_def_c << XCVR_RX_DIG_CTRL_RX_INTERP_EN_SHIFT) |
714 (chf_bypass << XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT) |
715 (0 << XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT) /* DCOC_CAL_EN set to zero here, changed below if appropriate */
716 ));
717
718 if (HWDCoffsetCal)
719 {
720 XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(XCVR, 1); /* DCOC_CAL 1=Enabled */
721 }
722 else
723 {
724 /* DCOC Calibration issue workaround. Performs a manual DCOC calibration and disables RX_DCOC_CAL_EN
725 * Manipulates AGC settings during the calibration and then reverts them
726 */
727 if (mode_change == FIRST_INIT)
728 {
729 switch (radioMode)
730 {
731 case BLE:
732 XcvrManualDCOCCal(20); /* Use channel 20 for BLE calibration @ ~mid-band */
733 break;
734 case ZIGBEE:
735 XcvrManualDCOCCal(18); /* Use channel 18 for Zigbee calibration @ ~mid-band */
736 break;
737 default:
738 break;
739 }
740 }
741 }
742 }
743
744 /*! *********************************************************************************
745 * \brief This function sets the default vaues of the TSM registers.
746 *
747 * \param[in] radioMode Radio mode is used to enable mode specific settings.
748 *
749 * \ingroup PrivateAPIs
750 *
751 * \details This function also sets link layer registers to account for TX and
752 * delays.
753 *
754 ***********************************************************************************/
XcvrSetTsmDefaults(radio_mode_t radioMode)755 void XcvrSetTsmDefaults ( radio_mode_t radioMode )
756 {
757 /*TSM_CTRL*/
758 XCVR_TSM_CTRL = (uint32_t)((XCVR_TSM_CTRL & (uint32_t)~(uint32_t)(
759 XCVR_TSM_CTRL_BKPT_MASK |
760 XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK |
761 XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK |
762 XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK |
763 XCVR_TSM_CTRL_RX_ABORT_DIS_MASK |
764 XCVR_TSM_CTRL_TX_ABORT_DIS_MASK |
765 XCVR_TSM_CTRL_DATA_PADDING_EN_MASK |
766 XCVR_TSM_CTRL_PA_RAMP_SEL_MASK |
767 XCVR_TSM_CTRL_FORCE_RX_EN_MASK |
768 XCVR_TSM_CTRL_FORCE_TX_EN_MASK
769 )) | (uint32_t)(
770 (BKPT_def_c << XCVR_TSM_CTRL_BKPT_SHIFT) |
771 (ABORT_ON_FREQ_TARG_def_c << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT) |
772 (ABORT_ON_CYCLE_SLIP_def_c << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT) |
773 (ABORT_ON_CTUNE_def_c << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT) |
774 (RX_ABORT_DIS_def_c << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT) |
775 (TX_ABORT_DIS_def_c << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT) |
776 (DATA_PADDING_EN_def_c << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT) |
777 (PA_RAMP_SEL_def_c << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT) |
778 (FORCE_RX_EN_def_c << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT) |
779 (FORCE_TX_EN_def_c << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)
780 ));
781
782 /* Perform mode specific portion of TSM setup using mode switch routine */
783 XcvrSetTsmDef_ModeSwitch(radioMode);
784
785 /* Only init OVRD registers if a non-default setting is needed */
786 /*PA_POWER*/
787 XCVR_BWR_PA_POWER_PA_POWER(XCVR, PA_POWER_def_c);
788
789 /*PA_BIAS_TBL0*/
790 XCVR_PA_BIAS_TBL0 = (uint32_t)((XCVR_PA_BIAS_TBL0 & (uint32_t)~(uint32_t)(
791 XCVR_PA_BIAS_TBL0_PA_BIAS3_MASK |
792 XCVR_PA_BIAS_TBL0_PA_BIAS2_MASK |
793 XCVR_PA_BIAS_TBL0_PA_BIAS1_MASK |
794 XCVR_PA_BIAS_TBL0_PA_BIAS0_MASK
795 )) | (uint32_t)(
796 (gPABiasTbl[3] << XCVR_PA_BIAS_TBL0_PA_BIAS3_SHIFT) |
797 (gPABiasTbl[2] << XCVR_PA_BIAS_TBL0_PA_BIAS2_SHIFT) |
798 (gPABiasTbl[1] << XCVR_PA_BIAS_TBL0_PA_BIAS1_SHIFT) |
799 (gPABiasTbl[0] << XCVR_PA_BIAS_TBL0_PA_BIAS0_SHIFT)
800 ));
801
802 /*PA_BIAS_TBL1*/
803 XCVR_PA_BIAS_TBL1 = (uint32_t)((XCVR_PA_BIAS_TBL1 & (uint32_t)~(uint32_t)(
804 XCVR_PA_BIAS_TBL1_PA_BIAS7_MASK |
805 XCVR_PA_BIAS_TBL1_PA_BIAS6_MASK |
806 XCVR_PA_BIAS_TBL1_PA_BIAS5_MASK |
807 XCVR_PA_BIAS_TBL1_PA_BIAS4_MASK
808 )) | (uint32_t)(
809 (gPABiasTbl[7] << XCVR_PA_BIAS_TBL1_PA_BIAS7_SHIFT) |
810 (gPABiasTbl[6] << XCVR_PA_BIAS_TBL1_PA_BIAS6_SHIFT) |
811 (gPABiasTbl[5] << XCVR_PA_BIAS_TBL1_PA_BIAS5_SHIFT) |
812 (gPABiasTbl[4] << XCVR_PA_BIAS_TBL1_PA_BIAS4_SHIFT)
813 ));
814 }
815
816 /*! *********************************************************************************
817 * \brief This function sets the radio mode specific default vaues of the TSM registers.
818 *
819 * \param[in] radioMode Radio mode is used to enable mode specific settings.
820 *
821 * \ingroup PrivateAPIs
822 *
823 * \details This function also sets link layer registers to account for TX and
824 * delays.
825 *
826 ***********************************************************************************/
XcvrSetTsmDef_ModeSwitch(radio_mode_t radioMode)827 void XcvrSetTsmDef_ModeSwitch ( radio_mode_t radioMode )
828 {
829 /* Setup TSM timing registers and LL timing registers at the same time */
830 switch (radioMode)
831 {
832 case BLE:
833 tsm_ll_timing_init(BLE_RADIO);
834 break;
835 case ZIGBEE:
836 tsm_ll_timing_init(ZIGBEE_RADIO);
837 break;
838 default:
839 break;
840 }
841 }
842
843 /*! *********************************************************************************
844 * \brief This function sets the default vaues of the RX DIG registers.
845 *
846 * \param[in] filt_coeff_ptr pointer to an array of 8 UINT8_T receive filter coefficients.
847 * \param[in] iir3a_idx value of the 3rd IIR index
848 * \param[in] iir2a_idx value of the 2nd IIR index
849 * \param[in] iir1a_idx value of the 1st IIR index
850 *
851 * \ingroup PrivateAPIs
852 *
853 * \details Sets up RX digital registers with command and mode specific settings.
854 *
855 * \note Only uses read-modify-write when only part of the register is being written.
856 *
857 ***********************************************************************************/
XcvrSetRxDigDefaults(const uint8_t * filt_coeff_ptr,uint8_t iir3a_idx,uint8_t iir2a_idx,uint8_t iir1a_idx,uint8_t rssi_hold_src)858 void XcvrSetRxDigDefaults ( const uint8_t * filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src )
859 {
860 /* Program RSSI registers */
861 /* RSSI_CTRL_0 */
862 XCVR_RSSI_CTRL_0 = (uint32_t)((XCVR_RSSI_CTRL_0 & (uint32_t)~(uint32_t)(
863 XCVR_RSSI_CTRL_0_RSSI_USE_VALS_MASK |
864 XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_MASK |
865 XCVR_RSSI_CTRL_0_RSSI_DEC_EN_MASK |
866 XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK |
867 XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK |
868 XCVR_RSSI_CTRL_0_RSSI_ADJ_MASK
869 )) | (uint32_t)(
870 (RSSI_USE_VALS_def_c << XCVR_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT) |
871 (RSSI_HOLD_EN_def_c << XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT) |
872 (RSSI_DEC_EN_def_c << XCVR_RSSI_CTRL_0_RSSI_DEC_EN_SHIFT) |
873 (RSSI_IIR_WEIGHT_def_c << XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT) |
874 (RSSI_IIR_CW_WEIGHT_BYPASSEDdef_c << XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT) |
875 (RSSI_ADJ_def_c << XCVR_RSSI_CTRL_0_RSSI_ADJ_SHIFT)
876 ));
877
878 /* RSSI_CTRL_1 */
879 XCVR_RSSI_CTRL_1 = (uint32_t)((XCVR_RSSI_CTRL_1 & (uint32_t)~(uint32_t)(
880 XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_MASK |
881 XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_MASK |
882 XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_MASK |
883 XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_MASK
884 )) | (uint32_t)(
885 (RSSI_ED_THRESH1_H_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_SHIFT) |
886 (RSSI_ED_THRESH0_H_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_SHIFT) |
887 (RSSI_ED_THRESH1_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_SHIFT) |
888 (RSSI_ED_THRESH0_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_SHIFT)
889 ));
890
891 /* Program AGC registers */
892 /* AGC_CTRL_0 */
893 XCVR_AGC_CTRL_0 = (uint32_t)((XCVR_AGC_CTRL_0 & (uint32_t)~(uint32_t)(
894 XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK |
895 XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK |
896 XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_MASK |
897 XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_MASK |
898 XCVR_AGC_CTRL_0_AGC_UP_SRC_MASK |
899 XCVR_AGC_CTRL_0_AGC_UP_EN_MASK |
900 XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_MASK |
901 XCVR_AGC_CTRL_0_AGC_FREEZE_EN_MASK |
902 XCVR_AGC_CTRL_0_SLOW_AGC_SRC_MASK |
903 XCVR_AGC_CTRL_0_SLOW_AGC_EN_MASK
904 )) | (uint32_t)(
905 (AGC_DOWN_RSSI_THRESH_def_c << XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT) |
906 (AGC_UP_RSSI_THRESH_def_c << XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT) |
907 (AGC_DOWN_BBF_STEP_SZ_def_c << XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_SHIFT) |
908 (AGC_DOWN_TZA_STEP_SZ_def_c << XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_SHIFT) |
909 (AGC_UP_SRC_def_c << XCVR_AGC_CTRL_0_AGC_UP_SRC_SHIFT) |
910 (AGC_UP_EN_def_c << XCVR_AGC_CTRL_0_AGC_UP_EN_SHIFT) |
911 (FREEZE_AGC_SRC_def_c << XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_SHIFT) |
912 (AGC_FREEZE_EN_def_c << XCVR_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT) |
913 (SLOW_AGC_SRC_def_c << XCVR_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT) |
914 (SLOW_AGC_EN_def_c << XCVR_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)
915 ));
916
917 /* AGC_CTRL_1 */
918 XCVR_AGC_CTRL_1 = (uint32_t)((XCVR_AGC_CTRL_1 & (uint32_t)~(uint32_t)(
919 XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_MASK |
920 XCVR_AGC_CTRL_1_PRESLOW_EN_MASK |
921 XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_MASK |
922 XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_MASK |
923 XCVR_AGC_CTRL_1_BBF_USER_GAIN_MASK |
924 XCVR_AGC_CTRL_1_LNM_USER_GAIN_MASK |
925 XCVR_AGC_CTRL_1_LNM_ALT_CODE_MASK |
926 XCVR_AGC_CTRL_1_BBF_ALT_CODE_MASK
927 )) | (uint32_t)(
928 (TZA_GAIN_SETTLE_TIME_def_c << XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_SHIFT) |
929 (PRESLOW_EN_def_c << XCVR_AGC_CTRL_1_PRESLOW_EN_SHIFT) |
930 (USER_BBF_GAIN_EN_def_c << XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_SHIFT) |
931 (USER_LNM_GAIN_EN_def_c << XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_SHIFT) |
932 (BBF_USER_GAIN_def_c << XCVR_AGC_CTRL_1_BBF_USER_GAIN_SHIFT) |
933 (LNM_USER_GAIN_def_c << XCVR_AGC_CTRL_1_LNM_USER_GAIN_SHIFT) |
934 (LNM_ALT_CODE_def_c << XCVR_AGC_CTRL_1_LNM_ALT_CODE_SHIFT) |
935 (BBF_ALT_CODE_def_c << XCVR_AGC_CTRL_1_BBF_ALT_CODE_SHIFT)
936 ));
937
938 /* AGC_CTRL_2 */
939 XCVR_AGC_CTRL_2 = (uint32_t)((XCVR_AGC_CTRL_2 & (uint32_t)~(uint32_t)(
940 XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK |
941 XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_MASK |
942 XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_MASK |
943 XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_MASK |
944 XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_MASK |
945 XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_MASK
946 )) | (uint32_t)(
947 (AGC_FAST_EXPIRE_def_c << XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT) |
948 (TZA_PDET_THRESH_HI_def_c << XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_SHIFT) |
949 (TZA_PDET_THRESH_LO_def_c << XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_SHIFT) |
950 (BBF_PDET_THRESH_HI_def_c << XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_SHIFT) |
951 (BBF_PDET_THRESH_LO_def_c << XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_SHIFT) |
952 (BBF_GAIN_SETTLE_TIME_def_c << XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_SHIFT)
953 ));
954
955 /* AGC_CTRL_3 */
956 XCVR_AGC_CTRL_3 = (uint32_t)((XCVR_AGC_CTRL_3 & (uint32_t)~(uint32_t)(
957 XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK |
958 XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK |
959 XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK |
960 XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK |
961 XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK
962 )) | (uint32_t)(
963 (AGC_UP_STEP_SZ_def_c << XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT) |
964 (AGC_H2S_STEP_SZ_def_c << XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT) |
965 (AGC_RSSI_DELT_H2S_def_c << XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT) |
966 (AGC_PDET_LO_DLY_def_c << XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT) |
967 (AGC_UNFREEZE_TIME_def_c << XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)
968 ));
969
970 /* AGC_GAIN_TBL*** registers */
971 XCVR_AGC_GAIN_TBL_03_00 = (uint32_t)(
972 (BBF_GAIN_00_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_SHIFT) |
973 (LNM_GAIN_00_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_SHIFT) |
974 (BBF_GAIN_01_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_SHIFT) |
975 (LNM_GAIN_01_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_SHIFT) |
976 (BBF_GAIN_02_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_SHIFT) |
977 (LNM_GAIN_02_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_SHIFT) |
978 (BBF_GAIN_03_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_SHIFT) |
979 (LNM_GAIN_03_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_SHIFT)
980 );
981
982 XCVR_AGC_GAIN_TBL_07_04 = (uint32_t)(
983 (BBF_GAIN_04_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_SHIFT) |
984 (LNM_GAIN_04_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_SHIFT) |
985 (BBF_GAIN_05_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_SHIFT) |
986 (LNM_GAIN_05_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_SHIFT) |
987 (BBF_GAIN_06_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_SHIFT) |
988 (LNM_GAIN_06_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_SHIFT) |
989 (BBF_GAIN_07_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_SHIFT) |
990 (LNM_GAIN_07_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_SHIFT)
991 );
992
993 XCVR_AGC_GAIN_TBL_11_08 = (uint32_t)(
994 (BBF_GAIN_08_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_SHIFT) |
995 (LNM_GAIN_08_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_SHIFT) |
996 (BBF_GAIN_09_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_SHIFT) |
997 (LNM_GAIN_09_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_SHIFT) |
998 (BBF_GAIN_10_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_SHIFT) |
999 (LNM_GAIN_10_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_SHIFT) |
1000 (BBF_GAIN_11_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_SHIFT) |
1001 (LNM_GAIN_11_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_SHIFT)
1002 );
1003
1004 XCVR_AGC_GAIN_TBL_15_12 = (uint32_t)(
1005 (BBF_GAIN_12_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_SHIFT) |
1006 (LNM_GAIN_12_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_SHIFT) |
1007 (BBF_GAIN_13_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_SHIFT) |
1008 (LNM_GAIN_13_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_SHIFT) |
1009 (BBF_GAIN_14_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_SHIFT) |
1010 (LNM_GAIN_14_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_SHIFT) |
1011 (BBF_GAIN_15_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_SHIFT) |
1012 (LNM_GAIN_15_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_SHIFT)
1013 );
1014
1015 XCVR_AGC_GAIN_TBL_19_16 = (uint32_t)(
1016 (BBF_GAIN_16_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_SHIFT) |
1017 (LNM_GAIN_16_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_SHIFT) |
1018 (BBF_GAIN_17_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_SHIFT) |
1019 (LNM_GAIN_17_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_SHIFT) |
1020 (BBF_GAIN_18_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_SHIFT) |
1021 (LNM_GAIN_18_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_SHIFT) |
1022 (BBF_GAIN_19_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_SHIFT) |
1023 (LNM_GAIN_19_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_SHIFT)
1024 );
1025
1026 XCVR_AGC_GAIN_TBL_23_20 = (uint32_t)(
1027 (BBF_GAIN_20_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_SHIFT) |
1028 (LNM_GAIN_20_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_SHIFT) |
1029 (BBF_GAIN_21_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_SHIFT) |
1030 (LNM_GAIN_21_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_SHIFT) |
1031 (BBF_GAIN_22_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_SHIFT) |
1032 (LNM_GAIN_22_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_SHIFT) |
1033 (BBF_GAIN_23_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_SHIFT) |
1034 (LNM_GAIN_23_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_SHIFT)
1035 );
1036
1037 XCVR_AGC_GAIN_TBL_26_24 = (uint32_t)(
1038 (BBF_GAIN_24_def_c << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_SHIFT) |
1039 (LNM_GAIN_24_def_c << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_SHIFT) |
1040 (BBF_GAIN_25_def_c << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_SHIFT) |
1041 (LNM_GAIN_25_def_c << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_SHIFT) |
1042 (BBF_GAIN_26_def_c << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_SHIFT) |
1043 (LNM_GAIN_26_def_c << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_SHIFT)
1044 );
1045
1046 XCVR_TCA_AGC_VAL_3_0 = (uint32_t)(
1047 (TCA_AGC_VAL_3_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_SHIFT) |
1048 (TCA_AGC_VAL_2_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_SHIFT) |
1049 (TCA_AGC_VAL_1_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_SHIFT) |
1050 (TCA_AGC_VAL_0_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_SHIFT)
1051 );
1052
1053 XCVR_TCA_AGC_VAL_7_4 = (uint32_t)(
1054 (TCA_AGC_VAL_7_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_SHIFT) |
1055 (TCA_AGC_VAL_6_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_SHIFT) |
1056 (TCA_AGC_VAL_5_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_SHIFT) |
1057 (TCA_AGC_VAL_4_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_SHIFT)
1058 );
1059
1060 XCVR_TCA_AGC_VAL_8 = (uint32_t)(
1061 (TCA_AGC_VAL_8_def_c<< XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_SHIFT)
1062 );
1063
1064 XCVR_BBF_RES_TUNE_VAL_7_0 = (uint32_t)(
1065 (BBF_RES_TUNE_VAL_7_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_SHIFT) |
1066 (BBF_RES_TUNE_VAL_6_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_SHIFT) |
1067 (BBF_RES_TUNE_VAL_5_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_SHIFT) |
1068 (BBF_RES_TUNE_VAL_4_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_SHIFT) |
1069 (BBF_RES_TUNE_VAL_3_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_SHIFT) |
1070 (BBF_RES_TUNE_VAL_2_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_SHIFT) |
1071 (BBF_RES_TUNE_VAL_1_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_SHIFT) |
1072 (BBF_RES_TUNE_VAL_0_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_SHIFT)
1073 );
1074
1075 XCVR_BBF_RES_TUNE_VAL_10_8 = (uint32_t)(
1076 (BBF_RES_TUNE_VAL_10_def_c<< XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_SHIFT) |
1077 (BBF_RES_TUNE_VAL_9_def_c<< XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_SHIFT) |
1078 (BBF_RES_TUNE_VAL_8_def_c<< XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_SHIFT)
1079 );
1080
1081 /* Program DCOC registers */
1082 XcvrCalcSetupDcoc();
1083
1084 /* Use mode switch routine to setup the defaults that depend on radio mode */
1085 XcvrSetRxDigDef_ModeSwitch(filt_coeff_ptr, iir3a_idx, iir2a_idx, iir1a_idx, rssi_hold_src);
1086 }
1087
1088 /*! *********************************************************************************
1089 * \brief This function sets the radio mode dependent default values of the RX DIG registers.
1090 *
1091 * \param[in] in_filt_coeff_ptr pointer to an array of 8 UINT8_T receive filter coefficients.
1092 * \param[in] iir3a_idx value of the 3rd IIR index
1093 * \param[in] iir2a_idx value of the 2nd IIR index
1094 * \param[in] iir1a_idx value of the 1st IIR index
1095 *
1096 * \ingroup PrivateAPIs
1097 *
1098 * \details Sets up RX digital registers with command and mode specific settings.
1099 *
1100 * \note Only uses read-modify-write when only part of the register is being written.
1101 *
1102 **********************************************************************************/
XcvrSetRxDigDef_ModeSwitch(const uint8_t * in_filt_coeff_ptr,uint8_t iir3a_idx,uint8_t iir2a_idx,uint8_t iir1a_idx,uint8_t rssi_hold_src)1103 void XcvrSetRxDigDef_ModeSwitch ( const uint8_t * in_filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src )
1104 {
1105 uint8_t * filt_coeff_ptr = (uint8_t *)in_filt_coeff_ptr;
1106
1107 /*RX_CHF_COEFn*/
1108 XCVR_RX_CHF_COEF0 = *filt_coeff_ptr++;
1109 XCVR_RX_CHF_COEF1 = *filt_coeff_ptr++;
1110 XCVR_RX_CHF_COEF2 = *filt_coeff_ptr++;
1111 XCVR_RX_CHF_COEF3 = *filt_coeff_ptr++;
1112 XCVR_RX_CHF_COEF4 = *filt_coeff_ptr++;
1113 XCVR_RX_CHF_COEF5 = *filt_coeff_ptr++;
1114 XCVR_RX_CHF_COEF6 = *filt_coeff_ptr++;
1115 XCVR_RX_CHF_COEF7 = *filt_coeff_ptr;
1116
1117 /* DCOC_CAL_IIR */
1118 XCVR_DCOC_CAL_IIR = (uint32_t)((XCVR_DCOC_CAL_IIR & (uint32_t)~(uint32_t)(
1119 XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK |
1120 XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK |
1121 XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK
1122 )) | (uint32_t)(
1123 (iir1a_idx << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT) |
1124 (iir2a_idx << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT) |
1125 (iir3a_idx << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)
1126 ));
1127
1128 XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_SRC(XCVR, rssi_hold_src);
1129 }
1130
1131 /*! *********************************************************************************
1132 * \brief This function programs a set of DCOC registers either from raw values
1133 * or from calculated (equations) values.
1134 *
1135 * \return Status of the operation.
1136 *
1137 * \ingroup PrivateAPIs
1138 *
1139 * \details
1140 *
1141 ***********************************************************************************/
XcvrCalcSetupDcoc(void)1142 xcvrStatus_t XcvrCalcSetupDcoc ( void )
1143 {
1144 #if !USE_DCOC_MAGIC_NUMBERS
1145
1146 /* Define variables to replace all of the #defined constants which are used
1147 * below and which are defined in BLEDefaults.h for the case where
1148 * USE_DCOC_MAGIC_NUMBERS == 1
1149 */
1150
1151 /* DCOC_CAL_RCP */
1152 #define ALPHA_CALC_RECIP_def_c 0x00
1153 #define TMP_CALC_RECIP_def_c 0x00
1154
1155 /* TCA_AGC_LIN_VAL_2_0 */
1156 uint16_t TCA_AGC_LIN_VAL_0_def_c;
1157 uint16_t TCA_AGC_LIN_VAL_1_def_c;
1158 uint16_t TCA_AGC_LIN_VAL_2_def_c;
1159
1160 /* TCA_AGC_LIN_VAL_5_3 */
1161 uint16_t TCA_AGC_LIN_VAL_3_def_c;
1162 uint16_t TCA_AGC_LIN_VAL_4_def_c;
1163 uint16_t TCA_AGC_LIN_VAL_5_def_c;
1164
1165 /* TCA_AGC_LIN_VAL_8_6 */
1166 uint16_t TCA_AGC_LIN_VAL_6_def_c;
1167 uint16_t TCA_AGC_LIN_VAL_7_def_c;
1168 uint16_t TCA_AGC_LIN_VAL_8_def_c;
1169
1170 /* BBF_RES_TUNE_LIN_VAL_3_0 */
1171 uint8_t BBF_RES_TUNE_LIN_VAL_0_def_c;
1172 uint8_t BBF_RES_TUNE_LIN_VAL_1_def_c;
1173 uint8_t BBF_RES_TUNE_LIN_VAL_2_def_c;
1174 uint8_t BBF_RES_TUNE_LIN_VAL_3_def_c;
1175
1176 /* BBF_RES_TUNE_LIN_VAL_7_4 */
1177 uint8_t BBF_RES_TUNE_LIN_VAL_4_def_c;
1178 uint8_t BBF_RES_TUNE_LIN_VAL_5_def_c;
1179 uint8_t BBF_RES_TUNE_LIN_VAL_6_def_c;
1180 uint8_t BBF_RES_TUNE_LIN_VAL_7_def_c;
1181
1182 /* BBF_RES_TUNE_LIN_VAL_10_8 */
1183 uint8_t BBF_RES_TUNE_LIN_VAL_8_def_c;
1184 uint8_t BBF_RES_TUNE_LIN_VAL_9_def_c;
1185 uint8_t BBF_RES_TUNE_LIN_VAL_10_def_c;
1186
1187 /* DCOC_TZA_STEP */
1188 uint16_t DCOC_TZA_STEP_GAIN_00_def_c;
1189 uint16_t DCOC_TZA_STEP_RCP_00_def_c;
1190 uint16_t DCOC_TZA_STEP_GAIN_01_def_c;
1191 uint16_t DCOC_TZA_STEP_RCP_01_def_c;
1192 uint16_t DCOC_TZA_STEP_GAIN_02_def_c;
1193 uint16_t DCOC_TZA_STEP_RCP_02_def_c;
1194 uint16_t DCOC_TZA_STEP_GAIN_03_def_c;
1195 uint16_t DCOC_TZA_STEP_RCP_03_def_c;
1196 uint16_t DCOC_TZA_STEP_GAIN_04_def_c;
1197 uint16_t DCOC_TZA_STEP_RCP_04_def_c;
1198 uint16_t DCOC_TZA_STEP_GAIN_05_def_c;
1199 uint16_t DCOC_TZA_STEP_RCP_05_def_c;
1200 uint16_t DCOC_TZA_STEP_GAIN_06_def_c;
1201 uint16_t DCOC_TZA_STEP_RCP_06_def_c;
1202 uint16_t DCOC_TZA_STEP_GAIN_07_def_c;
1203 uint16_t DCOC_TZA_STEP_RCP_07_def_c;
1204 uint16_t DCOC_TZA_STEP_GAIN_08_def_c;
1205 uint16_t DCOC_TZA_STEP_RCP_08_def_c;
1206 uint16_t DCOC_TZA_STEP_GAIN_09_def_c;
1207 uint16_t DCOC_TZA_STEP_RCP_09_def_c;
1208 uint16_t DCOC_TZA_STEP_GAIN_10_def_c;
1209 uint16_t DCOC_TZA_STEP_RCP_10_def_c;
1210
1211 /* DCOC_CTRL_1 DCOC_CTRL_2 */
1212 uint16_t BBF_STEP_def_c;
1213 uint16_t BBF_STEP_RECIP_def_c;
1214
1215 /* DCOC_CAL_RCP */
1216 uint16_t RCP_GLHmGLLxGBL_def_c;
1217 uint16_t RCP_GBHmGBL_def_c;
1218
1219 /* Equations to calculate these values */
1220 TCA_AGC_LIN_VAL_0_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_0_def_c));
1221 TCA_AGC_LIN_VAL_1_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_1_def_c));
1222 TCA_AGC_LIN_VAL_2_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_2_def_c));
1223
1224 TCA_AGC_LIN_VAL_3_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_3_def_c));
1225 TCA_AGC_LIN_VAL_4_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_4_def_c));
1226 TCA_AGC_LIN_VAL_5_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_5_def_c));
1227
1228 TCA_AGC_LIN_VAL_6_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_6_def_c));
1229 TCA_AGC_LIN_VAL_7_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_7_def_c));
1230 TCA_AGC_LIN_VAL_8_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_8_def_c));
1231
1232 BBF_RES_TUNE_LIN_VAL_0_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_0_def_c));
1233 BBF_RES_TUNE_LIN_VAL_1_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_1_def_c));
1234 BBF_RES_TUNE_LIN_VAL_2_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_2_def_c));
1235 BBF_RES_TUNE_LIN_VAL_3_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_3_def_c));
1236
1237 BBF_RES_TUNE_LIN_VAL_4_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_4_def_c));
1238 BBF_RES_TUNE_LIN_VAL_5_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_5_def_c));
1239 BBF_RES_TUNE_LIN_VAL_6_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_6_def_c));
1240 BBF_RES_TUNE_LIN_VAL_7_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_7_def_c));
1241
1242 BBF_RES_TUNE_LIN_VAL_8_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_8_def_c));
1243 BBF_RES_TUNE_LIN_VAL_9_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_9_def_c));
1244
1245 if ((0x8*DB_TO_LINEAR(BBF_GAIN_DB_10_def_c)) > 255)
1246 {
1247 BBF_RES_TUNE_LIN_VAL_10_def_c = (uint8_t)(0xFF);
1248 }
1249 else
1250 {
1251 BBF_RES_TUNE_LIN_VAL_10_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_10_def_c));
1252 }
1253
1254 if (gen1_dcgain_trims_enabled)
1255 {
1256 double temp_prd = TZA_DCOC_STEP_RAW * adc_gain_trimmed;
1257 DCOC_TZA_STEP_GAIN_00_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_0_def_c) * 0x8);
1258 DCOC_TZA_STEP_RCP_00_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_0_def_c)));
1259 DCOC_TZA_STEP_GAIN_01_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_1_def_c) * 0x8);
1260 DCOC_TZA_STEP_RCP_01_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_1_def_c)));
1261 DCOC_TZA_STEP_GAIN_02_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_2_def_c) * 0x8);
1262 DCOC_TZA_STEP_RCP_02_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_2_def_c)));
1263 DCOC_TZA_STEP_GAIN_03_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_3_def_c) * 0x8);
1264 DCOC_TZA_STEP_RCP_03_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_3_def_c)));
1265 DCOC_TZA_STEP_GAIN_04_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_4_def_c) * 0x8);
1266 DCOC_TZA_STEP_RCP_04_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_4_def_c)));
1267 DCOC_TZA_STEP_GAIN_05_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_5_def_c) * 0x8);
1268 DCOC_TZA_STEP_RCP_05_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_5_def_c)));
1269 DCOC_TZA_STEP_GAIN_06_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_6_def_c) * 0x8);
1270 DCOC_TZA_STEP_RCP_06_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_6_def_c)));
1271 DCOC_TZA_STEP_GAIN_07_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_7_def_c) * 0x8);
1272 DCOC_TZA_STEP_RCP_07_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_7_def_c)));
1273 DCOC_TZA_STEP_GAIN_08_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_8_def_c) * 0x8);
1274 DCOC_TZA_STEP_RCP_08_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_8_def_c)));
1275 DCOC_TZA_STEP_GAIN_09_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_9_def_c) * 0x8);
1276 DCOC_TZA_STEP_RCP_09_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_9_def_c)));
1277 DCOC_TZA_STEP_GAIN_10_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_10_def_c) * 0x8);
1278 DCOC_TZA_STEP_RCP_10_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_10_def_c)));
1279
1280 BBF_STEP_def_c = (uint16_t)round(BBF_DCOC_STEP_RAW * adc_gain_trimmed *0x8);
1281 BBF_STEP_RECIP_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(BBF_DCOC_STEP_RAW * adc_gain_trimmed));
1282 }
1283
1284 RCP_GLHmGLLxGBL_def_c = (uint16_t)(round(((double)(2048*1.0))/((DB_TO_LINEAR(TCA_GAIN_DB_8_def_c)-DB_TO_LINEAR(TCA_GAIN_DB_4_def_c))*DB_TO_LINEAR(BBF_GAIN_DB_4_def_c))));
1285 RCP_GBHmGBL_def_c = (uint16_t)(round(((double)(1024*1.0))/((DB_TO_LINEAR(BBF_GAIN_DB_8_def_c)-DB_TO_LINEAR(BBF_GAIN_DB_4_def_c)))));
1286
1287 #endif /* !USE_DCOC_MAGIC_NUMBERS */
1288
1289 /* Write the registers with either the raw or calculated values.
1290 * NOTE: Values will be either #define constants or local variables.
1291 */
1292
1293 /* Miscellaneous DCOC Tracking & GearShift Control Settings (Misc Registers) */
1294 XCVR_ADC_TEST_CTRL = (uint32_t)((XCVR_ADC_TEST_CTRL & (uint32_t)~(uint32_t)(
1295 XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_MASK
1296 )) | (uint32_t)(
1297 (DCOC_ALPHA_RADIUS_GS_IDX_def_c << XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)
1298 ));
1299
1300 XCVR_RX_ANA_CTRL = (uint32_t)((XCVR_RX_ANA_CTRL & (uint32_t)~(uint32_t)(
1301 XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_MASK
1302 )) | (uint32_t)(
1303 (IQMC_DC_GAIN_ADJ_EN_def_c << XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_SHIFT)
1304 ));
1305
1306 XCVR_ANA_SPARE = (uint32_t)((XCVR_ANA_SPARE & (uint32_t)~(uint32_t)(
1307 XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_MASK |
1308 XCVR_ANA_SPARE_HPM_LSB_INVERT_MASK
1309 )) | (uint32_t)(
1310 (DCOC_TRK_EST_GS_CNT_def_c << XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_SHIFT) |
1311 (HPM_LSB_INVERT_def_c << XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT)
1312 ));
1313
1314 /* DCOC_CAL_GAIN */
1315 XCVR_DCOC_CAL_GAIN = (uint32_t)((XCVR_DCOC_CAL_GAIN & (uint32_t)~(uint32_t)(
1316 XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_MASK |
1317 XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_MASK |
1318 XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_MASK |
1319 XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_MASK |
1320 XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_MASK |
1321 XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_MASK
1322 )) | (uint32_t)(
1323 (DCOC_BBF_CAL_GAIN1_def_c << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT) |
1324 (DCOC_TZA_CAL_GAIN1_def_c << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT) |
1325 (DCOC_BBF_CAL_GAIN2_def_c << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT) |
1326 (DCOC_TZA_CAL_GAIN2_def_c << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT) |
1327 (DCOC_BBF_CAL_GAIN3_def_c << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT) |
1328 (DCOC_TZA_CAL_GAIN3_def_c << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT)
1329 ));
1330
1331 /* DCOC_CALC_RCP */
1332 XCVR_DCOC_CAL_RCP = (uint32_t)((XCVR_DCOC_CAL_RCP & (uint32_t)~(uint32_t)(
1333 XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK |
1334 XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK
1335 )) | (uint32_t)(
1336 (TMP_CALC_RECIP_def_c << XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT) |
1337 (ALPHA_CALC_RECIP_def_c << XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)
1338 ));
1339
1340 /* TCA_AGC_LIN_VAL_2_0 */
1341 XCVR_TCA_AGC_LIN_VAL_2_0 = (uint32_t)((XCVR_TCA_AGC_LIN_VAL_2_0 & (uint32_t)~(uint32_t)(
1342 XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_MASK |
1343 XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_MASK |
1344 XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_MASK
1345 )) | (uint32_t)(
1346 (TCA_AGC_LIN_VAL_0_def_c << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_SHIFT) |
1347 (TCA_AGC_LIN_VAL_1_def_c << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_SHIFT) |
1348 (TCA_AGC_LIN_VAL_2_def_c << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_SHIFT)
1349 ));
1350
1351 /* TCA_AGC_LIN_VAL_5_3 */
1352 XCVR_TCA_AGC_LIN_VAL_5_3 = (uint32_t)((XCVR_TCA_AGC_LIN_VAL_5_3 & (uint32_t)~(uint32_t)(
1353 XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_MASK |
1354 XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_MASK |
1355 XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_MASK
1356 )) | (uint32_t)(
1357 (TCA_AGC_LIN_VAL_3_def_c << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_SHIFT) |
1358 (TCA_AGC_LIN_VAL_4_def_c << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_SHIFT) |
1359 (TCA_AGC_LIN_VAL_5_def_c << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_SHIFT)
1360 ));
1361
1362 /* TCA_AGC_LIN_VAL_8_6 */
1363 XCVR_TCA_AGC_LIN_VAL_8_6 = (uint32_t)((XCVR_TCA_AGC_LIN_VAL_8_6 & (uint32_t)~(uint32_t)(
1364 XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_MASK |
1365 XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_MASK |
1366 XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_MASK
1367 )) | (uint32_t)(
1368 (TCA_AGC_LIN_VAL_6_def_c << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_SHIFT) |
1369 (TCA_AGC_LIN_VAL_7_def_c << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_SHIFT) |
1370 (TCA_AGC_LIN_VAL_8_def_c << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_SHIFT)
1371 ));
1372
1373 /* BBF_RES_TUNE_LIN_VAL_3_0 */
1374 XCVR_BBF_RES_TUNE_LIN_VAL_3_0 = (uint32_t)((XCVR_BBF_RES_TUNE_LIN_VAL_3_0 & (uint32_t)~(uint32_t)(
1375 XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_MASK |
1376 XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_MASK |
1377 XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_MASK |
1378 XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_MASK
1379 )) | (uint32_t)(
1380 (BBF_RES_TUNE_LIN_VAL_0_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_SHIFT) |
1381 (BBF_RES_TUNE_LIN_VAL_1_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_SHIFT) |
1382 (BBF_RES_TUNE_LIN_VAL_2_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_SHIFT) |
1383 (BBF_RES_TUNE_LIN_VAL_3_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_SHIFT)
1384 ));
1385
1386 /* BBF_RES_TUNE_LIN_VAL_7_4 */
1387 XCVR_BBF_RES_TUNE_LIN_VAL_7_4 = (uint32_t)((XCVR_BBF_RES_TUNE_LIN_VAL_7_4 & (uint32_t)~(uint32_t)(
1388 XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_MASK |
1389 XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_MASK |
1390 XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_MASK |
1391 XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_MASK
1392 )) | (uint32_t)(
1393 (BBF_RES_TUNE_LIN_VAL_4_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_SHIFT) |
1394 (BBF_RES_TUNE_LIN_VAL_5_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_SHIFT) |
1395 (BBF_RES_TUNE_LIN_VAL_6_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_SHIFT) |
1396 (BBF_RES_TUNE_LIN_VAL_7_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_SHIFT)
1397 ));
1398
1399 /* BBF_RES_TUNE_LIN_VAL_10_8 */
1400 XCVR_BBF_RES_TUNE_LIN_VAL_10_8 = (uint32_t)((XCVR_BBF_RES_TUNE_LIN_VAL_10_8 & (uint32_t)~(uint32_t)(
1401 XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_MASK |
1402 XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_MASK |
1403 XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_MASK
1404 )) | (uint32_t)(
1405 (BBF_RES_TUNE_LIN_VAL_8_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_SHIFT) |
1406 (BBF_RES_TUNE_LIN_VAL_9_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_SHIFT) |
1407 (BBF_RES_TUNE_LIN_VAL_10_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_SHIFT)
1408 ));
1409
1410 if (gen1_dcgain_trims_enabled) /* Only run this code when Gen 1 DC GAIN trims are being used. */
1411 {
1412 /* DCOC_TZA_STEP_GAIN & RCP 00-10 */
1413 XCVR_DCOC_TZA_STEP_00 = (uint32_t)((XCVR_DCOC_TZA_STEP_00 & (uint32_t)~(uint32_t)(
1414 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1415 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1416 )) | (uint32_t)(
1417 (DCOC_TZA_STEP_RCP_00_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1418 (DCOC_TZA_STEP_GAIN_00_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1419 ));
1420
1421 XCVR_DCOC_TZA_STEP_01 = (uint32_t)((XCVR_DCOC_TZA_STEP_01 & (uint32_t)~(uint32_t)(
1422 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1423 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1424 )) | (uint32_t)(
1425 (DCOC_TZA_STEP_RCP_01_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1426 (DCOC_TZA_STEP_GAIN_01_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1427 ));
1428
1429 XCVR_DCOC_TZA_STEP_02 = (uint32_t)((XCVR_DCOC_TZA_STEP_02 & (uint32_t)~(uint32_t)(
1430 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1431 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1432 )) | (uint32_t)(
1433 (DCOC_TZA_STEP_RCP_02_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1434 (DCOC_TZA_STEP_GAIN_02_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1435 ));
1436
1437 XCVR_DCOC_TZA_STEP_03 = (uint32_t)((XCVR_DCOC_TZA_STEP_03 & (uint32_t)~(uint32_t)(
1438 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1439 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1440 )) | (uint32_t)(
1441 (DCOC_TZA_STEP_RCP_03_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1442 (DCOC_TZA_STEP_GAIN_03_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1443 ));
1444
1445 XCVR_DCOC_TZA_STEP_04 = (uint32_t)((XCVR_DCOC_TZA_STEP_04 & (uint32_t)~(uint32_t)(
1446 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1447 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1448 )) | (uint32_t)(
1449 (DCOC_TZA_STEP_RCP_04_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1450 (DCOC_TZA_STEP_GAIN_04_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1451 ));
1452
1453 XCVR_DCOC_TZA_STEP_05 = (uint32_t)((XCVR_DCOC_TZA_STEP_05 & (uint32_t)~(uint32_t)(
1454 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1455 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1456 )) | (uint32_t)(
1457 (DCOC_TZA_STEP_RCP_05_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1458 (DCOC_TZA_STEP_GAIN_05_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1459 ));
1460
1461 XCVR_DCOC_TZA_STEP_06 = (uint32_t)((XCVR_DCOC_TZA_STEP_06 & (uint32_t)~(uint32_t)(
1462 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1463 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1464 )) | (uint32_t)(
1465 (DCOC_TZA_STEP_RCP_06_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1466 (DCOC_TZA_STEP_GAIN_06_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1467 ));
1468
1469 XCVR_DCOC_TZA_STEP_07 = (uint32_t)((XCVR_DCOC_TZA_STEP_07 & (uint32_t)~(uint32_t)(
1470 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1471 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1472 )) | (uint32_t)(
1473 (DCOC_TZA_STEP_RCP_07_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1474 (DCOC_TZA_STEP_GAIN_07_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1475 ));
1476
1477 XCVR_DCOC_TZA_STEP_08 = (uint32_t)((XCVR_DCOC_TZA_STEP_08 & (uint32_t)~(uint32_t)(
1478 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1479 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1480 )) | (uint32_t)(
1481 (DCOC_TZA_STEP_RCP_08_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1482 (DCOC_TZA_STEP_GAIN_08_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1483 ));
1484
1485 XCVR_DCOC_TZA_STEP_09 = (uint32_t)((XCVR_DCOC_TZA_STEP_09 & (uint32_t)~(uint32_t)(
1486 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1487 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1488 )) | (uint32_t)(
1489 (DCOC_TZA_STEP_RCP_09_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1490 (DCOC_TZA_STEP_GAIN_09_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1491 ));
1492
1493 XCVR_DCOC_TZA_STEP_10 = (uint32_t)((XCVR_DCOC_TZA_STEP_10 & (uint32_t)~(uint32_t)(
1494 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK |
1495 XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK
1496 )) | (uint32_t)(
1497 (DCOC_TZA_STEP_RCP_10_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) |
1498 (DCOC_TZA_STEP_GAIN_10_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
1499 ));
1500 }
1501
1502 /* DCOC_CTRL_1 */
1503 XCVR_DCOC_CTRL_1 = (uint32_t)((XCVR_DCOC_CTRL_1 & (uint32_t)~(uint32_t)(
1504 XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_MASK |
1505 XCVR_DCOC_CTRL_1_BBA_CORR_POL_MASK |
1506 XCVR_DCOC_CTRL_1_TZA_CORR_POL_MASK
1507 )) | (uint32_t)(
1508 (TRACK_FROM_ZERO_def_c << XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT) |
1509 (BBF_CORR_POL_def_c << XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT) |
1510 (TZA_CORR_POL_def_c << XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT)
1511 ));
1512
1513 if (gen1_dcgain_trims_enabled)
1514 {
1515 XCVR_BWR_DCOC_CTRL_1_BBF_DCOC_STEP(XCVR, BBF_STEP_def_c); /* Only write this field if Gen1 DC GAIN trims being used. */
1516 }
1517
1518 /* DCOC_CTRL_2 */
1519 if (gen1_dcgain_trims_enabled)
1520 {
1521 XCVR_BWR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(XCVR, BBF_STEP_RECIP_def_c);
1522 }
1523
1524 /* DCOC_CAL_RCP */
1525 XCVR_DCOC_CAL_RCP = (uint32_t)((XCVR_DCOC_CAL_RCP & (uint32_t)~(uint32_t)(
1526 XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK |
1527 XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK
1528 )) | (uint32_t)(
1529 (RCP_GBHmGBL_def_c << XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT) |
1530 (RCP_GLHmGLLxGBL_def_c << XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)
1531 ));
1532
1533 return gXcvrSuccess_c;
1534 }
1535
1536 /*! *********************************************************************************
1537 * \brief This function sets up the TX_DIG and PLL settings
1538 *
1539 * \param[in] radioMode - the operating mode for the radio to be configured
1540 *
1541 * \return status of the operation.
1542 *
1543 * \ingroup PrivateAPIs
1544 *
1545 * \details
1546 *
1547 ***********************************************************************************/
XcvrSetTxDigPLLDefaults(radio_mode_t radioMode)1548 void XcvrSetTxDigPLLDefaults( radio_mode_t radioMode )
1549 {
1550 /* Configure the High Port Sigma Delta */
1551 XCVR_BWR_ANA_SPARE_HPM_LSB_INVERT(XCVR, HPM_LSB_INVERT_def_c);
1552 XCVR_BWR_PLL_HPM_SDM_FRACTION_HPM_DENOM(XCVR, HPM_DENOM_def_c);
1553
1554 /* Configure the PLL Modulation Delays */
1555 XCVR_BWR_PLL_DELAY_MATCH_HPM_BANK_DELAY(XCVR, HPM_BANK_DELAY_def_c);
1556 XCVR_BWR_PLL_DELAY_MATCH_HPM_SDM_DELAY(XCVR, HPM_SDM_DELAY_def_c);
1557 XCVR_BWR_PLL_DELAY_MATCH_LP_SDM_DELAY(XCVR, LP_SDM_DELAY_def_c);
1558
1559 /* Configure PLL Loop Filter Configuration from Default value */
1560 XCVR_BWR_PLL_CTRL_PLL_LFILT_CNTL(XCVR, PLL_LFILT_CNTL_def_c);
1561
1562 /* Change FSK_MODULATION_SCALE_1 from it Default value */
1563 XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(XCVR, FSK_MODULATION_SCALE_1_def_c);
1564
1565 /* PLL Dithering */
1566 XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_OVRD(XCVR, 1); /* Enable over-riding dither control */
1567 XCVR_BWR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(XCVR, 0x8); /* Set dither range */
1568 XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_CTRL(XCVR, 1); /* Turn on dither all the time */
1569
1570 /* Use mode switch routine to setup the defaults that depend on radio mode (none at this time) */
1571 XcvrSetTxDigPLLDef_ModeSwitch(radioMode);
1572 }
1573
1574 /*! *********************************************************************************
1575 * \brief This function sets up the TX_DIG and PLL radio mode specific settings
1576 *
1577 * \param[in] radioMode - the operating mode for the radio to be configured
1578 *
1579 * \ingroup PrivateAPIs
1580 *
1581 * \details
1582 *
1583 ***********************************************************************************/
XcvrSetTxDigPLLDef_ModeSwitch(radio_mode_t radioMode)1584 void XcvrSetTxDigPLLDef_ModeSwitch( radio_mode_t radioMode )
1585 {
1586
1587 }
1588
1589 /*! *********************************************************************************
1590 * \brief This function sets up the analog settings
1591 *
1592 * \param[in] radioMode - the operating mode for the radio to be configured
1593 *
1594 * \ingroup PrivateAPIs
1595 *
1596 * \details
1597 *
1598 ***********************************************************************************/
XcvrSetAnalogDefaults(radio_mode_t radioMode)1599 void XcvrSetAnalogDefaults ( radio_mode_t radioMode )
1600 {
1601 /* Use mode switch routine to setup the defaults that depend on radio mode */
1602 XcvrSetAnalogDef_ModeSwitch(radioMode);
1603
1604 /* Regulator trim and ADC trims */
1605 XCVR_BWR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(XCVR, 1);
1606 XCVR_BWR_ADC_TUNE_ADC_R1_TUNE(XCVR, 5);
1607 XCVR_BWR_ADC_TUNE_ADC_R2_TUNE(XCVR, 5);
1608 XCVR_BWR_ADC_TUNE_ADC_C1_TUNE(XCVR, 8);
1609 XCVR_BWR_ADC_TUNE_ADC_C2_TUNE(XCVR, 8);
1610
1611 XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(XCVR, 5);
1612 XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(XCVR, 7);
1613 XCVR_BWR_ADC_ADJ_ADC_IB_DAC1_ADJ(XCVR, 2);
1614 XCVR_BWR_ADC_ADJ_ADC_IB_DAC2_ADJ(XCVR, 2);
1615 XCVR_BWR_ADC_ADJ_ADC_IB_FLSH_ADJ(XCVR, 6);
1616 XCVR_BWR_ADC_ADJ_ADC_FLSH_RES_ADJ(XCVR, 0);
1617
1618 XCVR_BWR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(XCVR, 2);
1619 XCVR_BWR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(XCVR, 4);
1620 XCVR_BWR_ADC_TRIMS_ADC_VCM_TRIM(XCVR, 4);
1621
1622 /* Raise QGEN and ADC_ANA and ADC_DIG supplies */
1623 XCVR_BWR_ADC_REGS_ADC_ANA_REG_SUPPLY(XCVR, 9);
1624 XCVR_BWR_ADC_REGS_ADC_REG_DIG_SUPPLY(XCVR, 9);
1625 XCVR_BWR_QGEN_CTRL_QGEN_REG_SUPPLY(XCVR, 9);
1626 }
1627
1628 /*! *********************************************************************************
1629 * \brief This function sets up the radio mode specific analog settings
1630 *
1631 * \param[in] radioMode - the operating mode for the radio to be configured
1632 *
1633 * \ingroup PrivateAPIs
1634 *
1635 * \details
1636 *
1637 ***********************************************************************************/
XcvrSetAnalogDef_ModeSwitch(radio_mode_t radioMode)1638 void XcvrSetAnalogDef_ModeSwitch ( radio_mode_t radioMode )
1639 {
1640 switch (radioMode)
1641 {
1642 case BLE:
1643 /* TZA_CTRL for BLE */
1644 XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(XCVR, ble_tza_cap_tune);
1645
1646 /* BBF_CTRL for BLE */
1647 XCVR_BBF_CTRL = (uint32_t)((XCVR_BBF_CTRL & (uint32_t)~(uint32_t)(
1648 XCVR_BBF_CTRL_BBF_CAP_TUNE_MASK |
1649 XCVR_BBF_CTRL_BBF_RES_TUNE2_MASK |
1650 XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_MASK
1651 )) | (uint32_t)(
1652 (ble_bbf_cap_tune << XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT) |
1653 (ble_bbf_res_tune2 << XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT) |
1654 (DCOC_ALPHAC_SCALE_GS_IDX_def_c << XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)
1655 ));
1656 break;
1657 case ZIGBEE:
1658 /* TZA_CTRL for Zigbee */
1659 XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(XCVR, zb_tza_cap_tune);
1660
1661 /* BBF_CTRL for Zigbee */
1662 XCVR_BBF_CTRL = (uint32_t)((XCVR_BBF_CTRL & (uint32_t)~(uint32_t)(
1663 XCVR_BBF_CTRL_BBF_CAP_TUNE_MASK |
1664 XCVR_BBF_CTRL_BBF_RES_TUNE2_MASK |
1665 XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_MASK
1666 )) | (uint32_t)(
1667 (zb_bbf_cap_tune << XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT) |
1668 (zb_bbf_res_tune2 << XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT) |
1669 (DCOC_ALPHAC_SCALE_GS_IDX_def_c << XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)
1670 ));
1671 break;
1672 default:
1673 break;
1674 }
1675 }
1676
1677 /*! *********************************************************************************
1678 * \brief This function controls the enable/disable of RSSI IIR narrowband filter
1679 * used in Zigbee CCA tests for narrowband RSSI measurement.
1680 *
1681 * \param[in] IIRnbEnable - enable or disable the narrowband IIR filter
1682 *
1683 * \ingroup PublicAPIs
1684 *
1685 * \details
1686 *
1687 ***********************************************************************************/
XcvrEnaNBRSSIMeas(bool_t IIRnbEnable)1688 void XcvrEnaNBRSSIMeas( bool_t IIRnbEnable )
1689 {
1690 if (IIRnbEnable)
1691 {
1692 /* enable narrowband IIR filter for RSSI */
1693 XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(XCVR, RSSI_IIR_CW_WEIGHT_ENABLEDdef_c);
1694 }
1695 else
1696 {
1697 /* Disable narrowband IIR filter for RSSI */
1698 XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(XCVR, RSSI_IIR_CW_WEIGHT_BYPASSEDdef_c);
1699 }
1700 }
1701
1702 /* Customer level trim functions */
1703 /*! *********************************************************************************
1704 * \brief This function sets the XTAL trim field to control crystal osc frequency.
1705 *
1706 * \param[in] xtalTrim - value to control the trim of the crystal osc.
1707 *
1708 * \return status of the operation.
1709 *
1710 * \ingroup PublicAPIs
1711 *
1712 * \details
1713 *
1714 ***********************************************************************************/
XcvrSetXtalTrim(int8_t xtalTrim)1715 xcvrStatus_t XcvrSetXtalTrim(int8_t xtalTrim)
1716 {
1717 XCVR_BWR_XTAL_CTRL_XTAL_TRIM(XCVR, xtalTrim);
1718 return gXcvrSuccess_c;
1719 }
1720
1721 /*! *********************************************************************************
1722 * \brief This function reads the XTAL trim field
1723 *
1724 * \return the current value of the crystal osc trim.
1725 *
1726 * \ingroup PublicAPIs
1727 *
1728 * \details
1729 *
1730 ***********************************************************************************/
XcvrGetXtalTrim(void)1731 int8_t XcvrGetXtalTrim(void)
1732 {
1733 return (int8_t)XCVR_BRD_XTAL_CTRL_XTAL_TRIM(XCVR);
1734 }
1735
1736 /*! *********************************************************************************
1737 * \brief This function sets the AGC gain setting table entry and the DCOC table
1738 * entry to be used.
1739 *
1740 * \param[in] entry: Entry number from AGC table to use.
1741 *
1742 * \return status of the operation.
1743 *
1744 * \ingroup PrivateAPIs
1745 *
1746 * \details
1747 *
1748 ***********************************************************************************/
XcvrSetGain(uint8_t entry)1749 xcvrStatus_t XcvrSetGain ( uint8_t entry )
1750 {
1751 #if INCLUDE_OLD_DRV_CODE
1752 if (entry > 26)
1753 {
1754 return gXcvrInvalidParameters_c;
1755 }
1756
1757 XCVR_AGC_CTRL_1_WR((uint32_t)((XCVR_AGC_CTRL_1_RD & (uint32_t)~(uint32_t)(
1758 XCVR_AGC_CTRL_1_AGC_IDLE_GAIN_MASK
1759 )) | (uint32_t)(
1760 (entry << XCVR_AGC_CTRL_1_AGC_IDLE_GAIN_SHIFT)
1761 )));
1762 #endif
1763 return gXcvrSuccess_c;
1764 }
1765
1766 /*! *********************************************************************************
1767 * \brief This function sets the channel for test mode and overrides the BLE and Zigbee channel.
1768 *
1769 * \param[in] channel: Channel number.
1770 * \param[in] useMappedChannel: Selects to use the channel map table (TRUE) or to use the manual frequency setting based on a SW table of numerator and denominator values for the PLL.
1771 *
1772 * \return status of the operation.
1773 *
1774 * \ingroup PrivateAPIs
1775 *
1776 * \details This function overrides both the BLE and Zigbee channel values from the respective LLs.
1777 *
1778 ***********************************************************************************/
XcvrOverrideChannel(uint8_t channel,uint8_t useMappedChannel)1779 xcvrStatus_t XcvrOverrideChannel ( uint8_t channel, uint8_t useMappedChannel )
1780 {
1781 if(channel == 0xFF)
1782 {
1783 /* Clear all of the overrides and restore to LL channel control */
1784
1785 XCVR_PLL_CHAN_MAP = (uint32_t)((XCVR_PLL_CHAN_MAP & (uint32_t)~(uint32_t)(
1786 XCVR_PLL_CHAN_MAP_CHANNEL_NUM_MASK |
1787 XCVR_PLL_CHAN_MAP_ZOC_MASK |
1788 XCVR_PLL_CHAN_MAP_BOC_MASK
1789 )));
1790
1791 /* Stop using the manual frequency setting */
1792 XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(XCVR, 0);
1793
1794 return gXcvrSuccess_c;
1795 }
1796
1797 if(channel >= 128)
1798 {
1799 return gXcvrInvalidParameters_c;
1800 }
1801
1802 if(useMappedChannel == TRUE)
1803 {
1804 XCVR_PLL_CHAN_MAP = (uint32_t)((XCVR_PLL_CHAN_MAP & (uint32_t)~(uint32_t)(
1805 XCVR_PLL_CHAN_MAP_CHANNEL_NUM_MASK |
1806 XCVR_PLL_CHAN_MAP_BOC_MASK |
1807 XCVR_PLL_CHAN_MAP_ZOC_MASK
1808 )) | (uint32_t)(
1809 (channel << XCVR_PLL_CHAN_MAP_CHANNEL_NUM_SHIFT) |
1810 (0x01 << XCVR_PLL_CHAN_MAP_BOC_SHIFT) |
1811 (0x01 << XCVR_PLL_CHAN_MAP_ZOC_SHIFT)
1812 ));
1813 }
1814 else
1815 {
1816 XCVR_PLL_CHAN_MAP = (uint32_t)((XCVR_PLL_CHAN_MAP & (uint32_t)~(uint32_t)(
1817 XCVR_PLL_CHAN_MAP_BOC_MASK |
1818 XCVR_PLL_CHAN_MAP_ZOC_MASK
1819 )) | (uint32_t)(
1820 (0x01 << XCVR_PLL_CHAN_MAP_BOC_SHIFT) |
1821 (0x01 << XCVR_PLL_CHAN_MAP_ZOC_SHIFT)
1822 ));
1823
1824 XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR, gPllDenom_c);
1825 XCVR_BWR_PLL_LP_SDM_CTRL2_LPM_NUM(XCVR, mapTable[channel].numerator);
1826 XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(XCVR, mapTable[channel].integer);
1827
1828 /* Stop using the LL channel map and use the manual frequency setting */
1829 XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(XCVR, 1);
1830 }
1831
1832 return gXcvrSuccess_c;
1833 }
1834
1835 /*! *********************************************************************************
1836 * \brief This function sets the frequency at the PLL for test mode and overrides the BLE/ZB channel
1837 *
1838 * \param[in] freq: Frequency in KHz.
1839 * \param[in] refOsc: Osc in MHz.
1840 *
1841 * \return status of the operation.
1842 *
1843 * \ingroup PrivateAPIs
1844 *
1845 * \details
1846
1847 The Manual carrier frequency selected can be calculated using the formula below:
1848 Radio Carrier Frequency = ((Reference Clock Frequency x 2) x (LPM_INTG +
1849 (LPM_NUM / LPM_DENOM))
1850 WARNING : The fraction (LPM_NUM / LPM_DENOM) must be in the range of -0.55
1851 to +0.55 for valid Sigma Delta Modulator operation.
1852
1853 *
1854 ***********************************************************************************/
XcvrOverrideFrequency(uint32_t freq,uint32_t refOsc)1855 xcvrStatus_t XcvrOverrideFrequency ( uint32_t freq , uint32_t refOsc)
1856 {
1857 int32_t intg;
1858 int32_t num;
1859 int32_t denom = 0x04000000;
1860 uint32_t sdRate = 64000000;
1861 double fract_check;
1862
1863 intg = (uint32_t) freq / sdRate;
1864
1865 /* CTUNE Target must be loaded manually +/- 6MHz should be ok for PLL Lock. */
1866 XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(XCVR, freq/1000000);
1867 XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TD(XCVR,1); /*CTUNE Target Disable */
1868
1869 XCVR_PLL_CHAN_MAP |= XCVR_PLL_CHAN_MAP_BOC_MASK | XCVR_PLL_CHAN_MAP_ZOC_MASK;
1870
1871 XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(XCVR, 1);
1872
1873 fract_check = (freq % sdRate);
1874 fract_check /= sdRate;
1875
1876 if (fract_check >= 0.55)
1877 {
1878 fract_check--;
1879 intg++;
1880 }
1881
1882 num = refOsc;
1883 num = (int32_t) (fract_check * denom);
1884
1885 if (num < 0)
1886 num = (((1 << 28) - 1) & ((1 << 28) - 1) - ABS(num)) + 1;
1887
1888 XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(XCVR, intg);
1889 XCVR_BWR_PLL_LP_SDM_CTRL2_LPM_NUM(XCVR, num);
1890 XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR, denom);
1891
1892 return gXcvrSuccess_c;
1893 }
1894
1895 /*! *********************************************************************************
1896 * \brief This function reads the RF PLL values and returns the programmed frequency
1897 *
1898 * \return Frequency generated by the PLL.
1899 *
1900 * \ingroup PrivateAPIs
1901 *
1902 * \details
1903 *
1904 ***********************************************************************************/
XcvrGetFreq(void)1905 uint32_t XcvrGetFreq ( void )
1906 {
1907 uint32_t pll_int, pll_denom;
1908 int64_t pll_num;
1909
1910 pll_int = XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG(XCVR);
1911 pll_num = XCVR_BRD_PLL_LP_SDM_CTRL2_LPM_NUM(XCVR);
1912
1913 if ( (pll_num & 0x0000000004000000) == 0x0000000004000000)
1914 pll_num = 0xFFFFFFFFF8000000 + pll_num; /* Sign extend the numerator */
1915
1916 pll_denom = XCVR_BRD_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR);
1917
1918 /* Original formula: ((float) pll_int + ((float)pll_num / (float)pll_denom)) * 64 */
1919 return (uint32_t)(pll_int << 6) + ((pll_num << 6) / pll_denom); /* Calculate the frequency in MHz */
1920 }
1921
1922 /*! *********************************************************************************
1923 * \brief This function overrides the TSM module and starts the RX warmup procedure
1924 *
1925 * \ingroup PrivateAPIs
1926 *
1927 * \details
1928 *
1929 ***********************************************************************************/
XcvrForceRxWu(void)1930 void XcvrForceRxWu ( void )
1931 {
1932 /* Set "FORCE_RX_EN" in TSM Control register */
1933 XCVR_BWR_TSM_CTRL_FORCE_RX_EN(XCVR, 1);
1934 }
1935
1936 /*! *********************************************************************************
1937 * \brief This function overrides the TSM module and starts the RX warmdown procedure
1938 *
1939 * \ingroup PrivateAPIs
1940 *
1941 * \details
1942 *
1943 ***********************************************************************************/
XcvrForceRxWd(void)1944 void XcvrForceRxWd ( void )
1945 {
1946 /* Clear "FORCE_RX_EN" in TSM Control register */
1947 XCVR_BWR_TSM_CTRL_FORCE_RX_EN(XCVR, 0);
1948 }
1949
1950 /*! *********************************************************************************
1951 * \brief This function overrides the TSM module and starts the TX warmup procedure
1952 *
1953 * \ingroup PrivateAPIs
1954 *
1955 * \details
1956 *
1957 ***********************************************************************************/
XcvrForceTxWu(void)1958 void XcvrForceTxWu ( void )
1959 {
1960 XCVR_BWR_TSM_CTRL_FORCE_TX_EN(XCVR, 1);
1961 }
1962
1963 /*! *********************************************************************************
1964 * \brief This function overrides the TSM module and starts the TX warmdown procedure
1965 *
1966 * \ingroup PrivateAPIs
1967 *
1968 * \details
1969 *
1970 ***********************************************************************************/
XcvrForceTxWd(void)1971 void XcvrForceTxWd ( void )
1972 {
1973 XCVR_BWR_TSM_CTRL_FORCE_TX_EN(XCVR, 0);
1974
1975 /* Clear "TX_CW_NOMOD" bit in TX Digital Control register */
1976 XCVR_BWR_TX_DIG_CTRL_DFT_MODE(XCVR, 0); /* Normal radio operation */
1977 }
1978
1979 /*! *********************************************************************************
1980 * \brief This function performs an unmodulated TX test.
1981 *
1982 * \ingroup PrivateAPIs
1983 *
1984 * \details
1985 *
1986 ***********************************************************************************/
XcvrTxTest(void)1987 void XcvrTxTest ( void )
1988 {
1989 volatile uint32_t rez[128], i;
1990
1991 for(i=0;i<=127;i++)
1992 {
1993 XcvrOverrideChannel (i, 0);
1994 rez[i] = XcvrGetFreq ();
1995 XcvrForceTxWu();
1996 XcvrDelay(30000);
1997 XcvrForceTxWd();
1998 }
1999
2000 XcvrOverrideChannel (0xFF, 1);
2001 }
2002
2003 /*! *********************************************************************************
2004 * \brief Temporary delay function
2005 *
2006 * \param[in] time the number of counts to decrement through in a wait loop.
2007 *
2008 * \return none.
2009 *
2010 * \ingroup PrivateAPIs
2011 *
2012 * \details
2013 *
2014 ***********************************************************************************/
XcvrDelay(volatile uint32_t time)2015 void XcvrDelay(volatile uint32_t time){
2016 while(time>0){
2017 time--;
2018 }
2019 }
2020
2021 /*! *********************************************************************************
2022 * \brief Manual DCOC calibration function to support board level calibration.
2023 *
2024 * \param[in] chnum Channel number.
2025 *
2026 * \ingroup PrivateAPIs
2027 *
2028 * \details
2029 * Performs manual DCOC calibration and sets TZA and BBF gains per this calibration.
2030 * Disables DCOC_CAL_EN to prevent TSM signals from triggering calibration.
2031 * Intended to enable software development to continue during DCOC cal debug.
2032 *
2033 ***********************************************************************************/
XcvrManualDCOCCal(uint8_t chnum)2034 void XcvrManualDCOCCal (uint8_t chnum)
2035 {
2036 static uint8_t DAC_idx;
2037 static int16_t dc_meas_i;
2038 static int16_t dc_meas_q;
2039 static int16_t dc_meas_total;
2040 static uint8_t curr_min_dc_tza_i_idx, curr_min_dc_tza_q_idx;
2041 static int16_t curr_min_dc_tza_i, curr_min_dc_tza_q;
2042 static int16_t curr_min_dc_total;
2043 static uint8_t curr_min_dc_bbf_i_idx, curr_min_dc_bbf_q_idx;
2044 static int16_t curr_min_dc_bbf_i, curr_min_dc_bbf_q;
2045 uint32_t dcoc_ctrl_0_stack;
2046 uint32_t dcoc_ctrl_1_stack;
2047 uint32_t dcoc_cal_gain_state;
2048 uint8_t gearshift_state;
2049
2050 XcvrOverrideChannel(chnum,TRUE);
2051
2052 dcoc_ctrl_0_stack = XCVR_DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */
2053 dcoc_ctrl_1_stack = XCVR_DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */
2054 dcoc_cal_gain_state = XCVR_DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */
2055 gearshift_state = XCVR_BRD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(XCVR); /* Save state of gearshift control for later restore */
2056
2057 /* Set DCOC_CTRL_0, DCOC_CAL_GAIN, and GEARSHIFT to appropriate values for manual nulling of DC */
2058 XCVR_DCOC_CTRL_0 = ((0x2 << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT) |
2059 (0x3 << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT) |
2060 (0x3 << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT) |
2061 (0x12 << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT) |
2062 (0x52 << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT) |
2063 (0x10 << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT) |
2064 (0x1 << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) |
2065 (0x1 << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) |
2066 (0x1 << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)
2067 );
2068 XCVR_DCOC_CTRL_1 = ((0x0 << XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT) |
2069 (0x1 << XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT) |
2070 (0x1 << XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT)
2071 );
2072 XCVR_DCOC_CAL_GAIN = ((0x03 << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT) |
2073 (0x02 << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT) |
2074 (0x08 << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT) |
2075 (0x02 << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT) |
2076 (0x03 << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT) |
2077 (0x08 << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT)
2078 );
2079
2080 XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(XCVR, 0x00);
2081
2082 /* Search for optimal DC DAC settings */
2083 XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(XCVR, 1); /* DCOC track */
2084 XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(XCVR, 0); /* AGC Control */
2085 XCVR_BWR_RX_DIG_CTRL_RX_DCOC_EN(XCVR, 1); /* DCOC_EN */
2086 XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(XCVR, 0); /* DCOC_CAL 0=disabled; 1=Enabled */
2087 XcvrForceRxWu();
2088 XcvrDelay(2000);
2089
2090 XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(XCVR, 1); /* Force dcoc dacs to use manual override */
2091
2092 /* Go through gain table to get each setting */
2093
2094 static uint8_t tbl_idx;
2095 uint8_t * tbl_ptr=(uint8_t *)(&XCVR_AGC_GAIN_TBL_03_00);
2096 static uint8_t tbl_val;
2097 for (tbl_idx = 0; tbl_idx <27; tbl_idx++)
2098 {
2099 tbl_val = *tbl_ptr;
2100 tbl_ptr++;
2101 XCVR_BWR_AGC_CTRL_1_LNM_USER_GAIN(XCVR, ((0xF0&tbl_val)>>4)); /* Set Manual Gain Index for LNM */
2102 XCVR_BWR_AGC_CTRL_1_BBF_USER_GAIN(XCVR, (0x0F&tbl_val)); /* Set Manual Gain Index for BBF */
2103 XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(XCVR, 1); /* Use Manual Gain for LNM */
2104 XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(XCVR, 1); /* Use Manual Gain for BBF */
2105
2106 XcvrDelay(32*3);
2107
2108 /* Init fixed, mid-point values for BBF while sweeping TZA */
2109 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, 0x20); /* Set bbf I to mid */
2110 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, 0x20); /* Set bbf Q to mid */
2111
2112 /* Measure optimal TZA DAC setting */
2113 curr_min_dc_tza_i = 2000;
2114 curr_min_dc_tza_q = 2000;
2115 curr_min_dc_total = 4000;
2116 DAC_idx=0;
2117
2118 if(0) /* Set to 1 for brute force, takes a long time */
2119 {
2120 do
2121 {
2122 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, (0x00FF & DAC_idx));
2123 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, (0xFF00 & DAC_idx)>>8);
2124 XcvrDelay(32*2);
2125 /* Take I measurement */
2126 dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR);
2127 dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0);
2128 dc_meas_i = (dc_meas_i < 0) ? (-1*dc_meas_i) : (dc_meas_i);
2129
2130 /* Take Q measurement */
2131 dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR);
2132 dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0);
2133 dc_meas_q = (dc_meas_q < 0) ? (-1*dc_meas_q) : (dc_meas_q);
2134 dc_meas_total = dc_meas_i + dc_meas_q;
2135 if(dc_meas_total < curr_min_dc_total)
2136 {
2137 curr_min_dc_total = dc_meas_total;
2138 curr_min_dc_tza_i_idx = (0x00FF & DAC_idx);
2139 curr_min_dc_tza_q_idx = (0xFF00 & DAC_idx)>>8;
2140 }
2141
2142 if(dc_meas_i < curr_min_dc_tza_i)
2143 {
2144 curr_min_dc_tza_i = dc_meas_i;
2145 }
2146 if(dc_meas_q < curr_min_dc_tza_q)
2147 {
2148 curr_min_dc_tza_q = dc_meas_q;
2149 }
2150 DAC_idx++;
2151 } while (DAC_idx > 0); /* Relies on 8 bit increment rolling over to zero. */
2152 }
2153 else
2154 {
2155 do /* First do I channel because it is aggressor */
2156 {
2157 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, DAC_idx);
2158 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, 0x80);
2159 XcvrDelay(32*2);
2160
2161 /* Take I measurement */
2162 dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR);
2163 dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0);
2164 dc_meas_i = (dc_meas_i < 0) ? (-1*dc_meas_i) : (dc_meas_i);
2165 if(dc_meas_i < curr_min_dc_tza_i)
2166 {
2167 curr_min_dc_tza_i = dc_meas_i;
2168 curr_min_dc_tza_i_idx = DAC_idx;
2169 }
2170 DAC_idx++;
2171 } while (DAC_idx > 0); /* Relies on 8 bit increment rolling over to zero. */
2172 DAC_idx=0;
2173 do /* First do Q channel */
2174 {
2175 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, curr_min_dc_tza_i_idx);
2176 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, DAC_idx);
2177 XcvrDelay(32*2);
2178 /* Take Q measurement */
2179 dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR);
2180 dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0);
2181 dc_meas_q = (dc_meas_q < 0) ? (-1*dc_meas_q) : (dc_meas_q);
2182 if(dc_meas_q < curr_min_dc_tza_q)
2183 {
2184 curr_min_dc_tza_q = dc_meas_q;
2185 curr_min_dc_tza_q_idx = DAC_idx;
2186 }
2187 DAC_idx++;
2188 } while (DAC_idx > 0); /* relies on 8 bit increment rolling over to zero. */
2189 }
2190 /* Now set the manual TZA settings from this sweep */
2191 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, curr_min_dc_tza_i_idx);
2192 XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, curr_min_dc_tza_q_idx);
2193 curr_min_dc_tza_i_idx = (curr_min_dc_tza_i_idx >= 0x80) ? ((curr_min_dc_tza_i_idx-0x80)) : ((0x80+curr_min_dc_tza_i_idx));
2194 curr_min_dc_tza_q_idx = (curr_min_dc_tza_q_idx >= 0x80) ? ((curr_min_dc_tza_q_idx-0x80)) : ((0x80+curr_min_dc_tza_q_idx));
2195
2196 /* Measure optimal BBF I DAC setting (I and Q split as there are I->Q DC changes) */
2197 curr_min_dc_bbf_i = curr_min_dc_tza_i;
2198 curr_min_dc_bbf_i_idx = 0x20;
2199 for (DAC_idx=0;DAC_idx<=63;DAC_idx+=1)
2200 {
2201 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, DAC_idx); /* Adjust I bbf DAC */
2202 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, 0x20); //set bbf Q to mid
2203 XcvrDelay(32*2);
2204 dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR); /* Take I measurement */
2205 dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0);
2206 dc_meas_i = (dc_meas_i < 0) ? (-1*dc_meas_i) : (dc_meas_i);
2207 if(dc_meas_i < curr_min_dc_bbf_i)
2208 {
2209 curr_min_dc_bbf_i = dc_meas_i;
2210 curr_min_dc_bbf_i_idx = DAC_idx;
2211 }
2212 }
2213
2214 /* Measure optimal BBF Q DAC setting (I and Q split as there are I->Q DC changes) */
2215 curr_min_dc_bbf_q = curr_min_dc_tza_q;
2216 curr_min_dc_bbf_q_idx = 0x20;
2217 for (DAC_idx=0;DAC_idx<=63;DAC_idx+=1)
2218 {
2219 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, curr_min_dc_bbf_i_idx); /* Set bbf I to calibrated value */
2220 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, DAC_idx); /* Adjust bbf Q */
2221 XcvrDelay(32*2);
2222 dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR); /* Take Q measurement */
2223 dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0);
2224 XcvrDelay(32*2);
2225 dc_meas_q = (dc_meas_q < 0) ? (-1*dc_meas_q) : (dc_meas_q);
2226 if(dc_meas_q < curr_min_dc_bbf_q)
2227 {
2228 curr_min_dc_bbf_q = dc_meas_q;
2229 curr_min_dc_bbf_q_idx = DAC_idx;
2230 }
2231 }
2232 /* Now set the manual BBF Q settings from this sweep */
2233 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, curr_min_dc_bbf_q_idx); /* Set bbf Q to new manual value */
2234 XcvrDelay(32*15);
2235
2236 dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR); /* Take final I measurement */
2237 XcvrDelay(32*10);
2238 dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR); /* Take final Q measurement */
2239 dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0);
2240 dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0);
2241 XcvrDelay(32*2);
2242
2243 /* Store this gain setting's dc dac values */
2244 XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(XCVR, tbl_idx,curr_min_dc_tza_q_idx);
2245 XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(XCVR, tbl_idx,curr_min_dc_tza_i_idx);
2246 curr_min_dc_bbf_i_idx = (curr_min_dc_bbf_i_idx >= 0x20) ? ((curr_min_dc_bbf_i_idx-0x20)) : (0x20+(curr_min_dc_bbf_i_idx));
2247 curr_min_dc_bbf_q_idx = (curr_min_dc_bbf_q_idx >= 0x20) ? ((curr_min_dc_bbf_q_idx-0x20)) : (0x20+(curr_min_dc_bbf_q_idx));
2248 XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(XCVR, tbl_idx,curr_min_dc_bbf_q_idx);
2249 XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(XCVR, tbl_idx,curr_min_dc_bbf_i_idx);
2250 }
2251
2252 /* Now set the manual BBF settings from this sweep */
2253 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, curr_min_dc_bbf_i_idx); /* Set bbf I to new manual value */
2254 XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, curr_min_dc_bbf_q_idx); /* Set bbf Q to new manual value */
2255 XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(XCVR, DCOC_TRACK_EN_def_c); /* Disable tracking */
2256 XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(XCVR, 0); /* Force dcoc dacs to not use manual override */
2257
2258 XCVR_BWR_DCOC_CTRL_1_BBA_CORR_POL(XCVR, 1);
2259 XCVR_BWR_DCOC_CTRL_1_TZA_CORR_POL(XCVR, 1);
2260 XcvrForceRxWd();
2261 XcvrDelay(200);
2262
2263 /* Revert AGC settings to normal values for usage */
2264 XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(XCVR, 0); /* Use Manual Gain for LNM */
2265 XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(XCVR, 0); /* Use Manual Gain for BBF */
2266 XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(XCVR, RX_AGC_EN_def_c); /* AGC Control enabled */
2267 XCVR_DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */
2268 XCVR_DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */
2269 XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(XCVR, gearshift_state); /* Restore gearshift state to prior setting */
2270 XCVR_DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */
2271 XcvrOverrideChannel(0xFF,TRUE); /* Release channel overrides */
2272 }
2273
2274 /*! *********************************************************************************
2275 * \brief IQ Mismatch Calibration. Performs IQMCalibrationIter calibrations, averages and set the calibration values in the XCVR_IQMC_CAL register
2276 *
2277 * \ingroup PublicAPIs
2278 *
2279 * \details IQMC requires a tone input of 250 kHz (+/-75 kHz) to be applied at the RF port and RF/Ana gains set up to for a 0-5 dBm signal at ADC
2280 *
2281 ***********************************************************************************/
XcvrIQMCal(void)2282 void XcvrIQMCal ( void )
2283 {
2284 uint8_t CH_filt_bypass_state;
2285 uint8_t Decimator_OSR_state;
2286 uint16_t IQMC_gain_cal_trials[IQMCalibrationTrials]={0};
2287 uint16_t IQMC_phase_cal_trials[IQMCalibrationTrials]={0};
2288 uint8_t cnt;
2289 uint32_t cal_wait_time;
2290 uint32_t IQMC_gain_adj_sum = 0;
2291 uint32_t IQMC_phase_adj_sum = 0;
2292 uint16_t IQMC_gain_adj_mean = 0;
2293 uint16_t IQMC_phase_adj_mean = 0;
2294
2295 /* Read current Rx Decimation OSR Value and Channel Filter State. Set Decimation Filter OSR to 2 and Bypass Rx Channel Filter */
2296 Decimator_OSR_state = XCVR_BRD_RX_DIG_CTRL_RX_DEC_FILT_OSR(XCVR);
2297 CH_filt_bypass_state = XCVR_BRD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(XCVR);
2298 XCVR_BWR_RX_DIG_CTRL_RX_DEC_FILT_OSR(XCVR, 2); /* Set Decimation OSR to 2 */
2299 XCVR_BWR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(XCVR, 1); /* Bypass Channel Filter */
2300
2301 for (cnt=0;cnt<IQMCalibrationTrials;cnt+=1)
2302 {
2303 /* Set up for IQMC calibration trial */
2304 XCVR_BWR_IQMC_CAL_IQMC_GAIN_ADJ(XCVR, 0x400); /* Set IQ gain mismatch to default (1.0) */
2305 XCVR_BWR_IQMC_CAL_IQMC_PHASE_ADJ(XCVR, 0x0); /* Set IQ phase mismatch to default (0) */
2306 XCVR_BWR_IQMC_CTRL_IQMC_NUM_ITER(XCVR, IQMCalibrationIter); /* Set number of iterations to compute IQMC. Default: 0x80. Max: 0xFF */
2307 XCVR_BWR_IQMC_CTRL_IQMC_CAL_EN(XCVR, 1); /* Enable IQMC HW Calibration */
2308
2309 /* Wait for IQMCalibrationIter * 13 microseconds */
2310 cal_wait_time = IQMCalibrationIter * 13 * 32;
2311 XcvrDelay(cal_wait_time);
2312
2313 /* Read Calibration Trial Results and save in Trial Value Buffers */
2314 IQMC_gain_cal_trials[cnt] = XCVR_BRD_IQMC_CAL_IQMC_GAIN_ADJ(XCVR);
2315 IQMC_phase_cal_trials[cnt] = XCVR_BRD_IQMC_CAL_IQMC_PHASE_ADJ(XCVR);
2316
2317 /* Compute Sum of gain/phase adjustment values */
2318 IQMC_gain_adj_sum = IQMC_gain_adj_sum + IQMC_gain_cal_trials[cnt] ;
2319 IQMC_phase_adj_sum = IQMC_phase_adj_sum + IQMC_phase_cal_trials[cnt] ;
2320 }
2321
2322 /* Average Trial Values and load in XCVR_IQMC_CAL register */
2323 IQMC_gain_adj_mean = IQMC_gain_adj_sum/IQMCalibrationTrials;
2324 IQMC_phase_adj_mean = IQMC_phase_adj_sum/IQMCalibrationTrials;
2325
2326 XCVR_BWR_IQMC_CAL_IQMC_GAIN_ADJ(XCVR, IQMC_gain_adj_mean); /* Set IQ gain mismatch to default (1.0) */
2327 XCVR_BWR_IQMC_CAL_IQMC_PHASE_ADJ(XCVR, IQMC_phase_adj_mean); /* Set IQ phase mismatch to default (0) */
2328
2329 /* Restore Decimation OSR Value and Channel Filter State. */
2330 XCVR_BWR_RX_DIG_CTRL_RX_DEC_FILT_OSR(XCVR, Decimator_OSR_state);
2331 XCVR_BWR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(XCVR, CH_filt_bypass_state);
2332 }
2333
