1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef MMA8491Q_H_ 9 #define MMA8491Q_H_ 10 11 /** 12 ** 13 ** MMA8491Q Sensor Internal Registers 14 */ 15 enum 16 { 17 MMA8491Q_STATUS = 0x00, 18 MMA8491Q_OUT_X_MSB = 0x01, 19 MMA8491Q_OUT_X_LSB = 0x02, 20 MMA8491Q_OUT_Y_MSB = 0x03, 21 MMA8491Q_OUT_Y_LSB = 0x04, 22 MMA8491Q_OUT_Z_MSB = 0x05, 23 MMA8491Q_OUT_Z_LSB = 0x06, 24 }; 25 26 #define MMA8491Q_I2C_ADDRESS (0x55) /* MMA8491Q I2C Slave Address. */ 27 28 #define MMA8491Q_T_RST_MIN (1U) /* Approx time between falling edge of EN and next rising edge of EN. */ 29 #define MMA8491Q_T_ON_TYPICAL (1U) /* Approx time taken for Data to become available after rising edge of EN. */ 30 31 /*-------------------------------- 32 ** Register: STATUS 33 ** Enum: MMA8491Q_STATUS 34 ** -- 35 ** Offset : 0x00 - Data-ready status information 36 ** ------------------------------*/ 37 typedef union 38 { 39 struct 40 { 41 uint8_t xdr : 1; /* - X-Axis new Data Available. */ 42 43 uint8_t ydr : 1; /* - Y-Axis new data available. */ 44 45 uint8_t zdr : 1; /* - Z-Axis new data available. */ 46 47 uint8_t zyxdr : 1; /* - X or Y or Z-Axis new data available. */ 48 49 uint8_t reserved : 4; /* - Reserved bits (Will always be set to zero). */ 50 51 } b; 52 uint8_t w; 53 } MMA8491Q_STATUS_t; 54 55 /* 56 ** STATUS - Bit field mask definitions 57 */ 58 #define MMA8491Q_STATUS_XDR_MASK ((uint8_t)0x01) 59 #define MMA8491Q_STATUS_XDR_SHIFT ((uint8_t)0) 60 61 #define MMA8491Q_STATUS_YDR_MASK ((uint8_t)0x02) 62 #define MMA8491Q_STATUS_YDR_SHIFT ((uint8_t)1) 63 64 #define MMA8491Q_STATUS_ZDR_MASK ((uint8_t)0x04) 65 #define MMA8491Q_STATUS_ZDR_SHIFT ((uint8_t)2) 66 67 #define MMA8491Q_STATUS_ZYXDR_MASK ((uint8_t)0x08) 68 #define MMA8491Q_STATUS_ZYXDR_SHIFT ((uint8_t)3) 69 70 #define MMA8491Q_STATUS_RESERVED_MASK ((uint8_t)0xF0) 71 #define MMA8491Q_STATUS_RESERVED_SHIFT ((uint8_t)4) 72 73 /* 74 ** STATUS - Bit field value definitions 75 */ 76 #define MMA8491Q_STATUS_XDR_DRDY ((uint8_t)0x01) /* - Set to 1 whenever new X-axis data acquisition is */ 77 /* completed. XDR is cleared any time OUT_X_MSB register */ 78 /* is read. */ 79 #define MMA8491Q_STATUS_YDR_DRDY ((uint8_t)0x02) /* - Set to 1 whenever new Y-axis data acquisition is */ 80 /* completed. YDR is cleared any time OUT_Y_MSB register */ 81 /* is read. */ 82 #define MMA8491Q_STATUS_ZDR_DRDY ((uint8_t)0x04) /* - Set to 1 whenever new Z-axis data acquisition is */ 83 /* completed. ZDR is cleared any time OUT_Z_MSB register */ 84 /* is read. */ 85 #define MMA8491Q_STATUS_ZYXDR_DRDY ((uint8_t)0x08) /* - Signals that new acquisition for any of the enabled */ 86 /* channels is available. ZYXDR is cleared when the */ 87 /* high-bytes of the acceleration data (OUT_X_MSB, */ 88 /* OUT_Y_MSB, OUT_Z_MSB) of all channels are read. */ 89 #define MMA8491Q_STATUS_RESERVED_ZERO ((uint8_t)0x00) /* - Value of reserved field. */ 90 /*------------------------------*/ 91 92 /*-------------------------------- 93 ** Register: OUT_X_MSB 94 ** Enum: MMA8491Q_OUT_X_MSB 95 ** -- 96 ** Offset : 0x01 - Bits 8-15 of 14-bit X-Axis output sample data (expressed as 2's complement numbers). 97 ** ------------------------------*/ 98 typedef uint8_t MMA8491Q_OUT_X_MSB_t; 99 100 /*-------------------------------- 101 ** Register: OUT_X_LSB 102 ** Enum: MMA8491Q_OUT_X_LSB 103 ** -- 104 ** Offset : 0x02 - Bits 0-7 of 14-bit X-Axis output sample data (expressed as 2's complement numbers). 105 ** ------------------------------*/ 106 typedef union 107 { 108 struct 109 { 110 uint8_t _reserved_ : 2; 111 uint8_t out_x_lsb : 6; /* - OUT_X_LSB register bits 2-7. (Bit 0 and 1 will always be 0). */ 112 113 } b; 114 uint8_t w; 115 } MMA8491Q_OUT_X_LSB_t; 116 117 /* 118 ** OUT_X_LSB - Bit field mask definitions 119 */ 120 #define MMA8491Q_OUT_X_LSB_OUT_X_LSB_MASK ((uint8_t)0xFC) 121 #define MMA8491Q_OUT_X_LSB_OUT_X_LSB_SHIFT ((uint8_t)2) 122 123 /*------------------------------*/ 124 125 /*-------------------------------- 126 ** Register: OUT_Y_MSB 127 ** Enum: MMA8491Q_OUT_Y_MSB 128 ** -- 129 ** Offset : 0x03 - Bits 8-15 of 14-bit Y-Axis output sample data (expressed as 2's complement numbers). 130 ** ------------------------------*/ 131 typedef uint8_t MMA8491Q_OUT_Y_MSB_t; 132 133 /*-------------------------------- 134 ** Register: OUT_Y_LSB 135 ** Enum: MMA8491Q_OUT_Y_LSB 136 ** -- 137 ** Offset : 0x04 - Bits 0-7 of 14-bit Y-Axis output sample data (expressed as 2's complement numbers). 138 ** ------------------------------*/ 139 typedef union 140 { 141 struct 142 { 143 uint8_t _reserved_ : 2; 144 uint8_t out_y_lsb : 6; /* - OUT_Y_LSB register bits 2-7. (Bit 0 and 1 will always be 0). */ 145 146 } b; 147 uint8_t w; 148 } MMA8491Q_OUT_Y_LSB_t; 149 150 /* 151 ** OUT_Y_LSB - Bit field mask definitions 152 */ 153 #define MMA8491Q_OUT_Y_LSB_OUT_Y_LSB_MASK ((uint8_t)0xFC) 154 #define MMA8491Q_OUT_Y_LSB_OUT_Y_LSB_SHIFT ((uint8_t)2) 155 156 /*------------------------------*/ 157 158 /*-------------------------------- 159 ** Register: OUT_Z_MSB 160 ** Enum: MMA8491Q_OUT_Z_MSB 161 ** -- 162 ** Offset : 0x05 - Bits 8-15 of 14-bit Z-Axis output sample data (expressed as 2's complement numbers). 163 ** ------------------------------*/ 164 typedef uint8_t MMA8491Q_OUT_Z_MSB_t; 165 166 /*-------------------------------- 167 ** Register: OUT_Z_LSB 168 ** Enum: MMA8491Q_OUT_Z_LSB 169 ** -- 170 ** Offset : 0x06 - Bits 0-7 of 14-bit Z-Axis output sample data (expressed as 2's complement numbers). 171 ** ------------------------------*/ 172 typedef union 173 { 174 struct 175 { 176 uint8_t _reserved_ : 2; 177 uint8_t out_z_lsb : 6; /* - OUT_Z_LSB register bits 2-7. (Bit 0 and 1 will always be 0). */ 178 179 } b; 180 uint8_t w; 181 } MMA8491Q_OUT_Z_LSB_t; 182 183 /* 184 ** OUT_Z_LSB - Bit field mask definitions 185 */ 186 #define MMA8491Q_OUT_Z_LSB_OUT_Z_LSB_MASK ((uint8_t)0xFC) 187 #define MMA8491Q_OUT_Z_LSB_OUT_Z_LSB_SHIFT ((uint8_t)2) 188 189 /*------------------------------*/ 190 191 #endif /* MMA8491Q_H_ */ 192
