1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef __RTE_DEVICE_H 9 #define __RTE_DEVICE_H 10 11 /*Driver name mapping*/ 12 #define RTE_I2C0 1 13 #define RTE_I2C0_DMA_EN 0 14 #define RTE_I2C1 1 15 #define RTE_I2C1_DMA_EN 0 16 17 #define RTE_SPI0 1 18 #define RTE_SPI0_DMA_EN 0 19 #define RTE_SPI1 0 20 #define RTE_SPI1_DMA_EN 0 21 22 #define RTE_USART0 1 23 #define RTE_USART0_DMA_EN 0 24 #define RTE_USART1 0 25 #define RTE_USART1_DMA_EN 0 26 #define RTE_USART2 0 27 #define RTE_USART2_DMA_EN 0 28 29 /* UART configuration. */ 30 #define USART_RX_BUFFER_LEN 64 31 #define USART0_RX_BUFFER_ENABLE 1 32 33 #define RTE_USART0_DMA_TX_CH 0 34 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 35 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 36 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 37 #define RTE_USART0_DMA_RX_CH 1 38 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 39 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 40 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 41 42 #define RTE_USART1_DMA_TX_CH 0 43 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx 44 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 45 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 46 #define RTE_USART1_DMA_RX_CH 1 47 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx 48 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 49 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 50 51 #define RTE_USART2_DMA_TX_CH 0 52 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 53 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 54 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 55 #define RTE_USART2_DMA_RX_CH 1 56 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 57 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 58 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 59 60 /* SPI configuration. */ 61 #define RTE_SPI0_DMA_TX_CH 0 62 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 63 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 64 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 65 #define RTE_SPI0_DMA_RX_CH 1 66 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 67 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 68 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 69 70 #define RTE_SPI1_DMA_TX_CH 2 71 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx 72 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 73 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 74 #define RTE_SPI1_DMA_RX_CH 3 75 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx 76 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 77 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 78 79 /*I2C configuration*/ 80 #define RTE_I2C0_Master_DMA_BASE DMA0 81 #define RTE_I2C0_Master_DMA_CH 0 82 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 83 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 84 85 #define RTE_I2C1_Master_DMA_BASE DMA0 86 #define RTE_I2C1_Master_DMA_CH 1 87 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 88 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 89 90 #endif /* __RTE_DEVICE_H */ 91
