1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef __RTE_DEVICE_H 11 #define __RTE_DEVICE_H 12 13 /* Driver name mapping. */ 14 #define RTE_I2C1 1 15 #define RTE_I2C1_DMA_EN 0 16 #define RTE_I2C2 0 17 #define RTE_I2C2_DMA_EN 0 18 #define RTE_I2C3 0 19 #define RTE_I2C3_DMA_EN 0 20 #define RTE_I2C4 0 21 #define RTE_I2C4_DMA_EN 0 22 23 #define RTE_SPI1 1 24 #define RTE_SPI1_DMA_EN 0 25 #define RTE_SPI2 0 26 #define RTE_SPI2_DMA_EN 0 27 #define RTE_SPI3 0 28 #define RTE_SPI3_DMA_EN 0 29 #define RTE_SPI4 0 30 #define RTE_SPI4_DMA_EN 0 31 32 #define RTE_USART1 1 33 #define RTE_USART1_DMA_EN 0 34 #define RTE_USART2 0 35 #define RTE_USART2_DMA_EN 0 36 #define RTE_USART3 0 37 #define RTE_USART3_DMA_EN 0 38 #define RTE_USART4 0 39 #define RTE_USART4_DMA_EN 0 40 #define RTE_USART5 0 41 #define RTE_USART5_DMA_EN 0 42 #define RTE_USART6 0 43 #define RTE_USART6_DMA_EN 0 44 #define RTE_USART7 0 45 #define RTE_USART7_DMA_EN 0 46 #define RTE_USART8 1 47 #define RTE_USART8_DMA_EN 0 48 49 /* LPI2C configuration. */ 50 #define RTE_I2C1_DMA_TX_CH 0 51 #define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C1 52 #define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX 53 #define RTE_I2C1_DMA_TX_DMA_BASE DMA0 54 #define RTE_I2C1_DMA_RX_CH 1 55 #define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C1 56 #define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX 57 #define RTE_I2C1_DMA_RX_DMA_BASE DMA0 58 59 #define RTE_I2C2_DMA_TX_CH 2 60 #define RTE_I2C2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C2 61 #define RTE_I2C2_DMA_TX_DMAMUX_BASE DMAMUX 62 #define RTE_I2C2_DMA_TX_DMA_BASE DMA0 63 #define RTE_I2C2_DMA_RX_CH 3 64 #define RTE_I2C2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C2 65 #define RTE_I2C2_DMA_RX_DMAMUX_BASE DMAMUX 66 #define RTE_I2C2_DMA_RX_DMA_BASE DMA0 67 68 #define RTE_I2C3_DMA_TX_CH 4 69 #define RTE_I2C3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C3 70 #define RTE_I2C3_DMA_TX_DMAMUX_BASE DMAMUX 71 #define RTE_I2C3_DMA_TX_DMA_BASE DMA0 72 #define RTE_I2C3_DMA_RX_CH 5 73 #define RTE_I2C3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C3 74 #define RTE_I2C3_DMA_RX_DMAMUX_BASE DMAMUX 75 #define RTE_I2C3_DMA_RX_DMA_BASE DMA0 76 77 #define RTE_I2C4_DMA_TX_CH 6 78 #define RTE_I2C4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C4 79 #define RTE_I2C4_DMA_TX_DMAMUX_BASE DMAMUX 80 #define RTE_I2C4_DMA_TX_DMA_BASE DMA0 81 #define RTE_I2C4_DMA_RX_CH 7 82 #define RTE_I2C4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C4 83 #define RTE_I2C4_DMA_RX_DMAMUX_BASE DMAMUX 84 #define RTE_I2C4_DMA_RX_DMA_BASE DMA0 85 86 /* SPI configuration. */ 87 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 88 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 89 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 90 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 91 #define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 92 #define RTE_SPI1_DMA_TX_CH 0 93 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI1Tx 94 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX 95 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 96 #define RTE_SPI1_DMA_RX_CH 1 97 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI1Rx 98 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX 99 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 100 101 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 102 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 103 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 104 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 105 #define RTE_SPI2_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 106 #define RTE_SPI2_DMA_TX_CH 2 107 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI2Tx 108 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX 109 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 110 #define RTE_SPI2_DMA_RX_CH 3 111 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI2Tx 112 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX 113 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 114 115 #define RTE_SPI3_PCS_TO_SCK_DELAY 1000 116 #define RTE_SPI3_SCK_TO_PSC_DELAY 1000 117 #define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000 118 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 119 #define RTE_SPI3_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 120 #define RTE_SPI3_DMA_TX_CH 4 121 #define RTE_SPI3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI3Tx 122 #define RTE_SPI3_DMA_TX_DMAMUX_BASE DMAMUX 123 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 124 #define RTE_SPI3_DMA_RX_CH 5 125 #define RTE_SPI3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI3Rx 126 #define RTE_SPI3_DMA_RX_DMAMUX_BASE DMAMUX 127 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 128 129 #define RTE_SPI4_PCS_TO_SCK_DELAY 1000 130 #define RTE_SPI4_SCK_TO_PSC_DELAY 1000 131 #define RTE_SPI4_BETWEEN_TRANSFER_DELAY 1000 132 #define RTE_SPI4_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 133 #define RTE_SPI4_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 134 #define RTE_SPI4_DMA_TX_CH 6 135 #define RTE_SPI4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI4Tx 136 #define RTE_SPI4_DMA_TX_DMAMUX_BASE DMAMUX 137 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 138 #define RTE_SPI4_DMA_RX_CH 7 139 #define RTE_SPI4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI4Rx 140 #define RTE_SPI4_DMA_RX_DMAMUX_BASE DMAMUX 141 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 142 143 /* UART configuration. */ 144 #define RTE_USART1_DMA_TX_CH 0 145 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Tx 146 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX 147 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 148 #define RTE_USART1_DMA_RX_CH 1 149 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Rx 150 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX 151 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 152 153 #define RTE_USART2_DMA_TX_CH 0 154 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Tx 155 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX 156 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 157 #define RTE_USART2_DMA_RX_CH 1 158 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Rx 159 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX 160 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 161 162 #define RTE_USART3_DMA_TX_CH 0 163 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Tx 164 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX 165 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 166 #define RTE_USART3_DMA_RX_CH 1 167 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Rx 168 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX 169 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 170 171 #define RTE_USART4_DMA_TX_CH 0 172 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Tx 173 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX 174 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 175 #define RTE_USART4_DMA_RX_CH 1 176 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Rx 177 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX 178 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 179 180 #define RTE_USART5_DMA_TX_CH 0 181 #define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Tx 182 #define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX 183 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 184 #define RTE_USART5_DMA_RX_CH 1 185 #define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Rx 186 #define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX 187 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 188 189 #define RTE_USART6_DMA_TX_CH 0 190 #define RTE_USART6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Tx 191 #define RTE_USART6_DMA_TX_DMAMUX_BASE DMAMUX 192 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 193 #define RTE_USART6_DMA_RX_CH 1 194 #define RTE_USART6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Rx 195 #define RTE_USART6_DMA_RX_DMAMUX_BASE DMAMUX 196 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 197 198 #define RTE_USART7_DMA_TX_CH 0 199 #define RTE_USART7_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Tx 200 #define RTE_USART7_DMA_TX_DMAMUX_BASE DMAMUX 201 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 202 #define RTE_USART7_DMA_RX_CH 1 203 #define RTE_USART7_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Rx 204 #define RTE_USART7_DMA_RX_DMAMUX_BASE DMAMUX 205 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 206 207 #define RTE_USART8_DMA_TX_CH 0 208 #define RTE_USART8_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Tx 209 #define RTE_USART8_DMA_TX_DMAMUX_BASE DMAMUX 210 #define RTE_USART8_DMA_TX_DMA_BASE DMA0 211 #define RTE_USART8_DMA_RX_CH 1 212 #define RTE_USART8_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Rx 213 #define RTE_USART8_DMA_RX_DMAMUX_BASE DMAMUX 214 #define RTE_USART8_DMA_RX_DMA_BASE DMA0 215 216 #endif /* __RTE_DEVICE_H */ 217
