1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_mmau.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.mmau"
14 #endif
15
16 /*******************************************************************************
17 * Code
18 ******************************************************************************/
19 /*!
20 * brief Set control/status register into reset state.
21 *
22 * This function sets control/status register to a known state. This state is
23 * defined in Reference Manual, which is power on reset value. This function must
24 * execute in a Supervisor Mode
25 * param base MMAU peripheral address.
26 */
MMAU_Reset(MMAU_Type * base)27 void MMAU_Reset(MMAU_Type *base)
28 {
29 /* Reset all MMAU register */
30 base->X0 = 0U;
31 base->X1 = 0U;
32 base->X2 = 0U;
33 base->X3 = 0U;
34 base->A0 = 0U;
35 base->A1 = 0U;
36 base->CSR = 0U;
37 base->CSR_IF_CLR = 0U;
38 }
39
40 /*!
41 * brief Clears interrupt flags.
42 *
43 * This function clears the interrupt flags.
44 * Example, if you want to clear Overflow and DivideByZero interrupt flags:
45 code
46 MMAU_ClearInterruptFlags(MMAU, kMMAU_OverflowInterruptFlag|kMMAU_DivideByZeroInterruptFlag);
47 endcode
48 *
49 * param base MMAU peripheral address.
50 * param mask Mask of the asserted interrupt flags
51 * (kMMAU_AccumOverflowInterruptFlag|kMMAU_OverflowInterruptFlag|kMMAU_DivideByZeroInterruptFlag).
52 */
MMAU_ClearInterruptFlags(MMAU_Type * base,uint32_t mask)53 void MMAU_ClearInterruptFlags(MMAU_Type *base, uint32_t mask)
54 {
55 uint32_t regVal;
56
57 /* Assign regVal to MMAU_CSR_IF_CLR register's value */
58 regVal = base->CSR_IF_CLR;
59 /* Perform this command to avoid writing 1 into interrupt flag bits, which do not corresponding to the mask */
60 regVal &= (uint32_t)(~((uint32_t)kMMAU_AccumOverflowInterruptFlag | (uint32_t)kMMAU_OverflowInterruptFlag |
61 (uint32_t)kMMAU_DivideByZeroInterruptFlag));
62 /* Write 1 to interrupt flag bits corresponding to mask */
63 regVal |= mask & ((uint32_t)kMMAU_AccumOverflowInterruptFlag | (uint32_t)kMMAU_OverflowInterruptFlag |
64 (uint32_t)kMMAU_DivideByZeroInterruptFlag);
65 /* Write regVal's value into MMAU_CSR_IF_CLR register */
66 base->CSR_IF_CLR = regVal;
67 }
68
69 /*!
70 * brief Sets the instruction flags.
71 *
72 * This function sets the instruction flags.
73 * Example:
74 code
75 MMAU_SetInstructionFlags(MMAU, kMMAU_AccumOverflowInstructionFlag | kMMAU_NegativeInstructionFlag);
76 MMAU_SetInstructionFlags(MMAU, kMMAU_OverflowInstructionFlag | kMMAU_DivideByZeroInstructionFlag);
77 endcode
78 *
79 * param base MMAU peripheral address.
80 * param mask Mask of the instruction flags to be written
81 *
82 (kMMAU_AccumOverflowInstructionFlag|kMMAU_OverflowInstructionFlag|kMMAU_DivideByZeroInstructionFlag|kMMAU_NegativeInstructionFlag).
83 */
MMAU_SetInstructionFlags(MMAU_Type * base,uint32_t mask)84 void MMAU_SetInstructionFlags(MMAU_Type *base, uint32_t mask)
85 {
86 uint32_t regVal;
87
88 /* Assign regVal to MMAU_CSR_IF_CLR register's value */
89 regVal = base->CSR_IF_CLR;
90 /* Write 1 to interrupt flag bits corresponding to mask */
91 regVal |= mask & ((uint32_t)kMMAU_AccumOverflowInstructionFlag | (uint32_t)kMMAU_OverflowInstructionFlag |
92 (uint32_t)kMMAU_DivideByZeroInstructionFlag | (uint32_t)kMMAU_NegativeInstructionFlag);
93 /* Perform this command to avoid writing 1 into interrupt flag bits, which do not corresponding to the mask */
94 regVal &= (uint32_t)(~((uint32_t)kMMAU_AccumOverflowInterruptFlag | (uint32_t)kMMAU_OverflowInterruptFlag |
95 (uint32_t)kMMAU_DivideByZeroInterruptFlag));
96 /* Write regVal's value into MMAU_CSR_IF_CLR register */
97 base->CSR_IF_CLR = regVal;
98 }
99
100 /*!
101 * brief Clears instruction flags.
102 *
103 * This function clears the instruction flags.
104 * Example, if you want to clear Overflow and DivideByZero instruction flags:
105 code
106 MMAU_ClearInstructionFlags(MMAU, kMMAU_OverflowInstructionFlag|kMMAU_DivideByZeroInstructionFlag);
107 endcode
108 *
109 * param base MMAU peripheral address.
110 * param mask Mask of the asserted instruction flags
111 *
112 (kMMAU_AccumOverflowInstructionFlag|kMMAU_OverflowInstructionFlag|kMMAU_DivideByZeroInstructionFlag|kMMAU_NegativeInstructionFlag).
113 */
MMAU_ClearInstructionFlags(MMAU_Type * base,uint32_t mask)114 void MMAU_ClearInstructionFlags(MMAU_Type *base, uint32_t mask)
115 {
116 uint32_t regVal;
117
118 /* Assign regVal to MMAU_CSR_IF_CLR register's value */
119 regVal = base->CSR_IF_CLR;
120 /* Write 0 to interrupt flag bits corresponding to mask */
121 regVal &= ~(mask & ((uint32_t)kMMAU_AccumOverflowInstructionFlag | (uint32_t)kMMAU_OverflowInstructionFlag |
122 (uint32_t)kMMAU_DivideByZeroInstructionFlag | (uint32_t)kMMAU_NegativeInstructionFlag));
123 /* Perform this command to avoid writing 1 into interrupt flag bits, which do not corresponding to the mask */
124 regVal &= (uint32_t)(~((uint32_t)kMMAU_AccumOverflowInterruptFlag | (uint32_t)kMMAU_OverflowInterruptFlag |
125 (uint32_t)kMMAU_DivideByZeroInterruptFlag));
126 /* Write regVal's value into MMAU_CSR_IF_CLR register */
127 base->CSR_IF_CLR = regVal;
128 }
129
