1 /*
2  * Copyright 2019-2021 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef _FSL_MECC_H_
10 #define _FSL_MECC_H_
11 
12 #include "fsl_common.h"
13 
14 /*!
15  * @addtogroup mecc
16  * @{
17  */
18 
19 /******************************************************************************
20  * Definitions.
21  *****************************************************************************/
22 
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief Driver version 2.0.2. */
26 #define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
27 /*@}*/
28 /*! @brief Error codes for the MECC driver. */
29 enum
30 {
31     kStatus_MECC_BankMiss = MAKE_STATUS(kStatusGroup_MECC, 0), /*!< Ocram bank miss */
32 };
33 
34 /*!
35  * @brief MECC interrupt configuration structure, default settings all disabled.
36  *
37  * This structure contains the settings for all of the MECC interrupt configurations.
38  */
39 enum
40 {
41     kMECC_SingleError0InterruptEnable =
42         MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt enable.*/
43     kMECC_SingleError1InterruptEnable =
44         MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt enable*/
45     kMECC_SingleError2InterruptEnable =
46         MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt enable*/
47     kMECC_SingleError3InterruptEnable =
48         MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt enable*/
49 
50     kMECC_MultiError0InterruptEnable =
51         MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt enable*/
52     kMECC_MultiError1InterruptEnable =
53         MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt enable*/
54     kMECC_MultiError2InterruptEnable =
55         MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt enable*/
56     kMECC_MultiError3InterruptEnable =
57         MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt enable*/
58 
59     kMECC_StrobeError0InterruptEnable =
60         MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt enable*/
61     kMECC_StrobeError1InterruptEnable =
62         MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt enable*/
63     kMECC_StrobeError2InterruptEnable =
64         MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt enable*/
65     kMECC_StrobeError3InterruptEnable =
66         MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt enable*/
67 
68     kMECC_AccessError0InterruptEnable =
69         MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt enable*/
70     kMECC_AccessError1InterruptEnable =
71         MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt enable*/
72     kMECC_AccessError2InterruptEnable =
73         MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt enable*/
74     kMECC_AccessError3InterruptEnable =
75         MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt enable*/
76 
77     kMECC_AllInterruptsEnable = 0xFFFF, /*!< all  interrupts enable */
78 };
79 
80 /*!
81  * @brief MECC interrupt status configuration structure, default settings all disabled.
82  *
83  * This structure contains the settings for all of the MECC interrupt status configurations.
84  */
85 enum
86 {
87     kMECC_SingleError0InterruptStatusEnable =
88         MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt status enable.*/
89     kMECC_SingleError1InterruptStatusEnable =
90         MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt status enable*/
91     kMECC_SingleError2InterruptStatusEnable =
92         MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt status enable*/
93     kMECC_SingleError3InterruptStatusEnable =
94         MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt status enable*/
95 
96     kMECC_MultiError0InterruptStatusEnable =
97         MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt status enable*/
98     kMECC_MultiError1InterruptStatusEnable =
99         MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt status enable*/
100     kMECC_MultiError2InterruptStatusEnable =
101         MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt status enable*/
102     kMECC_MultiError3InterruptStatusEnable =
103         MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt status enable*/
104 
105     kMECC_StrobeError0InterruptStatusEnable =
106         MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt status enable*/
107     kMECC_StrobeError1InterruptStatusEnable =
108         MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt status enable*/
109     kMECC_StrobeError2InterruptStatusEnable =
110         MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt status enable*/
111     kMECC_StrobeError3InterruptStatusEnable =
112         MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt status enable*/
113 
114     kMECC_AccessError0InterruptStatusEnable =
115         MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt status enable*/
116     kMECC_AccessError1InterruptStatusEnable =
117         MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt status enable*/
118     kMECC_AccessError2InterruptStatusEnable =
119         MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt status enable*/
120     kMECC_AccessError3InterruptStatusEnable =
121         MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt status enable*/
122 
123     kMECC_AllInterruptsStatusEnable = 0xFFFF, /*!< all  interrupts enable */
124 };
125 
126 /*!
127  * @brief MECC status flags.
128  *
129  * This provides constants for the MECC status flags for use in the MECC functions.
130  */
131 enum
132 {
133     kMECC_SingleError0InterruptFlag =
134         MECC_ERR_STATUS_SINGLE_ERR0_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt flag*/
135     kMECC_SingleError1InterruptFlag =
136         MECC_ERR_STATUS_SINGLE_ERR1_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt flag*/
137     kMECC_SingleError2InterruptFlag =
138         MECC_ERR_STATUS_SINGLE_ERR2_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt flag*/
139     kMECC_SingleError3InterruptFlag =
140         MECC_ERR_STATUS_SINGLE_ERR3_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt flag*/
141 
142     kMECC_MultiError0InterruptFlag =
143         MECC_ERR_STATUS_MULTI_ERR0_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt flag*/
144     kMECC_MultiError1InterruptFlag =
145         MECC_ERR_STATUS_MULTI_ERR1_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt flag*/
146     kMECC_MultiError2InterruptFlag =
147         MECC_ERR_STATUS_MULTI_ERR2_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt flag*/
148     kMECC_MultiError3InterruptFlag =
149         MECC_ERR_STATUS_MULTI_ERR3_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt flag*/
150 
151     kMECC_StrobeError0InterruptFlag =
152         MECC_ERR_STATUS_STRB_ERR0_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt flag*/
153     kMECC_StrobeError1InterruptFlag =
154         MECC_ERR_STATUS_STRB_ERR1_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt flag*/
155     kMECC_StrobeError2InterruptFlag =
156         MECC_ERR_STATUS_STRB_ERR2_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt flag*/
157     kMECC_StrobeError3InterruptFlag =
158         MECC_ERR_STATUS_STRB_ERR3_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt flag*/
159 
160     kMECC_AccessError0InterruptFlag = MECC_ERR_STATUS_ADDR_ERR0_MASK, /*!< Ocram Access Error On Bank0 interrupt flag*/
161     kMECC_AccessError1InterruptFlag = MECC_ERR_STATUS_ADDR_ERR1_MASK, /*!< Ocram Access Error On Bank1 interrupt flag*/
162     kMECC_AccessError2InterruptFlag = MECC_ERR_STATUS_ADDR_ERR2_MASK, /*!< Ocram Access Error On Bank2 interrupt flag*/
163     kMECC_AccessError3InterruptFlag = MECC_ERR_STATUS_ADDR_ERR3_MASK, /*!< Ocram Access Error On Bank3 interrupt flag*/
164 
165     kMECC_AllInterruptsFlag = 0xFFFF, /*!< all interrupts interrupt flag */
166 };
167 
168 /*! @brief MECC ocram bank number */
169 enum
170 {
171     kMECC_OcramBank0 = 0U, /*!< ocram bank number 0: ocram_base_address+0x20*i */
172     kMECC_OcramBank1 = 1U, /*!< ocram bank number 1: ocram_base_address+0x20*i+0x8 */
173     kMECC_OcramBank2 = 2U, /*!< ocram bank number 2: ocram_base_address+0x20*i+0x10 */
174     kMECC_OcramBank3 = 3U, /*!< ocram bank number 3: ocram_base_address+0x20*i+0x18 */
175 };
176 
177 /*! @brief MECC instance */
178 enum
179 {
180     kMECC_Instance0 = 0U, /*!< Peripheral MECC1 base */
181     kMECC_Instance1 = 1U, /*!< Peripheral MECC2 base */
182 };
183 
184 /*! @brief MECC user configuration.*/
185 typedef struct _mecc_config
186 {
187     bool enableMecc;             /*!< Enable the MECC function. */
188     uint32_t Ocram1StartAddress; /*!< Ocram 1 start address. */
189     uint32_t Ocram1EndAddress;   /*!< Ocram 1 end address. */
190     uint32_t Ocram2StartAddress; /*!< Ocram 2 start address. */
191     uint32_t Ocram2EndAddress;   /*!< Ocram 2 end address. */
192 } mecc_config_t;
193 
194 /*! @brief MECC ocram single error information, including single error address, ECC code, error data and error bit
195  * position */
196 typedef struct _mecc_single_error_info
197 {
198     uint32_t singleErrorAddress;  /*!< Single error address on Ocram bank n */
199     uint32_t singleErrorDataLow;  /*!< Single error low 32 bits uncorrected read data on Ocram bank n */
200     uint32_t singleErrorDataHigh; /*!< Single error high 32 bits uncorrected read data on Ocram bank n */
201     uint32_t singleErrorPosLow;   /*!< Single error bit postion of low 32 bits read data on Ocram bank n */
202     uint32_t singleErrorPosHigh;  /*!< Single error bit postion of high 32 bits read data on Ocram bank n */
203     uint8_t singleErrorEccCode;   /*!< Single error ECC code on Ocram bank n */
204 } mecc_single_error_info_t;
205 
206 /*! @brief MECC ocram multiple error information, including multiple error address, ECC code, error data */
207 typedef struct _mecc_multi_error_info
208 {
209     uint32_t multiErrorAddress;  /*!< Multiple error address on Ocram bank n */
210     uint32_t multiErrorDataLow;  /*!< Multiple error low 32 bits read data on Ocram bank n */
211     uint32_t multiErrorDataHigh; /*!< Multiple error high 32 bits read data on Ocram bank n */
212     uint8_t multiErrorEccCode;   /*!< Multiple error ECC code on Ocram bank n */
213 } mecc_multi_error_info_t;
214 
215 /*******************************************************************************
216  * APIs
217  ******************************************************************************/
218 
219 #if defined(__cplusplus)
220 extern "C" {
221 #endif
222 
223 /*!
224  * @name Initialization and deinitialization
225  * @{
226  */
227 
228 /*!
229  * @brief MECC module initialization function.
230  *
231  * @param base MECC base address.
232  * @param config pointer to the MECC configuration structure.
233  */
234 void MECC_Init(MECC_Type *base, mecc_config_t *config);
235 
236 /*!
237  * @brief Deinitializes the MECC.
238  *
239  * @param base MECC base address.
240  */
241 void MECC_Deinit(MECC_Type *base);
242 
243 /*!
244  * @brief Sets the MECC configuration structure to default values.
245  *
246  * @param config pointer to the MECC configuration structure.
247  */
248 void MECC_GetDefaultConfig(mecc_config_t *config);
249 
250 /* @} */
251 
252 /*!
253  * @name Status
254  * @{
255  */
256 /*!
257  * @brief Gets MECC status flags.
258  *
259  * @param base MECC peripheral base address.
260  * @return MECC status flags.
261  */
MECC_GetStatusFlags(MECC_Type * base)262 static inline uint32_t MECC_GetStatusFlags(MECC_Type *base)
263 {
264     return base->ERR_STATUS & (uint32_t)kMECC_AllInterruptsFlag;
265 }
266 
267 /*!
268  * @brief MECC module clear interrupt status.
269  *
270  * @param base MECC base address.
271  * @param mask status to clear.
272  */
MECC_ClearStatusFlags(MECC_Type * base,uint32_t mask)273 static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask)
274 {
275     base->ERR_STATUS = mask;
276 }
277 
278 /*!
279  * @brief MECC module enable interrupt status.
280  *
281  * @param base MECC base address.
282  * @param mask status to enable.
283  */
MECC_EnableInterruptStatus(MECC_Type * base,uint32_t mask)284 static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask)
285 {
286     base->ERR_STAT_EN |= mask;
287 }
288 
289 /*!
290  * @brief MECC module disable interrupt status.
291  *
292  * @param base MECC base address.
293  * @param mask status to disable.
294  */
MECC_DisableInterruptStatus(MECC_Type * base,uint32_t mask)295 static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask)
296 {
297     base->ERR_STAT_EN &= ~mask;
298 }
299 
300 /* @} */
301 
302 /*!
303  * @name Interrupts
304  * @{
305  */
306 
307 /*!
308  * @brief MECC module enable interrupt.
309  *
310  * @param base MECC base address.
311  * @param mask The interrupts to enable.
312  */
MECC_EnableInterrupts(MECC_Type * base,uint32_t mask)313 static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask)
314 {
315     base->ERR_SIG_EN |= mask;
316 }
317 
318 /*!
319  * @brief MECC module disable interrupt.
320  *
321  * @param base MECC base address.
322  * @param mask The interrupts to disable.
323  */
MECC_DisableInterrupts(MECC_Type * base,uint32_t mask)324 static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask)
325 {
326     base->ERR_SIG_EN &= ~mask;
327 }
328 /* @} */
329 
330 /*!
331  * @name functional
332  * @{
333  */
334 
335 /*!
336  * @brief MECC module error injection.
337  *
338  * @param base MECC base address.
339  * @param lowerrordata low 32 bits data.
340  * @param higherrordata high 32 bits data.
341  * @param eccdata ecc code.
342  * @param banknumber ocram bank number.
343  * @retval kStatus_Success.
344  *
345  *   Bank0: ocram_base_address+0x20*i
346  *   Bank1: ocram_base_address+0x20*i+0x8
347  *   Bank2: ocram_base_address+0x20*i+0x10
348  *   Bank3: ocram_base_address+0x20*i+0x18
349  *   i = 0,1,2,3,4.....
350  */
351 status_t MECC_ErrorInjection(
352     MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber);
353 
354 /*!
355  * @brief MECC module get single error information.
356  *
357  * @param base MECC base address.
358  * @param info single error information.
359  * @param banknumber ocram bank number.
360  * @retval kStatus_Success.
361  * @retval kStatus_MECC_BankMiss.
362  *
363  *   Bank0: ocram_base_address+0x20*i
364  *   Bank1: ocram_base_address+0x20*i+0x8
365  *   Bank2: ocram_base_address+0x20*i+0x10
366  *   Bank3: ocram_base_address+0x20*i+0x18
367  *   i = 0,1,2,3,4.....
368  */
369 status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber);
370 
371 /*!
372  * @brief MECC module get multiple error information.
373  *
374  * @param base MECC base address.
375  * @param info multiple error information.
376  * @param banknumber ocram bank number.
377  * @retval kStatus_Success.
378  * @retval kStatus_MECC_BankMiss.
379  *
380  *   Bank0: ocram_base_address+0x20*i
381  *   Bank1: ocram_base_address+0x20*i+0x8
382  *   Bank2: ocram_base_address+0x20*i+0x10
383  *   Bank3: ocram_base_address+0x20*i+0x18
384  *   i = 0,1,2,3,4.....
385  */
386 status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber);
387 
388 /*! @}*/
389 
390 #if defined(__cplusplus)
391 }
392 #endif
393 
394 /*! @}*/
395 
396 #endif
397