1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select. */ 16 /* Select UART0 - UART2. */ 17 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 18 * LPUART instance. */ 19 #define RTE_USART0 0 20 #define RTE_USART0_DMA_EN 0 21 #define RTE_USART1 0 22 #define RTE_USART1_DMA_EN 0 23 #define RTE_USART2 0 24 #define RTE_USART2_DMA_EN 0 25 /* Select LPUART0. */ 26 #define RTE_USART3 0 27 #define RTE_USART3_DMA_EN 0 28 29 /* UART configuration. */ 30 #define USART_RX_BUFFER_LEN 64 31 #define USART0_RX_BUFFER_ENABLE 0 32 #define USART1_RX_BUFFER_ENABLE 0 33 #define USART2_RX_BUFFER_ENABLE 0 34 #define USART3_RX_BUFFER_ENABLE 0 35 36 #define RTE_USART0_PIN_INIT LPUART0_InitPins 37 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 38 #define RTE_USART0_DMA_TX_CH 0 39 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 40 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 41 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 42 #define RTE_USART0_DMA_RX_CH 1 43 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 44 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 45 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 46 47 #define RTE_USART1_PIN_INIT LPUART1_InitPins 48 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 49 #define RTE_USART1_DMA_TX_CH 0 50 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 51 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 52 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 53 #define RTE_USART1_DMA_RX_CH 1 54 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 55 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 56 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 57 58 #define RTE_USART2_PIN_INIT LPUART2_InitPins 59 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 60 #define RTE_USART2_DMA_TX_CH 0 61 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 62 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 63 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 64 #define RTE_USART2_DMA_RX_CH 1 65 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 66 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 67 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 68 69 #define RTE_USART3_PIN_INIT LPUART3_InitPins 70 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 71 #define RTE_USART3_DMA_TX_CH 0 72 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 73 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 74 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 75 #define RTE_USART3_DMA_RX_CH 1 76 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 77 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 78 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 79 80 /* I2C Select, I2C0 - I2C1. */ 81 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 82 */ 83 #define RTE_I2C0 0 84 #define RTE_I2C0_DMA_EN 0 85 #define RTE_I2C1 0 86 #define RTE_I2C1_DMA_EN 0 87 88 /*I2C configuration*/ 89 #define RTE_I2C0_Master_DMA_BASE DMA0 90 #define RTE_I2C0_Master_DMA_CH 0 91 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 92 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 93 94 #define RTE_I2C1_Master_DMA_BASE DMA0 95 #define RTE_I2C1_Master_DMA_CH 1 96 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 97 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 98 99 /* SPI Select, DSPI0 - DSPI1. */ 100 /* User needs to provide the implementation of DSPIX_GetFreq/DSPIX_InitPins/DSPIX_DeinitPins for the enabled DSPI 101 * instance. */ 102 #define RTE_SPI0 0 103 #define RTE_SPI0_DMA_EN 0 104 #define RTE_SPI1 0 105 #define RTE_SPI1_DMA_EN 0 106 107 /* UART configuration. */ 108 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 109 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 110 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 111 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 112 #define RTE_SPI0_PIN_INIT DSPI0_InitPins 113 #define RTE_SPI0_PIN_DEINIT DSPI0_DeinitPins 114 #define RTE_SPI0_DMA_TX_CH 0 115 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 116 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 117 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 118 #define RTE_SPI0_DMA_RX_CH 1 119 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 120 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 121 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 122 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 123 #define RTE_SPI0_DMA_LINK_CH 2 124 125 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 126 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 127 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 128 #define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 129 #define RTE_SPI1_PIN_INIT DSPI1_InitPins 130 #define RTE_SPI1_PIN_DEINIT DSPI1_DeinitPins 131 #define RTE_SPI1_DMA_TX_CH 3 132 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 133 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 134 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 135 #define RTE_SPI1_DMA_RX_CH 4 136 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 137 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 138 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 139 #define RTE_SPI1_DMA_LINK_DMA_BASE DMA0 140 #define RTE_SPI1_DMA_LINK_CH 5 141 142 #endif /* _RTE_DEVICE_H */ 143
