1 /*
2 ** ###################################################################
3 ** Processors: MKV30F128VFM10
4 ** MKV30F128VLF10
5 ** MKV30F128VLH10
6 ** MKV30F64VFM10
7 ** MKV30F64VLF10
8 ** MKV30F64VLH10
9 **
10 ** Compilers: Freescale C/C++ for Embedded ARM
11 ** GNU C Compiler
12 ** IAR ANSI C/C++ Compiler for ARM
13 ** Keil ARM C/C++ Compiler
14 ** MCUXpresso Compiler
15 **
16 ** Reference manual: KV30P64M100SFARM, Rev. 0, February 14, 2014
17 ** Version: rev. 0.5, 2015-02-19
18 ** Build: b181105
19 **
20 ** Abstract:
21 ** Provides a system configuration function and a global variable that
22 ** contains the system frequency. It configures the device and initializes
23 ** the oscillator (PLL) that is part of the microcontroller device.
24 **
25 ** Copyright 2016 Freescale Semiconductor, Inc.
26 ** Copyright 2016-2018 NXP
27 ** All rights reserved.
28 **
29 ** SPDX-License-Identifier: BSD-3-Clause
30 **
31 ** http: www.nxp.com
32 ** mail: support@nxp.com
33 **
34 ** Revisions:
35 ** - rev. 0.1 (2014-02-24)
36 ** Initial version
37 ** - rev. 0.2 (2014-07-15)
38 ** Module access macro module_BASES replaced by module_BASE_PTRS.
39 ** Update of system and startup files.
40 ** - rev. 0.3 (2014-08-28)
41 ** Update of system files - default clock configuration changed.
42 ** Update of startup files - possibility to override DefaultISR added.
43 ** - rev. 0.4 (2014-10-14)
44 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
45 ** - rev. 0.5 (2015-02-19)
46 ** Renamed interrupt vector LLW to LLWU.
47 **
48 ** ###################################################################
49 */
50
51 /*!
52 * @file MKV30F12810
53 * @version 0.5
54 * @date 2015-02-19
55 * @brief Device specific configuration file for MKV30F12810 (implementation
56 * file)
57 *
58 * Provides a system configuration function and a global variable that contains
59 * the system frequency. It configures the device and initializes the oscillator
60 * (PLL) that is part of the microcontroller device.
61 */
62
63 #include <stdint.h>
64 #include "fsl_device_registers.h"
65
66
67
68 /* ----------------------------------------------------------------------------
69 -- Core clock
70 ---------------------------------------------------------------------------- */
71
72 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
73
74 /* ----------------------------------------------------------------------------
75 -- SystemInit()
76 ---------------------------------------------------------------------------- */
77
SystemInit(void)78 void SystemInit (void) {
79 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
80 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
81 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
82
83 #if (DISABLE_WDOG)
84 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
85 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
86 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
87 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
88 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
89 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
90 WDOG_STCTRLH_WAITEN_MASK |
91 WDOG_STCTRLH_STOPEN_MASK |
92 WDOG_STCTRLH_ALLOWUPDATE_MASK |
93 WDOG_STCTRLH_CLKSRC_MASK |
94 0x0100U;
95 #endif /* (DISABLE_WDOG) */
96
97 SystemInitHook();
98 }
99
100 /* ----------------------------------------------------------------------------
101 -- SystemCoreClockUpdate()
102 ---------------------------------------------------------------------------- */
103
SystemCoreClockUpdate(void)104 void SystemCoreClockUpdate (void) {
105
106 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
107 uint16_t Divider;
108 uint8_t tmpC7 = 0;
109
110 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
111 /* FLL is selected */
112 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
113 /* External reference clock is selected */
114 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
115 case 0x00U:
116 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
117 break;
118 case 0x02U:
119 default:
120 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
121 break;
122 }
123 tmpC7 = MCG->C7;
124 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
125 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
126 case 0x38U:
127 Divider = 1536U;
128 break;
129 case 0x30U:
130 Divider = 1280U;
131 break;
132 default:
133 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
134 break;
135 }
136 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
137 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
138 }
139 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
140 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
141 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
142 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
143 /* Select correct multiplier to calculate the MCG output clock */
144 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
145 case 0x00U:
146 MCGOUTClock *= 640U;
147 break;
148 case 0x20U:
149 MCGOUTClock *= 1280U;
150 break;
151 case 0x40U:
152 MCGOUTClock *= 1920U;
153 break;
154 case 0x60U:
155 MCGOUTClock *= 2560U;
156 break;
157 case 0x80U:
158 MCGOUTClock *= 732U;
159 break;
160 case 0xA0U:
161 MCGOUTClock *= 1464U;
162 break;
163 case 0xC0U:
164 MCGOUTClock *= 2197U;
165 break;
166 case 0xE0U:
167 MCGOUTClock *= 2929U;
168 break;
169 default:
170 MCGOUTClock *= 640U;
171 break;
172 }
173 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
174 /* Internal reference clock is selected */
175 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
176 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
177 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
178 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
179 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
180 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
181 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
182 /* External reference clock is selected */
183 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
184 case 0x00U:
185 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
186 break;
187 case 0x02U:
188 default:
189 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
190 break;
191 }
192 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
193 /* Reserved value */
194 return;
195 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
196 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
197 }
198
199 /* ----------------------------------------------------------------------------
200 -- SystemInitHook()
201 ---------------------------------------------------------------------------- */
202
SystemInitHook(void)203 __attribute__ ((weak)) void SystemInitHook (void) {
204 /* Void implementation of the weak function. */
205 }
206
