1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, UART0 - UART1. */ 14 /* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART 15 * instance. */ 16 #define RTE_USART0 0 17 #define RTE_USART0_DMA_EN 0 18 #define RTE_USART1 0 19 #define RTE_USART1_DMA_EN 0 20 21 /* UART configuration. */ 22 #define USART_RX_BUFFER_LEN 64 23 #define USART0_RX_BUFFER_ENABLE 0 24 #define USART1_RX_BUFFER_ENABLE 0 25 26 #define RTE_USART0_PIN_INIT UART0_InitPins 27 #define RTE_USART0_PIN_DEINIT UART0_DeinitPins 28 #define RTE_USART0_DMA_TX_CH 0 29 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 30 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 31 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 32 #define RTE_USART0_DMA_RX_CH 1 33 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 34 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 35 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 36 37 #define RTE_USART1_PIN_INIT UART1_InitPins 38 #define RTE_USART1_PIN_DEINIT UART1_DeinitPins 39 #define RTE_USART1_DMA_TX_CH 0 40 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 41 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 42 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 43 #define RTE_USART1_DMA_RX_CH 1 44 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 45 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 46 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 47 48 /* I2C Select, I2C0. */ 49 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 50 */ 51 #define RTE_I2C0 0 52 #define RTE_I2C0_DMA_EN 0 53 54 /*I2C configuration*/ 55 #define RTE_I2C0_Master_DMA_BASE DMA0 56 #define RTE_I2C0_Master_DMA_CH 0 57 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 58 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 59 60 /* SPI Select, DSPI0.*/ 61 /* User needs to provide the implementation of DSPIX_GetFreq/DSPIX_InitPins/DSPIX_DeinitPins for the enabled DSPI 62 * instance. */ 63 #define RTE_SPI0 0 64 #define RTE_SPI0_DMA_EN 0 65 66 /* SPI configuration. */ 67 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 68 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 69 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 70 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 71 #define RTE_SPI0_PIN_INIT DSPI0_InitPins 72 #define RTE_SPI0_PIN_DEINIT DSPI0_DeinitPins 73 #define RTE_SPI0_DMA_TX_CH 0 74 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 75 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 76 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 77 #define RTE_SPI0_DMA_RX_CH 1 78 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 79 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 80 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 81 82 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 83 #define RTE_SPI0_DMA_LINK_CH 2 84 85 #endif /* _RTE_DEVICE_H */ 86
