1 /*
2 ** ###################################################################
3 **     Processors:          MKV10Z16VFM7
4 **                          MKV10Z16VLC7
5 **                          MKV10Z16VLF7
6 **                          MKV10Z32VFM7
7 **                          MKV10Z32VLC7
8 **                          MKV10Z32VLF7
9 **
10 **     Compilers:           Freescale C/C++ for Embedded ARM
11 **                          GNU C Compiler
12 **                          IAR ANSI C/C++ Compiler for ARM
13 **                          Keil ARM C/C++ Compiler
14 **                          MCUXpresso Compiler
15 **
16 **     Reference manual:    KV10P48M75RM Rev.6, June 2014
17 **     Version:             rev. 1.2, 2014-08-28
18 **     Build:               b181105
19 **
20 **     Abstract:
21 **         Provides a system configuration function and a global variable that
22 **         contains the system frequency. It configures the device and initializes
23 **         the oscillator (PLL) that is part of the microcontroller device.
24 **
25 **     Copyright 2016 Freescale Semiconductor, Inc.
26 **     Copyright 2016-2018 NXP
27 **     All rights reserved.
28 **
29 **     SPDX-License-Identifier: BSD-3-Clause
30 **
31 **     http:                 www.nxp.com
32 **     mail:                 support@nxp.com
33 **
34 **     Revisions:
35 **     - rev. 1.0 (2013-05-09)
36 **         Initial version.
37 **     - rev. 1.1 (2014-02-20)
38 **         ADC module - removed PGA registers
39 **         UART0 module - removed CEA709.1 registers
40 **     - rev. 1.2 (2014-08-28)
41 **         Update of system files - default clock configuration changed.
42 **         Update of startup files - possibility to override DefaultISR added.
43 **
44 ** ###################################################################
45 */
46 
47 /*!
48  * @file MKV10Z7
49  * @version 1.2
50  * @date 2014-08-28
51  * @brief Device specific configuration file for MKV10Z7 (implementation file)
52  *
53  * Provides a system configuration function and a global variable that contains
54  * the system frequency. It configures the device and initializes the oscillator
55  * (PLL) that is part of the microcontroller device.
56  */
57 
58 #include <stdint.h>
59 #include "fsl_device_registers.h"
60 
61 
62 
63 /* ----------------------------------------------------------------------------
64    -- Core clock
65    ---------------------------------------------------------------------------- */
66 
67 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
68 
69 /* ----------------------------------------------------------------------------
70    -- SystemInit()
71    ---------------------------------------------------------------------------- */
72 
SystemInit(void)73 void SystemInit (void) {
74 
75 #if (DISABLE_WDOG)
76   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
77   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
78   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
79   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
80   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
81   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
82                  WDOG_STCTRLH_WAITEN_MASK |
83                  WDOG_STCTRLH_STOPEN_MASK |
84                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
85                  WDOG_STCTRLH_CLKSRC_MASK |
86                  0x0100U;
87 #endif /* (DISABLE_WDOG) */
88 
89   SystemInitHook();
90 }
91 
92 /* ----------------------------------------------------------------------------
93    -- SystemCoreClockUpdate()
94    ---------------------------------------------------------------------------- */
95 
SystemCoreClockUpdate(void)96 void SystemCoreClockUpdate (void) {
97 
98   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
99   uint16_t Divider;
100 
101   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
102     /* FLL is selected */
103     if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
104       /* External reference clock is selected */
105       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
106       if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) {
107         switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
108         case 0x38U:
109           Divider = 1536U;
110           break;
111         case 0x30U:
112           Divider = 1280U;
113           break;
114         default:
115           Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
116           break;
117         }
118       } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
119         Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
120       }
121       MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
122     } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
123       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
124     } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
125     /* Select correct multiplier to calculate the MCG output clock  */
126     switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
127       case 0x00U:
128         MCGOUTClock *= 640U;
129         break;
130       case 0x20U:
131         MCGOUTClock *= 1280U;
132         break;
133       case 0x40U:
134         MCGOUTClock *= 1920U;
135         break;
136       case 0x60U:
137         MCGOUTClock *= 2560U;
138         break;
139       case 0x80U:
140         MCGOUTClock *= 732U;
141         break;
142       case 0xA0U:
143         MCGOUTClock *= 1464U;
144         break;
145       case 0xC0U:
146         MCGOUTClock *= 2197U;
147         break;
148       case 0xE0U:
149         MCGOUTClock *= 2929U;
150         break;
151       default:
152         MCGOUTClock *= 640U;
153         break;
154     }
155   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
156     /* Internal reference clock is selected */
157     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
158       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
159     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
160       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
161       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
162     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
163   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
164     /* External reference clock is selected */
165     MCGOUTClock = CPU_XTAL_CLK_HZ;     /* System oscillator drives MCG clock */
166   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
167     /* Reserved value */
168     return;
169   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
170   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
171 
172 }
173 
174 /* ----------------------------------------------------------------------------
175    -- SystemInitHook()
176    ---------------------------------------------------------------------------- */
177 
SystemInitHook(void)178 __attribute__ ((weak)) void SystemInitHook (void) {
179   /* Void implementation of the weak function. */
180 }
181