1 /* 2 ** ################################################################### 3 ** Version: rev. 1.4, 2015-05-25 4 ** Build: b201125 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2020 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2014-10-17) 20 ** Initial version. 21 ** - rev. 1.1 (2015-01-21) 22 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 23 ** - rev. 1.2 (2015-01-27) 24 ** Update according to reference manual rev. 1, RC. 25 ** - rev. 1.3 (2015-03-06) 26 ** Update according to reference manual rev. 1. 27 ** - rev. 1.4 (2015-05-25) 28 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 29 ** 30 ** ################################################################### 31 */ 32 33 #ifndef _MKM34Z7_FEATURES_H_ 34 #define _MKM34Z7_FEATURES_H_ 35 36 /* SOC module features */ 37 38 /* @brief ADC16 availability on the SoC. */ 39 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 40 /* @brief AFE availability on the SoC. */ 41 #define FSL_FEATURE_SOC_AFE_COUNT (1) 42 /* @brief AIPS availability on the SoC. */ 43 #define FSL_FEATURE_SOC_AIPS_COUNT (1) 44 /* @brief MMCAU availability on the SoC. */ 45 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 46 /* @brief CMP availability on the SoC. */ 47 #define FSL_FEATURE_SOC_CMP_COUNT (3) 48 /* @brief CRC availability on the SoC. */ 49 #define FSL_FEATURE_SOC_CRC_COUNT (1) 50 /* @brief DMA availability on the SoC. */ 51 #define FSL_FEATURE_SOC_DMA_COUNT (1) 52 /* @brief DMAMUX availability on the SoC. */ 53 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 54 /* @brief EWM availability on the SoC. */ 55 #define FSL_FEATURE_SOC_EWM_COUNT (1) 56 /* @brief FGPIO availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FGPIO_COUNT (13) 58 /* @brief FTFA availability on the SoC. */ 59 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 60 /* @brief GPIO availability on the SoC. */ 61 #define FSL_FEATURE_SOC_GPIO_COUNT (13) 62 /* @brief I2C availability on the SoC. */ 63 #define FSL_FEATURE_SOC_I2C_COUNT (2) 64 /* @brief SLCD availability on the SoC. */ 65 #define FSL_FEATURE_SOC_SLCD_COUNT (1) 66 /* @brief LLWU availability on the SoC. */ 67 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 68 /* @brief LPTMR availability on the SoC. */ 69 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 70 /* @brief LPUART availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LPUART_COUNT (1) 72 /* @brief MCG availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MCG_COUNT (1) 74 /* @brief MCM availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MCM_COUNT (1) 76 /* @brief MMAU availability on the SoC. */ 77 #define FSL_FEATURE_SOC_MMAU_COUNT (1) 78 /* @brief SYSMPU availability on the SoC. */ 79 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 80 /* @brief MTB availability on the SoC. */ 81 #define FSL_FEATURE_SOC_MTB_COUNT (1) 82 /* @brief MTBDWT availability on the SoC. */ 83 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 84 /* @brief OSC availability on the SoC. */ 85 #define FSL_FEATURE_SOC_OSC_COUNT (1) 86 /* @brief PDB availability on the SoC. */ 87 #define FSL_FEATURE_SOC_PDB_COUNT (1) 88 /* @brief PIT availability on the SoC. */ 89 #define FSL_FEATURE_SOC_PIT_COUNT (2) 90 /* @brief PMC availability on the SoC. */ 91 #define FSL_FEATURE_SOC_PMC_COUNT (1) 92 /* @brief PORT availability on the SoC. */ 93 #define FSL_FEATURE_SOC_PORT_COUNT (13) 94 /* @brief RCM availability on the SoC. */ 95 #define FSL_FEATURE_SOC_RCM_COUNT (1) 96 /* @brief RNG availability on the SoC. */ 97 #define FSL_FEATURE_SOC_RNG_COUNT (1) 98 /* @brief ROM availability on the SoC. */ 99 #define FSL_FEATURE_SOC_ROM_COUNT (1) 100 /* @brief RTC availability on the SoC. */ 101 #define FSL_FEATURE_SOC_RTC_COUNT (1) 102 /* @brief SIM availability on the SoC. */ 103 #define FSL_FEATURE_SOC_SIM_COUNT (1) 104 /* @brief SMC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_SMC_COUNT (1) 106 /* @brief SPI availability on the SoC. */ 107 #define FSL_FEATURE_SOC_SPI_COUNT (2) 108 /* @brief TMR availability on the SoC. */ 109 #define FSL_FEATURE_SOC_TMR_COUNT (4) 110 /* @brief UART availability on the SoC. */ 111 #define FSL_FEATURE_SOC_UART_COUNT (4) 112 /* @brief VREF availability on the SoC. */ 113 #define FSL_FEATURE_SOC_VREF_COUNT (1) 114 /* @brief WDOG availability on the SoC. */ 115 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 116 /* @brief XBAR availability on the SoC. */ 117 #define FSL_FEATURE_SOC_XBAR_COUNT (1) 118 119 /* ADC16 module features */ 120 121 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 122 #define FSL_FEATURE_ADC16_HAS_PGA (0) 123 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 124 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 125 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 126 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 127 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 128 #define FSL_FEATURE_ADC16_HAS_DMA (1) 129 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 130 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (0) 131 /* @brief Has FIFO (bit SC4[AFDEP]). */ 132 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 133 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 134 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 135 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 136 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 137 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 138 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 139 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 140 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 141 /* @brief Has HW averaging (bit SC3[AVGE]). */ 142 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 143 /* @brief Has offset correction (register OFS). */ 144 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 145 /* @brief Maximum ADC resolution. */ 146 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 147 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 148 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (4) 149 /* @brief Has reference from PMC Bandgap voltage. */ 150 #define FSL_FEATURE_ADC16_HAS_VREF_BANDGAP (1) 151 152 /* AFE module features */ 153 154 /* @brief AFE channel counter. */ 155 #define FSL_FEATURE_AFE_CHANNEL_NUMBER (4) 156 /* @brief AFE channel counter with PGA feature. */ 157 #define FSL_FEATURE_AFE_CHANNEL_NUMBER_WITH_PGA (4) 158 /* @brief AFE has four channels. */ 159 #define FSL_FEATURE_AFE_HAS_FOUR_CHANNELS (1) 160 161 /* CMP module features */ 162 163 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 164 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 165 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 166 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 167 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 168 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 169 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 170 #define FSL_FEATURE_CMP_HAS_DMA (1) 171 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 172 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 173 /* @brief Has DAC Test function in CMP (register DACTEST). */ 174 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 175 176 /* CRC module features */ 177 178 /* @brief Has data register with name CRC */ 179 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 180 181 /* DMA module features */ 182 183 /* @brief Number of DMA channels. */ 184 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) 185 /* @brief Total number of DMA channels on all modules. */ 186 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (4) 187 188 /* DMAMUX module features */ 189 190 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 191 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 192 /* @brief Total number of DMA channels on all modules. */ 193 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4) 194 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 195 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 196 /* @brief Register CHCFGn width. */ 197 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 198 199 /* EWM module features */ 200 201 /* @brief Has clock select (register CLKCTRL). */ 202 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 203 /* @brief Has clock prescaler (register CLKPRESCALER). */ 204 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 205 206 /* FGPIO module features */ 207 208 /* @brief Has FGPIO attribute checker register (GACR). */ 209 #define FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER (1) 210 211 /* FLASH module features */ 212 213 /* @brief Is of type FTFA. */ 214 #define FSL_FEATURE_FLASH_IS_FTFA (1) 215 /* @brief Is of type FTFE. */ 216 #define FSL_FEATURE_FLASH_IS_FTFE (0) 217 /* @brief Is of type FTFL. */ 218 #define FSL_FEATURE_FLASH_IS_FTFL (0) 219 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). 220 */ 221 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 222 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 223 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 224 /* @brief Has EEPROM region protection (register FEPROT). */ 225 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 226 /* @brief Has data flash region protection (register FDPROT). */ 227 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 228 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 229 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 230 /* @brief Has flash cache control in FMC module. */ 231 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 232 /* @brief Has flash cache control in MCM module. */ 233 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 234 /* @brief Has flash cache control in MSCM module. */ 235 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 236 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 237 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 238 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 239 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 240 /* @brief P-Flash start address. */ 241 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 242 /* @brief P-Flash block count. */ 243 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 244 /* @brief P-Flash block size. */ 245 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 246 /* @brief P-Flash sector size. */ 247 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 248 /* @brief P-Flash write unit size. */ 249 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 250 /* @brief P-Flash data path width. */ 251 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 252 /* @brief P-Flash block swap feature. */ 253 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 254 /* @brief P-Flash protection region count. */ 255 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 256 /* @brief Has FlexNVM memory. */ 257 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 258 /* @brief Has FlexNVM alias. */ 259 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 260 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 261 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 262 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 263 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 264 /* @brief FlexNVM block count. */ 265 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 266 /* @brief FlexNVM block size. */ 267 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 268 /* @brief FlexNVM sector size. */ 269 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 270 /* @brief FlexNVM write unit size. */ 271 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 272 /* @brief FlexNVM data path width. */ 273 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 274 /* @brief Has FlexRAM memory. */ 275 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 276 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 277 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 278 /* @brief FlexRAM size. */ 279 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 280 /* @brief Has 0x00 Read 1s Block command. */ 281 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 282 /* @brief Has 0x01 Read 1s Section command. */ 283 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 284 /* @brief Has 0x02 Program Check command. */ 285 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 286 /* @brief Has 0x03 Read Resource command. */ 287 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 288 /* @brief Has 0x06 Program Longword command. */ 289 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 290 /* @brief Has 0x07 Program Phrase command. */ 291 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 292 /* @brief Has 0x08 Erase Flash Block command. */ 293 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 294 /* @brief Has 0x09 Erase Flash Sector command. */ 295 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 296 /* @brief Has 0x0B Program Section command. */ 297 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 298 /* @brief Has 0x40 Read 1s All Blocks command. */ 299 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 300 /* @brief Has 0x41 Read Once command. */ 301 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 302 /* @brief Has 0x43 Program Once command. */ 303 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 304 /* @brief Has 0x44 Erase All Blocks command. */ 305 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 306 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 307 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 308 /* @brief Has 0x46 Swap Control command. */ 309 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 310 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 311 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 312 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 313 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 314 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 315 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 316 /* @brief Has 0x80 Program Partition command. */ 317 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 318 /* @brief Has 0x81 Set FlexRAM Function command. */ 319 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 320 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 321 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 322 /* @brief P-Flash Erase sector command address alignment. */ 323 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 324 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 325 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 326 /* @brief P-Flash Read resource command address alignment. */ 327 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 328 /* @brief P-Flash Program check command address alignment. */ 329 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 330 /* @brief P-Flash Program check command address alignment. */ 331 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 332 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 333 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 334 /* @brief FlexNVM Erase sector command address alignment. */ 335 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 336 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 337 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 338 /* @brief FlexNVM Read resource command address alignment. */ 339 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 340 /* @brief FlexNVM Program check command address alignment. */ 341 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 342 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 343 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 344 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 345 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 346 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 347 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 348 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 349 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 350 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 351 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 352 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 353 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 354 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 355 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 356 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 357 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 358 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 359 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 360 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 361 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 362 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 363 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 364 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 366 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 368 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 370 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 372 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 374 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 376 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 378 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 380 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 382 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 384 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 386 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 388 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 390 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 392 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 394 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 396 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 398 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 400 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 402 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 404 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 406 407 /* GPIO module features */ 408 409 /* @brief Has GPIO attribute checker register (GACR). */ 410 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (1) 411 /* @brief GPIO registers width */ 412 #define FSL_FEATURE_GPIO_REGISTERS_WIDTH (8) 413 414 /* I2C module features */ 415 416 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 417 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 418 /* @brief Maximum supported baud rate in kilobit per second. */ 419 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 420 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a 421 * non-zero value). */ 422 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 423 /* @brief Has DMA support (register bit C1[DMAEN]). */ 424 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 425 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 426 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 427 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 428 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 429 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 430 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 431 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 432 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 433 /* @brief Has control of the drive capability of the I2C pins. */ 434 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 435 /* @brief Has double buffering support (register S2). */ 436 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) 437 /* @brief Has double buffer enable. */ 438 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 439 /* @brief I2C0 and I2C1 has shared interrupt vector. */ 440 #define FSL_FEATURE_I2C_HAS_SHARED_IRQ0_IRQ1 (1) 441 442 /* SLCD module features */ 443 444 /* @brief Has Multi Alternate Clock Source (register bit GCR[ATLSOURCE]). */ 445 #define FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE (0) 446 /* @brief Has fast frame rate (register bit GCR[FFR]). */ 447 #define FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE (0) 448 /* @brief Has frame frequency interrupt (register bit GCR[LCDIEN]). */ 449 #define FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT (0) 450 /* @brief Has high reference select (register bit GCR[HREFSEL]). */ 451 #define FSL_FEATURE_SLCD_HAS_HIGH_REFERENCE_SELECT (0) 452 /* @brief Has pad safe (register bit GCR[PADSAFE]). */ 453 #define FSL_FEATURE_SLCD_HAS_PAD_SAFE (0) 454 /* @brief Has lcd wait (register bit GCR[LCDWAIT]). */ 455 #define FSL_FEATURE_SLCD_HAS_LCD_WAIT (0) 456 /* @brief Has lcd doze enable (register bit GCR[LCDDOZE]). */ 457 #define FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE (1) 458 /* @brief Total pin number on LCD. */ 459 #define FSL_FEATURE_SLCD_HAS_PIN_NUM (64) 460 /* @brief Total phase number on SLCD. */ 461 #define FSL_FEATURE_SLCD_HAS_PHASE_NUM (8) 462 463 /* LLWU module features */ 464 465 #if defined(CPU_MKM34Z256VLL7) 466 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 467 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (23) 468 /* @brief Has pins 8-15 connected to LLWU device. */ 469 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 470 /* @brief Maximum number of internal modules connected to LLWU device. */ 471 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (6) 472 /* @brief Number of digital filters. */ 473 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 474 /* @brief Has MF register. */ 475 #define FSL_FEATURE_LLWU_HAS_MF (1) 476 /* @brief Has PF register. */ 477 #define FSL_FEATURE_LLWU_HAS_PF (1) 478 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register 479 * LLWU_RST). */ 480 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 481 /* @brief Has no internal module wakeup flag register. */ 482 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 483 /* @brief Has external pin 0 connected to LLWU device. */ 484 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 485 /* @brief Index of port of external pin. */ 486 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOG_IDX) 487 /* @brief Number of external pin port on specified port. */ 488 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (6) 489 /* @brief Has external pin 1 connected to LLWU device. */ 490 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 491 /* @brief Index of port of external pin. */ 492 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOG_IDX) 493 /* @brief Number of external pin port on specified port. */ 494 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 495 /* @brief Has external pin 2 connected to LLWU device. */ 496 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 497 /* @brief Index of port of external pin. */ 498 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOG_IDX) 499 /* @brief Number of external pin port on specified port. */ 500 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (1) 501 /* @brief Has external pin 3 connected to LLWU device. */ 502 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 503 /* @brief Index of port of external pin. */ 504 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOF_IDX) 505 /* @brief Number of external pin port on specified port. */ 506 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (6) 507 /* @brief Has external pin 4 connected to LLWU device. */ 508 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 509 /* @brief Index of port of external pin. */ 510 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOF_IDX) 511 /* @brief Number of external pin port on specified port. */ 512 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 513 /* @brief Has external pin 5 connected to LLWU device. */ 514 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 515 /* @brief Index of port of external pin. */ 516 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOE_IDX) 517 /* @brief Number of external pin port on specified port. */ 518 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (6) 519 /* @brief Has external pin 6 connected to LLWU device. */ 520 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 521 /* @brief Index of port of external pin. */ 522 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOE_IDX) 523 /* @brief Number of external pin port on specified port. */ 524 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (5) 525 /* @brief Has external pin 7 connected to LLWU device. */ 526 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 527 /* @brief Index of port of external pin. */ 528 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOD_IDX) 529 /* @brief Number of external pin port on specified port. */ 530 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (7) 531 /* @brief Has external pin 8 connected to LLWU device. */ 532 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 533 /* @brief Index of port of external pin. */ 534 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOD_IDX) 535 /* @brief Number of external pin port on specified port. */ 536 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (6) 537 /* @brief Has external pin 9 connected to LLWU device. */ 538 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 539 /* @brief Index of port of external pin. */ 540 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOD_IDX) 541 /* @brief Number of external pin port on specified port. */ 542 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (4) 543 /* @brief Has external pin 10 connected to LLWU device. */ 544 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 545 /* @brief Index of port of external pin. */ 546 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOD_IDX) 547 /* @brief Number of external pin port on specified port. */ 548 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) 549 /* @brief Has external pin 11 connected to LLWU device. */ 550 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 551 /* @brief Index of port of external pin. */ 552 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOD_IDX) 553 /* @brief Number of external pin port on specified port. */ 554 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 555 /* @brief Has external pin 12 connected to LLWU device. */ 556 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 557 /* @brief Index of port of external pin. */ 558 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) 559 /* @brief Number of external pin port on specified port. */ 560 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (5) 561 /* @brief Has external pin 13 connected to LLWU device. */ 562 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 563 /* @brief Index of port of external pin. */ 564 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) 565 /* @brief Number of external pin port on specified port. */ 566 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (3) 567 /* @brief Has external pin 14 connected to LLWU device. */ 568 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 569 /* @brief Index of port of external pin. */ 570 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOA_IDX) 571 /* @brief Number of external pin port on specified port. */ 572 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) 573 /* @brief Has external pin 15 connected to LLWU device. */ 574 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 575 /* @brief Index of port of external pin. */ 576 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOA_IDX) 577 /* @brief Number of external pin port on specified port. */ 578 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (4) 579 /* @brief Has external pin 16 connected to LLWU device. */ 580 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 581 /* @brief Index of port of external pin. */ 582 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOA_IDX) 583 /* @brief Number of external pin port on specified port. */ 584 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 585 /* @brief Has external pin 17 connected to LLWU device. */ 586 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 587 /* @brief Index of port of external pin. */ 588 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOB_IDX) 589 /* @brief Number of external pin port on specified port. */ 590 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (1) 591 /* @brief Has external pin 18 connected to LLWU device. */ 592 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 593 /* @brief Index of port of external pin. */ 594 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 595 /* @brief Number of external pin port on specified port. */ 596 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 597 /* @brief Has external pin 19 connected to LLWU device. */ 598 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 599 /* @brief Index of port of external pin. */ 600 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 601 /* @brief Number of external pin port on specified port. */ 602 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 603 /* @brief Has external pin 20 connected to LLWU device. */ 604 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 605 /* @brief Index of port of external pin. */ 606 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOF_IDX) 607 /* @brief Number of external pin port on specified port. */ 608 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (3) 609 /* @brief Has external pin 21 connected to LLWU device. */ 610 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 611 /* @brief Index of port of external pin. */ 612 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOI_IDX) 613 /* @brief Number of external pin port on specified port. */ 614 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 615 /* @brief Has external pin 22 connected to LLWU device. */ 616 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 617 /* @brief Index of port of external pin. */ 618 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOI_IDX) 619 /* @brief Number of external pin port on specified port. */ 620 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (2) 621 /* @brief Has external pin 23 connected to LLWU device. */ 622 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 623 /* @brief Index of port of external pin. */ 624 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 625 /* @brief Number of external pin port on specified port. */ 626 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 627 /* @brief Has external pin 24 connected to LLWU device. */ 628 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 629 /* @brief Index of port of external pin. */ 630 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 631 /* @brief Number of external pin port on specified port. */ 632 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 633 /* @brief Has external pin 25 connected to LLWU device. */ 634 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 635 /* @brief Index of port of external pin. */ 636 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 637 /* @brief Number of external pin port on specified port. */ 638 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 639 /* @brief Has external pin 26 connected to LLWU device. */ 640 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 641 /* @brief Index of port of external pin. */ 642 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 643 /* @brief Number of external pin port on specified port. */ 644 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 645 /* @brief Has external pin 27 connected to LLWU device. */ 646 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 647 /* @brief Index of port of external pin. */ 648 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 649 /* @brief Number of external pin port on specified port. */ 650 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 651 /* @brief Has external pin 28 connected to LLWU device. */ 652 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 653 /* @brief Index of port of external pin. */ 654 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 655 /* @brief Number of external pin port on specified port. */ 656 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 657 /* @brief Has external pin 29 connected to LLWU device. */ 658 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 659 /* @brief Index of port of external pin. */ 660 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 661 /* @brief Number of external pin port on specified port. */ 662 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 663 /* @brief Has external pin 30 connected to LLWU device. */ 664 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 665 /* @brief Index of port of external pin. */ 666 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 667 /* @brief Number of external pin port on specified port. */ 668 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 669 /* @brief Has external pin 31 connected to LLWU device. */ 670 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 671 /* @brief Index of port of external pin. */ 672 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 673 /* @brief Number of external pin port on specified port. */ 674 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 675 /* @brief Has internal module 0 connected to LLWU device. */ 676 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 677 /* @brief Has internal module 1 connected to LLWU device. */ 678 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 679 /* @brief Has internal module 2 connected to LLWU device. */ 680 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 681 /* @brief Has internal module 3 connected to LLWU device. */ 682 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 683 /* @brief Has internal module 4 connected to LLWU device. */ 684 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 685 /* @brief Has internal module 5 connected to LLWU device. */ 686 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 687 /* @brief Has internal module 6 connected to LLWU device. */ 688 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 689 /* @brief Has internal module 7 connected to LLWU device. */ 690 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 691 /* @brief Has Version ID Register (LLWU_VERID). */ 692 #define FSL_FEATURE_LLWU_HAS_VERID (0) 693 /* @brief Has Parameter Register (LLWU_PARAM). */ 694 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 695 /* @brief Width of registers of the LLWU. */ 696 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 697 /* @brief Has DMA Enable register (LLWU_DE). */ 698 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 699 #elif defined(CPU_MKM34Z256VLQ7) 700 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 701 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (24) 702 /* @brief Has pins 8-15 connected to LLWU device. */ 703 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 704 /* @brief Maximum number of internal modules connected to LLWU device. */ 705 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (6) 706 /* @brief Number of digital filters. */ 707 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 708 /* @brief Has MF register. */ 709 #define FSL_FEATURE_LLWU_HAS_MF (1) 710 /* @brief Has PF register. */ 711 #define FSL_FEATURE_LLWU_HAS_PF (1) 712 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register 713 * LLWU_RST). */ 714 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 715 /* @brief Has no internal module wakeup flag register. */ 716 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 717 /* @brief Has external pin 0 connected to LLWU device. */ 718 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 719 /* @brief Index of port of external pin. */ 720 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOG_IDX) 721 /* @brief Number of external pin port on specified port. */ 722 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (6) 723 /* @brief Has external pin 1 connected to LLWU device. */ 724 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 725 /* @brief Index of port of external pin. */ 726 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOG_IDX) 727 /* @brief Number of external pin port on specified port. */ 728 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 729 /* @brief Has external pin 2 connected to LLWU device. */ 730 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 731 /* @brief Index of port of external pin. */ 732 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOG_IDX) 733 /* @brief Number of external pin port on specified port. */ 734 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (1) 735 /* @brief Has external pin 3 connected to LLWU device. */ 736 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 737 /* @brief Index of port of external pin. */ 738 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOF_IDX) 739 /* @brief Number of external pin port on specified port. */ 740 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (6) 741 /* @brief Has external pin 4 connected to LLWU device. */ 742 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 743 /* @brief Index of port of external pin. */ 744 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOF_IDX) 745 /* @brief Number of external pin port on specified port. */ 746 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 747 /* @brief Has external pin 5 connected to LLWU device. */ 748 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 749 /* @brief Index of port of external pin. */ 750 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOE_IDX) 751 /* @brief Number of external pin port on specified port. */ 752 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (6) 753 /* @brief Has external pin 6 connected to LLWU device. */ 754 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 755 /* @brief Index of port of external pin. */ 756 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOE_IDX) 757 /* @brief Number of external pin port on specified port. */ 758 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (5) 759 /* @brief Has external pin 7 connected to LLWU device. */ 760 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 761 /* @brief Index of port of external pin. */ 762 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOD_IDX) 763 /* @brief Number of external pin port on specified port. */ 764 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (7) 765 /* @brief Has external pin 8 connected to LLWU device. */ 766 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 767 /* @brief Index of port of external pin. */ 768 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOD_IDX) 769 /* @brief Number of external pin port on specified port. */ 770 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (6) 771 /* @brief Has external pin 9 connected to LLWU device. */ 772 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 773 /* @brief Index of port of external pin. */ 774 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOD_IDX) 775 /* @brief Number of external pin port on specified port. */ 776 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (4) 777 /* @brief Has external pin 10 connected to LLWU device. */ 778 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 779 /* @brief Index of port of external pin. */ 780 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOD_IDX) 781 /* @brief Number of external pin port on specified port. */ 782 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) 783 /* @brief Has external pin 11 connected to LLWU device. */ 784 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 785 /* @brief Index of port of external pin. */ 786 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOD_IDX) 787 /* @brief Number of external pin port on specified port. */ 788 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 789 /* @brief Has external pin 12 connected to LLWU device. */ 790 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 791 /* @brief Index of port of external pin. */ 792 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) 793 /* @brief Number of external pin port on specified port. */ 794 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (5) 795 /* @brief Has external pin 13 connected to LLWU device. */ 796 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 797 /* @brief Index of port of external pin. */ 798 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) 799 /* @brief Number of external pin port on specified port. */ 800 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (3) 801 /* @brief Has external pin 14 connected to LLWU device. */ 802 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 803 /* @brief Index of port of external pin. */ 804 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOA_IDX) 805 /* @brief Number of external pin port on specified port. */ 806 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) 807 /* @brief Has external pin 15 connected to LLWU device. */ 808 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 809 /* @brief Index of port of external pin. */ 810 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOA_IDX) 811 /* @brief Number of external pin port on specified port. */ 812 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (4) 813 /* @brief Has external pin 16 connected to LLWU device. */ 814 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 815 /* @brief Index of port of external pin. */ 816 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOA_IDX) 817 /* @brief Number of external pin port on specified port. */ 818 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 819 /* @brief Has external pin 17 connected to LLWU device. */ 820 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 821 /* @brief Index of port of external pin. */ 822 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOB_IDX) 823 /* @brief Number of external pin port on specified port. */ 824 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (1) 825 /* @brief Has external pin 18 connected to LLWU device. */ 826 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 827 /* @brief Index of port of external pin. */ 828 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOJ_IDX) 829 /* @brief Number of external pin port on specified port. */ 830 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (6) 831 /* @brief Has external pin 19 connected to LLWU device. */ 832 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 833 /* @brief Index of port of external pin. */ 834 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOK_IDX) 835 /* @brief Number of external pin port on specified port. */ 836 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (3) 837 /* @brief Has external pin 20 connected to LLWU device. */ 838 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 839 /* @brief Index of port of external pin. */ 840 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOF_IDX) 841 /* @brief Number of external pin port on specified port. */ 842 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (3) 843 /* @brief Has external pin 21 connected to LLWU device. */ 844 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 845 /* @brief Index of port of external pin. */ 846 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOI_IDX) 847 /* @brief Number of external pin port on specified port. */ 848 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 849 /* @brief Has external pin 22 connected to LLWU device. */ 850 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 851 /* @brief Index of port of external pin. */ 852 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOI_IDX) 853 /* @brief Number of external pin port on specified port. */ 854 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (2) 855 /* @brief Has external pin 23 connected to LLWU device. */ 856 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 857 /* @brief Index of port of external pin. */ 858 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOL_IDX) 859 /* @brief Number of external pin port on specified port. */ 860 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (5) 861 /* @brief Has external pin 24 connected to LLWU device. */ 862 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 863 /* @brief Index of port of external pin. */ 864 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 865 /* @brief Number of external pin port on specified port. */ 866 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 867 /* @brief Has external pin 25 connected to LLWU device. */ 868 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 869 /* @brief Index of port of external pin. */ 870 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 871 /* @brief Number of external pin port on specified port. */ 872 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 873 /* @brief Has external pin 26 connected to LLWU device. */ 874 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 875 /* @brief Index of port of external pin. */ 876 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 877 /* @brief Number of external pin port on specified port. */ 878 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 879 /* @brief Has external pin 27 connected to LLWU device. */ 880 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 881 /* @brief Index of port of external pin. */ 882 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 883 /* @brief Number of external pin port on specified port. */ 884 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 885 /* @brief Has external pin 28 connected to LLWU device. */ 886 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 887 /* @brief Index of port of external pin. */ 888 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 889 /* @brief Number of external pin port on specified port. */ 890 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 891 /* @brief Has external pin 29 connected to LLWU device. */ 892 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 893 /* @brief Index of port of external pin. */ 894 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 895 /* @brief Number of external pin port on specified port. */ 896 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 897 /* @brief Has external pin 30 connected to LLWU device. */ 898 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 899 /* @brief Index of port of external pin. */ 900 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 901 /* @brief Number of external pin port on specified port. */ 902 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 903 /* @brief Has external pin 31 connected to LLWU device. */ 904 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 905 /* @brief Index of port of external pin. */ 906 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 907 /* @brief Number of external pin port on specified port. */ 908 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 909 /* @brief Has internal module 0 connected to LLWU device. */ 910 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 911 /* @brief Has internal module 1 connected to LLWU device. */ 912 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 913 /* @brief Has internal module 2 connected to LLWU device. */ 914 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 915 /* @brief Has internal module 3 connected to LLWU device. */ 916 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 917 /* @brief Has internal module 4 connected to LLWU device. */ 918 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 919 /* @brief Has internal module 5 connected to LLWU device. */ 920 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 921 /* @brief Has internal module 6 connected to LLWU device. */ 922 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 923 /* @brief Has internal module 7 connected to LLWU device. */ 924 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 925 /* @brief Has Version ID Register (LLWU_VERID). */ 926 #define FSL_FEATURE_LLWU_HAS_VERID (0) 927 /* @brief Has Parameter Register (LLWU_PARAM). */ 928 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 929 /* @brief Width of registers of the LLWU. */ 930 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 931 /* @brief Has DMA Enable register (LLWU_DE). */ 932 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 933 #endif /* defined(CPU_MKM34Z256VLL7) */ 934 935 /* LPTMR module features */ 936 937 /* @brief Has shared interrupt handler with another LPTMR module. */ 938 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 939 /* @brief Whether LPTMR counter is 32 bits width. */ 940 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 941 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 942 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 943 944 /* LPUART module features */ 945 946 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 947 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 948 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 949 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 950 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the 951 * registers are 32-bit wide). */ 952 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 953 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 954 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 955 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 956 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 957 /* @brief Has 32-bit register MODIR */ 958 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 959 /* @brief Hardware flow control (RTS, CTS) is supported. */ 960 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 961 /* @brief Infrared (modulation) is supported. */ 962 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 963 /* @brief 2 bits long stop bit is available. */ 964 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 965 /* @brief If 10-bit mode is supported. */ 966 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 967 /* @brief If 7-bit mode is supported. */ 968 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 969 /* @brief Baud rate fine adjustment is available. */ 970 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 971 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], 972 * BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 973 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 974 /* @brief Baud rate oversampling is available. */ 975 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 976 /* @brief Baud rate oversampling is available. */ 977 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 978 /* @brief Peripheral type. */ 979 #define FSL_FEATURE_LPUART_IS_SCI (1) 980 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 981 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 982 /* @brief Supports two match addresses to filter incoming frames. */ 983 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 984 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 985 * 32-bit wide). */ 986 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 987 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 988 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 989 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit 990 * wide). */ 991 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 992 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 993 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 994 /* @brief Has improved smart card (ISO7816 protocol) support. */ 995 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 996 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 997 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 998 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 999 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1000 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1001 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1002 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1003 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1004 /* @brief Has separate DMA RX and TX requests. */ 1005 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1006 /* @brief Has separate RX and TX interrupts. */ 1007 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1008 /* @brief Has LPAURT_PARAM. */ 1009 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 1010 /* @brief Has LPUART_VERID. */ 1011 #define FSL_FEATURE_LPUART_HAS_VERID (0) 1012 /* @brief Has LPUART_GLOBAL. */ 1013 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 1014 /* @brief Has LPUART_PINCFG. */ 1015 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 1016 1017 /* MCG module features */ 1018 1019 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1020 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) 1021 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1022 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) 1023 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1024 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) 1025 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1026 #define FSL_FEATURE_MCG_PLL_REF_MIN (0) 1027 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1028 #define FSL_FEATURE_MCG_PLL_REF_MAX (0) 1029 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1030 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1031 /* @brief FRDIV supports 1280. */ 1032 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1033 /* @brief FRDIV supports 1536. */ 1034 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1035 /* @brief MCGFFCLK divider. */ 1036 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1037 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1038 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1039 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are 1040 * present). */ 1041 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 1042 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1043 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1044 /* @brief Has 48MHz internal oscillator. */ 1045 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1046 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1047 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1048 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1049 #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) 1050 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1051 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1052 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1053 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1054 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1055 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1056 /* @brief TBD */ 1057 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1058 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], 1059 * S[LOLS0]). */ 1060 #define FSL_FEATURE_MCG_HAS_PLL (1) 1061 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1062 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) 1063 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1064 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) 1065 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1066 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 1067 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1068 #define FSL_FEATURE_MCG_HAS_FLL (1) 1069 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1070 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1071 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1072 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1073 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1074 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1075 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1076 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1077 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1078 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1079 /* @brief Has external clock monitor (register bit C6[CME]). */ 1080 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1081 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1082 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1083 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1084 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1085 /* @brief Has PEI mode or PBI mode. */ 1086 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (1) 1087 /* @brief Reset clock mode is BLPI. */ 1088 #define FSL_FEATURE_MCG_RESET_IS_BLPI (1) 1089 1090 /* interrupt module features */ 1091 1092 /* @brief Lowest interrupt request number. */ 1093 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1094 /* @brief Highest interrupt request number. */ 1095 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 1096 1097 /* OSC module features */ 1098 1099 /* @brief Has OSC1 external oscillator. */ 1100 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1101 /* @brief Has OSC0 external oscillator. */ 1102 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1103 /* @brief Has OSC external oscillator (without index). */ 1104 #define FSL_FEATURE_OSC_HAS_OSC (0) 1105 /* @brief Number of OSC external oscillators. */ 1106 #define FSL_FEATURE_OSC_OSC_COUNT (0) 1107 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1108 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 1109 1110 /* PDB module features */ 1111 1112 /* @brief Has DAC support. */ 1113 #define FSL_FEATURE_PDB_HAS_DAC (0) 1114 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1115 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1116 /* @brief PDB channel number). */ 1117 #define FSL_FEATURE_PDB_CHANNEL_COUNT (1) 1118 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1119 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (4) 1120 /* @brief DAC interval trigger number). */ 1121 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (0) 1122 /* @brief Pulse out number). */ 1123 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (1) 1124 1125 /* PIT module features */ 1126 1127 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1128 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 1129 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1130 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1131 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1132 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1133 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1134 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 1135 /* @brief Has timer enable control. */ 1136 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1137 1138 /* PMC module features */ 1139 1140 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1141 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1142 /* @brief Has Bandgap Buffer Enable. */ 1143 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1144 /* @brief Has Bandgap Buffer Drive Select. */ 1145 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1146 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1147 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1148 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1149 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1150 /* @brief Has LPO. */ 1151 #define FSL_FEATURE_PMC_HAS_LPO (0) 1152 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1153 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1154 /* @brief Has acknowledge isolation support. */ 1155 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1156 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1157 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1158 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1159 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1160 /* @brief Has PMC_HVDSC1. */ 1161 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1162 /* @brief Has PMC_PARAM. */ 1163 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1164 /* @brief Has PMC_VERID. */ 1165 #define FSL_FEATURE_PMC_HAS_VERID (0) 1166 1167 /* PORT module features */ 1168 1169 /* @brief Has control lock (register bit PCR[LK]). */ 1170 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1171 /* @brief Has open drain control (register bit PCR[ODE]). */ 1172 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1173 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1174 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1175 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1176 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1177 /* @brief Has pull resistor selection available. */ 1178 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1179 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1180 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1181 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1182 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1183 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1184 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (0) 1185 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1186 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0) 1187 /* @brief Has separate drive strength register (HDRVE). */ 1188 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1189 /* @brief Has glitch filter (register IOFLT). */ 1190 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1191 /* @brief Defines width of PCR[MUX] field. */ 1192 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1193 /* @brief Has dedicated interrupt vector. */ 1194 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1195 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1196 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1197 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1198 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1199 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1200 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1201 1202 /* RCM module features */ 1203 1204 /* @brief Has Loss-of-Lock Reset support. */ 1205 #define FSL_FEATURE_RCM_HAS_LOL (1) 1206 /* @brief Has Loss-of-Clock Reset support. */ 1207 #define FSL_FEATURE_RCM_HAS_LOC (1) 1208 /* @brief Has JTAG generated Reset support. */ 1209 #define FSL_FEATURE_RCM_HAS_JTAG (0) 1210 /* @brief Has EzPort generated Reset support. */ 1211 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1212 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1213 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1214 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1215 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1216 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1217 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1218 /* @brief Has Version ID Register (RCM_VERID). */ 1219 #define FSL_FEATURE_RCM_HAS_VERID (0) 1220 /* @brief Has Parameter Register (RCM_PARAM). */ 1221 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1222 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1223 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1224 /* @brief Width of registers of the RCM. */ 1225 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1226 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1227 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1228 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1229 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1230 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1231 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1232 1233 /* RTC module features */ 1234 1235 /* @brief Has Tamper Direction Register support. */ 1236 #define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) 1237 /* @brief Has Tamper Queue Status and Control Register support. */ 1238 #define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) 1239 /* @brief Whether RTC is IRTC. */ 1240 #define FSL_FEATURE_RTC_IS_IRTC (1) 1241 1242 /* SIM module features */ 1243 1244 /* @brief Has USB FS divider. */ 1245 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1246 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1247 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1248 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1249 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1250 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1251 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1252 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1253 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1254 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1255 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1256 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1257 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1258 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], 1259 * SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1260 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1261 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], 1262 * USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1263 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1264 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1265 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1266 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1267 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1268 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1269 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1270 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1271 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1272 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1273 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1274 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1275 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1276 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1277 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1278 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1279 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1280 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1281 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1282 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1283 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1284 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1285 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1286 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1287 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1288 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1289 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1290 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1291 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1292 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1293 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1294 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1295 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1296 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1297 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1298 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1299 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1300 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1301 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1302 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1303 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1304 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1305 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1306 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1307 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1308 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1309 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1310 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1311 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1312 /* @brief Has FTM module(s) configuration. */ 1313 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1314 /* @brief Number of FTM modules. */ 1315 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1316 /* @brief Number of FTM triggers with selectable source. */ 1317 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1318 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1319 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1320 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1321 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1322 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1323 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1324 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1325 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1326 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1327 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1328 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1329 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1330 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a 1331 * number starting from zero). */ 1332 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1333 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a 1334 * number starting from zero). */ 1335 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1336 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a 1337 * number starting from zero). */ 1338 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1339 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a 1340 * number starting from zero). */ 1341 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1342 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module 1343 * instance index). */ 1344 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1345 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index 1346 * and n is a channel index). */ 1347 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1348 /* @brief Has TPM module(s) configuration. */ 1349 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1350 /* @brief The highest TPM module index. */ 1351 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1352 /* @brief Has TPM module with index 0. */ 1353 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1354 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1355 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1356 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n 1357 * is a module instance index). */ 1358 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1359 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). 1360 */ 1361 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1362 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1363 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1364 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or 1365 * SOPT9[TPM1CH0SRC]). */ 1366 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1367 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1368 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1369 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1370 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1371 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1372 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1373 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1374 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1375 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1376 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1377 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1378 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1379 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1380 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1381 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1382 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1383 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1384 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1385 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1386 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1387 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1388 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1389 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1390 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1391 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1392 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1393 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1394 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1395 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1396 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1397 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1398 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1399 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1400 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1401 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1402 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1403 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1404 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1405 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1406 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1407 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is 1408 * a module instance index). */ 1409 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) 1410 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1411 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) 1412 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1413 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1414 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1415 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1416 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1417 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1418 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1419 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1420 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1421 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1422 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1423 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1424 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1425 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1426 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1427 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1428 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1429 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1430 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1431 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1432 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1433 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1434 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1435 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) 1436 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1437 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) 1438 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1439 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1440 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1441 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1442 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1443 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1444 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1445 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1446 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1447 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1448 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1449 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1450 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1451 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1452 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1453 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1454 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1455 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1456 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1457 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1458 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1459 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1460 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1461 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1462 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1463 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1464 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1465 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1466 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1467 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1468 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1469 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1470 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1471 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1472 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1473 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1474 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1475 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1476 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1477 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1478 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1479 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) 1480 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1481 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1482 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1483 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1484 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1485 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1486 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1487 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1488 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1489 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1490 /* @brief Has miscellanious control register (register MCR). */ 1491 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1492 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1493 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1494 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1495 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1496 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1497 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1498 /* @brief Has UIDH registers. */ 1499 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1500 /* @brief Has UIDM registers. */ 1501 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1502 1503 /* SMC module features */ 1504 1505 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1506 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1507 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1508 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1509 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1510 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1511 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1512 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1513 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1514 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1515 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1516 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1517 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1518 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1519 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1520 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1521 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1522 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1523 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1524 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1525 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1526 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1527 /* @brief Has stop submode. */ 1528 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1529 /* @brief Has stop submode 0(VLLS0). */ 1530 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1531 /* @brief Has stop submode 1(VLLS1). */ 1532 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1533 /* @brief Has stop submode 2(VLLS2). */ 1534 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1535 /* @brief Has SMC_PARAM. */ 1536 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1537 /* @brief Has SMC_VERID. */ 1538 #define FSL_FEATURE_SMC_HAS_VERID (0) 1539 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1540 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1541 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1542 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1543 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1544 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1545 /* @brief Width of SMC registers. */ 1546 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1547 1548 /* SPI module features */ 1549 1550 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1551 #define FSL_FEATURE_SPI_HAS_FIFO (1) 1552 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 1553 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) 1554 /* @brief Has separate DMA RX and TX requests. */ 1555 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1556 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 1557 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) (((x) == SPI0) ? (0) : (((x) == SPI1) ? (4) : (-1))) 1558 /* @brief Maximum transfer data width in bits. */ 1559 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) 1560 /* @brief The data register name has postfix (L as low and H as high). */ 1561 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) 1562 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1563 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1564 /* @brief SPI0 and SPI1 has shared interrupt vector. */ 1565 #define FSL_FEATURE_SPI_HAS_SHARED_IRQ0_IRQ1 (1) 1566 /* @brief Has 16-bit data transfer support. */ 1567 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) 1568 1569 /* SYSMPU module features */ 1570 1571 /* @brief Specifies number of descriptors available. */ 1572 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (8) 1573 /* @brief Has process identifier support. */ 1574 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1575 /* @brief Total number of MPU slave. */ 1576 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (2) 1577 /* @brief Total number of MPU master. */ 1578 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (3) 1579 1580 /* SysTick module features */ 1581 1582 /* @brief Systick has external reference clock. */ 1583 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1584 /* @brief Systick external reference clock is core clock divided by this value. */ 1585 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1586 1587 /* UART module features */ 1588 1589 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1590 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1591 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the 1592 * registers are 32-bit wide). */ 1593 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1594 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1595 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1596 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1597 #define FSL_FEATURE_UART_HAS_FIFO (1) 1598 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1599 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1600 /* @brief Infrared (modulation) is supported. */ 1601 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1602 /* @brief 2 bits long stop bit is available. */ 1603 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1604 /* @brief If 10-bit mode is supported. */ 1605 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1606 /* @brief Baud rate fine adjustment is available. */ 1607 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1608 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], 1609 * BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1610 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1611 /* @brief Baud rate oversampling is available. */ 1612 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1613 /* @brief Baud rate oversampling is available. */ 1614 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1615 /* @brief Peripheral type. */ 1616 #define FSL_FEATURE_UART_IS_SCI (0) 1617 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1618 #define FSL_FEATURE_UART_FIFO_SIZEn(x) (8) 1619 /* @brief Supports two match addresses to filter incoming frames. */ 1620 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1621 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 1622 * 32-bit wide). */ 1623 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1624 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1625 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1626 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit 1627 * wide). */ 1628 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1629 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1630 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1631 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1632 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1633 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1634 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1635 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1636 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1637 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1638 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0) 1639 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1640 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0) 1641 /* @brief Has separate DMA RX and TX requests. */ 1642 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1643 /* @brief UART0, UART1, UART2 and UART3 have shared interrupt vector. */ 1644 #define FSL_FEATURE_UART_HAS_SHARED_IRQ0_IRQ1_IRQ2_IRQ3 (1) 1645 1646 /* VREF module features */ 1647 1648 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1649 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1650 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1651 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1652 /* @brief If high/low buffer mode supported */ 1653 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1654 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1655 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (1) 1656 1657 /* WDOG module features */ 1658 1659 /* @brief Watchdog is available. */ 1660 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1661 /* @brief Has Wait mode support. */ 1662 #define FSL_FEATURE_WDOG_HAS_WAITEN (0) 1663 1664 /* XBAR module features */ 1665 1666 /* @brief Number of interrupt requests. */ 1667 #define FSL_FEATURE_XBAR_INTERRUPT_COUNT (4) 1668 1669 #endif /* _MKM34Z7_FEATURES_H_ */ 1670
