1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select, LPUART0 - LPUART2. */ 16 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 17 * LPUART instance. */ 18 #define RTE_USART0 0 19 #define RTE_USART0_DMA_EN 0 20 #define RTE_USART1 0 21 #define RTE_USART1_DMA_EN 0 22 #define RTE_USART2 0 23 #define RTE_USART2_DMA_EN 0 24 25 /* UART configuration. */ 26 #define USART_RX_BUFFER_LEN 64 27 #define USART0_RX_BUFFER_ENABLE 0 28 #define USART1_RX_BUFFER_ENABLE 0 29 #define USART2_RX_BUFFER_ENABLE 0 30 31 #define RTE_USART0_PIN_INIT LPUART0_InitPins 32 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 33 #define RTE_USART0_DMA_TX_CH 0 34 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 35 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX 36 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 37 #define RTE_USART0_DMA_RX_CH 1 38 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 39 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX 40 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 41 42 #define RTE_USART1_PIN_INIT LPUART1_InitPins 43 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 44 #define RTE_USART1_DMA_TX_CH 0 45 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx 46 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX 47 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 48 #define RTE_USART1_DMA_RX_CH 1 49 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx 50 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX 51 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 52 53 #define RTE_USART2_PIN_INIT LPUART2_InitPins 54 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 55 #define RTE_USART2_DMA_TX_CH 0 56 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 57 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX 58 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 59 #define RTE_USART2_DMA_RX_CH 1 60 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Rx 61 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX 62 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 63 64 /* I2C Select, LPI2C0 - LPI2C1. */ 65 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 66 * instance. */ 67 #define RTE_I2C0 0 68 #define RTE_I2C0_DMA_EN 0 69 #define RTE_I2C1 0 70 #define RTE_I2C1_DMA_EN 0 71 72 /* LPI2C configuration. */ 73 #define RTE_I2C0_PIN_INIT LPI2C0_InitPins 74 #define RTE_I2C0_PIN_DEINIT LPI2C0_DeinitPins 75 #define RTE_I2C0_DMA_TX_CH 0 76 #define RTE_I2C0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Tx 77 #define RTE_I2C0_DMA_TX_DMAMUX_BASE DMAMUX 78 #define RTE_I2C0_DMA_TX_DMA_BASE DMA0 79 #define RTE_I2C0_DMA_RX_CH 1 80 #define RTE_I2C0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Rx 81 #define RTE_I2C0_DMA_RX_DMAMUX_BASE DMAMUX 82 #define RTE_I2C0_DMA_RX_DMA_BASE DMA0 83 84 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 85 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 86 #define RTE_I2C1_DMA_TX_CH 0 87 #define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C1Tx 88 #define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX 89 #define RTE_I2C1_DMA_TX_DMA_BASE DMA0 90 #define RTE_I2C1_DMA_RX_CH 1 91 #define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C1Rx 92 #define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX 93 #define RTE_I2C1_DMA_RX_DMA_BASE DMA0 94 95 /* SPI Select, DSPI0 - DSPI1. */ 96 /* User needs to provide the implementation of LPSPIX_GetFreq/LPSPIX_InitPins/LPSPIX_DeinitPins for the enabled LPSPI 97 * instance. */ 98 #define RTE_SPI0 0 99 #define RTE_SPI0_DMA_EN 0 100 #define RTE_SPI1 0 101 #define RTE_SPI1_DMA_EN 0 102 103 /* SPI configuration. */ 104 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 105 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 106 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 107 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs3) 108 #define RTE_SPI0_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs3) 109 #define RTE_SPI0_PIN_INIT LPSPI0_InitPins 110 #define RTE_SPI0_PIN_DEINIT LPSPI0_DeinitPins 111 #define RTE_SPI0_DMA_TX_CH 0 112 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Tx 113 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX 114 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 115 #define RTE_SPI0_DMA_RX_CH 1 116 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Rx 117 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX 118 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 119 120 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 121 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 122 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 123 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs3) 124 #define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs3) 125 #define RTE_SPI1_PIN_INIT LPSPI1_InitPins 126 #define RTE_SPI1_PIN_DEINIT LPSPI1_DeinitPins 127 #define RTE_SPI1_DMA_TX_CH 0 128 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI1Tx 129 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX 130 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 131 #define RTE_SPI1_DMA_RX_CH 1 132 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI1Rx 133 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX 134 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 135 136 #endif /* _RTE_DEVICE_H */ 137
