1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40 /* clang-format off */
41 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42 !!GlobalInfo
43 product: Clocks v5.0
44 processor: MK26FN2M0xxx18
45 mcu_data: ksdk2_0
46 processor_version: 0.0.16
47 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
48 /* clang-format on */
49
50 #include "clock_config.h"
51
52 /*******************************************************************************
53 * Definitions
54 ******************************************************************************/
55 #define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */
56 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
57 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
58 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
59 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
60 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
61
62 /*******************************************************************************
63 * Variables
64 ******************************************************************************/
65 /* System clock frequency. */
66 extern uint32_t SystemCoreClock;
67
68 /*******************************************************************************
69 * Code
70 ******************************************************************************/
71 /*FUNCTION**********************************************************************
72 *
73 * Function Name : CLOCK_CONFIG_FllStableDelay
74 * Description : This function is used to delay for FLL stable.
75 *
76 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)77 static void CLOCK_CONFIG_FllStableDelay(void)
78 {
79 uint32_t i = 30000U;
80 while (i--)
81 {
82 __NOP();
83 }
84 }
85
86 /*******************************************************************************
87 ************************ BOARD_InitBootClocks function ************************
88 ******************************************************************************/
BOARD_InitBootClocks(void)89 void BOARD_InitBootClocks(void)
90 {
91 BOARD_BootClockRUN();
92 }
93
94 /*******************************************************************************
95 ********************** Configuration BOARD_BootClockRUN ***********************
96 ******************************************************************************/
97 /* clang-format off */
98 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
99 !!Configuration
100 name: BOARD_BootClockRUN
101 called_from_default_init: true
102 outputs:
103 - {id: Bus_clock.outFreq, value: 20.97152 MHz}
104 - {id: Core_clock.outFreq, value: 20.97152 MHz}
105 - {id: Flash_clock.outFreq, value: 10.48576 MHz}
106 - {id: FlexBus_clock.outFreq, value: 10.48576 MHz}
107 - {id: LPO_clock.outFreq, value: 1 kHz}
108 - {id: MCGFFCLK.outFreq, value: 32.768 kHz}
109 - {id: PLLFLLCLK.outFreq, value: 20.97152 MHz}
110 - {id: System_clock.outFreq, value: 20.97152 MHz}
111 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
112 /* clang-format on */
113
114 /*******************************************************************************
115 * Variables for BOARD_BootClockRUN configuration
116 ******************************************************************************/
117 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
118 {
119 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
120 .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
121 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
122 .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
123 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
124 .drs = kMCG_DrsLow, /* Low frequency range */
125 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
126 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
127 .pll0Config =
128 {
129 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
130 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
131 .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
132 },
133 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
134 };
135 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
136 {
137 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
138 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
139 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
140 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
141 .clkdiv1 = 0x110000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /2 */
142 };
143 const osc_config_t oscConfig_BOARD_BootClockRUN =
144 {
145 .freq = 0U, /* Oscillator frequency: 0Hz */
146 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
147 .workMode = kOSC_ModeExt, /* Use external clock */
148 .oscerConfig =
149 {
150 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
151 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
152 }
153 };
154
155 /*******************************************************************************
156 * Code for BOARD_BootClockRUN configuration
157 ******************************************************************************/
BOARD_BootClockRUN(void)158 void BOARD_BootClockRUN(void)
159 {
160 /* Set the system clock dividers in SIM to safe value. */
161 CLOCK_SetSimSafeDivs();
162 /* Configure the Internal Reference clock (MCGIRCLK). */
163 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
164 mcgConfig_BOARD_BootClockRUN.ircs,
165 mcgConfig_BOARD_BootClockRUN.fcrdiv);
166 /* Set MCG to FEI mode. */
167 #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
168 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32,
169 mcgConfig_BOARD_BootClockRUN.drs,
170 CLOCK_CONFIG_FllStableDelay);
171 #else
172 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs,
173 CLOCK_CONFIG_FllStableDelay);
174 #endif
175 /* Set the clock configuration in SIM module. */
176 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
177 /* Set SystemCoreClock variable. */
178 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
179 }
180
181
