1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART select, UART0-UART5 */ 16 /* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART 17 * instance. */ 18 #define RTE_USART0 0 19 #define RTE_USART0_DMA_EN 0 20 #define RTE_USART1 0 21 #define RTE_USART1_DMA_EN 0 22 #define RTE_USART2 0 23 #define RTE_USART2_DMA_EN 0 24 #define RTE_USART3 0 25 #define RTE_USART3_DMA_EN 0 26 #define RTE_USART4 0 27 #define RTE_USART4_DMA_EN 0 28 #define RTE_USART5 0 29 #define RTE_USART5_DMA_EN 0 30 31 /* UART RX Buffer configuration. */ 32 #define USART_RX_BUFFER_LEN 64 33 #define USART0_RX_BUFFER_ENABLE 0 34 #define USART1_RX_BUFFER_ENABLE 0 35 #define USART2_RX_BUFFER_ENABLE 0 36 #define USART3_RX_BUFFER_ENABLE 0 37 #define USART4_RX_BUFFER_ENABLE 0 38 #define USART5_RX_BUFFER_ENABLE 0 39 40 #define RTE_USART0_PIN_INIT UART0_InitPins 41 #define RTE_USART0_PIN_DEINIT UART0_DeinitPins 42 #define RTE_USART0_DMA_TX_CH 0 43 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 44 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 45 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 46 #define RTE_USART0_DMA_RX_CH 1 47 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 48 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 49 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 50 51 #define RTE_USART1_PIN_INIT UART1_InitPins 52 #define RTE_USART1_PIN_DEINIT UART1_DeinitPins 53 #define RTE_USART1_DMA_TX_CH 0 54 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 55 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 56 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 57 #define RTE_USART1_DMA_RX_CH 1 58 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 59 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 60 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 61 62 #define RTE_USART2_PIN_INIT UART2_InitPins 63 #define RTE_USART2_PIN_DEINIT UART2_DeinitPins 64 #define RTE_USART2_DMA_TX_CH 0 65 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 66 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 67 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 68 #define RTE_USART2_DMA_RX_CH 1 69 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 70 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 71 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 72 73 #define RTE_USART3_PIN_INIT UART3_InitPins 74 #define RTE_USART3_PIN_DEINIT UART3_DeinitPins 75 #define RTE_USART3_DMA_TX_CH 0 76 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx 77 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 78 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 79 #define RTE_USART3_DMA_RX_CH 1 80 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx 81 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 82 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 83 84 #define RTE_USART4_PIN_INIT UART4_InitPins 85 #define RTE_USART4_PIN_DEINIT UART4_DeinitPins 86 #define RTE_USART4_DMA_TX_CH 0 87 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 88 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0 89 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 90 #define RTE_USART4_DMA_RX_CH 1 91 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 92 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0 93 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 94 95 #define RTE_USART5_PIN_INIT UART5_InitPins 96 #define RTE_USART5_PIN_DEINIT UART5_DeinitPins 97 #define RTE_USART5_DMA_TX_CH 0 98 #define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART5 99 #define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0 100 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 101 #define RTE_USART5_DMA_RX_CH 1 102 #define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART5 103 #define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0 104 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 105 106 /* I2C select, I2C0 - I2C2. */ 107 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 108 */ 109 #define RTE_I2C0 0 110 #define RTE_I2C0_DMA_EN 0 111 #define RTE_I2C1 0 112 #define RTE_I2C1_DMA_EN 0 113 #define RTE_I2C2 0 114 #define RTE_I2C2_DMA_EN 0 115 116 /*I2C configuration*/ 117 #define RTE_I2C0_Master_DMA_BASE DMA0 118 #define RTE_I2C0_Master_DMA_CH 0 119 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 120 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 121 122 #define RTE_I2C1_Master_DMA_BASE DMA0 123 #define RTE_I2C1_Master_DMA_CH 1 124 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 125 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 126 127 #define RTE_I2C2_Master_DMA_BASE DMA0 128 #define RTE_I2C2_Master_DMA_CH 2 129 #define RTE_I2C2_Master_DMAMUX_BASE DMAMUX0 130 #define RTE_I2C2_Master_PERI_SEL kDmaRequestMux0I2C2 131 132 /* SPI select, DSPI0 - DSPI2. */ 133 /* User needs to provide the implementation of DSPIX_GetFreq/DSPIX_InitPins/DSPIX_DeinitPins for the enabled DSPI 134 * instance. */ 135 #define RTE_SPI0 0 136 #define RTE_SPI0_DMA_EN 0 137 #define RTE_SPI1 0 138 #define RTE_SPI1_DMA_EN 0 139 #define RTE_SPI2 0 140 #define RTE_SPI2_DMA_EN 0 141 142 /* DSPI configuration. */ 143 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 144 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 145 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 146 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 147 #define RTE_SPI0_PIN_INIT DSPI0_InitPins 148 #define RTE_SPI0_PIN_DEINIT DSPI0_DeinitPins 149 #define RTE_SPI0_DMA_TX_CH 0 150 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 151 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 152 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 153 #define RTE_SPI0_DMA_RX_CH 1 154 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 155 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 156 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 157 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 158 #define RTE_SPI0_DMA_LINK_CH 2 159 160 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 161 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 162 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 163 #define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 164 #define RTE_SPI1_PIN_INIT DSPI1_InitPins 165 #define RTE_SPI1_PIN_DEINIT DSPI1_DeinitPins 166 #define RTE_SPI1_DMA_TX_CH 4 167 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 168 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 169 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 170 #define RTE_SPI1_DMA_RX_CH 3 171 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 172 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 173 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 174 #define RTE_SPI1_DMA_LINK_DMA_BASE DMA0 175 #define RTE_SPI1_DMA_LINK_CH 2 176 177 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 178 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 179 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 180 #define RTE_SPI2_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 181 #define RTE_SPI2_PIN_INIT DSPI2_InitPins 182 #define RTE_SPI2_PIN_DEINIT DSPI2_DeinitPins 183 #define RTE_SPI2_DMA_TX_CH 6 184 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2 185 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0 186 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 187 #define RTE_SPI2_DMA_RX_CH 7 188 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2 189 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0 190 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 191 #define RTE_SPI2_DMA_LINK_DMA_BASE DMA0 192 #define RTE_SPI2_DMA_LINK_CH 8 193 194 #endif /* _RTE_DEVICE_H */ 195
