1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* USART Select. */ 16 /* Use UART0 - UART2. */ 17 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 18 * LPUART instance. */ 19 #define RTE_USART0 0 20 #define RTE_USART0_DMA_EN 0 21 #define RTE_USART1 0 22 #define RTE_USART1_DMA_EN 0 23 #define RTE_USART2 0 24 #define RTE_USART2_DMA_EN 0 25 /*Use LPUART0. */ 26 #define RTE_USART3 0 27 #define RTE_USART3_DMA_EN 0 28 29 /* UART RX Buffer configuration. */ 30 #define USART_RX_BUFFER_LEN 64 31 #define USART0_RX_BUFFER_ENABLE 0 32 #define USART1_RX_BUFFER_ENABLE 0 33 #define USART2_RX_BUFFER_ENABLE 0 34 #define USART3_RX_BUFFER_ENABLE 0 35 36 /* UART configuration. */ 37 38 #define RTE_USART0_PIN_INIT LPUART0_InitPins 39 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 40 #define RTE_USART0_DMA_TX_CH 0 41 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 42 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 43 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 44 #define RTE_USART0_DMA_RX_CH 1 45 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 46 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 47 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 48 49 #define RTE_USART1_PIN_INIT LPUART1_InitPins 50 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 51 #define RTE_USART1_DMA_TX_CH 0 52 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 53 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 54 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 55 #define RTE_USART1_DMA_RX_CH 1 56 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 57 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 58 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 59 60 #define RTE_USART2_PIN_INIT LPUART2_InitPins 61 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 62 #define RTE_USART2_DMA_TX_CH 0 63 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 64 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 65 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 66 #define RTE_USART2_DMA_RX_CH 1 67 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 68 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 69 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 70 71 #define RTE_USART3_PIN_INIT LPUART3_InitPins 72 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 73 #define RTE_USART3_DMA_TX_CH 0 74 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 75 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 76 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 77 #define RTE_USART3_DMA_RX_CH 1 78 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 79 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 80 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 81 82 /* I2C Select */ 83 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 84 */ 85 #define RTE_I2C0 0 86 #define RTE_I2C0_DMA_EN 0 87 #define RTE_I2C1 0 88 #define RTE_I2C1_DMA_EN 0 89 90 /*I2C configuration*/ 91 #define RTE_I2C0_Master_DMA_BASE DMA0 92 #define RTE_I2C0_Master_DMA_CH 0 93 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 94 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 95 96 #define RTE_I2C1_Master_DMA_BASE DMA0 97 #define RTE_I2C1_Master_DMA_CH 1 98 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 99 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 100 101 /* DSPI Select. */ 102 /* User needs to provide the implementation of DSPIX_GetFreq/DSPIX_InitPins/DSPIX_DeinitPins for the enabled DSPI 103 * instance. */ 104 #define RTE_SPI0 0 105 #define RTE_SPI0_DMA_EN 0 106 #define RTE_SPI1 0 107 #define RTE_SPI1_DMA_EN 0 108 109 /* DSPI configuration. */ 110 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 111 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 112 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 113 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 114 #define RTE_SPI0_PIN_INIT DSPI0_InitPins 115 #define RTE_SPI0_PIN_DEINIT DSPI0_DeinitPins 116 #define RTE_SPI0_DMA_TX_CH 0 117 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 118 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 119 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 120 #define RTE_SPI0_DMA_RX_CH 1 121 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 122 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 123 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 124 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 125 #define RTE_SPI0_DMA_LINK_CH 2 126 127 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 128 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 129 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 130 #define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 131 #define RTE_SPI1_PIN_INIT DSPI1_InitPins 132 #define RTE_SPI1_PIN_DEINIT DSPI1_DeinitPins 133 #define RTE_SPI1_DMA_TX_CH 0 134 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 135 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 136 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 137 #define RTE_SPI1_DMA_RX_CH 1 138 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 139 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 140 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 141 #define RTE_SPI1_DMA_LINK_DMA_BASE DMA0 142 #define RTE_SPI1_DMA_LINK_CH 2 143 144 #endif /* _RTE_DEVICE_H */ 145
