1 /* 2 * Copyright 2018 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, UART0-UART7. */ 14 /* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART 15 * instance. */ 16 #define RTE_USART0 0 17 #define RTE_USART0_DMA_EN 0 18 #define RTE_USART1 0 19 #define RTE_USART1_DMA_EN 0 20 #define RTE_USART2 0 21 #define RTE_USART2_DMA_EN 0 22 #define RTE_USART3 0 23 #define RTE_USART3_DMA_EN 0 24 #define RTE_USART4 0 25 #define RTE_USART4_DMA_EN 0 26 #define RTE_USART5 0 27 #define RTE_USART5_DMA_EN 0 28 #define RTE_USART6 0 29 #define RTE_USART6_DMA_EN 0 30 #define RTE_USART7 0 31 #define RTE_USART7_DMA_EN 0 32 33 /* USART configuration. */ 34 #define USART_RX_BUFFER_LEN 64 35 #define USART0_RX_BUFFER_ENABLE 0 36 #define USART1_RX_BUFFER_ENABLE 0 37 #define USART2_RX_BUFFER_ENABLE 0 38 #define USART3_RX_BUFFER_ENABLE 0 39 #define USART4_RX_BUFFER_ENABLE 0 40 #define USART5_RX_BUFFER_ENABLE 0 41 #define USART6_RX_BUFFER_ENABLE 0 42 #define USART7_RX_BUFFER_ENABLE 0 43 44 #define RTE_USART0_PIN_INIT USART0_InitPins 45 #define RTE_USART0_PIN_DEINIT USART0_DeinitPins 46 #define RTE_USART0_DMA_TX_CH 1 47 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 48 #define RTE_USART0_DMA_RX_CH 0 49 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 50 51 #define RTE_USART1_PIN_INIT USART1_InitPins 52 #define RTE_USART1_PIN_DEINIT USART1_DeinitPins 53 #define RTE_USART1_DMA_TX_CH 3 54 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 55 #define RTE_USART1_DMA_RX_CH 2 56 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 57 58 #define RTE_USART2_PIN_INIT USART2_InitPins 59 #define RTE_USART2_PIN_DEINIT USART2_DeinitPins 60 #define RTE_USART2_DMA_TX_CH 5 61 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 62 #define RTE_USART2_DMA_RX_CH 4 63 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 64 65 #define RTE_USART3_PIN_INIT USART3_InitPins 66 #define RTE_USART3_PIN_DEINIT USART3_DeinitPins 67 #define RTE_USART3_DMA_TX_CH 7 68 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 69 #define RTE_USART3_DMA_RX_CH 6 70 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 71 72 #define RTE_USART4_PIN_INIT USART4_InitPins 73 #define RTE_USART4_PIN_DEINIT USART4_DeinitPins 74 #define RTE_USART4_DMA_TX_CH 9 75 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 76 #define RTE_USART4_DMA_RX_CH 8 77 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 78 79 #define RTE_USART5_PIN_INIT USART5_InitPins 80 #define RTE_USART5_PIN_DEINIT USART5_DeinitPins 81 #define RTE_USART5_DMA_TX_CH 11 82 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 83 #define RTE_USART5_DMA_RX_CH 10 84 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 85 86 #define RTE_USART6_PIN_INIT USART6_InitPins 87 #define RTE_USART6_PIN_DEINIT USART6_DeinitPins 88 #define RTE_USART6_DMA_TX_CH 13 89 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 90 #define RTE_USART6_DMA_RX_CH 12 91 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 92 93 #define RTE_USART7_PIN_INIT USART7_InitPins 94 #define RTE_USART7_PIN_DEINIT USART7_DeinitPins 95 #define RTE_USART7_DMA_TX_CH 15 96 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 97 #define RTE_USART7_DMA_RX_CH 14 98 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 99 100 /* I2C Select, I2C0 -I2C7*/ 101 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 102 */ 103 #define RTE_I2C0 0 104 #define RTE_I2C0_DMA_EN 0 105 #define RTE_I2C1 0 106 #define RTE_I2C1_DMA_EN 0 107 #define RTE_I2C2 0 108 #define RTE_I2C2_DMA_EN 0 109 #define RTE_I2C3 0 110 #define RTE_I2C3_DMA_EN 0 111 #define RTE_I2C4 0 112 #define RTE_I2C4_DMA_EN 0 113 #define RTE_I2C5 0 114 #define RTE_I2C5_DMA_EN 0 115 #define RTE_I2C6 0 116 #define RTE_I2C6_DMA_EN 0 117 #define RTE_I2C7 0 118 #define RTE_I2C7_DMA_EN 0 119 120 /*I2C configuration*/ 121 #define RTE_I2C0_Master_DMA_BASE DMA0 122 #define RTE_I2C0_Master_DMA_CH 1 123 124 #define RTE_I2C1_Master_DMA_BASE DMA0 125 #define RTE_I2C1_Master_DMA_CH 3 126 127 #define RTE_I2C2_Master_DMA_BASE DMA0 128 #define RTE_I2C2_Master_DMA_CH 5 129 130 #define RTE_I2C3_Master_DMA_BASE DMA0 131 #define RTE_I2C3_Master_DMA_CH 7 132 133 #define RTE_I2C4_Master_DMA_BASE DMA0 134 #define RTE_I2C4_Master_DMA_CH 9 135 136 #define RTE_I2C5_Master_DMA_BASE DMA0 137 #define RTE_I2C5_Master_DMA_CH 11 138 139 #define RTE_I2C6_Master_DMA_BASE DMA0 140 #define RTE_I2C6_Master_DMA_CH 13 141 142 #define RTE_I2C7_Master_DMA_BASE DMA0 143 #define RTE_I2C7_Master_DMA_CH 15 144 145 /* SPI select, SPI0 - SPI7, SPI14.*/ 146 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 147 */ 148 #define RTE_SPI0 0 149 #define RTE_SPI0_DMA_EN 0 150 #define RTE_SPI1 0 151 #define RTE_SPI1_DMA_EN 0 152 #define RTE_SPI2 0 153 #define RTE_SPI2_DMA_EN 0 154 #define RTE_SPI3 0 155 #define RTE_SPI3_DMA_EN 0 156 #define RTE_SPI4 0 157 #define RTE_SPI4_DMA_EN 0 158 #define RTE_SPI5 0 159 #define RTE_SPI5_DMA_EN 0 160 #define RTE_SPI6 0 161 #define RTE_SPI6_DMA_EN 0 162 #define RTE_SPI7 0 163 #define RTE_SPI7_DMA_EN 0 164 #define RTE_SPI14 0 165 #define RTE_SPI14_DMA_EN 0 166 167 /* SPI configuration. */ 168 #define RTE_SPI0_SSEL_NUM kSPI_Ssel0 169 #define RTE_SPI0_PIN_INIT SPI0_InitPins 170 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 171 #define RTE_SPI0_DMA_TX_CH 1 172 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 173 #define RTE_SPI0_DMA_RX_CH 0 174 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 175 176 #define RTE_SPI1_SSEL_NUM kSPI_Ssel0 177 #define RTE_SPI1_PIN_INIT SPI1_InitPins 178 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 179 #define RTE_SPI1_DMA_TX_CH 3 180 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 181 #define RTE_SPI1_DMA_RX_CH 2 182 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 183 184 #define RTE_SPI2_SSEL_NUM kSPI_Ssel0 185 #define RTE_SPI2_PIN_INIT SPI2_InitPins 186 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 187 #define RTE_SPI2_DMA_TX_CH 5 188 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 189 #define RTE_SPI2_DMA_RX_CH 4 190 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 191 192 #define RTE_SPI3_SSEL_NUM kSPI_Ssel0 193 #define RTE_SPI3_PIN_INIT SPI3_InitPins 194 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 195 #define RTE_SPI3_DMA_TX_CH 7 196 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 197 #define RTE_SPI3_DMA_RX_CH 6 198 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 199 200 #define RTE_SPI4_SSEL_NUM kSPI_Ssel0 201 #define RTE_SPI4_PIN_INIT SPI4_InitPins 202 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 203 #define RTE_SPI4_DMA_TX_CH 9 204 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 205 #define RTE_SPI4_DMA_RX_CH 8 206 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 207 208 #define RTE_SPI5_SSEL_NUM kSPI_Ssel0 209 #define RTE_SPI5_PIN_INIT SPI5_InitPins 210 #define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins 211 #define RTE_SPI5_DMA_TX_CH 11 212 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 213 #define RTE_SPI5_DMA_RX_CH 10 214 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 215 216 #define RTE_SPI6_SSEL_NUM kSPI_Ssel0 217 #define RTE_SPI6_PIN_INIT SPI6_InitPins 218 #define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins 219 #define RTE_SPI6_DMA_TX_CH 13 220 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 221 #define RTE_SPI6_DMA_RX_CH 12 222 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 223 224 #define RTE_SPI7_SSEL_NUM kSPI_Ssel0 225 #define RTE_SPI7_PIN_INIT SPI7_InitPins 226 #define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins 227 #define RTE_SPI7_DMA_TX_CH 15 228 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 229 #define RTE_SPI7_DMA_RX_CH 14 230 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 231 232 #define RTE_SPI14_SSEL_NUM kSPI_Ssel0 233 #define RTE_SPI14_PIN_INIT SPI14_InitPins 234 #define RTE_SPI14_PIN_DEINIT SPI14_DeinitPins 235 #define RTE_SPI14_DMA_TX_CH 27 236 #define RTE_SPI14_DMA_TX_DMA_BASE DMA0 237 #define RTE_SPI14_DMA_RX_CH 26 238 #define RTE_SPI14_DMA_RX_DMA_BASE DMA0 239 240 #endif /* _RTE_DEVICE_H */ 241
