1 /* 2 ** ################################################################### 3 ** Processors: MIMXRT595SFAWC_dsp 4 ** MIMXRT595SFFOC_dsp 5 ** 6 ** Compiler: Xtensa Compiler 7 ** Reference manual: iMXRT500RM Rev.0, 01/2021 8 ** Version: rev. 5.0, 2020-08-27 9 ** Build: b220711 10 ** 11 ** Abstract: 12 ** Provides a system configuration function and a global variable that 13 ** contains the system frequency. It configures the device and initializes 14 ** the oscillator (PLL) that is part of the microcontroller device. 15 ** 16 ** Copyright 2016 Freescale Semiconductor, Inc. 17 ** Copyright 2016-2022 NXP 18 ** All rights reserved. 19 ** 20 ** SPDX-License-Identifier: BSD-3-Clause 21 ** 22 ** http: www.nxp.com 23 ** mail: support@nxp.com 24 ** 25 ** Revisions: 26 ** - rev. 1.0 (2019-04-19) 27 ** Initial version. 28 ** - rev. 2.0 (2019-07-22) 29 ** Base on rev 0.7 RM. 30 ** - rev. 3.0 (2020-03-16) 31 ** Base on Rev.A RM. 32 ** - rev. 4.0 (2020-05-18) 33 ** Base on Rev.B RM. 34 ** - rev. 5.0 (2020-08-27) 35 ** Base on Rev.C RM. 36 ** 37 ** ################################################################### 38 */ 39 40 /*! 41 * @file MIMXRT595S 42 * @version 1.0 43 * @date 110722 44 * @brief Device specific configuration file for MIMXRT595S (implementation file) 45 * 46 * Provides a system configuration function and a global variable that contains 47 * the system frequency. It configures the device and initializes the oscillator 48 * (PLL) that is part of the microcontroller device. 49 */ 50 51 #include <stdint.h> 52 #include "fsl_device_registers.h" 53 getSpllFreq(void)54static uint32_t getSpllFreq(void) 55 { 56 uint32_t freq = 0U; 57 uint64_t freqTmp = 0U; 58 59 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) 60 { 61 case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* FRO_DIV8 clock */ 62 freq = CLK_FRO_DIV8_CLK; 63 break; 64 case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock */ 65 freq = CLK_OSC_CLK; 66 break; 67 default: 68 freq = 0U; 69 break; 70 } 71 72 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) 73 { 74 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ 75 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM)); 76 freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; 77 freq += (uint32_t)freqTmp; 78 } 79 80 return freq; 81 } 82 83 /* ---------------------------------------------------------------------------- 84 -- Core clock 85 ---------------------------------------------------------------------------- */ 86 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 87 88 /* ---------------------------------------------------------------------------- 89 -- SystemInit() 90 ---------------------------------------------------------------------------- */ 91 SystemInit(void)92__attribute__((weak)) void SystemInit(void) 93 { 94 SystemInitHook(); 95 } 96 97 /* ---------------------------------------------------------------------------- 98 -- SystemCoreClockUpdate() 99 ---------------------------------------------------------------------------- */ 100 SystemCoreClockUpdate(void)101void SystemCoreClockUpdate(void) 102 { 103 /* iMXRT5xx systemCoreClockUpdate */ 104 uint32_t freq = 0U; 105 106 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) 107 { 108 case CLKCTL1_DSPCPUCLKSELB_SEL(0): /* DSPCPUCLKSELA clock */ 109 switch ((CLKCTL1->DSPCPUCLKSELA) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK) 110 { 111 case CLKCTL1_DSPCPUCLKSELA_SEL(0): /* FRO clock */ 112 freq = CLK_FRO_CLK; 113 break; 114 case CLKCTL1_DSPCPUCLKSELA_SEL(1): /* OSC_CLK clock */ 115 freq = CLK_OSC_CLK; 116 break; 117 case CLKCTL1_DSPCPUCLKSELA_SEL(2): /* Low Power Oscillator Clock (1m_lposc) */ 118 freq = CLK_LPOSC_1MHZ; 119 break; 120 default: 121 freq = 0U; 122 break; 123 } 124 break; 125 case CLKCTL1_DSPCPUCLKSELB_SEL(1): /* Main System PLL clock */ 126 freq = getSpllFreq(); 127 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) 128 { 129 freq = 130 (uint32_t)((uint64_t)freq * 18U / 131 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); 132 } 133 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); 134 break; 135 case CLKCTL1_DSPCPUCLKSELB_SEL(2): /* DSP PLL clock */ 136 freq = getSpllFreq(); 137 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) 138 { 139 freq = 140 (uint32_t)((uint64_t)freq * 18U / 141 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); 142 } 143 freq = freq / ((CLKCTL0->DSPPLLCLKDIV & CLKCTL0_DSPPLLCLKDIV_DIV_MASK) + 1U); 144 break; 145 case CLKCTL1_DSPCPUCLKSELB_SEL(3): /* RTC 32KHz clock */ 146 freq = CLK_RTC_32K_CLK; 147 break; 148 default: 149 freq = 0U; 150 break; 151 } 152 153 SystemCoreClock = freq / ((CLKCTL1->DSPCPUCLKDIV & 0xFFU) + 1U); 154 } 155 156 /* ---------------------------------------------------------------------------- 157 -- SystemInitHook() 158 ---------------------------------------------------------------------------- */ 159 SystemInitHook(void)160__attribute__((weak)) void SystemInitHook(void) 161 { 162 /* Void implementation of the weak function. */ 163 } 164