1 /*
2  * Copyright 2019-2020 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "fsl_soc_mipi_csi2rx.h"
9 /* Component ID definition, used by tools. */
10 #ifndef FSL_COMPONENT_ID
11 #define FSL_COMPONENT_ID "platform.drivers.soc_mipi_csi2rx"
12 #endif
13 
14 /*******************************************************************************
15  * Definitions
16  ******************************************************************************/
17 
18 /*******************************************************************************
19  * Prototypes
20  ******************************************************************************/
21 
22 /*******************************************************************************
23  * Variables
24  ******************************************************************************/
25 
26 /*******************************************************************************
27  * Code
28  ******************************************************************************/
29 
MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type * base,bool reset)30 void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset)
31 {
32     if (reset)
33     {
34         IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK;
35     }
36     else
37     {
38         IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK;
39     }
40 }
41 
MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type * base,uint8_t tHsSettle_EscClk)42 void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk)
43 {
44     /* Pixel link control */
45     VIDEO_MUX->PLM_CTRL.RW = 0U;
46 
47     IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) |
48                         IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK |  /* Enable RX. */
49                         IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK | /* Auto power down unused lanes. */
50                         IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK |
51                         IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK |      /* Enable the DDR clock. */
52                         IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK | /* Continue clock. */
53                         IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(tHsSettle_EscClk - 1UL); /* T(HS-SETTLE) */
54 
55     /* Don't mask any data type */
56     VIDEO_MUX->CFG_DT_DISABLE.RW = 0U;
57 
58     /* Enable pixel link master. */
59     VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK);
60 
61     /* Power up PHY. */
62     IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK;
63 }
64 
MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type * base)65 void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base)
66 {
67     IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK;
68 
69     /* Pixel link control */
70     VIDEO_MUX->PLM_CTRL.RW = 0U;
71 }
72