1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1165CVM5A_cm4
4 ** MIMXRT1165DVM6A_cm4
5 ** MIMXRT1165XVM5A_cm4
6 **
7 ** Compilers: Freescale C/C++ for Embedded ARM
8 ** GNU C Compiler
9 ** IAR ANSI C/C++ Compiler for ARM
10 ** Keil ARM C/C++ Compiler
11 ** MCUXpresso Compiler
12 **
13 ** Reference manual: IMXRT1160RM, Rev 0, 03/2021
14 ** Version: rev. 0.1, 2020-12-29
15 ** Build: b210615
16 **
17 ** Abstract:
18 ** Provides a system configuration function and a global variable that
19 ** contains the system frequency. It configures the device and initializes
20 ** the oscillator (PLL) that is part of the microcontroller device.
21 **
22 ** Copyright 2016 Freescale Semiconductor, Inc.
23 ** Copyright 2016-2021 NXP
24 ** All rights reserved.
25 **
26 ** SPDX-License-Identifier: BSD-3-Clause
27 **
28 ** http: www.nxp.com
29 ** mail: support@nxp.com
30 **
31 ** Revisions:
32 ** - rev. 0.1 (2020-12-29)
33 ** Initial version.
34 **
35 ** ###################################################################
36 */
37
38 /*!
39 * @file MIMXRT1165_cm4
40 * @version 1.0
41 * @date 2021-06-15
42 * @brief Device specific configuration file for MIMXRT1165_cm4 (implementation
43 * file)
44 *
45 * Provides a system configuration function and a global variable that contains
46 * the system frequency. It configures the device and initializes the oscillator
47 * (PLL) that is part of the microcontroller device.
48 */
49
50 #include <stdint.h>
51 #include "fsl_device_registers.h"
52
53
54
55 /* ----------------------------------------------------------------------------
56 -- Core clock
57 ---------------------------------------------------------------------------- */
58
59 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
60
61 /* ----------------------------------------------------------------------------
62 -- SystemInit()
63 ---------------------------------------------------------------------------- */
64
SystemInit(void)65 void SystemInit (void) {
66 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
67 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
68 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
69
70 #if defined(__MCUXPRESSO)
71 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
72 SCB->VTOR = (uint32_t)g_pfnVectors;
73 #endif
74
75 /* Watchdog disable */
76
77 #if (DISABLE_WDOG)
78 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
79 {
80 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
81 }
82 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
83 {
84 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
85 }
86 if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
87 {
88 RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
89 }
90 else
91 {
92 RTWDOG3->CNT = 0xC520U;
93 RTWDOG3->CNT = 0xD928U;
94 }
95 RTWDOG3->TOVAL = 0xFFFF;
96 RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
97 if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
98 {
99 RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
100 }
101 else
102 {
103 RTWDOG4->CNT = 0xC520U;
104 RTWDOG4->CNT = 0xD928U;
105 }
106 RTWDOG4->TOVAL = 0xFFFF;
107 RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
108 #endif /* (DISABLE_WDOG) */
109
110 /* Disable Systick which might be enabled by bootrom */
111 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
112 {
113 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
114 }
115
116 /* Initialize Cache */
117 /* Enable Code Bus Cache */
118 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK))
119 {
120 /* set command to invalidate all ways, and write GO bit to initiate command */
121 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_GO_MASK;
122 /* Wait until the command completes */
123 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
124 }
125 /* Enable cache, enable write buffer */
126 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
127 }
128
129 /* Enable System Bus Cache */
130 if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK))
131 {
132 /* set command to invalidate all ways, and write GO bit to initiate command */
133 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_GO_MASK;
134 /* Wait until the command completes */
135 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
136 }
137 /* Enable cache, enable write buffer */
138 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
139 }
140
141 /* Clear bit 13 to its reset value since it might be set by ROM. */
142 IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
143
144 #if defined(ROM_ECC_ENABLED)
145 /* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
146 Save SRSR to SRC->GPR[11] so that application can still check SRSR value from SRC->GPR[11]. */
147 SRC->GPR[11] = SRC->SRSR;
148 /* clear SRSR */
149 SRC->SRSR = 0xFFFFFFFFU;
150 #endif
151
152 /* Enable entry to thread mode when divide by zero */
153 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
154 __DSB();
155 __ISB();
156
157 SystemInitHook();
158 }
159
160 /* ----------------------------------------------------------------------------
161 -- SystemCoreClockUpdate()
162 ---------------------------------------------------------------------------- */
163
SystemCoreClockUpdate(void)164 void SystemCoreClockUpdate (void) {
165
166 /* TBD */
167
168 }
169
170 /* ----------------------------------------------------------------------------
171 -- SystemInitHook()
172 ---------------------------------------------------------------------------- */
173
SystemInitHook(void)174 __attribute__ ((weak)) void SystemInitHook (void) {
175 /* Void implementation of the weak function. */
176 }
177
