1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select, UART0 - UART5. */ 16 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 17 * LPUART instance. */ 18 #define RTE_USART1 1 19 #define RTE_USART1_DMA_EN 1 20 #define RTE_USART2 0 21 #define RTE_USART2_DMA_EN 0 22 #define RTE_USART3 0 23 #define RTE_USART3_DMA_EN 0 24 #define RTE_USART4 0 25 #define RTE_USART4_DMA_EN 0 26 #define RTE_USART5 0 27 #define RTE_USART5_DMA_EN 0 28 #define RTE_USART6 0 29 #define RTE_USART6_DMA_EN 0 30 #define RTE_USART7 0 31 #define RTE_USART7_DMA_EN 0 32 #define RTE_USART8 0 33 #define RTE_USART8_DMA_EN 0 34 35 /* UART configuration. */ 36 #define RTE_USART1_PIN_INIT LPUART1_InitPins 37 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 38 #define RTE_USART1_DMA_TX_CH 0 39 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Tx 40 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX 41 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 42 #define RTE_USART1_DMA_RX_CH 1 43 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Rx 44 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX 45 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 46 47 #define RTE_USART2_PIN_INIT LPUART2_InitPins 48 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 49 #define RTE_USART2_DMA_TX_CH 2 50 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Tx 51 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX 52 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 53 #define RTE_USART2_DMA_RX_CH 3 54 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Rx 55 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX 56 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 57 58 #define RTE_USART3_PIN_INIT LPUART3_InitPins 59 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 60 #define RTE_USART3_DMA_TX_CH 4 61 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Tx 62 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX 63 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 64 #define RTE_USART3_DMA_RX_CH 5 65 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Rx 66 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX 67 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 68 69 #define RTE_USART4_PIN_INIT LPUART4_InitPins 70 #define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins 71 #define RTE_USART4_DMA_TX_CH 6 72 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Tx 73 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX 74 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 75 #define RTE_USART4_DMA_RX_CH 7 76 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Rx 77 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX 78 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 79 80 #define RTE_USART5_PIN_INIT LPUART5_InitPins 81 #define RTE_USART5_PIN_DEINIT LPUART5_DeinitPins 82 #define RTE_USART5_DMA_TX_CH 8 83 #define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Tx 84 #define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX 85 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 86 #define RTE_USART5_DMA_RX_CH 9 87 #define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Rx 88 #define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX 89 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 90 91 #define RTE_USART6_PIN_INIT LPUART6_InitPins 92 #define RTE_USART6_PIN_DEINIT LPUART6_DeinitPins 93 #define RTE_USART6_DMA_TX_CH 10 94 #define RTE_USART6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Tx 95 #define RTE_USART6_DMA_TX_DMAMUX_BASE DMAMUX 96 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 97 #define RTE_USART6_DMA_RX_CH 11 98 #define RTE_USART6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Rx 99 #define RTE_USART6_DMA_RX_DMAMUX_BASE DMAMUX 100 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 101 102 #define RTE_USART7_PIN_INIT LPUART7_InitPins 103 #define RTE_USART7_PIN_DEINIT LPUART7_DeinitPins 104 #define RTE_USART7_DMA_TX_CH 12 105 #define RTE_USART7_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Tx 106 #define RTE_USART7_DMA_TX_DMAMUX_BASE DMAMUX 107 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 108 #define RTE_USART7_DMA_RX_CH 13 109 #define RTE_USART7_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Rx 110 #define RTE_USART7_DMA_RX_DMAMUX_BASE DMAMUX 111 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 112 113 #define RTE_USART8_PIN_INIT LPUART8_InitPins 114 #define RTE_USART8_PIN_DEINIT LPUART8_DeinitPins 115 #define RTE_USART8_DMA_TX_CH 14 116 #define RTE_USART8_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Tx 117 #define RTE_USART8_DMA_TX_DMAMUX_BASE DMAMUX 118 #define RTE_USART8_DMA_TX_DMA_BASE DMA0 119 #define RTE_USART8_DMA_RX_CH 15 120 #define RTE_USART8_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Rx 121 #define RTE_USART8_DMA_RX_DMAMUX_BASE DMAMUX 122 #define RTE_USART8_DMA_RX_DMA_BASE DMA0 123 124 /* I2C select, I2C1 - I2C4. */ 125 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 126 * instance. */ 127 #define RTE_I2C1 1 128 #define RTE_I2C1_DMA_EN 1 129 #define RTE_I2C2 0 130 #define RTE_I2C2_DMA_EN 0 131 #define RTE_I2C3 0 132 #define RTE_I2C3_DMA_EN 0 133 #define RTE_I2C4 0 134 #define RTE_I2C4_DMA_EN 0 135 136 /* LPI2C configuration. */ 137 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 138 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 139 #define RTE_I2C1_DMA_TX_CH 0 140 #define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C1 141 #define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX 142 #define RTE_I2C1_DMA_TX_DMA_BASE DMA0 143 #define RTE_I2C1_DMA_RX_CH 1 144 #define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C1 145 #define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX 146 #define RTE_I2C1_DMA_RX_DMA_BASE DMA0 147 148 #define RTE_I2C2_PIN_INIT LPI2C2_InitPins 149 #define RTE_I2C2_PIN_DEINIT LPI2C2_DeinitPins 150 #define RTE_I2C2_DMA_TX_CH 2 151 #define RTE_I2C2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C2 152 #define RTE_I2C2_DMA_TX_DMAMUX_BASE DMAMUX 153 #define RTE_I2C2_DMA_TX_DMA_BASE DMA0 154 #define RTE_I2C2_DMA_RX_CH 3 155 #define RTE_I2C2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C2 156 #define RTE_I2C2_DMA_RX_DMAMUX_BASE DMAMUX 157 #define RTE_I2C2_DMA_RX_DMA_BASE DMA0 158 159 #define RTE_I2C3_PIN_INIT LPI2C3_InitPins 160 #define RTE_I2C3_PIN_DEINIT LPI2C3_DeinitPins 161 #define RTE_I2C3_DMA_TX_CH 4 162 #define RTE_I2C3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C3 163 #define RTE_I2C3_DMA_TX_DMAMUX_BASE DMAMUX 164 #define RTE_I2C3_DMA_TX_DMA_BASE DMA0 165 #define RTE_I2C3_DMA_RX_CH 5 166 #define RTE_I2C3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C3 167 #define RTE_I2C3_DMA_RX_DMAMUX_BASE DMAMUX 168 #define RTE_I2C3_DMA_RX_DMA_BASE DMA0 169 170 #define RTE_I2C4_PIN_INIT LPI2C4_InitPins 171 #define RTE_I2C4_PIN_DEINIT LPI2C4_DeinitPins 172 #define RTE_I2C4_DMA_TX_CH 6 173 #define RTE_I2C4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C4 174 #define RTE_I2C4_DMA_TX_DMAMUX_BASE DMAMUX 175 #define RTE_I2C4_DMA_TX_DMA_BASE DMA0 176 #define RTE_I2C4_DMA_RX_CH 7 177 #define RTE_I2C4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C4 178 #define RTE_I2C4_DMA_RX_DMAMUX_BASE DMAMUX 179 #define RTE_I2C4_DMA_RX_DMA_BASE DMA0 180 181 /*SPI select, SPI1 - SPI4.*/ 182 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 183 */ 184 #define RTE_SPI1 1 185 #define RTE_SPI1_DMA_EN 1 186 #define RTE_SPI2 0 187 #define RTE_SPI2_DMA_EN 0 188 #define RTE_SPI3 0 189 #define RTE_SPI3_DMA_EN 0 190 #define RTE_SPI4 0 191 #define RTE_SPI4_DMA_EN 0 192 193 /* SPI configuration. */ 194 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 195 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 196 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 197 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 198 #define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 199 #define RTE_SPI1_PIN_INIT SPI1_InitPins 200 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 201 #define RTE_SPI1_DMA_TX_CH 0 202 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI1Tx 203 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX 204 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 205 #define RTE_SPI1_DMA_RX_CH 1 206 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI1Rx 207 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX 208 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 209 210 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 211 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 212 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 213 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 214 #define RTE_SPI2_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 215 #define RTE_SPI2_PIN_INIT SPI2_InitPins 216 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 217 #define RTE_SPI2_DMA_TX_CH 2 218 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI2Tx 219 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX 220 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 221 #define RTE_SPI2_DMA_RX_CH 3 222 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI2Tx 223 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX 224 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 225 226 #define RTE_SPI3_PCS_TO_SCK_DELAY 1000 227 #define RTE_SPI3_SCK_TO_PSC_DELAY 1000 228 #define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000 229 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 230 #define RTE_SPI3_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 231 #define RTE_SPI3_PIN_INIT SPI3_InitPins 232 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 233 #define RTE_SPI3_DMA_TX_CH 4 234 #define RTE_SPI3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI3Tx 235 #define RTE_SPI3_DMA_TX_DMAMUX_BASE DMAMUX 236 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 237 #define RTE_SPI3_DMA_RX_CH 5 238 #define RTE_SPI3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI3Rx 239 #define RTE_SPI3_DMA_RX_DMAMUX_BASE DMAMUX 240 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 241 242 #define RTE_SPI4_PCS_TO_SCK_DELAY 1000 243 #define RTE_SPI4_SCK_TO_PSC_DELAY 1000 244 #define RTE_SPI4_BETWEEN_TRANSFER_DELAY 1000 245 #define RTE_SPI4_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 246 #define RTE_SPI4_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 247 #define RTE_SPI4_PIN_INIT SPI4_InitPins 248 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 249 #define RTE_SPI4_DMA_TX_CH 6 250 #define RTE_SPI4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI4Tx 251 #define RTE_SPI4_DMA_TX_DMAMUX_BASE DMAMUX 252 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 253 #define RTE_SPI4_DMA_RX_CH 7 254 #define RTE_SPI4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI4Rx 255 #define RTE_SPI4_DMA_RX_DMAMUX_BASE DMAMUX 256 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 257 258 /* ENET configuration. */ 259 #define RTE_ENET 1 260 #define RTE_ENET_PHY_ADDRESS 2 261 #define RTE_ENET_MII 0 262 #define RTE_ENET_RMII 1 263 264 #endif /* _RTE_DEVICE_H */ 265
