1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_IOMUXC_H_
10 #define _FSL_IOMUXC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup iomuxc_driver
16 * @{
17 */
18
19 /*! @file */
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24 /* Component ID definition, used by tools. */
25 #ifndef FSL_COMPONENT_ID
26 #define FSL_COMPONENT_ID "platform.drivers.iomuxc"
27 #endif
28
29 /*! @name Driver version */
30 /*@{*/
31 /*! @brief IOMUXC driver version 2.0.0. */
32 #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
33 /*@}*/
34
35 /*!
36 * @name Pin function ID
37 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
38 *
39 * @{
40 */
41 #define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U
42 #define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U
43 #define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U
44 #define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U
45 #define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U
46 #define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U
47
48 #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U
49 #define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U
50 #define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U
51 #define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U
52 #define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U
53 #define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U
54
55 #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU
56 #define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU
57 #define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU
58 #define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU
59 #define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU
60 #define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU
61
62 #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U
63 #define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U
64 #define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U
65 #define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U
66 #define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U
67 #define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U
68
69 #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U
70 #define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U
71 #define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U
72 #define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U
73 #define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U
74 #define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U
75
76 #define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U
77 #define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U
78 #define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U
79 #define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U
80 #define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U
81 #define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U
82
83 #define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU
84 #define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU
85 #define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU
86 #define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU
87 #define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU
88 #define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU
89
90 #define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U
91 #define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U
92 #define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U
93 #define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U
94 #define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U
95 #define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U
96
97 #define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U
98 #define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U
99 #define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U
100 #define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U
101 #define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U
102 #define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U
103
104 #define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U
105 #define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U
106 #define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U
107 #define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U
108 #define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U
109 #define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U
110 #define IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B 0x401F8038U, 0x8U, 0, 0, 0x401F8228U
111
112 #define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU
113 #define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU
114 #define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU
115 #define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU
116 #define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU
117 #define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU
118 #define IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B 0x401F803CU, 0x8U, 0, 0, 0x401F822CU
119
120 #define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U
121 #define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U
122 #define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U
123 #define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U
124 #define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U
125 #define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U
126 #define IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS 0x401F8040U, 0x8U, 0, 0, 0x401F8230U
127
128 #define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U
129 #define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U
130 #define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U
131 #define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U
132 #define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U
133 #define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U
134 #define IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK 0x401F8044U, 0x8U, 0x401F8754U, 0x0U, 0x401F8234U
135
136 #define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U
137 #define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U
138 #define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U
139 #define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U
140 #define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U
141 #define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U
142 #define IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA00 0x401F8048U, 0x8U, 0x401F8740U, 0x0U, 0x401F8238U
143
144 #define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU
145 #define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU
146 #define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU
147 #define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU
148 #define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU
149 #define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU
150 #define IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA01 0x401F804CU, 0x8U, 0x401F8744U, 0x0U, 0x401F823CU
151
152 #define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U
153 #define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U
154 #define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U
155 #define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U
156 #define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U
157 #define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U
158 #define IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA02 0x401F8050U, 0x8U, 0x401F8748U, 0x0U, 0x401F8240U
159
160 #define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U
161 #define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U
162 #define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U
163 #define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U
164 #define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U
165 #define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U
166 #define IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA03 0x401F8054U, 0x8U, 0x401F874CU, 0x0U, 0x401F8244U
167
168 #define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U
169 #define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U
170 #define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U
171 #define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U
172 #define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U
173 #define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U
174
175 #define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU
176 #define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU
177 #define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU
178 #define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU
179 #define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU
180 #define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU
181 #define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU
182
183 #define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U
184 #define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U
185 #define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U
186 #define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U
187 #define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U
188 #define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U
189 #define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U
190
191 #define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U
192 #define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U
193 #define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U
194 #define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U
195 #define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U
196 #define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U
197
198 #define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U
199 #define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U
200 #define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U
201 #define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U
202 #define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U
203 #define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U
204
205 #define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU
206 #define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU
207 #define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU
208 #define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU
209 #define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU
210 #define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU
211 #define IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B 0x401F806CU, 0x8U, 0, 0, 0x401F825CU
212
213 #define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U
214 #define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U
215 #define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U
216 #define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U
217 #define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0x401F875CU, 0x0U, 0x401F8260U
218 #define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U
219 #define IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS 0x401F8070U, 0x8U, 0x401F872CU, 0x1U, 0x401F8260U
220
221 #define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U
222 #define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U
223 #define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U
224 #define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U
225 #define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0x401F8758U, 0x0U, 0x401F8264U
226 #define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U
227 #define IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B 0x401F8074U, 0x8U, 0, 0, 0x401F8264U
228
229 #define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U
230 #define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U
231 #define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U
232 #define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U
233 #define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U
234 #define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U
235 #define IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK 0x401F8078U, 0x8U, 0x401F8750U, 0x1U, 0x401F8268U
236
237 #define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU
238 #define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU
239 #define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU
240 #define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU
241 #define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU
242 #define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU
243 #define IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA00 0x401F807CU, 0x8U, 0x401F8730U, 0x1U, 0x401F826CU
244
245 #define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U
246 #define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U
247 #define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U
248 #define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U
249 #define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U
250 #define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U
251 #define IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA01 0x401F8080U, 0x8U, 0x401F8734U, 0x1U, 0x401F8270U
252
253 #define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U
254 #define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U
255 #define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U
256 #define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U
257 #define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U
258 #define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U
259 #define IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA02 0x401F8084U, 0x8U, 0x401F8738U, 0x1U, 0x401F8274U
260
261 #define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U
262 #define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U
263 #define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U
264 #define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U
265 #define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U
266 #define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U
267 #define IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA03 0x401F8088U, 0x8U, 0x401F873CU, 0x1U, 0x401F8278U
268
269 #define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU
270 #define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU
271 #define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU
272 #define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU
273 #define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU
274
275 #define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U
276 #define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U
277 #define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U
278 #define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U
279 #define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U
280
281 #define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U
282 #define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U
283 #define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U
284 #define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U
285 #define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U
286
287 #define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U
288 #define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U
289 #define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U
290 #define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0x401F8778U, 0x0U, 0x401F8288U
291 #define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U
292
293 #define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU
294 #define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU
295 #define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU
296 #define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0x401F877CU, 0x0U, 0x401F828CU
297 #define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU
298
299 #define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U
300 #define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U
301 #define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U
302 #define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0x401F8774U, 0x0U, 0x401F8290U
303 #define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U
304 #define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U
305
306 #define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U
307 #define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U
308 #define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U
309 #define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U
310 #define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U
311 #define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U
312 #define IOMUXC_GPIO_EMC_36_FLEXCAN3_TX 0x401F80A4U, 0x9U, 0, 0, 0x401F8294U
313
314 #define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U
315 #define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U
316 #define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U
317 #define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0x401F8770U, 0x0U, 0x401F8298U
318 #define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U
319 #define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U
320 #define IOMUXC_GPIO_EMC_37_FLEXCAN3_RX 0x401F80A8U, 0x9U, 0x401F878CU, 0x0U, 0x401F8298U
321
322 #define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU
323 #define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU
324 #define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU
325 #define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0x401F8780U, 0x0U, 0x401F829CU
326 #define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU
327 #define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU
328
329 #define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U
330 #define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U
331 #define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U
332 #define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0x401F8784U, 0x0U, 0x401F82A0U
333 #define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U
334 #define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U
335 #define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U
336 #define IOMUXC_GPIO_EMC_39_SEMC_DQS4 0x401F80B0U, 0x9U, 0x401F8788U, 0x1U, 0x401F82A0U
337
338 #define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U
339 #define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0x401F8768U, 0x0U, 0x401F82A4U
340 #define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U
341 #define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U
342 #define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U
343 #define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U
344 #define IOMUXC_GPIO_EMC_40_SEMC_CLK5 0x401F80B4U, 0x9U, 0, 0, 0x401F82A4U
345
346 #define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U
347 #define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0x401F8764U, 0x0U, 0x401F82A8U
348 #define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U
349 #define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U
350 #define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U
351 #define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U
352
353 #define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU
354 #define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU
355 #define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU
356 #define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU
357 #define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU
358 #define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU
359
360 #define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U
361 #define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U
362 #define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U
363 #define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U
364 #define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U
365 #define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U
366
367 #define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U
368 #define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U
369 #define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U
370 #define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U
371 #define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U
372 #define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U
373
374 #define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U
375 #define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U
376 #define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U
377 #define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U
378 #define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U
379 #define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U
380 #define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U
381
382 #define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU
383 #define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU
384 #define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU
385 #define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU
386 #define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU
387 #define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU
388 #define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU
389
390 #define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U
391 #define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U
392 #define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U
393 #define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U
394 #define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U
395 #define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U
396 #define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0x401F876CU, 0x0U, 0x401F82D0U
397 #define IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 0x401F80E0U, 0x9U, 0x401F8788U, 0x2U, 0x401F82D0U
398
399 #define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U
400 #define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U
401 #define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U
402 #define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U
403 #define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U
404 #define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U
405 #define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U
406 #define IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX 0x401F80E4U, 0x8U, 0, 0, 0x401F82D4U
407 #define IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO 0x401F80E4U, 0x9U, 0, 0, 0x401F82D4U
408
409 #define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U
410 #define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U
411 #define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U
412 #define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U
413 #define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U
414 #define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U
415 #define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U
416 #define IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX 0x401F80E8U, 0x8U, 0x401F878CU, 0x2U, 0x401F82D8U
417 #define IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 0x401F80E8U, 0x9U, 0, 0, 0x401F82D8U
418
419 #define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU
420 #define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU
421 #define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU
422 #define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU
423 #define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU
424 #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU
425 #define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU
426 #define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU
427
428 #define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U
429 #define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0x401F8760U, 0x0U, 0x401F82E0U
430 #define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U
431 #define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U
432 #define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U
433 #define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U
434 #define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U
435 #define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U
436
437 #define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U
438 #define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U
439 #define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U
440 #define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U
441 #define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U
442 #define IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX 0x401F80F4U, 0x8U, 0, 0, 0x401F82E4U
443
444 #define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U
445 #define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U
446 #define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U
447 #define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U
448 #define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U
449 #define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U
450 #define IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX 0x401F80F8U, 0x8U, 0x401F878CU, 0x1U, 0x401F82E8U
451
452 #define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU
453 #define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU
454 #define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU
455 #define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU
456 #define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU
457 #define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU
458 #define IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 0x401F80FCU, 0x9U, 0, 0, 0x401F82ECU
459
460 #define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U
461 #define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U
462 #define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U
463 #define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U
464 #define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U
465 #define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U
466 #define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U
467 #define IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 0x401F8100U, 0x9U, 0, 0, 0x401F82F0U
468
469 #define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U
470 #define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U
471 #define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U
472 #define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U
473 #define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U
474 #define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U
475 #define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U
476 #define IOMUXC_GPIO_AD_B1_02_GPT2_CLK 0x401F8104U, 0x8U, 0x401F876CU, 0x1U, 0x401F82F4U
477 #define IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 0x401F8104U, 0x9U, 0, 0, 0x401F82F4U
478
479 #define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U
480 #define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U
481 #define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U
482 #define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U
483 #define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U
484 #define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U
485 #define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U
486 #define IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 0x401F8108U, 0x8U, 0x401F8764U, 0x1U, 0x401F82F8U
487 #define IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 0x401F8108U, 0x9U, 0, 0, 0x401F82F8U
488
489 #define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU
490 #define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU
491 #define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU
492 #define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU
493 #define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU
494 #define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU
495 #define IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 0x401F810CU, 0x8U, 0x401F8768U, 0x1U, 0x401F82FCU
496 #define IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 0x401F810CU, 0x9U, 0, 0, 0x401F82FCU
497
498 #define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U
499 #define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U
500 #define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U
501 #define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U
502 #define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U
503 #define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U
504 #define IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 0x401F8110U, 0x8U, 0, 0, 0x401F8300U
505 #define IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 0x401F8110U, 0x9U, 0, 0, 0x401F8300U
506
507 #define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U
508 #define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U
509 #define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U
510 #define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U
511 #define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U
512 #define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U
513 #define IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 0x401F8114U, 0x8U, 0, 0, 0x401F8304U
514 #define IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 0x401F8114U, 0x9U, 0, 0, 0x401F8304U
515
516 #define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U
517 #define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U
518 #define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U
519 #define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U
520 #define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U
521 #define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U
522 #define IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 0x401F8118U, 0x8U, 0, 0, 0x401F8308U
523 #define IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 0x401F8118U, 0x9U, 0, 0, 0x401F8308U
524
525 #define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU
526 #define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU
527 #define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU
528 #define IOMUXC_GPIO_B0_00_LPSPI3_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU
529 #define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU
530 #define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU
531 #define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU
532
533 #define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U
534 #define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U
535 #define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U
536 #define IOMUXC_GPIO_B0_01_LPSPI3_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U
537 #define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U
538 #define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U
539 #define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U
540
541 #define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U
542 #define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U
543 #define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U
544 #define IOMUXC_GPIO_B0_02_LPSPI3_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U
545 #define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U
546 #define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U
547 #define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U
548
549 #define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U
550 #define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U
551 #define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U
552 #define IOMUXC_GPIO_B0_03_LPSPI3_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U
553 #define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U
554 #define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U
555 #define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U
556
557 #define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU
558 #define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU
559 #define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU
560 #define IOMUXC_GPIO_B0_04_ARM_TRACE0 0x401F814CU, 0x3U, 0, 0, 0x401F833CU
561 #define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU
562 #define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU
563 #define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU
564
565 #define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U
566 #define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U
567 #define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U
568 #define IOMUXC_GPIO_B0_05_ARM_TRACE1 0x401F8150U, 0x3U, 0, 0, 0x401F8340U
569 #define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U
570 #define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U
571 #define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U
572
573 #define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U
574 #define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U
575 #define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U
576 #define IOMUXC_GPIO_B0_06_ARM_TRACE2 0x401F8154U, 0x3U, 0, 0, 0x401F8344U
577 #define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U
578 #define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U
579 #define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U
580
581 #define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U
582 #define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U
583 #define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U
584 #define IOMUXC_GPIO_B0_07_ARM_TRACE3 0x401F8158U, 0x3U, 0, 0, 0x401F8348U
585 #define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U
586 #define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U
587 #define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U
588
589 #define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU
590 #define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU
591 #define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU
592 #define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU
593 #define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU
594 #define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU
595 #define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU
596
597 #define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U
598 #define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U
599 #define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U
600 #define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U
601 #define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U
602 #define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U
603 #define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U
604
605 #define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U
606 #define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U
607 #define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U
608 #define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U
609 #define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U
610 #define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U
611 #define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U
612
613 #define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U
614 #define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U
615 #define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U
616 #define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U
617 #define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U
618 #define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U
619 #define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U
620
621 #define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU
622 #define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU
623 #define IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU
624 #define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU
625 #define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU
626 #define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU
627 #define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU
628
629 #define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U
630 #define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U
631 #define IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U
632 #define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U
633 #define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U
634 #define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U
635 #define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U
636
637 #define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U
638 #define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U
639 #define IOMUXC_GPIO_B0_14_ARM_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U
640 #define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U
641 #define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U
642 #define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U
643 #define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U
644
645 #define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U
646 #define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U
647 #define IOMUXC_GPIO_B0_15_ARM_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U
648 #define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U
649 #define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U
650 #define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U
651 #define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U
652
653 #define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU
654 #define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU
655 #define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU
656 #define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU
657 #define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU
658 #define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU
659 #define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU
660 #define IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 0x401F817CU, 0x9U, 0, 0, 0x401F836CU
661
662 #define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U
663 #define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U
664 #define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U
665 #define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U
666 #define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U
667 #define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U
668 #define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U
669 #define IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 0x401F8180U, 0x9U, 0, 0, 0x401F8370U
670
671 #define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U
672 #define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U
673 #define IOMUXC_GPIO_B1_02_LPSPI3_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U
674 #define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U
675 #define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U
676 #define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U
677 #define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U
678 #define IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 0x401F8184U, 0x9U, 0, 0, 0x401F8374U
679
680 #define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U
681 #define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U
682 #define IOMUXC_GPIO_B1_03_LPSPI3_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U
683 #define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U
684 #define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U
685 #define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U
686 #define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U
687 #define IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 0x401F8188U, 0x9U, 0, 0, 0x401F8378U
688
689 #define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU
690 #define IOMUXC_GPIO_B1_04_LPSPI3_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU
691 #define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU
692 #define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU
693 #define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU
694 #define IOMUXC_GPIO_B1_04_GPT1_CLK 0x401F818CU, 0x8U, 0x401F8760U, 0x1U, 0x401F837CU
695 #define IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 0x401F818CU, 0x9U, 0, 0, 0x401F837CU
696
697 #define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U
698 #define IOMUXC_GPIO_B1_05_LPSPI3_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U
699 #define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U
700 #define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U
701 #define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U
702 #define IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 0x401F8190U, 0x8U, 0x401F8758U, 0x1U, 0x401F8380U
703 #define IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 0x401F8190U, 0x9U, 0, 0, 0x401F8380U
704
705 #define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U
706 #define IOMUXC_GPIO_B1_06_LPSPI3_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U
707 #define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U
708 #define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U
709 #define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U
710 #define IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 0x401F8194U, 0x8U, 0x401F875CU, 0x1U, 0x401F8384U
711 #define IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 0x401F8194U, 0x9U, 0, 0, 0x401F8384U
712
713 #define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U
714 #define IOMUXC_GPIO_B1_07_LPSPI3_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U
715 #define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U
716 #define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U
717 #define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U
718 #define IOMUXC_GPIO_B1_07_GPT1_COMPARE1 0x401F8198U, 0x8U, 0, 0, 0x401F8388U
719 #define IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 0x401F8198U, 0x9U, 0, 0, 0x401F8388U
720
721 #define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU
722 #define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU
723 #define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU
724 #define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU
725 #define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU
726 #define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU
727 #define IOMUXC_GPIO_B1_08_GPT1_COMPARE2 0x401F819CU, 0x8U, 0, 0, 0x401F838CU
728 #define IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 0x401F819CU, 0x9U, 0, 0, 0x401F838CU
729
730 #define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U
731 #define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U
732 #define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U
733 #define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U
734 #define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U
735 #define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U
736 #define IOMUXC_GPIO_B1_09_GPT1_COMPARE3 0x401F81A0U, 0x8U, 0, 0, 0x401F8390U
737 #define IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 0x401F81A0U, 0x9U, 0, 0, 0x401F8390U
738
739 #define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U
740 #define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U
741 #define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U
742 #define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U
743 #define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U
744 #define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U
745 #define IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 0x401F81A4U, 0x9U, 0, 0, 0x401F8394U
746
747 #define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U
748 #define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U
749 #define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U
750 #define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U
751 #define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U
752 #define IOMUXC_GPIO_B1_11_LPSPI3_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U
753 #define IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 0x401F81A8U, 0x9U, 0, 0, 0x401F8398U
754
755 #define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU
756 #define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU
757 #define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU
758 #define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU
759 #define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU
760 #define IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 0x401F81ACU, 0x9U, 0, 0, 0x401F839CU
761
762 #define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U
763 #define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U
764 #define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U
765 #define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U
766 #define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U
767 #define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U
768 #define IOMUXC_GPIO_B1_13_SEMC_DQS4 0x401F81B0U, 0x8U, 0x401F8788U, 0x3U, 0x401F83A0U
769 #define IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 0x401F81B0U, 0x9U, 0, 0, 0x401F83A0U
770
771 #define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U
772 #define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U
773 #define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U
774 #define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U
775 #define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U
776 #define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U
777 #define IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 0x401F81B4U, 0x9U, 0, 0, 0x401F83A4U
778
779 #define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U
780 #define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U
781 #define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U
782 #define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U
783 #define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U
784 #define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U
785 #define IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 0x401F81B8U, 0x9U, 0, 0, 0x401F83A8U
786
787 #define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU
788 #define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU
789 #define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU
790 #define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU
791 #define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU
792 #define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU
793 #define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU
794 #define IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 0x401F81BCU, 0x9U, 0x401F8788U, 0x0U, 0x401F83ACU
795
796 #define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U
797 #define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U
798 #define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U
799 #define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U
800 #define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U
801 #define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U
802 #define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U
803
804 #define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U
805 #define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U
806 #define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U
807 #define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U
808 #define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U
809 #define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U
810 #define IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 0x401F81C4U, 0x9U, 0, 0, 0x401F83B4U
811
812 #define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U
813 #define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U
814 #define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U
815 #define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U
816 #define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U
817 #define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U
818 #define IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 0x401F81C8U, 0x9U, 0, 0, 0x401F83B8U
819
820 #define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU
821 #define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU
822 #define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU
823 #define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU
824 #define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU
825 #define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU
826 #define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU
827
828 #define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U
829 #define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U
830 #define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U
831 #define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U
832 #define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U
833 #define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U
834 #define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U
835
836 #define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U
837 #define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U
838 #define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U
839 #define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U
840 #define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U
841 #define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U
842 #define IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA 0x401F81D4U, 0x8U, 0x401F8778U, 0x1U, 0x401F83C4U
843
844 #define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U
845 #define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U
846 #define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U
847 #define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U
848 #define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U
849 #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U
850 #define IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA 0x401F81D8U, 0x8U, 0, 0, 0x401F83C8U
851
852 #define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU
853 #define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU
854 #define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU
855 #define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU
856 #define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU
857 #define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU
858 #define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU
859 #define IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC 0x401F81DCU, 0x8U, 0x401F8784U, 0x1U, 0x401F83CCU
860
861 #define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U
862 #define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U
863 #define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U
864 #define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U
865 #define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U
866 #define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U
867 #define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U
868 #define IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK 0x401F81E0U, 0x8U, 0x401F8780U, 0x1U, 0x401F83D0U
869
870 #define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U
871 #define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U
872 #define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U
873 #define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U
874 #define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U
875 #define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U
876 #define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U
877 #define IOMUXC_GPIO_SD_B1_04_SAI3_MCLK 0x401F81E4U, 0x8U, 0x401F8770U, 0x1U, 0x401F83D4U
878
879 #define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U
880 #define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U
881 #define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U
882 #define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U
883 #define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U
884 #define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U
885 #define IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC 0x401F81E8U, 0x8U, 0x401F877CU, 0x1U, 0x401F83D8U
886
887 #define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU
888 #define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU
889 #define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU
890 #define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU
891 #define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU
892 #define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU
893 #define IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK 0x401F81ECU, 0x8U, 0x401F8774U, 0x1U, 0x401F83DCU
894
895 #define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U
896 #define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U
897 #define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U
898 #define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U
899 #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U
900 #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U
901
902 #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U
903 #define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U
904 #define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U
905 #define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U
906 #define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U
907 #define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U
908 #define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U
909
910 #define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U
911 #define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U
912 #define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U
913 #define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U
914 #define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U
915 #define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U
916
917 #define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU
918 #define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU
919 #define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU
920 #define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU
921 #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU
922 #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU
923
924 #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U
925 #define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U
926 #define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U
927 #define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U
928 #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U
929 #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U
930
931 #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
932 #define IOMUXC_SNVS_WAKEUP_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U
933
934 #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU
935 #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU
936
937 #define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U
938 #define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U
939
940 #define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU
941
942 #define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U
943
944 #define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U
945
946 /*@}*/
947
948 #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
949 #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
950
951 typedef enum _iomuxc_gpr_mode
952 {
953 kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
954 kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK,
955 kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK,
956 kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
957 kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK,
958 kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
959 kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
960 kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK,
961 kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
962 } iomuxc_gpr_mode_t;
963
964 typedef enum _iomuxc_gpr_saimclk
965 {
966 kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
967 kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
968 kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
969 kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
970 kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
971 } iomuxc_gpr_saimclk_t;
972
973 typedef enum _iomuxc_mqs_pwm_oversample_rate
974 {
975 kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */
976 kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */
977 } iomuxc_mqs_pwm_oversample_rate_t;
978
979 #if defined(__cplusplus)
980 extern "C" {
981 #endif /*_cplusplus */
982
983 /*! @name Configuration */
984 /*@{*/
985
986 /*!
987 * @brief Sets the IOMUXC pin mux mode.
988 * @note The first five parameters can be filled with the pin function ID macros.
989 *
990 * This is an example to set the PTA6 as the lpuart0_tx:
991 * @code
992 * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
993 * @endcode
994 *
995 * This is an example to set the PTA0 as GPIOA0:
996 * @code
997 * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
998 * @endcode
999 *
1000 * @param muxRegister The pin mux register.
1001 * @param muxMode The pin mux mode.
1002 * @param inputRegister The select input register.
1003 * @param inputDaisy The input daisy.
1004 * @param configRegister The config register.
1005 * @param inputOnfield Software input on field.
1006 */
IOMUXC_SetPinMux(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t inputOnfield)1007 static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
1008 uint32_t muxMode,
1009 uint32_t inputRegister,
1010 uint32_t inputDaisy,
1011 uint32_t configRegister,
1012 uint32_t inputOnfield)
1013 {
1014 *((volatile uint32_t *)muxRegister) =
1015 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
1016
1017 if (inputRegister != 0UL)
1018 {
1019 *((volatile uint32_t *)inputRegister) = inputDaisy;
1020 }
1021 }
1022
1023 /*!
1024 * @brief Sets the IOMUXC pin configuration.
1025 * @note The previous five parameters can be filled with the pin function ID macros.
1026 *
1027 * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
1028 * @code
1029 * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
1030 * @endcode
1031 *
1032 * @param muxRegister The pin mux register.
1033 * @param muxMode The pin mux mode.
1034 * @param inputRegister The select input register.
1035 * @param inputDaisy The input daisy.
1036 * @param configRegister The config register.
1037 * @param configValue The pin config value.
1038 */
IOMUXC_SetPinConfig(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t configValue)1039 static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
1040 uint32_t muxMode,
1041 uint32_t inputRegister,
1042 uint32_t inputDaisy,
1043 uint32_t configRegister,
1044 uint32_t configValue)
1045 {
1046 if (configRegister != 0UL)
1047 {
1048 *((volatile uint32_t *)configRegister) = configValue;
1049 }
1050 }
1051
1052 /*!
1053 * @brief Sets IOMUXC general configuration for some mode.
1054 *
1055 * @param base The IOMUXC GPR base address.
1056 * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode"
1057 * @param enable True enable false disable.
1058 */
IOMUXC_EnableMode(IOMUXC_GPR_Type * base,uint32_t mode,bool enable)1059 static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
1060 {
1061 mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
1062 IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
1063 IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
1064
1065 if (enable)
1066 {
1067 base->GPR1 |= mode;
1068 }
1069 else
1070 {
1071 base->GPR1 &= ~mode;
1072 }
1073 }
1074
1075 /*!
1076 * @brief Sets IOMUXC general configuration for SAI MCLK selection.
1077 *
1078 * @param base The IOMUXC GPR base address.
1079 * @param mclk The SAI MCLK.
1080 * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM.
1081 */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type * base,iomuxc_gpr_saimclk_t mclk,uint8_t clkSrc)1082 static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
1083 {
1084 uint32_t gpr;
1085
1086 if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
1087 {
1088 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
1089 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr;
1090 }
1091 else
1092 {
1093 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
1094 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr;
1095 }
1096 }
1097
1098 /*!
1099 * @brief Enters or exit MQS software reset.
1100 *
1101 * @param base The IOMUXC GPR base address.
1102 * @param enable Enter or exit MQS software reset.
1103 */
IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type * base,bool enable)1104 static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable)
1105 {
1106 if (enable)
1107 {
1108 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
1109 }
1110 else
1111 {
1112 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
1113 }
1114 }
1115
1116 /*!
1117 * @brief Enables or disables MQS.
1118 *
1119 * @param base The IOMUXC GPR base address.
1120 * @param enable Enable or disable the MQS.
1121 */
IOMUXC_MQSEnable(IOMUXC_GPR_Type * base,bool enable)1122 static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
1123 {
1124 if (enable)
1125 {
1126 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
1127 }
1128 else
1129 {
1130 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
1131 }
1132 }
1133
1134 /*!
1135 * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
1136 *
1137 * @param base The IOMUXC GPR base address.
1138 * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
1139 * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.
1140 */
1141
IOMUXC_MQSConfig(IOMUXC_GPR_Type * base,iomuxc_mqs_pwm_oversample_rate_t rate,uint8_t divider)1142 static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
1143 {
1144 uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
1145 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
1146 }
1147
1148 /*@}*/
1149
1150 #if defined(__cplusplus)
1151 }
1152 #endif /*_cplusplus */
1153
1154 /*! @}*/
1155
1156 #endif /* _FSL_IOMUXC_H_ */
1157
