1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016, NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_RESET_H_ 10 #define _FSL_RESET_H_ 11 12 #include <assert.h> 13 #include <stdbool.h> 14 #include <stdint.h> 15 #include <string.h> 16 #include "fsl_device_registers.h" 17 18 /*! 19 * @addtogroup reset 20 * @{ 21 */ 22 23 /******************************************************************************* 24 * Definitions 25 ******************************************************************************/ 26 27 /*! @name Driver version */ 28 /*@{*/ 29 /*! @brief reset driver version 2.0.0. */ 30 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 31 /*@}*/ 32 33 /*! 34 * @brief Enumeration for peripheral reset control bits 35 * 36 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers 37 */ 38 typedef enum _SYSCON_RSTn 39 { 40 kROM_RST_SHIFT_RSTn = (0 | (1U)), /**< ROM reset control .*/ 41 kSRAM_CTRL1_RST_SHIFT_RSTn = (0 | (3U)), /**< SRAM Controller 1 reset control .*/ 42 kSRAM_CTRL2_RST_SHIFT_RSTn = (0 | (4U)), /**< SRAM Controller 2 reset control .*/ 43 kSRAM_CTRL3_RST_SHIFT_RSTn = (0 | (5U)), /**< SRAM Controller 3 reset control .*/ 44 kSRAM_CTRL4_RST_SHIFT_RSTn = (0 | (6U)), /**< SRAM Controller 4 reset control .*/ 45 kFLASH_RST_SHIFT_RSTn = (0 | (7U)), /**< FLASH reset control .*/ 46 kFMC_RST_SHIFT_RSTn = (0 | (8U)), /**< FMC reset control .*/ 47 kFLEXSPI_RST_SHIFT_RSTn = (0 | (10U)), /**< FLEXSPI reset control .*/ 48 kMUX_RST_SHIFT_RSTn = (0 | (11U)), /**< MUX reset control .*/ 49 kIOCON_RST_SHIFT_RSTn = (0 | (13U)), /**< IOCON reset control .*/ 50 kGPIO0_RST_SHIFT_RSTn = (0 | (14U)), /**< GPIO0 reset control .*/ 51 kGPIO1_RST_SHIFT_RSTn = (0 | (15U)), /**< GPIO1 reset control .*/ 52 kGPIO2_RST_SHIFT_RSTn = (0 | (16U)), /**< GPIO2 reset control .*/ 53 kGPIO3_RST_SHIFT_RSTn = (0 | (17U)), /**< GPIO3 reset control .*/ 54 kPINT_RST_SHIFT_RSTn = (0 | (18U)), /**< PINT reset control .*/ 55 kGINT_RST_SHIFT_RSTn = (0 | (19U)), /**< GINT reset control .*/ 56 kDMA0_RST_SHIFT_RSTn = (0 | (20U)), /**< DMA0 reset control .*/ 57 kCRC_RST_SHIFT_RSTn = (0 | (21U)), /**< CRC reset control .*/ 58 kWWDT_RST_SHIFT_RSTn = (0 | (22U)), /**< WWDT reset control .*/ 59 kRTC_RST_SHIFT_RSTn = (0 | (23U)), /**< RTC reset control .*/ 60 kMAILBOX_RST_SHIFT_RSTn = (0 | (26U)), /**< MAILBOX reset control .*/ 61 kADC0_RST_SHIFT_RSTn = (0 | (27U)), /**< ADC0 reset control .*/ 62 kADC1_RST_SHIFT_RSTn = (0 | (28U)), /**< ADC1 reset control .*/ 63 kDAC0_RST_SHIFT_RSTn = (0 | (29U)), /**< DAC0 reset control .*/ 64 65 kMRT_RST_SHIFT_RSTn = (0x10000 | (0U)), /**< MRT reset control .*/ 66 kOSTIMER_RST_SHIFT_RSTn = (0x10000 | (1U)), /**< OSTIMER reset control .*/ 67 kSCT_RST_SHIFT_RSTn = (0x10000 | (2U)), /**< SCT reset control .*/ 68 kMCAN_RST_SHIFT_RSTn = (0x10000 | (7U)), /**< MCAN reset control .*/ 69 kUTICK_RST_SHIFT_RSTn = (0x10000 | (10U)), /**< UTICK reset control .*/ 70 kFC0_RST_SHIFT_RSTn = (0x10000 | (11U)), /**< FC0 reset control .*/ 71 kFC1_RST_SHIFT_RSTn = (0x10000 | (12U)), /**< FC1 reset control .*/ 72 kFC2_RST_SHIFT_RSTn = (0x10000 | (13U)), /**< FC2 reset control .*/ 73 kFC3_RST_SHIFT_RSTn = (0x10000 | (14U)), /**< FC3 reset control .*/ 74 kFC4_RST_SHIFT_RSTn = (0x10000 | (15U)), /**< FC4 reset control .*/ 75 kFC5_RST_SHIFT_RSTn = (0x10000 | (16U)), /**< FC5 reset control .*/ 76 kFC6_RST_SHIFT_RSTn = (0x10000 | (17U)), /**< FC6 reset control .*/ 77 kFC7_RST_SHIFT_RSTn = (0x10000 | (18U)), /**< FC7 reset control .*/ 78 kDMIC_RST_SHIFT_RSTn = (0x10000 | (19U)), /**< DMIC reset control .*/ 79 kCTIMER2_RST_SHIFT_RSTn = (0x10000 | (22U)), /**< TIMER2 reset control .*/ 80 kUSB0_DEV_RST_SHIFT_RSTn = (0x10000 | (25U)), /**< USB0_DEV reset control .*/ 81 kCTIMER0_RST_SHIFT_RSTn = (0x10000 | (26U)), /**< TIMER0 reset control .*/ 82 kCTIMER1_RST_SHIFT_RSTn = (0x10000 | (27U)), /**< TIMER1 reset control .*/ 83 84 kDMA1_RST_SHIFT_RSTn = (0x20000 | (1U)), /**< DMA1 reset control .*/ 85 kCMP_RST_SHIFT_RSTn = (0x20000 | (2U)), /**< CMP reset control .*/ 86 kFREQME_RST_SHIFT_RSTn = (0x20000 | (8U)), /**< FREQME reset control .*/ 87 kCDOG_RST_SHIFT_RSTn = (0x20000 | (11U)), /**< Code Watchdog reset control */ 88 kRNG_RST_SHIFT_RSTn = (0x20000 | (13U)), /**< RNG reset control .*/ 89 kSYSCTL_RST_SHIFT_RSTn = (0x20000 | (15U)), /**< SYSCTL reset control .*/ 90 kUSB0HMR_RST_SHIFT_RSTn = (0x20000 | (16U)), /**< USB0HMR reset control */ 91 kUSB0HSL_RST_SHIFT_RSTn = (0x20000 | (17U)), /**< USB0HSL reset control */ 92 kCSS_RST_SHIFT_RSTn = (0x20000 | (18U)), /**< CSS reset control .*/ 93 kPOWERQUAD_RST_SHIFT_RSTn = (0x20000 | (19U)), /**< PowerQuad reset control .*/ 94 kCTIMER3_RST_SHIFT_RSTn = (0x20000 | (21U)), /**< TIMER3 reset control .*/ 95 kCTIMER4_RST_SHIFT_RSTn = (0x20000 | (22U)), /**< TIMER4 reset control .*/ 96 kPUF_RST_SHIFT_RSTn = (0x20000 | (23U)), /**< PUF reset control */ 97 kPKC_RST_SHIFT_RSTn = (0x20000 | (24U)), /**< PKC reset control .*/ 98 kANACTRL_RST_SHIFT_RSTn = (0x20000 | (27U)), /**< ANACTRL reset control .*/ 99 kHSLSPI_RST_SHIFT_RSTn = (0x20000 | (28U)), /**< HS LSPI reset control */ 100 kGPIOSEC_RST_SHIFT_RSTn = (0x20000 | (29U)), /**< GPIO_SEC reset control .*/ 101 kGPIOSECINT_RST_SHIFT_RSTn = (0x20000 | (30U)), /**< GPIO secure int reset control .*/ 102 103 kI3C0_RST_SHIFT_RSTn = (0x30000 | (0U)), /**< I3C0 reset control .*/ 104 kENC0_RST_SHIFT_RSTn = (0x30000 | (3U)), /**< ENC0 reset control .*/ 105 kENC1_RST_SHIFT_RSTn = (0x30000 | (4U)), /**< ENC1 reset control .*/ 106 kPWM0_RST_SHIFT_RSTn = (0x30000 | (5U)), /**< PWM0 reset control .*/ 107 kPWM1_RST_SHIFT_RSTn = (0x30000 | (6U)), /**< PWM1 reset control .*/ 108 kAOI0_RST_SHIFT_RSTn = (0x30000 | (7U)), /**< AOI0 reset control .*/ 109 kAOI1_RST_SHIFT_RSTn = (0x30000 | (8U)), /**< AOI1 reset control .*/ 110 kFTM0_RST_SHIFT_RSTn = (0x30000 | (9U)), /**< FTM0 reset control .*/ 111 kDAC1_RST_SHIFT_RSTn = (0x30000 | (10U)), /**< DAC1 reset control .*/ 112 kDAC2_RST_SHIFT_RSTn = (0x30000 | (11U)), /**< DAC2 reset control .*/ 113 kOPAMP0_RST_SHIFT_RSTn = (0x30000 | (12U)), /**< OPAMP0 reset control .*/ 114 kOPAMP1_RST_SHIFT_RSTn = (0x30000 | (13U)), /**< OPAMP1 reset control .*/ 115 kOPAMP2_RST_SHIFT_RSTn = (0x30000 | (14U)), /**< OPAMP2 reset control .*/ 116 kHSCMP0_RST_SHIFT_RSTn = (0x30000 | (15U)), /**< HSCMP0 reset control .*/ 117 kHSCMP1_RST_SHIFT_RSTn = (0x30000 | (16U)), /**< HSCMP1 reset control .*/ 118 kHSCMP2_RST_SHIFT_RSTn = (0x30000 | (17U)), /**< HSCMP2 reset control .*/ 119 kVREF_RST_SHIFT_RSTn = (0x30000 | (18U)), /**< VREF reset control .*/ 120 } SYSCON_RSTn_t; 121 122 /** Array initializers with peripheral reset bits **/ 123 #define ADC_RSTS \ 124 { \ 125 kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ 126 } /* Reset bits for ADC peripheral */ 127 #define MCAN_RSTS \ 128 { \ 129 kMCAN_RST_SHIFT_RSTn \ 130 } /* Reset bits for CAN peripheral */ 131 #define CRC_RSTS \ 132 { \ 133 kCRC_RST_SHIFT_RSTn \ 134 } /* Reset bits for CRC peripheral */ 135 #define CTIMER_RSTS \ 136 { \ 137 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ 138 kCTIMER4_RST_SHIFT_RSTn \ 139 } /* Reset bits for CTIMER peripheral */ 140 #define DMA_RSTS_N \ 141 { \ 142 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ 143 } /* Reset bits for DMA peripheral */ 144 145 #define FLEXCOMM_RSTS \ 146 { \ 147 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ 148 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ 149 } /* Reset bits for FLEXCOMM peripheral */ 150 #define GINT_RSTS \ 151 { \ 152 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ 153 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ 154 #define GPIO_RSTS_N \ 155 { \ 156 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn \ 157 } /* Reset bits for GPIO peripheral */ 158 #define INPUTMUX_RSTS \ 159 { \ 160 kMUX_RST_SHIFT_RSTn \ 161 } /* Reset bits for INPUTMUX peripheral */ 162 #define IOCON_RSTS \ 163 { \ 164 kIOCON_RST_SHIFT_RSTn \ 165 } /* Reset bits for IOCON peripheral */ 166 #define FLASH_RSTS \ 167 { \ 168 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ 169 } /* Reset bits for Flash peripheral */ 170 #define MRT_RSTS \ 171 { \ 172 kMRT_RST_SHIFT_RSTn \ 173 } /* Reset bits for MRT peripheral */ 174 #define PINT_RSTS \ 175 { \ 176 kPINT_RST_SHIFT_RSTn, kGPIO_SEC_INT_RST_SHIFT_RSTn \ 177 } /* Reset bits for PINT peripheral */ 178 #define CDOG_RSTS \ 179 { \ 180 kCDOG_RST_SHIFT_RSTn \ 181 } /* Reset bits for CDOG peripheral */ 182 #define RNG_RSTS \ 183 { \ 184 kRNG_RST_SHIFT_RSTn \ 185 } /* Reset bits for RNG peripheral */ 186 #define SCT_RSTS \ 187 { \ 188 kSCT_RST_SHIFT_RSTn \ 189 } /* Reset bits for SCT peripheral */ 190 #define USB0D_RST \ 191 { \ 192 kUSB0_DEV_RST_SHIFT_RSTn \ 193 } /* Reset bits for USB0D peripheral */ 194 #define USB0HMR_RST \ 195 { \ 196 kUSB0HMR_RST_SHIFT_RSTn \ 197 } /* Reset bits for USB0HMR peripheral */ 198 #define USB0HSL_RST \ 199 { \ 200 kUSB0HSL_RST_SHIFT_RSTn \ 201 } /* Reset bits for USB0HSL peripheral */ 202 #define UTICK_RSTS \ 203 { \ 204 kUTICK_RST_SHIFT_RSTn \ 205 } /* Reset bits for UTICK peripheral */ 206 #define WWDT_RSTS \ 207 { \ 208 kWWDT_RST_SHIFT_RSTn \ 209 } /* Reset bits for WWDT peripheral */ 210 #define OSTIMER_RSTS \ 211 { \ 212 kOSTIMER_RST_SHIFT_RSTn \ 213 } /* Reset bits for OSTIMER peripheral */ 214 #define I3C_RSTS \ 215 { \ 216 kI3C0_RST_SHIFT_RSTn \ 217 } /* Reset bits for I3C peripheral */ 218 #define ENC_RSTS \ 219 { \ 220 kENC0_RST_SHIFT_RSTn, kENC1_RST_SHIFT_RSTn \ 221 } /* Reset bits for ENC peripheral */ 222 #define PWM_RSTS \ 223 { \ 224 kPWM0_RST_SHIFT_RSTn, kPWM1_RST_SHIFT_RSTn \ 225 } /* Reset bits for PWM peripheral */ 226 #define AOI_RSTS \ 227 { \ 228 kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn \ 229 } /* Reset bits for AOI peripheral */ 230 #define DAC_RSTS \ 231 { \ 232 kDAC0_RST_SHIFT_RSTn, kDAC1_RST_SHIFT_RSTn \ 233 } /* Reset bits for DAC peripheral */ 234 #define OPAMP_RSTS \ 235 { \ 236 kOPAMP0_RST_SHIFT_RSTn, kOPAMP1_RST_SHIFT_RSTn, kOPAMP2_RST_SHIFT_RSTn \ 237 } /* Reset bits for OPAMP peripheral */ 238 #define HSCMP_RSTS \ 239 { \ 240 kHSCMP0_RST_SHIFT_RSTn, kHSCMP1_RST_SHIFT_RSTn, kHSCMP2_RST_SHIFT_RSTn \ 241 } /* Reset bits for HSCMP peripheral */ 242 #define POWERQUAD_RSTS \ 243 { \ 244 kPOWERQUAD_RST_SHIFT_RSTn \ 245 } /* Reset bits for Powerquad peripheral */ 246 typedef SYSCON_RSTn_t reset_ip_name_t; 247 248 /******************************************************************************* 249 * API 250 ******************************************************************************/ 251 #if defined(__cplusplus) 252 extern "C" { 253 #endif 254 255 /*! 256 * @brief Assert reset to peripheral. 257 * 258 * Asserts reset signal to specified peripheral module. 259 * 260 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register 261 * and reset bit position in the reset register. 262 */ 263 void RESET_SetPeripheralReset(reset_ip_name_t peripheral); 264 265 /*! 266 * @brief Clear reset to peripheral. 267 * 268 * Clears reset signal to specified peripheral module, allows it to operate. 269 * 270 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register 271 * and reset bit position in the reset register. 272 */ 273 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); 274 275 /*! 276 * @brief Reset peripheral module. 277 * 278 * Reset peripheral module. 279 * 280 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register 281 * and reset bit position in the reset register. 282 */ 283 void RESET_PeripheralReset(reset_ip_name_t peripheral); 284 285 #if defined(__cplusplus) 286 } 287 #endif 288 289 /*! @} */ 290 291 #endif /* _FSL_RESET_H_ */ 292
