1 /*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_POWER_H_
8 #define _FSL_POWER_H_
9
10 #include "fsl_common.h"
11 #include "fsl_device_registers.h"
12 #include <stdint.h>
13
14 /*!
15 * @addtogroup power
16 * @{
17 */
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief power driver version 2.3.2. */
25 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
26 /*@}*/
27
28 /* Power mode configuration API parameter */
29 typedef enum _power_mode_config
30 {
31 kPmu_Sleep = 0U,
32 kPmu_Deep_Sleep = 1U,
33 kPmu_PowerDown = 2U,
34 kPmu_Deep_PowerDown = 3U,
35 } power_mode_cfg_t;
36
37 /**
38 * @brief Analog components power modes control during low power modes
39 */
40 typedef enum pd_bits
41 {
42 kPDRUNCFG_PD_DCDC = (1UL << 0),
43 kPDRUNCFG_PD_BIAS = (1UL << 1),
44 kPDRUNCFG_PD_BODCORE = (1UL << 2),
45 kPDRUNCFG_PD_BODVBAT = (1UL << 3),
46 kPDRUNCFG_PD_FRO1M = (1UL << 4),
47 kPDRUNCFG_PD_FRO192M = (1UL << 5),
48 kPDRUNCFG_PD_FRO32K = (1UL << 6),
49 kPDRUNCFG_PD_XTAL32K = (1UL << 7),
50 kPDRUNCFG_PD_XTAL32M = (1UL << 8),
51 kPDRUNCFG_PD_PLL0 = (1UL << 9),
52 kPDRUNCFG_PD_PLL1 = (1UL << 10),
53 kPDRUNCFG_PD_COMP = (1UL << 13),
54 kPDRUNCFG_PD_TEMPSENS = (1UL << 14),
55 kPDRUNCFG_PD_GPADC = (1UL << 15),
56 kPDRUNCFG_PD_LDOMEM = (1UL << 16),
57 kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17),
58 kPDRUNCFG_PD_LDOGPADC = (1UL << 19),
59 kPDRUNCFG_PD_LDOXO32M = (1UL << 20),
60 kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
61 kPDRUNCFG_PD_RNG = (1UL << 22),
62 kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
63 kPDRUNCFG_PD_ROM = (1UL << 24),
64 /*
65 This enum member has no practical meaning,it is used to avoid MISRA issue,
66 user should not trying to use it.
67 */
68 kPDRUNCFG_ForceUnsigned = 0x80000000U,
69 } pd_bit_t;
70
71 /**
72 * @brief BOD VBAT level
73 */
74 typedef enum _power_bod_vbat_level
75 {
76 kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
77 kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */
78 kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */
79 kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */
80 kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */
81 kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */
82 kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */
83 kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */
84 kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */
85 kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */
86 kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */
87 kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */
88 kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */
89 kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */
90 kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */
91 kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */
92 kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */
93 kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */
94 kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */
95 kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */
96 kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */
97 kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */
98 kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */
99 kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */
100 kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */
101 kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
102 } power_bod_vbat_level_t;
103
104 /**
105 * @brief BOD Hysteresis control
106 */
107 typedef enum _power_bod_hyst
108 {
109 kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
110 kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
111 kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
112 kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
113 } power_bod_hyst_t;
114 /**
115 * @brief BOD core level
116 */
117 typedef enum _power_bod_core_level
118 {
119 kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
120 kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */
121 kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */
122 kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */
123 kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */
124 kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */
125 kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */
126 kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
127 } power_bod_core_level_t;
128
129 /**
130 * @brief Device Reset Causes
131 */
132 typedef enum _power_device_reset_cause
133 {
134 kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */
135 kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */
136 kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */
137 kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */
138 kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */
139 kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */
140 kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */
141 /* Reset causes in DEEP-POWER-DOWN low power mode */
142 kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */
143 kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */
144 kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */
145 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish
146 which of these 2 events occured first) */
147 kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to
148 distinguish which of these 2 events occured first) */
149 kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to
150 distinguish which of these 2 events occured first) */
151 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish
152 which of these 3 events occured first) */
153 /* Miscallenous */
154 kRESET_CAUSE_NOT_RELEVANT =
155 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */
156 kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an
157 application point of view. */
158 } power_device_reset_cause_t;
159
160 /**
161 * @brief Device Boot Modes
162 */
163 typedef enum _power_device_boot_mode
164 {
165 kBOOT_MODE_POWER_UP =
166 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */
167 kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */
168 kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */
169 kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */
170 } power_device_boot_mode_t;
171
172 /**
173 * @brief SRAM instances retention control during low power modes
174 */
175 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \
176 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */
177 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \
178 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */
179 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \
180 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */
181 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \
182 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */
183 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \
184 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */
185 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \
186 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */
187 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \
188 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */
189 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM3 \
190 (1UL << 14) /*!< Enable SRAM3 retention when entering in Low power modes */
191
192 /**
193 * @brief Low Power Modes Wake up sources
194 */
195 #define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
196 #define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
197 #define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
198 #define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
199 #define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
200 #define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
201 #define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
202 #define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
203 #define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
204 #define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
205 #define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
206 #define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
207 #define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
208 #define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
209 #define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
210 #define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
211 #define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
212 #define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
213 #define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
214 #define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
215 #define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
216 #define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
217 #define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
218 // reserved (1ULL << 23)
219 #define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
220 // reserved (1ULL << 25)
221 // reserved (1ULL << 26)
222 // reserved (1ULL << 27)
223 // reserved (1ULL << 28)
224 #define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
225 // reserved (1ULL << 30)
226 // reserved (1ULL << 31)
227 #define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
228 #define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
229 #define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
230 #define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
231 #define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
232 #define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
233 #define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
234 // reserved (1ULL << 39)
235 // reserved (1ULL << 40)
236 // reserved (1ULL << 41)
237 // reserved (1ULL << 42)
238 #define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */
239 #define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */
240 // reserved (1ULL << 45)
241 // reserved (1ULL << 46)
242 // reserved (1ULL << 47)
243 // reserved (1ULL << 48) ] */
244 #define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
245 #define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
246 #define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
247 #define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
248 #define WAKEUP_SEC_VIO (1ULL << 53)
249 #define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
250 #define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
251 #define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */
252 // reserved (1ULL << 57)
253 #define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
254 #define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
255 //#define CDOG (1ULL << 60) !< [SLEEP, ]
256 // reserved (1ULL << 61)
257 // reserved (1ULL << 62)
258 #define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */
259
260 /**
261 * @brief Sleep Postpone
262 */
263 #define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */
264 #define LOWPOWER_HWWAKE_PERIPHERALS \
265 (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \
266 peripheral clocking to wake up temporarily while the related status is asserted */
267 #define LOWPOWER_HWWAKE_SDMA0 \
268 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \
269 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
270 #define LOWPOWER_HWWAKE_SDMA1 \
271 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \
272 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
273 #define LOWPOWER_HWWAKE_ENABLE_FRO192M \
274 (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \
275 LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */
276
277 #define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
278 #define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
279 /**
280 * @brief Wake up I/O sources
281 */
282 #define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
283 #define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
284 #define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
285 #define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
286
287 #define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
288 #define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
289 #define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
290 #define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
291
292 #define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */
293 #define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */
294 #define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */
295 #define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */
296
297 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */
298 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */
299 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */
300 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */
301
302 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */
303 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */
304 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */
305 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */
306
307 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \
308 (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */
309 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \
310 (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */
311 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \
312 (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */
313 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \
314 (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */
315
316 #define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */
317 #define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
318
319 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \
320 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */
321 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \
322 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */
323 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \
324 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */
325 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \
326 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */
327 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \
328 (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */
329 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \
330 (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */
331 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \
332 (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */
333 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
334 (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
335
336 #define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \
337 (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/
338 #define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \
339 (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */
340 #define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \
341 (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */
342 #define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \
343 (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */
344 #define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \
345 (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \
346 disable/enable mask, 0: disable, 1: enable */
347 #define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \
348 (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \
349 disable/enable mask, 0: disable, 1: enable */
350 #define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \
351 (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \
352 disable/enable mask, 0: disable, 1: enable */
353 #define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \
354 (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \
355 disable/enable mask, 0: disable, 1: enable */
356
357 #ifdef __cplusplus
358 extern "C" {
359 #endif
360 /*******************************************************************************
361 * API
362 ******************************************************************************/
363
364 /*!
365 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
366 *
367 * @param en peripheral for which to enable the PDRUNCFG bit
368 * @return none
369 */
POWER_EnablePD(pd_bit_t en)370 static inline void POWER_EnablePD(pd_bit_t en)
371 {
372 /* PDRUNCFGSET */
373 PMC->PDRUNCFGSET0 = (uint32_t)en;
374 }
375
376 /*!
377 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
378 *
379 * @param en peripheral for which to disable the PDRUNCFG bit
380 * @return none
381 */
POWER_DisablePD(pd_bit_t en)382 static inline void POWER_DisablePD(pd_bit_t en)
383 {
384 /* PDRUNCFGCLR */
385 PMC->PDRUNCFGCLR0 = (uint32_t)en;
386 }
387
388 /*!
389 * @brief set BOD VBAT level.
390 *
391 * @param level BOD detect level
392 * @param hyst BoD Hysteresis control
393 * @param enBodVbatReset VBAT brown out detect reset
394 */
395 void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset);
396
397 #if defined(PMC_BODCORE_TRIGLVL_MASK)
398 /*!
399 * @brief set BOD core level.
400 *
401 * @param level BOD detect level
402 * @param hyst BoD Hysteresis control
403 * @param enBodCoreReset core brown out detect reset
404 */
405 void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset);
406 #endif
407
408 /*!
409 * @brief API to enable deep sleep bit in the ARM Core.
410 *
411 * @return none
412 */
POWER_EnableDeepSleep(void)413 static inline void POWER_EnableDeepSleep(void)
414 {
415 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
416 }
417
418 /*!
419 * @brief API to disable deep sleep bit in the ARM Core.
420 *
421 * @return none
422 */
POWER_DisableDeepSleep(void)423 static inline void POWER_DisableDeepSleep(void)
424 {
425 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
426 }
427
428 /**
429 * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event
430 * This MUST BE EXECUTED outside the Flash:
431 * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
432 * preferable to have all functions defined in this file implemented in ROM.
433 *
434 * @return Nothing
435 */
436 void POWER_CycleCpuAndFlash(void);
437
438 /**
439 * @brief Configures and enters in DEEP-SLEEP low power mode
440 * @param exclude_from_pd:
441 * @param sram_retention_ctrl:
442 * @param wakeup_interrupts:
443 * @param hardware_wake_ctrl:
444
445 * @return Nothing
446 *
447 * !!! IMPORTANT NOTES :
448 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
449 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back
450 in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
451 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function
452 will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
453 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full
454 chip reset) reset)
455 */
456 void POWER_EnterDeepSleep(uint32_t exclude_from_pd,
457 uint32_t sram_retention_ctrl,
458 uint64_t wakeup_interrupts,
459 uint32_t hardware_wake_ctrl);
460
461 /**
462 * @brief Configures and enters in POWERDOWN low power mode
463 * @param exclude_from_pd:
464 * @param sram_retention_ctrl:
465 * @param wakeup_interrupts:
466 * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are
467 RESERVED.
468
469 * @return Nothing
470 *
471 * !!! IMPORTANT NOTES :
472 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
473 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back
474 in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
475 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function
476 will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
477 * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance
478 containing the stack used to call this function WILL BE preserved during low power (via parameter
479 "sram_retention_ctrl")
480 * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full
481 chip reset) reset)
482 */
483
484 void POWER_EnterPowerDown(uint32_t exclude_from_pd,
485 uint32_t sram_retention_ctrl,
486 uint64_t wakeup_interrupts,
487 uint32_t cpu_retention_ctrl);
488
489 /**
490 * @brief Configures and enters in DEEPPOWERDOWN low power mode
491 * @param exclude_from_pd:
492 * @param sram_retention_ctrl:
493 * @param wakeup_interrupts:
494 * @param wakeup_io_ctrl:
495
496 * @return Nothing
497 *
498 * !!! IMPORTANT NOTES :
499 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
500 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back
501 if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
502 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function
503 will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
504 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full
505 chip reset)
506 */
507 void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd,
508 uint32_t sram_retention_ctrl,
509 uint64_t wakeup_interrupts,
510 uint32_t wakeup_io_ctrl);
511
512 /**
513 * @brief Configures and enters in SLEEP low power mode
514 *
515 * @return Nothing
516 */
517 void POWER_EnterSleep(void);
518
519 /*!
520 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
521 *
522 * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate,
523 * note that the voltage and flash wait states should be set before changing frequency
524 * @return none
525 */
526 void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
527
528 /**
529 * @brief Sets board-specific trim values for 16MHz XTAL
530 * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
531 * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes
532 * 600, 1.2pF becomes 120
533 * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes
534 * 600, 1.2pF becomes 120
535 * @return none
536 * @note Following default Values can be used:
537 * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
538 * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20
539 * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
540 */
541 extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100,
542 int32_t pi32_16MfXtalPPcbParCappF_x100,
543 int32_t pi32_16MfXtalNPcbParCappF_x100);
544 /**
545 * @brief Sets board-specific trim values for 32kHz XTAL
546 * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
547 * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes
548 600, 1.2pF becomes 120
549 * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes
550 600, 1.2pF becomes 120
551
552 * @return none
553 * @note Following default Values can be used:
554 * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
555 * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40
556 * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
557 */
558 extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
559 int32_t pi32_32kfXtalPPcbParCappF_x100,
560 int32_t pi32_32kfXtalNPcbParCappF_x100);
561 /**
562 * @brief Enables and sets LDO for 16MHz XTAL
563 * @return none
564 */
565 extern void POWER_SetXtal16mhzLdo(void);
566
567 /**
568 * @brief Set up 16-MHz XTAL Trimmings
569 * @param amp Amplitude
570 * @param gm Transconductance
571 * @return none
572 */
573 extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);
574
575 /**
576 * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes.
577 * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t
578 type.
579 * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type.
580 * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register
581 PMC->WAKEIOCAUSE[3:0].
582
583 * @return Nothing
584 *
585 * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!!
586 * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!!
587 * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!!
588 * - 1. p_wakeupio_cause is NOT ACCURATE
589 * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when
590 * several wake-up sources are enabled during DEEP-POWER-DOWN
591 * (like enabling wake-up on RTC and Falling edge wake-up pins)
592 *
593 */
594 void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause,
595 power_device_boot_mode_t *p_boot_mode,
596 uint32_t *p_wakeupio_cause);
597 #ifdef __cplusplus
598 }
599 #endif
600
601 /**
602 * @}
603 */
604
605 #endif /* _FSL_POWER_H_ */
606
